Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/RISCV/RISCVGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Writer Source Fragment                                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
#include <assert.h>
15
16
17
/// printInstruction - This method is automatically generated by tablegen
18
/// from the instruction set description.
19
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
20
89.4k
{
21
89.4k
#ifndef CAPSTONE_DIET
22
89.4k
  static const char AsmStrs[] = {
23
89.4k
  /* 0 */ 'l', 'l', 'a', 9, 0,
24
89.4k
  /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0,
25
89.4k
  /* 17 */ 's', 'r', 'a', 9, 0,
26
89.4k
  /* 22 */ 'l', 'b', 9, 0,
27
89.4k
  /* 26 */ 's', 'b', 9, 0,
28
89.4k
  /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0,
29
89.4k
  /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0,
30
89.4k
  /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0,
31
89.4k
  /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0,
32
89.4k
  /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
33
89.4k
  /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
34
89.4k
  /* 78 */ 's', 'c', '.', 'd', 9, 0,
35
89.4k
  /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0,
36
89.4k
  /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
37
89.4k
  /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
38
89.4k
  /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0,
39
89.4k
  /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0,
40
89.4k
  /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0,
41
89.4k
  /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0,
42
89.4k
  /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0,
43
89.4k
  /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0,
44
89.4k
  /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0,
45
89.4k
  /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0,
46
89.4k
  /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0,
47
89.4k
  /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0,
48
89.4k
  /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0,
49
89.4k
  /* 211 */ 'l', 'r', '.', 'd', 9, 0,
50
89.4k
  /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0,
51
89.4k
  /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0,
52
89.4k
  /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0,
53
89.4k
  /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0,
54
89.4k
  /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0,
55
89.4k
  /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0,
56
89.4k
  /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0,
57
89.4k
  /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0,
58
89.4k
  /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0,
59
89.4k
  /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0,
60
89.4k
  /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0,
61
89.4k
  /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0,
62
89.4k
  /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0,
63
89.4k
  /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0,
64
89.4k
  /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0,
65
89.4k
  /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0,
66
89.4k
  /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0,
67
89.4k
  /* 378 */ 'c', '.', 'l', 'd', 9, 0,
68
89.4k
  /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0,
69
89.4k
  /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0,
70
89.4k
  /* 398 */ 'c', '.', 's', 'd', 9, 0,
71
89.4k
  /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0,
72
89.4k
  /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0,
73
89.4k
  /* 418 */ 'b', 'g', 'e', 9, 0,
74
89.4k
  /* 423 */ 'b', 'n', 'e', 9, 0,
75
89.4k
  /* 428 */ 'm', 'u', 'l', 'h', 9, 0,
76
89.4k
  /* 434 */ 's', 'h', 9, 0,
77
89.4k
  /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0,
78
89.4k
  /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0,
79
89.4k
  /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0,
80
89.4k
  /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0,
81
89.4k
  /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0,
82
89.4k
  /* 479 */ 'w', 'f', 'i', 9, 0,
83
89.4k
  /* 484 */ 'c', '.', 'l', 'i', 9, 0,
84
89.4k
  /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0,
85
89.4k
  /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0,
86
89.4k
  /* 506 */ 'x', 'o', 'r', 'i', 9, 0,
87
89.4k
  /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0,
88
89.4k
  /* 520 */ 's', 'l', 't', 'i', 9, 0,
89
89.4k
  /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0,
90
89.4k
  /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0,
91
89.4k
  /* 541 */ 'c', '.', 'j', 9, 0,
92
89.4k
  /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0,
93
89.4k
  /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0,
94
89.4k
  /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0,
95
89.4k
  /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0,
96
89.4k
  /* 583 */ 't', 'a', 'i', 'l', 9, 0,
97
89.4k
  /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0,
98
89.4k
  /* 596 */ 's', 'l', 'l', 9, 0,
99
89.4k
  /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0,
100
89.4k
  /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
101
89.4k
  /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
102
89.4k
  /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0,
103
89.4k
  /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0,
104
89.4k
  /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
105
89.4k
  /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
106
89.4k
  /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
107
89.4k
  /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
108
89.4k
  /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
109
89.4k
  /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0,
110
89.4k
  /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0,
111
89.4k
  /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
112
89.4k
  /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
113
89.4k
  /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0,
114
89.4k
  /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0,
115
89.4k
  /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
116
89.4k
  /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
117
89.4k
  /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
118
89.4k
  /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
119
89.4k
  /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
120
89.4k
  /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0,
121
89.4k
  /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
122
89.4k
  /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
123
89.4k
  /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
124
89.4k
  /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
125
89.4k
  /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
126
89.4k
  /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
127
89.4k
  /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
128
89.4k
  /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
129
89.4k
  /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
130
89.4k
  /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
131
89.4k
  /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
132
89.4k
  /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
133
89.4k
  /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
134
89.4k
  /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
135
89.4k
  /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
136
89.4k
  /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
137
89.4k
  /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
138
89.4k
  /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
139
89.4k
  /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
140
89.4k
  /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
141
89.4k
  /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
142
89.4k
  /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
143
89.4k
  /* 1193 */ 's', 'r', 'l', 9, 0,
144
89.4k
  /* 1198 */ 'm', 'u', 'l', 9, 0,
145
89.4k
  /* 1203 */ 'r', 'e', 'm', 9, 0,
146
89.4k
  /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0,
147
89.4k
  /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0,
148
89.4k
  /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0,
149
89.4k
  /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0,
150
89.4k
  /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0,
151
89.4k
  /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0,
152
89.4k
  /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0,
153
89.4k
  /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0,
154
89.4k
  /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0,
155
89.4k
  /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0,
156
89.4k
  /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0,
157
89.4k
  /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0,
158
89.4k
  /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0,
159
89.4k
  /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0,
160
89.4k
  /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
161
89.4k
  /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
162
89.4k
  /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0,
163
89.4k
  /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0,
164
89.4k
  /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
165
89.4k
  /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
166
89.4k
  /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
167
89.4k
  /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
168
89.4k
  /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
169
89.4k
  /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0,
170
89.4k
  /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0,
171
89.4k
  /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
172
89.4k
  /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
173
89.4k
  /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0,
174
89.4k
  /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0,
175
89.4k
  /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
176
89.4k
  /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
177
89.4k
  /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
178
89.4k
  /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
179
89.4k
  /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
180
89.4k
  /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0,
181
89.4k
  /* 1601 */ 'b', 'e', 'q', 9, 0,
182
89.4k
  /* 1606 */ 'c', '.', 'j', 'r', 9, 0,
183
89.4k
  /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0,
184
89.4k
  /* 1620 */ 'c', '.', 'o', 'r', 9, 0,
185
89.4k
  /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0,
186
89.4k
  /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0,
187
89.4k
  /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0,
188
89.4k
  /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0,
189
89.4k
  /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0,
190
89.4k
  /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0,
191
89.4k
  /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
192
89.4k
  /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
193
89.4k
  /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0,
194
89.4k
  /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0,
195
89.4k
  /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0,
196
89.4k
  /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0,
197
89.4k
  /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0,
198
89.4k
  /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0,
199
89.4k
  /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0,
200
89.4k
  /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0,
201
89.4k
  /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0,
202
89.4k
  /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0,
203
89.4k
  /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0,
204
89.4k
  /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0,
205
89.4k
  /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0,
206
89.4k
  /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0,
207
89.4k
  /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0,
208
89.4k
  /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0,
209
89.4k
  /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0,
210
89.4k
  /* 1847 */ 'm', 'r', 'e', 't', 9, 0,
211
89.4k
  /* 1853 */ 's', 'r', 'e', 't', 9, 0,
212
89.4k
  /* 1859 */ 'u', 'r', 'e', 't', 9, 0,
213
89.4k
  /* 1865 */ 'b', 'l', 't', 9, 0,
214
89.4k
  /* 1870 */ 's', 'l', 't', 9, 0,
215
89.4k
  /* 1875 */ 'l', 'b', 'u', 9, 0,
216
89.4k
  /* 1880 */ 'b', 'g', 'e', 'u', 9, 0,
217
89.4k
  /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0,
218
89.4k
  /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0,
219
89.4k
  /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0,
220
89.4k
  /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0,
221
89.4k
  /* 1922 */ 'r', 'e', 'm', 'u', 9, 0,
222
89.4k
  /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0,
223
89.4k
  /* 1936 */ 'b', 'l', 't', 'u', 9, 0,
224
89.4k
  /* 1942 */ 's', 'l', 't', 'u', 9, 0,
225
89.4k
  /* 1948 */ 'd', 'i', 'v', 'u', 9, 0,
226
89.4k
  /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0,
227
89.4k
  /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0,
228
89.4k
  /* 1976 */ 'l', 'w', 'u', 9, 0,
229
89.4k
  /* 1981 */ 'd', 'i', 'v', 9, 0,
230
89.4k
  /* 1986 */ 'c', '.', 'm', 'v', 9, 0,
231
89.4k
  /* 1992 */ 's', 'c', '.', 'w', 9, 0,
232
89.4k
  /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0,
233
89.4k
  /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0,
234
89.4k
  /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0,
235
89.4k
  /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0,
236
89.4k
  /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0,
237
89.4k
  /* 2049 */ 'l', 'r', '.', 'w', 9, 0,
238
89.4k
  /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0,
239
89.4k
  /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0,
240
89.4k
  /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0,
241
89.4k
  /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0,
242
89.4k
  /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0,
243
89.4k
  /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0,
244
89.4k
  /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0,
245
89.4k
  /* 2125 */ 's', 'r', 'a', 'w', 9, 0,
246
89.4k
  /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0,
247
89.4k
  /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0,
248
89.4k
  /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0,
249
89.4k
  /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0,
250
89.4k
  /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0,
251
89.4k
  /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0,
252
89.4k
  /* 2177 */ 'c', '.', 'l', 'w', 9, 0,
253
89.4k
  /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0,
254
89.4k
  /* 2190 */ 's', 'l', 'l', 'w', 9, 0,
255
89.4k
  /* 2196 */ 's', 'r', 'l', 'w', 9, 0,
256
89.4k
  /* 2202 */ 'm', 'u', 'l', 'w', 9, 0,
257
89.4k
  /* 2208 */ 'r', 'e', 'm', 'w', 9, 0,
258
89.4k
  /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0,
259
89.4k
  /* 2221 */ 'c', '.', 's', 'w', 9, 0,
260
89.4k
  /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0,
261
89.4k
  /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0,
262
89.4k
  /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0,
263
89.4k
  /* 2248 */ 'd', 'i', 'v', 'w', 9, 0,
264
89.4k
  /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0,
265
89.4k
  /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0,
266
89.4k
  /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0,
267
89.4k
  /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0,
268
89.4k
  /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0,
269
89.4k
  /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
270
89.4k
  /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
271
89.4k
  /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0,
272
89.4k
  /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0,
273
89.4k
  /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0,
274
89.4k
  /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
275
89.4k
  /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
276
89.4k
  /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
277
89.4k
  /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
278
89.4k
  /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
279
89.4k
  /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
280
89.4k
  };
281
89.4k
#endif
282
283
89.4k
  static const uint16_t OpInfo0[] = {
284
89.4k
    0U, // PHI
285
89.4k
    0U, // INLINEASM
286
89.4k
    0U, // INLINEASM_BR
287
89.4k
    0U, // CFI_INSTRUCTION
288
89.4k
    0U, // EH_LABEL
289
89.4k
    0U, // GC_LABEL
290
89.4k
    0U, // ANNOTATION_LABEL
291
89.4k
    0U, // KILL
292
89.4k
    0U, // EXTRACT_SUBREG
293
89.4k
    0U, // INSERT_SUBREG
294
89.4k
    0U, // IMPLICIT_DEF
295
89.4k
    0U, // SUBREG_TO_REG
296
89.4k
    0U, // COPY_TO_REGCLASS
297
89.4k
    2457U,  // DBG_VALUE
298
89.4k
    2467U,  // DBG_LABEL
299
89.4k
    0U, // REG_SEQUENCE
300
89.4k
    0U, // COPY
301
89.4k
    2450U,  // BUNDLE
302
89.4k
    2477U,  // LIFETIME_START
303
89.4k
    2437U,  // LIFETIME_END
304
89.4k
    0U, // STACKMAP
305
89.4k
    2492U,  // FENTRY_CALL
306
89.4k
    0U, // PATCHPOINT
307
89.4k
    0U, // LOAD_STACK_GUARD
308
89.4k
    0U, // STATEPOINT
309
89.4k
    0U, // LOCAL_ESCAPE
310
89.4k
    0U, // FAULTING_OP
311
89.4k
    0U, // PATCHABLE_OP
312
89.4k
    2369U,  // PATCHABLE_FUNCTION_ENTER
313
89.4k
    2289U,  // PATCHABLE_RET
314
89.4k
    2415U,  // PATCHABLE_FUNCTION_EXIT
315
89.4k
    2392U,  // PATCHABLE_TAIL_CALL
316
89.4k
    2344U,  // PATCHABLE_EVENT_CALL
317
89.4k
    2320U,  // PATCHABLE_TYPED_EVENT_CALL
318
89.4k
    0U, // ICALL_BRANCH_FUNNEL
319
89.4k
    0U, // G_ADD
320
89.4k
    0U, // G_SUB
321
89.4k
    0U, // G_MUL
322
89.4k
    0U, // G_SDIV
323
89.4k
    0U, // G_UDIV
324
89.4k
    0U, // G_SREM
325
89.4k
    0U, // G_UREM
326
89.4k
    0U, // G_AND
327
89.4k
    0U, // G_OR
328
89.4k
    0U, // G_XOR
329
89.4k
    0U, // G_IMPLICIT_DEF
330
89.4k
    0U, // G_PHI
331
89.4k
    0U, // G_FRAME_INDEX
332
89.4k
    0U, // G_GLOBAL_VALUE
333
89.4k
    0U, // G_EXTRACT
334
89.4k
    0U, // G_UNMERGE_VALUES
335
89.4k
    0U, // G_INSERT
336
89.4k
    0U, // G_MERGE_VALUES
337
89.4k
    0U, // G_BUILD_VECTOR
338
89.4k
    0U, // G_BUILD_VECTOR_TRUNC
339
89.4k
    0U, // G_CONCAT_VECTORS
340
89.4k
    0U, // G_PTRTOINT
341
89.4k
    0U, // G_INTTOPTR
342
89.4k
    0U, // G_BITCAST
343
89.4k
    0U, // G_INTRINSIC_TRUNC
344
89.4k
    0U, // G_INTRINSIC_ROUND
345
89.4k
    0U, // G_LOAD
346
89.4k
    0U, // G_SEXTLOAD
347
89.4k
    0U, // G_ZEXTLOAD
348
89.4k
    0U, // G_STORE
349
89.4k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
350
89.4k
    0U, // G_ATOMIC_CMPXCHG
351
89.4k
    0U, // G_ATOMICRMW_XCHG
352
89.4k
    0U, // G_ATOMICRMW_ADD
353
89.4k
    0U, // G_ATOMICRMW_SUB
354
89.4k
    0U, // G_ATOMICRMW_AND
355
89.4k
    0U, // G_ATOMICRMW_NAND
356
89.4k
    0U, // G_ATOMICRMW_OR
357
89.4k
    0U, // G_ATOMICRMW_XOR
358
89.4k
    0U, // G_ATOMICRMW_MAX
359
89.4k
    0U, // G_ATOMICRMW_MIN
360
89.4k
    0U, // G_ATOMICRMW_UMAX
361
89.4k
    0U, // G_ATOMICRMW_UMIN
362
89.4k
    0U, // G_BRCOND
363
89.4k
    0U, // G_BRINDIRECT
364
89.4k
    0U, // G_INTRINSIC
365
89.4k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
366
89.4k
    0U, // G_ANYEXT
367
89.4k
    0U, // G_TRUNC
368
89.4k
    0U, // G_CONSTANT
369
89.4k
    0U, // G_FCONSTANT
370
89.4k
    0U, // G_VASTART
371
89.4k
    0U, // G_VAARG
372
89.4k
    0U, // G_SEXT
373
89.4k
    0U, // G_ZEXT
374
89.4k
    0U, // G_SHL
375
89.4k
    0U, // G_LSHR
376
89.4k
    0U, // G_ASHR
377
89.4k
    0U, // G_ICMP
378
89.4k
    0U, // G_FCMP
379
89.4k
    0U, // G_SELECT
380
89.4k
    0U, // G_UADDO
381
89.4k
    0U, // G_UADDE
382
89.4k
    0U, // G_USUBO
383
89.4k
    0U, // G_USUBE
384
89.4k
    0U, // G_SADDO
385
89.4k
    0U, // G_SADDE
386
89.4k
    0U, // G_SSUBO
387
89.4k
    0U, // G_SSUBE
388
89.4k
    0U, // G_UMULO
389
89.4k
    0U, // G_SMULO
390
89.4k
    0U, // G_UMULH
391
89.4k
    0U, // G_SMULH
392
89.4k
    0U, // G_FADD
393
89.4k
    0U, // G_FSUB
394
89.4k
    0U, // G_FMUL
395
89.4k
    0U, // G_FMA
396
89.4k
    0U, // G_FDIV
397
89.4k
    0U, // G_FREM
398
89.4k
    0U, // G_FPOW
399
89.4k
    0U, // G_FEXP
400
89.4k
    0U, // G_FEXP2
401
89.4k
    0U, // G_FLOG
402
89.4k
    0U, // G_FLOG2
403
89.4k
    0U, // G_FLOG10
404
89.4k
    0U, // G_FNEG
405
89.4k
    0U, // G_FPEXT
406
89.4k
    0U, // G_FPTRUNC
407
89.4k
    0U, // G_FPTOSI
408
89.4k
    0U, // G_FPTOUI
409
89.4k
    0U, // G_SITOFP
410
89.4k
    0U, // G_UITOFP
411
89.4k
    0U, // G_FABS
412
89.4k
    0U, // G_FCANONICALIZE
413
89.4k
    0U, // G_GEP
414
89.4k
    0U, // G_PTR_MASK
415
89.4k
    0U, // G_BR
416
89.4k
    0U, // G_INSERT_VECTOR_ELT
417
89.4k
    0U, // G_EXTRACT_VECTOR_ELT
418
89.4k
    0U, // G_SHUFFLE_VECTOR
419
89.4k
    0U, // G_CTTZ
420
89.4k
    0U, // G_CTTZ_ZERO_UNDEF
421
89.4k
    0U, // G_CTLZ
422
89.4k
    0U, // G_CTLZ_ZERO_UNDEF
423
89.4k
    0U, // G_CTPOP
424
89.4k
    0U, // G_BSWAP
425
89.4k
    0U, // G_FCEIL
426
89.4k
    0U, // G_FCOS
427
89.4k
    0U, // G_FSIN
428
89.4k
    0U, // G_FSQRT
429
89.4k
    0U, // G_FFLOOR
430
89.4k
    0U, // G_ADDRSPACE_CAST
431
89.4k
    0U, // G_BLOCK_ADDR
432
89.4k
    4U, // ADJCALLSTACKDOWN
433
89.4k
    4U, // ADJCALLSTACKUP
434
89.4k
    4U, // BuildPairF64Pseudo
435
89.4k
    4U, // PseudoAtomicLoadNand32
436
89.4k
    4U, // PseudoAtomicLoadNand64
437
89.4k
    4U, // PseudoBR
438
89.4k
    4U, // PseudoBRIND
439
89.4k
    4687U,  // PseudoCALL
440
89.4k
    4U, // PseudoCALLIndirect
441
89.4k
    4U, // PseudoCmpXchg32
442
89.4k
    4U, // PseudoCmpXchg64
443
89.4k
    20482U, // PseudoLA
444
89.4k
    20967U, // PseudoLI
445
89.4k
    20481U, // PseudoLLA
446
89.4k
    4U, // PseudoMaskedAtomicLoadAdd32
447
89.4k
    4U, // PseudoMaskedAtomicLoadMax32
448
89.4k
    4U, // PseudoMaskedAtomicLoadMin32
449
89.4k
    4U, // PseudoMaskedAtomicLoadNand32
450
89.4k
    4U, // PseudoMaskedAtomicLoadSub32
451
89.4k
    4U, // PseudoMaskedAtomicLoadUMax32
452
89.4k
    4U, // PseudoMaskedAtomicLoadUMin32
453
89.4k
    4U, // PseudoMaskedAtomicSwap32
454
89.4k
    4U, // PseudoMaskedCmpXchg32
455
89.4k
    4U, // PseudoRET
456
89.4k
    4680U,  // PseudoTAIL
457
89.4k
    4U, // PseudoTAILIndirect
458
89.4k
    4U, // Select_FPR32_Using_CC_GPR
459
89.4k
    4U, // Select_FPR64_Using_CC_GPR
460
89.4k
    4U, // Select_GPR_Using_CC_GPR
461
89.4k
    4U, // SplitF64Pseudo
462
89.4k
    20854U, // ADD
463
89.4k
    20946U, // ADDI
464
89.4k
    22637U, // ADDIW
465
89.4k
    22622U, // ADDW
466
89.4k
    20592U, // AMOADD_D
467
89.4k
    21817U, // AMOADD_D_AQ
468
89.4k
    21367U, // AMOADD_D_AQ_RL
469
89.4k
    21091U, // AMOADD_D_RL
470
89.4k
    22489U, // AMOADD_W
471
89.4k
    21954U, // AMOADD_W_AQ
472
89.4k
    21526U, // AMOADD_W_AQ_RL
473
89.4k
    21228U, // AMOADD_W_RL
474
89.4k
    20602U, // AMOAND_D
475
89.4k
    21830U, // AMOAND_D_AQ
476
89.4k
    21382U, // AMOAND_D_AQ_RL
477
89.4k
    21104U, // AMOAND_D_RL
478
89.4k
    22499U, // AMOAND_W
479
89.4k
    21967U, // AMOAND_W_AQ
480
89.4k
    21541U, // AMOAND_W_AQ_RL
481
89.4k
    21241U, // AMOAND_W_RL
482
89.4k
    20786U, // AMOMAXU_D
483
89.4k
    21918U, // AMOMAXU_D_AQ
484
89.4k
    21484U, // AMOMAXU_D_AQ_RL
485
89.4k
    21192U, // AMOMAXU_D_RL
486
89.4k
    22576U, // AMOMAXU_W
487
89.4k
    22055U, // AMOMAXU_W_AQ
488
89.4k
    21643U, // AMOMAXU_W_AQ_RL
489
89.4k
    21329U, // AMOMAXU_W_RL
490
89.4k
    20832U, // AMOMAX_D
491
89.4k
    21932U, // AMOMAX_D_AQ
492
89.4k
    21500U, // AMOMAX_D_AQ_RL
493
89.4k
    21206U, // AMOMAX_D_RL
494
89.4k
    22596U, // AMOMAX_W
495
89.4k
    22069U, // AMOMAX_W_AQ
496
89.4k
    21659U, // AMOMAX_W_AQ_RL
497
89.4k
    21343U, // AMOMAX_W_RL
498
89.4k
    20764U, // AMOMINU_D
499
89.4k
    21904U, // AMOMINU_D_AQ
500
89.4k
    21468U, // AMOMINU_D_AQ_RL
501
89.4k
    21178U, // AMOMINU_D_RL
502
89.4k
    22565U, // AMOMINU_W
503
89.4k
    22041U, // AMOMINU_W_AQ
504
89.4k
    21627U, // AMOMINU_W_AQ_RL
505
89.4k
    21315U, // AMOMINU_W_RL
506
89.4k
    20654U, // AMOMIN_D
507
89.4k
    21843U, // AMOMIN_D_AQ
508
89.4k
    21397U, // AMOMIN_D_AQ_RL
509
89.4k
    21117U, // AMOMIN_D_RL
510
89.4k
    22509U, // AMOMIN_W
511
89.4k
    21980U, // AMOMIN_W_AQ
512
89.4k
    21556U, // AMOMIN_W_AQ_RL
513
89.4k
    21254U, // AMOMIN_W_RL
514
89.4k
    20698U, // AMOOR_D
515
89.4k
    21879U, // AMOOR_D_AQ
516
89.4k
    21439U, // AMOOR_D_AQ_RL
517
89.4k
    21153U, // AMOOR_D_RL
518
89.4k
    22536U, // AMOOR_W
519
89.4k
    22016U, // AMOOR_W_AQ
520
89.4k
    21598U, // AMOOR_W_AQ_RL
521
89.4k
    21290U, // AMOOR_W_RL
522
89.4k
    20674U, // AMOSWAP_D
523
89.4k
    21856U, // AMOSWAP_D_AQ
524
89.4k
    21412U, // AMOSWAP_D_AQ_RL
525
89.4k
    21130U, // AMOSWAP_D_RL
526
89.4k
    22519U, // AMOSWAP_W
527
89.4k
    21993U, // AMOSWAP_W_AQ
528
89.4k
    21571U, // AMOSWAP_W_AQ_RL
529
89.4k
    21267U, // AMOSWAP_W_RL
530
89.4k
    20707U, // AMOXOR_D
531
89.4k
    21891U, // AMOXOR_D_AQ
532
89.4k
    21453U, // AMOXOR_D_AQ_RL
533
89.4k
    21165U, // AMOXOR_D_RL
534
89.4k
    22545U, // AMOXOR_W
535
89.4k
    22028U, // AMOXOR_W_AQ
536
89.4k
    21612U, // AMOXOR_W_AQ_RL
537
89.4k
    21302U, // AMOXOR_W_RL
538
89.4k
    20874U, // AND
539
89.4k
    20954U, // ANDI
540
89.4k
    20518U, // AUIPC
541
89.4k
    22082U, // BEQ
542
89.4k
    20899U, // BGE
543
89.4k
    22361U, // BGEU
544
89.4k
    22346U, // BLT
545
89.4k
    22417U, // BLTU
546
89.4k
    20904U, // BNE
547
89.4k
    20525U, // CSRRC
548
89.4k
    20936U, // CSRRCI
549
89.4k
    22321U, // CSRRS
550
89.4k
    20993U, // CSRRSI
551
89.4k
    22695U, // CSRRW
552
89.4k
    21014U, // CSRRWI
553
89.4k
    8564U,  // C_ADD
554
89.4k
    8656U,  // C_ADDI
555
89.4k
    9440U,  // C_ADDI16SP
556
89.4k
    21689U, // C_ADDI4SPN
557
89.4k
    10347U, // C_ADDIW
558
89.4k
    10332U, // C_ADDW
559
89.4k
    8584U,  // C_AND
560
89.4k
    8664U,  // C_ANDI
561
89.4k
    22761U, // C_BEQZ
562
89.4k
    22753U, // C_BNEZ
563
89.4k
    547U, // C_EBREAK
564
89.4k
    20865U, // C_FLD
565
89.4k
    21748U, // C_FLDSP
566
89.4k
    22664U, // C_FLW
567
89.4k
    21782U, // C_FLWSP
568
89.4k
    20885U, // C_FSD
569
89.4k
    21765U, // C_FSDSP
570
89.4k
    22708U, // C_FSW
571
89.4k
    21799U, // C_FSWSP
572
89.4k
    4638U,  // C_J
573
89.4k
    4673U,  // C_JAL
574
89.4k
    5709U,  // C_JALR
575
89.4k
    5703U,  // C_JR
576
89.4k
    20859U, // C_LD
577
89.4k
    21740U, // C_LDSP
578
89.4k
    20965U, // C_LI
579
89.4k
    21007U, // C_LUI
580
89.4k
    22658U, // C_LW
581
89.4k
    21774U, // C_LWSP
582
89.4k
    22467U, // C_MV
583
89.4k
    1241U,  // C_NOP
584
89.4k
    9813U,  // C_OR
585
89.4k
    20879U, // C_SD
586
89.4k
    21757U, // C_SDSP
587
89.4k
    8683U,  // C_SLLI
588
89.4k
    8640U,  // C_SRAI
589
89.4k
    8691U,  // C_SRLI
590
89.4k
    8223U,  // C_SUB
591
89.4k
    10324U, // C_SUBW
592
89.4k
    22702U, // C_SW
593
89.4k
    21791U, // C_SWSP
594
89.4k
    1232U,  // C_UNIMP
595
89.4k
    9819U,  // C_XOR
596
89.4k
    22462U, // DIV
597
89.4k
    22429U, // DIVU
598
89.4k
    22722U, // DIVUW
599
89.4k
    22729U, // DIVW
600
89.4k
    549U, // EBREAK
601
89.4k
    590U, // ECALL
602
89.4k
    20565U, // FADD_D
603
89.4k
    22151U, // FADD_S
604
89.4k
    20727U, // FCLASS_D
605
89.4k
    22237U, // FCLASS_S
606
89.4k
    21037U, // FCVT_D_L
607
89.4k
    22381U, // FCVT_D_LU
608
89.4k
    22141U, // FCVT_D_S
609
89.4k
    22479U, // FCVT_D_W
610
89.4k
    22435U, // FCVT_D_WU
611
89.4k
    20753U, // FCVT_LU_D
612
89.4k
    22263U, // FCVT_LU_S
613
89.4k
    20628U, // FCVT_L_D
614
89.4k
    22194U, // FCVT_L_S
615
89.4k
    20717U, // FCVT_S_D
616
89.4k
    21047U, // FCVT_S_L
617
89.4k
    22392U, // FCVT_S_LU
618
89.4k
    22555U, // FCVT_S_W
619
89.4k
    22446U, // FCVT_S_WU
620
89.4k
    20775U, // FCVT_WU_D
621
89.4k
    22274U, // FCVT_WU_S
622
89.4k
    20805U, // FCVT_W_D
623
89.4k
    22293U, // FCVT_W_S
624
89.4k
    20797U, // FDIV_D
625
89.4k
    22285U, // FDIV_S
626
89.4k
    12700U, // FENCE
627
89.4k
    439U, // FENCE_I
628
89.4k
    1221U,  // FENCE_TSO
629
89.4k
    20685U, // FEQ_D
630
89.4k
    22230U, // FEQ_S
631
89.4k
    20867U, // FLD
632
89.4k
    20612U, // FLE_D
633
89.4k
    22178U, // FLE_S
634
89.4k
    20737U, // FLT_D
635
89.4k
    22247U, // FLT_S
636
89.4k
    22666U, // FLW
637
89.4k
    20573U, // FMADD_D
638
89.4k
    22159U, // FMADD_S
639
89.4k
    20824U, // FMAX_D
640
89.4k
    22303U, // FMAX_S
641
89.4k
    20646U, // FMIN_D
642
89.4k
    22212U, // FMIN_S
643
89.4k
    20540U, // FMSUB_D
644
89.4k
    22122U, // FMSUB_S
645
89.4k
    20638U, // FMUL_D
646
89.4k
    22204U, // FMUL_S
647
89.4k
    22735U, // FMV_D_X
648
89.4k
    22744U, // FMV_W_X
649
89.4k
    20815U, // FMV_X_D
650
89.4k
    22587U, // FMV_X_W
651
89.4k
    20582U, // FNMADD_D
652
89.4k
    22168U, // FNMADD_S
653
89.4k
    20549U, // FNMSUB_D
654
89.4k
    22131U, // FNMSUB_S
655
89.4k
    20887U, // FSD
656
89.4k
    20664U, // FSGNJN_D
657
89.4k
    22220U, // FSGNJN_S
658
89.4k
    20842U, // FSGNJX_D
659
89.4k
    22311U, // FSGNJX_S
660
89.4k
    20619U, // FSGNJ_D
661
89.4k
    22185U, // FSGNJ_S
662
89.4k
    20744U, // FSQRT_D
663
89.4k
    22254U, // FSQRT_S
664
89.4k
    20532U, // FSUB_D
665
89.4k
    22114U, // FSUB_S
666
89.4k
    22710U, // FSW
667
89.4k
    21059U, // JAL
668
89.4k
    22095U, // JALR
669
89.4k
    20503U, // LB
670
89.4k
    22356U, // LBU
671
89.4k
    20861U, // LD
672
89.4k
    20911U, // LH
673
89.4k
    22369U, // LHU
674
89.4k
    37076U, // LR_D
675
89.4k
    38254U, // LR_D_AQ
676
89.4k
    37812U, // LR_D_AQ_RL
677
89.4k
    37528U, // LR_D_RL
678
89.4k
    38914U, // LR_W
679
89.4k
    38391U, // LR_W_AQ
680
89.4k
    37971U, // LR_W_AQ_RL
681
89.4k
    37665U, // LR_W_RL
682
89.4k
    21009U, // LUI
683
89.4k
    22660U, // LW
684
89.4k
    22457U, // LWU
685
89.4k
    1848U,  // MRET
686
89.4k
    21679U, // MUL
687
89.4k
    20909U, // MULH
688
89.4k
    22409U, // MULHSU
689
89.4k
    22367U, // MULHU
690
89.4k
    22683U, // MULW
691
89.4k
    22103U, // OR
692
89.4k
    20988U, // ORI
693
89.4k
    21684U, // REM
694
89.4k
    22403U, // REMU
695
89.4k
    22715U, // REMUW
696
89.4k
    22689U, // REMW
697
89.4k
    20507U, // SB
698
89.4k
    20559U, // SC_D
699
89.4k
    21808U, // SC_D_AQ
700
89.4k
    21356U, // SC_D_AQ_RL
701
89.4k
    21082U, // SC_D_RL
702
89.4k
    22473U, // SC_W
703
89.4k
    21945U, // SC_W_AQ
704
89.4k
    21515U, // SC_W_AQ_RL
705
89.4k
    21219U, // SC_W_RL
706
89.4k
    20881U, // SD
707
89.4k
    20486U, // SFENCE_VMA
708
89.4k
    20915U, // SH
709
89.4k
    21077U, // SLL
710
89.4k
    20973U, // SLLI
711
89.4k
    22644U, // SLLIW
712
89.4k
    22671U, // SLLW
713
89.4k
    22351U, // SLT
714
89.4k
    21001U, // SLTI
715
89.4k
    22374U, // SLTIU
716
89.4k
    22423U, // SLTU
717
89.4k
    20498U, // SRA
718
89.4k
    20930U, // SRAI
719
89.4k
    22628U, // SRAIW
720
89.4k
    22606U, // SRAW
721
89.4k
    1854U,  // SRET
722
89.4k
    21674U, // SRL
723
89.4k
    20981U, // SRLI
724
89.4k
    22651U, // SRLIW
725
89.4k
    22677U, // SRLW
726
89.4k
    20513U, // SUB
727
89.4k
    22614U, // SUBW
728
89.4k
    22704U, // SW
729
89.4k
    1234U,  // UNIMP
730
89.4k
    1860U,  // URET
731
89.4k
    480U, // WFI
732
89.4k
    22109U, // XOR
733
89.4k
    20987U, // XORI
734
89.4k
  };
735
736
89.4k
  static const uint8_t OpInfo1[] = {
737
89.4k
    0U, // PHI
738
89.4k
    0U, // INLINEASM
739
89.4k
    0U, // INLINEASM_BR
740
89.4k
    0U, // CFI_INSTRUCTION
741
89.4k
    0U, // EH_LABEL
742
89.4k
    0U, // GC_LABEL
743
89.4k
    0U, // ANNOTATION_LABEL
744
89.4k
    0U, // KILL
745
89.4k
    0U, // EXTRACT_SUBREG
746
89.4k
    0U, // INSERT_SUBREG
747
89.4k
    0U, // IMPLICIT_DEF
748
89.4k
    0U, // SUBREG_TO_REG
749
89.4k
    0U, // COPY_TO_REGCLASS
750
89.4k
    0U, // DBG_VALUE
751
89.4k
    0U, // DBG_LABEL
752
89.4k
    0U, // REG_SEQUENCE
753
89.4k
    0U, // COPY
754
89.4k
    0U, // BUNDLE
755
89.4k
    0U, // LIFETIME_START
756
89.4k
    0U, // LIFETIME_END
757
89.4k
    0U, // STACKMAP
758
89.4k
    0U, // FENTRY_CALL
759
89.4k
    0U, // PATCHPOINT
760
89.4k
    0U, // LOAD_STACK_GUARD
761
89.4k
    0U, // STATEPOINT
762
89.4k
    0U, // LOCAL_ESCAPE
763
89.4k
    0U, // FAULTING_OP
764
89.4k
    0U, // PATCHABLE_OP
765
89.4k
    0U, // PATCHABLE_FUNCTION_ENTER
766
89.4k
    0U, // PATCHABLE_RET
767
89.4k
    0U, // PATCHABLE_FUNCTION_EXIT
768
89.4k
    0U, // PATCHABLE_TAIL_CALL
769
89.4k
    0U, // PATCHABLE_EVENT_CALL
770
89.4k
    0U, // PATCHABLE_TYPED_EVENT_CALL
771
89.4k
    0U, // ICALL_BRANCH_FUNNEL
772
89.4k
    0U, // G_ADD
773
89.4k
    0U, // G_SUB
774
89.4k
    0U, // G_MUL
775
89.4k
    0U, // G_SDIV
776
89.4k
    0U, // G_UDIV
777
89.4k
    0U, // G_SREM
778
89.4k
    0U, // G_UREM
779
89.4k
    0U, // G_AND
780
89.4k
    0U, // G_OR
781
89.4k
    0U, // G_XOR
782
89.4k
    0U, // G_IMPLICIT_DEF
783
89.4k
    0U, // G_PHI
784
89.4k
    0U, // G_FRAME_INDEX
785
89.4k
    0U, // G_GLOBAL_VALUE
786
89.4k
    0U, // G_EXTRACT
787
89.4k
    0U, // G_UNMERGE_VALUES
788
89.4k
    0U, // G_INSERT
789
89.4k
    0U, // G_MERGE_VALUES
790
89.4k
    0U, // G_BUILD_VECTOR
791
89.4k
    0U, // G_BUILD_VECTOR_TRUNC
792
89.4k
    0U, // G_CONCAT_VECTORS
793
89.4k
    0U, // G_PTRTOINT
794
89.4k
    0U, // G_INTTOPTR
795
89.4k
    0U, // G_BITCAST
796
89.4k
    0U, // G_INTRINSIC_TRUNC
797
89.4k
    0U, // G_INTRINSIC_ROUND
798
89.4k
    0U, // G_LOAD
799
89.4k
    0U, // G_SEXTLOAD
800
89.4k
    0U, // G_ZEXTLOAD
801
89.4k
    0U, // G_STORE
802
89.4k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
803
89.4k
    0U, // G_ATOMIC_CMPXCHG
804
89.4k
    0U, // G_ATOMICRMW_XCHG
805
89.4k
    0U, // G_ATOMICRMW_ADD
806
89.4k
    0U, // G_ATOMICRMW_SUB
807
89.4k
    0U, // G_ATOMICRMW_AND
808
89.4k
    0U, // G_ATOMICRMW_NAND
809
89.4k
    0U, // G_ATOMICRMW_OR
810
89.4k
    0U, // G_ATOMICRMW_XOR
811
89.4k
    0U, // G_ATOMICRMW_MAX
812
89.4k
    0U, // G_ATOMICRMW_MIN
813
89.4k
    0U, // G_ATOMICRMW_UMAX
814
89.4k
    0U, // G_ATOMICRMW_UMIN
815
89.4k
    0U, // G_BRCOND
816
89.4k
    0U, // G_BRINDIRECT
817
89.4k
    0U, // G_INTRINSIC
818
89.4k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
819
89.4k
    0U, // G_ANYEXT
820
89.4k
    0U, // G_TRUNC
821
89.4k
    0U, // G_CONSTANT
822
89.4k
    0U, // G_FCONSTANT
823
89.4k
    0U, // G_VASTART
824
89.4k
    0U, // G_VAARG
825
89.4k
    0U, // G_SEXT
826
89.4k
    0U, // G_ZEXT
827
89.4k
    0U, // G_SHL
828
89.4k
    0U, // G_LSHR
829
89.4k
    0U, // G_ASHR
830
89.4k
    0U, // G_ICMP
831
89.4k
    0U, // G_FCMP
832
89.4k
    0U, // G_SELECT
833
89.4k
    0U, // G_UADDO
834
89.4k
    0U, // G_UADDE
835
89.4k
    0U, // G_USUBO
836
89.4k
    0U, // G_USUBE
837
89.4k
    0U, // G_SADDO
838
89.4k
    0U, // G_SADDE
839
89.4k
    0U, // G_SSUBO
840
89.4k
    0U, // G_SSUBE
841
89.4k
    0U, // G_UMULO
842
89.4k
    0U, // G_SMULO
843
89.4k
    0U, // G_UMULH
844
89.4k
    0U, // G_SMULH
845
89.4k
    0U, // G_FADD
846
89.4k
    0U, // G_FSUB
847
89.4k
    0U, // G_FMUL
848
89.4k
    0U, // G_FMA
849
89.4k
    0U, // G_FDIV
850
89.4k
    0U, // G_FREM
851
89.4k
    0U, // G_FPOW
852
89.4k
    0U, // G_FEXP
853
89.4k
    0U, // G_FEXP2
854
89.4k
    0U, // G_FLOG
855
89.4k
    0U, // G_FLOG2
856
89.4k
    0U, // G_FLOG10
857
89.4k
    0U, // G_FNEG
858
89.4k
    0U, // G_FPEXT
859
89.4k
    0U, // G_FPTRUNC
860
89.4k
    0U, // G_FPTOSI
861
89.4k
    0U, // G_FPTOUI
862
89.4k
    0U, // G_SITOFP
863
89.4k
    0U, // G_UITOFP
864
89.4k
    0U, // G_FABS
865
89.4k
    0U, // G_FCANONICALIZE
866
89.4k
    0U, // G_GEP
867
89.4k
    0U, // G_PTR_MASK
868
89.4k
    0U, // G_BR
869
89.4k
    0U, // G_INSERT_VECTOR_ELT
870
89.4k
    0U, // G_EXTRACT_VECTOR_ELT
871
89.4k
    0U, // G_SHUFFLE_VECTOR
872
89.4k
    0U, // G_CTTZ
873
89.4k
    0U, // G_CTTZ_ZERO_UNDEF
874
89.4k
    0U, // G_CTLZ
875
89.4k
    0U, // G_CTLZ_ZERO_UNDEF
876
89.4k
    0U, // G_CTPOP
877
89.4k
    0U, // G_BSWAP
878
89.4k
    0U, // G_FCEIL
879
89.4k
    0U, // G_FCOS
880
89.4k
    0U, // G_FSIN
881
89.4k
    0U, // G_FSQRT
882
89.4k
    0U, // G_FFLOOR
883
89.4k
    0U, // G_ADDRSPACE_CAST
884
89.4k
    0U, // G_BLOCK_ADDR
885
89.4k
    0U, // ADJCALLSTACKDOWN
886
89.4k
    0U, // ADJCALLSTACKUP
887
89.4k
    0U, // BuildPairF64Pseudo
888
89.4k
    0U, // PseudoAtomicLoadNand32
889
89.4k
    0U, // PseudoAtomicLoadNand64
890
89.4k
    0U, // PseudoBR
891
89.4k
    0U, // PseudoBRIND
892
89.4k
    0U, // PseudoCALL
893
89.4k
    0U, // PseudoCALLIndirect
894
89.4k
    0U, // PseudoCmpXchg32
895
89.4k
    0U, // PseudoCmpXchg64
896
89.4k
    0U, // PseudoLA
897
89.4k
    0U, // PseudoLI
898
89.4k
    0U, // PseudoLLA
899
89.4k
    0U, // PseudoMaskedAtomicLoadAdd32
900
89.4k
    0U, // PseudoMaskedAtomicLoadMax32
901
89.4k
    0U, // PseudoMaskedAtomicLoadMin32
902
89.4k
    0U, // PseudoMaskedAtomicLoadNand32
903
89.4k
    0U, // PseudoMaskedAtomicLoadSub32
904
89.4k
    0U, // PseudoMaskedAtomicLoadUMax32
905
89.4k
    0U, // PseudoMaskedAtomicLoadUMin32
906
89.4k
    0U, // PseudoMaskedAtomicSwap32
907
89.4k
    0U, // PseudoMaskedCmpXchg32
908
89.4k
    0U, // PseudoRET
909
89.4k
    0U, // PseudoTAIL
910
89.4k
    0U, // PseudoTAILIndirect
911
89.4k
    0U, // Select_FPR32_Using_CC_GPR
912
89.4k
    0U, // Select_FPR64_Using_CC_GPR
913
89.4k
    0U, // Select_GPR_Using_CC_GPR
914
89.4k
    0U, // SplitF64Pseudo
915
89.4k
    4U, // ADD
916
89.4k
    4U, // ADDI
917
89.4k
    4U, // ADDIW
918
89.4k
    4U, // ADDW
919
89.4k
    9U, // AMOADD_D
920
89.4k
    9U, // AMOADD_D_AQ
921
89.4k
    9U, // AMOADD_D_AQ_RL
922
89.4k
    9U, // AMOADD_D_RL
923
89.4k
    9U, // AMOADD_W
924
89.4k
    9U, // AMOADD_W_AQ
925
89.4k
    9U, // AMOADD_W_AQ_RL
926
89.4k
    9U, // AMOADD_W_RL
927
89.4k
    9U, // AMOAND_D
928
89.4k
    9U, // AMOAND_D_AQ
929
89.4k
    9U, // AMOAND_D_AQ_RL
930
89.4k
    9U, // AMOAND_D_RL
931
89.4k
    9U, // AMOAND_W
932
89.4k
    9U, // AMOAND_W_AQ
933
89.4k
    9U, // AMOAND_W_AQ_RL
934
89.4k
    9U, // AMOAND_W_RL
935
89.4k
    9U, // AMOMAXU_D
936
89.4k
    9U, // AMOMAXU_D_AQ
937
89.4k
    9U, // AMOMAXU_D_AQ_RL
938
89.4k
    9U, // AMOMAXU_D_RL
939
89.4k
    9U, // AMOMAXU_W
940
89.4k
    9U, // AMOMAXU_W_AQ
941
89.4k
    9U, // AMOMAXU_W_AQ_RL
942
89.4k
    9U, // AMOMAXU_W_RL
943
89.4k
    9U, // AMOMAX_D
944
89.4k
    9U, // AMOMAX_D_AQ
945
89.4k
    9U, // AMOMAX_D_AQ_RL
946
89.4k
    9U, // AMOMAX_D_RL
947
89.4k
    9U, // AMOMAX_W
948
89.4k
    9U, // AMOMAX_W_AQ
949
89.4k
    9U, // AMOMAX_W_AQ_RL
950
89.4k
    9U, // AMOMAX_W_RL
951
89.4k
    9U, // AMOMINU_D
952
89.4k
    9U, // AMOMINU_D_AQ
953
89.4k
    9U, // AMOMINU_D_AQ_RL
954
89.4k
    9U, // AMOMINU_D_RL
955
89.4k
    9U, // AMOMINU_W
956
89.4k
    9U, // AMOMINU_W_AQ
957
89.4k
    9U, // AMOMINU_W_AQ_RL
958
89.4k
    9U, // AMOMINU_W_RL
959
89.4k
    9U, // AMOMIN_D
960
89.4k
    9U, // AMOMIN_D_AQ
961
89.4k
    9U, // AMOMIN_D_AQ_RL
962
89.4k
    9U, // AMOMIN_D_RL
963
89.4k
    9U, // AMOMIN_W
964
89.4k
    9U, // AMOMIN_W_AQ
965
89.4k
    9U, // AMOMIN_W_AQ_RL
966
89.4k
    9U, // AMOMIN_W_RL
967
89.4k
    9U, // AMOOR_D
968
89.4k
    9U, // AMOOR_D_AQ
969
89.4k
    9U, // AMOOR_D_AQ_RL
970
89.4k
    9U, // AMOOR_D_RL
971
89.4k
    9U, // AMOOR_W
972
89.4k
    9U, // AMOOR_W_AQ
973
89.4k
    9U, // AMOOR_W_AQ_RL
974
89.4k
    9U, // AMOOR_W_RL
975
89.4k
    9U, // AMOSWAP_D
976
89.4k
    9U, // AMOSWAP_D_AQ
977
89.4k
    9U, // AMOSWAP_D_AQ_RL
978
89.4k
    9U, // AMOSWAP_D_RL
979
89.4k
    9U, // AMOSWAP_W
980
89.4k
    9U, // AMOSWAP_W_AQ
981
89.4k
    9U, // AMOSWAP_W_AQ_RL
982
89.4k
    9U, // AMOSWAP_W_RL
983
89.4k
    9U, // AMOXOR_D
984
89.4k
    9U, // AMOXOR_D_AQ
985
89.4k
    9U, // AMOXOR_D_AQ_RL
986
89.4k
    9U, // AMOXOR_D_RL
987
89.4k
    9U, // AMOXOR_W
988
89.4k
    9U, // AMOXOR_W_AQ
989
89.4k
    9U, // AMOXOR_W_AQ_RL
990
89.4k
    9U, // AMOXOR_W_RL
991
89.4k
    4U, // AND
992
89.4k
    4U, // ANDI
993
89.4k
    0U, // AUIPC
994
89.4k
    4U, // BEQ
995
89.4k
    4U, // BGE
996
89.4k
    4U, // BGEU
997
89.4k
    4U, // BLT
998
89.4k
    4U, // BLTU
999
89.4k
    4U, // BNE
1000
89.4k
    2U, // CSRRC
1001
89.4k
    2U, // CSRRCI
1002
89.4k
    2U, // CSRRS
1003
89.4k
    2U, // CSRRSI
1004
89.4k
    2U, // CSRRW
1005
89.4k
    2U, // CSRRWI
1006
89.4k
    0U, // C_ADD
1007
89.4k
    0U, // C_ADDI
1008
89.4k
    0U, // C_ADDI16SP
1009
89.4k
    4U, // C_ADDI4SPN
1010
89.4k
    0U, // C_ADDIW
1011
89.4k
    0U, // C_ADDW
1012
89.4k
    0U, // C_AND
1013
89.4k
    0U, // C_ANDI
1014
89.4k
    0U, // C_BEQZ
1015
89.4k
    0U, // C_BNEZ
1016
89.4k
    0U, // C_EBREAK
1017
89.4k
    13U,  // C_FLD
1018
89.4k
    13U,  // C_FLDSP
1019
89.4k
    13U,  // C_FLW
1020
89.4k
    13U,  // C_FLWSP
1021
89.4k
    13U,  // C_FSD
1022
89.4k
    13U,  // C_FSDSP
1023
89.4k
    13U,  // C_FSW
1024
89.4k
    13U,  // C_FSWSP
1025
89.4k
    0U, // C_J
1026
89.4k
    0U, // C_JAL
1027
89.4k
    0U, // C_JALR
1028
89.4k
    0U, // C_JR
1029
89.4k
    13U,  // C_LD
1030
89.4k
    13U,  // C_LDSP
1031
89.4k
    0U, // C_LI
1032
89.4k
    0U, // C_LUI
1033
89.4k
    13U,  // C_LW
1034
89.4k
    13U,  // C_LWSP
1035
89.4k
    0U, // C_MV
1036
89.4k
    0U, // C_NOP
1037
89.4k
    0U, // C_OR
1038
89.4k
    13U,  // C_SD
1039
89.4k
    13U,  // C_SDSP
1040
89.4k
    0U, // C_SLLI
1041
89.4k
    0U, // C_SRAI
1042
89.4k
    0U, // C_SRLI
1043
89.4k
    0U, // C_SUB
1044
89.4k
    0U, // C_SUBW
1045
89.4k
    13U,  // C_SW
1046
89.4k
    13U,  // C_SWSP
1047
89.4k
    0U, // C_UNIMP
1048
89.4k
    0U, // C_XOR
1049
89.4k
    4U, // DIV
1050
89.4k
    4U, // DIVU
1051
89.4k
    4U, // DIVUW
1052
89.4k
    4U, // DIVW
1053
89.4k
    0U, // EBREAK
1054
89.4k
    0U, // ECALL
1055
89.4k
    36U,  // FADD_D
1056
89.4k
    36U,  // FADD_S
1057
89.4k
    0U, // FCLASS_D
1058
89.4k
    0U, // FCLASS_S
1059
89.4k
    20U,  // FCVT_D_L
1060
89.4k
    20U,  // FCVT_D_LU
1061
89.4k
    0U, // FCVT_D_S
1062
89.4k
    0U, // FCVT_D_W
1063
89.4k
    0U, // FCVT_D_WU
1064
89.4k
    20U,  // FCVT_LU_D
1065
89.4k
    20U,  // FCVT_LU_S
1066
89.4k
    20U,  // FCVT_L_D
1067
89.4k
    20U,  // FCVT_L_S
1068
89.4k
    20U,  // FCVT_S_D
1069
89.4k
    20U,  // FCVT_S_L
1070
89.4k
    20U,  // FCVT_S_LU
1071
89.4k
    20U,  // FCVT_S_W
1072
89.4k
    20U,  // FCVT_S_WU
1073
89.4k
    20U,  // FCVT_WU_D
1074
89.4k
    20U,  // FCVT_WU_S
1075
89.4k
    20U,  // FCVT_W_D
1076
89.4k
    20U,  // FCVT_W_S
1077
89.4k
    36U,  // FDIV_D
1078
89.4k
    36U,  // FDIV_S
1079
89.4k
    0U, // FENCE
1080
89.4k
    0U, // FENCE_I
1081
89.4k
    0U, // FENCE_TSO
1082
89.4k
    4U, // FEQ_D
1083
89.4k
    4U, // FEQ_S
1084
89.4k
    13U,  // FLD
1085
89.4k
    4U, // FLE_D
1086
89.4k
    4U, // FLE_S
1087
89.4k
    4U, // FLT_D
1088
89.4k
    4U, // FLT_S
1089
89.4k
    13U,  // FLW
1090
89.4k
    100U, // FMADD_D
1091
89.4k
    100U, // FMADD_S
1092
89.4k
    4U, // FMAX_D
1093
89.4k
    4U, // FMAX_S
1094
89.4k
    4U, // FMIN_D
1095
89.4k
    4U, // FMIN_S
1096
89.4k
    100U, // FMSUB_D
1097
89.4k
    100U, // FMSUB_S
1098
89.4k
    36U,  // FMUL_D
1099
89.4k
    36U,  // FMUL_S
1100
89.4k
    0U, // FMV_D_X
1101
89.4k
    0U, // FMV_W_X
1102
89.4k
    0U, // FMV_X_D
1103
89.4k
    0U, // FMV_X_W
1104
89.4k
    100U, // FNMADD_D
1105
89.4k
    100U, // FNMADD_S
1106
89.4k
    100U, // FNMSUB_D
1107
89.4k
    100U, // FNMSUB_S
1108
89.4k
    13U,  // FSD
1109
89.4k
    4U, // FSGNJN_D
1110
89.4k
    4U, // FSGNJN_S
1111
89.4k
    4U, // FSGNJX_D
1112
89.4k
    4U, // FSGNJX_S
1113
89.4k
    4U, // FSGNJ_D
1114
89.4k
    4U, // FSGNJ_S
1115
89.4k
    20U,  // FSQRT_D
1116
89.4k
    20U,  // FSQRT_S
1117
89.4k
    36U,  // FSUB_D
1118
89.4k
    36U,  // FSUB_S
1119
89.4k
    13U,  // FSW
1120
89.4k
    0U, // JAL
1121
89.4k
    4U, // JALR
1122
89.4k
    13U,  // LB
1123
89.4k
    13U,  // LBU
1124
89.4k
    13U,  // LD
1125
89.4k
    13U,  // LH
1126
89.4k
    13U,  // LHU
1127
89.4k
    0U, // LR_D
1128
89.4k
    0U, // LR_D_AQ
1129
89.4k
    0U, // LR_D_AQ_RL
1130
89.4k
    0U, // LR_D_RL
1131
89.4k
    0U, // LR_W
1132
89.4k
    0U, // LR_W_AQ
1133
89.4k
    0U, // LR_W_AQ_RL
1134
89.4k
    0U, // LR_W_RL
1135
89.4k
    0U, // LUI
1136
89.4k
    13U,  // LW
1137
89.4k
    13U,  // LWU
1138
89.4k
    0U, // MRET
1139
89.4k
    4U, // MUL
1140
89.4k
    4U, // MULH
1141
89.4k
    4U, // MULHSU
1142
89.4k
    4U, // MULHU
1143
89.4k
    4U, // MULW
1144
89.4k
    4U, // OR
1145
89.4k
    4U, // ORI
1146
89.4k
    4U, // REM
1147
89.4k
    4U, // REMU
1148
89.4k
    4U, // REMUW
1149
89.4k
    4U, // REMW
1150
89.4k
    13U,  // SB
1151
89.4k
    9U, // SC_D
1152
89.4k
    9U, // SC_D_AQ
1153
89.4k
    9U, // SC_D_AQ_RL
1154
89.4k
    9U, // SC_D_RL
1155
89.4k
    9U, // SC_W
1156
89.4k
    9U, // SC_W_AQ
1157
89.4k
    9U, // SC_W_AQ_RL
1158
89.4k
    9U, // SC_W_RL
1159
89.4k
    13U,  // SD
1160
89.4k
    0U, // SFENCE_VMA
1161
89.4k
    13U,  // SH
1162
89.4k
    4U, // SLL
1163
89.4k
    4U, // SLLI
1164
89.4k
    4U, // SLLIW
1165
89.4k
    4U, // SLLW
1166
89.4k
    4U, // SLT
1167
89.4k
    4U, // SLTI
1168
89.4k
    4U, // SLTIU
1169
89.4k
    4U, // SLTU
1170
89.4k
    4U, // SRA
1171
89.4k
    4U, // SRAI
1172
89.4k
    4U, // SRAIW
1173
89.4k
    4U, // SRAW
1174
89.4k
    0U, // SRET
1175
89.4k
    4U, // SRL
1176
89.4k
    4U, // SRLI
1177
89.4k
    4U, // SRLIW
1178
89.4k
    4U, // SRLW
1179
89.4k
    4U, // SUB
1180
89.4k
    4U, // SUBW
1181
89.4k
    13U,  // SW
1182
89.4k
    0U, // UNIMP
1183
89.4k
    0U, // URET
1184
89.4k
    0U, // WFI
1185
89.4k
    4U, // XOR
1186
89.4k
    4U, // XORI
1187
89.4k
  };
1188
1189
  // Emit the opcode for the instruction.
1190
89.4k
  uint32_t Bits = 0;
1191
89.4k
  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
1192
89.4k
  Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16;
1193
89.4k
  CS_ASSERT(Bits != 0 && "Cannot print this instruction.");
1194
89.4k
#ifndef CAPSTONE_DIET
1195
89.4k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
1196
89.4k
#endif
1197
1198
1199
  // Fragment 0 encoded into 2 bits for 4 unique commands.
1200
89.4k
  switch ((Bits >> 12) & 3) {
1201
0
  default: CS_ASSERT(0 && "Invalid command number.");
1202
69
  case 0:
1203
    // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
1204
69
    return;
1205
0
    break;
1206
87.6k
  case 1:
1207
    // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI...
1208
87.6k
    printOperand(MI, 0, O);
1209
87.6k
    break;
1210
0
  case 2:
1211
    // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL...
1212
0
    printOperand(MI, 1, O);
1213
0
    SStream_concat0(O, ", ");
1214
0
    printOperand(MI, 2, O);
1215
0
    return;
1216
0
    break;
1217
1.80k
  case 3:
1218
    // FENCE
1219
1.80k
    printFenceArg(MI, 0, O);
1220
1.80k
    SStream_concat0(O, ", ");
1221
1.80k
    printFenceArg(MI, 1, O);
1222
1.80k
    return;
1223
0
    break;
1224
89.4k
  }
1225
1226
1227
  // Fragment 1 encoded into 2 bits for 3 unique commands.
1228
87.6k
  switch ((Bits >> 14) & 3) {
1229
0
  default: CS_ASSERT(0 && "Invalid command number.");
1230
0
  case 0:
1231
    // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR
1232
0
    return;
1233
0
    break;
1234
87.5k
  case 1:
1235
    // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD...
1236
87.5k
    SStream_concat0(O, ", ");
1237
87.5k
    break;
1238
21
  case 2:
1239
    // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL
1240
21
    SStream_concat0(O, ", (");
1241
21
    printOperand(MI, 1, O);
1242
21
    SStream_concat0(O, ")");
1243
21
    return;
1244
0
    break;
1245
87.6k
  }
1246
1247
1248
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1249
87.5k
  switch ((Bits >> 16) & 3) {
1250
0
  default: CS_ASSERT(0 && "Invalid command number.");
1251
23.3k
  case 0:
1252
    // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP...
1253
23.3k
    printOperand(MI, 1, O);
1254
23.3k
    break;
1255
2.03k
  case 1:
1256
    // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W...
1257
2.03k
    printOperand(MI, 2, O);
1258
2.03k
    break;
1259
62.1k
  case 2:
1260
    // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI
1261
62.1k
    printCSRSystemRegister(MI, 1, O);
1262
62.1k
    SStream_concat0(O, ", ");
1263
62.1k
    printOperand(MI, 2, O);
1264
62.1k
    return;
1265
0
    break;
1266
87.5k
  }
1267
1268
1269
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1270
25.3k
  switch ((Bits >> 18) & 3) {
1271
0
  default: CS_ASSERT(0 && "Invalid command number.");
1272
3.79k
  case 0:
1273
    // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M...
1274
3.79k
    return;
1275
0
    break;
1276
19.5k
  case 1:
1277
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1278
19.5k
    SStream_concat0(O, ", ");
1279
19.5k
    break;
1280
142
  case 2:
1281
    // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W...
1282
142
    SStream_concat0(O, ", (");
1283
142
    printOperand(MI, 1, O);
1284
142
    SStream_concat0(O, ")");
1285
142
    return;
1286
0
    break;
1287
1.89k
  case 3:
1288
    // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ...
1289
1.89k
    SStream_concat0(O, "(");
1290
1.89k
    printOperand(MI, 1, O);
1291
1.89k
    SStream_concat0(O, ")");
1292
1.89k
    return;
1293
0
    break;
1294
25.3k
  }
1295
1296
1297
  // Fragment 4 encoded into 1 bits for 2 unique commands.
1298
19.5k
  if ((Bits >> 20) & 1) {
1299
    // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_...
1300
5.42k
    printFRMArg(MI, 2, O);
1301
5.42k
    return;
1302
14.1k
  } else {
1303
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1304
14.1k
    printOperand(MI, 2, O);
1305
14.1k
  }
1306
1307
1308
  // Fragment 5 encoded into 1 bits for 2 unique commands.
1309
14.1k
  if ((Bits >> 21) & 1) {
1310
    // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM...
1311
6.52k
    SStream_concat0(O, ", ");
1312
7.61k
  } else {
1313
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1314
7.61k
    return;
1315
7.61k
  }
1316
1317
1318
  // Fragment 6 encoded into 1 bits for 2 unique commands.
1319
6.52k
  if ((Bits >> 22) & 1) {
1320
    // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS...
1321
3.45k
    printOperand(MI, 3, O);
1322
3.45k
    SStream_concat0(O, ", ");
1323
3.45k
    printFRMArg(MI, 4, O);
1324
3.45k
    return;
1325
3.45k
  } else {
1326
    // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S
1327
3.07k
    printFRMArg(MI, 3, O);
1328
3.07k
    return;
1329
3.07k
  }
1330
1331
6.52k
}
1332
1333
1334
/// getRegisterName - This method is automatically generated by tblgen
1335
/// from the register set description.  This returns the assembler name
1336
/// for the specified register.
1337
static const char *
1338
getRegisterName(unsigned RegNo, unsigned AltIdx)
1339
202k
{
1340
202k
  CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!");
1341
1342
202k
#ifndef CAPSTONE_DIET
1343
202k
  static const char AsmStrsABIRegAltName[] = {
1344
202k
  /* 0 */ 'f', 's', '1', '0', 0,
1345
202k
  /* 5 */ 'f', 't', '1', '0', 0,
1346
202k
  /* 10 */ 'f', 'a', '0', 0,
1347
202k
  /* 14 */ 'f', 's', '0', 0,
1348
202k
  /* 18 */ 'f', 't', '0', 0,
1349
202k
  /* 22 */ 'f', 's', '1', '1', 0,
1350
202k
  /* 27 */ 'f', 't', '1', '1', 0,
1351
202k
  /* 32 */ 'f', 'a', '1', 0,
1352
202k
  /* 36 */ 'f', 's', '1', 0,
1353
202k
  /* 40 */ 'f', 't', '1', 0,
1354
202k
  /* 44 */ 'f', 'a', '2', 0,
1355
202k
  /* 48 */ 'f', 's', '2', 0,
1356
202k
  /* 52 */ 'f', 't', '2', 0,
1357
202k
  /* 56 */ 'f', 'a', '3', 0,
1358
202k
  /* 60 */ 'f', 's', '3', 0,
1359
202k
  /* 64 */ 'f', 't', '3', 0,
1360
202k
  /* 68 */ 'f', 'a', '4', 0,
1361
202k
  /* 72 */ 'f', 's', '4', 0,
1362
202k
  /* 76 */ 'f', 't', '4', 0,
1363
202k
  /* 80 */ 'f', 'a', '5', 0,
1364
202k
  /* 84 */ 'f', 's', '5', 0,
1365
202k
  /* 88 */ 'f', 't', '5', 0,
1366
202k
  /* 92 */ 'f', 'a', '6', 0,
1367
202k
  /* 96 */ 'f', 's', '6', 0,
1368
202k
  /* 100 */ 'f', 't', '6', 0,
1369
202k
  /* 104 */ 'f', 'a', '7', 0,
1370
202k
  /* 108 */ 'f', 's', '7', 0,
1371
202k
  /* 112 */ 'f', 't', '7', 0,
1372
202k
  /* 116 */ 'f', 's', '8', 0,
1373
202k
  /* 120 */ 'f', 't', '8', 0,
1374
202k
  /* 124 */ 'f', 's', '9', 0,
1375
202k
  /* 128 */ 'f', 't', '9', 0,
1376
202k
  /* 132 */ 'r', 'a', 0,
1377
202k
  /* 135 */ 'z', 'e', 'r', 'o', 0,
1378
202k
  /* 140 */ 'g', 'p', 0,
1379
202k
  /* 143 */ 's', 'p', 0,
1380
202k
  /* 146 */ 't', 'p', 0,
1381
202k
  };
1382
1383
202k
  static const uint8_t RegAsmOffsetABIRegAltName[] = {
1384
202k
    135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, 
1385
202k
    69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, 
1386
202k
    65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, 
1387
202k
    88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, 
1388
202k
    44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, 
1389
202k
    60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, 
1390
202k
    0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, 
1391
202k
  };
1392
1393
202k
  static const char AsmStrsNoRegAltName[] = {
1394
202k
  /* 0 */ 'f', '1', '0', 0,
1395
202k
  /* 4 */ 'x', '1', '0', 0,
1396
202k
  /* 8 */ 'f', '2', '0', 0,
1397
202k
  /* 12 */ 'x', '2', '0', 0,
1398
202k
  /* 16 */ 'f', '3', '0', 0,
1399
202k
  /* 20 */ 'x', '3', '0', 0,
1400
202k
  /* 24 */ 'f', '0', 0,
1401
202k
  /* 27 */ 'x', '0', 0,
1402
202k
  /* 30 */ 'f', '1', '1', 0,
1403
202k
  /* 34 */ 'x', '1', '1', 0,
1404
202k
  /* 38 */ 'f', '2', '1', 0,
1405
202k
  /* 42 */ 'x', '2', '1', 0,
1406
202k
  /* 46 */ 'f', '3', '1', 0,
1407
202k
  /* 50 */ 'x', '3', '1', 0,
1408
202k
  /* 54 */ 'f', '1', 0,
1409
202k
  /* 57 */ 'x', '1', 0,
1410
202k
  /* 60 */ 'f', '1', '2', 0,
1411
202k
  /* 64 */ 'x', '1', '2', 0,
1412
202k
  /* 68 */ 'f', '2', '2', 0,
1413
202k
  /* 72 */ 'x', '2', '2', 0,
1414
202k
  /* 76 */ 'f', '2', 0,
1415
202k
  /* 79 */ 'x', '2', 0,
1416
202k
  /* 82 */ 'f', '1', '3', 0,
1417
202k
  /* 86 */ 'x', '1', '3', 0,
1418
202k
  /* 90 */ 'f', '2', '3', 0,
1419
202k
  /* 94 */ 'x', '2', '3', 0,
1420
202k
  /* 98 */ 'f', '3', 0,
1421
202k
  /* 101 */ 'x', '3', 0,
1422
202k
  /* 104 */ 'f', '1', '4', 0,
1423
202k
  /* 108 */ 'x', '1', '4', 0,
1424
202k
  /* 112 */ 'f', '2', '4', 0,
1425
202k
  /* 116 */ 'x', '2', '4', 0,
1426
202k
  /* 120 */ 'f', '4', 0,
1427
202k
  /* 123 */ 'x', '4', 0,
1428
202k
  /* 126 */ 'f', '1', '5', 0,
1429
202k
  /* 130 */ 'x', '1', '5', 0,
1430
202k
  /* 134 */ 'f', '2', '5', 0,
1431
202k
  /* 138 */ 'x', '2', '5', 0,
1432
202k
  /* 142 */ 'f', '5', 0,
1433
202k
  /* 145 */ 'x', '5', 0,
1434
202k
  /* 148 */ 'f', '1', '6', 0,
1435
202k
  /* 152 */ 'x', '1', '6', 0,
1436
202k
  /* 156 */ 'f', '2', '6', 0,
1437
202k
  /* 160 */ 'x', '2', '6', 0,
1438
202k
  /* 164 */ 'f', '6', 0,
1439
202k
  /* 167 */ 'x', '6', 0,
1440
202k
  /* 170 */ 'f', '1', '7', 0,
1441
202k
  /* 174 */ 'x', '1', '7', 0,
1442
202k
  /* 178 */ 'f', '2', '7', 0,
1443
202k
  /* 182 */ 'x', '2', '7', 0,
1444
202k
  /* 186 */ 'f', '7', 0,
1445
202k
  /* 189 */ 'x', '7', 0,
1446
202k
  /* 192 */ 'f', '1', '8', 0,
1447
202k
  /* 196 */ 'x', '1', '8', 0,
1448
202k
  /* 200 */ 'f', '2', '8', 0,
1449
202k
  /* 204 */ 'x', '2', '8', 0,
1450
202k
  /* 208 */ 'f', '8', 0,
1451
202k
  /* 211 */ 'x', '8', 0,
1452
202k
  /* 214 */ 'f', '1', '9', 0,
1453
202k
  /* 218 */ 'x', '1', '9', 0,
1454
202k
  /* 222 */ 'f', '2', '9', 0,
1455
202k
  /* 226 */ 'x', '2', '9', 0,
1456
202k
  /* 230 */ 'f', '9', 0,
1457
202k
  /* 233 */ 'x', '9', 0,
1458
202k
  };
1459
1460
202k
  static const uint8_t RegAsmOffsetNoRegAltName[] = {
1461
202k
    27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, 
1462
202k
    108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, 
1463
202k
    204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, 
1464
202k
    142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, 
1465
202k
    60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, 
1466
202k
    214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, 
1467
202k
    156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, 
1468
202k
  };
1469
1470
202k
  switch(AltIdx) {
1471
0
  default: CS_ASSERT(0 && "Invalid register alt name index!");
1472
202k
  case RISCV_ABIRegAltName:
1473
202k
    CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) &&
1474
202k
           "Invalid alt name index for register!");
1475
202k
    return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1];
1476
0
  case RISCV_NoRegAltName:
1477
0
    CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1478
0
           "Invalid alt name index for register!");
1479
0
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1480
202k
  }
1481
#else
1482
  return NULL;
1483
#endif
1484
202k
}
1485
1486
#ifdef PRINT_ALIAS_INSTR
1487
#undef PRINT_ALIAS_INSTR
1488
1489
static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp,
1490
                  unsigned PredicateIndex);
1491
1492
static bool printAliasInstr(MCInst *MI, SStream * OS, void *info)
1493
120k
{
1494
120k
  MCRegisterInfo *MRI = (MCRegisterInfo *) info;
1495
120k
  const char *AsmString;
1496
120k
  unsigned I = 0;
1497
120k
#define ASMSTRING_CONTAIN_SIZE 64
1498
120k
  unsigned AsmStringLen = 0;
1499
120k
  char tmpString_[ASMSTRING_CONTAIN_SIZE];
1500
120k
  char *tmpString = tmpString_;
1501
120k
  switch (MCInst_getOpcode(MI)) {
1502
5.89k
  default: return false;
1503
701
  case RISCV_ADDI:
1504
701
    if (MCInst_getNumOperands(MI) == 3 &&
1505
701
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1506
701
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1507
701
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1508
701
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1509
      // (ADDI X0, X0, 0)
1510
73
      AsmString = "nop";
1511
73
      break;
1512
73
    }
1513
628
    if (MCInst_getNumOperands(MI) == 3 &&
1514
628
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1515
628
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1516
628
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1517
628
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1518
628
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1519
628
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1520
      // (ADDI GPR:$rd, GPR:$rs, 0)
1521
212
      AsmString = "mv $\x01, $\x02";
1522
212
      break;
1523
212
    }
1524
416
    return false;
1525
842
  case RISCV_ADDIW:
1526
842
    if (MCInst_getNumOperands(MI) == 3 &&
1527
842
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1528
842
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1529
842
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1530
842
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1531
842
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1532
842
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1533
      // (ADDIW GPR:$rd, GPR:$rs, 0)
1534
548
      AsmString = "sext.w $\x01, $\x02";
1535
548
      break;
1536
548
    }
1537
294
    return false;
1538
141
  case RISCV_BEQ:
1539
141
    if (MCInst_getNumOperands(MI) == 3 &&
1540
141
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1541
141
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1542
141
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1543
141
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1544
      // (BEQ GPR:$rs, X0, simm13_lsb0:$offset)
1545
36
      AsmString = "beqz $\x01, $\x03";
1546
36
      break;
1547
36
    }
1548
105
    return false;
1549
655
  case RISCV_BGE:
1550
655
    if (MCInst_getNumOperands(MI) == 3 &&
1551
655
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1552
655
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1553
655
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1554
655
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1555
      // (BGE X0, GPR:$rs, simm13_lsb0:$offset)
1556
117
      AsmString = "blez $\x02, $\x03";
1557
117
      break;
1558
117
    }
1559
538
    if (MCInst_getNumOperands(MI) == 3 &&
1560
538
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1561
538
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1562
538
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1563
538
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1564
      // (BGE GPR:$rs, X0, simm13_lsb0:$offset)
1565
125
      AsmString = "bgez $\x01, $\x03";
1566
125
      break;
1567
125
    }
1568
413
    return false;
1569
345
  case RISCV_BLT:
1570
345
    if (MCInst_getNumOperands(MI) == 3 &&
1571
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1572
345
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1573
345
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1574
345
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1575
      // (BLT GPR:$rs, X0, simm13_lsb0:$offset)
1576
73
      AsmString = "bltz $\x01, $\x03";
1577
73
      break;
1578
73
    }
1579
272
    if (MCInst_getNumOperands(MI) == 3 &&
1580
272
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1581
272
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1582
272
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1583
272
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1584
      // (BLT X0, GPR:$rs, simm13_lsb0:$offset)
1585
102
      AsmString = "bgtz $\x02, $\x03";
1586
102
      break;
1587
102
    }
1588
170
    return false;
1589
300
  case RISCV_BNE:
1590
300
    if (MCInst_getNumOperands(MI) == 3 &&
1591
300
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1592
300
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1593
300
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1594
300
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1595
      // (BNE GPR:$rs, X0, simm13_lsb0:$offset)
1596
150
      AsmString = "bnez $\x01, $\x03";
1597
150
      break;
1598
150
    }
1599
150
    return false;
1600
9.38k
  case RISCV_CSRRC:
1601
9.38k
    if (MCInst_getNumOperands(MI) == 3 &&
1602
9.38k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1603
9.38k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1604
9.38k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1605
      // (CSRRC X0, csr_sysreg:$csr, GPR:$rs)
1606
2.11k
      AsmString = "csrc $\xFF\x02\x01, $\x03";
1607
2.11k
      break;
1608
2.11k
    }
1609
7.26k
    return false;
1610
13.9k
  case RISCV_CSRRCI:
1611
13.9k
    if (MCInst_getNumOperands(MI) == 3 &&
1612
13.9k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1613
      // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)
1614
1.20k
      AsmString = "csrci $\xFF\x02\x01, $\x03";
1615
1.20k
      break;
1616
1.20k
    }
1617
12.7k
    return false;
1618
30.2k
  case RISCV_CSRRS:
1619
30.2k
    if (MCInst_getNumOperands(MI) == 3 &&
1620
30.2k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1621
30.2k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1622
30.2k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
30.2k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1624
30.2k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1625
      // (CSRRS GPR:$rd, 3, X0)
1626
64
      AsmString = "frcsr $\x01";
1627
64
      break;
1628
64
    }
1629
30.2k
    if (MCInst_getNumOperands(MI) == 3 &&
1630
30.2k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1631
30.2k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1632
30.2k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1633
30.2k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1634
30.2k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1635
      // (CSRRS GPR:$rd, 2, X0)
1636
52
      AsmString = "frrm $\x01";
1637
52
      break;
1638
52
    }
1639
30.1k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
30.1k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1641
30.1k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1642
30.1k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1643
30.1k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1644
30.1k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1645
      // (CSRRS GPR:$rd, 1, X0)
1646
99
      AsmString = "frflags $\x01";
1647
99
      break;
1648
99
    }
1649
30.0k
    if (MCInst_getNumOperands(MI) == 3 &&
1650
30.0k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1651
30.0k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1652
30.0k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1653
30.0k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 &&
1654
30.0k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1655
      // (CSRRS GPR:$rd, 3074, X0)
1656
87
      AsmString = "rdinstret $\x01";
1657
87
      break;
1658
87
    }
1659
29.9k
    if (MCInst_getNumOperands(MI) == 3 &&
1660
29.9k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1661
29.9k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1662
29.9k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1663
29.9k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 &&
1664
29.9k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1665
      // (CSRRS GPR:$rd, 3072, X0)
1666
123
      AsmString = "rdcycle $\x01";
1667
123
      break;
1668
123
    }
1669
29.8k
    if (MCInst_getNumOperands(MI) == 3 &&
1670
29.8k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1671
29.8k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1672
29.8k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1673
29.8k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 &&
1674
29.8k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1675
      // (CSRRS GPR:$rd, 3073, X0)
1676
244
      AsmString = "rdtime $\x01";
1677
244
      break;
1678
244
    }
1679
29.6k
    if (MCInst_getNumOperands(MI) == 3 &&
1680
29.6k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1681
29.6k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1682
29.6k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1683
29.6k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 &&
1684
29.6k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1685
      // (CSRRS GPR:$rd, 3202, X0)
1686
14
      AsmString = "rdinstreth $\x01";
1687
14
      break;
1688
14
    }
1689
29.6k
    if (MCInst_getNumOperands(MI) == 3 &&
1690
29.6k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1691
29.6k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1692
29.6k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1693
29.6k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 &&
1694
29.6k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1695
      // (CSRRS GPR:$rd, 3200, X0)
1696
31
      AsmString = "rdcycleh $\x01";
1697
31
      break;
1698
31
    }
1699
29.5k
    if (MCInst_getNumOperands(MI) == 3 &&
1700
29.5k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1701
29.5k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1702
29.5k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1703
29.5k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 &&
1704
29.5k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1705
      // (CSRRS GPR:$rd, 3201, X0)
1706
92
      AsmString = "rdtimeh $\x01";
1707
92
      break;
1708
92
    }
1709
29.4k
    if (MCInst_getNumOperands(MI) == 3 &&
1710
29.4k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1711
29.4k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1712
29.4k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1713
      // (CSRRS GPR:$rd, csr_sysreg:$csr, X0)
1714
6.95k
      AsmString = "csrr $\x01, $\xFF\x02\x01";
1715
6.95k
      break;
1716
6.95k
    }
1717
22.5k
    if (MCInst_getNumOperands(MI) == 3 &&
1718
22.5k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1719
22.5k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1720
22.5k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1721
      // (CSRRS X0, csr_sysreg:$csr, GPR:$rs)
1722
538
      AsmString = "csrs $\xFF\x02\x01, $\x03";
1723
538
      break;
1724
538
    }
1725
21.9k
    return false;
1726
9.98k
  case RISCV_CSRRSI:
1727
9.98k
    if (MCInst_getNumOperands(MI) == 3 &&
1728
9.98k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1729
      // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)
1730
682
      AsmString = "csrsi $\xFF\x02\x01, $\x03";
1731
682
      break;
1732
682
    }
1733
9.30k
    return false;
1734
8.02k
  case RISCV_CSRRW:
1735
8.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1736
8.02k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1737
8.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1738
8.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1739
8.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1740
8.02k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1741
      // (CSRRW X0, 3, GPR:$rs)
1742
25
      AsmString = "fscsr $\x03";
1743
25
      break;
1744
25
    }
1745
7.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1746
7.99k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1747
7.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1748
7.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1749
7.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1750
7.99k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1751
      // (CSRRW X0, 2, GPR:$rs)
1752
225
      AsmString = "fsrm $\x03";
1753
225
      break;
1754
225
    }
1755
7.77k
    if (MCInst_getNumOperands(MI) == 3 &&
1756
7.77k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1757
7.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
7.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1759
7.77k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1760
7.77k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1761
      // (CSRRW X0, 1, GPR:$rs)
1762
144
      AsmString = "fsflags $\x03";
1763
144
      break;
1764
144
    }
1765
7.62k
    if (MCInst_getNumOperands(MI) == 3 &&
1766
7.62k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1767
7.62k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1768
7.62k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1769
      // (CSRRW X0, csr_sysreg:$csr, GPR:$rs)
1770
769
      AsmString = "csrw $\xFF\x02\x01, $\x03";
1771
769
      break;
1772
769
    }
1773
6.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1774
6.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1775
6.86k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1776
6.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1777
6.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1778
6.86k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1779
6.86k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1780
      // (CSRRW GPR:$rd, 3, GPR:$rs)
1781
1.27k
      AsmString = "fscsr $\x01, $\x03";
1782
1.27k
      break;
1783
1.27k
    }
1784
5.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1785
5.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1786
5.58k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1787
5.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1788
5.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1789
5.58k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1790
5.58k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1791
      // (CSRRW GPR:$rd, 2, GPR:$rs)
1792
71
      AsmString = "fsrm $\x01, $\x03";
1793
71
      break;
1794
71
    }
1795
5.51k
    if (MCInst_getNumOperands(MI) == 3 &&
1796
5.51k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1797
5.51k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1798
5.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1799
5.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1800
5.51k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1801
5.51k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1802
      // (CSRRW GPR:$rd, 1, GPR:$rs)
1803
82
      AsmString = "fsflags $\x01, $\x03";
1804
82
      break;
1805
82
    }
1806
5.43k
    return false;
1807
7.86k
  case RISCV_CSRRWI:
1808
7.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1809
7.86k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1810
7.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1811
7.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1812
      // (CSRRWI X0, 2, uimm5:$imm)
1813
22
      AsmString = "fsrmi $\x03";
1814
22
      break;
1815
22
    }
1816
7.84k
    if (MCInst_getNumOperands(MI) == 3 &&
1817
7.84k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1818
7.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1819
7.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1820
      // (CSRRWI X0, 1, uimm5:$imm)
1821
151
      AsmString = "fsflagsi $\x03";
1822
151
      break;
1823
151
    }
1824
7.69k
    if (MCInst_getNumOperands(MI) == 3 &&
1825
7.69k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1826
      // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)
1827
2.10k
      AsmString = "csrwi $\xFF\x02\x01, $\x03";
1828
2.10k
      break;
1829
2.10k
    }
1830
5.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1831
5.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1832
5.58k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1833
5.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1834
5.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1835
      // (CSRRWI GPR:$rd, 2, uimm5:$imm)
1836
84
      AsmString = "fsrmi $\x01, $\x03";
1837
84
      break;
1838
84
    }
1839
5.50k
    if (MCInst_getNumOperands(MI) == 3 &&
1840
5.50k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1841
5.50k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1842
5.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1843
5.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1844
      // (CSRRWI GPR:$rd, 1, uimm5:$imm)
1845
30
      AsmString = "fsflagsi $\x01, $\x03";
1846
30
      break;
1847
30
    }
1848
5.47k
    return false;
1849
74
  case RISCV_FADD_D:
1850
74
    if (MCInst_getNumOperands(MI) == 4 &&
1851
74
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1852
74
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1853
74
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1854
74
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1855
74
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1856
74
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
1857
74
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
1858
74
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
1859
      // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
1860
27
      AsmString = "fadd.d $\x01, $\x02, $\x03";
1861
27
      break;
1862
27
    }
1863
47
    return false;
1864
929
  case RISCV_FADD_S:
1865
929
    if (MCInst_getNumOperands(MI) == 4 &&
1866
929
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1867
929
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1868
929
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1869
929
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1870
929
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1871
929
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
1872
929
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
1873
929
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
1874
      // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
1875
417
      AsmString = "fadd.s $\x01, $\x02, $\x03";
1876
417
      break;
1877
417
    }
1878
512
    return false;
1879
1.43k
  case RISCV_FCVT_D_L:
1880
1.43k
    if (MCInst_getNumOperands(MI) == 3 &&
1881
1.43k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1882
1.43k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1883
1.43k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1884
1.43k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1885
1.43k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1886
1.43k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1887
      // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 })
1888
526
      AsmString = "fcvt.d.l $\x01, $\x02";
1889
526
      break;
1890
526
    }
1891
910
    return false;
1892
104
  case RISCV_FCVT_D_LU:
1893
104
    if (MCInst_getNumOperands(MI) == 3 &&
1894
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1895
104
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1896
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1897
104
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1898
104
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1899
104
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1900
      // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 })
1901
69
      AsmString = "fcvt.d.lu $\x01, $\x02";
1902
69
      break;
1903
69
    }
1904
35
    return false;
1905
189
  case RISCV_FCVT_LU_D:
1906
189
    if (MCInst_getNumOperands(MI) == 3 &&
1907
189
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1908
189
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1909
189
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1910
189
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1911
189
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1912
189
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1913
      // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
1914
118
      AsmString = "fcvt.lu.d $\x01, $\x02";
1915
118
      break;
1916
118
    }
1917
71
    return false;
1918
100
  case RISCV_FCVT_LU_S:
1919
100
    if (MCInst_getNumOperands(MI) == 3 &&
1920
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1921
100
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1922
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1923
100
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1924
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1925
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1926
      // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
1927
67
      AsmString = "fcvt.lu.s $\x01, $\x02";
1928
67
      break;
1929
67
    }
1930
33
    return false;
1931
276
  case RISCV_FCVT_L_D:
1932
276
    if (MCInst_getNumOperands(MI) == 3 &&
1933
276
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1934
276
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1935
276
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1936
276
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1937
276
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1938
276
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1939
      // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
1940
211
      AsmString = "fcvt.l.d $\x01, $\x02";
1941
211
      break;
1942
211
    }
1943
65
    return false;
1944
696
  case RISCV_FCVT_L_S:
1945
696
    if (MCInst_getNumOperands(MI) == 3 &&
1946
696
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1947
696
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1948
696
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1949
696
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1950
696
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1951
696
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1952
      // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
1953
510
      AsmString = "fcvt.l.s $\x01, $\x02";
1954
510
      break;
1955
510
    }
1956
186
    return false;
1957
624
  case RISCV_FCVT_S_D:
1958
624
    if (MCInst_getNumOperands(MI) == 3 &&
1959
624
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1960
624
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1961
624
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1962
624
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1963
624
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1964
624
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1965
      // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 })
1966
211
      AsmString = "fcvt.s.d $\x01, $\x02";
1967
211
      break;
1968
211
    }
1969
413
    return false;
1970
973
  case RISCV_FCVT_S_L:
1971
973
    if (MCInst_getNumOperands(MI) == 3 &&
1972
973
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1973
973
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1974
973
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1975
973
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1976
973
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1977
973
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1978
      // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
1979
421
      AsmString = "fcvt.s.l $\x01, $\x02";
1980
421
      break;
1981
421
    }
1982
552
    return false;
1983
618
  case RISCV_FCVT_S_LU:
1984
618
    if (MCInst_getNumOperands(MI) == 3 &&
1985
618
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1986
618
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1987
618
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1988
618
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1989
618
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1990
618
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1991
      // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
1992
21
      AsmString = "fcvt.s.lu $\x01, $\x02";
1993
21
      break;
1994
21
    }
1995
597
    return false;
1996
670
  case RISCV_FCVT_S_W:
1997
670
    if (MCInst_getNumOperands(MI) == 3 &&
1998
670
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1999
670
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2000
670
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2001
670
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2002
670
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2003
670
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2004
      // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
2005
317
      AsmString = "fcvt.s.w $\x01, $\x02";
2006
317
      break;
2007
317
    }
2008
353
    return false;
2009
371
  case RISCV_FCVT_S_WU:
2010
371
    if (MCInst_getNumOperands(MI) == 3 &&
2011
371
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2012
371
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2013
371
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2014
371
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2015
371
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2016
371
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2017
      // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
2018
213
      AsmString = "fcvt.s.wu $\x01, $\x02";
2019
213
      break;
2020
213
    }
2021
158
    return false;
2022
628
  case RISCV_FCVT_WU_D:
2023
628
    if (MCInst_getNumOperands(MI) == 3 &&
2024
628
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2025
628
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2026
628
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2027
628
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2028
628
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2029
628
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2030
      // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
2031
346
      AsmString = "fcvt.wu.d $\x01, $\x02";
2032
346
      break;
2033
346
    }
2034
282
    return false;
2035
437
  case RISCV_FCVT_WU_S:
2036
437
    if (MCInst_getNumOperands(MI) == 3 &&
2037
437
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2038
437
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2039
437
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2040
437
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2041
437
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2042
437
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2043
      // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
2044
210
      AsmString = "fcvt.wu.s $\x01, $\x02";
2045
210
      break;
2046
210
    }
2047
227
    return false;
2048
262
  case RISCV_FCVT_W_D:
2049
262
    if (MCInst_getNumOperands(MI) == 3 &&
2050
262
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2051
262
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2052
262
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2053
262
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2054
262
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2055
262
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2056
      // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
2057
196
      AsmString = "fcvt.w.d $\x01, $\x02";
2058
196
      break;
2059
196
    }
2060
66
    return false;
2061
1.20k
  case RISCV_FCVT_W_S:
2062
1.20k
    if (MCInst_getNumOperands(MI) == 3 &&
2063
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2064
1.20k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2065
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2066
1.20k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2067
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2068
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2069
      // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
2070
1.06k
      AsmString = "fcvt.w.s $\x01, $\x02";
2071
1.06k
      break;
2072
1.06k
    }
2073
145
    return false;
2074
1.59k
  case RISCV_FDIV_D:
2075
1.59k
    if (MCInst_getNumOperands(MI) == 4 &&
2076
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2077
1.59k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2078
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2079
1.59k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2080
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2081
1.59k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2082
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2083
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2084
      // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2085
166
      AsmString = "fdiv.d $\x01, $\x02, $\x03";
2086
166
      break;
2087
166
    }
2088
1.42k
    return false;
2089
78
  case RISCV_FDIV_S:
2090
78
    if (MCInst_getNumOperands(MI) == 4 &&
2091
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2092
78
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2093
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2094
78
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2095
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2096
78
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2097
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2098
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2099
      // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2100
48
      AsmString = "fdiv.s $\x01, $\x02, $\x03";
2101
48
      break;
2102
48
    }
2103
30
    return false;
2104
1.82k
  case RISCV_FENCE:
2105
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
2107
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
2108
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2109
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2110
      // (FENCE 15, 15)
2111
17
      AsmString = "fence";
2112
17
      break;
2113
17
    }
2114
1.80k
    return false;
2115
971
  case RISCV_FMADD_D:
2116
971
    if (MCInst_getNumOperands(MI) == 5 &&
2117
971
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2118
971
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2119
971
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2120
971
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2121
971
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2122
971
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2123
971
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2124
971
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2125
971
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2126
971
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2127
      // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2128
139
      AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04";
2129
139
      break;
2130
139
    }
2131
832
    return false;
2132
1.83k
  case RISCV_FMADD_S:
2133
1.83k
    if (MCInst_getNumOperands(MI) == 5 &&
2134
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2135
1.83k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2136
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2137
1.83k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2138
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2139
1.83k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2140
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2141
1.83k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2142
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2143
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2144
      // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2145
87
      AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04";
2146
87
      break;
2147
87
    }
2148
1.74k
    return false;
2149
192
  case RISCV_FMSUB_D:
2150
192
    if (MCInst_getNumOperands(MI) == 5 &&
2151
192
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2152
192
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2153
192
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2154
192
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2155
192
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2156
192
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2157
192
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2158
192
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2159
192
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2160
192
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2161
      // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2162
100
      AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04";
2163
100
      break;
2164
100
    }
2165
92
    return false;
2166
207
  case RISCV_FMSUB_S:
2167
207
    if (MCInst_getNumOperands(MI) == 5 &&
2168
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2169
207
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2170
207
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2171
207
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2172
207
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2173
207
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2174
207
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2175
207
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2176
207
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2177
207
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2178
      // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2179
126
      AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04";
2180
126
      break;
2181
126
    }
2182
81
    return false;
2183
579
  case RISCV_FMUL_D:
2184
579
    if (MCInst_getNumOperands(MI) == 4 &&
2185
579
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2186
579
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2187
579
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2188
579
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2189
579
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2190
579
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2191
579
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2192
579
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2193
      // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2194
76
      AsmString = "fmul.d $\x01, $\x02, $\x03";
2195
76
      break;
2196
76
    }
2197
503
    return false;
2198
217
  case RISCV_FMUL_S:
2199
217
    if (MCInst_getNumOperands(MI) == 4 &&
2200
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2201
217
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2202
217
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2203
217
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2204
217
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2205
217
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2206
217
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2207
217
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2208
      // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2209
139
      AsmString = "fmul.s $\x01, $\x02, $\x03";
2210
139
      break;
2211
139
    }
2212
78
    return false;
2213
1.24k
  case RISCV_FNMADD_D:
2214
1.24k
    if (MCInst_getNumOperands(MI) == 5 &&
2215
1.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2216
1.24k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2217
1.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2218
1.24k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2219
1.24k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2220
1.24k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2221
1.24k
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2222
1.24k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2223
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2224
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2225
      // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2226
1.04k
      AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04";
2227
1.04k
      break;
2228
1.04k
    }
2229
198
    return false;
2230
201
  case RISCV_FNMADD_S:
2231
201
    if (MCInst_getNumOperands(MI) == 5 &&
2232
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2233
201
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2234
201
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2235
201
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2236
201
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2237
201
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2238
201
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2239
201
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2240
201
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2241
201
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2242
      // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2243
74
      AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04";
2244
74
      break;
2245
74
    }
2246
127
    return false;
2247
313
  case RISCV_FNMSUB_D:
2248
313
    if (MCInst_getNumOperands(MI) == 5 &&
2249
313
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2250
313
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2251
313
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2252
313
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2253
313
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2254
313
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2255
313
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2256
313
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2257
313
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2258
313
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2259
      // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2260
28
      AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04";
2261
28
      break;
2262
28
    }
2263
285
    return false;
2264
120
  case RISCV_FNMSUB_S:
2265
120
    if (MCInst_getNumOperands(MI) == 5 &&
2266
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2267
120
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2268
120
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2269
120
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2270
120
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2271
120
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2272
120
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2273
120
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2274
120
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2275
120
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2276
      // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2277
31
      AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04";
2278
31
      break;
2279
31
    }
2280
89
    return false;
2281
652
  case RISCV_FSGNJN_D:
2282
652
    if (MCInst_getNumOperands(MI) == 3 &&
2283
652
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
652
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2285
652
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
652
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2287
652
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2288
652
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2289
      // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2290
286
      AsmString = "fneg.d $\x01, $\x02";
2291
286
      break;
2292
286
    }
2293
366
    return false;
2294
1.09k
  case RISCV_FSGNJN_S:
2295
1.09k
    if (MCInst_getNumOperands(MI) == 3 &&
2296
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2297
1.09k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2298
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2299
1.09k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2300
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2301
1.09k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2302
      // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2303
223
      AsmString = "fneg.s $\x01, $\x02";
2304
223
      break;
2305
223
    }
2306
875
    return false;
2307
396
  case RISCV_FSGNJX_D:
2308
396
    if (MCInst_getNumOperands(MI) == 3 &&
2309
396
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2310
396
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2311
396
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2312
396
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2313
396
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2314
396
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2315
      // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2316
251
      AsmString = "fabs.d $\x01, $\x02";
2317
251
      break;
2318
251
    }
2319
145
    return false;
2320
820
  case RISCV_FSGNJX_S:
2321
820
    if (MCInst_getNumOperands(MI) == 3 &&
2322
820
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2323
820
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2324
820
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2325
820
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2326
820
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2327
820
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2328
      // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2329
581
      AsmString = "fabs.s $\x01, $\x02";
2330
581
      break;
2331
581
    }
2332
239
    return false;
2333
332
  case RISCV_FSGNJ_D:
2334
332
    if (MCInst_getNumOperands(MI) == 3 &&
2335
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2336
332
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2337
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2338
332
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2339
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2340
332
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2341
      // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2342
32
      AsmString = "fmv.d $\x01, $\x02";
2343
32
      break;
2344
32
    }
2345
300
    return false;
2346
329
  case RISCV_FSGNJ_S:
2347
329
    if (MCInst_getNumOperands(MI) == 3 &&
2348
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2349
329
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2350
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2351
329
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2352
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2353
329
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2354
      // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2355
107
      AsmString = "fmv.s $\x01, $\x02";
2356
107
      break;
2357
107
    }
2358
222
    return false;
2359
243
  case RISCV_FSQRT_D:
2360
243
    if (MCInst_getNumOperands(MI) == 3 &&
2361
243
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2362
243
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2363
243
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2364
243
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2365
243
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2366
243
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2367
      // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 })
2368
126
      AsmString = "fsqrt.d $\x01, $\x02";
2369
126
      break;
2370
126
    }
2371
117
    return false;
2372
1.79k
  case RISCV_FSQRT_S:
2373
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
2374
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2375
1.79k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2376
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2377
1.79k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2378
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2379
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2380
      // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 })
2381
578
      AsmString = "fsqrt.s $\x01, $\x02";
2382
578
      break;
2383
578
    }
2384
1.21k
    return false;
2385
550
  case RISCV_FSUB_D:
2386
550
    if (MCInst_getNumOperands(MI) == 4 &&
2387
550
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2388
550
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2389
550
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2390
550
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2391
550
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2392
550
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2393
550
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2394
550
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2395
      // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2396
94
      AsmString = "fsub.d $\x01, $\x02, $\x03";
2397
94
      break;
2398
94
    }
2399
456
    return false;
2400
129
  case RISCV_FSUB_S:
2401
129
    if (MCInst_getNumOperands(MI) == 4 &&
2402
129
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2403
129
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2404
129
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2405
129
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2406
129
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2407
129
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2408
129
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2409
129
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2410
      // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2411
110
      AsmString = "fsub.s $\x01, $\x02, $\x03";
2412
110
      break;
2413
110
    }
2414
19
    return false;
2415
1.58k
  case RISCV_JAL:
2416
1.58k
    if (MCInst_getNumOperands(MI) == 2 &&
2417
1.58k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2418
1.58k
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) {
2419
      // (JAL X0, simm21_lsb0_jal:$offset)
2420
219
      AsmString = "j $\x02";
2421
219
      break;
2422
219
    }
2423
1.36k
    if (MCInst_getNumOperands(MI) == 2 &&
2424
1.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 &&
2425
1.36k
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) {
2426
      // (JAL X1, simm21_lsb0_jal:$offset)
2427
205
      AsmString = "jal $\x02";
2428
205
      break;
2429
205
    }
2430
1.15k
    return false;
2431
1.01k
  case RISCV_JALR:
2432
1.01k
    if (MCInst_getNumOperands(MI) == 3 &&
2433
1.01k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2434
1.01k
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 &&
2435
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2436
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2437
      // (JALR X0, X1, 0)
2438
211
      AsmString = "ret";
2439
211
      break;
2440
211
    }
2441
808
    if (MCInst_getNumOperands(MI) == 3 &&
2442
808
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2443
808
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2444
808
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2445
808
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2446
808
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2447
      // (JALR X0, GPR:$rs, 0)
2448
105
      AsmString = "jr $\x02";
2449
105
      break;
2450
105
    }
2451
703
    if (MCInst_getNumOperands(MI) == 3 &&
2452
703
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 &&
2453
703
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2454
703
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2455
703
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2456
703
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2457
      // (JALR X1, GPR:$rs, 0)
2458
83
      AsmString = "jalr $\x02";
2459
83
      break;
2460
83
    }
2461
620
    return false;
2462
1.08k
  case RISCV_SFENCE_VMA:
2463
1.08k
    if (MCInst_getNumOperands(MI) == 2 &&
2464
1.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2465
1.08k
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) {
2466
      // (SFENCE_VMA X0, X0)
2467
189
      AsmString = "sfence.vma";
2468
189
      break;
2469
189
    }
2470
900
    if (MCInst_getNumOperands(MI) == 2 &&
2471
900
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2472
900
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2473
900
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) {
2474
      // (SFENCE_VMA GPR:$rs, X0)
2475
236
      AsmString = "sfence.vma $\x01";
2476
236
      break;
2477
236
    }
2478
664
    return false;
2479
1.95k
  case RISCV_SLT:
2480
1.95k
    if (MCInst_getNumOperands(MI) == 3 &&
2481
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2482
1.95k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2483
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2484
1.95k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2485
1.95k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
2486
      // (SLT GPR:$rd, GPR:$rs, X0)
2487
89
      AsmString = "sltz $\x01, $\x02";
2488
89
      break;
2489
89
    }
2490
1.86k
    if (MCInst_getNumOperands(MI) == 3 &&
2491
1.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2492
1.86k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2493
1.86k
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2494
1.86k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2495
1.86k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2496
      // (SLT GPR:$rd, X0, GPR:$rs)
2497
838
      AsmString = "sgtz $\x01, $\x03";
2498
838
      break;
2499
838
    }
2500
1.02k
    return false;
2501
209
  case RISCV_SLTIU:
2502
209
    if (MCInst_getNumOperands(MI) == 3 &&
2503
209
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2504
209
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2505
209
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2506
209
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2507
209
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2508
209
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2509
      // (SLTIU GPR:$rd, GPR:$rs, 1)
2510
56
      AsmString = "seqz $\x01, $\x02";
2511
56
      break;
2512
56
    }
2513
153
    return false;
2514
616
  case RISCV_SLTU:
2515
616
    if (MCInst_getNumOperands(MI) == 3 &&
2516
616
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
616
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2518
616
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2519
616
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2520
616
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2521
      // (SLTU GPR:$rd, X0, GPR:$rs)
2522
485
      AsmString = "snez $\x01, $\x03";
2523
485
      break;
2524
485
    }
2525
131
    return false;
2526
53
  case RISCV_SUB:
2527
53
    if (MCInst_getNumOperands(MI) == 3 &&
2528
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2529
53
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2530
53
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2531
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2532
53
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2533
      // (SUB GPR:$rd, X0, GPR:$rs)
2534
10
      AsmString = "neg $\x01, $\x03";
2535
10
      break;
2536
10
    }
2537
43
    return false;
2538
34
  case RISCV_SUBW:
2539
34
    if (MCInst_getNumOperands(MI) == 3 &&
2540
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2541
34
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2542
34
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2543
34
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2544
34
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2545
      // (SUBW GPR:$rd, X0, GPR:$rs)
2546
18
      AsmString = "negw $\x01, $\x03";
2547
18
      break;
2548
18
    }
2549
16
    return false;
2550
199
  case RISCV_XORI:
2551
199
    if (MCInst_getNumOperands(MI) == 3 &&
2552
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2553
199
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2554
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2555
199
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2556
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2557
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) {
2558
      // (XORI GPR:$rd, GPR:$rs, -1)
2559
76
      AsmString = "not $\x01, $\x02";
2560
76
      break;
2561
76
    }
2562
123
    return false;
2563
120k
  }
2564
2565
30.9k
  AsmStringLen = strlen(AsmString);
2566
30.9k
  if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen)
2567
0
    tmpString = cs_strdup(AsmString);
2568
30.9k
  else
2569
30.9k
    tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen);
2570
2571
197k
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
2572
197k
         AsmString[I] != '$' && AsmString[I] != '\0')
2573
166k
    ++I;
2574
30.9k
  tmpString[I] = 0;
2575
30.9k
  SStream_concat0(OS, tmpString);
2576
30.9k
  if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen)
2577
    /* Free the possible cs_strdup() memory. PR#1424. */
2578
0
    cs_mem_free(tmpString);
2579
30.9k
#undef ASMSTRING_CONTAIN_SIZE
2580
2581
30.9k
  if (AsmString[I] != '\0') {
2582
30.4k
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
2583
30.4k
      SStream_concat0(OS, " ");
2584
30.4k
      ++I;
2585
30.4k
    }
2586
128k
    do {
2587
128k
      if (AsmString[I] == '$') {
2588
63.0k
        ++I;
2589
63.0k
        if (AsmString[I] == (char)0xff) {
2590
14.3k
          ++I;
2591
14.3k
          int OpIdx = AsmString[I++] - 1;
2592
14.3k
          int PrintMethodIdx = AsmString[I++] - 1;
2593
14.3k
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
2594
14.3k
        } else
2595
48.6k
          printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
2596
65.1k
      } else {
2597
65.1k
        SStream_concat1(OS, AsmString[I++]);
2598
65.1k
      }
2599
128k
    } while (AsmString[I] != '\0');
2600
30.4k
  }
2601
2602
30.9k
  return true;
2603
120k
}
2604
2605
static void printCustomAliasOperand(
2606
         MCInst *MI, unsigned OpIdx,
2607
         unsigned PrintMethodIdx,
2608
14.3k
         SStream *OS) {
2609
14.3k
  switch (PrintMethodIdx) {
2610
0
  default:
2611
0
    CS_ASSERT(0 && "Unknown PrintMethod kind");
2612
0
    break;
2613
14.3k
  case 0:
2614
14.3k
    printCSRSystemRegister(MI, OpIdx, OS);
2615
14.3k
    break;
2616
14.3k
  }
2617
14.3k
}
2618
2619
static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp,
2620
1.02k
                  unsigned PredicateIndex) {
2621
  // TODO: need some constant untils operate the MCOperand,
2622
  // but current CAPSTONE does't have.
2623
  // So, We just return true
2624
1.02k
  return true;
2625
2626
#if 0
2627
  switch (PredicateIndex) {
2628
  default:
2629
    llvm_unreachable("Unknown MCOperandPredicate kind");
2630
    break;
2631
  case 1: {
2632
2633
    int64_t Imm;
2634
    if (MCOp.evaluateAsConstantImm(Imm))
2635
      return isShiftedInt<12, 1>(Imm);
2636
    return MCOp.isBareSymbolRef();
2637
  
2638
    }
2639
  case 2: {
2640
2641
    int64_t Imm;
2642
    if (MCOp.evaluateAsConstantImm(Imm))
2643
      return isShiftedInt<20, 1>(Imm);
2644
    return MCOp.isBareSymbolRef();
2645
  
2646
    }
2647
  }
2648
#endif
2649
1.02k
}
2650
2651
#endif // PRINT_ALIAS_INSTR