Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/X86/X86IntelInstPrinter.c
Line
Count
Source (jump to first uncovered line)
1
//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file includes code for rendering MCInst instances as Intel-style
11
// assembly.
12
//
13
//===----------------------------------------------------------------------===//
14
15
/* Capstone Disassembly Engine */
16
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
17
18
#ifdef CAPSTONE_HAS_X86
19
20
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
21
#pragma warning(disable:4996)     // disable MSVC's warning on strncpy()
22
#pragma warning(disable:28719)    // disable MSVC's warning on strncpy()
23
#endif
24
25
#if !defined(CAPSTONE_HAS_OSXKERNEL)
26
#include <ctype.h>
27
#endif
28
#include <capstone/platform.h>
29
30
#if defined(CAPSTONE_HAS_OSXKERNEL)
31
#include <Availability.h>
32
#include <libkern/libkern.h>
33
#else
34
#include <stdio.h>
35
#include <stdlib.h>
36
#endif
37
#include <string.h>
38
39
#include "../../utils.h"
40
#include "../../MCInst.h"
41
#include "../../SStream.h"
42
#include "../../MCRegisterInfo.h"
43
44
#include "X86InstPrinter.h"
45
#include "X86Mapping.h"
46
#include "X86InstPrinterCommon.h"
47
48
#define GET_INSTRINFO_ENUM
49
#ifdef CAPSTONE_X86_REDUCE
50
#include "X86GenInstrInfo_reduce.inc"
51
#else
52
#include "X86GenInstrInfo.inc"
53
#endif
54
55
#define GET_REGINFO_ENUM
56
#include "X86GenRegisterInfo.inc"
57
58
#include "X86BaseInfo.h"
59
60
static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
61
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
62
63
64
static void set_mem_access(MCInst *MI, bool status)
65
123k
{
66
123k
  if (MI->csh->detail_opt != CS_OPT_ON)
67
0
    return;
68
69
123k
  MI->csh->doing_mem = status;
70
123k
  if (!status)
71
    // done, create the next operand slot
72
61.7k
    MI->flat_insn->detail->x86.op_count++;
73
74
123k
}
75
76
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O)
77
10.5k
{
78
  // FIXME: do this with autogen
79
  // printf(">>> ID = %u\n", MI->flat_insn->id);
80
10.5k
  switch(MI->flat_insn->id) {
81
3.88k
    default:
82
3.88k
      SStream_concat0(O, "ptr ");
83
3.88k
      break;
84
1.39k
    case X86_INS_SGDT:
85
2.20k
    case X86_INS_SIDT:
86
3.17k
    case X86_INS_LGDT:
87
4.14k
    case X86_INS_LIDT:
88
4.49k
    case X86_INS_FXRSTOR:
89
5.02k
    case X86_INS_FXSAVE:
90
5.94k
    case X86_INS_LJMP:
91
6.63k
    case X86_INS_LCALL:
92
      // do not print "ptr"
93
6.63k
      break;
94
10.5k
  }
95
96
10.5k
  switch(MI->csh->mode) {
97
3.32k
    case CS_MODE_16:
98
3.32k
      switch(MI->flat_insn->id) {
99
1.30k
        default:
100
1.30k
          MI->x86opsize = 2;
101
1.30k
          break;
102
316
        case X86_INS_LJMP:
103
622
        case X86_INS_LCALL:
104
622
          MI->x86opsize = 4;
105
622
          break;
106
344
        case X86_INS_SGDT:
107
568
        case X86_INS_SIDT:
108
938
        case X86_INS_LGDT:
109
1.40k
        case X86_INS_LIDT:
110
1.40k
          MI->x86opsize = 6;
111
1.40k
          break;
112
3.32k
      }
113
3.32k
      break;
114
4.55k
    case CS_MODE_32:
115
4.55k
      switch(MI->flat_insn->id) {
116
1.93k
        default:
117
1.93k
          MI->x86opsize = 4;
118
1.93k
          break;
119
376
        case X86_INS_LJMP:
120
1.12k
        case X86_INS_JMP:
121
1.24k
        case X86_INS_LCALL:
122
1.83k
        case X86_INS_SGDT:
123
2.08k
        case X86_INS_SIDT:
124
2.36k
        case X86_INS_LGDT:
125
2.62k
        case X86_INS_LIDT:
126
2.62k
          MI->x86opsize = 6;
127
2.62k
          break;
128
4.55k
      }
129
4.55k
      break;
130
4.55k
    case CS_MODE_64:
131
2.64k
      switch(MI->flat_insn->id) {
132
779
        default:
133
779
          MI->x86opsize = 8;
134
779
          break;
135
233
        case X86_INS_LJMP:
136
491
        case X86_INS_LCALL:
137
951
        case X86_INS_SGDT:
138
1.29k
        case X86_INS_SIDT:
139
1.61k
        case X86_INS_LGDT:
140
1.86k
        case X86_INS_LIDT:
141
1.86k
          MI->x86opsize = 10;
142
1.86k
          break;
143
2.64k
      }
144
2.64k
      break;
145
2.64k
    default:  // never reach
146
0
      break;
147
10.5k
  }
148
149
10.5k
  printMemReference(MI, OpNo, O);
150
10.5k
}
151
152
static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O)
153
108k
{
154
108k
  SStream_concat0(O, "byte ptr ");
155
108k
  MI->x86opsize = 1;
156
108k
  printMemReference(MI, OpNo, O);
157
108k
}
158
159
static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O)
160
23.9k
{
161
23.9k
  MI->x86opsize = 2;
162
23.9k
  SStream_concat0(O, "word ptr ");
163
23.9k
  printMemReference(MI, OpNo, O);
164
23.9k
}
165
166
static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O)
167
49.2k
{
168
49.2k
  MI->x86opsize = 4;
169
49.2k
  SStream_concat0(O, "dword ptr ");
170
49.2k
  printMemReference(MI, OpNo, O);
171
49.2k
}
172
173
static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O)
174
16.4k
{
175
16.4k
  SStream_concat0(O, "qword ptr ");
176
16.4k
  MI->x86opsize = 8;
177
16.4k
  printMemReference(MI, OpNo, O);
178
16.4k
}
179
180
static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O)
181
8.01k
{
182
8.01k
  SStream_concat0(O, "xmmword ptr ");
183
8.01k
  MI->x86opsize = 16;
184
8.01k
  printMemReference(MI, OpNo, O);
185
8.01k
}
186
187
static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O)
188
3.82k
{
189
3.82k
  SStream_concat0(O, "zmmword ptr ");
190
3.82k
  MI->x86opsize = 64;
191
3.82k
  printMemReference(MI, OpNo, O);
192
3.82k
}
193
194
#ifndef CAPSTONE_X86_REDUCE
195
static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O)
196
3.26k
{
197
3.26k
  SStream_concat0(O, "ymmword ptr ");
198
3.26k
  MI->x86opsize = 32;
199
3.26k
  printMemReference(MI, OpNo, O);
200
3.26k
}
201
202
static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O)
203
6.13k
{
204
6.13k
  switch(MCInst_getOpcode(MI)) {
205
4.89k
    default:
206
4.89k
      SStream_concat0(O, "dword ptr ");
207
4.89k
      MI->x86opsize = 4;
208
4.89k
      break;
209
631
    case X86_FSTENVm:
210
1.24k
    case X86_FLDENVm:
211
      // TODO: fix this in tablegen instead
212
1.24k
      switch(MI->csh->mode) {
213
0
        default:    // never reach
214
0
          break;
215
366
        case CS_MODE_16:
216
366
          MI->x86opsize = 14;
217
366
          break;
218
328
        case CS_MODE_32:
219
878
        case CS_MODE_64:
220
878
          MI->x86opsize = 28;
221
878
          break;
222
1.24k
      }
223
1.24k
      break;
224
6.13k
  }
225
226
6.13k
  printMemReference(MI, OpNo, O);
227
6.13k
}
228
229
static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O)
230
6.37k
{
231
  // TODO: fix COMISD in Tablegen instead (#1456)
232
6.37k
  if (MI->op1_size == 16) {
233
    // printf("printf64mem id = %u\n", MCInst_getOpcode(MI));
234
3.34k
    switch(MCInst_getOpcode(MI)) {
235
2.95k
      default:
236
2.95k
        SStream_concat0(O, "qword ptr ");
237
2.95k
        MI->x86opsize = 8;
238
2.95k
        break;
239
0
      case X86_MOVPQI2QImr:
240
391
      case X86_COMISDrm:
241
391
        SStream_concat0(O, "xmmword ptr ");
242
391
        MI->x86opsize = 16;
243
391
        break;
244
3.34k
    }
245
3.34k
  } else {
246
3.03k
    SStream_concat0(O, "qword ptr ");
247
3.03k
    MI->x86opsize = 8;
248
3.03k
  }
249
250
6.37k
  printMemReference(MI, OpNo, O);
251
6.37k
}
252
253
static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O)
254
792
{
255
792
  switch(MCInst_getOpcode(MI)) {
256
262
    default:
257
262
      SStream_concat0(O, "xword ptr ");
258
262
      break;
259
407
    case X86_FBLDm:
260
530
    case X86_FBSTPm:
261
530
      break;
262
792
  }
263
264
792
  MI->x86opsize = 10;
265
792
  printMemReference(MI, OpNo, O);
266
792
}
267
268
static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O)
269
4.92k
{
270
4.92k
  SStream_concat0(O, "xmmword ptr ");
271
4.92k
  MI->x86opsize = 16;
272
4.92k
  printMemReference(MI, OpNo, O);
273
4.92k
}
274
275
static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O)
276
3.05k
{
277
3.05k
  SStream_concat0(O, "ymmword ptr ");
278
3.05k
  MI->x86opsize = 32;
279
3.05k
  printMemReference(MI, OpNo, O);
280
3.05k
}
281
282
static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O)
283
2.22k
{
284
2.22k
  SStream_concat0(O, "zmmword ptr ");
285
2.22k
  MI->x86opsize = 64;
286
2.22k
  printMemReference(MI, OpNo, O);
287
2.22k
}
288
#endif
289
290
static const char *getRegisterName(unsigned RegNo);
291
static void printRegName(SStream *OS, unsigned RegNo)
292
838k
{
293
838k
  SStream_concat0(OS, getRegisterName(RegNo));
294
838k
}
295
296
// for MASM syntax, 0x123 = 123h, 0xA123 = 0A123h
297
// this function tell us if we need to have prefix 0 in front of a number
298
static bool need_zero_prefix(uint64_t imm)
299
0
{
300
  // find the first hex letter representing imm
301
0
  while(imm >= 0x10)
302
0
    imm >>= 4;
303
304
0
  if (imm < 0xa)
305
0
    return false;
306
0
  else  // this need 0 prefix
307
0
    return true;
308
0
}
309
310
static void printImm(MCInst *MI, SStream *O, int64_t imm, bool positive)
311
220k
{
312
220k
  if (positive) {
313
    // always print this number in positive form
314
186k
    if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) {
315
0
      if (imm < 0) {
316
0
        if (MI->op1_size) {
317
0
          switch(MI->op1_size) {
318
0
            default:
319
0
              break;
320
0
            case 1:
321
0
              imm &= 0xff;
322
0
              break;
323
0
            case 2:
324
0
              imm &= 0xffff;
325
0
              break;
326
0
            case 4:
327
0
              imm &= 0xffffffff;
328
0
              break;
329
0
          }
330
0
        }
331
332
0
        if (imm == 0x8000000000000000LL)  // imm == -imm
333
0
          SStream_concat0(O, "8000000000000000h");
334
0
        else if (need_zero_prefix(imm))
335
0
          SStream_concat(O, "0%"PRIx64"h", imm);
336
0
        else
337
0
          SStream_concat(O, "%"PRIx64"h", imm);
338
0
      } else {
339
0
        if (imm > HEX_THRESHOLD) {
340
0
          if (need_zero_prefix(imm))
341
0
            SStream_concat(O, "0%"PRIx64"h", imm);
342
0
          else
343
0
            SStream_concat(O, "%"PRIx64"h", imm);
344
0
        } else
345
0
          SStream_concat(O, "%"PRIu64, imm);
346
0
      }
347
186k
    } else { // Intel syntax
348
186k
      if (imm < 0) {
349
2.40k
        if (MI->op1_size) {
350
564
          switch(MI->op1_size) {
351
564
            default:
352
564
              break;
353
564
            case 1:
354
0
              imm &= 0xff;
355
0
              break;
356
0
            case 2:
357
0
              imm &= 0xffff;
358
0
              break;
359
0
            case 4:
360
0
              imm &= 0xffffffff;
361
0
              break;
362
564
          }
363
564
        }
364
365
2.40k
        SStream_concat(O, "0x%"PRIx64, imm);
366
183k
      } else {
367
183k
        if (imm > HEX_THRESHOLD)
368
170k
          SStream_concat(O, "0x%"PRIx64, imm);
369
13.2k
        else
370
13.2k
          SStream_concat(O, "%"PRIu64, imm);
371
183k
      }
372
186k
    }
373
186k
  } else {
374
33.9k
    if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) {
375
0
      if (imm < 0) {
376
0
        if (imm == 0x8000000000000000LL)  // imm == -imm
377
0
          SStream_concat0(O, "8000000000000000h");
378
0
        else if (imm < -HEX_THRESHOLD) {
379
0
          if (need_zero_prefix(imm))
380
0
            SStream_concat(O, "-0%"PRIx64"h", -imm);
381
0
          else
382
0
            SStream_concat(O, "-%"PRIx64"h", -imm);
383
0
        } else
384
0
          SStream_concat(O, "-%"PRIu64, -imm);
385
0
      } else {
386
0
        if (imm > HEX_THRESHOLD) {
387
0
          if (need_zero_prefix(imm))
388
0
            SStream_concat(O, "0%"PRIx64"h", imm);
389
0
          else
390
0
            SStream_concat(O, "%"PRIx64"h", imm);
391
0
        } else
392
0
          SStream_concat(O, "%"PRIu64, imm);
393
0
      }
394
33.9k
    } else { // Intel syntax
395
33.9k
      if (imm < 0) {
396
3.98k
        if (imm == 0x8000000000000000LL)  // imm == -imm
397
0
          SStream_concat0(O, "0x8000000000000000");
398
3.98k
        else if (imm < -HEX_THRESHOLD)
399
3.31k
          SStream_concat(O, "-0x%"PRIx64, -imm);
400
664
        else
401
664
          SStream_concat(O, "-%"PRIu64, -imm);
402
403
29.9k
      } else {
404
29.9k
        if (imm > HEX_THRESHOLD)
405
25.6k
          SStream_concat(O, "0x%"PRIx64, imm);
406
4.31k
        else
407
4.31k
          SStream_concat(O, "%"PRIu64, imm);
408
29.9k
      }
409
33.9k
    }
410
33.9k
  }
411
220k
}
412
413
// local printOperand, without updating public operands
414
static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
415
310k
{
416
310k
  MCOperand *Op  = MCInst_getOperand(MI, OpNo);
417
310k
  if (MCOperand_isReg(Op)) {
418
310k
    printRegName(O, MCOperand_getReg(Op));
419
310k
  } else if (MCOperand_isImm(Op)) {
420
0
    int64_t imm = MCOperand_getImm(Op);
421
0
    printImm(MI, O, imm, MI->csh->imm_unsigned);
422
0
  }
423
310k
}
424
425
#ifndef CAPSTONE_DIET
426
// copy & normalize access info
427
static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
428
1.52M
{
429
1.52M
#ifndef CAPSTONE_DIET
430
1.52M
  uint8_t i;
431
1.52M
  const uint8_t *arr = X86_get_op_access(h, id, eflags);
432
433
1.52M
  if (!arr) {
434
0
    access[0] = 0;
435
0
    return;
436
0
  }
437
438
  // copy to access but zero out CS_AC_IGNORE
439
4.35M
  for(i = 0; arr[i]; i++) {
440
2.83M
    if (arr[i] != CS_AC_IGNORE)
441
2.39M
      access[i] = arr[i];
442
434k
    else
443
434k
      access[i] = 0;
444
2.83M
  }
445
446
  // mark the end of array
447
1.52M
  access[i] = 0;
448
1.52M
#endif
449
1.52M
}
450
#endif
451
452
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
453
25.5k
{
454
25.5k
  MCOperand *SegReg;
455
25.5k
  int reg;
456
457
25.5k
  if (MI->csh->detail_opt) {
458
25.5k
#ifndef CAPSTONE_DIET
459
25.5k
    uint8_t access[6];
460
25.5k
#endif
461
462
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
463
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
464
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
465
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
466
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
467
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
468
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
469
470
25.5k
#ifndef CAPSTONE_DIET
471
25.5k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
472
25.5k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
473
25.5k
#endif
474
25.5k
  }
475
476
25.5k
  SegReg = MCInst_getOperand(MI, Op + 1);
477
25.5k
  reg = MCOperand_getReg(SegReg);
478
479
  // If this has a segment register, print it.
480
25.5k
  if (reg) {
481
1.22k
    _printOperand(MI, Op + 1, O);
482
1.22k
    if (MI->csh->detail_opt) {
483
1.22k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
484
1.22k
    }
485
1.22k
    SStream_concat0(O, ":");
486
1.22k
  }
487
488
25.5k
  SStream_concat0(O, "[");
489
25.5k
  set_mem_access(MI, true);
490
25.5k
  printOperand(MI, Op, O);
491
25.5k
  SStream_concat0(O, "]");
492
25.5k
  set_mem_access(MI, false);
493
25.5k
}
494
495
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
496
36.1k
{
497
36.1k
  if (MI->csh->detail_opt) {
498
36.1k
#ifndef CAPSTONE_DIET
499
36.1k
    uint8_t access[6];
500
36.1k
#endif
501
502
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
503
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
504
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
505
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
506
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
507
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
508
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
509
510
36.1k
#ifndef CAPSTONE_DIET
511
36.1k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
512
36.1k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
513
36.1k
#endif
514
36.1k
  }
515
516
  // DI accesses are always ES-based on non-64bit mode
517
36.1k
  if (MI->csh->mode != CS_MODE_64) {
518
22.5k
    SStream_concat0(O, "es:[");
519
22.5k
    if (MI->csh->detail_opt) {
520
22.5k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
521
22.5k
    }
522
22.5k
  } else
523
13.6k
    SStream_concat0(O, "[");
524
525
36.1k
  set_mem_access(MI, true);
526
36.1k
  printOperand(MI, Op, O);
527
36.1k
  SStream_concat0(O, "]");
528
36.1k
  set_mem_access(MI, false);
529
36.1k
}
530
531
static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O)
532
9.92k
{
533
9.92k
  SStream_concat0(O, "byte ptr ");
534
9.92k
  MI->x86opsize = 1;
535
9.92k
  printSrcIdx(MI, OpNo, O);
536
9.92k
}
537
538
static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O)
539
3.91k
{
540
3.91k
  SStream_concat0(O, "word ptr ");
541
3.91k
  MI->x86opsize = 2;
542
3.91k
  printSrcIdx(MI, OpNo, O);
543
3.91k
}
544
545
static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O)
546
9.55k
{
547
9.55k
  SStream_concat0(O, "dword ptr ");
548
9.55k
  MI->x86opsize = 4;
549
9.55k
  printSrcIdx(MI, OpNo, O);
550
9.55k
}
551
552
static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O)
553
2.18k
{
554
2.18k
  SStream_concat0(O, "qword ptr ");
555
2.18k
  MI->x86opsize = 8;
556
2.18k
  printSrcIdx(MI, OpNo, O);
557
2.18k
}
558
559
static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O)
560
14.7k
{
561
14.7k
  SStream_concat0(O, "byte ptr ");
562
14.7k
  MI->x86opsize = 1;
563
14.7k
  printDstIdx(MI, OpNo, O);
564
14.7k
}
565
566
static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O)
567
4.87k
{
568
4.87k
  SStream_concat0(O, "word ptr ");
569
4.87k
  MI->x86opsize = 2;
570
4.87k
  printDstIdx(MI, OpNo, O);
571
4.87k
}
572
573
static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O)
574
13.4k
{
575
13.4k
  SStream_concat0(O, "dword ptr ");
576
13.4k
  MI->x86opsize = 4;
577
13.4k
  printDstIdx(MI, OpNo, O);
578
13.4k
}
579
580
static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O)
581
3.14k
{
582
3.14k
  SStream_concat0(O, "qword ptr ");
583
3.14k
  MI->x86opsize = 8;
584
3.14k
  printDstIdx(MI, OpNo, O);
585
3.14k
}
586
587
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
588
5.34k
{
589
5.34k
  MCOperand *DispSpec = MCInst_getOperand(MI, Op);
590
5.34k
  MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
591
5.34k
  int reg;
592
593
5.34k
  if (MI->csh->detail_opt) {
594
5.34k
#ifndef CAPSTONE_DIET
595
5.34k
    uint8_t access[6];
596
5.34k
#endif
597
598
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
599
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
600
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
601
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
602
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
603
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
604
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
605
606
5.34k
#ifndef CAPSTONE_DIET
607
5.34k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
608
5.34k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
609
5.34k
#endif
610
5.34k
  }
611
612
  // If this has a segment register, print it.
613
5.34k
  reg = MCOperand_getReg(SegReg);
614
5.34k
  if (reg) {
615
249
    _printOperand(MI, Op + 1, O);
616
249
    SStream_concat0(O, ":");
617
249
    if (MI->csh->detail_opt) {
618
249
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
619
249
    }
620
249
  }
621
622
5.34k
  SStream_concat0(O, "[");
623
624
5.34k
  if (MCOperand_isImm(DispSpec)) {
625
5.34k
    int64_t imm = MCOperand_getImm(DispSpec);
626
5.34k
    if (MI->csh->detail_opt)
627
5.34k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
628
629
5.34k
    if (imm < 0)
630
686
      printImm(MI, O, arch_masks[MI->csh->mode] & imm, true);
631
4.65k
    else
632
4.65k
      printImm(MI, O, imm, true);
633
5.34k
  }
634
635
5.34k
  SStream_concat0(O, "]");
636
637
5.34k
  if (MI->csh->detail_opt)
638
5.34k
    MI->flat_insn->detail->x86.op_count++;
639
640
5.34k
  if (MI->op1_size == 0)
641
5.34k
    MI->op1_size = MI->x86opsize;
642
5.34k
}
643
644
static void printU8Imm(MCInst *MI, unsigned Op, SStream *O)
645
30.2k
{
646
30.2k
  uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff;
647
648
30.2k
  printImm(MI, O, val, true);
649
650
30.2k
  if (MI->csh->detail_opt) {
651
30.2k
#ifndef CAPSTONE_DIET
652
30.2k
    uint8_t access[6];
653
30.2k
#endif
654
655
30.2k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
656
30.2k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val;
657
30.2k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1;
658
659
30.2k
#ifndef CAPSTONE_DIET
660
30.2k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
661
30.2k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
662
30.2k
#endif
663
664
30.2k
    MI->flat_insn->detail->x86.op_count++;
665
30.2k
  }
666
30.2k
}
667
668
static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O)
669
2.85k
{
670
2.85k
  SStream_concat0(O, "byte ptr ");
671
2.85k
  MI->x86opsize = 1;
672
2.85k
  printMemOffset(MI, OpNo, O);
673
2.85k
}
674
675
static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O)
676
877
{
677
877
  SStream_concat0(O, "word ptr ");
678
877
  MI->x86opsize = 2;
679
877
  printMemOffset(MI, OpNo, O);
680
877
}
681
682
static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O)
683
1.29k
{
684
1.29k
  SStream_concat0(O, "dword ptr ");
685
1.29k
  MI->x86opsize = 4;
686
1.29k
  printMemOffset(MI, OpNo, O);
687
1.29k
}
688
689
static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O)
690
319
{
691
319
  SStream_concat0(O, "qword ptr ");
692
319
  MI->x86opsize = 8;
693
319
  printMemOffset(MI, OpNo, O);
694
319
}
695
696
static void printInstruction(MCInst *MI, SStream *O);
697
698
void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
699
593k
{
700
593k
  x86_reg reg, reg2;
701
593k
  enum cs_ac_type access1, access2;
702
703
  // printf("opcode = %u\n", MCInst_getOpcode(MI));
704
705
  // perhaps this instruction does not need printer
706
593k
  if (MI->assembly[0]) {
707
0
    strncpy(O->buffer, MI->assembly, sizeof(O->buffer));
708
0
    return;
709
0
  }
710
711
593k
  X86_lockrep(MI, O);
712
593k
  printInstruction(MI, O);
713
714
593k
  reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1);
715
593k
  if (MI->csh->detail_opt) {
716
593k
#ifndef CAPSTONE_DIET
717
593k
    uint8_t access[6] = {0};
718
593k
#endif
719
720
    // first op can be embedded in the asm by llvm.
721
    // so we have to add the missing register as the first operand
722
593k
    if (reg) {
723
      // shift all the ops right to leave 1st slot for this new register op
724
56.1k
      memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]),
725
56.1k
          sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1));
726
56.1k
      MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG;
727
56.1k
      MI->flat_insn->detail->x86.operands[0].reg = reg;
728
56.1k
      MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg];
729
56.1k
      MI->flat_insn->detail->x86.operands[0].access = access1;
730
56.1k
      MI->flat_insn->detail->x86.op_count++;
731
537k
    } else {
732
537k
      if (X86_insn_reg_intel2(MCInst_getOpcode(MI), &reg, &access1, &reg2, &access2)) {
733
8.48k
        MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG;
734
8.48k
        MI->flat_insn->detail->x86.operands[0].reg = reg;
735
8.48k
        MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg];
736
8.48k
        MI->flat_insn->detail->x86.operands[0].access = access1;
737
8.48k
        MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG;
738
8.48k
        MI->flat_insn->detail->x86.operands[1].reg = reg2;
739
8.48k
        MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2];
740
8.48k
        MI->flat_insn->detail->x86.operands[1].access = access2;
741
8.48k
        MI->flat_insn->detail->x86.op_count = 2;
742
8.48k
      }
743
537k
    }
744
745
593k
#ifndef CAPSTONE_DIET
746
593k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
747
593k
    MI->flat_insn->detail->x86.operands[0].access = access[0];
748
593k
    MI->flat_insn->detail->x86.operands[1].access = access[1];
749
593k
#endif
750
593k
  }
751
752
593k
  if (MI->op1_size == 0 && reg)
753
40.8k
    MI->op1_size = MI->csh->regsize_map[reg];
754
593k
}
755
756
/// printPCRelImm - This is used to print an immediate value that ends up
757
/// being encoded as a pc-relative value.
758
static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
759
40.5k
{
760
40.5k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
761
40.5k
  if (MCOperand_isImm(Op)) {
762
40.5k
    int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address;
763
40.5k
    uint8_t opsize = X86_immediate_size(MI->Opcode, NULL);
764
765
    // truncat imm for non-64bit
766
40.5k
    if (MI->csh->mode != CS_MODE_64) {
767
26.1k
      imm = imm & 0xffffffff;
768
26.1k
    }
769
770
40.5k
    printImm(MI, O, imm, true);
771
772
40.5k
    if (MI->csh->detail_opt) {
773
40.5k
#ifndef CAPSTONE_DIET
774
40.5k
      uint8_t access[6];
775
40.5k
#endif
776
777
40.5k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
778
      // if op_count > 0, then this operand's size is taken from the destination op
779
40.5k
      if (MI->flat_insn->detail->x86.op_count > 0)
780
0
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
781
40.5k
      else if (opsize > 0)
782
1.41k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
783
39.0k
      else
784
39.0k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
785
40.5k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
786
787
40.5k
#ifndef CAPSTONE_DIET
788
40.5k
      get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
789
40.5k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
790
40.5k
#endif
791
792
40.5k
      MI->flat_insn->detail->x86.op_count++;
793
40.5k
    }
794
795
40.5k
    if (MI->op1_size == 0)
796
40.5k
      MI->op1_size = MI->imm_size;
797
40.5k
  }
798
40.5k
}
799
800
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
801
599k
{
802
599k
  MCOperand *Op  = MCInst_getOperand(MI, OpNo);
803
804
599k
  if (MCOperand_isReg(Op)) {
805
528k
    unsigned int reg = MCOperand_getReg(Op);
806
807
528k
    printRegName(O, reg);
808
528k
    if (MI->csh->detail_opt) {
809
528k
      if (MI->csh->doing_mem) {
810
61.7k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg);
811
466k
      } else {
812
466k
#ifndef CAPSTONE_DIET
813
466k
        uint8_t access[6];
814
466k
#endif
815
816
466k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
817
466k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg);
818
466k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)];
819
820
466k
#ifndef CAPSTONE_DIET
821
466k
        get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
822
466k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
823
466k
#endif
824
825
466k
        MI->flat_insn->detail->x86.op_count++;
826
466k
      }
827
528k
    }
828
829
528k
    if (MI->op1_size == 0)
830
261k
      MI->op1_size = MI->csh->regsize_map[X86_register_map(reg)];
831
528k
  } else if (MCOperand_isImm(Op)) {
832
70.8k
    uint8_t encsize;
833
70.8k
    int64_t imm = MCOperand_getImm(Op);
834
70.8k
    uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize);
835
836
70.8k
    if (opsize == 1)    // print 1 byte immediate in positive form
837
30.7k
      imm = imm & 0xff;
838
839
    // printf(">>> id = %u\n", MI->flat_insn->id);
840
70.8k
    switch(MI->flat_insn->id) {
841
33.9k
      default:
842
33.9k
        printImm(MI, O, imm, MI->csh->imm_unsigned);
843
33.9k
        break;
844
845
303
      case X86_INS_MOVABS:
846
9.63k
      case X86_INS_MOV:
847
        // do not print number in negative form
848
9.63k
        printImm(MI, O, imm, true);
849
9.63k
        break;
850
851
0
      case X86_INS_IN:
852
0
      case X86_INS_OUT:
853
0
      case X86_INS_INT:
854
        // do not print number in negative form
855
0
        imm = imm & 0xff;
856
0
        printImm(MI, O, imm, true);
857
0
        break;
858
859
800
      case X86_INS_LCALL:
860
2.34k
      case X86_INS_LJMP:
861
2.34k
      case X86_INS_JMP:
862
        // always print address in positive form
863
2.34k
        if (OpNo == 1) { // ptr16 part
864
1.17k
          imm = imm & 0xffff;
865
1.17k
          opsize = 2;
866
1.17k
        } else
867
1.17k
          opsize = 4;
868
2.34k
        printImm(MI, O, imm, true);
869
2.34k
        break;
870
871
6.80k
      case X86_INS_AND:
872
12.9k
      case X86_INS_OR:
873
17.0k
      case X86_INS_XOR:
874
        // do not print number in negative form
875
17.0k
        if (imm >= 0 && imm <= HEX_THRESHOLD)
876
2.58k
          printImm(MI, O, imm, true);
877
14.4k
        else {
878
14.4k
          imm = arch_masks[opsize? opsize : MI->imm_size] & imm;
879
14.4k
          printImm(MI, O, imm, true);
880
14.4k
        }
881
17.0k
        break;
882
883
6.40k
      case X86_INS_RET:
884
7.93k
      case X86_INS_RETF:
885
        // RET imm16
886
7.93k
        if (imm >= 0 && imm <= HEX_THRESHOLD)
887
780
          printImm(MI, O, imm, true);
888
7.15k
        else {
889
7.15k
          imm = 0xffff & imm;
890
7.15k
          printImm(MI, O, imm, true);
891
7.15k
        }
892
7.93k
        break;
893
70.8k
    }
894
895
70.8k
    if (MI->csh->detail_opt) {
896
70.8k
      if (MI->csh->doing_mem) {
897
0
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
898
70.8k
      } else {
899
70.8k
#ifndef CAPSTONE_DIET
900
70.8k
        uint8_t access[6];
901
70.8k
#endif
902
903
70.8k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
904
70.8k
        if (opsize > 0) {
905
58.5k
          MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
906
58.5k
          MI->flat_insn->detail->x86.encoding.imm_size = encsize;
907
58.5k
        } else if (MI->flat_insn->detail->x86.op_count > 0) {
908
3.10k
          if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) {
909
3.10k
            MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size =
910
3.10k
              MI->flat_insn->detail->x86.operands[0].size;
911
3.10k
          } else
912
0
            MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
913
3.10k
        } else
914
9.22k
          MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
915
70.8k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
916
917
70.8k
#ifndef CAPSTONE_DIET
918
70.8k
        get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
919
70.8k
        MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
920
70.8k
#endif
921
922
70.8k
        MI->flat_insn->detail->x86.op_count++;
923
70.8k
      }
924
70.8k
    }
925
70.8k
  }
926
599k
}
927
928
static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
929
252k
{
930
252k
  bool NeedPlus = false;
931
252k
  MCOperand *BaseReg  = MCInst_getOperand(MI, Op + X86_AddrBaseReg);
932
252k
  uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt));
933
252k
  MCOperand *IndexReg  = MCInst_getOperand(MI, Op + X86_AddrIndexReg);
934
252k
  MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp);
935
252k
  MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg);
936
252k
  int reg;
937
938
252k
  if (MI->csh->detail_opt) {
939
252k
#ifndef CAPSTONE_DIET
940
252k
    uint8_t access[6];
941
252k
#endif
942
943
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
944
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
945
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
946
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg));
947
252k
        if (MCOperand_getReg(IndexReg) != X86_EIZ) {
948
250k
            MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg));
949
250k
        }
950
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal;
951
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
952
953
252k
#ifndef CAPSTONE_DIET
954
252k
    get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
955
252k
    MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
956
252k
#endif
957
252k
  }
958
959
  // If this has a segment register, print it.
960
252k
  reg = MCOperand_getReg(SegReg);
961
252k
  if (reg) {
962
7.12k
    _printOperand(MI, Op + X86_AddrSegmentReg, O);
963
7.12k
    if (MI->csh->detail_opt) {
964
7.12k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg);
965
7.12k
    }
966
7.12k
    SStream_concat0(O, ":");
967
7.12k
  }
968
969
252k
  SStream_concat0(O, "[");
970
971
252k
  if (MCOperand_getReg(BaseReg)) {
972
246k
    _printOperand(MI, Op + X86_AddrBaseReg, O);
973
246k
    NeedPlus = true;
974
246k
  }
975
976
252k
  if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) {
977
54.9k
    if (NeedPlus) SStream_concat0(O, " + ");
978
54.9k
    _printOperand(MI, Op + X86_AddrIndexReg, O);
979
54.9k
    if (ScaleVal != 1)
980
7.76k
      SStream_concat(O, "*%u", ScaleVal);
981
54.9k
    NeedPlus = true;
982
54.9k
  }
983
984
252k
  if (MCOperand_isImm(DispSpec)) {
985
252k
    int64_t DispVal = MCOperand_getImm(DispSpec);
986
252k
    if (MI->csh->detail_opt)
987
252k
      MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
988
252k
    if (DispVal) {
989
73.1k
      if (NeedPlus) {
990
69.0k
        if (DispVal < 0) {
991
26.8k
          SStream_concat0(O, " - ");
992
26.8k
          printImm(MI, O, -DispVal, true);
993
42.2k
        } else {
994
42.2k
          SStream_concat0(O, " + ");
995
42.2k
          printImm(MI, O, DispVal, true);
996
42.2k
        }
997
69.0k
      } else {
998
        // memory reference to an immediate address
999
4.08k
        if (MI->csh->mode == CS_MODE_64)
1000
182
          MI->op1_size = 8;
1001
4.08k
        if (DispVal < 0) {
1002
1.58k
          printImm(MI, O, arch_masks[MI->csh->mode] & DispVal, true);
1003
2.50k
        } else {
1004
2.50k
          printImm(MI, O, DispVal, true);
1005
2.50k
        }
1006
4.08k
      }
1007
1008
178k
    } else {
1009
      // DispVal = 0
1010
178k
      if (!NeedPlus)  // [0]
1011
405
        SStream_concat0(O, "0");
1012
178k
    }
1013
252k
  }
1014
1015
252k
  SStream_concat0(O, "]");
1016
1017
252k
  if (MI->csh->detail_opt)
1018
252k
    MI->flat_insn->detail->x86.op_count++;
1019
1020
252k
  if (MI->op1_size == 0)
1021
171k
    MI->op1_size = MI->x86opsize;
1022
252k
}
1023
1024
static void printanymem(MCInst *MI, unsigned OpNo, SStream *O)
1025
5.15k
{
1026
5.15k
  switch(MI->Opcode) {
1027
223
    default: break;
1028
561
    case X86_LEA16r:
1029
561
         MI->x86opsize = 2;
1030
561
         break;
1031
574
    case X86_LEA32r:
1032
1.02k
    case X86_LEA64_32r:
1033
1.02k
         MI->x86opsize = 4;
1034
1.02k
         break;
1035
435
    case X86_LEA64r:
1036
435
         MI->x86opsize = 8;
1037
435
         break;
1038
236
    case X86_BNDCL32rm:
1039
606
    case X86_BNDCN32rm:
1040
1.03k
    case X86_BNDCU32rm:
1041
1.60k
    case X86_BNDSTXmr:
1042
2.02k
    case X86_BNDLDXrm:
1043
2.24k
    case X86_BNDCL64rm:
1044
2.54k
    case X86_BNDCN64rm:
1045
2.91k
    case X86_BNDCU64rm:
1046
2.91k
         MI->x86opsize = 16;
1047
2.91k
         break;
1048
5.15k
  }
1049
1050
5.15k
  printMemReference(MI, OpNo, O);
1051
5.15k
}
1052
1053
#ifdef CAPSTONE_X86_REDUCE
1054
#include "X86GenAsmWriter1_reduce.inc"
1055
#else
1056
#include "X86GenAsmWriter1.inc"
1057
#endif
1058
1059
#include "X86GenRegisterName1.inc"
1060
1061
#endif