Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/AArch64/AArch64InstPrinter.c
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Count
Source (jump to first uncovered line)
1
//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an AArch64 MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
16
17
#ifdef CAPSTONE_HAS_ARM64
18
19
#include <capstone/platform.h>
20
#include <stdio.h>
21
#include <stdlib.h>
22
23
#include "AArch64InstPrinter.h"
24
#include "AArch64Disassembler.h"
25
#include "AArch64BaseInfo.h"
26
#include "../../utils.h"
27
#include "../../MCInst.h"
28
#include "../../SStream.h"
29
#include "../../MCRegisterInfo.h"
30
#include "../../MathExtras.h"
31
32
#include "AArch64Mapping.h"
33
#include "AArch64AddressingModes.h"
34
35
#define GET_REGINFO_ENUM
36
#include "AArch64GenRegisterInfo.inc"
37
38
#define GET_INSTRINFO_ENUM
39
#include "AArch64GenInstrInfo.inc"
40
41
#include "AArch64GenSubtargetInfo.inc"
42
43
44
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
45
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
46
static bool printSysAlias(MCInst *MI, SStream *O);
47
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
48
static void printInstruction(MCInst *MI, SStream *O);
49
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
50
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
51
    unsigned PrintMethodIdx, SStream *OS);
52
53
54
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
55
1.25M
{
56
1.25M
#ifndef CAPSTONE_DIET
57
1.25M
  const uint8_t *arr = AArch64_get_op_access(h, id);
58
59
1.25M
  if (arr[index] == CS_AC_IGNORE)
60
0
    return 0;
61
62
1.25M
  return arr[index];
63
#else
64
  return 0;
65
#endif
66
1.25M
}
67
68
static void op_addImm(MCInst *MI, int v)
69
3.24k
{
70
3.24k
  if (MI->csh->detail) {
71
3.24k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
72
3.24k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v;
73
3.24k
    MI->flat_insn->detail->arm64.op_count++;
74
3.24k
  }
75
3.24k
}
76
77
static void set_sme_index(MCInst *MI, bool status)
78
13.8k
{
79
  // Doing SME Index operand
80
13.8k
  MI->csh->doing_SME_Index = status;
81
82
13.8k
  if (MI->csh->detail != CS_OPT_ON)
83
0
    return;
84
85
13.8k
  if (status) {
86
10.3k
    unsigned prevOpNum = MI->flat_insn->detail->arm64.op_count - 1; 
87
10.3k
    unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, prevOpNum));
88
    // Replace previous SME register operand with an OP_SME_INDEX operand
89
10.3k
    MI->flat_insn->detail->arm64.operands[prevOpNum].type = ARM64_OP_SME_INDEX;
90
10.3k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.reg = Reg;
91
10.3k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.base = ARM64_REG_INVALID;
92
10.3k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.disp = 0;
93
10.3k
  }
94
13.8k
}
95
96
static void set_mem_access(MCInst *MI, bool status)
97
425k
{
98
  // If status == false, check if this is meant for SME_index
99
425k
  if(!status && MI->csh->doing_SME_Index) {
100
6.76k
    MI->csh->doing_SME_Index = status;
101
6.76k
    return;
102
6.76k
  }
103
104
  // Doing Memory Operation
105
418k
  MI->csh->doing_mem = status;
106
107
108
418k
  if (MI->csh->detail != CS_OPT_ON)
109
0
    return;
110
111
418k
  if (status) {
112
209k
#ifndef CAPSTONE_DIET
113
209k
    uint8_t access;
114
209k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
115
209k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
116
209k
    MI->ac_idx++;
117
209k
#endif
118
209k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
119
209k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
120
209k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
121
209k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
122
209k
  } else {
123
    // done, create the next operand slot
124
209k
    MI->flat_insn->detail->arm64.op_count++;
125
209k
  }
126
418k
}
127
128
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
129
443k
{
130
  // Check for special encodings and print the canonical alias instead.
131
443k
  unsigned Opcode = MCInst_getOpcode(MI);
132
443k
  int LSB, Width;
133
443k
  char *mnem;
134
135
  // printf(">>> opcode = %u\n", MCInst_getOpcode(MI));
136
137
443k
  if (Opcode == AArch64_SYSxt && printSysAlias(MI, O))
138
1.19k
    return;
139
140
  // SBFM/UBFM should print to a nicer aliased form if possible.
141
442k
  if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri ||
142
442k
      Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) {
143
9.50k
    bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri);
144
9.50k
    bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
145
146
9.50k
    MCOperand *Op0 = MCInst_getOperand(MI, 0);
147
9.50k
    MCOperand *Op1 = MCInst_getOperand(MI, 1);
148
9.50k
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
149
9.50k
    MCOperand *Op3 = MCInst_getOperand(MI, 3);
150
151
9.50k
    if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
152
8.37k
      const char *AsmMnemonic = NULL;
153
154
8.37k
      switch (MCOperand_getImm(Op3)) {
155
2.31k
        default:
156
2.31k
          break;
157
158
2.31k
        case 7:
159
1.79k
          if (IsSigned)
160
1.70k
            AsmMnemonic = "sxtb";
161
87
          else if (!Is64Bit)
162
69
            AsmMnemonic = "uxtb";
163
1.79k
          break;
164
165
3.85k
        case 15:
166
3.85k
          if (IsSigned)
167
3.07k
            AsmMnemonic = "sxth";
168
786
          else if (!Is64Bit)
169
484
            AsmMnemonic = "uxth";
170
3.85k
          break;
171
172
412
        case 31:
173
          // *xtw is only valid for signed 64-bit operations.
174
412
          if (Is64Bit && IsSigned)
175
247
            AsmMnemonic = "sxtw";
176
412
          break;
177
8.37k
      }
178
179
8.37k
      if (AsmMnemonic) {
180
5.57k
        SStream_concat(O, "%s\t%s, %s", AsmMnemonic,
181
5.57k
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
182
5.57k
            getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));
183
184
5.57k
        if (MI->csh->detail) {
185
5.57k
#ifndef CAPSTONE_DIET
186
5.57k
          uint8_t access;
187
5.57k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
188
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
189
5.57k
          MI->ac_idx++;
190
5.57k
#endif
191
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
192
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
193
5.57k
          MI->flat_insn->detail->arm64.op_count++;
194
5.57k
#ifndef CAPSTONE_DIET
195
5.57k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
196
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
197
5.57k
          MI->ac_idx++;
198
5.57k
#endif
199
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
200
5.57k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1));
201
5.57k
          MI->flat_insn->detail->arm64.op_count++;
202
5.57k
        }
203
204
5.57k
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
205
206
5.57k
        return;
207
5.57k
      }
208
8.37k
    }
209
210
    // All immediate shifts are aliases, implemented using the Bitfield
211
    // instruction. In all cases the immediate shift amount shift must be in
212
    // the range 0 to (reg.size -1).
213
3.93k
    if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
214
3.93k
      const char *AsmMnemonic = NULL;
215
3.93k
      int shift = 0;
216
3.93k
      int immr = (int)MCOperand_getImm(Op2);
217
3.93k
      int imms = (int)MCOperand_getImm(Op3);
218
219
3.93k
      if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
220
33
        AsmMnemonic = "lsl";
221
33
        shift = 31 - imms;
222
3.89k
      } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
223
3.89k
          ((imms + 1 == immr))) {
224
18
        AsmMnemonic = "lsl";
225
18
        shift = 63 - imms;
226
3.87k
      } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
227
50
        AsmMnemonic = "lsr";
228
50
        shift = immr;
229
3.82k
      } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
230
40
        AsmMnemonic = "lsr";
231
40
        shift = immr;
232
3.78k
      } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) {
233
106
        AsmMnemonic = "asr";
234
106
        shift = immr;
235
3.68k
      } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) {
236
563
        AsmMnemonic = "asr";
237
563
        shift = immr;
238
563
      }
239
240
3.93k
      if (AsmMnemonic) {
241
810
        SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic,
242
810
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
243
810
            getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
244
245
810
        printInt32Bang(O, shift);
246
247
810
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
248
249
810
        if (MI->csh->detail) {
250
810
#ifndef CAPSTONE_DIET
251
810
          uint8_t access;
252
810
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
253
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
254
810
          MI->ac_idx++;
255
810
#endif
256
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
257
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
258
810
          MI->flat_insn->detail->arm64.op_count++;
259
810
#ifndef CAPSTONE_DIET
260
810
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
261
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
262
810
          MI->ac_idx++;
263
810
#endif
264
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
265
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
266
810
          MI->flat_insn->detail->arm64.op_count++;
267
810
#ifndef CAPSTONE_DIET
268
810
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
269
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
270
810
          MI->ac_idx++;
271
810
#endif
272
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
273
810
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift;
274
810
          MI->flat_insn->detail->arm64.op_count++;
275
810
        }
276
277
810
        return;
278
810
      }
279
3.93k
    }
280
281
    // SBFIZ/UBFIZ aliases
282
3.12k
    if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) {
283
638
      SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"),
284
638
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
285
638
          getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
286
287
638
      printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2)));
288
289
638
      SStream_concat0(O, ", ");
290
291
638
      printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1);
292
293
638
      MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));
294
295
638
      if (MI->csh->detail) {
296
638
#ifndef CAPSTONE_DIET
297
638
        uint8_t access;
298
638
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
299
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
300
638
        MI->ac_idx++;
301
638
#endif
302
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
303
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
304
638
        MI->flat_insn->detail->arm64.op_count++;
305
638
#ifndef CAPSTONE_DIET
306
638
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
307
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
308
638
        MI->ac_idx++;
309
638
#endif
310
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
311
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
312
638
        MI->flat_insn->detail->arm64.op_count++;
313
638
#ifndef CAPSTONE_DIET
314
638
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
315
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
316
638
        MI->ac_idx++;
317
638
#endif
318
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
319
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2);
320
638
        MI->flat_insn->detail->arm64.op_count++;
321
638
#ifndef CAPSTONE_DIET
322
638
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
323
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
324
638
        MI->ac_idx++;
325
638
#endif
326
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
327
638
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1;
328
638
        MI->flat_insn->detail->arm64.op_count++;
329
638
      }
330
331
638
      return;
332
638
    }
333
334
    // Otherwise SBFX/UBFX is the preferred form
335
2.48k
    SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"),
336
2.48k
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
337
2.48k
        getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
338
339
2.48k
    printInt32Bang(O, (int)MCOperand_getImm(Op2));
340
2.48k
    SStream_concat0(O, ", ");
341
2.48k
    printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1);
342
343
2.48k
    MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));
344
345
2.48k
    if (MI->csh->detail) {
346
2.48k
#ifndef CAPSTONE_DIET
347
2.48k
      uint8_t access;
348
2.48k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
349
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
350
2.48k
      MI->ac_idx++;
351
2.48k
#endif
352
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
353
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
354
2.48k
      MI->flat_insn->detail->arm64.op_count++;
355
2.48k
#ifndef CAPSTONE_DIET
356
2.48k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
357
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
358
2.48k
      MI->ac_idx++;
359
2.48k
#endif
360
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
361
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
362
2.48k
      MI->flat_insn->detail->arm64.op_count++;
363
2.48k
#ifndef CAPSTONE_DIET
364
2.48k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
365
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
366
2.48k
      MI->ac_idx++;
367
2.48k
#endif
368
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
369
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2);
370
2.48k
      MI->flat_insn->detail->arm64.op_count++;
371
2.48k
#ifndef CAPSTONE_DIET
372
2.48k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
373
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
374
2.48k
      MI->ac_idx++;
375
2.48k
#endif
376
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
377
2.48k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1;
378
2.48k
      MI->flat_insn->detail->arm64.op_count++;
379
2.48k
    }
380
381
2.48k
    return;
382
3.12k
  }
383
384
433k
  if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) {
385
2.99k
    MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0
386
2.99k
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
387
2.99k
    int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3));
388
2.99k
    int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4));
389
390
2.99k
    if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) &&
391
2.99k
        (ImmR == 0 || ImmS < ImmR)) {
392
      // BFC takes precedence over its entire range, sligtly differently to BFI.
393
1.57k
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
394
1.57k
      int LSB = (BitWidth - ImmR) % BitWidth;
395
1.57k
      int Width = ImmS + 1;
396
397
1.57k
      SStream_concat(O, "bfc\t%s, ",
398
1.57k
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName));
399
400
1.57k
      printInt32Bang(O, LSB);
401
1.57k
      SStream_concat0(O, ", ");
402
1.57k
      printInt32Bang(O, Width);
403
1.57k
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfc"));
404
405
1.57k
      if (MI->csh->detail) {
406
1.57k
#ifndef CAPSTONE_DIET
407
1.57k
        uint8_t access;
408
1.57k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
409
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
410
1.57k
        MI->ac_idx++;
411
1.57k
#endif
412
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
413
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
414
1.57k
        MI->flat_insn->detail->arm64.op_count++;
415
416
1.57k
#ifndef CAPSTONE_DIET
417
1.57k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
418
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
419
1.57k
        MI->ac_idx++;
420
1.57k
#endif
421
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
422
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
423
1.57k
        MI->flat_insn->detail->arm64.op_count++;
424
1.57k
#ifndef CAPSTONE_DIET
425
1.57k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
426
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
427
1.57k
        MI->ac_idx++;
428
1.57k
#endif
429
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
430
1.57k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
431
1.57k
        MI->flat_insn->detail->arm64.op_count++;
432
1.57k
      }
433
434
1.57k
      return;
435
1.57k
    } else if (ImmS < ImmR) {
436
      // BFI alias
437
442
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
438
442
      LSB = (BitWidth - ImmR) % BitWidth;
439
442
      Width = ImmS + 1;
440
441
442
      SStream_concat(O, "bfi\t%s, %s, ",
442
442
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
443
442
          getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
444
445
442
      printInt32Bang(O, LSB);
446
442
      SStream_concat0(O, ", ");
447
442
      printInt32Bang(O, Width);
448
449
442
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));
450
451
442
      if (MI->csh->detail) {
452
442
#ifndef CAPSTONE_DIET
453
442
        uint8_t access;
454
442
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
455
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
456
442
        MI->ac_idx++;
457
442
#endif
458
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
459
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
460
442
        MI->flat_insn->detail->arm64.op_count++;
461
442
#ifndef CAPSTONE_DIET
462
442
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
463
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
464
442
        MI->ac_idx++;
465
442
#endif
466
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
467
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
468
442
        MI->flat_insn->detail->arm64.op_count++;
469
442
#ifndef CAPSTONE_DIET
470
442
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
471
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
472
442
        MI->ac_idx++;
473
442
#endif
474
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
475
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
476
442
        MI->flat_insn->detail->arm64.op_count++;
477
442
#ifndef CAPSTONE_DIET
478
442
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
479
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
480
442
        MI->ac_idx++;
481
442
#endif
482
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
483
442
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
484
442
        MI->flat_insn->detail->arm64.op_count++;
485
442
      }
486
487
442
      return;
488
442
    }
489
490
970
    LSB = ImmR;
491
970
    Width = ImmS - ImmR + 1;
492
    // Otherwise BFXIL the preferred form
493
970
    SStream_concat(O, "bfxil\t%s, %s, ",
494
970
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
495
970
        getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
496
497
970
    printInt32Bang(O, LSB);
498
970
    SStream_concat0(O, ", ");
499
970
    printInt32Bang(O, Width);
500
501
970
    MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));
502
503
970
    if (MI->csh->detail) {
504
970
#ifndef CAPSTONE_DIET
505
970
      uint8_t access;
506
970
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
507
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
508
970
      MI->ac_idx++;
509
970
#endif
510
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
511
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
512
970
      MI->flat_insn->detail->arm64.op_count++;
513
970
#ifndef CAPSTONE_DIET
514
970
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
515
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
516
970
      MI->ac_idx++;
517
970
#endif
518
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
519
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
520
970
      MI->flat_insn->detail->arm64.op_count++;
521
970
#ifndef CAPSTONE_DIET
522
970
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
523
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
524
970
      MI->ac_idx++;
525
970
#endif
526
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
527
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
528
970
      MI->flat_insn->detail->arm64.op_count++;
529
970
#ifndef CAPSTONE_DIET
530
970
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
531
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
532
970
      MI->ac_idx++;
533
970
#endif
534
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
535
970
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
536
970
      MI->flat_insn->detail->arm64.op_count++;
537
970
    }
538
539
970
    return;
540
2.99k
  }
541
542
  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
543
  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
544
  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
545
  // that can represent the move is the MOV alias, and the rest get printed
546
  // normally.
547
430k
  if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) &&
548
430k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
549
1.10k
    int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32;
550
1.10k
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
551
1.10k
    uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift;
552
553
1.10k
    if (isMOVZMovAlias(Value, Shift,
554
1.10k
          Opcode == AArch64_MOVZXi ? 64 : 32)) {
555
1.02k
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
556
557
1.02k
      printInt64Bang(O, SignExtend64(Value, RegWidth));
558
559
1.02k
      if (MI->csh->detail) {
560
1.02k
#ifndef CAPSTONE_DIET
561
1.02k
        uint8_t access;
562
1.02k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
563
1.02k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
564
1.02k
        MI->ac_idx++;
565
1.02k
#endif
566
1.02k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
567
1.02k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
568
1.02k
        MI->flat_insn->detail->arm64.op_count++;
569
570
1.02k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
571
1.02k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
572
1.02k
        MI->flat_insn->detail->arm64.op_count++;
573
1.02k
      }
574
575
1.02k
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
576
577
1.02k
      return;
578
1.02k
    }
579
1.10k
  }
580
581
429k
  if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&
582
429k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
583
2.75k
    int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32;
584
2.75k
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
585
2.75k
    uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift);
586
587
2.75k
    if (RegWidth == 32)
588
2.06k
      Value = Value & 0xffffffff;
589
590
2.75k
    if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) {
591
1.16k
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
592
593
1.16k
      printInt64Bang(O, SignExtend64(Value, RegWidth));
594
595
1.16k
      if (MI->csh->detail) {
596
1.16k
#ifndef CAPSTONE_DIET
597
1.16k
        uint8_t access;
598
1.16k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
599
1.16k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
600
1.16k
        MI->ac_idx++;
601
1.16k
#endif
602
1.16k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
603
1.16k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
604
1.16k
        MI->flat_insn->detail->arm64.op_count++;
605
606
1.16k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
607
1.16k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
608
1.16k
        MI->flat_insn->detail->arm64.op_count++;
609
1.16k
      }
610
611
1.16k
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
612
613
1.16k
      return;
614
1.16k
    }
615
2.75k
  }
616
617
428k
  if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) &&
618
428k
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR ||
619
3.74k
       MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) &&
620
428k
      MCOperand_isImm(MCInst_getOperand(MI, 2))) {
621
1.09k
    int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32;
622
1.09k
    uint64_t Value = AArch64_AM_decodeLogicalImmediate(
623
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth);
624
1.09k
    SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
625
626
1.09k
    printInt64Bang(O, SignExtend64(Value, RegWidth));
627
628
1.09k
    if (MI->csh->detail) {
629
1.09k
#ifndef CAPSTONE_DIET
630
1.09k
      uint8_t access;
631
1.09k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
632
1.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
633
1.09k
      MI->ac_idx++;
634
1.09k
#endif
635
1.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
636
1.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
637
1.09k
      MI->flat_insn->detail->arm64.op_count++;
638
639
1.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
640
1.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
641
1.09k
      MI->flat_insn->detail->arm64.op_count++;
642
1.09k
    }
643
644
1.09k
    MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
645
646
1.09k
    return;
647
1.09k
  }
648
649
  // Instruction TSB is specified as a one operand instruction, but 'csync' is
650
  // not encoded, so for printing it is treated as a special case here:
651
426k
  if (Opcode == AArch64_TSB) {
652
16
    SStream_concat0(O, "tsb\tcsync");
653
16
    MCInst_setOpcodePub(MI, AArch64_map_insn("tsb"));
654
16
    return;
655
16
  }
656
657
426k
  MI->MRI = Info;
658
659
426k
  mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info);
660
426k
  if (mnem) {
661
60.7k
    MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
662
60.7k
    cs_mem_free(mnem);
663
664
60.7k
    switch(MCInst_getOpcode(MI)) {
665
34.8k
      default: break;
666
34.8k
      case AArch64_LD1i8_POST:
667
547
        arm64_op_addImm(MI, 1);
668
547
        break;
669
54
      case AArch64_LD1i16_POST:
670
54
        arm64_op_addImm(MI, 2);
671
54
        break;
672
1.36k
      case AArch64_LD1i32_POST:
673
1.36k
        arm64_op_addImm(MI, 4);
674
1.36k
        break;
675
232
      case AArch64_LD1Onev1d_POST:
676
1.49k
      case AArch64_LD1Onev2s_POST:
677
1.66k
      case AArch64_LD1Onev4h_POST:
678
3.15k
      case AArch64_LD1Onev8b_POST:
679
3.44k
      case AArch64_LD1i64_POST:
680
3.44k
        arm64_op_addImm(MI, 8);
681
3.44k
        break;
682
474
      case AArch64_LD1Onev16b_POST:
683
884
      case AArch64_LD1Onev2d_POST:
684
1.00k
      case AArch64_LD1Onev4s_POST:
685
1.46k
      case AArch64_LD1Onev8h_POST:
686
2.82k
      case AArch64_LD1Twov1d_POST:
687
2.88k
      case AArch64_LD1Twov2s_POST:
688
3.02k
      case AArch64_LD1Twov4h_POST:
689
3.06k
      case AArch64_LD1Twov8b_POST:
690
3.06k
        arm64_op_addImm(MI, 16);
691
3.06k
        break;
692
79
      case AArch64_LD1Threev1d_POST:
693
546
      case AArch64_LD1Threev2s_POST:
694
620
      case AArch64_LD1Threev4h_POST:
695
727
      case AArch64_LD1Threev8b_POST:
696
727
        arm64_op_addImm(MI, 24);
697
727
        break;
698
77
      case AArch64_LD1Fourv1d_POST:
699
416
      case AArch64_LD1Fourv2s_POST:
700
462
      case AArch64_LD1Fourv4h_POST:
701
747
      case AArch64_LD1Fourv8b_POST:
702
823
      case AArch64_LD1Twov16b_POST:
703
951
      case AArch64_LD1Twov2d_POST:
704
1.05k
      case AArch64_LD1Twov4s_POST:
705
1.13k
      case AArch64_LD1Twov8h_POST:
706
1.13k
        arm64_op_addImm(MI, 32);
707
1.13k
        break;
708
98
      case AArch64_LD1Threev16b_POST:
709
152
      case AArch64_LD1Threev2d_POST:
710
207
      case AArch64_LD1Threev4s_POST:
711
469
      case AArch64_LD1Threev8h_POST:
712
469
         arm64_op_addImm(MI, 48);
713
469
         break;
714
403
      case AArch64_LD1Fourv16b_POST:
715
543
      case AArch64_LD1Fourv2d_POST:
716
975
      case AArch64_LD1Fourv4s_POST:
717
1.47k
      case AArch64_LD1Fourv8h_POST:
718
1.47k
        arm64_op_addImm(MI, 64);
719
1.47k
        break;
720
266
      case AArch64_UMOVvi64:
721
266
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
722
266
        break;
723
277
      case AArch64_UMOVvi32:
724
277
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
725
277
        break;
726
34
      case AArch64_INSvi8gpr:
727
210
      case AArch64_DUP_ZI_B:
728
311
      case AArch64_CPY_ZPmI_B:
729
500
      case AArch64_CPY_ZPzI_B:
730
521
      case AArch64_CPY_ZPmV_B:
731
610
      case AArch64_CPY_ZPmR_B:
732
1.18k
      case AArch64_DUP_ZR_B:
733
1.18k
        if (MI->csh->detail) {
734
1.18k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
735
1.18k
        }
736
1.18k
        break;
737
45
      case AArch64_INSvi16gpr:
738
86
      case AArch64_DUP_ZI_H:
739
138
      case AArch64_CPY_ZPmI_H:
740
541
      case AArch64_CPY_ZPzI_H:
741
593
      case AArch64_CPY_ZPmV_H:
742
663
      case AArch64_CPY_ZPmR_H:
743
915
      case AArch64_DUP_ZR_H:
744
1.00k
      case AArch64_FCPY_ZPmI_H:
745
1.05k
      case AArch64_FDUP_ZI_H:
746
1.05k
        if (MI->csh->detail) {
747
1.05k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
748
1.05k
        }
749
1.05k
        break;
750
109
      case AArch64_INSvi32gpr:
751
195
      case AArch64_DUP_ZI_S:
752
433
      case AArch64_CPY_ZPmI_S:
753
825
      case AArch64_CPY_ZPzI_S:
754
1.39k
      case AArch64_CPY_ZPmV_S:
755
1.42k
      case AArch64_CPY_ZPmR_S:
756
1.44k
      case AArch64_DUP_ZR_S:
757
1.46k
      case AArch64_FCPY_ZPmI_S:
758
1.51k
      case AArch64_FDUP_ZI_S:
759
1.51k
        if (MI->csh->detail) {
760
1.51k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
761
1.51k
        }
762
1.51k
        break;
763
46
      case AArch64_INSvi64gpr:
764
244
      case AArch64_DUP_ZI_D:
765
1.01k
      case AArch64_CPY_ZPmI_D:
766
2.10k
      case AArch64_CPY_ZPzI_D:
767
2.14k
      case AArch64_CPY_ZPmV_D:
768
2.24k
      case AArch64_CPY_ZPmR_D:
769
2.54k
      case AArch64_DUP_ZR_D:
770
3.43k
      case AArch64_FCPY_ZPmI_D:
771
3.45k
      case AArch64_FDUP_ZI_D:
772
3.45k
        if (MI->csh->detail) {
773
3.45k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
774
3.45k
        }
775
3.45k
        break;
776
60
      case AArch64_INSvi8lane:
777
1.32k
      case AArch64_ORR_PPzPP:
778
1.44k
      case AArch64_ORRS_PPzPP:
779
1.44k
        if (MI->csh->detail) {
780
1.44k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
781
1.44k
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
782
1.44k
        }
783
1.44k
        break;
784
39
      case AArch64_INSvi16lane:
785
39
        if (MI->csh->detail) {
786
39
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
787
39
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
788
39
        }
789
39
         break;
790
43
      case AArch64_INSvi32lane:
791
43
        if (MI->csh->detail) {
792
43
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
793
43
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
794
43
        }
795
43
        break;
796
288
      case AArch64_INSvi64lane:
797
354
      case AArch64_ORR_ZZZ:
798
354
        if (MI->csh->detail) {
799
354
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
800
354
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
801
354
        }
802
354
        break;
803
368
      case AArch64_ORRv16i8:
804
695
      case AArch64_NOTv16i8:
805
695
        if (MI->csh->detail) {
806
695
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_16B;
807
695
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_16B;
808
695
        }
809
695
        break;
810
925
      case AArch64_ORRv8i8:
811
949
      case AArch64_NOTv8i8:
812
949
        if (MI->csh->detail) {
813
949
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_8B;
814
949
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_8B;
815
949
        }
816
949
        break;
817
21
      case AArch64_AND_PPzPP:
818
35
      case AArch64_ANDS_PPzPP:
819
57
      case AArch64_EOR_PPzPP:
820
80
      case AArch64_EORS_PPzPP:
821
111
      case AArch64_SEL_PPPP:
822
141
      case AArch64_SEL_ZPZZ_B:
823
141
        if (MI->csh->detail) {
824
141
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
825
141
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1B;
826
141
        }
827
141
        break;
828
166
      case AArch64_SEL_ZPZZ_D:
829
166
        if (MI->csh->detail) {
830
166
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
831
166
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1D;
832
166
        }
833
166
        break;
834
740
      case AArch64_SEL_ZPZZ_H:
835
740
        if (MI->csh->detail) {
836
740
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
837
740
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1H;
838
740
        }
839
740
        break;
840
382
      case AArch64_SEL_ZPZZ_S:
841
382
        if (MI->csh->detail) {
842
382
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
843
382
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1S;
844
382
        }
845
382
        break;
846
118
      case AArch64_DUP_ZZI_B:
847
118
        if (MI->csh->detail) {
848
118
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
849
118
          if (MI->flat_insn->detail->arm64.op_count == 1) {
850
0
            arm64_op_addReg(MI, ARM64_REG_B0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
851
118
          } else {
852
118
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
853
118
          }
854
118
        }
855
118
        break;
856
67
      case AArch64_DUP_ZZI_D:
857
67
        if (MI->csh->detail) {
858
67
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
859
67
          if (MI->flat_insn->detail->arm64.op_count == 1) {
860
0
            arm64_op_addReg(MI, ARM64_REG_D0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
861
67
          } else {
862
67
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
863
67
          }
864
67
        }
865
67
        break;
866
160
      case AArch64_DUP_ZZI_H:
867
160
        if (MI->csh->detail) {
868
160
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
869
160
          if (MI->flat_insn->detail->arm64.op_count == 1) {
870
0
            arm64_op_addReg(MI, ARM64_REG_H0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
871
160
          } else {
872
160
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
873
160
          }
874
160
        }
875
160
        break;
876
429
      case AArch64_DUP_ZZI_Q:
877
429
        if (MI->csh->detail) {
878
429
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1Q;
879
429
          if (MI->flat_insn->detail->arm64.op_count == 1) {
880
0
            arm64_op_addReg(MI, ARM64_REG_Q0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
881
429
          } else {
882
429
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1Q;
883
429
          }
884
429
         }
885
429
         break;
886
80
      case AArch64_DUP_ZZI_S:
887
80
        if (MI->csh->detail) {
888
80
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
889
80
          if (MI->flat_insn->detail->arm64.op_count == 1) {
890
0
            arm64_op_addReg(MI, ARM64_REG_S0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
891
80
          } else {
892
80
             MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
893
80
          }
894
80
        }
895
80
        break;
896
      // Hacky detail filling of SMSTART and SMSTOP alias'
897
83
      case AArch64_MSRpstatesvcrImm1:{
898
83
        if(MI->csh->detail){
899
83
          MI->flat_insn->detail->arm64.op_count = 2;
900
83
#ifndef CAPSTONE_DIET
901
83
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
902
83
          MI->ac_idx++;
903
83
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
904
83
          MI->ac_idx++;
905
83
#endif
906
83
          MI->flat_insn->detail->arm64.operands[0].type = ARM64_OP_SVCR;
907
83
          MI->flat_insn->detail->arm64.operands[0].sys = (unsigned)ARM64_SYSREG_SVCR;
908
83
          MI->flat_insn->detail->arm64.operands[0].svcr = lookupSVCRByEncoding(MCOperand_getImm(MCInst_getOperand(MI, 0)))->Encoding;
909
83
          MI->flat_insn->detail->arm64.operands[1].type = ARM64_OP_IMM;
910
83
          MI->flat_insn->detail->arm64.operands[1].imm = MCOperand_getImm(MCInst_getOperand(MI, 1));
911
83
        }
912
83
        break;
913
111
      }
914
60.7k
    }
915
366k
  } else {
916
366k
    printInstruction(MI, O);
917
366k
  }
918
426k
}
919
920
static bool printSysAlias(MCInst *MI, SStream *O)
921
4.26k
{
922
  // unsigned Opcode = MCInst_getOpcode(MI);
923
  //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!");
924
925
4.26k
  const char *Ins;
926
4.26k
  uint16_t Encoding;
927
4.26k
  bool NeedsReg;
928
4.26k
  char Name[64];
929
4.26k
  MCOperand *Op1 = MCInst_getOperand(MI, 0);
930
4.26k
  MCOperand *Cn = MCInst_getOperand(MI, 1);
931
4.26k
  MCOperand *Cm = MCInst_getOperand(MI, 2);
932
4.26k
  MCOperand *Op2 = MCInst_getOperand(MI, 3);
933
934
4.26k
  unsigned Op1Val = (unsigned)MCOperand_getImm(Op1);
935
4.26k
  unsigned CnVal = (unsigned)MCOperand_getImm(Cn);
936
4.26k
  unsigned CmVal = (unsigned)MCOperand_getImm(Cm);
937
4.26k
  unsigned Op2Val = (unsigned)MCOperand_getImm(Op2);
938
939
4.26k
  Encoding = Op2Val;
940
4.26k
  Encoding |= CmVal << 3;
941
4.26k
  Encoding |= CnVal << 7;
942
4.26k
  Encoding |= Op1Val << 11;
943
944
4.26k
  if (CnVal == 7) {
945
3.14k
    switch (CmVal) {
946
671
      default:
947
671
        return false;
948
949
      // IC aliases
950
696
      case 1: case 5: {
951
696
        const IC *IC = lookupICByEncoding(Encoding);
952
        // if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
953
696
        if (!IC)
954
126
          return false;
955
956
570
        NeedsReg = IC->NeedsReg;
957
570
        Ins = "ic";
958
570
        strncpy(Name, IC->Name, sizeof(Name) - 1);
959
570
      }
960
0
      break;
961
962
      // DC aliases
963
1.33k
      case 4: case 6: case 10: case 11: case 12: case 14: {
964
1.33k
        const DC *DC = lookupDCByEncoding(Encoding);
965
        // if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
966
1.33k
        if (!DC)
967
1.14k
          return false;
968
969
188
        NeedsReg = true;
970
188
        Ins = "dc";
971
188
        strncpy(Name, DC->Name, sizeof(Name) - 1);
972
188
      }
973
0
      break;
974
975
      // AT aliases
976
445
      case 8: case 9: {
977
445
        const AT *AT = lookupATByEncoding(Encoding);
978
        // if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
979
445
        if (!AT)
980
248
          return false;
981
982
197
        NeedsReg = true;
983
197
        Ins = "at";
984
197
        strncpy(Name, AT->Name, sizeof(Name) - 1);
985
197
      }
986
0
      break;
987
3.14k
    }
988
3.14k
  } else if (CnVal == 8) {
989
    // TLBI aliases
990
608
    const TLBI *TLBI = lookupTLBIByEncoding(Encoding);
991
    // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
992
608
    if (!TLBI)
993
365
      return false;
994
995
243
    NeedsReg = TLBI->NeedsReg;
996
243
    Ins = "tlbi";
997
243
    strncpy(Name, TLBI->Name, sizeof(Name) - 1);
998
243
  } else
999
510
    return false;
1000
1001
1.19k
  SStream_concat(O, "%s\t%s", Ins, Name);
1002
1003
1.19k
  if (NeedsReg) {
1004
419
    SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName));
1005
419
  }
1006
1007
1.19k
  MCInst_setOpcodePub(MI, AArch64_map_insn(Ins));
1008
1009
1.19k
  if (MI->csh->detail) {
1010
#if 0
1011
#ifndef CAPSTONE_DIET
1012
    uint8_t access;
1013
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1014
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1015
    MI->ac_idx++;
1016
#endif
1017
#endif
1018
1.19k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
1019
1.19k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = AArch64_map_sys_op(Name);
1020
1.19k
    MI->flat_insn->detail->arm64.op_count++;
1021
1022
1.19k
    if (NeedsReg) {
1023
419
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1024
419
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4));
1025
419
      MI->flat_insn->detail->arm64.op_count++;
1026
419
    }
1027
1.19k
  }
1028
1029
1.19k
  return true;
1030
4.26k
}
1031
1032
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
1033
617k
{
1034
617k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1035
1036
617k
  if (MCOperand_isReg(Op)) {
1037
540k
    unsigned Reg = MCOperand_getReg(Op);
1038
1039
540k
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1040
1041
540k
    if (MI->csh->detail) {
1042
540k
      if (MI->csh->doing_mem) {
1043
236k
        if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
1044
207k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
1045
207k
        }
1046
28.4k
        else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) {
1047
28.4k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
1048
28.4k
        }
1049
304k
      } else if (MI->csh->doing_SME_Index) {
1050
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1051
10.3k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.base = Reg;
1052
293k
      } else {
1053
293k
#ifndef CAPSTONE_DIET
1054
293k
        uint8_t access;
1055
1056
293k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1057
293k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1058
293k
        MI->ac_idx++;
1059
293k
#endif
1060
293k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1061
293k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1062
293k
        MI->flat_insn->detail->arm64.op_count++;
1063
293k
      }
1064
540k
    }
1065
540k
  } else if (MCOperand_isImm(Op)) {
1066
77.6k
    int64_t imm = MCOperand_getImm(Op);
1067
1068
77.6k
    if (MI->Opcode == AArch64_ADR) {
1069
6.42k
      imm += MI->address;
1070
6.42k
      printUInt64Bang(O, imm);
1071
71.2k
    } else {
1072
71.2k
      if (MI->csh->doing_mem) {
1073
22.5k
        if (MI->csh->imm_unsigned) {
1074
0
          printUInt64Bang(O, imm);
1075
22.5k
        } else {
1076
22.5k
          printInt64Bang(O, imm);
1077
22.5k
        }
1078
22.5k
      } else
1079
48.7k
        printUInt64Bang(O, imm);
1080
71.2k
    }
1081
1082
77.6k
    if (MI->csh->detail) {
1083
77.6k
      if (MI->csh->doing_mem) {
1084
22.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
1085
55.1k
      } else if (MI->csh->doing_SME_Index) {
1086
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1087
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = (int32_t)imm; 
1088
55.1k
      } else {
1089
55.1k
#ifndef CAPSTONE_DIET
1090
55.1k
        uint8_t access;
1091
1092
55.1k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1093
55.1k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1094
55.1k
#endif
1095
55.1k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1096
55.1k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
1097
55.1k
        MI->flat_insn->detail->arm64.op_count++;
1098
55.1k
      }
1099
77.6k
    }
1100
77.6k
  }
1101
617k
}
1102
1103
static void printImm(MCInst *MI, unsigned OpNum, SStream *O)
1104
8.55k
{
1105
8.55k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1106
8.55k
  printUInt64Bang(O, MCOperand_getImm(Op));
1107
1108
8.55k
  if (MI->csh->detail) {
1109
8.55k
#ifndef CAPSTONE_DIET
1110
8.55k
    uint8_t access;
1111
8.55k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1112
8.55k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1113
8.55k
    MI->ac_idx++;
1114
8.55k
#endif
1115
8.55k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1116
8.55k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1117
8.55k
    MI->flat_insn->detail->arm64.op_count++;
1118
8.55k
  }
1119
8.55k
}
1120
1121
static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O)
1122
110
{
1123
110
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1124
110
  printUInt64Bang(O, MCOperand_getImm(Op));
1125
1126
110
  if (MI->csh->detail) {
1127
110
#ifndef CAPSTONE_DIET
1128
110
    uint8_t access;
1129
110
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1130
110
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1131
110
    MI->ac_idx++;
1132
110
#endif
1133
110
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1134
110
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1135
110
    MI->flat_insn->detail->arm64.op_count++;
1136
110
  }
1137
110
}
1138
1139
3.56k
static void printSImm(MCInst *MI, unsigned OpNo, SStream *O, int Size) {
1140
3.56k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1141
3.56k
  if (Size == 8)
1142
3.12k
  printInt64Bang(O, (signed char) MCOperand_getImm(Op));
1143
436
  else if (Size == 16)
1144
436
  printInt64Bang(O, (signed short) MCOperand_getImm(Op));
1145
0
  else
1146
0
    printInt64Bang(O, MCOperand_getImm(Op));
1147
1148
3.56k
  if (MI->csh->detail) {
1149
3.56k
#ifndef CAPSTONE_DIET
1150
3.56k
    uint8_t access;
1151
3.56k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1152
3.56k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1153
3.56k
    MI->ac_idx++;
1154
3.56k
#endif
1155
3.56k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1156
3.56k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1157
3.56k
    MI->flat_insn->detail->arm64.op_count++;
1158
3.56k
  }
1159
3.56k
}
1160
1161
static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O,
1162
    unsigned Imm)
1163
39.5k
{
1164
39.5k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1165
1166
39.5k
  if (MCOperand_isReg(Op)) {
1167
39.5k
    unsigned Reg = MCOperand_getReg(Op);
1168
39.5k
    if (Reg == AArch64_XZR) {
1169
0
      printInt32Bang(O, Imm);
1170
1171
0
      if (MI->csh->detail) {
1172
0
#ifndef CAPSTONE_DIET
1173
0
        uint8_t access;
1174
1175
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1176
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1177
0
        MI->ac_idx++;
1178
0
#endif
1179
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1180
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
1181
0
        MI->flat_insn->detail->arm64.op_count++;
1182
0
      }
1183
39.5k
    } else {
1184
39.5k
      SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1185
1186
39.5k
      if (MI->csh->detail) {
1187
39.5k
#ifndef CAPSTONE_DIET
1188
39.5k
        uint8_t access;
1189
1190
39.5k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1191
39.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1192
39.5k
        MI->ac_idx++;
1193
39.5k
#endif
1194
39.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1195
39.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1196
39.5k
        MI->flat_insn->detail->arm64.op_count++;
1197
39.5k
      }
1198
39.5k
    }
1199
39.5k
  }
1200
  //llvm_unreachable("unknown operand kind in printPostIncOperand64");
1201
39.5k
}
1202
1203
static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1204
75.5k
{
1205
75.5k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1206
  //assert(Op.isReg() && "Non-register vreg operand!");
1207
75.5k
  unsigned Reg = MCOperand_getReg(Op);
1208
1209
75.5k
  SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
1210
1211
75.5k
  if (MI->csh->detail) {
1212
75.5k
#ifndef CAPSTONE_DIET
1213
75.5k
    uint8_t access;
1214
75.5k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1215
75.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1216
75.5k
    MI->ac_idx++;
1217
75.5k
#endif
1218
75.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1219
75.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
1220
75.5k
    MI->flat_insn->detail->arm64.op_count++;
1221
75.5k
  }
1222
75.5k
}
1223
1224
static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O)
1225
6.21k
{
1226
6.21k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1227
  //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1228
6.21k
  SStream_concat(O, "c%u", MCOperand_getImm(Op));
1229
1230
6.21k
  if (MI->csh->detail) {
1231
6.21k
#ifndef CAPSTONE_DIET
1232
6.21k
    uint8_t access;
1233
1234
6.21k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1235
6.21k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1236
6.21k
    MI->ac_idx++;
1237
6.21k
#endif
1238
6.21k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
1239
6.21k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1240
6.21k
    MI->flat_insn->detail->arm64.op_count++;
1241
6.21k
  }
1242
6.21k
}
1243
1244
static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
1245
5.31k
{
1246
5.31k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1247
5.31k
  if (MCOperand_isImm(MO)) {
1248
5.31k
    unsigned Val = (MCOperand_getImm(MO) & 0xfff);
1249
    //assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1250
5.31k
    unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)));
1251
1252
5.31k
    printInt32Bang(O, Val);
1253
1254
5.31k
    if (MI->csh->detail) {
1255
5.31k
#ifndef CAPSTONE_DIET
1256
5.31k
      uint8_t access;
1257
1258
5.31k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1259
5.31k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1260
5.31k
      MI->ac_idx++;
1261
5.31k
#endif
1262
5.31k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1263
5.31k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1264
5.31k
      MI->flat_insn->detail->arm64.op_count++;
1265
5.31k
    }
1266
1267
5.31k
    if (Shift != 0)
1268
1.84k
      printShifter(MI, OpNum + 1, O);
1269
5.31k
  }
1270
5.31k
}
1271
1272
static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
1273
6.71k
{
1274
6.71k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1275
1276
6.71k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 32);
1277
6.71k
  printUInt32Bang(O, (int)Val);
1278
1279
6.71k
  if (MI->csh->detail) {
1280
6.71k
#ifndef CAPSTONE_DIET
1281
6.71k
    uint8_t access;
1282
1283
6.71k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1284
6.71k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1285
6.71k
    MI->ac_idx++;
1286
6.71k
#endif
1287
6.71k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1288
6.71k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1289
6.71k
    MI->flat_insn->detail->arm64.op_count++;
1290
6.71k
  }
1291
6.71k
}
1292
1293
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
1294
4.48k
{
1295
4.48k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1296
4.48k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
1297
1298
4.48k
  switch(MI->flat_insn->id) {
1299
1.38k
    default:
1300
1.38k
      printInt64Bang(O, Val);
1301
1.38k
      break;
1302
1303
900
    case ARM64_INS_ORR:
1304
1.25k
    case ARM64_INS_AND:
1305
3.10k
    case ARM64_INS_EOR:
1306
3.10k
    case ARM64_INS_TST:
1307
      // do not print number in negative form
1308
3.10k
      if (Val >= 0 && Val <= HEX_THRESHOLD)
1309
340
        SStream_concat(O, "#%u", (int)Val);
1310
2.76k
      else
1311
2.76k
        SStream_concat(O, "#0x%"PRIx64, Val);
1312
3.10k
      break;
1313
4.48k
  }
1314
1315
4.48k
  if (MI->csh->detail) {
1316
4.48k
#ifndef CAPSTONE_DIET
1317
4.48k
    uint8_t access;
1318
1319
4.48k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1320
4.48k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1321
4.48k
    MI->ac_idx++;
1322
4.48k
#endif
1323
4.48k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1324
4.48k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val;
1325
4.48k
    MI->flat_insn->detail->arm64.op_count++;
1326
4.48k
  }
1327
4.48k
}
1328
1329
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
1330
21.9k
{
1331
21.9k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1332
1333
  // LSL #0 should not be printed.
1334
21.9k
  if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL &&
1335
21.9k
      AArch64_AM_getShiftValue(Val) == 0)
1336
2.08k
    return;
1337
1338
19.8k
  SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)));
1339
19.8k
  printInt32BangDec(O, AArch64_AM_getShiftValue(Val));
1340
1341
19.8k
  if (MI->csh->detail) {
1342
19.8k
    arm64_shifter shifter = ARM64_SFT_INVALID;
1343
1344
19.8k
    switch(AArch64_AM_getShiftType(Val)) {
1345
0
      default:  // never reach
1346
10.3k
      case AArch64_AM_LSL:
1347
10.3k
        shifter = ARM64_SFT_LSL;
1348
10.3k
        break;
1349
1350
3.36k
      case AArch64_AM_LSR:
1351
3.36k
        shifter = ARM64_SFT_LSR;
1352
3.36k
        break;
1353
1354
2.40k
      case AArch64_AM_ASR:
1355
2.40k
        shifter = ARM64_SFT_ASR;
1356
2.40k
        break;
1357
1358
2.26k
      case AArch64_AM_ROR:
1359
2.26k
        shifter = ARM64_SFT_ROR;
1360
2.26k
        break;
1361
1362
1.49k
      case AArch64_AM_MSL:
1363
1.49k
        shifter = ARM64_SFT_MSL;
1364
1.49k
        break;
1365
19.8k
    }
1366
1367
19.8k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter;
1368
19.8k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val);
1369
19.8k
  }
1370
19.8k
}
1371
1372
static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1373
13.1k
{
1374
13.1k
  SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1375
1376
13.1k
  if (MI->csh->detail) {
1377
13.1k
#ifndef CAPSTONE_DIET
1378
13.1k
    uint8_t access;
1379
13.1k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1380
13.1k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1381
13.1k
    MI->ac_idx++;
1382
13.1k
#endif
1383
13.1k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1384
13.1k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1385
13.1k
    MI->flat_insn->detail->arm64.op_count++;
1386
13.1k
  }
1387
1388
13.1k
  printShifter(MI, OpNum + 1, O);
1389
13.1k
}
1390
1391
static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
1392
12.7k
{
1393
12.7k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1394
12.7k
  AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
1395
12.7k
  unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
1396
1397
  // If the destination or first source register operand is [W]SP, print
1398
  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1399
  // all.
1400
12.7k
  if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) {
1401
4.66k
    unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0));
1402
4.66k
    unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
1403
1404
4.66k
    if (((Dest == AArch64_SP || Src1 == AArch64_SP) &&
1405
4.66k
          ExtType == AArch64_AM_UXTX) ||
1406
4.66k
        ((Dest == AArch64_WSP || Src1 == AArch64_WSP) &&
1407
3.09k
         ExtType == AArch64_AM_UXTW)) {
1408
1.68k
      if (ShiftVal != 0) {
1409
1.68k
        SStream_concat0(O, ", lsl ");
1410
1.68k
        printInt32Bang(O, ShiftVal);
1411
1412
1.68k
        if (MI->csh->detail) {
1413
1.68k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1414
1.68k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1415
1.68k
        }
1416
1.68k
      }
1417
1418
1.68k
      return;
1419
1.68k
    }
1420
4.66k
  }
1421
1422
11.0k
  SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
1423
1424
11.0k
  if (MI->csh->detail) {
1425
11.0k
    arm64_extender ext = ARM64_EXT_INVALID;
1426
11.0k
    switch(ExtType) {
1427
0
      default:  // never reach
1428
1429
419
      case AArch64_AM_UXTB:
1430
419
        ext = ARM64_EXT_UXTB;
1431
419
        break;
1432
1433
2.15k
      case AArch64_AM_UXTH:
1434
2.15k
        ext = ARM64_EXT_UXTH;
1435
2.15k
        break;
1436
1437
1.56k
      case AArch64_AM_UXTW:
1438
1.56k
        ext = ARM64_EXT_UXTW;
1439
1.56k
        break;
1440
1441
1.41k
      case AArch64_AM_UXTX:
1442
1.41k
        ext = ARM64_EXT_UXTX;
1443
1.41k
        break;
1444
1445
1.07k
      case AArch64_AM_SXTB:
1446
1.07k
        ext = ARM64_EXT_SXTB;
1447
1.07k
        break;
1448
1449
894
      case AArch64_AM_SXTH:
1450
894
        ext = ARM64_EXT_SXTH;
1451
894
        break;
1452
1453
525
      case AArch64_AM_SXTW:
1454
525
        ext = ARM64_EXT_SXTW;
1455
525
        break;
1456
1457
2.98k
      case AArch64_AM_SXTX:
1458
2.98k
        ext = ARM64_EXT_SXTX;
1459
2.98k
        break;
1460
11.0k
    }
1461
1462
11.0k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext;
1463
11.0k
  }
1464
1465
11.0k
  if (ShiftVal != 0) {
1466
7.51k
    SStream_concat0(O, " ");
1467
7.51k
    printInt32Bang(O, ShiftVal);
1468
1469
7.51k
    if (MI->csh->detail) {
1470
7.51k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1471
7.51k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1472
7.51k
    }
1473
7.51k
  }
1474
11.0k
}
1475
1476
static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1477
6.61k
{
1478
6.61k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1479
1480
6.61k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1481
1482
6.61k
  if (MI->csh->detail) {
1483
6.61k
#ifndef CAPSTONE_DIET
1484
6.61k
    uint8_t access;
1485
6.61k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1486
6.61k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1487
6.61k
    MI->ac_idx++;
1488
6.61k
#endif
1489
6.61k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1490
6.61k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1491
6.61k
    MI->flat_insn->detail->arm64.op_count++;
1492
6.61k
  }
1493
1494
6.61k
  printArithExtend(MI, OpNum + 1, O);
1495
6.61k
}
1496
1497
static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width,
1498
             char SrcRegKind, SStream *O)
1499
25.7k
{
1500
  // sxtw, sxtx, uxtw or lsl (== uxtx)
1501
25.7k
  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1502
25.7k
  if (IsLSL) {
1503
9.88k
    SStream_concat0(O, "lsl");
1504
1505
9.88k
    if (MI->csh->detail) {
1506
9.88k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1507
9.88k
    }
1508
15.8k
  } else {
1509
15.8k
    SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind);
1510
1511
15.8k
    if (MI->csh->detail) {
1512
15.8k
      if (!SignExtend) {
1513
6.39k
        switch(SrcRegKind) {
1514
0
          default: break;
1515
0
          case 'b':
1516
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB;
1517
0
               break;
1518
0
          case 'h':
1519
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH;
1520
0
               break;
1521
6.39k
          case 'w':
1522
6.39k
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW;
1523
6.39k
               break;
1524
6.39k
        }
1525
9.44k
      } else {
1526
9.44k
          switch(SrcRegKind) {
1527
0
            default: break;
1528
0
            case 'b':
1529
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB;
1530
0
              break;
1531
0
            case 'h':
1532
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH;
1533
0
              break;
1534
5.04k
            case 'w':
1535
5.04k
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW;
1536
5.04k
              break;
1537
4.40k
            case 'x':
1538
4.40k
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX;
1539
4.40k
              break;
1540
9.44k
          }
1541
9.44k
      }
1542
15.8k
    }
1543
15.8k
  }
1544
1545
25.7k
  if (DoShift || IsLSL) {
1546
21.1k
    SStream_concat(O, " #%u", Log2_32(Width / 8));
1547
1548
21.1k
    if (MI->csh->detail) {
1549
21.1k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1550
21.1k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8);
1551
21.1k
    }
1552
21.1k
  }
1553
25.7k
}
1554
1555
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
1556
7.67k
{
1557
7.67k
  unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1558
7.67k
  unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
1559
1560
7.67k
  printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O);
1561
7.67k
}
1562
1563
static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O,
1564
            bool SignExtend, int ExtWidth,
1565
            char SrcRegKind, char Suffix)
1566
23.5k
{
1567
23.5k
  bool DoShift;
1568
1569
23.5k
  printOperand(MI, OpNum, O);
1570
1571
23.5k
  if (Suffix == 's' || Suffix == 'd')
1572
13.6k
    SStream_concat(O, ".%c", Suffix);
1573
1574
23.5k
  DoShift = ExtWidth != 8;
1575
23.5k
  if (SignExtend || DoShift || SrcRegKind == 'w') {
1576
18.0k
    SStream_concat0(O, ", ");
1577
18.0k
    printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1578
18.0k
  }
1579
23.5k
}
1580
1581
static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1582
3.67k
{
1583
3.67k
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1584
3.67k
  SStream_concat0(O, getCondCodeName(CC));
1585
1586
3.67k
  if (MI->csh->detail)
1587
3.67k
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1);
1588
3.67k
}
1589
1590
static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1591
259
{
1592
259
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1593
259
  SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC)));
1594
1595
259
  if (MI->csh->detail) {
1596
259
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1);
1597
259
  }
1598
259
}
1599
1600
static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
1601
38.4k
{
1602
38.4k
  int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1603
1604
38.4k
  printInt64Bang(O, val);
1605
1606
38.4k
  if (MI->csh->detail) {
1607
38.4k
    if (MI->csh->doing_mem) {
1608
30.8k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1609
30.8k
    } else {
1610
7.62k
#ifndef CAPSTONE_DIET
1611
7.62k
      uint8_t access;
1612
1613
7.62k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1614
7.62k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1615
7.62k
      MI->ac_idx++;
1616
7.62k
#endif
1617
7.62k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1618
7.62k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
1619
7.62k
      MI->flat_insn->detail->arm64.op_count++;
1620
7.62k
    }
1621
38.4k
  }
1622
38.4k
}
1623
1624
static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale)
1625
10.4k
{
1626
10.4k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1627
1628
10.4k
  if (MCOperand_isImm(MO)) {
1629
10.4k
    int64_t val = Scale * MCOperand_getImm(MO);
1630
10.4k
    printInt64Bang(O, val);
1631
1632
10.4k
    if (MI->csh->detail) {
1633
10.4k
      if (MI->csh->doing_mem) {
1634
10.4k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1635
10.4k
      } else {
1636
0
#ifndef CAPSTONE_DIET
1637
0
        uint8_t access;
1638
1639
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1640
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1641
0
        MI->ac_idx++;
1642
0
#endif
1643
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1644
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
1645
0
        MI->flat_insn->detail->arm64.op_count++;
1646
0
      }
1647
10.4k
    }
1648
10.4k
  }
1649
10.4k
}
1650
1651
#if 0
1652
static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale)
1653
{
1654
  MCOperand *MO = MCInst_getOperand(MI, OpNum + 1);
1655
1656
  SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1657
1658
  if (MCOperand_isImm(MO)) {
1659
    int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1660
    printInt64Bang(O, val);
1661
  // } else {
1662
  //   // assert(MO1.isExpr() && "Unexpected operand type!");
1663
  //   SStream_concat0(O, ", ");
1664
  //   MO1.getExpr()->print(O, &MAI);
1665
  }
1666
1667
  SStream_concat0(O, "]");
1668
}
1669
#endif
1670
1671
// IsSVEPrefetch = false
1672
static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch)
1673
9.20k
{
1674
9.20k
  unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1675
1676
9.20k
  if (IsSVEPrefetch) {
1677
6.41k
    const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop);
1678
6.41k
    if (PRFM)
1679
5.58k
      SStream_concat0(O, PRFM->Name);
1680
1681
6.41k
    return;
1682
6.41k
  } else {
1683
2.78k
    const PRFM *PRFM = lookupPRFMByEncoding(prfop);
1684
2.78k
    if (PRFM)
1685
975
      SStream_concat0(O, PRFM->Name);
1686
1687
2.78k
    return;
1688
2.78k
  }
1689
1690
  // FIXME: set OpcodePub?
1691
1692
0
  printInt32Bang(O, prfop);
1693
1694
0
  if (MI->csh->detail) {
1695
0
#ifndef CAPSTONE_DIET
1696
0
    uint8_t access;
1697
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1698
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1699
0
    MI->ac_idx++;
1700
0
#endif
1701
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1702
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop;
1703
0
    MI->flat_insn->detail->arm64.op_count++;
1704
0
  }
1705
0
}
1706
1707
static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
1708
420
{
1709
420
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1710
420
  unsigned int psbhintop = MCOperand_getImm(Op);
1711
1712
420
  const PSB *PSB = lookupPSBByEncoding(psbhintop);
1713
420
  if (PSB)
1714
420
    SStream_concat0(O, PSB->Name);
1715
0
  else
1716
0
    printUInt32Bang(O, psbhintop);
1717
420
}
1718
1719
18
static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) {
1720
18
  unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) ^ 32;
1721
1722
18
  const BTI *BTI = lookupBTIByEncoding(btihintop);
1723
18
  if (BTI)
1724
18
  SStream_concat0(O, BTI->Name);
1725
0
  else
1726
0
  printUInt32Bang(O, btihintop);
1727
18
}
1728
1729
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1730
3.66k
{
1731
3.66k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1732
3.66k
  float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO));
1733
1734
  // 8 decimal places are enough to perfectly represent permitted floats.
1735
#if defined(_KERNEL_MODE)
1736
  // Issue #681: Windows kernel does not support formatting float point
1737
  SStream_concat0(O, "#<float_point_unsupported>");
1738
#else
1739
3.66k
  SStream_concat(O, "#%.8f", FPImm);
1740
3.66k
#endif
1741
1742
3.66k
  if (MI->csh->detail) {
1743
3.66k
#ifndef CAPSTONE_DIET
1744
3.66k
    uint8_t access;
1745
1746
3.66k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1747
3.66k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1748
3.66k
    MI->ac_idx++;
1749
3.66k
#endif
1750
3.66k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
1751
3.66k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm;
1752
3.66k
    MI->flat_insn->detail->arm64.op_count++;
1753
3.66k
  }
1754
3.66k
}
1755
1756
//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1)
1757
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride)
1758
245k
{
1759
490k
  while (Stride--) {
1760
245k
    if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30
1761
199k
      Reg += 1;
1762
46.1k
    else if (Reg == AArch64_Q31) // Vector lists can wrap around.
1763
12.3k
      Reg = AArch64_Q0;
1764
33.7k
    else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30
1765
32.8k
      Reg += 1;
1766
923
    else if (Reg == AArch64_Z31) // Vector lists can wrap around.
1767
923
      Reg = AArch64_Z0;
1768
245k
  }
1769
1770
245k
  return Reg;
1771
245k
}
1772
1773
static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size)
1774
3.32k
{
1775
  // static_assert(size == 64 || size == 32,
1776
  //    "Template parameter must be either 32 or 64");
1777
3.32k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1778
3.32k
  unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64;
1779
3.32k
  unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64;
1780
3.32k
  unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube);
1781
3.32k
  unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo);
1782
1783
3.32k
  SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName),
1784
3.32k
      getRegisterName(Odd, AArch64_NoRegAltName));
1785
1786
3.32k
  if (MI->csh->detail) {
1787
3.32k
#ifndef CAPSTONE_DIET
1788
3.32k
    uint8_t access;
1789
1790
3.32k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1791
3.32k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1792
3.32k
    MI->ac_idx++;
1793
3.32k
#endif
1794
1795
3.32k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1796
3.32k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Even;
1797
3.32k
    MI->flat_insn->detail->arm64.op_count++;
1798
1799
3.32k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1800
3.32k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Odd;
1801
3.32k
    MI->flat_insn->detail->arm64.op_count++;
1802
3.32k
  }
1803
3.32k
}
1804
1805
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
1806
    char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas)
1807
110k
{
1808
1.62M
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
1809
110k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1810
110k
  unsigned NumRegs = 1, FirstReg, i;
1811
1812
110k
  SStream_concat0(O, "{");
1813
1814
  // Work out how many registers there are in the list (if there is an actual
1815
  // list).
1816
110k
  if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) ||
1817
110k
      GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) ||
1818
110k
      GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg))
1819
26.2k
    NumRegs = 2;
1820
84.5k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) ||
1821
84.5k
      GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) ||
1822
84.5k
      GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg))
1823
18.7k
    NumRegs = 3;
1824
65.7k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) ||
1825
65.7k
      GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) ||
1826
65.7k
      GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg))
1827
23.6k
    NumRegs = 4;
1828
1829
  // Now forget about the list and find out what the first register is.
1830
110k
  if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0)))
1831
14.3k
    Reg = FirstReg;
1832
96.4k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0)))
1833
48.4k
    Reg = FirstReg;
1834
47.9k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0)))
1835
5.85k
    Reg = FirstReg;
1836
1837
  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1838
  // printing (otherwise getRegisterName fails).
1839
110k
  if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
1840
21.8k
    const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
1841
21.8k
    Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
1842
21.8k
  }
1843
1844
356k
  for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) {
1845
245k
    bool isZReg = GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg);
1846
245k
    if (isZReg)
1847
33.7k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix);
1848
211k
    else
1849
211k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
1850
1851
245k
    if (MI->csh->detail) {
1852
245k
#ifndef CAPSTONE_DIET
1853
245k
      uint8_t access;
1854
1855
245k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1856
245k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1857
245k
      MI->ac_idx++;
1858
245k
#endif
1859
245k
      unsigned regForDetail = isZReg ? Reg : AArch64_map_vregister(Reg);
1860
245k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1861
245k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = regForDetail;
1862
245k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
1863
245k
      MI->flat_insn->detail->arm64.op_count++;
1864
245k
    }
1865
1866
245k
    if (i + 1 != NumRegs)
1867
134k
      SStream_concat0(O, ", ");
1868
245k
  }
1869
1870
110k
  SStream_concat0(O, "}");
1871
110k
}
1872
1873
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind)
1874
110k
{
1875
110k
  char Suffix[32];
1876
110k
  arm64_vas vas = 0;
1877
1878
110k
  if (NumLanes) {
1879
48.3k
    cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind);
1880
1881
48.3k
    switch(LaneKind) {
1882
0
      default: break;
1883
14.1k
      case 'b':
1884
14.1k
        switch(NumLanes) {
1885
0
          default: break;
1886
0
          case 1:
1887
0
               vas = ARM64_VAS_1B;
1888
0
               break;
1889
0
          case 4:
1890
0
               vas = ARM64_VAS_4B;
1891
0
               break;
1892
5.97k
          case 8:
1893
5.97k
               vas = ARM64_VAS_8B;
1894
5.97k
               break;
1895
8.14k
          case 16:
1896
8.14k
               vas = ARM64_VAS_16B;
1897
8.14k
               break;
1898
14.1k
        }
1899
14.1k
        break;
1900
14.1k
      case 'h':
1901
10.6k
        switch(NumLanes) {
1902
0
          default: break;
1903
0
          case 1:
1904
0
               vas = ARM64_VAS_1H;
1905
0
               break;
1906
0
          case 2:
1907
0
               vas = ARM64_VAS_2H;
1908
0
               break;
1909
4.54k
          case 4:
1910
4.54k
               vas = ARM64_VAS_4H;
1911
4.54k
               break;
1912
6.05k
          case 8:
1913
6.05k
               vas = ARM64_VAS_8H;
1914
6.05k
               break;
1915
10.6k
        }
1916
10.6k
        break;
1917
14.2k
      case 's':
1918
14.2k
        switch(NumLanes) {
1919
0
          default: break;
1920
0
          case 1:
1921
0
               vas = ARM64_VAS_1S;
1922
0
               break;
1923
6.81k
          case 2:
1924
6.81k
               vas = ARM64_VAS_2S;
1925
6.81k
               break;
1926
7.38k
          case 4:
1927
7.38k
               vas = ARM64_VAS_4S;
1928
7.38k
               break;
1929
14.2k
        }
1930
14.2k
        break;
1931
14.2k
      case 'd':
1932
9.47k
        switch(NumLanes) {
1933
0
          default: break;
1934
4.54k
          case 1:
1935
4.54k
               vas = ARM64_VAS_1D;
1936
4.54k
               break;
1937
4.93k
          case 2:
1938
4.93k
               vas = ARM64_VAS_2D;
1939
4.93k
               break;
1940
9.47k
        }
1941
9.47k
        break;
1942
9.47k
      case 'q':
1943
0
        switch(NumLanes) {
1944
0
          default: break;
1945
0
          case 1:
1946
0
               vas = ARM64_VAS_1Q;
1947
0
               break;
1948
0
        }
1949
0
        break;
1950
48.3k
    }
1951
62.3k
  } else {
1952
62.3k
    cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind);
1953
1954
62.3k
    switch(LaneKind) {
1955
0
      default: break;
1956
11.3k
      case 'b':
1957
11.3k
           vas = ARM64_VAS_1B;
1958
11.3k
           break;
1959
14.3k
      case 'h':
1960
14.3k
           vas = ARM64_VAS_1H;
1961
14.3k
           break;
1962
14.6k
      case 's':
1963
14.6k
           vas = ARM64_VAS_1S;
1964
14.6k
           break;
1965
22.0k
      case 'd':
1966
22.0k
           vas = ARM64_VAS_1D;
1967
22.0k
           break;
1968
0
      case 'q':
1969
0
           vas = ARM64_VAS_1Q;
1970
0
           break;
1971
62.3k
    }
1972
62.3k
  }
1973
1974
110k
  printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas);
1975
110k
}
1976
1977
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
1978
52.5k
{
1979
52.5k
  SStream_concat0(O, "[");
1980
52.5k
  printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
1981
52.5k
  SStream_concat0(O, "]");
1982
1983
52.5k
  if (MI->csh->detail) {
1984
52.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1985
52.5k
  }
1986
52.5k
}
1987
1988
static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
1989
19.0k
{
1990
19.0k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1991
1992
  // If the label has already been resolved to an immediate offset (say, when
1993
  // we're running the disassembler), just print the immediate.
1994
19.0k
  if (MCOperand_isImm(Op)) {
1995
19.0k
    uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address;
1996
19.0k
    printUInt64Bang(O, imm);
1997
1998
19.0k
    if (MI->csh->detail) {
1999
19.0k
#ifndef CAPSTONE_DIET
2000
19.0k
      uint8_t access;
2001
2002
19.0k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2003
19.0k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2004
19.0k
      MI->ac_idx++;
2005
19.0k
#endif
2006
19.0k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2007
19.0k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2008
19.0k
      MI->flat_insn->detail->arm64.op_count++;
2009
19.0k
    }
2010
19.0k
  }
2011
19.0k
}
2012
2013
static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
2014
3.09k
{
2015
3.09k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
2016
2017
3.09k
  if (MCOperand_isImm(Op)) {
2018
    // ADRP sign extends a 21-bit offset, shifts it left by 12
2019
    // and adds it to the value of the PC with its bottom 12 bits cleared
2020
3.09k
    uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff);
2021
3.09k
    printUInt64Bang(O, imm);
2022
2023
3.09k
    if (MI->csh->detail) {
2024
3.09k
#ifndef CAPSTONE_DIET
2025
3.09k
      uint8_t access;
2026
2027
3.09k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2028
3.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2029
3.09k
      MI->ac_idx++;
2030
3.09k
#endif
2031
3.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2032
3.09k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2033
3.09k
      MI->flat_insn->detail->arm64.op_count++;
2034
3.09k
    }
2035
3.09k
  }
2036
3.09k
}
2037
2038
static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
2039
531
{
2040
531
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2041
531
  unsigned Opcode = MCInst_getOpcode(MI);
2042
531
  const char *Name = NULL;
2043
2044
531
  if (Opcode == AArch64_ISB) {
2045
28
    const ISB *ISB = lookupISBByEncoding(Val);
2046
28
    Name = ISB ? ISB->Name : NULL;
2047
503
  } else if (Opcode == AArch64_TSB) {
2048
0
    const TSB *TSB = lookupTSBByEncoding(Val);
2049
0
    Name = TSB ? TSB->Name : NULL;
2050
503
  } else {
2051
503
    const DB *DB = lookupDBByEncoding(Val);
2052
503
    Name = DB ? DB->Name : NULL;
2053
503
  }
2054
2055
531
  if (Name) {
2056
202
    SStream_concat0(O, Name);
2057
2058
202
    if (MI->csh->detail) {
2059
202
#ifndef CAPSTONE_DIET
2060
202
      uint8_t access;
2061
2062
202
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2063
202
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2064
202
      MI->ac_idx++;
2065
202
#endif
2066
202
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2067
202
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2068
202
      MI->flat_insn->detail->arm64.op_count++;
2069
202
    }
2070
329
  } else {
2071
329
    printUInt32Bang(O, Val);
2072
2073
329
    if (MI->csh->detail) {
2074
329
#ifndef CAPSTONE_DIET
2075
329
      uint8_t access;
2076
2077
329
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2078
329
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2079
329
      MI->ac_idx++;
2080
329
#endif
2081
329
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2082
329
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2083
329
      MI->flat_insn->detail->arm64.op_count++;
2084
329
    }
2085
329
  }
2086
531
}
2087
2088
49
static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) {
2089
49
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
2090
  // assert(MI->getOpcode() == AArch64::DSBnXS);
2091
2092
49
  const char *Name = NULL;
2093
49
  const DBnXS *DB = lookupDBnXSByEncoding(Val);
2094
49
  Name = DB ? DB->Name : NULL;
2095
2096
49
  if (Name) {
2097
49
    SStream_concat0(O, Name);
2098
2099
49
    if (MI->csh->detail) {
2100
49
#ifndef CAPSTONE_DIET
2101
49
      uint8_t access;
2102
2103
49
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2104
49
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2105
49
      MI->ac_idx++;
2106
49
#endif
2107
49
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2108
49
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2109
49
      MI->flat_insn->detail->arm64.op_count++;
2110
49
    }
2111
49
  }
2112
0
  else {
2113
0
    printUInt32Bang(O, Val);
2114
2115
0
    if (MI->csh->detail) {
2116
0
#ifndef CAPSTONE_DIET
2117
0
      uint8_t access;
2118
2119
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2120
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2121
0
      MI->ac_idx++;
2122
0
#endif
2123
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2124
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2125
0
      MI->flat_insn->detail->arm64.op_count++;
2126
0
    }
2127
0
  }
2128
49
}
2129
2130
static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2131
2.43k
{
2132
2.43k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2133
2.43k
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2134
2135
  // Horrible hack for the one register that has identical encodings but
2136
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2137
  // going to get the wrong entry
2138
2.43k
  if (Val == ARM64_SYSREG_DBGDTRRX_EL0) {
2139
32
    SStream_concat0(O, "dbgdtrrx_el0");
2140
2141
32
    if (MI->csh->detail) {
2142
32
#ifndef CAPSTONE_DIET
2143
32
      uint8_t access;
2144
2145
32
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2146
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2147
32
      MI->ac_idx++;
2148
32
#endif
2149
2150
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2151
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2152
32
      MI->flat_insn->detail->arm64.op_count++;
2153
32
    }
2154
2155
32
    return;
2156
32
  }
2157
2158
  // Another hack for a register which has an alternative name which is not an alias,
2159
  // and is not in the Armv9-A documentation.
2160
2.39k
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2161
27
    SStream_concat0(O, "ttbr0_el2");
2162
2163
27
    if (MI->csh->detail) {
2164
27
#ifndef CAPSTONE_DIET
2165
27
      uint8_t access;
2166
2167
27
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2168
27
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2169
27
      MI->ac_idx++;
2170
27
#endif
2171
2172
27
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2173
27
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2174
27
      MI->flat_insn->detail->arm64.op_count++;
2175
27
    }
2176
2177
27
    return;
2178
27
  }
2179
2180
  // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
2181
2.37k
  if (Reg && Reg->Readable) {
2182
302
    SStream_concat0(O, Reg->Name);
2183
2184
302
    if (MI->csh->detail) {
2185
302
#ifndef CAPSTONE_DIET
2186
302
      uint8_t access;
2187
2188
302
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2189
302
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2190
302
      MI->ac_idx++;
2191
302
#endif
2192
2193
302
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2194
302
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2195
302
      MI->flat_insn->detail->arm64.op_count++;
2196
302
    }
2197
2.06k
  } else {
2198
2.06k
    char result[128];
2199
2200
2.06k
    AArch64SysReg_genericRegisterString(Val, result);
2201
2.06k
    SStream_concat0(O, result);
2202
2203
2.06k
    if (MI->csh->detail) {
2204
2.06k
#ifndef CAPSTONE_DIET
2205
2.06k
      uint8_t access;
2206
2.06k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2207
2.06k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2208
2.06k
      MI->ac_idx++;
2209
2.06k
#endif
2210
2.06k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2211
2.06k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2212
2.06k
      MI->flat_insn->detail->arm64.op_count++;
2213
2.06k
    }
2214
2.06k
  }
2215
2.37k
}
2216
2217
static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2218
2.04k
{
2219
2.04k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2220
2.04k
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2221
2222
  // Horrible hack for the one register that has identical encodings but
2223
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2224
  // going to get the wrong entry
2225
2.04k
  if (Val == ARM64_SYSREG_DBGDTRTX_EL0) {
2226
57
    SStream_concat0(O, "dbgdtrtx_el0");
2227
2228
57
    if (MI->csh->detail) {
2229
57
#ifndef CAPSTONE_DIET
2230
57
      uint8_t access;
2231
2232
57
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2233
57
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2234
57
      MI->ac_idx++;
2235
57
#endif
2236
2237
57
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2238
57
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2239
57
      MI->flat_insn->detail->arm64.op_count++;
2240
57
    }
2241
2242
57
    return;
2243
57
  }
2244
2245
  // Another hack for a register which has an alternative name which is not an alias,
2246
  // and is not in the Armv9-A documentation.
2247
1.99k
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2248
21
    SStream_concat0(O, "ttbr0_el2");
2249
2250
21
    if (MI->csh->detail) {
2251
21
#ifndef CAPSTONE_DIET
2252
21
      uint8_t access;
2253
2254
21
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2255
21
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2256
21
      MI->ac_idx++;
2257
21
#endif
2258
2259
21
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2260
21
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2261
21
      MI->flat_insn->detail->arm64.op_count++;
2262
21
    }
2263
2264
21
    return;
2265
21
  }
2266
2267
  // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
2268
1.97k
  if (Reg && Reg->Writeable) {
2269
85
    SStream_concat0(O, Reg->Name);
2270
2271
85
    if (MI->csh->detail) {
2272
85
#ifndef CAPSTONE_DIET
2273
85
      uint8_t access;
2274
2275
85
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2276
85
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2277
85
      MI->ac_idx++;
2278
85
#endif
2279
2280
85
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2281
85
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2282
85
      MI->flat_insn->detail->arm64.op_count++;
2283
85
    }
2284
1.88k
  } else {
2285
1.88k
    char result[128];
2286
2287
1.88k
    AArch64SysReg_genericRegisterString(Val, result);
2288
1.88k
    SStream_concat0(O, result);
2289
2290
1.88k
    if (MI->csh->detail) {
2291
1.88k
#ifndef CAPSTONE_DIET
2292
1.88k
      uint8_t access;
2293
1.88k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2294
1.88k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2295
1.88k
      MI->ac_idx++;
2296
1.88k
#endif
2297
1.88k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2298
1.88k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2299
1.88k
      MI->flat_insn->detail->arm64.op_count++;
2300
1.88k
    }
2301
1.88k
  }
2302
1.97k
}
2303
2304
static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
2305
71
{
2306
71
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2307
2308
71
  const PState *PState = lookupPStateByEncoding(Val);
2309
2310
71
  if (PState) {
2311
71
    SStream_concat0(O, PState->Name);
2312
2313
71
    if (MI->csh->detail) {
2314
71
#ifndef CAPSTONE_DIET
2315
71
      uint8_t access;
2316
71
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2317
71
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2318
71
      MI->ac_idx++;
2319
71
#endif
2320
71
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE;
2321
71
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val;
2322
71
      MI->flat_insn->detail->arm64.op_count++;
2323
71
    }
2324
71
  } else {
2325
0
    printUInt32Bang(O, Val);
2326
2327
0
    if (MI->csh->detail) {
2328
0
#ifndef CAPSTONE_DIET
2329
0
      unsigned char access;
2330
2331
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2332
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2333
0
      MI->ac_idx++;
2334
0
#endif
2335
2336
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2337
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2338
0
      MI->flat_insn->detail->arm64.op_count++;
2339
0
    }
2340
0
  }
2341
71
}
2342
2343
static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O)
2344
2.39k
{
2345
2.39k
  uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2346
2.39k
  uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
2347
2348
2.39k
  SStream_concat(O, "#%#016llx", Val);
2349
2350
2.39k
  if (MI->csh->detail) {
2351
2.39k
#ifndef CAPSTONE_DIET
2352
2.39k
    unsigned char access;
2353
2354
2.39k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2355
2.39k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2356
2.39k
    MI->ac_idx++;
2357
2.39k
#endif
2358
2.39k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2359
2.39k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2360
2.39k
    MI->flat_insn->detail->arm64.op_count++;
2361
2.39k
  }
2362
2.39k
}
2363
2364
static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder)
2365
3.17k
{
2366
3.17k
  unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2367
3.17k
  printInt64Bang(O, (Val * Angle) + Remainder);
2368
3.17k
  op_addImm(MI, (Val * Angle) + Remainder);
2369
3.17k
}
2370
2371
static void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
2372
0
{
2373
0
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
2374
    // assert(MCOperand_isImm(MO) && "Unexpected operand type!");
2375
0
    unsigned svcrop = MCOperand_getImm(MO);
2376
0
  const SVCR *svcr = lookupSVCRByEncoding(svcrop);
2377
    // assert(svcr && "Unexpected SVCR operand!");
2378
0
  SStream_concat0(O, svcr->Name);
2379
2380
0
  if (MI->csh->detail) {
2381
0
#ifndef CAPSTONE_DIET
2382
0
    uint8_t access;
2383
2384
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2385
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2386
0
    MI->ac_idx++;
2387
0
#endif
2388
2389
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SVCR;
2390
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = (unsigned)ARM64_SYSREG_SVCR;
2391
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].svcr = svcr->Encoding;
2392
0
    MI->flat_insn->detail->arm64.op_count++;
2393
0
  }
2394
0
}
2395
2396
static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize)
2397
202
{
2398
202
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2399
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2400
202
  unsigned Reg = MCOperand_getReg(RegOp);
2401
2402
202
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2403
202
  const char *sizeStr = "";
2404
202
    switch (EltSize) {
2405
202
    case 0:
2406
202
    sizeStr = "";
2407
202
      break;
2408
0
    case 8:
2409
0
      sizeStr = ".b";
2410
0
      break;
2411
0
    case 16:
2412
0
      sizeStr = ".h";
2413
0
      break;
2414
0
    case 32:
2415
0
      sizeStr = ".s";
2416
0
      break;
2417
0
    case 64:
2418
0
      sizeStr = ".d";
2419
0
      break;
2420
0
    case 128:
2421
0
      sizeStr = ".q";
2422
0
      break;
2423
0
    default:
2424
0
    break;
2425
    //   llvm_unreachable("Unsupported element size");
2426
202
    }
2427
202
  SStream_concat0(O, sizeStr);
2428
2429
202
  if (MI->csh->detail) {
2430
202
#ifndef CAPSTONE_DIET
2431
202
    uint8_t access;
2432
2433
202
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2434
202
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2435
202
    MI->ac_idx++;
2436
202
#endif
2437
2438
202
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2439
202
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2440
202
    MI->flat_insn->detail->arm64.op_count++;
2441
202
  }
2442
202
}
2443
2444
static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O)
2445
10.3k
{
2446
10.3k
  int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2447
10.3k
  printInt64(O, imm);
2448
2449
10.3k
  if (MI->csh->detail) {
2450
10.3k
    if (MI->csh->doing_SME_Index) {
2451
      // Access op_count-1 as We want to add info to previous operand, not create a new one
2452
10.3k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = imm;
2453
10.3k
    }
2454
10.3k
  }
2455
10.3k
}
2456
2457
static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
2458
2.28k
{
2459
2.28k
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2460
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2461
2.28k
  unsigned Reg = MCOperand_getReg(RegOp);
2462
2.28k
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2463
2464
2.28k
  if (MI->csh->detail) {
2465
2.28k
#ifndef CAPSTONE_DIET
2466
2.28k
    uint8_t access;
2467
2468
2.28k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2469
2.28k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2470
2.28k
    MI->ac_idx++;
2471
2.28k
#endif
2472
2473
2.28k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2474
2.28k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2475
2.28k
    MI->flat_insn->detail->arm64.op_count++;
2476
2.28k
  }
2477
2.28k
}
2478
2479
static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool IsVertical)
2480
9.62k
{
2481
9.62k
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2482
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2483
9.62k
  unsigned Reg = MCOperand_getReg(RegOp);
2484
9.62k
#ifndef CAPSTONE_DIET
2485
9.62k
  const char *RegName = getRegisterName(Reg, AArch64_NoRegAltName);
2486
2487
9.62k
  const size_t strLn = strlen(RegName);
2488
  // +2 for extra chars, + 1 for null char \0
2489
9.62k
  char *RegNameNew = cs_mem_malloc(sizeof(char) * (strLn + 2 + 1));
2490
9.62k
  int index = 0, i;
2491
77.3k
  for (i = 0; i < (strLn + 2); i++){
2492
67.7k
    if(RegName[i] != '.'){
2493
58.0k
      RegNameNew[index] = RegName[i];
2494
58.0k
      index++;
2495
58.0k
    }
2496
9.62k
    else{
2497
9.62k
      RegNameNew[index] = IsVertical ? 'v' : 'h';
2498
9.62k
      RegNameNew[index + 1] = '.';
2499
9.62k
      index += 2;
2500
9.62k
    }
2501
67.7k
  }
2502
9.62k
  SStream_concat0(O, RegNameNew);
2503
9.62k
#endif
2504
2505
9.62k
  if (MI->csh->detail) {
2506
9.62k
#ifndef CAPSTONE_DIET
2507
9.62k
    uint8_t access;
2508
2509
9.62k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2510
9.62k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2511
9.62k
    MI->ac_idx++;
2512
9.62k
#endif
2513
2514
9.62k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2515
9.62k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2516
9.62k
    MI->flat_insn->detail->arm64.op_count++;
2517
9.62k
  }
2518
9.62k
#ifndef CAPSTONE_DIET
2519
9.62k
  cs_mem_free(RegNameNew);
2520
9.62k
#endif
2521
9.62k
}
2522
2523
static const unsigned MatrixZADRegisterTable[] = {
2524
  AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3,
2525
  AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7
2526
};
2527
2528
360
static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
2529
360
  unsigned MaxRegs = 8;
2530
360
  unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2531
2532
360
  unsigned NumRegs = 0, I;
2533
3.24k
  for (I = 0; I < MaxRegs; ++I)
2534
2.88k
    if ((RegMask & (1 << I)) != 0)
2535
984
      ++NumRegs;
2536
2537
360
  SStream_concat0(O, "{");
2538
360
  unsigned Printed = 0, J;
2539
3.24k
  for (J = 0; J < MaxRegs; ++J) {
2540
2.88k
    unsigned Reg = RegMask & (1 << J);
2541
2.88k
    if (Reg == 0)
2542
1.89k
      continue;
2543
984
    SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName));
2544
2545
984
    if (MI->csh->detail) {
2546
984
#ifndef CAPSTONE_DIET
2547
984
      uint8_t access;
2548
2549
984
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2550
984
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2551
984
      MI->ac_idx++;
2552
984
#endif
2553
2554
984
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2555
984
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[J];
2556
984
      MI->flat_insn->detail->arm64.op_count++;
2557
984
    }
2558
2559
984
    if (Printed + 1 != NumRegs)
2560
625
      SStream_concat0(O, ", ");
2561
984
    ++Printed;
2562
984
  }
2563
360
  SStream_concat0(O, "}");
2564
360
}
2565
2566
static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
2567
4.85k
{
2568
4.85k
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2569
2570
4.85k
  const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val);
2571
4.85k
  if (Pat)
2572
3.28k
    SStream_concat0(O, Pat->Name);
2573
1.56k
  else
2574
1.56k
    printUInt32Bang(O, Val);
2575
4.85k
}
2576
2577
// default suffix = 0
2578
static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix)
2579
184k
{
2580
184k
  unsigned int Reg;
2581
2582
#if 0
2583
  switch (suffix) {
2584
    case 0:
2585
    case 'b':
2586
    case 'h':
2587
    case 's':
2588
    case 'd':
2589
    case 'q':
2590
      break;
2591
    default:
2592
      // llvm_unreachable("Invalid kind specifier.");
2593
  }
2594
#endif
2595
2596
184k
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2597
2598
184k
  if (MI->csh->detail) {
2599
184k
#ifndef CAPSTONE_DIET
2600
184k
      uint8_t access;
2601
2602
184k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2603
184k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2604
184k
      MI->ac_idx++;
2605
184k
#endif
2606
184k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2607
184k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2608
184k
    MI->flat_insn->detail->arm64.op_count++;
2609
184k
  }
2610
2611
184k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2612
2613
184k
  if (suffix != '\0')
2614
117k
    SStream_concat(O, ".%c", suffix);
2615
184k
}
2616
2617
static void printImmSVE16(int16_t Val, SStream *O)
2618
3.74k
{
2619
3.74k
  printUInt32Bang(O, Val);
2620
3.74k
}
2621
2622
static void printImmSVE32(int32_t Val, SStream *O)
2623
1.52k
{
2624
1.52k
  printUInt32Bang(O, Val);
2625
1.52k
}
2626
2627
static void printImmSVE64(int64_t Val, SStream *O)
2628
2.38k
{
2629
2.38k
  printUInt64Bang(O, Val);
2630
2.38k
}
2631
2632
static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O)
2633
1.92k
{
2634
1.92k
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2635
1.92k
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2636
1.92k
  uint32_t Val;
2637
2638
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2639
  //  "Unexepected shift type!");
2640
2641
  // #0 lsl #8 is never pretty printed
2642
1.92k
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2643
404
    printUInt32Bang(O, UnscaledVal);
2644
404
    printShifter(MI, OpNum + 1, O);
2645
404
    return;
2646
404
  }
2647
2648
1.52k
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2649
1.52k
  printImmSVE32(Val, O);
2650
1.52k
}
2651
2652
static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O)
2653
2.14k
{
2654
2.14k
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2655
2.14k
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2656
2.14k
  uint64_t Val;
2657
2658
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2659
  //  "Unexepected shift type!");
2660
2661
  // #0 lsl #8 is never pretty printed
2662
2.14k
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2663
334
    printUInt32Bang(O, UnscaledVal);
2664
334
    printShifter(MI, OpNum + 1, O);
2665
334
    return;
2666
334
  }
2667
2668
1.80k
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2669
1.80k
  printImmSVE64(Val, O);
2670
1.80k
}
2671
2672
static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O)
2673
3.61k
{
2674
3.61k
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2675
3.61k
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2676
2677
  // Prefer the default format for 16bit values, hex otherwise.
2678
3.61k
  printImmSVE16(PrintVal, O);
2679
3.61k
}
2680
2681
static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
2682
1.11k
{
2683
1.11k
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2684
1.11k
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2685
2686
  // Prefer the default format for 16bit values, hex otherwise.
2687
1.11k
  if ((uint16_t)PrintVal == (uint32_t)PrintVal)
2688
129
    printImmSVE16(PrintVal, O);
2689
983
  else
2690
983
    printUInt64Bang(O, PrintVal);
2691
1.11k
}
2692
2693
static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
2694
572
{
2695
572
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2696
572
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2697
2698
572
  printImmSVE64(PrintVal, O);
2699
572
}
2700
2701
static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width)
2702
2.57k
{
2703
2.57k
  unsigned int Base, Reg;
2704
2705
2.57k
  switch (Width) {
2706
0
    default: // llvm_unreachable("Unsupported width");
2707
127
    case 8:   Base = AArch64_B0; break;
2708
1.08k
    case 16:  Base = AArch64_H0; break;
2709
726
    case 32:  Base = AArch64_S0; break;
2710
610
    case 64:  Base = AArch64_D0; break;
2711
26
    case 128: Base = AArch64_Q0; break;
2712
2.57k
  }
2713
2714
2.57k
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) - AArch64_Z0 + Base;
2715
2716
2.57k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2717
2718
2.57k
  if (MI->csh->detail) {
2719
2.57k
#ifndef CAPSTONE_DIET
2720
2.57k
    uint8_t access;
2721
2722
2.57k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2723
2.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2724
2.57k
    MI->ac_idx++;
2725
2.57k
#endif
2726
2.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2727
2.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2728
2.57k
    MI->flat_insn->detail->arm64.op_count++;
2729
2.57k
  }
2730
2.57k
}
2731
2732
static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1)
2733
753
{
2734
753
  const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0);
2735
753
  const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1);
2736
753
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2737
2738
753
  SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2739
753
}
2740
2741
static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O)
2742
4.14k
{
2743
4.14k
  unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2744
2745
4.14k
  SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName));
2746
4.14k
}
2747
2748
static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) 
2749
431
{
2750
431
    unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2751
2752
431
    SStream_concat0(O, getRegisterName(MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0), AArch64_NoRegAltName));
2753
431
}
2754
2755
#define PRINT_ALIAS_INSTR
2756
#include "AArch64GenAsmWriter.inc"
2757
#include "AArch64GenRegisterName.inc"
2758
2759
void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci)
2760
443k
{
2761
443k
  if (((cs_struct *)handle)->detail != CS_OPT_ON)
2762
0
    return;
2763
2764
443k
  if (mci->csh->detail) {
2765
443k
    unsigned opcode = MCInst_getOpcode(mci);
2766
2767
443k
    switch (opcode) {
2768
356k
      default:
2769
356k
        break;
2770
356k
      case AArch64_LD1Fourv16b_POST:
2771
687
      case AArch64_LD1Fourv1d_POST:
2772
837
      case AArch64_LD1Fourv2d_POST:
2773
1.56k
      case AArch64_LD1Fourv2s_POST:
2774
1.61k
      case AArch64_LD1Fourv4h_POST:
2775
2.20k
      case AArch64_LD1Fourv4s_POST:
2776
2.52k
      case AArch64_LD1Fourv8b_POST:
2777
3.38k
      case AArch64_LD1Fourv8h_POST:
2778
3.89k
      case AArch64_LD1Onev16b_POST:
2779
4.12k
      case AArch64_LD1Onev1d_POST:
2780
4.60k
      case AArch64_LD1Onev2d_POST:
2781
5.89k
      case AArch64_LD1Onev2s_POST:
2782
6.06k
      case AArch64_LD1Onev4h_POST:
2783
6.26k
      case AArch64_LD1Onev4s_POST:
2784
7.76k
      case AArch64_LD1Onev8b_POST:
2785
8.36k
      case AArch64_LD1Onev8h_POST:
2786
8.47k
      case AArch64_LD1Rv16b_POST:
2787
8.55k
      case AArch64_LD1Rv1d_POST:
2788
8.77k
      case AArch64_LD1Rv2d_POST:
2789
9.08k
      case AArch64_LD1Rv2s_POST:
2790
9.17k
      case AArch64_LD1Rv4h_POST:
2791
9.37k
      case AArch64_LD1Rv4s_POST:
2792
9.45k
      case AArch64_LD1Rv8b_POST:
2793
9.88k
      case AArch64_LD1Rv8h_POST:
2794
10.2k
      case AArch64_LD1Threev16b_POST:
2795
10.2k
      case AArch64_LD1Threev1d_POST:
2796
10.3k
      case AArch64_LD1Threev2d_POST:
2797
10.8k
      case AArch64_LD1Threev2s_POST:
2798
10.9k
      case AArch64_LD1Threev4h_POST:
2799
10.9k
      case AArch64_LD1Threev4s_POST:
2800
11.1k
      case AArch64_LD1Threev8b_POST:
2801
11.6k
      case AArch64_LD1Threev8h_POST:
2802
11.7k
      case AArch64_LD1Twov16b_POST:
2803
13.1k
      case AArch64_LD1Twov1d_POST:
2804
13.2k
      case AArch64_LD1Twov2d_POST:
2805
13.3k
      case AArch64_LD1Twov2s_POST:
2806
13.4k
      case AArch64_LD1Twov4h_POST:
2807
13.7k
      case AArch64_LD1Twov4s_POST:
2808
13.9k
      case AArch64_LD1Twov8b_POST:
2809
14.0k
      case AArch64_LD1Twov8h_POST:
2810
14.1k
      case AArch64_LD1i16_POST:
2811
15.5k
      case AArch64_LD1i32_POST:
2812
16.3k
      case AArch64_LD1i64_POST:
2813
17.2k
      case AArch64_LD1i8_POST:
2814
17.7k
      case AArch64_LD2Rv16b_POST:
2815
17.7k
      case AArch64_LD2Rv1d_POST:
2816
18.0k
      case AArch64_LD2Rv2d_POST:
2817
18.2k
      case AArch64_LD2Rv2s_POST:
2818
18.3k
      case AArch64_LD2Rv4h_POST:
2819
20.7k
      case AArch64_LD2Rv4s_POST:
2820
20.7k
      case AArch64_LD2Rv8b_POST:
2821
20.8k
      case AArch64_LD2Rv8h_POST:
2822
21.0k
      case AArch64_LD2Twov16b_POST:
2823
21.1k
      case AArch64_LD2Twov2d_POST:
2824
21.1k
      case AArch64_LD2Twov2s_POST:
2825
22.2k
      case AArch64_LD2Twov4h_POST:
2826
22.2k
      case AArch64_LD2Twov4s_POST:
2827
22.6k
      case AArch64_LD2Twov8b_POST:
2828
23.1k
      case AArch64_LD2Twov8h_POST:
2829
23.6k
      case AArch64_LD2i16_POST:
2830
23.7k
      case AArch64_LD2i32_POST:
2831
25.3k
      case AArch64_LD2i64_POST:
2832
25.5k
      case AArch64_LD2i8_POST:
2833
26.1k
      case AArch64_LD3Rv16b_POST:
2834
26.4k
      case AArch64_LD3Rv1d_POST:
2835
26.4k
      case AArch64_LD3Rv2d_POST:
2836
26.5k
      case AArch64_LD3Rv2s_POST:
2837
26.5k
      case AArch64_LD3Rv4h_POST:
2838
26.5k
      case AArch64_LD3Rv4s_POST:
2839
26.6k
      case AArch64_LD3Rv8b_POST:
2840
26.6k
      case AArch64_LD3Rv8h_POST:
2841
26.8k
      case AArch64_LD3Threev16b_POST:
2842
27.0k
      case AArch64_LD3Threev2d_POST:
2843
27.1k
      case AArch64_LD3Threev2s_POST:
2844
27.2k
      case AArch64_LD3Threev4h_POST:
2845
27.3k
      case AArch64_LD3Threev4s_POST:
2846
27.3k
      case AArch64_LD3Threev8b_POST:
2847
27.3k
      case AArch64_LD3Threev8h_POST:
2848
28.2k
      case AArch64_LD3i16_POST:
2849
28.7k
      case AArch64_LD3i32_POST:
2850
29.0k
      case AArch64_LD3i64_POST:
2851
30.5k
      case AArch64_LD3i8_POST:
2852
30.7k
      case AArch64_LD4Fourv16b_POST:
2853
30.8k
      case AArch64_LD4Fourv2d_POST:
2854
31.2k
      case AArch64_LD4Fourv2s_POST:
2855
31.2k
      case AArch64_LD4Fourv4h_POST:
2856
31.4k
      case AArch64_LD4Fourv4s_POST:
2857
32.1k
      case AArch64_LD4Fourv8b_POST:
2858
32.2k
      case AArch64_LD4Fourv8h_POST:
2859
32.3k
      case AArch64_LD4Rv16b_POST:
2860
32.5k
      case AArch64_LD4Rv1d_POST:
2861
32.6k
      case AArch64_LD4Rv2d_POST:
2862
32.6k
      case AArch64_LD4Rv2s_POST:
2863
32.7k
      case AArch64_LD4Rv4h_POST:
2864
32.8k
      case AArch64_LD4Rv4s_POST:
2865
32.9k
      case AArch64_LD4Rv8b_POST:
2866
33.1k
      case AArch64_LD4Rv8h_POST:
2867
33.6k
      case AArch64_LD4i16_POST:
2868
34.2k
      case AArch64_LD4i32_POST:
2869
34.6k
      case AArch64_LD4i64_POST:
2870
34.8k
      case AArch64_LD4i8_POST:
2871
34.9k
      case AArch64_LDRBBpost:
2872
35.1k
      case AArch64_LDRBpost:
2873
35.2k
      case AArch64_LDRDpost:
2874
35.4k
      case AArch64_LDRHHpost:
2875
35.9k
      case AArch64_LDRHpost:
2876
36.0k
      case AArch64_LDRQpost:
2877
36.5k
      case AArch64_LDPDpost:
2878
36.8k
      case AArch64_LDPQpost:
2879
36.9k
      case AArch64_LDPSWpost:
2880
37.1k
      case AArch64_LDPSpost:
2881
37.6k
      case AArch64_LDPWpost:
2882
38.0k
      case AArch64_LDPXpost:
2883
38.2k
      case AArch64_ST1Fourv16b_POST:
2884
38.3k
      case AArch64_ST1Fourv1d_POST:
2885
38.4k
      case AArch64_ST1Fourv2d_POST:
2886
38.5k
      case AArch64_ST1Fourv2s_POST:
2887
38.5k
      case AArch64_ST1Fourv4h_POST:
2888
39.0k
      case AArch64_ST1Fourv4s_POST:
2889
39.1k
      case AArch64_ST1Fourv8b_POST:
2890
39.3k
      case AArch64_ST1Fourv8h_POST:
2891
39.5k
      case AArch64_ST1Onev16b_POST:
2892
39.9k
      case AArch64_ST1Onev1d_POST:
2893
40.0k
      case AArch64_ST1Onev2d_POST:
2894
40.0k
      case AArch64_ST1Onev2s_POST:
2895
41.4k
      case AArch64_ST1Onev4h_POST:
2896
41.6k
      case AArch64_ST1Onev4s_POST:
2897
41.6k
      case AArch64_ST1Onev8b_POST:
2898
41.8k
      case AArch64_ST1Onev8h_POST:
2899
41.9k
      case AArch64_ST1Threev16b_POST:
2900
42.3k
      case AArch64_ST1Threev1d_POST:
2901
42.6k
      case AArch64_ST1Threev2d_POST:
2902
42.7k
      case AArch64_ST1Threev2s_POST:
2903
42.7k
      case AArch64_ST1Threev4h_POST:
2904
42.9k
      case AArch64_ST1Threev4s_POST:
2905
43.0k
      case AArch64_ST1Threev8b_POST:
2906
43.3k
      case AArch64_ST1Threev8h_POST:
2907
43.4k
      case AArch64_ST1Twov16b_POST:
2908
44.5k
      case AArch64_ST1Twov1d_POST:
2909
44.7k
      case AArch64_ST1Twov2d_POST:
2910
44.8k
      case AArch64_ST1Twov2s_POST:
2911
45.1k
      case AArch64_ST1Twov4h_POST:
2912
45.8k
      case AArch64_ST1Twov4s_POST:
2913
45.8k
      case AArch64_ST1Twov8b_POST:
2914
46.6k
      case AArch64_ST1Twov8h_POST:
2915
47.0k
      case AArch64_ST1i16_POST:
2916
47.6k
      case AArch64_ST1i32_POST:
2917
50.6k
      case AArch64_ST1i64_POST:
2918
51.8k
      case AArch64_ST1i8_POST:
2919
52.0k
      case AArch64_ST2GPostIndex:
2920
52.0k
      case AArch64_ST2Twov16b_POST:
2921
52.1k
      case AArch64_ST2Twov2d_POST:
2922
52.2k
      case AArch64_ST2Twov2s_POST:
2923
52.3k
      case AArch64_ST2Twov4h_POST:
2924
52.5k
      case AArch64_ST2Twov4s_POST:
2925
53.1k
      case AArch64_ST2Twov8b_POST:
2926
53.3k
      case AArch64_ST2Twov8h_POST:
2927
53.6k
      case AArch64_ST2i16_POST:
2928
54.1k
      case AArch64_ST2i32_POST:
2929
54.5k
      case AArch64_ST2i64_POST:
2930
55.4k
      case AArch64_ST2i8_POST:
2931
55.5k
      case AArch64_ST3Threev16b_POST:
2932
56.2k
      case AArch64_ST3Threev2d_POST:
2933
56.3k
      case AArch64_ST3Threev2s_POST:
2934
56.4k
      case AArch64_ST3Threev4h_POST:
2935
56.4k
      case AArch64_ST3Threev4s_POST:
2936
56.9k
      case AArch64_ST3Threev8b_POST:
2937
57.0k
      case AArch64_ST3Threev8h_POST:
2938
57.7k
      case AArch64_ST3i16_POST:
2939
57.9k
      case AArch64_ST3i32_POST:
2940
58.2k
      case AArch64_ST3i64_POST:
2941
58.7k
      case AArch64_ST3i8_POST:
2942
58.9k
      case AArch64_ST4Fourv16b_POST:
2943
59.1k
      case AArch64_ST4Fourv2d_POST:
2944
59.3k
      case AArch64_ST4Fourv2s_POST:
2945
59.5k
      case AArch64_ST4Fourv4h_POST:
2946
60.1k
      case AArch64_ST4Fourv4s_POST:
2947
61.0k
      case AArch64_ST4Fourv8b_POST:
2948
61.2k
      case AArch64_ST4Fourv8h_POST:
2949
64.3k
      case AArch64_ST4i16_POST:
2950
64.5k
      case AArch64_ST4i32_POST:
2951
65.9k
      case AArch64_ST4i64_POST:
2952
66.2k
      case AArch64_ST4i8_POST:
2953
66.8k
      case AArch64_STPDpost:
2954
67.7k
      case AArch64_STPQpost:
2955
68.1k
      case AArch64_STPSpost:
2956
68.6k
      case AArch64_STPWpost:
2957
69.4k
      case AArch64_STPXpost:
2958
69.5k
      case AArch64_STRBBpost:
2959
69.8k
      case AArch64_STRBpost:
2960
69.9k
      case AArch64_STRDpost:
2961
70.1k
      case AArch64_STRHHpost:
2962
70.2k
      case AArch64_STRHpost:
2963
70.3k
      case AArch64_STRQpost:
2964
70.3k
      case AArch64_STRSpost:
2965
70.5k
      case AArch64_STRWpost:
2966
70.7k
      case AArch64_STRXpost:
2967
70.9k
      case AArch64_STZ2GPostIndex:
2968
71.0k
      case AArch64_STZGPostIndex:
2969
71.2k
      case AArch64_STGPostIndex:
2970
71.2k
      case AArch64_STGPpost:
2971
71.5k
      case AArch64_LDRSBWpost:
2972
71.6k
      case AArch64_LDRSBXpost:
2973
71.8k
      case AArch64_LDRSHWpost:
2974
72.1k
      case AArch64_LDRSHXpost:
2975
72.4k
      case AArch64_LDRSWpost:
2976
72.4k
      case AArch64_LDRSpost:
2977
72.6k
      case AArch64_LDRWpost:
2978
72.7k
      case AArch64_LDRXpost:
2979
72.7k
        flat_insn->detail->arm64.writeback = true;
2980
72.7k
          flat_insn->detail->arm64.post_index = true;
2981
72.7k
        break;
2982
1.47k
      case AArch64_LDRAAwriteback:
2983
2.63k
      case AArch64_LDRABwriteback:
2984
3.68k
      case AArch64_ST2GPreIndex:
2985
4.12k
      case AArch64_LDPDpre:
2986
4.40k
      case AArch64_LDPQpre:
2987
4.90k
      case AArch64_LDPSWpre:
2988
5.13k
      case AArch64_LDPSpre:
2989
5.63k
      case AArch64_LDPWpre:
2990
6.38k
      case AArch64_LDPXpre:
2991
6.43k
      case AArch64_LDRBBpre:
2992
6.57k
      case AArch64_LDRBpre:
2993
6.92k
      case AArch64_LDRDpre:
2994
7.21k
      case AArch64_LDRHHpre:
2995
7.27k
      case AArch64_LDRHpre:
2996
7.40k
      case AArch64_LDRQpre:
2997
8.39k
      case AArch64_LDRSBWpre:
2998
8.65k
      case AArch64_LDRSBXpre:
2999
9.10k
      case AArch64_LDRSHWpre:
3000
9.20k
      case AArch64_LDRSHXpre:
3001
9.24k
      case AArch64_LDRSWpre:
3002
9.34k
      case AArch64_LDRSpre:
3003
9.58k
      case AArch64_LDRWpre:
3004
9.76k
      case AArch64_LDRXpre:
3005
9.94k
      case AArch64_STGPreIndex:
3006
10.5k
      case AArch64_STPDpre:
3007
11.1k
      case AArch64_STPQpre:
3008
11.4k
      case AArch64_STPSpre:
3009
11.6k
      case AArch64_STPWpre:
3010
12.1k
      case AArch64_STPXpre:
3011
12.2k
      case AArch64_STRBBpre:
3012
12.3k
      case AArch64_STRBpre:
3013
12.5k
      case AArch64_STRDpre:
3014
12.6k
      case AArch64_STRHHpre:
3015
13.0k
      case AArch64_STRHpre:
3016
13.4k
      case AArch64_STRQpre:
3017
13.5k
      case AArch64_STRSpre:
3018
13.5k
      case AArch64_STRWpre:
3019
14.5k
      case AArch64_STRXpre:
3020
14.5k
      case AArch64_STZ2GPreIndex:
3021
15.0k
      case AArch64_STZGPreIndex:
3022
15.0k
      case AArch64_STGPpre:
3023
15.0k
        flat_insn->detail->arm64.writeback = true;
3024
15.0k
        break;
3025
443k
    }
3026
443k
  }
3027
443k
}
3028
3029
#endif