Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/ARM/ARMInstPrinter.c
Line
Count
Source (jump to first uncovered line)
1
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an ARM MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
16
17
#ifdef CAPSTONE_HAS_ARM
18
19
#include <stdio.h>  // DEBUG
20
#include <stdlib.h>
21
#include <string.h>
22
#include <capstone/platform.h>
23
24
#include "ARMInstPrinter.h"
25
#include "ARMAddressingModes.h"
26
#include "ARMBaseInfo.h"
27
#include "ARMDisassembler.h"
28
#include "../../MCInst.h"
29
#include "../../SStream.h"
30
#include "../../MCRegisterInfo.h"
31
#include "../../utils.h"
32
#include "ARMMapping.h"
33
34
#define GET_SUBTARGETINFO_ENUM
35
#include "ARMGenSubtargetInfo.inc"
36
37
#include "ARMGenSystemRegister.inc"
38
39
static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo);
40
41
// Autogenerated by tblgen.
42
static void printInstruction(MCInst *MI, SStream *O);
43
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
44
static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
45
static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
46
47
static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
48
static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
49
static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
50
static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
51
static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
52
static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
53
static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
54
static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0);
55
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
56
static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
57
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
58
static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
59
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
60
static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
61
static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
62
63
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
64
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
65
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
66
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
67
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
68
static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned);
69
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
70
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
71
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
72
static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
73
static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale);
74
static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
75
static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
76
static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
77
static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
78
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
79
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
80
static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
81
static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
82
static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
83
static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
84
static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
85
static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
86
static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
87
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
88
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
89
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
90
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
91
static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
92
static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
93
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
94
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
95
static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
96
static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
97
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
98
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
99
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
100
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
101
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
102
static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O);
103
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
104
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
105
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
106
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
107
static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
108
static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O);
109
static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O);
110
static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
111
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
112
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
113
static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
114
static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
115
static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
116
static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
117
static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
118
static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
119
static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
120
static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
121
static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
122
static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
123
124
static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
125
static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
126
static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder);
127
static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
128
129
130
#ifndef CAPSTONE_DIET
131
// copy & normalize access info
132
static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
133
529k
{
134
529k
  const uint8_t *arr = ARM_get_op_access(h, id);
135
136
529k
  if (!arr || arr[index] == CS_AC_IGNORE)
137
1.72k
    return 0;
138
139
528k
  return arr[index];
140
529k
}
141
#endif
142
143
static void set_mem_access(MCInst *MI, bool status)
144
208k
{
145
208k
  if (MI->csh->detail != CS_OPT_ON)
146
0
    return;
147
148
208k
  MI->csh->doing_mem = status;
149
208k
  if (status) {
150
104k
#ifndef CAPSTONE_DIET
151
104k
    uint8_t access;
152
104k
#endif
153
154
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
155
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
156
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
157
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
158
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
159
160
104k
#ifndef CAPSTONE_DIET
161
104k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
162
104k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
163
104k
    MI->ac_idx++;
164
104k
#endif
165
104k
  } else {
166
    // done, create the next operand slot
167
104k
    MI->flat_insn->detail->arm.op_count++;
168
104k
  }
169
208k
}
170
171
static void op_addImm(MCInst *MI, int v)
172
690
{
173
690
  if (MI->csh->detail) {
174
690
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
175
690
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
176
690
    MI->flat_insn->detail->arm.op_count++;
177
690
  }
178
690
}
179
180
#define GET_INSTRINFO_ENUM
181
#include "ARMGenInstrInfo.inc"
182
183
static void printCustomAliasOperand(MCInst *MI,
184
    unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS);
185
186
#define PRINT_ALIAS_INSTR
187
#include "ARMGenAsmWriter.inc"
188
#include "ARMGenRegisterName.inc"
189
#include "ARMGenRegisterName_digit.inc"
190
191
void ARM_getRegName(cs_struct *handle, int value)
192
4.99k
{
193
4.99k
  if (value == CS_OPT_SYNTAX_NOREGNAME) {
194
0
    handle->get_regname = getRegisterName_digit;
195
0
    handle->reg_name = ARM_reg_name2;
196
4.99k
  } else {
197
4.99k
    handle->get_regname = getRegisterName;
198
4.99k
    handle->reg_name = ARM_reg_name;
199
4.99k
  }
200
4.99k
}
201
202
/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
203
///
204
/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
205
static unsigned translateShiftImm(unsigned imm)
206
23.3k
{
207
  // lsr #32 and asr #32 exist, but should be encoded as a 0.
208
  //assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
209
23.3k
  if (imm == 0)
210
1.32k
    return 32;
211
21.9k
  return imm;
212
23.3k
}
213
214
/// Prints the shift value with an immediate value.
215
static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
216
12.1k
{
217
12.1k
  if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
218
305
    return;
219
220
11.8k
  SStream_concat0(O, ", ");
221
222
  //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
223
11.8k
  SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
224
225
11.8k
  if (MI->csh->detail) {
226
11.8k
    if (MI->csh->doing_mem)
227
2.43k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
228
9.42k
    else
229
9.42k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
230
11.8k
  }
231
232
11.8k
  if (ShOpc != ARM_AM_rrx) {
233
11.5k
    SStream_concat0(O, " ");
234
11.5k
    SStream_concat(O, "#%u", translateShiftImm(ShImm));
235
11.5k
    if (MI->csh->detail) {
236
11.5k
      if (MI->csh->doing_mem)
237
2.42k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
238
9.12k
      else
239
9.12k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
240
11.5k
    }
241
11.5k
  }
242
11.8k
}
243
244
static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
245
3.07M
{
246
3.07M
#ifndef CAPSTONE_DIET
247
3.07M
  SStream_concat0(OS, h->get_regname(RegNo));
248
3.07M
#endif
249
3.07M
}
250
251
// TODO
252
static const name_map insn_update_flgs[] = {
253
  { ARM_INS_CMN, "cmn" },
254
  { ARM_INS_CMP, "cmp" },
255
  { ARM_INS_TEQ, "teq" },
256
  { ARM_INS_TST, "tst" },
257
258
  { ARM_INS_ADC, "adcs" },
259
  { ARM_INS_ADD, "adds" },
260
  { ARM_INS_AND, "ands" },
261
  { ARM_INS_ASR, "asrs" },
262
  { ARM_INS_BIC, "bics" },
263
  { ARM_INS_EOR, "eors" },
264
  { ARM_INS_LSL, "lsls" },
265
  { ARM_INS_LSR, "lsrs" },
266
  { ARM_INS_MLA, "mlas" },
267
  { ARM_INS_MOV, "movs" },
268
  { ARM_INS_MUL, "muls" },
269
  { ARM_INS_MVN, "mvns" },
270
  { ARM_INS_ORN, "orns" },
271
  { ARM_INS_ORR, "orrs" },
272
  { ARM_INS_ROR, "rors" },
273
  { ARM_INS_RRX, "rrxs" },
274
  { ARM_INS_RSB, "rsbs" },
275
  { ARM_INS_RSC, "rscs" },
276
  { ARM_INS_SBC, "sbcs" },
277
  { ARM_INS_SMLAL, "smlals" },
278
  { ARM_INS_SMULL, "smulls" },
279
  { ARM_INS_SUB, "subs" },
280
  { ARM_INS_UMLAL, "umlals" },
281
  { ARM_INS_UMULL, "umulls" },
282
283
  { ARM_INS_UADD8, "uadd8" },
284
};
285
286
void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
287
306k
{
288
306k
  if (((cs_struct *)ud)->detail != CS_OPT_ON)
289
0
    return;
290
291
  // check if this insn requests write-back
292
306k
  if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) {
293
23.0k
    insn->detail->arm.writeback = true;
294
283k
  } else if (mci->csh->mode & CS_MODE_THUMB) {
295
    // handle some special instructions with writeback
296
        //printf(">> Opcode = %u\n", mci->Opcode);
297
226k
    switch(mci->Opcode) {
298
223k
      default:
299
223k
        break;
300
223k
      case ARM_t2LDC2L_PRE:
301
0
      case ARM_t2LDC2_PRE:
302
0
      case ARM_t2LDCL_PRE:
303
0
      case ARM_t2LDC_PRE:
304
305
0
      case ARM_t2LDRB_PRE:
306
0
      case ARM_t2LDRD_PRE:
307
0
      case ARM_t2LDRH_PRE:
308
0
      case ARM_t2LDRSB_PRE:
309
0
      case ARM_t2LDRSH_PRE:
310
0
      case ARM_t2LDR_PRE:
311
312
0
      case ARM_t2STC2L_PRE:
313
0
      case ARM_t2STC2_PRE:
314
0
      case ARM_t2STCL_PRE:
315
0
      case ARM_t2STC_PRE:
316
317
0
      case ARM_t2STRB_PRE:
318
0
      case ARM_t2STRD_PRE:
319
0
      case ARM_t2STRH_PRE:
320
0
      case ARM_t2STR_PRE:
321
0
        insn->detail->arm.writeback = true;
322
0
        break;
323
269
      case ARM_t2LDC2L_POST:
324
347
      case ARM_t2LDC2_POST:
325
535
      case ARM_t2LDCL_POST:
326
668
      case ARM_t2LDC_POST:
327
328
841
      case ARM_t2LDRB_POST:
329
985
      case ARM_t2LDRD_POST:
330
996
      case ARM_t2LDRH_POST:
331
1.09k
      case ARM_t2LDRSB_POST:
332
1.11k
      case ARM_t2LDRSH_POST:
333
1.27k
      case ARM_t2LDR_POST:
334
335
1.49k
      case ARM_t2STC2L_POST:
336
1.61k
      case ARM_t2STC2_POST:
337
1.77k
      case ARM_t2STCL_POST:
338
2.06k
      case ARM_t2STC_POST:
339
340
2.13k
      case ARM_t2STRB_POST:
341
2.75k
      case ARM_t2STRD_POST:
342
2.80k
      case ARM_t2STRH_POST:
343
2.83k
      case ARM_t2STR_POST:
344
2.83k
        insn->detail->arm.writeback = true;
345
2.83k
        insn->detail->arm.post_index = true;
346
2.83k
        break;
347
226k
    }
348
226k
  } else { // ARM mode
349
    // handle some special instructions with writeback
350
        //printf(">> Opcode = %u\n", mci->Opcode);
351
57.4k
    switch(mci->Opcode) {
352
53.5k
      default:
353
53.5k
        break;
354
53.5k
      case ARM_LDC2L_PRE:
355
0
      case ARM_LDC2_PRE:
356
0
      case ARM_LDCL_PRE:
357
0
      case ARM_LDC_PRE:
358
359
0
      case ARM_LDRD_PRE:
360
0
      case ARM_LDRH_PRE:
361
0
      case ARM_LDRSB_PRE:
362
0
      case ARM_LDRSH_PRE:
363
364
0
      case ARM_STC2L_PRE:
365
0
      case ARM_STC2_PRE:
366
0
      case ARM_STCL_PRE:
367
0
      case ARM_STC_PRE:
368
369
0
      case ARM_STRD_PRE:
370
0
      case ARM_STRH_PRE:
371
0
        insn->detail->arm.writeback = true;
372
0
        break;
373
384
      case ARM_LDC2L_POST:
374
422
      case ARM_LDC2_POST:
375
771
      case ARM_LDCL_POST:
376
1.06k
      case ARM_LDC_POST:
377
378
1.06k
      case ARM_LDRBT_POST:
379
1.06k
      case ARM_LDRD_POST:
380
1.06k
      case ARM_LDRH_POST:
381
1.06k
      case ARM_LDRSB_POST:
382
1.06k
      case ARM_LDRSH_POST:
383
384
1.12k
      case ARM_STC2L_POST:
385
1.18k
      case ARM_STC2_POST:
386
1.42k
      case ARM_STCL_POST:
387
1.63k
      case ARM_STC_POST:
388
389
1.63k
      case ARM_STRBT_POST:
390
1.63k
      case ARM_STRD_POST:
391
1.63k
      case ARM_STRH_POST:
392
393
1.90k
      case ARM_LDRB_POST_IMM:
394
2.14k
      case ARM_LDR_POST_IMM:
395
2.29k
      case ARM_LDR_POST_REG:
396
2.67k
      case ARM_STRB_POST_IMM:
397
398
3.29k
      case ARM_STR_POST_IMM:
399
3.89k
      case ARM_STR_POST_REG:
400
3.89k
        insn->detail->arm.writeback = true;
401
3.89k
        insn->detail->arm.post_index = true;
402
3.89k
        break;
403
57.4k
    }
404
57.4k
  }
405
406
  // check if this insn requests update flags
407
306k
  if (insn->detail->arm.update_flags == false) {
408
    // some insn still update flags, regardless of tabgen info
409
211k
    unsigned int i, j;
410
411
6.35M
    for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
412
6.14M
      if (insn->id == insn_update_flgs[i].id &&
413
6.14M
          !strncmp(insn_asm, insn_update_flgs[i].name,
414
21.3k
            strlen(insn_update_flgs[i].name))) {
415
25
        insn->detail->arm.update_flags = true;
416
        // we have to update regs_write array as well
417
25
        for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
418
25
          if (insn->detail->regs_write[j] == 0) {
419
25
            insn->detail->regs_write[j] = ARM_REG_CPSR;
420
25
            break;
421
25
          }
422
25
        }
423
25
        break;
424
25
      }
425
6.14M
    }
426
211k
  }
427
428
  // instruction should not have invalid CC
429
306k
  if (insn->detail->arm.cc == ARM_CC_INVALID) {
430
36.0k
    insn->detail->arm.cc = ARM_CC_AL;
431
36.0k
  }
432
433
  // manual fix for some special instructions
434
  // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
435
306k
  switch(mci->Opcode) {
436
306k
    default:
437
306k
      break;
438
306k
    case ARM_MOVPCLR:
439
23
      insn->detail->arm.operands[0].type = ARM_OP_REG;
440
23
      insn->detail->arm.operands[0].reg = ARM_REG_PC;
441
23
      insn->detail->arm.operands[0].access = CS_AC_WRITE;
442
23
      insn->detail->arm.operands[1].type = ARM_OP_REG;
443
23
      insn->detail->arm.operands[1].reg = ARM_REG_LR;
444
23
      insn->detail->arm.operands[1].access = CS_AC_READ;
445
23
      insn->detail->arm.op_count = 2;
446
23
      break;
447
306k
  }
448
306k
}
449
450
void ARM_printInst(MCInst *MI, SStream *O, void *Info)
451
306k
{
452
306k
  MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
453
306k
  unsigned Opcode = MCInst_getOpcode(MI), tmp, i;
454
455
  //printf(">>> Opcode = %u\n", Opcode);
456
306k
  switch (Opcode) {
457
    // Check for MOVs and print canonical forms, instead.
458
75
    case ARM_MOVsr: {
459
      // FIXME: Thumb variants?
460
75
      unsigned int opc;
461
75
      MCOperand *Dst = MCInst_getOperand(MI, 0);
462
75
      MCOperand *MO1 = MCInst_getOperand(MI, 1);
463
75
      MCOperand *MO2 = MCInst_getOperand(MI, 2);
464
75
      MCOperand *MO3 = MCInst_getOperand(MI, 3);
465
466
75
      opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
467
75
      SStream_concat0(O, ARM_AM_getShiftOpcStr(opc));
468
469
75
      switch (opc) {
470
0
        default: break;
471
14
        case ARM_AM_asr:
472
14
           MCInst_setOpcodePub(MI, ARM_INS_ASR);
473
14
           break;
474
30
        case ARM_AM_lsl:
475
30
           MCInst_setOpcodePub(MI, ARM_INS_LSL);
476
30
           break;
477
2
        case ARM_AM_lsr:
478
2
           MCInst_setOpcodePub(MI, ARM_INS_LSR);
479
2
           break;
480
29
        case ARM_AM_ror:
481
29
           MCInst_setOpcodePub(MI, ARM_INS_ROR);
482
29
           break;
483
0
        case ARM_AM_rrx:
484
0
           MCInst_setOpcodePub(MI, ARM_INS_RRX);
485
0
           break;
486
75
      }
487
488
75
      printSBitModifierOperand(MI, 6, O);
489
75
      printPredicateOperand(MI, 4, O);
490
491
75
      SStream_concat0(O, "\t");
492
75
      printRegName(MI->csh, O, MCOperand_getReg(Dst));
493
494
75
      if (MI->csh->detail) {
495
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
496
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
497
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
498
75
        MI->flat_insn->detail->arm.op_count++;
499
75
      }
500
501
75
      SStream_concat0(O, ", ");
502
75
      printRegName(MI->csh, O, MCOperand_getReg(MO1));
503
504
75
      if (MI->csh->detail) {
505
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
506
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
507
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
508
75
        MI->flat_insn->detail->arm.op_count++;
509
75
      }
510
511
75
      SStream_concat0(O, ", ");
512
75
      printRegName(MI->csh, O, MCOperand_getReg(MO2));
513
514
75
      if (MI->csh->detail) {
515
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
516
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
517
75
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
518
75
        MI->flat_insn->detail->arm.op_count++;
519
75
      }
520
521
75
      return;
522
75
    }
523
524
250
    case ARM_MOVsi: {
525
      // FIXME: Thumb variants?
526
250
      unsigned int opc;
527
250
      MCOperand *Dst = MCInst_getOperand(MI, 0);
528
250
      MCOperand *MO1 = MCInst_getOperand(MI, 1);
529
250
      MCOperand *MO2 = MCInst_getOperand(MI, 2);
530
531
250
      opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
532
250
      SStream_concat0(O, ARM_AM_getShiftOpcStr(opc));
533
534
250
      switch(opc) {
535
0
        default:
536
0
          break;
537
16
        case ARM_AM_asr:
538
16
          MCInst_setOpcodePub(MI, ARM_INS_ASR);
539
16
          break;
540
40
        case ARM_AM_lsl:
541
40
          MCInst_setOpcodePub(MI, ARM_INS_LSL);
542
40
          break;
543
79
        case ARM_AM_lsr:
544
79
          MCInst_setOpcodePub(MI, ARM_INS_LSR);
545
79
          break;
546
72
        case ARM_AM_ror:
547
72
          MCInst_setOpcodePub(MI, ARM_INS_ROR);
548
72
          break;
549
43
        case ARM_AM_rrx:
550
43
          MCInst_setOpcodePub(MI, ARM_INS_RRX);
551
43
          break;
552
250
      }
553
554
250
      printSBitModifierOperand(MI, 5, O);
555
250
      printPredicateOperand(MI, 3, O);
556
557
250
      SStream_concat0(O, "\t");
558
250
      printRegName(MI->csh, O, MCOperand_getReg(Dst));
559
560
250
      if (MI->csh->detail) {
561
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
562
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
563
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
564
250
        MI->flat_insn->detail->arm.op_count++;
565
250
      }
566
567
250
      SStream_concat0(O, ", ");
568
250
      printRegName(MI->csh, O, MCOperand_getReg(MO1));
569
250
      if (MI->csh->detail) {
570
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
571
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
572
250
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
573
250
        MI->flat_insn->detail->arm.op_count++;
574
250
      }
575
576
250
      if (opc == ARM_AM_rrx) {
577
        //printAnnotation(O, Annot);
578
43
        return;
579
43
      }
580
581
207
      SStream_concat0(O, ", ");
582
207
      tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
583
207
      printUInt32Bang(O, tmp);
584
207
      if (MI->csh->detail) {
585
207
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
586
207
          (arm_shifter)opc;
587
207
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
588
207
      }
589
590
207
      return;
591
250
    }
592
593
    // A8.6.123 PUSH
594
197
    case ARM_STMDB_UPD:
595
330
    case ARM_t2STMDB_UPD:
596
330
      if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
597
330
            MCInst_getNumOperands(MI) > 5) {
598
        // Should only print PUSH if there are at least two registers in the list.
599
152
        SStream_concat0(O, "push");
600
152
        MCInst_setOpcodePub(MI, ARM_INS_PUSH);
601
152
        printPredicateOperand(MI, 2, O);
602
603
152
        if (Opcode == ARM_t2STMDB_UPD)
604
63
          SStream_concat0(O, ".w");
605
606
152
        SStream_concat0(O, "\t");
607
608
152
        if (MI->csh->detail) {
609
152
          MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
610
152
          MI->flat_insn->detail->regs_read_count++;
611
152
          MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
612
152
          MI->flat_insn->detail->regs_write_count++;
613
152
        }
614
615
152
        printRegisterList(MI, 4, O);
616
152
        return;
617
152
      } else
618
178
        break;
619
620
470
    case ARM_STR_PRE_IMM:
621
470
      if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
622
470
          MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
623
0
        SStream_concat0(O, "push");
624
0
        MCInst_setOpcodePub(MI, ARM_INS_PUSH);
625
626
0
        printPredicateOperand(MI, 4, O);
627
628
0
        SStream_concat0(O, "\t{");
629
630
0
        printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
631
632
0
        if (MI->csh->detail) {
633
0
#ifndef CAPSTONE_DIET
634
0
          uint8_t access;
635
0
#endif
636
0
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
637
0
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
638
0
#ifndef CAPSTONE_DIET
639
0
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
640
0
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
641
0
          MI->ac_idx++;
642
0
#endif
643
0
          MI->flat_insn->detail->arm.op_count++;
644
0
        }
645
646
0
        SStream_concat0(O, "}");
647
648
0
        return;
649
0
      } else
650
470
        break;
651
652
    // A8.6.122 POP
653
170
    case ARM_LDMIA_UPD:
654
235
    case ARM_t2LDMIA_UPD:
655
235
      if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
656
235
          MCInst_getNumOperands(MI) > 5) {
657
        // Should only print POP if there are at least two registers in the list.
658
45
        SStream_concat0(O, "pop");
659
45
        MCInst_setOpcodePub(MI, ARM_INS_POP);
660
661
45
        printPredicateOperand(MI, 2, O);
662
45
        if (Opcode == ARM_t2LDMIA_UPD)
663
31
          SStream_concat0(O, ".w");
664
665
45
        SStream_concat0(O, "\t");
666
667
        // unlike LDM, POP only write to registers, so skip the 1st access code
668
45
        MI->ac_idx = 1;
669
45
        if (MI->csh->detail) {
670
45
          MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
671
45
          MI->flat_insn->detail->regs_read_count++;
672
45
          MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
673
45
          MI->flat_insn->detail->regs_write_count++;
674
45
        }
675
676
45
        printRegisterList(MI, 4, O);
677
678
45
        return;
679
45
      }
680
190
      break;
681
682
241
    case ARM_LDR_POST_IMM:
683
241
      if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) {
684
32
        MCOperand *MO2 = MCInst_getOperand(MI, 4);
685
686
32
        if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) {
687
17
          SStream_concat0(O, "pop");
688
17
          MCInst_setOpcodePub(MI, ARM_INS_POP);
689
17
          printPredicateOperand(MI, 5, O);
690
17
          SStream_concat0(O, "\t{");
691
692
17
          printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
693
694
17
          if (MI->csh->detail) {
695
17
            MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
696
17
            MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
697
17
            MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
698
17
            MI->flat_insn->detail->arm.op_count++;
699
                        // this instruction implicitly read/write SP register
700
17
                        MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
701
17
                        MI->flat_insn->detail->regs_read_count++;
702
17
                        MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
703
17
                        MI->flat_insn->detail->regs_write_count++;
704
17
          }
705
17
          SStream_concat0(O, "}");
706
17
          return;
707
17
        }
708
32
      }
709
224
      break;
710
711
    // A8.6.355 VPUSH
712
224
    case ARM_VSTMSDB_UPD:
713
103
    case ARM_VSTMDDB_UPD:
714
103
      if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
715
12
        SStream_concat0(O, "vpush");
716
12
        MCInst_setOpcodePub(MI, ARM_INS_VPUSH);
717
12
        printPredicateOperand(MI, 2, O);
718
12
        SStream_concat0(O, "\t");
719
12
        printRegisterList(MI, 4, O);
720
12
        return;
721
12
      }
722
91
      break;
723
724
    // A8.6.354 VPOP
725
105
    case ARM_VLDMSIA_UPD:
726
155
    case ARM_VLDMDIA_UPD:
727
155
      if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
728
85
        SStream_concat0(O, "vpop");
729
85
        MCInst_setOpcodePub(MI, ARM_INS_VPOP);
730
85
        printPredicateOperand(MI, 2, O);
731
85
        SStream_concat0(O, "\t");
732
85
        printRegisterList(MI, 4, O);
733
85
        return;
734
85
      }
735
70
      break;
736
737
2.82k
    case ARM_tLDMIA: {
738
2.82k
        bool Writeback = true;
739
2.82k
        unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
740
2.82k
        unsigned i;
741
742
15.8k
        for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
743
12.9k
          if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
744
1.57k
            Writeback = false;
745
12.9k
        }
746
747
2.82k
        SStream_concat0(O, "ldm");
748
2.82k
        MCInst_setOpcodePub(MI, ARM_INS_LDM);
749
750
2.82k
        printPredicateOperand(MI, 1, O);
751
2.82k
        SStream_concat0(O, "\t");
752
2.82k
        printRegName(MI->csh, O, BaseReg);
753
2.82k
        if (MI->csh->detail) {
754
2.82k
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
755
2.82k
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
756
2.82k
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE;
757
2.82k
          MI->flat_insn->detail->arm.op_count++;
758
2.82k
        }
759
760
2.82k
        if (Writeback) {
761
1.25k
          MI->writeback = true;
762
1.25k
          SStream_concat0(O, "!");
763
1.25k
        }
764
765
2.82k
        SStream_concat0(O, ", ");
766
2.82k
        printRegisterList(MI, 3, O);
767
2.82k
        return;
768
155
      }
769
770
    // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
771
    // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
772
    // a single GPRPair reg operand is used in the .td file to replace the two
773
    // GPRs. However, when decoding them, the two GRPs cannot be automatically
774
    // expressed as a GPRPair, so we have to manually merge them.
775
    // FIXME: We would really like to be able to tablegen'erate this.
776
310
    case ARM_LDREXD:
777
357
    case ARM_STREXD:
778
395
    case ARM_LDAEXD:
779
427
    case ARM_STLEXD: {
780
427
      const MCRegisterClass *MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
781
427
      bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
782
427
      unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
783
784
427
      if (MCRegisterClass_contains(MRC, Reg)) {
785
0
          MCInst NewMI;
786
787
0
          MCInst_Init(&NewMI);
788
0
          MCInst_setOpcode(&NewMI, Opcode);
789
790
0
          if (isStore)
791
0
          MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
792
793
0
          MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
794
0
              MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
795
796
          // Copy the rest operands into NewMI.
797
0
          for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
798
0
          MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
799
800
0
          printInstruction(&NewMI, O);
801
0
          return;
802
0
      }
803
427
      break;
804
427
    }
805
806
427
    case ARM_TSB:
807
436
    case ARM_t2TSB:
808
436
      SStream_concat0(O, "tsb\tcsync");
809
436
      MCInst_setOpcodePub(MI, ARM_INS_TSB);
810
      // TODO: add csync to operands[]?
811
436
      return;
812
306k
  }
813
814
302k
  MI->MRI = MRI;
815
816
302k
  if (!printAliasInstr(MI, O)) {
817
301k
    printInstruction(MI, O);
818
301k
  }
819
302k
}
820
821
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
822
486k
{
823
486k
  int32_t imm;
824
486k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
825
826
486k
  if (MCOperand_isReg(Op)) {
827
403k
    unsigned Reg = MCOperand_getReg(Op);
828
829
403k
    printRegName(MI->csh, O, Reg);
830
831
403k
    if (MI->csh->detail) {
832
403k
      if (MI->csh->doing_mem) {
833
0
        if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
834
0
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
835
0
        else
836
0
          MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
837
403k
      } else {
838
403k
#ifndef CAPSTONE_DIET
839
403k
        uint8_t access;
840
403k
#endif
841
842
403k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
843
403k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
844
403k
#ifndef CAPSTONE_DIET
845
403k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
846
403k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
847
403k
        MI->ac_idx++;
848
403k
#endif
849
403k
        MI->flat_insn->detail->arm.op_count++;
850
403k
      }
851
403k
    }
852
403k
  } else if (MCOperand_isImm(Op)) {
853
82.8k
    unsigned int opc = MCInst_getOpcode(MI);
854
855
82.8k
    imm = (int32_t)MCOperand_getImm(Op);
856
857
    // relative branch only has relative offset, so we have to update it
858
    // to reflect absolute address. 
859
    // Note: in ARM, PC is always 2 instructions ahead, so we have to
860
    // add 8 in ARM mode, or 4 in Thumb mode
861
    // printf(">> opcode: %u\n", MCInst_getOpcode(MI));
862
82.8k
    if (ARM_rel_branch(MI->csh, opc)) {
863
17.8k
      uint32_t address;
864
865
      // only do this for relative branch
866
17.8k
      if (MI->csh->mode & CS_MODE_THUMB) {
867
12.8k
        address = (uint32_t)MI->address + 4;
868
12.8k
        if (ARM_blx_to_arm_mode(MI->csh, opc)) {
869
          // here need to align down to the nearest 4-byte address
870
171
#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
871
171
          address = _ALIGN_DOWN(address, 4);
872
171
#undef _ALIGN_DOWN
873
171
        }
874
12.8k
      } else {
875
5.01k
        address = (uint32_t)MI->address + 8;
876
5.01k
      }
877
878
17.8k
      imm += address;
879
17.8k
      printUInt32Bang(O, imm);
880
65.0k
    } else {
881
65.0k
      switch(MI->flat_insn->id) {
882
64.0k
        default:
883
64.0k
          if (MI->csh->imm_unsigned)
884
0
            printUInt32Bang(O, imm);
885
64.0k
          else
886
64.0k
            printInt32Bang(O, imm);
887
64.0k
          break;
888
351
        case ARM_INS_AND:
889
457
        case ARM_INS_ORR:
890
570
        case ARM_INS_EOR:
891
741
        case ARM_INS_BIC:
892
953
        case ARM_INS_MVN:
893
          // do not print number in negative form
894
953
          printUInt32Bang(O, imm);
895
953
          break;
896
65.0k
      }
897
65.0k
    }
898
899
82.8k
    if (MI->csh->detail) {
900
82.8k
      if (MI->csh->doing_mem)
901
0
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
902
82.8k
      else {
903
82.8k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
904
82.8k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
905
82.8k
        MI->flat_insn->detail->arm.op_count++;
906
82.8k
      }
907
82.8k
    }
908
82.8k
  }
909
486k
}
910
911
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
912
7.34k
{
913
7.34k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
914
7.34k
  int32_t OffImm;
915
7.34k
  bool isSub;
916
7.34k
  SStream_concat0(O, "[pc, ");
917
918
7.34k
  OffImm = (int32_t)MCOperand_getImm(MO1);
919
7.34k
  isSub = OffImm < 0;
920
921
  // Special value for #-0. All others are normal.
922
7.34k
  if (OffImm == INT32_MIN)
923
182
    OffImm = 0;
924
925
7.34k
  if (isSub) {
926
2.18k
    SStream_concat(O, "#-0x%x", -OffImm);
927
5.15k
  } else {
928
5.15k
    printUInt32Bang(O, OffImm);
929
5.15k
  }
930
931
7.34k
  SStream_concat0(O, "]");
932
933
7.34k
  if (MI->csh->detail) {
934
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
935
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
936
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
937
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
938
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
939
7.34k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
940
7.34k
    MI->flat_insn->detail->arm.op_count++;
941
7.34k
  }
942
7.34k
}
943
944
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
945
// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
946
//    REG 0   0           - e.g. R5
947
//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
948
//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
949
static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
950
2.37k
{
951
2.37k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
952
2.37k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
953
2.37k
  MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2);
954
2.37k
  ARM_AM_ShiftOpc ShOpc;
955
956
2.37k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
957
958
2.37k
  if (MI->csh->detail) {
959
2.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
960
2.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
961
2.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
962
963
2.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
964
2.37k
    MI->flat_insn->detail->arm.op_count++;
965
2.37k
  }
966
967
  // Print the shift opc.
968
2.37k
  ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
969
2.37k
  SStream_concat0(O, ", ");
970
2.37k
  SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
971
2.37k
  if (ShOpc == ARM_AM_rrx)
972
0
    return;
973
974
2.37k
  SStream_concat0(O, " ");
975
976
2.37k
  printRegName(MI->csh, O, MCOperand_getReg(MO2));
977
978
2.37k
  if (MI->csh->detail)
979
2.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
980
2.37k
}
981
982
static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
983
5.90k
{
984
5.90k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
985
5.90k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
986
987
5.90k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
988
989
5.90k
  if (MI->csh->detail) {
990
5.90k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
991
5.90k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
992
5.90k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
993
5.90k
    MI->flat_insn->detail->arm.op_count++;
994
5.90k
  }
995
996
  // Print the shift opc.
997
5.90k
  printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
998
5.90k
      getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
999
5.90k
}
1000
1001
//===--------------------------------------------------------------------===//
1002
// Addressing Mode #2
1003
//===--------------------------------------------------------------------===//
1004
1005
static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
1006
2.53k
{
1007
2.53k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1008
2.53k
  MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
1009
2.53k
  MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
1010
2.53k
  unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3);
1011
2.53k
  ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
1012
1013
2.53k
  SStream_concat0(O, "[");
1014
2.53k
  set_mem_access(MI, true);
1015
1016
2.53k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1017
2.53k
  if (MI->csh->detail) {
1018
2.53k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1019
2.53k
  }
1020
1021
2.53k
  if (!MCOperand_getReg(MO2)) {
1022
0
    unsigned tmp = getAM2Offset(imm3);
1023
0
    if (tmp) { // Don't print +0.
1024
0
      subtracted = getAM2Op(imm3);
1025
1026
0
      SStream_concat0(O, ", ");
1027
0
      if (tmp > HEX_THRESHOLD)
1028
0
        SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp);
1029
0
      else
1030
0
        SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp);
1031
0
      if (MI->csh->detail) {
1032
0
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op(imm3);
1033
0
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
1034
0
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1035
0
      }
1036
0
    }
1037
1038
0
    SStream_concat0(O, "]");
1039
0
    set_mem_access(MI, false);
1040
1041
0
    return;
1042
0
  }
1043
1044
2.53k
  SStream_concat0(O, ", ");
1045
2.53k
  SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
1046
2.53k
  printRegName(MI->csh, O, MCOperand_getReg(MO2));
1047
2.53k
  if (MI->csh->detail) {
1048
2.53k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
1049
2.53k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1050
2.53k
  }
1051
1052
2.53k
  printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3));
1053
2.53k
  SStream_concat0(O, "]");
1054
2.53k
  set_mem_access(MI, false);
1055
2.53k
}
1056
1057
static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
1058
135
{
1059
135
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1060
135
  MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
1061
1062
135
  SStream_concat0(O, "[");
1063
135
  set_mem_access(MI, true);
1064
1065
135
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1066
1067
135
  if (MI->csh->detail)
1068
135
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1069
1070
135
  SStream_concat0(O, ", ");
1071
135
  printRegName(MI->csh, O, MCOperand_getReg(MO2));
1072
1073
135
  if (MI->csh->detail)
1074
135
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
1075
1076
135
  SStream_concat0(O, "]");
1077
135
  set_mem_access(MI, false);
1078
135
}
1079
1080
static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
1081
32
{
1082
32
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1083
32
  MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
1084
1085
32
  SStream_concat0(O, "[");
1086
32
  set_mem_access(MI, true);
1087
1088
32
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1089
1090
32
  if (MI->csh->detail)
1091
32
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1092
1093
32
  SStream_concat0(O, ", ");
1094
32
  printRegName(MI->csh, O, MCOperand_getReg(MO2));
1095
1096
32
  if (MI->csh->detail)
1097
32
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
1098
1099
32
  SStream_concat0(O, ", lsl #1]");
1100
1101
32
  if (MI->csh->detail) {
1102
32
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
1103
32
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
1104
32
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1;
1105
32
  }
1106
1107
32
  set_mem_access(MI, false);
1108
32
}
1109
1110
static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O)
1111
2.53k
{
1112
2.53k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1113
1114
2.53k
  if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1115
0
    printOperand(MI, Op, O);
1116
0
    return;
1117
0
  }
1118
1119
//#ifndef NDEBUG
1120
//  const MCOperand &MO3 = MI->getOperand(Op + 2);
1121
//  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
1122
//  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
1123
//#endif
1124
1125
2.53k
  printAM2PreOrOffsetIndexOp(MI, Op, O);
1126
2.53k
}
1127
1128
static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
1129
5.12k
{
1130
5.12k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1131
5.12k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1132
5.12k
  ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2));
1133
1134
5.12k
  if (!MCOperand_getReg(MO1)) {
1135
3.17k
    unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
1136
3.17k
    if (ImmOffs > HEX_THRESHOLD)
1137
3.03k
      SStream_concat(O, "#%s0x%x",
1138
3.03k
          ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1139
137
    else
1140
137
      SStream_concat(O, "#%s%u",
1141
137
          ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1142
1143
3.17k
    if (MI->csh->detail) {
1144
3.17k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1145
3.17k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1146
3.17k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1147
3.17k
      MI->flat_insn->detail->arm.op_count++;
1148
3.17k
    }
1149
3.17k
    return;
1150
3.17k
  }
1151
1152
1.94k
  SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
1153
1.94k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1154
1155
1.94k
  if (MI->csh->detail) {
1156
1.94k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1157
1.94k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1158
1.94k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1159
1.94k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1160
1.94k
    MI->flat_insn->detail->arm.op_count++;
1161
1.94k
  }
1162
1163
1.94k
  printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
1164
1.94k
      getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
1165
1.94k
}
1166
1167
//===--------------------------------------------------------------------===//
1168
// Addressing Mode #3
1169
//===--------------------------------------------------------------------===//
1170
1171
static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
1172
    bool AlwaysPrintImm0)
1173
2.40k
{
1174
2.40k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1175
2.40k
  MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
1176
2.40k
  MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
1177
2.40k
  ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3));
1178
2.40k
  unsigned ImmOffs;
1179
1180
2.40k
  SStream_concat0(O, "[");
1181
2.40k
  set_mem_access(MI, true);
1182
1183
2.40k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1184
1185
2.40k
  if (MI->csh->detail)
1186
2.40k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1187
1188
2.40k
  if (MCOperand_getReg(MO2)) {
1189
1.53k
    SStream_concat0(O, ", ");
1190
1.53k
    SStream_concat0(O, ARM_AM_getAddrOpcStr(sign));
1191
1192
1.53k
    printRegName(MI->csh, O, MCOperand_getReg(MO2));
1193
1194
1.53k
    if (MI->csh->detail) {
1195
1.53k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
1196
1.53k
      if (sign == ARM_AM_sub) {
1197
578
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
1198
578
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
1199
578
      }
1200
1.53k
    }
1201
1202
1.53k
    SStream_concat0(O, "]");
1203
1.53k
    set_mem_access(MI, false);
1204
1205
1.53k
    return;
1206
1.53k
  }
1207
1208
  // If the op is sub we have to print the immediate even if it is 0
1209
872
  ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
1210
1211
872
  if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) {
1212
850
    if (ImmOffs > HEX_THRESHOLD)
1213
811
      SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs);
1214
39
    else
1215
39
      SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs);
1216
850
  }
1217
1218
872
  if (MI->csh->detail) {
1219
872
    if (sign == ARM_AM_sub) {
1220
391
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
1221
391
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
1222
391
    } else
1223
481
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs;
1224
872
  }
1225
1226
872
  SStream_concat0(O, "]");
1227
872
  set_mem_access(MI, false);
1228
872
}
1229
1230
static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
1231
    bool AlwaysPrintImm0)
1232
2.40k
{
1233
2.40k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
1234
1235
2.40k
  if (!MCOperand_isReg(MO1)) {   // For label symbolic references.
1236
0
    printOperand(MI, Op, O);
1237
0
    return;
1238
0
  }
1239
1240
2.40k
  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
1241
2.40k
}
1242
1243
static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
1244
1.54k
{
1245
1.54k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1246
1.54k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1247
1.54k
  ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2));
1248
1.54k
  unsigned ImmOffs;
1249
1250
1.54k
  if (MCOperand_getReg(MO1)) {
1251
1.11k
    SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
1252
1.11k
    printRegName(MI->csh, O, MCOperand_getReg(MO1));
1253
1254
1.11k
    if (MI->csh->detail) {
1255
1.11k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1256
1.11k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1257
1.11k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1258
1.11k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1259
1.11k
      MI->flat_insn->detail->arm.op_count++;
1260
1.11k
    }
1261
1262
1.11k
    return;
1263
1.11k
  }
1264
1265
430
  ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
1266
430
  if (ImmOffs > HEX_THRESHOLD)
1267
300
    SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1268
130
  else
1269
130
    SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1270
1271
430
  if (MI->csh->detail) {
1272
430
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1273
430
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1274
430
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1275
430
    MI->flat_insn->detail->arm.op_count++;
1276
430
  }
1277
430
}
1278
1279
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
1280
403
{
1281
403
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1282
403
  unsigned Imm = (unsigned int)MCOperand_getImm(MO);
1283
1284
403
  if ((Imm & 0xff) > HEX_THRESHOLD)
1285
319
    SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1286
84
  else
1287
84
    SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1288
1289
403
  if (MI->csh->detail) {
1290
403
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1291
403
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
1292
403
    MI->flat_insn->detail->arm.op_count++;
1293
403
  }
1294
403
}
1295
1296
static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1297
830
{
1298
830
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1299
830
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1300
1301
830
  SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
1302
830
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1303
1304
830
  if (MI->csh->detail) {
1305
830
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1306
830
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1307
830
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1308
830
    MI->flat_insn->detail->arm.op_count++;
1309
830
  }
1310
830
}
1311
1312
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
1313
3.09k
{
1314
3.09k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1315
3.09k
  int Imm = (int)MCOperand_getImm(MO);
1316
1317
3.09k
  if (((Imm & 0xff) << 2) > HEX_THRESHOLD) {
1318
2.96k
    SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1319
2.96k
  } else {
1320
126
    SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1321
126
  }
1322
1323
3.09k
  if (MI->csh->detail) {
1324
3.09k
    int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2);
1325
3.09k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1326
3.09k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
1327
3.09k
    MI->flat_insn->detail->arm.op_count++;
1328
3.09k
  }
1329
3.09k
}
1330
1331
static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
1332
    bool AlwaysPrintImm0)
1333
6.24k
{
1334
6.24k
  unsigned ImmOffs;
1335
6.24k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1336
6.24k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1337
6.24k
  ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
1338
1339
6.24k
  if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1340
0
    printOperand(MI, OpNum, O);
1341
0
    return;
1342
0
  }
1343
1344
6.24k
  SStream_concat0(O, "[");
1345
6.24k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1346
1347
6.24k
  if (MI->csh->detail) {
1348
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
1349
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1350
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
1351
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
1352
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
1353
6.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1354
6.24k
  }
1355
1356
6.24k
  ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
1357
6.24k
  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
1358
6.19k
    if (ImmOffs * 4 > HEX_THRESHOLD)
1359
5.75k
      SStream_concat(O, ", #%s0x%x",
1360
5.75k
          ARM_AM_getAddrOpcStr(Op),
1361
5.75k
          ImmOffs * 4);
1362
433
    else
1363
433
      SStream_concat(O, ", #%s%u",
1364
433
          ARM_AM_getAddrOpcStr(Op),
1365
433
          ImmOffs * 4);
1366
1367
6.19k
    if (MI->csh->detail) {
1368
6.19k
      if (Op)
1369
3.29k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
1370
2.89k
      else
1371
2.89k
        MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4;
1372
6.19k
    }
1373
6.19k
  }
1374
1375
6.24k
  SStream_concat0(O, "]");
1376
1377
6.24k
  if (MI->csh->detail) {
1378
6.24k
    MI->flat_insn->detail->arm.op_count++;
1379
6.24k
  }
1380
6.24k
}
1381
1382
static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O,
1383
    bool AlwaysPrintImm0)
1384
165
{
1385
165
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1386
165
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1387
165
  unsigned ImmOffs = getAM5FP16Offset((unsigned)MCOperand_getImm(MO2));
1388
165
  unsigned Op = getAM5FP16Op((unsigned)MCOperand_getImm(MO2));
1389
1390
165
  if (!MCOperand_isReg(MO1)) {  // FIXME: This is for CP entries, but isn't right.
1391
0
    printOperand(MI, OpNum, O);
1392
0
    return;
1393
0
  }
1394
1395
165
  SStream_concat0(O, "[");
1396
165
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1397
1398
165
  if (MI->csh->detail) {
1399
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
1400
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1401
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
1402
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
1403
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
1404
165
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1405
165
  }
1406
1407
165
  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
1408
101
  if (ImmOffs * 2 > HEX_THRESHOLD)
1409
46
    SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2);
1410
55
  else
1411
55
    SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2);
1412
1413
101
  if (MI->csh->detail) {
1414
101
    if (Op)
1415
38
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 2;
1416
63
    else
1417
63
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 2;
1418
101
  }
1419
101
  }
1420
1421
165
  SStream_concat0(O, "]");
1422
1423
165
  if (MI->csh->detail) {
1424
165
    MI->flat_insn->detail->arm.op_count++;
1425
165
  }
1426
165
}
1427
1428
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
1429
15.3k
{
1430
15.3k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1431
15.3k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
1432
15.3k
  unsigned tmp;
1433
1434
15.3k
  SStream_concat0(O, "[");
1435
15.3k
  set_mem_access(MI, true);
1436
1437
15.3k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1438
1439
15.3k
  if (MI->csh->detail)
1440
15.3k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1441
1442
15.3k
  tmp = (unsigned int)MCOperand_getImm(MO2);
1443
15.3k
  if (tmp) {
1444
6.65k
    if (tmp << 3 > HEX_THRESHOLD)
1445
6.65k
      SStream_concat(O, ":0x%x", (tmp << 3));
1446
0
    else
1447
0
      SStream_concat(O, ":%u", (tmp << 3));
1448
1449
6.65k
    if (MI->csh->detail)
1450
6.65k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
1451
6.65k
  }
1452
1453
15.3k
  SStream_concat0(O, "]");
1454
15.3k
  set_mem_access(MI, false);
1455
15.3k
}
1456
1457
static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
1458
15.3k
{
1459
15.3k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1460
1461
15.3k
  SStream_concat0(O, "[");
1462
15.3k
  set_mem_access(MI, true);
1463
1464
15.3k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
1465
1466
15.3k
  if (MI->csh->detail)
1467
15.3k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1468
1469
15.3k
  SStream_concat0(O, "]");
1470
15.3k
  set_mem_access(MI, false);
1471
15.3k
}
1472
1473
static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
1474
4.59k
{
1475
4.59k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1476
1477
4.59k
  if (MCOperand_getReg(MO) == 0) {
1478
992
    MI->writeback = true;
1479
992
    SStream_concat0(O, "!");
1480
3.60k
  } else {
1481
3.60k
    SStream_concat0(O, ", ");
1482
3.60k
    printRegName(MI->csh, O, MCOperand_getReg(MO));
1483
1484
3.60k
    if (MI->csh->detail) {
1485
3.60k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1486
3.60k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
1487
3.60k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
1488
3.60k
      MI->flat_insn->detail->arm.op_count++;
1489
3.60k
    }
1490
3.60k
  }
1491
4.59k
}
1492
1493
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1494
523
{
1495
523
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1496
523
  uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
1497
523
  int32_t lsb = CountTrailingZeros_32(v);
1498
523
  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
1499
1500
  //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
1501
523
  printUInt32Bang(O, lsb);
1502
1503
523
  if (width > HEX_THRESHOLD)
1504
86
    SStream_concat(O, ", #0x%x", width);
1505
437
  else
1506
437
    SStream_concat(O, ", #%u", width);
1507
1508
523
  if (MI->csh->detail) {
1509
523
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1510
523
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
1511
523
    MI->flat_insn->detail->arm.op_count++;
1512
523
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1513
523
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
1514
523
    MI->flat_insn->detail->arm.op_count++;
1515
523
  }
1516
523
}
1517
1518
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
1519
513
{
1520
513
  unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1521
513
  SStream_concat0(O, ARM_MB_MemBOptToString(val,
1522
513
        ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)));
1523
1524
513
  if (MI->csh->detail) {
1525
513
    MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1);
1526
513
  }
1527
513
}
1528
1529
static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
1530
126
{
1531
126
  unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1532
126
  SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
1533
126
}
1534
1535
static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
1536
0
{
1537
0
  unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1538
0
  SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val));
1539
  // TODO: add to detail?
1540
0
}
1541
1542
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1543
684
{
1544
684
  unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1545
684
  bool isASR = (ShiftOp & (1 << 5)) != 0;
1546
684
  unsigned Amt = ShiftOp & 0x1f;
1547
1548
684
  if (isASR) {
1549
270
    unsigned tmp = Amt == 0 ? 32 : Amt;
1550
270
    if (tmp > HEX_THRESHOLD)
1551
241
      SStream_concat(O, ", asr #0x%x", tmp);
1552
29
    else
1553
29
      SStream_concat(O, ", asr #%u", tmp);
1554
1555
270
    if (MI->csh->detail) {
1556
270
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
1557
270
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
1558
270
    }
1559
414
  } else if (Amt) {
1560
297
    if (Amt > HEX_THRESHOLD)
1561
155
      SStream_concat(O, ", lsl #0x%x", Amt);
1562
142
    else
1563
142
      SStream_concat(O, ", lsl #%u", Amt);
1564
1565
297
    if (MI->csh->detail) {
1566
297
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
1567
297
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
1568
297
    }
1569
297
  }
1570
684
}
1571
1572
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
1573
128
{
1574
128
  unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1575
1576
128
  if (Imm == 0)
1577
72
    return;
1578
1579
  //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
1580
56
  if (Imm > HEX_THRESHOLD)
1581
42
    SStream_concat(O, ", lsl #0x%x", Imm);
1582
14
  else
1583
14
    SStream_concat(O, ", lsl #%u", Imm);
1584
1585
56
  if (MI->csh->detail) {
1586
56
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
1587
56
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1588
56
  }
1589
56
}
1590
1591
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
1592
326
{
1593
326
  unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1594
1595
  // A shift amount of 32 is encoded as 0.
1596
326
  if (Imm == 0)
1597
13
    Imm = 32;
1598
1599
  //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
1600
326
  if (Imm > HEX_THRESHOLD)
1601
87
    SStream_concat(O, ", asr #0x%x", Imm);
1602
239
  else
1603
239
    SStream_concat(O, ", asr #%u", Imm);
1604
1605
326
  if (MI->csh->detail) {
1606
326
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
1607
326
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1608
326
  }
1609
326
}
1610
1611
// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
1612
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
1613
12.7k
{
1614
12.7k
  unsigned i, e;
1615
12.7k
#ifndef CAPSTONE_DIET
1616
12.7k
  uint8_t access = 0;
1617
12.7k
#endif
1618
1619
12.7k
  SStream_concat0(O, "{");
1620
1621
12.7k
#ifndef CAPSTONE_DIET
1622
12.7k
  if (MI->csh->detail) {
1623
12.7k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1624
12.7k
  }
1625
12.7k
#endif
1626
1627
88.9k
  for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
1628
76.1k
    if (i != OpNum)
1629
63.4k
      SStream_concat0(O, ", ");
1630
1631
76.1k
    printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
1632
1633
76.1k
    if (MI->csh->detail) {
1634
76.1k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1635
76.1k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
1636
76.1k
#ifndef CAPSTONE_DIET
1637
76.1k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
1638
76.1k
#endif
1639
76.1k
      MI->flat_insn->detail->arm.op_count++;
1640
76.1k
    }
1641
76.1k
  }
1642
1643
12.7k
  SStream_concat0(O, "}");
1644
1645
12.7k
#ifndef CAPSTONE_DIET
1646
12.7k
  if (MI->csh->detail) {
1647
12.7k
    MI->ac_idx++;
1648
12.7k
  }
1649
12.7k
#endif
1650
12.7k
}
1651
1652
static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O)
1653
427
{
1654
427
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1655
1656
427
  printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0));
1657
1658
427
  if (MI->csh->detail) {
1659
427
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1660
427
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0);
1661
427
    MI->flat_insn->detail->arm.op_count++;
1662
427
  }
1663
1664
427
  SStream_concat0(O, ", ");
1665
1666
427
  printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1));
1667
1668
427
  if (MI->csh->detail) {
1669
427
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1670
427
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1);
1671
427
    MI->flat_insn->detail->arm.op_count++;
1672
427
  }
1673
427
}
1674
1675
// SETEND BE/LE
1676
static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
1677
966
{
1678
966
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1679
1680
966
  if (MCOperand_getImm(Op)) {
1681
140
    SStream_concat0(O, "be");
1682
1683
140
    if (MI->csh->detail) {
1684
140
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
1685
140
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE;
1686
140
      MI->flat_insn->detail->arm.op_count++;
1687
140
    }
1688
826
  } else {
1689
826
    SStream_concat0(O, "le");
1690
1691
826
    if (MI->csh->detail) {
1692
826
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
1693
826
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE;
1694
826
      MI->flat_insn->detail->arm.op_count++;
1695
826
    }
1696
826
  }
1697
966
}
1698
1699
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
1700
309
{
1701
309
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1702
309
  unsigned int mode = (unsigned int)MCOperand_getImm(Op);
1703
1704
309
  SStream_concat0(O, ARM_PROC_IModToString(mode));
1705
1706
309
  if (MI->csh->detail) {
1707
309
    MI->flat_insn->detail->arm.cps_mode = mode;
1708
309
  }
1709
309
}
1710
1711
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
1712
309
{
1713
309
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1714
309
  unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
1715
309
  int i;
1716
1717
1.23k
  for (i = 2; i >= 0; --i)
1718
927
    if (IFlags & (1 << i)) {
1719
469
      SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
1720
469
    }
1721
1722
309
  if (IFlags == 0) {
1723
139
    SStream_concat0(O, "none");
1724
139
    IFlags = ARM_CPSFLAG_NONE;
1725
139
  }
1726
1727
309
  if (MI->csh->detail) {
1728
309
    MI->flat_insn->detail->arm.cps_flag = IFlags;
1729
309
  }
1730
309
}
1731
1732
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
1733
2.25k
{
1734
2.25k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1735
2.25k
  unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
1736
2.25k
  unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf;
1737
2.25k
  unsigned reg;
1738
1739
2.25k
  if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
1740
1.75k
    const MClassSysReg *TheReg;
1741
1.75k
    unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF;  // 12-bit SYMm
1742
1.75k
    unsigned Opcode = MCInst_getOpcode(MI);
1743
1744
1.75k
    if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) {
1745
1.52k
      TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm);
1746
1.52k
      if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) {
1747
27
        SStream_concat0(O, TheReg->Name);
1748
27
        ARM_addSysReg(MI, TheReg->sysreg);
1749
27
        return;
1750
27
      }
1751
1.52k
    }
1752
1753
    // Handle the basic 8-bit mask.
1754
1.72k
    SYSm &= 0xff;
1755
1.72k
    if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) {
1756
      // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
1757
      // alias for MSR APSR_nzcvq.
1758
1.49k
      TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm);
1759
1.49k
      if (TheReg) {
1760
18
        SStream_concat0(O, TheReg->Name);
1761
18
        ARM_addSysReg(MI, TheReg->sysreg);
1762
18
        return;
1763
18
      }
1764
1.49k
    }
1765
1766
1.70k
    TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm);
1767
1.70k
    if (TheReg) {
1768
1.50k
      SStream_concat0(O, TheReg->Name);
1769
1.50k
      ARM_addSysReg(MI, TheReg->sysreg);
1770
1.50k
      return;
1771
1.50k
    }
1772
1773
203
    if (SYSm > HEX_THRESHOLD)
1774
199
      SStream_concat(O, "%x", SYSm);
1775
4
    else
1776
4
      SStream_concat(O, "%u", SYSm);
1777
1778
203
    if (MI->csh->detail)
1779
203
      MCOperand_CreateImm0(MI, SYSm);
1780
1781
203
    return;
1782
1.70k
  }
1783
1784
  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
1785
  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
1786
499
  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
1787
131
    SStream_concat0(O, "apsr_");
1788
131
    switch (Mask) {
1789
0
      default: // llvm_unreachable("Unexpected mask value!");
1790
41
      case 4:  SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
1791
56
      case 8:  SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
1792
34
      case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
1793
131
    }
1794
131
  }
1795
1796
368
  if (SpecRegRBit) {
1797
333
    SStream_concat0(O, "spsr");
1798
333
  } else {
1799
35
    SStream_concat0(O, "cpsr");
1800
35
  }
1801
1802
368
  reg = 0;
1803
368
  if (Mask) {
1804
189
    SStream_concat0(O, "_");
1805
1806
189
    if (Mask & 8) {
1807
86
      SStream_concat0(O, "f");
1808
86
      reg += ARM_SYSREG_SPSR_F;
1809
86
    }
1810
1811
189
    if (Mask & 4) {
1812
54
      SStream_concat0(O, "s");
1813
54
      reg += ARM_SYSREG_SPSR_S;
1814
54
    }
1815
1816
189
    if (Mask & 2) {
1817
89
      SStream_concat0(O, "x");
1818
89
      reg += ARM_SYSREG_SPSR_X;
1819
89
    }
1820
1821
189
    if (Mask & 1) {
1822
58
      SStream_concat0(O, "c");
1823
58
      reg += ARM_SYSREG_SPSR_C;
1824
58
    }
1825
1826
189
    ARM_addSysReg(MI, reg);
1827
189
  }
1828
368
}
1829
1830
static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1831
751
{
1832
751
  uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1833
751
  const BankedReg *TheReg = lookupBankedRegByEncoding(Banked);
1834
1835
751
  SStream_concat0(O, TheReg->Name);
1836
751
  ARM_addSysReg(MI, TheReg->sysreg);
1837
751
}
1838
1839
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
1840
266k
{
1841
266k
  ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1842
  // Handle the undefined 15 CC value here for printing so we don't abort().
1843
266k
  if ((unsigned)CC == 15) {
1844
130
    SStream_concat0(O, "<und>");
1845
1846
130
    if (MI->csh->detail)
1847
130
      MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
1848
266k
  } else {
1849
266k
    if (CC != ARMCC_AL) {
1850
65.0k
      SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
1851
65.0k
    }
1852
1853
266k
    if (MI->csh->detail)
1854
266k
      MI->flat_insn->detail->arm.cc = CC + 1;
1855
266k
  }
1856
266k
}
1857
1858
static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
1859
4.03k
{
1860
4.03k
  ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1861
4.03k
  SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
1862
1863
4.03k
  if (MI->csh->detail)
1864
4.03k
    MI->flat_insn->detail->arm.cc = CC + 1;
1865
4.03k
}
1866
1867
static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
1868
76.2k
{
1869
76.2k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
1870
    //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
1871
    //       "Expect ARM CPSR register!");
1872
59.9k
    SStream_concat0(O, "s");
1873
1874
59.9k
    if (MI->csh->detail)
1875
59.9k
      MI->flat_insn->detail->arm.update_flags = true;
1876
59.9k
  }
1877
76.2k
}
1878
1879
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1880
9.36k
{
1881
9.36k
  unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1882
1883
9.36k
  printUInt32(O, tmp);
1884
1885
9.36k
  if (MI->csh->detail) {
1886
9.36k
    if (MI->csh->doing_mem) {
1887
9.36k
      MI->flat_insn->detail->arm.op_count--;
1888
9.36k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp;
1889
9.36k
      MI->ac_idx--; // consecutive operands share the same access right
1890
9.36k
    } else {
1891
0
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1892
0
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1893
0
      MI->flat_insn->detail->arm.op_count++;
1894
0
    }
1895
9.36k
  }
1896
9.36k
}
1897
1898
static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1899
15.2k
{
1900
15.2k
  unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1901
1902
15.2k
  SStream_concat(O, "p%u", imm);
1903
1904
15.2k
  if (MI->csh->detail) {
1905
15.2k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
1906
15.2k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1907
15.2k
    MI->flat_insn->detail->arm.op_count++;
1908
15.2k
  }
1909
15.2k
}
1910
1911
static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1912
21.7k
{
1913
21.7k
  unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1914
1915
21.7k
  SStream_concat(O, "c%u", imm);
1916
1917
21.7k
  if (MI->csh->detail) {
1918
21.7k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
1919
21.7k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1920
21.7k
    MI->flat_insn->detail->arm.op_count++;
1921
21.7k
  }
1922
21.7k
}
1923
1924
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
1925
1.24k
{
1926
1.24k
  unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1927
1.24k
  if (tmp > HEX_THRESHOLD)
1928
1.17k
    SStream_concat(O, "{0x%x}", tmp);
1929
72
  else
1930
72
    SStream_concat(O, "{%u}", tmp);
1931
1932
1.24k
  if (MI->csh->detail) {
1933
1.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1934
1.24k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1935
1.24k
    MI->flat_insn->detail->arm.op_count++;
1936
1.24k
  }
1937
1.24k
}
1938
1939
static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale)
1940
6.21k
{
1941
6.21k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1942
1943
6.21k
  int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
1944
1945
6.21k
  if (OffImm == INT32_MIN) {
1946
0
    SStream_concat0(O, "#-0");
1947
1948
0
    if (MI->csh->detail) {
1949
0
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1950
0
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
1951
0
      MI->flat_insn->detail->arm.op_count++;
1952
0
    }
1953
6.21k
  } else {
1954
6.21k
    if (OffImm < 0)
1955
0
      SStream_concat(O, "#-0x%x", -OffImm);
1956
6.21k
    else {
1957
6.21k
      if (OffImm > HEX_THRESHOLD)
1958
5.60k
        SStream_concat(O, "#0x%x", OffImm);
1959
608
      else
1960
608
        SStream_concat(O, "#%u", OffImm);
1961
6.21k
    }
1962
1963
6.21k
    if (MI->csh->detail) {
1964
6.21k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1965
6.21k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
1966
6.21k
      MI->flat_insn->detail->arm.op_count++;
1967
6.21k
    }
1968
6.21k
  }
1969
6.21k
}
1970
1971
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1972
3.93k
{
1973
3.93k
  unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
1974
1975
3.93k
  printUInt32Bang(O, tmp);
1976
1977
3.93k
  if (MI->csh->detail) {
1978
3.93k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1979
3.93k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1980
3.93k
    MI->flat_insn->detail->arm.op_count++;
1981
3.93k
  }
1982
3.93k
}
1983
1984
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
1985
12.1k
{
1986
12.1k
  unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1987
12.1k
  unsigned tmp = Imm == 0 ? 32 : Imm;
1988
1989
12.1k
  printUInt32Bang(O, tmp);
1990
1991
12.1k
  if (MI->csh->detail) {
1992
12.1k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1993
12.1k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1994
12.1k
    MI->flat_insn->detail->arm.op_count++;
1995
12.1k
  }
1996
12.1k
}
1997
1998
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
1999
4.03k
{
2000
  // (3 - the number of trailing zeros) is the number of then / else.
2001
4.03k
  unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2002
4.03k
  unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1));
2003
4.03k
  unsigned CondBit0 = Firstcond & 1;
2004
4.03k
  unsigned NumTZ = CountTrailingZeros_32(Mask);
2005
  //assert(NumTZ <= 3 && "Invalid IT mask!");
2006
4.03k
  unsigned Pos, e;
2007
2008
14.7k
  for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
2009
10.7k
    bool T = ((Mask >> Pos) & 1) == CondBit0;
2010
10.7k
    if (T)
2011
7.27k
      SStream_concat0(O, "t");
2012
3.47k
    else
2013
3.47k
      SStream_concat0(O, "e");
2014
    // TODO: detail for this t/e
2015
10.7k
  }
2016
4.03k
}
2017
2018
static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
2019
7.86k
{
2020
7.86k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
2021
7.86k
  MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
2022
7.86k
  unsigned RegNum;
2023
2024
7.86k
  if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
2025
0
    printOperand(MI, Op, O);
2026
0
    return;
2027
0
  }
2028
2029
7.86k
  SStream_concat0(O, "[");
2030
7.86k
  set_mem_access(MI, true);
2031
2032
7.86k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2033
2034
7.86k
  if (MI->csh->detail)
2035
7.86k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2036
2037
7.86k
  RegNum = MCOperand_getReg(MO2);
2038
7.86k
  if (RegNum) {
2039
7.86k
    SStream_concat0(O, ", ");
2040
7.86k
    printRegName(MI->csh, O, RegNum);
2041
2042
7.86k
    if (MI->csh->detail)
2043
7.86k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
2044
7.86k
  }
2045
2046
7.86k
  SStream_concat0(O, "]");
2047
7.86k
  set_mem_access(MI, false);
2048
7.86k
}
2049
2050
static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
2051
    unsigned Scale)
2052
42.1k
{
2053
42.1k
  MCOperand *MO1 = MCInst_getOperand(MI, Op);
2054
42.1k
  MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
2055
42.1k
  unsigned ImmOffs, tmp;
2056
2057
42.1k
  if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
2058
0
    printOperand(MI, Op, O);
2059
0
    return;
2060
0
  }
2061
2062
42.1k
  SStream_concat0(O, "[");
2063
42.1k
  set_mem_access(MI, true);
2064
2065
42.1k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2066
2067
42.1k
  if (MI->csh->detail)
2068
42.1k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2069
2070
42.1k
  ImmOffs = (unsigned int)MCOperand_getImm(MO2);
2071
42.1k
  if (ImmOffs) {
2072
40.3k
    tmp = ImmOffs * Scale;
2073
40.3k
    SStream_concat0(O, ", ");
2074
40.3k
    printUInt32Bang(O, tmp);
2075
2076
40.3k
    if (MI->csh->detail)
2077
40.3k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
2078
40.3k
  }
2079
2080
42.1k
  SStream_concat0(O, "]");
2081
42.1k
  set_mem_access(MI, false);
2082
42.1k
}
2083
2084
static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O)
2085
8.51k
{
2086
8.51k
  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
2087
8.51k
}
2088
2089
static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O)
2090
12.1k
{
2091
12.1k
  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
2092
12.1k
}
2093
2094
static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O)
2095
14.9k
{
2096
14.9k
  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
2097
14.9k
}
2098
2099
static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
2100
6.45k
{
2101
6.45k
  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
2102
6.45k
}
2103
2104
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
2105
// register with shift forms.
2106
// REG 0   0           - e.g. R5
2107
// REG IMM, SH_OPC     - e.g. R5, LSL #3
2108
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
2109
1.78k
{
2110
1.78k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2111
1.78k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
2112
1.78k
  unsigned Reg = MCOperand_getReg(MO1);
2113
2114
1.78k
  printRegName(MI->csh, O, Reg);
2115
2116
1.78k
  if (MI->csh->detail) {
2117
1.78k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2118
1.78k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
2119
1.78k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
2120
1.78k
    MI->flat_insn->detail->arm.op_count++;
2121
1.78k
  }
2122
2123
  // Print the shift opc.
2124
  //assert(MO2.isImm() && "Not a valid t2_so_reg value!");
2125
1.78k
  printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
2126
1.78k
      getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
2127
1.78k
}
2128
2129
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
2130
    SStream *O, bool AlwaysPrintImm0)
2131
4.27k
{
2132
4.27k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2133
4.27k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
2134
4.27k
  int32_t OffImm;
2135
4.27k
  bool isSub;
2136
2137
4.27k
  if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
2138
0
    printOperand(MI, OpNum, O);
2139
0
    return;
2140
0
  }
2141
2142
4.27k
  SStream_concat0(O, "[");
2143
4.27k
  set_mem_access(MI, true);
2144
2145
4.27k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2146
2147
4.27k
  if (MI->csh->detail)
2148
4.27k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2149
2150
4.27k
  OffImm = (int32_t)MCOperand_getImm(MO2);
2151
4.27k
  isSub = OffImm < 0;
2152
2153
  // Special value for #-0. All others are normal.
2154
4.27k
  if (OffImm == INT32_MIN)
2155
351
    OffImm = 0;
2156
2157
4.27k
  if (isSub) {
2158
1.85k
    if (OffImm < -HEX_THRESHOLD)
2159
1.48k
      SStream_concat(O, ", #-0x%x", -OffImm);
2160
370
    else
2161
370
      SStream_concat(O, ", #-%u", -OffImm);
2162
2.42k
  } else if (AlwaysPrintImm0 || OffImm > 0) {
2163
2.38k
    if (OffImm >= 0) {
2164
2.38k
      if (OffImm > HEX_THRESHOLD)
2165
2.29k
        SStream_concat(O, ", #0x%x", OffImm);
2166
90
      else
2167
90
        SStream_concat(O, ", #%u", OffImm);
2168
2.38k
    } else {
2169
0
      if (OffImm < -HEX_THRESHOLD)
2170
0
        SStream_concat(O, ", #-0x%x", -OffImm);
2171
0
      else
2172
0
        SStream_concat(O, ", #-%u", -OffImm);
2173
0
    }
2174
2.38k
  }
2175
2176
4.27k
  if (MI->csh->detail)
2177
4.27k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
2178
2179
4.27k
  SStream_concat0(O, "]");
2180
4.27k
  set_mem_access(MI, false);
2181
4.27k
}
2182
2183
static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
2184
    bool AlwaysPrintImm0)
2185
1.48k
{
2186
1.48k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2187
1.48k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
2188
1.48k
  int32_t OffImm;
2189
1.48k
  bool isSub;
2190
2191
1.48k
  SStream_concat0(O, "[");
2192
1.48k
  set_mem_access(MI, true);
2193
2194
1.48k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2195
2196
1.48k
  if (MI->csh->detail)
2197
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2198
2199
1.48k
  OffImm = (int32_t)MCOperand_getImm(MO2);
2200
1.48k
  isSub = OffImm < 0;
2201
2202
  // Don't print +0.
2203
1.48k
  if (OffImm == INT32_MIN)
2204
310
    OffImm = 0;
2205
2206
1.48k
  if (isSub)
2207
696
    SStream_concat(O, ", #-0x%x", -OffImm);
2208
788
  else if (AlwaysPrintImm0 || OffImm > 0) {
2209
751
    if (OffImm > HEX_THRESHOLD)
2210
368
      SStream_concat(O, ", #0x%x", OffImm);
2211
383
    else
2212
383
      SStream_concat(O, ", #%u", OffImm);
2213
751
  }
2214
2215
1.48k
  if (MI->csh->detail)
2216
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
2217
2218
1.48k
  SStream_concat0(O, "]");
2219
1.48k
  set_mem_access(MI, false);
2220
1.48k
}
2221
2222
static void printT2AddrModeImm8s4Operand(MCInst *MI,
2223
    unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
2224
2.33k
{
2225
2.33k
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2226
2.33k
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
2227
2.33k
  int32_t OffImm;
2228
2.33k
  bool isSub;
2229
2230
2.33k
  if (!MCOperand_isReg(MO1)) {   //  For label symbolic references.
2231
0
    printOperand(MI, OpNum, O);
2232
0
    return;
2233
0
  }
2234
2235
2.33k
  SStream_concat0(O, "[");
2236
2.33k
  set_mem_access(MI, true);
2237
2238
2.33k
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2239
2240
2.33k
  if (MI->csh->detail)
2241
2.33k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2242
2243
2.33k
  OffImm = (int32_t)MCOperand_getImm(MO2);
2244
2.33k
  isSub = OffImm < 0;
2245
2246
  //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
2247
2248
  // Don't print +0.
2249
2.33k
  if (OffImm == INT32_MIN)
2250
216
    OffImm = 0;
2251
2252
2.33k
  if (isSub) {
2253
805
    SStream_concat(O, ", #-0x%x", -OffImm);
2254
1.53k
  } else if (AlwaysPrintImm0 || OffImm > 0) {
2255
1.47k
    if (OffImm > HEX_THRESHOLD)
2256
1.43k
      SStream_concat(O, ", #0x%x", OffImm);
2257
40
    else
2258
40
      SStream_concat(O, ", #%u", OffImm);
2259
1.47k
  }
2260
2261
2.33k
  if (MI->csh->detail)
2262
2.33k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
2263
2264
2.33k
  SStream_concat0(O, "]");
2265
2.33k
  set_mem_access(MI, false);
2266
2.33k
}
2267
2268
static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
2269
191
{
2270
191
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2271
191
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
2272
191
  unsigned tmp;
2273
2274
191
  SStream_concat0(O, "[");
2275
191
  set_mem_access(MI, true);
2276
2277
191
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2278
2279
191
  if (MI->csh->detail)
2280
191
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2281
2282
191
  if (MCOperand_getImm(MO2)) {
2283
145
    SStream_concat0(O, ", ");
2284
145
    tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
2285
145
    printUInt32Bang(O, tmp);
2286
2287
145
    if (MI->csh->detail)
2288
145
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
2289
145
  }
2290
2291
191
  SStream_concat0(O, "]");
2292
191
  set_mem_access(MI, false);
2293
191
}
2294
2295
static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
2296
    unsigned OpNum, SStream *O)
2297
617
{
2298
617
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2299
617
  int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
2300
2301
617
  SStream_concat0(O, ", ");
2302
617
  if (OffImm == INT32_MIN) {
2303
44
    SStream_concat0(O, "#-0");
2304
2305
44
    if (MI->csh->detail) {
2306
44
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2307
44
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2308
44
      MI->flat_insn->detail->arm.op_count++;
2309
44
    }
2310
573
  } else {
2311
573
    printInt32Bang(O, OffImm);
2312
2313
573
    if (MI->csh->detail) {
2314
573
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2315
573
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2316
573
      MI->flat_insn->detail->arm.op_count++;
2317
573
    }
2318
573
  }
2319
617
}
2320
2321
static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
2322
    unsigned OpNum, SStream *O)
2323
762
{
2324
762
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2325
762
  int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
2326
2327
  //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
2328
2329
762
  SStream_concat0(O, ", ");
2330
2331
762
  if (OffImm == INT32_MIN) {
2332
54
    SStream_concat0(O, "#-0");
2333
2334
54
    if (MI->csh->detail) {
2335
54
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2336
54
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2337
54
      MI->flat_insn->detail->arm.op_count++;
2338
54
    }
2339
708
  } else {
2340
708
    printInt32Bang(O, OffImm);
2341
2342
708
    if (MI->csh->detail) {
2343
708
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2344
708
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2345
708
      MI->flat_insn->detail->arm.op_count++;
2346
708
    }
2347
708
  }
2348
762
}
2349
2350
static void printT2AddrModeSoRegOperand(MCInst *MI,
2351
    unsigned OpNum, SStream *O)
2352
882
{
2353
882
  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2354
882
  MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
2355
882
  MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
2356
882
  unsigned ShAmt;
2357
2358
882
  SStream_concat0(O, "[");
2359
882
  set_mem_access(MI, true);
2360
2361
882
  printRegName(MI->csh, O, MCOperand_getReg(MO1));
2362
2363
882
  if (MI->csh->detail)
2364
882
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2365
2366
  //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
2367
882
  SStream_concat0(O, ", ");
2368
882
  printRegName(MI->csh, O, MCOperand_getReg(MO2));
2369
2370
882
  if (MI->csh->detail)
2371
882
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
2372
2373
882
  ShAmt = (unsigned int)MCOperand_getImm(MO3);
2374
882
  if (ShAmt) {
2375
    //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
2376
557
    SStream_concat0(O, ", lsl ");
2377
557
    SStream_concat(O, "#%u", ShAmt);
2378
2379
557
    if (MI->csh->detail) {
2380
557
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
2381
557
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;
2382
557
    }
2383
557
  }
2384
2385
882
  SStream_concat0(O, "]");
2386
882
  set_mem_access(MI, false);
2387
882
}
2388
2389
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2390
120
{
2391
120
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
2392
2393
#if defined(_KERNEL_MODE)
2394
  // Issue #681: Windows kernel does not support formatting float point
2395
  SStream_concat(O, "#<float_point_unsupported>");
2396
#else
2397
120
  SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
2398
120
#endif
2399
2400
120
  if (MI->csh->detail) {
2401
120
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
2402
120
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
2403
120
    MI->flat_insn->detail->arm.op_count++;
2404
120
  }
2405
120
}
2406
2407
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2408
1.37k
{
2409
1.37k
  unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2410
1.37k
  unsigned EltBits;
2411
1.37k
  uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
2412
2413
1.37k
  if (Val > HEX_THRESHOLD)
2414
1.28k
    SStream_concat(O, "#0x%"PRIx64, Val);
2415
87
  else
2416
87
    SStream_concat(O, "#%"PRIu64, Val);
2417
2418
1.37k
  if (MI->csh->detail) {
2419
1.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2420
1.37k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
2421
1.37k
    MI->flat_insn->detail->arm.op_count++;
2422
1.37k
  }
2423
1.37k
}
2424
2425
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
2426
828
{
2427
828
  unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2428
2429
828
  printUInt32Bang(O, Imm + 1);
2430
2431
828
  if (MI->csh->detail) {
2432
828
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2433
828
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
2434
828
    MI->flat_insn->detail->arm.op_count++;
2435
828
  }
2436
828
}
2437
2438
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2439
973
{
2440
973
  unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2441
2442
973
  if (Imm == 0)
2443
228
    return;
2444
2445
745
  SStream_concat0(O, ", ror #");
2446
2447
745
  switch (Imm) {
2448
0
    default: //assert (0 && "illegal ror immediate!");
2449
226
    case 1: SStream_concat0(O, "8"); break;
2450
54
    case 2: SStream_concat0(O, "16"); break;
2451
465
    case 3: SStream_concat0(O, "24"); break;
2452
745
  }
2453
2454
745
  if (MI->csh->detail) {
2455
745
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
2456
745
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
2457
745
  }
2458
745
}
2459
2460
static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2461
4.97k
{
2462
4.97k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
2463
4.97k
  unsigned Bits = MCOperand_getImm(Op) & 0xFF;
2464
4.97k
  unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7;
2465
4.97k
  int32_t Rotated;
2466
4.97k
  bool  PrintUnsigned = false;
2467
2468
4.97k
  switch (MCInst_getOpcode(MI)) {
2469
239
    case ARM_MOVi:
2470
      // Movs to PC should be treated unsigned
2471
239
      PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC);
2472
239
      break;
2473
369
    case ARM_MSRi:
2474
      // Movs to special registers should be treated unsigned
2475
369
      PrintUnsigned = true;
2476
369
      break;
2477
4.97k
  }
2478
2479
4.97k
  Rotated = rotr32(Bits, Rot);
2480
4.97k
  if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) {
2481
    // #rot has the least possible value
2482
4.20k
    if (PrintUnsigned) {
2483
345
      if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD)
2484
316
        SStream_concat(O, "#0x%x", Rotated);
2485
29
      else
2486
29
        SStream_concat(O, "#%u", Rotated);
2487
3.86k
    } else if (Rotated >= 0) {
2488
3.29k
      if (Rotated > HEX_THRESHOLD)
2489
3.06k
        SStream_concat(O, "#0x%x", Rotated);
2490
226
      else
2491
226
        SStream_concat(O, "#%u", Rotated);
2492
3.29k
    } else {
2493
568
      SStream_concat(O, "#0x%x", Rotated);
2494
568
    }
2495
2496
4.20k
    if (MI->csh->detail) {
2497
4.20k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2498
4.20k
      MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated;
2499
4.20k
      MI->flat_insn->detail->arm.op_count++;
2500
4.20k
    }
2501
2502
4.20k
    return;
2503
4.20k
  }
2504
2505
  // Explicit #bits, #rot implied
2506
769
  SStream_concat(O, "#%u, #%u", Bits, Rot);
2507
2508
769
  if (MI->csh->detail) {
2509
769
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2510
769
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits;
2511
769
    MI->flat_insn->detail->arm.op_count++;
2512
769
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2513
769
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot;
2514
769
    MI->flat_insn->detail->arm.op_count++;
2515
769
  }
2516
769
}
2517
2518
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
2519
620
{
2520
620
  unsigned tmp;
2521
2522
620
  tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2523
2524
620
  printUInt32Bang(O, tmp);
2525
2526
620
  if (MI->csh->detail) {
2527
620
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2528
620
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
2529
620
    MI->flat_insn->detail->arm.op_count++;
2530
620
  }
2531
620
}
2532
2533
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
2534
207
{
2535
207
  unsigned tmp;
2536
2537
207
  tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2538
2539
207
  printUInt32Bang(O, tmp);
2540
2541
207
  if (MI->csh->detail) {
2542
207
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2543
207
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
2544
207
    MI->flat_insn->detail->arm.op_count++;
2545
207
  }
2546
207
}
2547
2548
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
2549
1.72k
{
2550
1.72k
  unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2551
2552
1.72k
  if (tmp > HEX_THRESHOLD)
2553
0
    SStream_concat(O, "[0x%x]", tmp);
2554
1.72k
  else
2555
1.72k
    SStream_concat(O, "[%u]", tmp);
2556
2557
1.72k
  if (MI->csh->detail) {
2558
1.72k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
2559
1.72k
  }
2560
1.72k
}
2561
2562
static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
2563
919
{
2564
919
  SStream_concat0(O, "{");
2565
2566
919
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2567
2568
919
  if (MI->csh->detail) {
2569
919
#ifndef CAPSTONE_DIET
2570
919
    uint8_t access;
2571
2572
919
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2573
919
#endif
2574
2575
919
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2576
919
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2577
919
#ifndef CAPSTONE_DIET
2578
919
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2579
919
#endif
2580
919
    MI->flat_insn->detail->arm.op_count++;
2581
2582
919
#ifndef CAPSTONE_DIET
2583
919
  MI->ac_idx++;
2584
919
#endif
2585
919
  }
2586
2587
919
  SStream_concat0(O, "}");
2588
919
}
2589
2590
static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O)
2591
2.20k
{
2592
2.20k
#ifndef CAPSTONE_DIET
2593
2.20k
  uint8_t access;
2594
2.20k
#endif
2595
2.20k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2596
2.20k
  unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
2597
2.20k
  unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1);
2598
2599
2.20k
#ifndef CAPSTONE_DIET
2600
2.20k
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2601
2.20k
#endif
2602
2603
2.20k
  SStream_concat0(O, "{");
2604
2605
2.20k
  printRegName(MI->csh, O, Reg0);
2606
2607
2.20k
  if (MI->csh->detail) {
2608
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2609
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2610
2.20k
#ifndef CAPSTONE_DIET
2611
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2612
2.20k
#endif
2613
2.20k
    MI->flat_insn->detail->arm.op_count++;
2614
2.20k
  }
2615
2616
2.20k
  SStream_concat0(O, ", ");
2617
2618
2.20k
  printRegName(MI->csh, O, Reg1);
2619
2620
2.20k
  if (MI->csh->detail) {
2621
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2622
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2623
2.20k
#ifndef CAPSTONE_DIET
2624
2.20k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2625
2.20k
#endif
2626
2.20k
    MI->flat_insn->detail->arm.op_count++;
2627
2.20k
  }
2628
2629
2.20k
  SStream_concat0(O, "}");
2630
2631
2.20k
#ifndef CAPSTONE_DIET
2632
2.20k
  MI->ac_idx++;
2633
2.20k
#endif
2634
2.20k
}
2635
2636
static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O)
2637
1.46k
{
2638
1.46k
#ifndef CAPSTONE_DIET
2639
1.46k
  uint8_t access;
2640
1.46k
#endif
2641
1.46k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2642
1.46k
  unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
2643
1.46k
  unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2);
2644
2645
1.46k
#ifndef CAPSTONE_DIET
2646
1.46k
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2647
1.46k
#endif
2648
2649
1.46k
  SStream_concat0(O, "{");
2650
2651
1.46k
  printRegName(MI->csh, O, Reg0);
2652
2653
1.46k
  if (MI->csh->detail) {
2654
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2655
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2656
1.46k
#ifndef CAPSTONE_DIET
2657
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2658
1.46k
#endif
2659
1.46k
    MI->flat_insn->detail->arm.op_count++;
2660
1.46k
  }
2661
2662
1.46k
  SStream_concat0(O, ", ");
2663
2664
1.46k
  printRegName(MI->csh, O, Reg1);
2665
2666
1.46k
  if (MI->csh->detail) {
2667
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2668
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2669
1.46k
#ifndef CAPSTONE_DIET
2670
1.46k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2671
1.46k
#endif
2672
1.46k
    MI->flat_insn->detail->arm.op_count++;
2673
1.46k
  }
2674
2675
1.46k
  SStream_concat0(O, "}");
2676
2677
1.46k
#ifndef CAPSTONE_DIET
2678
1.46k
  MI->ac_idx++;
2679
1.46k
#endif
2680
1.46k
}
2681
2682
static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
2683
1.10k
{
2684
1.10k
#ifndef CAPSTONE_DIET
2685
1.10k
  uint8_t access;
2686
2687
1.10k
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2688
1.10k
#endif
2689
2690
  // Normally, it's not safe to use register enum values directly with
2691
  // addition to get the next register, but for VFP registers, the
2692
  // sort order is guaranteed because they're all of the form D<n>.
2693
1.10k
  SStream_concat0(O, "{");
2694
2695
1.10k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2696
2697
1.10k
  if (MI->csh->detail) {
2698
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2699
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2700
1.10k
#ifndef CAPSTONE_DIET
2701
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2702
1.10k
#endif
2703
1.10k
    MI->flat_insn->detail->arm.op_count++;
2704
1.10k
  }
2705
2706
1.10k
  SStream_concat0(O, ", ");
2707
2708
1.10k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2709
2710
1.10k
  if (MI->csh->detail) {
2711
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2712
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2713
1.10k
#ifndef CAPSTONE_DIET
2714
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2715
1.10k
#endif
2716
1.10k
    MI->flat_insn->detail->arm.op_count++;
2717
1.10k
  }
2718
2719
1.10k
  SStream_concat0(O, ", ");
2720
2721
1.10k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2722
2723
1.10k
  if (MI->csh->detail) {
2724
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2725
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2726
1.10k
#ifndef CAPSTONE_DIET
2727
1.10k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2728
1.10k
#endif
2729
1.10k
    MI->flat_insn->detail->arm.op_count++;
2730
1.10k
  }
2731
2732
1.10k
  SStream_concat0(O, "}");
2733
2734
1.10k
#ifndef CAPSTONE_DIET
2735
1.10k
  MI->ac_idx++;
2736
1.10k
#endif
2737
1.10k
}
2738
2739
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
2740
1.48k
{
2741
1.48k
#ifndef CAPSTONE_DIET
2742
1.48k
  uint8_t access;
2743
2744
1.48k
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2745
1.48k
#endif
2746
2747
  // Normally, it's not safe to use register enum values directly with
2748
  // addition to get the next register, but for VFP registers, the
2749
  // sort order is guaranteed because they're all of the form D<n>.
2750
1.48k
  SStream_concat0(O, "{");
2751
2752
1.48k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2753
2754
1.48k
  if (MI->csh->detail) {
2755
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2756
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2757
1.48k
#ifndef CAPSTONE_DIET
2758
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2759
1.48k
#endif
2760
1.48k
    MI->flat_insn->detail->arm.op_count++;
2761
1.48k
  }
2762
2763
1.48k
  SStream_concat0(O, ", ");
2764
2765
1.48k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2766
2767
1.48k
  if (MI->csh->detail) {
2768
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2769
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2770
1.48k
#ifndef CAPSTONE_DIET
2771
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2772
1.48k
#endif
2773
1.48k
    MI->flat_insn->detail->arm.op_count++;
2774
1.48k
  }
2775
2776
1.48k
  SStream_concat0(O, ", ");
2777
2778
1.48k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2779
2780
1.48k
  if (MI->csh->detail) {
2781
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2782
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2783
1.48k
#ifndef CAPSTONE_DIET
2784
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2785
1.48k
#endif
2786
1.48k
    MI->flat_insn->detail->arm.op_count++;
2787
1.48k
  }
2788
2789
1.48k
  SStream_concat0(O, ", ");
2790
2791
1.48k
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
2792
2793
1.48k
  if (MI->csh->detail) {
2794
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2795
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
2796
1.48k
#ifndef CAPSTONE_DIET
2797
1.48k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2798
1.48k
#endif
2799
1.48k
    MI->flat_insn->detail->arm.op_count++;
2800
1.48k
  }
2801
2802
1.48k
  SStream_concat0(O, "}");
2803
2804
1.48k
#ifndef CAPSTONE_DIET
2805
1.48k
  MI->ac_idx++;
2806
1.48k
#endif
2807
1.48k
}
2808
2809
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2810
128
{
2811
128
#ifndef CAPSTONE_DIET
2812
128
  uint8_t access;
2813
2814
128
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2815
128
#endif
2816
2817
128
  SStream_concat0(O, "{");
2818
2819
128
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2820
2821
128
  if (MI->csh->detail) {
2822
128
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2823
128
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2824
128
#ifndef CAPSTONE_DIET
2825
128
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2826
128
#endif
2827
128
    MI->flat_insn->detail->arm.op_count++;
2828
128
  }
2829
2830
128
  SStream_concat0(O, "[]}");
2831
2832
128
#ifndef CAPSTONE_DIET
2833
128
  MI->ac_idx++;
2834
128
#endif
2835
128
}
2836
2837
static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2838
1.22k
{
2839
1.22k
#ifndef CAPSTONE_DIET
2840
1.22k
  uint8_t access;
2841
1.22k
#endif
2842
1.22k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2843
1.22k
  unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
2844
1.22k
  unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1);
2845
2846
1.22k
#ifndef CAPSTONE_DIET
2847
1.22k
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2848
1.22k
#endif
2849
2850
1.22k
  SStream_concat0(O, "{");
2851
2852
1.22k
  printRegName(MI->csh, O, Reg0);
2853
2854
1.22k
  if (MI->csh->detail) {
2855
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2856
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2857
1.22k
#ifndef CAPSTONE_DIET
2858
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2859
1.22k
#endif
2860
1.22k
    MI->flat_insn->detail->arm.op_count++;
2861
1.22k
  }
2862
2863
1.22k
  SStream_concat0(O, "[], ");
2864
2865
1.22k
  printRegName(MI->csh, O, Reg1);
2866
2867
1.22k
  if (MI->csh->detail) {
2868
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2869
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2870
1.22k
#ifndef CAPSTONE_DIET
2871
1.22k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2872
1.22k
#endif
2873
1.22k
    MI->flat_insn->detail->arm.op_count++;
2874
1.22k
  }
2875
2876
1.22k
  SStream_concat0(O, "[]}");
2877
2878
1.22k
#ifndef CAPSTONE_DIET
2879
1.22k
  MI->ac_idx++;
2880
1.22k
#endif
2881
1.22k
}
2882
2883
static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2884
0
{
2885
0
#ifndef CAPSTONE_DIET
2886
0
  uint8_t access;
2887
2888
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2889
0
#endif
2890
2891
  // Normally, it's not safe to use register enum values directly with
2892
  // addition to get the next register, but for VFP registers, the
2893
  // sort order is guaranteed because they're all of the form D<n>.
2894
0
  SStream_concat0(O, "{");
2895
2896
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2897
2898
0
  if (MI->csh->detail) {
2899
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2900
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2901
0
#ifndef CAPSTONE_DIET
2902
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2903
0
#endif
2904
0
    MI->flat_insn->detail->arm.op_count++;
2905
0
  }
2906
2907
0
  SStream_concat0(O, "[], ");
2908
2909
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2910
2911
0
  if (MI->csh->detail) {
2912
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2913
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2914
0
#ifndef CAPSTONE_DIET
2915
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2916
0
#endif
2917
0
    MI->flat_insn->detail->arm.op_count++;
2918
0
  }
2919
2920
0
  SStream_concat0(O, "[], ");
2921
2922
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2923
2924
0
  if (MI->csh->detail) {
2925
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2926
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2927
0
#ifndef CAPSTONE_DIET
2928
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2929
0
#endif
2930
0
    MI->flat_insn->detail->arm.op_count++;
2931
0
  }
2932
2933
0
  SStream_concat0(O, "[]}");
2934
2935
0
#ifndef CAPSTONE_DIET
2936
0
  MI->ac_idx++;
2937
0
#endif
2938
0
}
2939
2940
static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2941
0
{
2942
0
#ifndef CAPSTONE_DIET
2943
0
  uint8_t access;
2944
2945
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2946
0
#endif
2947
2948
  // Normally, it's not safe to use register enum values directly with
2949
  // addition to get the next register, but for VFP registers, the
2950
  // sort order is guaranteed because they're all of the form D<n>.
2951
0
  SStream_concat0(O, "{");
2952
2953
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2954
2955
0
  if (MI->csh->detail) {
2956
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2957
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2958
0
#ifndef CAPSTONE_DIET
2959
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2960
0
#endif
2961
0
    MI->flat_insn->detail->arm.op_count++;
2962
0
  }
2963
2964
0
  SStream_concat0(O, "[], ");
2965
2966
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2967
2968
0
  if (MI->csh->detail) {
2969
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2970
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2971
0
#ifndef CAPSTONE_DIET
2972
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2973
0
#endif
2974
0
    MI->flat_insn->detail->arm.op_count++;
2975
0
  }
2976
2977
0
  SStream_concat0(O, "[], ");
2978
2979
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2980
2981
0
  if (MI->csh->detail) {
2982
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2983
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2984
0
#ifndef CAPSTONE_DIET
2985
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2986
0
#endif
2987
0
    MI->flat_insn->detail->arm.op_count++;
2988
0
  }
2989
2990
0
  SStream_concat0(O, "[], ");
2991
2992
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
2993
2994
0
  if (MI->csh->detail) {
2995
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2996
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
2997
0
#ifndef CAPSTONE_DIET
2998
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
2999
0
#endif
3000
0
    MI->flat_insn->detail->arm.op_count++;
3001
0
  }
3002
3003
0
  SStream_concat0(O, "[]}");
3004
3005
0
#ifndef CAPSTONE_DIET
3006
0
  MI->ac_idx++;
3007
0
#endif
3008
0
}
3009
3010
static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
3011
386
{
3012
386
#ifndef CAPSTONE_DIET
3013
386
  uint8_t access;
3014
386
#endif
3015
386
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
3016
386
  unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
3017
386
  unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2);
3018
3019
386
#ifndef CAPSTONE_DIET
3020
386
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
3021
386
#endif
3022
3023
386
  SStream_concat0(O, "{");
3024
3025
386
  printRegName(MI->csh, O, Reg0);
3026
3027
386
  if (MI->csh->detail) {
3028
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3029
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
3030
386
#ifndef CAPSTONE_DIET
3031
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3032
386
#endif
3033
386
    MI->flat_insn->detail->arm.op_count++;
3034
386
  }
3035
3036
386
  SStream_concat0(O, "[], ");
3037
3038
386
  printRegName(MI->csh, O, Reg1);
3039
3040
386
  if (MI->csh->detail) {
3041
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3042
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
3043
386
#ifndef CAPSTONE_DIET
3044
386
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3045
386
#endif
3046
386
    MI->flat_insn->detail->arm.op_count++;
3047
386
  }
3048
3049
386
  SStream_concat0(O, "[]}");
3050
3051
386
#ifndef CAPSTONE_DIET
3052
386
  MI->ac_idx++;
3053
386
#endif
3054
386
}
3055
3056
static void printVectorListThreeSpacedAllLanes(MCInst *MI,
3057
    unsigned OpNum, SStream *O)
3058
0
{
3059
0
#ifndef CAPSTONE_DIET
3060
0
  uint8_t access;
3061
3062
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
3063
0
#endif
3064
3065
  // Normally, it's not safe to use register enum values directly with
3066
  // addition to get the next register, but for VFP registers, the
3067
  // sort order is guaranteed because they're all of the form D<n>.
3068
0
  SStream_concat0(O, "{");
3069
3070
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
3071
3072
0
  if (MI->csh->detail) {
3073
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3074
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
3075
0
#ifndef CAPSTONE_DIET
3076
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3077
0
#endif
3078
0
    MI->flat_insn->detail->arm.op_count++;
3079
0
  }
3080
3081
0
  SStream_concat0(O, "[], ");
3082
3083
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
3084
3085
0
  if (MI->csh->detail) {
3086
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3087
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
3088
0
#ifndef CAPSTONE_DIET
3089
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3090
0
#endif
3091
0
    MI->flat_insn->detail->arm.op_count++;
3092
0
  }
3093
3094
0
  SStream_concat0(O, "[], ");
3095
3096
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
3097
3098
0
  if (MI->csh->detail) {
3099
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3100
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
3101
0
#ifndef CAPSTONE_DIET
3102
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3103
0
#endif
3104
0
    MI->flat_insn->detail->arm.op_count++;
3105
0
  }
3106
3107
0
  SStream_concat0(O, "[]}");
3108
3109
0
#ifndef CAPSTONE_DIET
3110
0
  MI->ac_idx++;
3111
0
#endif
3112
0
}
3113
3114
static void printVectorListFourSpacedAllLanes(MCInst *MI,
3115
    unsigned OpNum, SStream *O)
3116
0
{
3117
0
#ifndef CAPSTONE_DIET
3118
0
  uint8_t access;
3119
3120
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
3121
0
#endif
3122
3123
  // Normally, it's not safe to use register enum values directly with
3124
  // addition to get the next register, but for VFP registers, the
3125
  // sort order is guaranteed because they're all of the form D<n>.
3126
0
  SStream_concat0(O, "{");
3127
3128
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
3129
3130
0
  if (MI->csh->detail) {
3131
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3132
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
3133
0
#ifndef CAPSTONE_DIET
3134
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3135
0
#endif
3136
0
    MI->flat_insn->detail->arm.op_count++;
3137
0
  }
3138
3139
0
  SStream_concat0(O, "[], ");
3140
3141
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
3142
3143
0
  if (MI->csh->detail) {
3144
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3145
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
3146
0
#ifndef CAPSTONE_DIET
3147
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3148
0
#endif
3149
0
    MI->flat_insn->detail->arm.op_count++;
3150
0
  }
3151
3152
0
  SStream_concat0(O, "[], ");
3153
3154
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
3155
3156
0
  if (MI->csh->detail) {
3157
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3158
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
3159
0
#ifndef CAPSTONE_DIET
3160
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3161
0
#endif
3162
0
    MI->flat_insn->detail->arm.op_count++;
3163
0
  }
3164
3165
0
  SStream_concat0(O, "[], ");
3166
3167
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
3168
3169
0
  if (MI->csh->detail) {
3170
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3171
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
3172
0
#ifndef CAPSTONE_DIET
3173
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3174
0
#endif
3175
0
    MI->flat_insn->detail->arm.op_count++;
3176
0
  }
3177
3178
0
  SStream_concat0(O, "[]}");
3179
3180
0
#ifndef CAPSTONE_DIET
3181
0
  MI->ac_idx++;
3182
0
#endif
3183
0
}
3184
3185
static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
3186
0
{
3187
0
#ifndef CAPSTONE_DIET
3188
0
  uint8_t access;
3189
3190
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
3191
0
#endif
3192
3193
  // Normally, it's not safe to use register enum values directly with
3194
  // addition to get the next register, but for VFP registers, the
3195
  // sort order is guaranteed because they're all of the form D<n>.
3196
0
  SStream_concat0(O, "{");
3197
3198
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
3199
3200
0
  if (MI->csh->detail) {
3201
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3202
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
3203
0
#ifndef CAPSTONE_DIET
3204
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3205
0
#endif
3206
0
    MI->flat_insn->detail->arm.op_count++;
3207
0
  }
3208
3209
0
  SStream_concat0(O, ", ");
3210
3211
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
3212
3213
0
  if (MI->csh->detail) {
3214
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3215
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
3216
0
#ifndef CAPSTONE_DIET
3217
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3218
0
#endif
3219
0
    MI->flat_insn->detail->arm.op_count++;
3220
0
  }
3221
3222
0
  SStream_concat0(O, ", ");
3223
3224
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
3225
3226
0
  if (MI->csh->detail) {
3227
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3228
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
3229
0
#ifndef CAPSTONE_DIET
3230
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3231
0
#endif
3232
0
    MI->flat_insn->detail->arm.op_count++;
3233
0
  }
3234
3235
0
  SStream_concat0(O, "}");
3236
3237
0
#ifndef CAPSTONE_DIET
3238
0
  MI->ac_idx++;
3239
0
#endif
3240
0
}
3241
3242
static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
3243
0
{
3244
0
#ifndef CAPSTONE_DIET
3245
0
  uint8_t access;
3246
3247
0
  access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
3248
0
#endif
3249
3250
  // Normally, it's not safe to use register enum values directly with
3251
  // addition to get the next register, but for VFP registers, the
3252
  // sort order is guaranteed because they're all of the form D<n>.
3253
0
  SStream_concat0(O, "{");
3254
3255
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
3256
3257
0
  if (MI->csh->detail) {
3258
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3259
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
3260
0
#ifndef CAPSTONE_DIET
3261
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3262
0
#endif
3263
0
    MI->flat_insn->detail->arm.op_count++;
3264
0
  }
3265
3266
0
  SStream_concat0(O, ", ");
3267
3268
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
3269
3270
0
  if (MI->csh->detail) {
3271
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3272
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
3273
0
#ifndef CAPSTONE_DIET
3274
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3275
0
#endif
3276
0
    MI->flat_insn->detail->arm.op_count++;
3277
0
  }
3278
3279
0
  SStream_concat0(O, ", ");
3280
3281
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
3282
3283
0
  if (MI->csh->detail) {
3284
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3285
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
3286
0
#ifndef CAPSTONE_DIET
3287
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3288
0
#endif
3289
0
    MI->flat_insn->detail->arm.op_count++;
3290
0
  }
3291
3292
0
  SStream_concat0(O, ", ");
3293
3294
0
  printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
3295
3296
0
  if (MI->csh->detail) {
3297
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3298
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
3299
0
#ifndef CAPSTONE_DIET
3300
0
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
3301
0
#endif
3302
0
    MI->flat_insn->detail->arm.op_count++;
3303
0
  }
3304
3305
0
  SStream_concat0(O, "}");
3306
3307
0
#ifndef CAPSTONE_DIET
3308
0
  MI->ac_idx++;
3309
0
#endif
3310
0
}
3311
3312
static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder)
3313
352
{
3314
352
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
3315
352
  unsigned tmp = (unsigned)((Val * Angle) + Remainder);
3316
3317
352
  printUInt32Bang(O, tmp);
3318
352
  if (MI->csh->detail) {
3319
352
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
3320
352
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
3321
352
    MI->flat_insn->detail->arm.op_count++;
3322
352
  }
3323
352
}
3324
3325
void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)
3326
8.26k
{
3327
8.26k
  if (MI->csh->detail) {
3328
8.26k
    MI->flat_insn->detail->arm.vector_data = vd;
3329
8.26k
  }
3330
8.26k
}
3331
3332
void ARM_addVectorDataSize(MCInst *MI, int size)
3333
17.7k
{
3334
17.7k
  if (MI->csh->detail) {
3335
17.7k
    MI->flat_insn->detail->arm.vector_size = size;
3336
17.7k
  }
3337
17.7k
}
3338
3339
void ARM_addReg(MCInst *MI, int reg)
3340
1.43k
{
3341
1.43k
  if (MI->csh->detail) {
3342
1.43k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
3343
1.43k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
3344
1.43k
    MI->flat_insn->detail->arm.op_count++;
3345
1.43k
  }
3346
1.43k
}
3347
3348
void ARM_addUserMode(MCInst *MI)
3349
1.33k
{
3350
1.33k
  if (MI->csh->detail) {
3351
1.33k
    MI->flat_insn->detail->arm.usermode = true;
3352
1.33k
  }
3353
1.33k
}
3354
3355
void ARM_addSysReg(MCInst *MI, arm_sysreg reg)
3356
2.61k
{
3357
2.61k
  if (MI->csh->detail) {
3358
2.61k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG;
3359
2.61k
    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
3360
2.61k
    MI->flat_insn->detail->arm.op_count++;
3361
2.61k
  }
3362
2.61k
}
3363
3364
#endif