Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/PowerPC/PPCInstPrinter.c
Line
Count
Source (jump to first uncovered line)
1
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an PPC MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17
#ifdef CAPSTONE_HAS_POWERPC
18
19
#include <stdio.h>
20
#include <stdlib.h>
21
#include <string.h>
22
23
#include "PPCInstPrinter.h"
24
#include "PPCPredicates.h"
25
#include "../../MCInst.h"
26
#include "../../utils.h"
27
#include "../../SStream.h"
28
#include "../../MCRegisterInfo.h"
29
#include "../../MathExtras.h"
30
#include "PPCMapping.h"
31
32
#ifndef CAPSTONE_DIET
33
static const char *getRegisterName(unsigned RegNo);
34
#endif
35
36
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
37
static void printInstruction(MCInst *MI, SStream *O);
38
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
39
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
40
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info);
41
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
42
    unsigned PrintMethodIdx, SStream *OS);
43
44
#if 0
45
static void printRegName(SStream *OS, unsigned RegNo)
46
{
47
  char *RegName = getRegisterName(RegNo);
48
49
  if (RegName[0] == 'q' /* QPX */) {
50
    // The system toolchain on the BG/Q does not understand QPX register names
51
    // in .cfi_* directives, so print the name of the floating-point
52
    // subregister instead.
53
    RegName[0] = 'f';
54
  }
55
56
  SStream_concat0(OS, RegName);
57
}
58
#endif
59
60
static void set_mem_access(MCInst *MI, bool status)
61
11.9k
{
62
11.9k
  if (MI->csh->detail != CS_OPT_ON)
63
0
    return;
64
65
11.9k
  MI->csh->doing_mem = status;
66
67
11.9k
  if (status) {
68
5.98k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
69
5.98k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
70
5.98k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
71
5.98k
  } else {
72
    // done, create the next operand slot
73
5.98k
    MI->flat_insn->detail->ppc.op_count++;
74
5.98k
  }
75
11.9k
}
76
77
void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
78
31.2k
{
79
31.2k
  if (((cs_struct *)ud)->detail != CS_OPT_ON)
80
0
    return;
81
82
  // check if this insn has branch hint
83
31.2k
  if (strrchr(insn->mnemonic, '+') != NULL && !strstr(insn_asm, ".+")) {
84
1.58k
    insn->detail->ppc.bh = PPC_BH_PLUS;
85
29.6k
  } else if (strrchr(insn->mnemonic, '-') != NULL) {
86
499
    insn->detail->ppc.bh = PPC_BH_MINUS;
87
499
  }
88
89
31.2k
  if (strrchr(insn->mnemonic, '.') != NULL) {
90
3.14k
    insn->detail->ppc.update_cr0 = true;
91
3.14k
  }
92
31.2k
}
93
94
#define GET_INSTRINFO_ENUM
95
#include "PPCGenInstrInfo.inc"
96
97
#define GET_REGINFO_ENUM
98
#include "PPCGenRegisterInfo.inc"
99
100
static void op_addBC(MCInst *MI, unsigned int bc)
101
1.29k
{
102
1.29k
  if (MI->csh->detail) {
103
1.29k
    MI->flat_insn->detail->ppc.bc = (ppc_bc)bc;
104
1.29k
  }
105
1.29k
}
106
107
473
#define CREQ (0)
108
264
#define CRGT (1)
109
814
#define CRLT (2)
110
813
#define CRUN (3)
111
112
static int getBICRCond(int bi)
113
2.36k
{
114
2.36k
  return (bi - PPC_CR0EQ) >> 3;
115
2.36k
}
116
117
static int getBICR(int bi)
118
2.36k
{
119
2.36k
  return ((bi - PPC_CR0EQ) & 7) + PPC_CR0;
120
2.36k
}
121
122
static void op_addReg(MCInst *MI, unsigned int reg)
123
938
{
124
938
  if (MI->csh->detail) {
125
938
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
126
938
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
127
938
    MI->flat_insn->detail->ppc.op_count++;
128
938
  }
129
938
}
130
131
static void add_CRxx(MCInst *MI, ppc_reg reg)
132
524
{
133
524
  if (MI->csh->detail) {
134
524
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
135
524
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
136
524
    MI->flat_insn->detail->ppc.op_count++;
137
524
  }
138
524
}
139
140
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info)
141
31.0k
{
142
31.0k
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
143
31.0k
  SStream ss;
144
31.0k
  const char *opCode;
145
31.0k
  char *tmp, *AsmMnem, *AsmOps, *c;
146
31.0k
  int OpIdx, PrintMethodIdx;
147
31.0k
  int decCtr = false, needComma = false;
148
31.0k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
149
150
31.0k
  SStream_Init(&ss);
151
152
31.0k
  switch (MCInst_getOpcode(MI)) {
153
27.9k
    default: return NULL;
154
1.15k
    case PPC_gBC:
155
1.15k
         opCode = "b%s";
156
1.15k
         break;
157
526
    case PPC_gBCA:
158
526
         opCode = "b%sa";
159
526
         break;
160
7
    case PPC_gBCCTR:
161
7
         opCode = "b%sctr";
162
7
         break;
163
5
    case PPC_gBCCTRL:
164
5
         opCode = "b%sctrl";
165
5
         break;
166
679
    case PPC_gBCL:
167
679
         opCode = "b%sl";
168
679
         break;
169
677
    case PPC_gBCLA:
170
677
         opCode = "b%sla";
171
677
         break;
172
8
    case PPC_gBCLR:
173
8
         opCode = "b%slr";
174
8
         break;
175
6
    case PPC_gBCLRL:
176
6
         opCode = "b%slrl";
177
6
         break;
178
31.0k
  }
179
180
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
181
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
182
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
183
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
184
209
    SStream_concat(&ss, opCode, "dnzf");
185
209
    decCtr = true;
186
209
  }
187
188
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
189
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
190
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
191
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
192
390
    SStream_concat(&ss, opCode, "dzf");
193
390
    decCtr = true;
194
390
  }
195
196
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
197
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
198
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
199
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
200
3.06k
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
201
3.06k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
202
439
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
203
204
439
    switch(cr) {
205
10
      case CREQ:
206
10
        SStream_concat(&ss, opCode, "ne");
207
10
        break;
208
32
      case CRGT:
209
32
        SStream_concat(&ss, opCode, "le");
210
32
        break;
211
29
      case CRLT:
212
29
        SStream_concat(&ss, opCode, "ge");
213
29
        break;
214
368
      case CRUN:
215
368
        SStream_concat(&ss, opCode, "ns");
216
368
        break;
217
439
    }
218
219
439
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
220
28
      SStream_concat0(&ss, "-");
221
222
439
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
223
219
      SStream_concat0(&ss, "+");
224
225
439
    decCtr = false;
226
439
  }
227
228
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
229
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
230
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
231
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
232
210
    SStream_concat(&ss, opCode, "dnzt");
233
210
    decCtr = true;
234
210
  }
235
236
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
237
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
238
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
239
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
240
481
    SStream_concat(&ss, opCode, "dzt");
241
481
    decCtr = true;
242
481
  }
243
244
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
245
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
246
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
247
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
248
3.06k
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
249
3.06k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
250
635
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
251
252
635
    switch(cr) {
253
223
      case CREQ:
254
223
        SStream_concat(&ss, opCode, "eq");
255
223
        break;
256
8
      case CRGT:
257
8
        SStream_concat(&ss, opCode, "gt");
258
8
        break;
259
266
      case CRLT:
260
266
        SStream_concat(&ss, opCode, "lt");
261
266
        break;
262
138
      case CRUN:
263
138
        SStream_concat(&ss, opCode, "so");
264
138
        break;
265
635
    }
266
267
635
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
268
147
      SStream_concat0(&ss, "-");
269
270
635
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
271
232
      SStream_concat0(&ss, "+");
272
273
635
    decCtr = false;
274
635
  }
275
276
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
277
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
278
3.06k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
279
173
    SStream_concat(&ss, opCode, "dnz");
280
281
173
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
282
82
      SStream_concat0(&ss, "-");
283
284
173
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
285
30
      SStream_concat0(&ss, "+");
286
287
173
    needComma = false;
288
173
  }
289
290
3.06k
  if (MCInst_getNumOperands(MI) == 3 &&
291
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
292
3.06k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
293
525
    SStream_concat(&ss, opCode, "dz");
294
295
525
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
296
70
      SStream_concat0(&ss, "-");
297
298
525
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
299
323
      SStream_concat0(&ss, "+");
300
301
525
    needComma = false;
302
525
  }
303
304
3.06k
  if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
305
3.06k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
306
3.06k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
307
3.06k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
308
2.36k
    int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
309
310
2.36k
    if (decCtr) {
311
1.29k
      int cd;
312
1.29k
      needComma = true;
313
1.29k
      SStream_concat0(&ss, " ");
314
315
1.29k
      if (cr > PPC_CR0) {
316
766
        SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
317
766
      }
318
319
1.29k
      cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
320
1.29k
      switch(cd) {
321
240
        case CREQ:
322
240
          SStream_concat0(&ss, "eq");
323
240
          if (cr <= PPC_CR0)
324
11
            add_CRxx(MI, PPC_REG_CR0EQ);
325
240
          op_addBC(MI, PPC_BC_EQ);
326
240
          break;
327
224
        case CRGT:
328
224
          SStream_concat0(&ss, "gt");
329
224
          if (cr <= PPC_CR0)
330
114
            add_CRxx(MI, PPC_REG_CR0GT);
331
224
          op_addBC(MI, PPC_BC_GT);
332
224
          break;
333
519
        case CRLT:
334
519
          SStream_concat0(&ss, "lt");
335
519
          if (cr <= PPC_CR0)
336
233
            add_CRxx(MI, PPC_REG_CR0LT);
337
519
          op_addBC(MI, PPC_BC_LT);
338
519
          break;
339
307
        case CRUN:
340
307
          SStream_concat0(&ss, "so");
341
307
          if (cr <= PPC_CR0)
342
166
            add_CRxx(MI, PPC_REG_CR0UN);
343
307
          op_addBC(MI, PPC_BC_SO);
344
307
          break;
345
1.29k
      }
346
347
1.29k
      if (cr > PPC_CR0) {
348
766
        if (MI->csh->detail) {
349
766
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
350
766
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
351
766
          MI->flat_insn->detail->ppc.op_count++;
352
766
        }
353
766
      }
354
1.29k
    } else {
355
1.07k
      if (cr > PPC_CR0) {
356
938
        needComma = true;
357
938
        SStream_concat(&ss, " cr%d", cr - PPC_CR0);
358
938
        op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
359
938
      }
360
1.07k
    }
361
2.36k
  }
362
363
3.06k
  if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
364
3.06k
      MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
365
2.88k
    if (needComma)
366
2.07k
      SStream_concat0(&ss, ",");
367
368
2.88k
    SStream_concat0(&ss, " $\xFF\x03\x01");
369
2.88k
  }
370
371
3.06k
  tmp = cs_strdup(ss.buffer);
372
3.06k
  AsmMnem = tmp;
373
17.8k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
374
17.8k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
375
3.03k
      *AsmOps = '\0';
376
3.03k
      AsmOps++;
377
3.03k
      break;
378
3.03k
    }
379
17.8k
  }
380
381
3.06k
  SStream_concat0(OS, AsmMnem);
382
3.06k
  if (*AsmOps) {
383
3.03k
    SStream_concat0(OS, "\t");
384
20.0k
    for (c = AsmOps; *c; c++) {
385
17.0k
      if (*c == '$') {
386
2.88k
        c += 1;
387
2.88k
        if (*c == (char)0xff) {
388
2.88k
          c += 1;
389
2.88k
          OpIdx = *c - 1;
390
2.88k
          c += 1;
391
2.88k
          PrintMethodIdx = *c - 1;
392
2.88k
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
393
2.88k
        } else
394
0
          printOperand(MI, *c - 1, OS);
395
14.1k
      } else {
396
14.1k
        SStream_concat1(OS, *c);
397
14.1k
      }
398
17.0k
    }
399
3.03k
  }
400
401
3.06k
  return tmp;
402
3.06k
}
403
404
static bool isBOCTRBranch(unsigned int op)
405
31.0k
{
406
31.0k
  return ((op >= PPC_BDNZ) && (op <= PPC_BDZp));
407
31.0k
}
408
409
void PPC_printInst(MCInst *MI, SStream *O, void *Info)
410
31.2k
{
411
31.2k
  char *mnem;
412
31.2k
  unsigned int opcode = MCInst_getOpcode(MI);
413
31.2k
  memset(O->buffer, 0, sizeof(O->buffer));
414
415
  // printf("opcode = %u\n", opcode);
416
417
  // Check for slwi/srwi mnemonics.
418
31.2k
  if (opcode == PPC_RLWINM) {
419
143
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
420
143
    unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
421
143
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
422
143
    bool useSubstituteMnemonic = false;
423
424
143
    if (SH <= 31 && MB == 0 && ME == (31 - SH)) {
425
40
      SStream_concat0(O, "slwi\t");
426
40
      MCInst_setOpcodePub(MI, PPC_INS_SLWI);
427
40
      useSubstituteMnemonic = true;
428
40
    }
429
430
143
    if (SH <= 31 && MB == (32 - SH) && ME == 31) {
431
16
      SStream_concat0(O, "srwi\t");
432
16
      MCInst_setOpcodePub(MI, PPC_INS_SRWI);
433
16
      useSubstituteMnemonic = true;
434
16
      SH = 32 - SH;
435
16
    }
436
437
143
    if (useSubstituteMnemonic) {
438
56
      printOperand(MI, 0, O);
439
56
      SStream_concat0(O, ", ");
440
56
      printOperand(MI, 1, O);
441
442
56
      if (SH > HEX_THRESHOLD)
443
7
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
444
49
      else
445
49
        SStream_concat(O, ", %u", (unsigned int)SH);
446
447
56
      if (MI->csh->detail) {
448
56
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
449
450
56
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
451
56
        ppc->operands[ppc->op_count].imm = SH;
452
56
        ++ppc->op_count;
453
56
      }
454
455
56
      return;
456
56
    }
457
143
  }
458
459
31.1k
  if ((opcode == PPC_OR || opcode == PPC_OR8) &&
460
31.1k
      MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
461
20
    SStream_concat0(O, "mr\t");
462
20
    MCInst_setOpcodePub(MI, PPC_INS_MR);
463
464
20
    printOperand(MI, 0, O);
465
20
    SStream_concat0(O, ", ");
466
20
    printOperand(MI, 1, O);
467
468
20
    return;
469
20
  }
470
471
31.1k
  if (opcode == PPC_RLDICR ||
472
31.1k
      opcode == PPC_RLDICR_32) {
473
84
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
474
84
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
475
476
    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
477
84
    if (63 - SH == ME) {
478
18
      SStream_concat0(O, "sldi\t");
479
18
      MCInst_setOpcodePub(MI, PPC_INS_SLDI);
480
481
18
      printOperand(MI, 0, O);
482
18
      SStream_concat0(O, ", ");
483
18
      printOperand(MI, 1, O);
484
485
18
      if (SH > HEX_THRESHOLD)
486
1
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
487
17
      else
488
17
        SStream_concat(O, ", %u", (unsigned int)SH);
489
490
18
      if (MI->csh->detail) {
491
18
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
492
493
18
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
494
18
        ppc->operands[ppc->op_count].imm = SH;
495
18
        ++ppc->op_count;
496
18
      }
497
498
499
18
      return;
500
18
    }
501
84
  }
502
503
  // dcbt[st] is printed manually here because:
504
  //  1. The assembly syntax is different between embedded and server targets
505
  //  2. We must print the short mnemonics for TH == 0 because the
506
  //     embedded/server syntax default will not be stable across assemblers
507
  //  The syntax for dcbt is:
508
  //    dcbt ra, rb, th [server]
509
  //    dcbt th, ra, rb [embedded]
510
  //  where th can be omitted when it is 0. dcbtst is the same.
511
31.1k
  if (opcode == PPC_DCBT || opcode == PPC_DCBTST) {
512
80
    unsigned char TH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
513
514
80
    SStream_concat0(O, "dcbt");
515
80
    MCInst_setOpcodePub(MI, PPC_INS_DCBT);
516
517
80
    if (opcode == PPC_DCBTST) {
518
42
      SStream_concat0(O, "st");
519
42
      MCInst_setOpcodePub(MI, PPC_INS_DCBTST);
520
42
    }
521
522
80
    if (TH == 16) {
523
18
      SStream_concat0(O, "t");
524
18
      MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT);
525
18
    }
526
527
80
    SStream_concat0(O, "\t");
528
529
80
    if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) {
530
0
      if (TH > HEX_THRESHOLD)
531
0
        SStream_concat(O, "0x%x, ", (unsigned int)TH);
532
0
      else
533
0
        SStream_concat(O, "%u, ", (unsigned int)TH);
534
535
0
      if (MI->csh->detail) {
536
0
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
537
538
0
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
539
0
        ppc->operands[ppc->op_count].imm = TH;
540
0
        ++ppc->op_count;
541
0
      }
542
0
    }
543
544
80
    printOperand(MI, 1, O);
545
80
    SStream_concat0(O, ", ");
546
80
    printOperand(MI, 2, O);
547
548
80
    if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) {
549
35
      if (TH > HEX_THRESHOLD)
550
13
        SStream_concat(O, ", 0x%x", (unsigned int)TH);
551
22
      else
552
22
        SStream_concat(O, ", %u", (unsigned int)TH);
553
554
35
      if (MI->csh->detail) {
555
35
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
556
557
35
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
558
35
        ppc->operands[ppc->op_count].imm = TH;
559
35
        ++ppc->op_count;
560
35
      }
561
35
    }
562
563
80
    return;
564
80
  }
565
566
31.0k
  if (opcode == PPC_DCBF) {
567
60
    unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
568
569
60
    if (!L || L == 1 || L == 3) {
570
35
      SStream_concat0(O, "dcbf");
571
35
      MCInst_setOpcodePub(MI, PPC_INS_DCBF);
572
573
35
      if (L == 1 || L == 3) {
574
10
        SStream_concat0(O, "l");
575
10
        MCInst_setOpcodePub(MI, PPC_INS_DCBFL);
576
10
      }
577
578
35
      if (L == 3) {
579
9
        SStream_concat0(O, "p");
580
9
        MCInst_setOpcodePub(MI, PPC_INS_DCBFLP);
581
9
      }
582
583
35
      SStream_concat0(O, "\t");
584
585
35
      printOperand(MI, 1, O);
586
35
      SStream_concat0(O, ", ");
587
35
      printOperand(MI, 2, O);
588
589
35
      return;
590
35
    }
591
60
  }
592
593
31.0k
  if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL ||
594
31.0k
      opcode == PPC_BLA) {
595
750
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
596
750
    bd = SignExtend64(bd, 24);
597
750
    MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
598
750
  }
599
600
31.0k
  if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL ||
601
31.0k
      opcode == PPC_gBCLA) {
602
3.03k
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
603
3.03k
    bd = SignExtend64(bd, 14);
604
3.03k
    MCOperand_setImm(MCInst_getOperand(MI, 2), bd);
605
3.03k
  }
606
607
31.0k
  if (isBOCTRBranch(MCInst_getOpcode(MI))) {
608
250
    if (MCOperand_isImm(MCInst_getOperand(MI,0))) {
609
244
      int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
610
244
      bd = SignExtend64(bd, 14);
611
244
      MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
612
244
    }
613
250
  }
614
615
31.0k
  mnem = printAliasBcc(MI, O, Info);
616
31.0k
  if (!mnem)
617
27.9k
    mnem = printAliasInstr(MI, O, Info);
618
619
31.0k
  if (mnem != NULL) {
620
9.86k
    if (strlen(mnem) > 0) {
621
      // check to remove the last letter of ('.', '-', '+')
622
9.86k
      if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
623
1.24k
        mnem[strlen(mnem) - 1] = '\0';
624
625
9.86k
            MCInst_setOpcodePub(MI, PPC_map_insn(mnem));
626
627
9.86k
            if (MI->csh->detail) {
628
9.86k
        struct ppc_alias alias;
629
630
9.86k
        if (PPC_alias_insn(mnem, &alias)) {
631
1.07k
          MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
632
1.07k
        }
633
9.86k
            }
634
9.86k
    }
635
636
9.86k
    cs_mem_free(mnem);
637
9.86k
  } else
638
21.1k
    printInstruction(MI, O);
639
640
31.0k
  const char *mnem_end = strchr(O->buffer, ' ');
641
31.0k
  unsigned mnem_len = 0;
642
31.0k
  if (mnem_end)
643
29.5k
    mnem_len = mnem_end - O->buffer;
644
31.0k
  if (!mnem_end || mnem_len >= sizeof(MI->flat_insn->mnemonic))
645
1.41k
    mnem_len = sizeof(MI->flat_insn->mnemonic) - 1;
646
647
31.0k
  memset(MI->flat_insn->mnemonic, 0, sizeof(MI->flat_insn->mnemonic));
648
31.0k
  memcpy(MI->flat_insn->mnemonic, O->buffer, mnem_len);
649
31.0k
}
650
651
// FIXME
652
enum ppc_bc_hint {
653
  PPC_BC_LT_MINUS = (0 << 5) | 14,
654
  PPC_BC_LE_MINUS = (1 << 5) |  6,
655
  PPC_BC_EQ_MINUS = (2 << 5) | 14,
656
  PPC_BC_GE_MINUS = (0 << 5) |  6,
657
  PPC_BC_GT_MINUS = (1 << 5) | 14,
658
  PPC_BC_NE_MINUS = (2 << 5) |  6,
659
  PPC_BC_UN_MINUS = (3 << 5) | 14,
660
  PPC_BC_NU_MINUS = (3 << 5) |  6,
661
  PPC_BC_LT_PLUS  = (0 << 5) | 15,
662
  PPC_BC_LE_PLUS  = (1 << 5) |  7,
663
  PPC_BC_EQ_PLUS  = (2 << 5) | 15,
664
  PPC_BC_GE_PLUS  = (0 << 5) |  7,
665
  PPC_BC_GT_PLUS  = (1 << 5) | 15,
666
  PPC_BC_NE_PLUS  = (2 << 5) |  7,
667
  PPC_BC_UN_PLUS  = (3 << 5) | 15,
668
  PPC_BC_NU_PLUS  = (3 << 5) |  7,
669
};
670
671
// FIXME
672
// normalize CC to remove _MINUS & _PLUS
673
static int cc_normalize(int cc)
674
0
{
675
0
  switch(cc) {
676
0
    default: return cc;
677
0
    case PPC_BC_LT_MINUS: return PPC_BC_LT;
678
0
    case PPC_BC_LE_MINUS: return PPC_BC_LE;
679
0
    case PPC_BC_EQ_MINUS: return PPC_BC_EQ;
680
0
    case PPC_BC_GE_MINUS: return PPC_BC_GE;
681
0
    case PPC_BC_GT_MINUS: return PPC_BC_GT;
682
0
    case PPC_BC_NE_MINUS: return PPC_BC_NE;
683
0
    case PPC_BC_UN_MINUS: return PPC_BC_UN;
684
0
    case PPC_BC_NU_MINUS: return PPC_BC_NU;
685
0
    case PPC_BC_LT_PLUS : return PPC_BC_LT;
686
0
    case PPC_BC_LE_PLUS : return PPC_BC_LE;
687
0
    case PPC_BC_EQ_PLUS : return PPC_BC_EQ;
688
0
    case PPC_BC_GE_PLUS : return PPC_BC_GE;
689
0
    case PPC_BC_GT_PLUS : return PPC_BC_GT;
690
0
    case PPC_BC_NE_PLUS : return PPC_BC_NE;
691
0
    case PPC_BC_UN_PLUS : return PPC_BC_UN;
692
0
    case PPC_BC_NU_PLUS : return PPC_BC_NU;
693
0
  }
694
0
}
695
696
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
697
    SStream *O, const char *Modifier)
698
0
{
699
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
700
701
0
  MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
702
703
0
  if (!strcmp(Modifier, "cc")) {
704
0
    switch ((ppc_predicate)Code) {
705
0
      default:  // unreachable
706
0
      case PPC_PRED_LT_MINUS:
707
0
      case PPC_PRED_LT_PLUS:
708
0
      case PPC_PRED_LT:
709
0
        SStream_concat0(O, "lt");
710
0
        return;
711
0
      case PPC_PRED_LE_MINUS:
712
0
      case PPC_PRED_LE_PLUS:
713
0
      case PPC_PRED_LE:
714
0
        SStream_concat0(O, "le");
715
0
        return;
716
0
      case PPC_PRED_EQ_MINUS:
717
0
      case PPC_PRED_EQ_PLUS:
718
0
      case PPC_PRED_EQ:
719
0
        SStream_concat0(O, "eq");
720
0
        return;
721
0
      case PPC_PRED_GE_MINUS:
722
0
      case PPC_PRED_GE_PLUS:
723
0
      case PPC_PRED_GE:
724
0
        SStream_concat0(O, "ge");
725
0
        return;
726
0
      case PPC_PRED_GT_MINUS:
727
0
      case PPC_PRED_GT_PLUS:
728
0
      case PPC_PRED_GT:
729
0
        SStream_concat0(O, "gt");
730
0
        return;
731
0
      case PPC_PRED_NE_MINUS:
732
0
      case PPC_PRED_NE_PLUS:
733
0
      case PPC_PRED_NE:
734
0
        SStream_concat0(O, "ne");
735
0
        return;
736
0
      case PPC_PRED_UN_MINUS:
737
0
      case PPC_PRED_UN_PLUS:
738
0
      case PPC_PRED_UN:
739
0
        SStream_concat0(O, "un");
740
0
        return;
741
0
      case PPC_PRED_NU_MINUS:
742
0
      case PPC_PRED_NU_PLUS:
743
0
      case PPC_PRED_NU:
744
0
        SStream_concat0(O, "nu");
745
0
        return;
746
0
      case PPC_PRED_BIT_SET:
747
0
      case PPC_PRED_BIT_UNSET:
748
        // llvm_unreachable("Invalid use of bit predicate code");
749
0
        SStream_concat0(O, "invalid-predicate");
750
0
        return;
751
0
    }
752
0
  }
753
754
0
  if (!strcmp(Modifier, "pm")) {
755
0
    switch ((ppc_predicate)Code) {
756
0
      case PPC_PRED_LT:
757
0
      case PPC_PRED_LE:
758
0
      case PPC_PRED_EQ:
759
0
      case PPC_PRED_GE:
760
0
      case PPC_PRED_GT:
761
0
      case PPC_PRED_NE:
762
0
      case PPC_PRED_UN:
763
0
      case PPC_PRED_NU:
764
0
        return;
765
0
      case PPC_PRED_LT_MINUS:
766
0
      case PPC_PRED_LE_MINUS:
767
0
      case PPC_PRED_EQ_MINUS:
768
0
      case PPC_PRED_GE_MINUS:
769
0
      case PPC_PRED_GT_MINUS:
770
0
      case PPC_PRED_NE_MINUS:
771
0
      case PPC_PRED_UN_MINUS:
772
0
      case PPC_PRED_NU_MINUS:
773
0
        SStream_concat0(O, "-");
774
0
        return;
775
0
      case PPC_PRED_LT_PLUS:
776
0
      case PPC_PRED_LE_PLUS:
777
0
      case PPC_PRED_EQ_PLUS:
778
0
      case PPC_PRED_GE_PLUS:
779
0
      case PPC_PRED_GT_PLUS:
780
0
      case PPC_PRED_NE_PLUS:
781
0
      case PPC_PRED_UN_PLUS:
782
0
      case PPC_PRED_NU_PLUS:
783
0
        SStream_concat0(O, "+");
784
0
        return;
785
0
      case PPC_PRED_BIT_SET:
786
0
      case PPC_PRED_BIT_UNSET:
787
        // llvm_unreachable("Invalid use of bit predicate code");
788
0
        SStream_concat0(O, "invalid-predicate");
789
0
        return;
790
0
      default:  // unreachable
791
0
        return;
792
0
    }
793
    // llvm_unreachable("Invalid predicate code");
794
0
  }
795
796
  //assert(StringRef(Modifier) == "reg" &&
797
  //    "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
798
0
  printOperand(MI, OpNo + 1, O);
799
0
}
800
801
static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O)
802
0
{
803
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
804
805
0
  if (Code == 2) {
806
0
    SStream_concat0(O, "-");
807
0
  } else if (Code == 3) {
808
0
    SStream_concat0(O, "+");
809
0
  }
810
0
}
811
812
static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
813
89
{
814
89
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
815
816
  // assert(Value <= 1 && "Invalid u1imm argument!");
817
818
89
  printUInt32(O, Value);
819
820
89
  if (MI->csh->detail) {
821
89
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
822
89
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
823
89
    MI->flat_insn->detail->ppc.op_count++;
824
89
  }
825
89
}
826
827
static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
828
128
{
829
128
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
830
  //assert(Value <= 3 && "Invalid u2imm argument!");
831
832
128
  printUInt32(O, Value);
833
834
128
  if (MI->csh->detail) {
835
128
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
836
128
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
837
128
    MI->flat_insn->detail->ppc.op_count++;
838
128
  }
839
128
}
840
841
static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
842
5
{
843
5
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
844
  //assert(Value <= 8 && "Invalid u3imm argument!");
845
846
5
  printUInt32(O, Value);
847
848
5
  if (MI->csh->detail) {
849
5
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
850
5
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
851
5
    MI->flat_insn->detail->ppc.op_count++;
852
5
  }
853
5
}
854
855
static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
856
231
{
857
231
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
858
  //assert(Value <= 15 && "Invalid u4imm argument!");
859
860
231
  printUInt32(O, Value);
861
862
231
  if (MI->csh->detail) {
863
231
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
864
231
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
865
231
    MI->flat_insn->detail->ppc.op_count++;
866
231
  }
867
231
}
868
869
static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
870
8
{
871
8
  int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
872
8
  Value = SignExtend32(Value, 5);
873
874
8
  printInt32(O, Value);
875
876
8
  if (MI->csh->detail) {
877
8
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
878
8
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
879
8
    MI->flat_insn->detail->ppc.op_count++;
880
8
  }
881
8
}
882
883
static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
884
4.62k
{
885
4.62k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
886
887
  //assert(Value <= 31 && "Invalid u5imm argument!");
888
4.62k
  printUInt32(O, Value);
889
890
4.62k
  if (MI->csh->detail) {
891
4.62k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
892
4.62k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
893
4.62k
    MI->flat_insn->detail->ppc.op_count++;
894
4.62k
  }
895
4.62k
}
896
897
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
898
1.19k
{
899
1.19k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
900
901
  //assert(Value <= 63 && "Invalid u6imm argument!");
902
1.19k
  printUInt32(O, Value);
903
904
1.19k
  if (MI->csh->detail) {
905
1.19k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
906
1.19k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
907
1.19k
    MI->flat_insn->detail->ppc.op_count++;
908
1.19k
  }
909
1.19k
}
910
911
static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
912
176
{
913
176
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
914
915
  //assert(Value <= 127 && "Invalid u7imm argument!");
916
176
  printUInt32(O, Value);
917
918
176
  if (MI->csh->detail) {
919
176
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
920
176
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
921
176
    MI->flat_insn->detail->ppc.op_count++;
922
176
  }
923
176
}
924
925
// Operands of BUILD_VECTOR are signed and we use this to print operands
926
// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
927
// print as unsigned.
928
static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
929
0
{
930
0
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
931
932
0
  printUInt32(O, Value);
933
934
0
  if (MI->csh->detail) {
935
0
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
936
0
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
937
0
    MI->flat_insn->detail->ppc.op_count++;
938
0
  }
939
0
}
940
941
static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
942
13
{
943
13
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
944
945
  //assert(Value <= 1023 && "Invalid u10imm argument!");
946
13
  printUInt32(O, Value);
947
948
13
  if (MI->csh->detail) {
949
13
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
950
13
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
951
13
    MI->flat_insn->detail->ppc.op_count++;
952
13
  }
953
13
}
954
955
static void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
956
0
{
957
0
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
958
0
    int Imm = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
959
0
    Imm = SignExtend32(Imm, 12);
960
961
0
    printInt32(O, Imm);
962
963
0
    if (MI->csh->detail) {
964
0
      if (MI->csh->doing_mem) {
965
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
966
0
      } else {
967
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
968
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
969
0
                MI->flat_insn->detail->ppc.op_count++;
970
0
            }
971
0
    }
972
0
  } else
973
0
    printOperand(MI, OpNo, O);
974
0
}
975
976
static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
977
68
{
978
68
  unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
979
980
  // assert(Value <= 4095 && "Invalid u12imm argument!");
981
982
68
  printUInt32(O, Value);
983
984
68
  if (MI->csh->detail) {
985
68
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
986
68
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
987
68
    MI->flat_insn->detail->ppc.op_count++;
988
68
  }
989
68
}
990
991
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
992
11.0k
{
993
11.0k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
994
11.0k
    short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
995
11.0k
    printInt32(O, Imm);
996
997
11.0k
    if (MI->csh->detail) {
998
11.0k
      if (MI->csh->doing_mem) {
999
5.98k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
1000
5.98k
      } else {
1001
5.09k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1002
5.09k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1003
5.09k
                MI->flat_insn->detail->ppc.op_count++;
1004
5.09k
            }
1005
11.0k
    }
1006
11.0k
  } else
1007
0
    printOperand(MI, OpNo, O);
1008
11.0k
}
1009
1010
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
1011
2.83k
{
1012
2.83k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1013
2.83k
    unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
1014
2.83k
    printUInt32(O, Imm);
1015
1016
2.83k
    if (MI->csh->detail) {
1017
2.83k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1018
2.83k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1019
2.83k
      MI->flat_insn->detail->ppc.op_count++;
1020
2.83k
    }
1021
2.83k
  } else
1022
0
    printOperand(MI, OpNo, O);
1023
2.83k
}
1024
1025
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1026
3.48k
{
1027
3.48k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1028
0
    printOperand(MI, OpNo, O);
1029
1030
0
    return;
1031
0
  }
1032
1033
  // Branches can take an immediate operand.  This is used by the branch
1034
  // selection pass to print .+8, an eight byte displacement from the PC.
1035
  // O << ".+";
1036
3.48k
  printAbsBranchOperand(MI, OpNo, O);
1037
3.48k
}
1038
1039
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1040
3.87k
{
1041
3.87k
  int64_t imm;
1042
1043
3.87k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1044
0
    printOperand(MI, OpNo, O);
1045
1046
0
    return;
1047
0
  }
1048
1049
3.87k
  imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32);
1050
  //imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
1051
1052
3.87k
  if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
1053
2.28k
    imm += MI->address;
1054
2.28k
  }
1055
1056
3.87k
  printUInt64(O, imm);
1057
1058
3.87k
  if (MI->csh->detail) {
1059
3.87k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1060
3.87k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1061
3.87k
    MI->flat_insn->detail->ppc.op_count++;
1062
3.87k
  }
1063
3.87k
}
1064
1065
static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
1066
68
{
1067
68
  unsigned RegNo;
1068
68
  unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
1069
1070
68
  switch (CCReg) {
1071
0
    default: // llvm_unreachable("Unknown CR register");
1072
51
    case PPC_CR0: RegNo = 0; break;
1073
5
    case PPC_CR1: RegNo = 1; break;
1074
1
    case PPC_CR2: RegNo = 2; break;
1075
8
    case PPC_CR3: RegNo = 3; break;
1076
2
    case PPC_CR4: RegNo = 4; break;
1077
1
    case PPC_CR5: RegNo = 5; break;
1078
0
    case PPC_CR6: RegNo = 6; break;
1079
0
    case PPC_CR7: RegNo = 7; break;
1080
68
  }
1081
1082
68
  printUInt32(O, 0x80 >> RegNo);
1083
68
}
1084
1085
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1086
5.98k
{
1087
5.98k
  set_mem_access(MI, true);
1088
1089
5.98k
  printS16ImmOperand(MI, OpNo, O);
1090
1091
5.98k
  SStream_concat0(O, "(");
1092
1093
5.98k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
1094
0
    SStream_concat0(O, "0");
1095
5.98k
  else
1096
5.98k
    printOperand(MI, OpNo + 1, O);
1097
1098
5.98k
  SStream_concat0(O, ")");
1099
1100
5.98k
  set_mem_access(MI, false);
1101
5.98k
}
1102
1103
static void printPSMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1104
0
{
1105
0
  set_mem_access(MI, true);
1106
1107
0
  printS12ImmOperand(MI, OpNo, O);
1108
1109
0
  SStream_concat0(O, "(");
1110
0
  printOperand(MI, OpNo + 1, O);
1111
0
  SStream_concat0(O, ")");
1112
1113
0
  set_mem_access(MI, false);
1114
0
}
1115
1116
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
1117
927
{
1118
  // When used as the base register, r0 reads constant zero rather than
1119
  // the value contained in the register.  For this reason, the darwin
1120
  // assembler requires that we print r0 as 0 (no r) when used as the base.
1121
927
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
1122
0
    SStream_concat0(O, "0");
1123
927
  else
1124
927
    printOperand(MI, OpNo, O);
1125
927
  SStream_concat0(O, ", ");
1126
1127
927
  printOperand(MI, OpNo + 1, O);
1128
927
}
1129
1130
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
1131
0
{
1132
0
  set_mem_access(MI, true);
1133
  //printBranchOperand(MI, OpNo, O);
1134
1135
  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
1136
  // come at the _end_ of the expression.
1137
1138
0
  SStream_concat0(O, "(");
1139
0
  printOperand(MI, OpNo + 1, O);
1140
0
  SStream_concat0(O, ")");
1141
1142
0
  set_mem_access(MI, false);
1143
0
}
1144
1145
/// stripRegisterPrefix - This method strips the character prefix from a
1146
/// register name so that only the number is left.  Used by for linux asm.
1147
static char *stripRegisterPrefix(const char *RegName)
1148
0
{
1149
0
  switch (RegName[0]) {
1150
0
    case 'r':
1151
0
    case 'f':
1152
0
    case 'q': // for QPX
1153
0
    case 'v':
1154
0
      if (RegName[1] == 's')
1155
0
        return cs_strdup(RegName + 2);
1156
1157
0
      return cs_strdup(RegName + 1);
1158
0
    case 'c':
1159
0
      if (RegName[1] == 'r') {
1160
        // skip the first 2 letters "cr"
1161
0
        char *name = cs_strdup(RegName + 2);
1162
1163
        // also strip the last 2 letters
1164
0
        if(strlen(name) > 2)
1165
0
          name[strlen(name) - 2] = '\0';
1166
1167
0
        return name;
1168
0
      }
1169
0
  }
1170
1171
0
  return cs_strdup(RegName);
1172
0
}
1173
1174
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
1175
53.8k
{
1176
53.8k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1177
53.8k
  if (MCOperand_isReg(Op)) {
1178
52.6k
    unsigned reg = MCOperand_getReg(Op);
1179
52.6k
#ifndef CAPSTONE_DIET
1180
52.6k
    const char *RegName = getRegisterName(reg);
1181
1182
    // printf("reg = %u (%s)\n", reg, RegName);
1183
1184
    // convert internal register ID to public register ID
1185
52.6k
    reg = PPC_name_reg(RegName);
1186
1187
    // The linux and AIX assembler does not take register prefixes.
1188
52.6k
    if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) {
1189
0
      char *name = stripRegisterPrefix(RegName);
1190
0
      SStream_concat0(O, name);
1191
0
      cs_mem_free(name);
1192
0
    } else
1193
52.6k
      SStream_concat0(O, RegName);
1194
52.6k
#endif
1195
1196
52.6k
    if (MI->csh->detail) {
1197
52.6k
      if (MI->csh->doing_mem) {
1198
5.98k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
1199
46.6k
      } else {
1200
46.6k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
1201
46.6k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
1202
46.6k
        MI->flat_insn->detail->ppc.op_count++;
1203
46.6k
      }
1204
52.6k
    }
1205
1206
52.6k
    return;
1207
52.6k
  }
1208
1209
1.21k
  if (MCOperand_isImm(Op)) {
1210
1.21k
    int32_t imm = (int32_t)MCOperand_getImm(Op);
1211
1.21k
    printInt32(O, imm);
1212
1213
1.21k
    if (MI->csh->detail) {
1214
1.21k
      if (MI->csh->doing_mem) {
1215
0
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm;
1216
1.21k
      } else {
1217
1.21k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1218
1.21k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1219
1.21k
        MI->flat_insn->detail->ppc.op_count++;
1220
1.21k
      }
1221
1.21k
    }
1222
1.21k
  }
1223
1.21k
}
1224
1225
static void op_addImm(MCInst *MI, int v)
1226
19
{
1227
19
  if (MI->csh->detail) {
1228
19
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1229
19
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v;
1230
19
    MI->flat_insn->detail->ppc.op_count++;
1231
19
  }
1232
19
}
1233
1234
#define PRINT_ALIAS_INSTR
1235
#include "PPCGenRegisterName.inc"
1236
#include "PPCGenAsmWriter.inc"
1237
1238
#endif