Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
60.5k
{
20
60.5k
  static const uint32_t OpInfo[] = {
21
60.5k
    0U, // PHI
22
60.5k
    0U, // INLINEASM
23
60.5k
    0U, // CFI_INSTRUCTION
24
60.5k
    0U, // EH_LABEL
25
60.5k
    0U, // GC_LABEL
26
60.5k
    0U, // KILL
27
60.5k
    0U, // EXTRACT_SUBREG
28
60.5k
    0U, // INSERT_SUBREG
29
60.5k
    0U, // IMPLICIT_DEF
30
60.5k
    0U, // SUBREG_TO_REG
31
60.5k
    0U, // COPY_TO_REGCLASS
32
60.5k
    2452U,  // DBG_VALUE
33
60.5k
    0U, // REG_SEQUENCE
34
60.5k
    0U, // COPY
35
60.5k
    2445U,  // BUNDLE
36
60.5k
    2462U,  // LIFETIME_START
37
60.5k
    2432U,  // LIFETIME_END
38
60.5k
    0U, // STACKMAP
39
60.5k
    0U, // PATCHPOINT
40
60.5k
    0U, // LOAD_STACK_GUARD
41
60.5k
    0U, // STATEPOINT
42
60.5k
    0U, // FRAME_ALLOC
43
60.5k
    4688U,  // ADDCCri
44
60.5k
    4688U,  // ADDCCrr
45
60.5k
    5925U,  // ADDCri
46
60.5k
    5925U,  // ADDCrr
47
60.5k
    4772U,  // ADDEri
48
60.5k
    4772U,  // ADDErr
49
60.5k
    4786U,  // ADDXC
50
60.5k
    4678U,  // ADDXCCC
51
60.5k
    4808U,  // ADDXri
52
60.5k
    4808U,  // ADDXrr
53
60.5k
    4808U,  // ADDri
54
60.5k
    4808U,  // ADDrr
55
60.5k
    74166U, // ADJCALLSTACKDOWN
56
60.5k
    74185U, // ADJCALLSTACKUP
57
60.5k
    5497U,  // ALIGNADDR
58
60.5k
    5127U,  // ALIGNADDRL
59
60.5k
    4695U,  // ANDCCri
60
60.5k
    4695U,  // ANDCCrr
61
60.5k
    4718U,  // ANDNCCri
62
60.5k
    4718U,  // ANDNCCrr
63
60.5k
    5182U,  // ANDNri
64
60.5k
    5182U,  // ANDNrr
65
60.5k
    5182U,  // ANDXNrr
66
60.5k
    4876U,  // ANDXri
67
60.5k
    4876U,  // ANDXrr
68
60.5k
    4876U,  // ANDri
69
60.5k
    4876U,  // ANDrr
70
60.5k
    4502U,  // ARRAY16
71
60.5k
    4255U,  // ARRAY32
72
60.5k
    4526U,  // ARRAY8
73
60.5k
    0U, // ATOMIC_LOAD_ADD_32
74
60.5k
    0U, // ATOMIC_LOAD_ADD_64
75
60.5k
    0U, // ATOMIC_LOAD_AND_32
76
60.5k
    0U, // ATOMIC_LOAD_AND_64
77
60.5k
    0U, // ATOMIC_LOAD_MAX_32
78
60.5k
    0U, // ATOMIC_LOAD_MAX_64
79
60.5k
    0U, // ATOMIC_LOAD_MIN_32
80
60.5k
    0U, // ATOMIC_LOAD_MIN_64
81
60.5k
    0U, // ATOMIC_LOAD_NAND_32
82
60.5k
    0U, // ATOMIC_LOAD_NAND_64
83
60.5k
    0U, // ATOMIC_LOAD_OR_32
84
60.5k
    0U, // ATOMIC_LOAD_OR_64
85
60.5k
    0U, // ATOMIC_LOAD_SUB_32
86
60.5k
    0U, // ATOMIC_LOAD_SUB_64
87
60.5k
    0U, // ATOMIC_LOAD_UMAX_32
88
60.5k
    0U, // ATOMIC_LOAD_UMAX_64
89
60.5k
    0U, // ATOMIC_LOAD_UMIN_32
90
60.5k
    0U, // ATOMIC_LOAD_UMIN_64
91
60.5k
    0U, // ATOMIC_LOAD_XOR_32
92
60.5k
    0U, // ATOMIC_LOAD_XOR_64
93
60.5k
    0U, // ATOMIC_SWAP_64
94
60.5k
    74271U, // BA
95
60.5k
    1194492U, // BCOND
96
60.5k
    1260028U, // BCONDA
97
60.5k
    17659U, // BINDri
98
60.5k
    17659U, // BINDrr
99
60.5k
    5065U,  // BMASK
100
60.5k
    145915U,  // BPFCC
101
60.5k
    211451U,  // BPFCCA
102
60.5k
    276987U,  // BPFCCANT
103
60.5k
    342523U,  // BPFCCNT
104
60.5k
    2106465U, // BPGEZapn
105
60.5k
    2105838U, // BPGEZapt
106
60.5k
    2106532U, // BPGEZnapn
107
60.5k
    2107288U, // BPGEZnapt
108
60.5k
    2106489U, // BPGZapn
109
60.5k
    2105856U, // BPGZapt
110
60.5k
    2106552U, // BPGZnapn
111
60.5k
    2107384U, // BPGZnapt
112
60.5k
    1456636U, // BPICC
113
60.5k
    473596U,  // BPICCA
114
60.5k
    539132U,  // BPICCANT
115
60.5k
    604668U,  // BPICCNT
116
60.5k
    2106477U, // BPLEZapn
117
60.5k
    2105847U, // BPLEZapt
118
60.5k
    2106542U, // BPLEZnapn
119
60.5k
    2107337U, // BPLEZnapt
120
60.5k
    2106500U, // BPLZapn
121
60.5k
    2105864U, // BPLZapt
122
60.5k
    2106561U, // BPLZnapn
123
60.5k
    2107428U, // BPLZnapt
124
60.5k
    2106511U, // BPNZapn
125
60.5k
    2105872U, // BPNZapt
126
60.5k
    2106570U, // BPNZnapn
127
60.5k
    2107472U, // BPNZnapt
128
60.5k
    1718780U, // BPXCC
129
60.5k
    735740U,  // BPXCCA
130
60.5k
    801276U,  // BPXCCANT
131
60.5k
    866812U,  // BPXCCNT
132
60.5k
    2106522U, // BPZapn
133
60.5k
    2105880U, // BPZapt
134
60.5k
    2106579U, // BPZnapn
135
60.5k
    2107505U, // BPZnapt
136
60.5k
    4983U,  // BSHUFFLE
137
60.5k
    74742U, // CALL
138
60.5k
    17398U, // CALLri
139
60.5k
    17398U, // CALLrr
140
60.5k
    924148U,  // CASXrr
141
60.5k
    924129U,  // CASrr
142
60.5k
    74001U, // CMASK16
143
60.5k
    73833U, // CMASK32
144
60.5k
    74150U, // CMASK8
145
60.5k
    2106607U, // CMPri
146
60.5k
    2106607U, // CMPrr
147
60.5k
    4332U,  // EDGE16
148
60.5k
    5081U,  // EDGE16L
149
60.5k
    5198U,  // EDGE16LN
150
60.5k
    5165U,  // EDGE16N
151
60.5k
    4164U,  // EDGE32
152
60.5k
    5072U,  // EDGE32L
153
60.5k
    5188U,  // EDGE32LN
154
60.5k
    5156U,  // EDGE32N
155
60.5k
    4511U,  // EDGE8
156
60.5k
    5090U,  // EDGE8L
157
60.5k
    5208U,  // EDGE8LN
158
60.5k
    5174U,  // EDGE8N
159
60.5k
    1053516U, // FABSD
160
60.5k
    1054031U, // FABSQ
161
60.5k
    1054376U, // FABSS
162
60.5k
    4813U,  // FADDD
163
60.5k
    5383U,  // FADDQ
164
60.5k
    5645U,  // FADDS
165
60.5k
    4648U,  // FALIGNADATA
166
60.5k
    4875U,  // FAND
167
60.5k
    4112U,  // FANDNOT1
168
60.5k
    5544U,  // FANDNOT1S
169
60.5k
    4271U,  // FANDNOT2
170
60.5k
    5591U,  // FANDNOT2S
171
60.5k
    5677U,  // FANDS
172
60.5k
    1194491U, // FBCOND
173
60.5k
    1260027U, // FBCONDA
174
60.5k
    4394U,  // FCHKSM16
175
60.5k
    2106173U, // FCMPD
176
60.5k
    4413U,  // FCMPEQ16
177
60.5k
    4226U,  // FCMPEQ32
178
60.5k
    4432U,  // FCMPGT16
179
60.5k
    4245U,  // FCMPGT32
180
60.5k
    4340U,  // FCMPLE16
181
60.5k
    4172U,  // FCMPLE32
182
60.5k
    4350U,  // FCMPNE16
183
60.5k
    4182U,  // FCMPNE32
184
60.5k
    2106696U, // FCMPQ
185
60.5k
    2107005U, // FCMPS
186
60.5k
    4960U,  // FDIVD
187
60.5k
    5475U,  // FDIVQ
188
60.5k
    5815U,  // FDIVS
189
60.5k
    5405U,  // FDMULQ
190
60.5k
    1053620U, // FDTOI
191
60.5k
    1053996U, // FDTOQ
192
60.5k
    1054305U, // FDTOS
193
60.5k
    1054536U, // FDTOX
194
60.5k
    1053464U, // FEXPAND
195
60.5k
    4820U,  // FHADDD
196
60.5k
    5652U,  // FHADDS
197
60.5k
    4800U,  // FHSUBD
198
60.5k
    5637U,  // FHSUBS
199
60.5k
    1053473U, // FITOD
200
60.5k
    1054003U, // FITOQ
201
60.5k
    1054312U, // FITOS
202
60.5k
    6300484U, // FLCMPD
203
60.5k
    6301316U, // FLCMPS
204
60.5k
    2606U,  // FLUSHW
205
60.5k
    4404U,  // FMEAN16
206
60.5k
    1053543U, // FMOVD
207
60.5k
    1006078U, // FMOVD_FCC
208
60.5k
    23484926U,  // FMOVD_ICC
209
60.5k
    23747070U,  // FMOVD_XCC
210
60.5k
    1054058U, // FMOVQ
211
60.5k
    1006102U, // FMOVQ_FCC
212
60.5k
    23484950U,  // FMOVQ_ICC
213
60.5k
    23747094U,  // FMOVQ_XCC
214
60.5k
    6018U,  // FMOVRGEZD
215
60.5k
    6029U,  // FMOVRGEZQ
216
60.5k
    6056U,  // FMOVRGEZS
217
60.5k
    6116U,  // FMOVRGZD
218
60.5k
    6126U,  // FMOVRGZQ
219
60.5k
    6150U,  // FMOVRGZS
220
60.5k
    6067U,  // FMOVRLEZD
221
60.5k
    6078U,  // FMOVRLEZQ
222
60.5k
    6105U,  // FMOVRLEZS
223
60.5k
    6160U,  // FMOVRLZD
224
60.5k
    6170U,  // FMOVRLZQ
225
60.5k
    6194U,  // FMOVRLZS
226
60.5k
    6204U,  // FMOVRNZD
227
60.5k
    6214U,  // FMOVRNZQ
228
60.5k
    6238U,  // FMOVRNZS
229
60.5k
    6009U,  // FMOVRZD
230
60.5k
    6248U,  // FMOVRZQ
231
60.5k
    6269U,  // FMOVRZS
232
60.5k
    1054398U, // FMOVS
233
60.5k
    1006114U, // FMOVS_FCC
234
60.5k
    23484962U,  // FMOVS_ICC
235
60.5k
    23747106U,  // FMOVS_XCC
236
60.5k
    4490U,  // FMUL8SUX16
237
60.5k
    4465U,  // FMUL8ULX16
238
60.5k
    4442U,  // FMUL8X16
239
60.5k
    5098U,  // FMUL8X16AL
240
60.5k
    5849U,  // FMUL8X16AU
241
60.5k
    4860U,  // FMULD
242
60.5k
    4477U,  // FMULD8SUX16
243
60.5k
    4452U,  // FMULD8ULX16
244
60.5k
    5413U,  // FMULQ
245
60.5k
    5714U,  // FMULS
246
60.5k
    4837U,  // FNADDD
247
60.5k
    5669U,  // FNADDS
248
60.5k
    4881U,  // FNAND
249
60.5k
    5684U,  // FNANDS
250
60.5k
    1053429U, // FNEGD
251
60.5k
    1053974U, // FNEGQ
252
60.5k
    1054283U, // FNEGS
253
60.5k
    4828U,  // FNHADDD
254
60.5k
    5660U,  // FNHADDS
255
60.5k
    4828U,  // FNMULD
256
60.5k
    5660U,  // FNMULS
257
60.5k
    5513U,  // FNOR
258
60.5k
    5778U,  // FNORS
259
60.5k
    1052698U, // FNOT1
260
60.5k
    1054131U, // FNOT1S
261
60.5k
    1052857U, // FNOT2
262
60.5k
    1054178U, // FNOT2S
263
60.5k
    5660U,  // FNSMULD
264
60.5k
    74625U, // FONE
265
60.5k
    75324U, // FONES
266
60.5k
    5508U,  // FOR
267
60.5k
    4129U,  // FORNOT1
268
60.5k
    5563U,  // FORNOT1S
269
60.5k
    4288U,  // FORNOT2
270
60.5k
    5610U,  // FORNOT2S
271
60.5k
    5772U,  // FORS
272
60.5k
    1052936U, // FPACK16
273
60.5k
    4192U,  // FPACK32
274
60.5k
    1054507U, // FPACKFIX
275
60.5k
    4323U,  // FPADD16
276
60.5k
    5620U,  // FPADD16S
277
60.5k
    4155U,  // FPADD32
278
60.5k
    5573U,  // FPADD32S
279
60.5k
    4297U,  // FPADD64
280
60.5k
    4974U,  // FPMERGE
281
60.5k
    4314U,  // FPSUB16
282
60.5k
    4580U,  // FPSUB16S
283
60.5k
    4146U,  // FPSUB32
284
60.5k
    4570U,  // FPSUB32S
285
60.5k
    1053480U, // FQTOD
286
60.5k
    1053627U, // FQTOI
287
60.5k
    1054319U, // FQTOS
288
60.5k
    1054552U, // FQTOX
289
60.5k
    4423U,  // FSLAS16
290
60.5k
    4236U,  // FSLAS32
291
60.5k
    4378U,  // FSLL16
292
60.5k
    4210U,  // FSLL32
293
60.5k
    4867U,  // FSMULD
294
60.5k
    1053523U, // FSQRTD
295
60.5k
    1054038U, // FSQRTQ
296
60.5k
    1054383U, // FSQRTS
297
60.5k
    4306U,  // FSRA16
298
60.5k
    4138U,  // FSRA32
299
60.5k
    1052681U, // FSRC1
300
60.5k
    1054112U, // FSRC1S
301
60.5k
    1052840U, // FSRC2
302
60.5k
    1054159U, // FSRC2S
303
60.5k
    4386U,  // FSRL16
304
60.5k
    4218U,  // FSRL32
305
60.5k
    1053487U, // FSTOD
306
60.5k
    1053634U, // FSTOI
307
60.5k
    1054010U, // FSTOQ
308
60.5k
    1054559U, // FSTOX
309
60.5k
    4793U,  // FSUBD
310
60.5k
    5376U,  // FSUBQ
311
60.5k
    5630U,  // FSUBS
312
60.5k
    5519U,  // FXNOR
313
60.5k
    5785U,  // FXNORS
314
60.5k
    5526U,  // FXOR
315
60.5k
    5793U,  // FXORS
316
60.5k
    1053494U, // FXTOD
317
60.5k
    1054017U, // FXTOQ
318
60.5k
    1054326U, // FXTOS
319
60.5k
    74984U, // FZERO
320
60.5k
    75353U, // FZEROS
321
60.5k
    24584U, // GETPCX
322
60.5k
    1078273U, // JMPLri
323
60.5k
    1078273U, // JMPLrr
324
60.5k
    1997243U, // LDDFri
325
60.5k
    1997243U, // LDDFrr
326
60.5k
    1997249U, // LDFri
327
60.5k
    1997249U, // LDFrr
328
60.5k
    1997275U, // LDQFri
329
60.5k
    1997275U, // LDQFrr
330
60.5k
    1997229U, // LDSBri
331
60.5k
    1997229U, // LDSBrr
332
60.5k
    1997254U, // LDSHri
333
60.5k
    1997254U, // LDSHrr
334
60.5k
    1997287U, // LDSWri
335
60.5k
    1997287U, // LDSWrr
336
60.5k
    1997236U, // LDUBri
337
60.5k
    1997236U, // LDUBrr
338
60.5k
    1997261U, // LDUHri
339
60.5k
    1997261U, // LDUHrr
340
60.5k
    1997294U, // LDXri
341
60.5k
    1997294U, // LDXrr
342
60.5k
    1997249U, // LDri
343
60.5k
    1997249U, // LDrr
344
60.5k
    33480U, // LEAX_ADDri
345
60.5k
    33480U, // LEA_ADDri
346
60.5k
    1054405U, // LZCNT
347
60.5k
    75121U, // MEMBARi
348
60.5k
    1054543U, // MOVDTOX
349
60.5k
    1006122U, // MOVFCCri
350
60.5k
    1006122U, // MOVFCCrr
351
60.5k
    23484970U,  // MOVICCri
352
60.5k
    23484970U,  // MOVICCrr
353
60.5k
    6047U,  // MOVRGEZri
354
60.5k
    6047U,  // MOVRGEZrr
355
60.5k
    6142U,  // MOVRGZri
356
60.5k
    6142U,  // MOVRGZrr
357
60.5k
    6096U,  // MOVRLEZri
358
60.5k
    6096U,  // MOVRLEZrr
359
60.5k
    6186U,  // MOVRLZri
360
60.5k
    6186U,  // MOVRLZrr
361
60.5k
    6230U,  // MOVRNZri
362
60.5k
    6230U,  // MOVRNZrr
363
60.5k
    6262U,  // MOVRRZri
364
60.5k
    6262U,  // MOVRRZrr
365
60.5k
    1054469U, // MOVSTOSW
366
60.5k
    1054479U, // MOVSTOUW
367
60.5k
    1054543U, // MOVWTOS
368
60.5k
    23747114U,  // MOVXCCri
369
60.5k
    23747114U,  // MOVXCCrr
370
60.5k
    1054543U, // MOVXTOD
371
60.5k
    5954U,  // MULXri
372
60.5k
    5954U,  // MULXrr
373
60.5k
    2578U,  // NOP
374
60.5k
    4735U,  // ORCCri
375
60.5k
    4735U,  // ORCCrr
376
60.5k
    4726U,  // ORNCCri
377
60.5k
    4726U,  // ORNCCrr
378
60.5k
    5339U,  // ORNri
379
60.5k
    5339U,  // ORNrr
380
60.5k
    5339U,  // ORXNrr
381
60.5k
    5509U,  // ORXri
382
60.5k
    5509U,  // ORXrr
383
60.5k
    5509U,  // ORri
384
60.5k
    5509U,  // ORrr
385
60.5k
    5836U,  // PDIST
386
60.5k
    5344U,  // PDISTN
387
60.5k
    1053356U, // POPCrr
388
60.5k
    73729U, // RDY
389
60.5k
    4999U,  // RESTOREri
390
60.5k
    4999U,  // RESTORErr
391
60.5k
    76132U, // RET
392
60.5k
    76141U, // RETL
393
60.5k
    18131U, // RETTri
394
60.5k
    18131U, // RETTrr
395
60.5k
    5008U,  // SAVEri
396
60.5k
    5008U,  // SAVErr
397
60.5k
    4748U,  // SDIVCCri
398
60.5k
    4748U,  // SDIVCCrr
399
60.5k
    5995U,  // SDIVXri
400
60.5k
    5995U,  // SDIVXrr
401
60.5k
    5861U,  // SDIVri
402
60.5k
    5861U,  // SDIVrr
403
60.5k
    2182U,  // SELECT_CC_DFP_FCC
404
60.5k
    2293U,  // SELECT_CC_DFP_ICC
405
60.5k
    2238U,  // SELECT_CC_FP_FCC
406
60.5k
    2349U,  // SELECT_CC_FP_ICC
407
60.5k
    2265U,  // SELECT_CC_Int_FCC
408
60.5k
    2376U,  // SELECT_CC_Int_ICC
409
60.5k
    2210U,  // SELECT_CC_QFP_FCC
410
60.5k
    2321U,  // SELECT_CC_QFP_ICC
411
60.5k
    1053595U, // SETHIXi
412
60.5k
    1053595U, // SETHIi
413
60.5k
    2569U,  // SHUTDOWN
414
60.5k
    2564U,  // SIAM
415
60.5k
    5941U,  // SLLXri
416
60.5k
    5941U,  // SLLXrr
417
60.5k
    5116U,  // SLLri
418
60.5k
    5116U,  // SLLrr
419
60.5k
    4702U,  // SMULCCri
420
60.5k
    4702U,  // SMULCCrr
421
60.5k
    5144U,  // SMULri
422
60.5k
    5144U,  // SMULrr
423
60.5k
    5913U,  // SRAXri
424
60.5k
    5913U,  // SRAXrr
425
60.5k
    4643U,  // SRAri
426
60.5k
    4643U,  // SRArr
427
60.5k
    5947U,  // SRLXri
428
60.5k
    5947U,  // SRLXrr
429
60.5k
    5139U,  // SRLri
430
60.5k
    5139U,  // SRLrr
431
60.5k
    2588U,  // STBAR
432
60.5k
    37428U, // STBri
433
60.5k
    37428U, // STBrr
434
60.5k
    37723U, // STDFri
435
60.5k
    37723U, // STDFrr
436
60.5k
    38607U, // STFri
437
60.5k
    38607U, // STFrr
438
60.5k
    37782U, // STHri
439
60.5k
    37782U, // STHrr
440
60.5k
    38238U, // STQFri
441
60.5k
    38238U, // STQFrr
442
60.5k
    38758U, // STXri
443
60.5k
    38758U, // STXrr
444
60.5k
    38607U, // STri
445
60.5k
    38607U, // STrr
446
60.5k
    4671U,  // SUBCCri
447
60.5k
    4671U,  // SUBCCrr
448
60.5k
    5919U,  // SUBCri
449
60.5k
    5919U,  // SUBCrr
450
60.5k
    4764U,  // SUBEri
451
60.5k
    4764U,  // SUBErr
452
60.5k
    4665U,  // SUBXri
453
60.5k
    4665U,  // SUBXrr
454
60.5k
    4665U,  // SUBri
455
60.5k
    4665U,  // SUBrr
456
60.5k
    1997268U, // SWAPri
457
60.5k
    1997268U, // SWAPrr
458
60.5k
    2422U,  // TA3
459
60.5k
    2427U,  // TA5
460
60.5k
    5883U,  // TADDCCTVri
461
60.5k
    5883U,  // TADDCCTVrr
462
60.5k
    4687U,  // TADDCCri
463
60.5k
    4687U,  // TADDCCrr
464
60.5k
    9873960U, // TICCri
465
60.5k
    9873960U, // TICCrr
466
60.5k
    37753544U,  // TLS_ADDXrr
467
60.5k
    37753544U,  // TLS_ADDrr
468
60.5k
    2106358U, // TLS_CALL
469
60.5k
    39746030U,  // TLS_LDXrr
470
60.5k
    39745985U,  // TLS_LDrr
471
60.5k
    5873U,  // TSUBCCTVri
472
60.5k
    5873U,  // TSUBCCTVrr
473
60.5k
    4670U,  // TSUBCCri
474
60.5k
    4670U,  // TSUBCCrr
475
60.5k
    10136104U,  // TXCCri
476
60.5k
    10136104U,  // TXCCrr
477
60.5k
    4756U,  // UDIVCCri
478
60.5k
    4756U,  // UDIVCCrr
479
60.5k
    6002U,  // UDIVXri
480
60.5k
    6002U,  // UDIVXrr
481
60.5k
    5867U,  // UDIVri
482
60.5k
    5867U,  // UDIVrr
483
60.5k
    4710U,  // UMULCCri
484
60.5k
    4710U,  // UMULCCrr
485
60.5k
    5026U,  // UMULXHI
486
60.5k
    5150U,  // UMULri
487
60.5k
    5150U,  // UMULrr
488
60.5k
    74996U, // UNIMP
489
60.5k
    6300477U, // V9FCMPD
490
60.5k
    6300397U, // V9FCMPED
491
60.5k
    6300942U, // V9FCMPEQ
492
60.5k
    6301251U, // V9FCMPES
493
60.5k
    6301000U, // V9FCMPQ
494
60.5k
    6301309U, // V9FCMPS
495
60.5k
    47614U, // V9FMOVD_FCC
496
60.5k
    47638U, // V9FMOVQ_FCC
497
60.5k
    47650U, // V9FMOVS_FCC
498
60.5k
    47658U, // V9MOVFCCri
499
60.5k
    47658U, // V9MOVFCCrr
500
60.5k
    14689692U,  // WRYri
501
60.5k
    14689692U,  // WRYrr
502
60.5k
    5953U,  // XMULX
503
60.5k
    5035U,  // XMULXHI
504
60.5k
    4733U,  // XNORCCri
505
60.5k
    4733U,  // XNORCCrr
506
60.5k
    5520U,  // XNORXrr
507
60.5k
    5520U,  // XNORri
508
60.5k
    5520U,  // XNORrr
509
60.5k
    4741U,  // XORCCri
510
60.5k
    4741U,  // XORCCrr
511
60.5k
    5527U,  // XORXri
512
60.5k
    5527U,  // XORXrr
513
60.5k
    5527U,  // XORri
514
60.5k
    5527U,  // XORrr
515
60.5k
    0U
516
60.5k
  };
517
518
60.5k
#ifndef CAPSTONE_DIET
519
60.5k
  static const char AsmStrs[] = {
520
60.5k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
60.5k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
60.5k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
60.5k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
60.5k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
60.5k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
60.5k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
60.5k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
60.5k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
60.5k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
60.5k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
60.5k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
60.5k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
60.5k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
60.5k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
60.5k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
60.5k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
60.5k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
60.5k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
60.5k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
60.5k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
60.5k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
60.5k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
60.5k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
60.5k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
60.5k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
60.5k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
60.5k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
60.5k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
60.5k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
60.5k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
60.5k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
60.5k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
60.5k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
60.5k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
60.5k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
60.5k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
60.5k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
60.5k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
60.5k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
60.5k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
60.5k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
60.5k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
60.5k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
60.5k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
60.5k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
60.5k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
60.5k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
60.5k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
60.5k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
60.5k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
60.5k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
60.5k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
60.5k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
60.5k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
60.5k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
60.5k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
60.5k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
60.5k
  /* 542 */ 'b', 'a', 32, 0,
579
60.5k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
60.5k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
60.5k
  /* 563 */ 's', 't', 'b', 32, 0,
582
60.5k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
60.5k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
60.5k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
60.5k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
60.5k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
60.5k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
60.5k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
60.5k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
60.5k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
60.5k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
60.5k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
60.5k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
60.5k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
60.5k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
60.5k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
60.5k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
60.5k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
60.5k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
60.5k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
60.5k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
60.5k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
60.5k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
60.5k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
60.5k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
60.5k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
60.5k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
60.5k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
60.5k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
60.5k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
60.5k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
60.5k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
60.5k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
60.5k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
60.5k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
60.5k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
60.5k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
60.5k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
60.5k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
60.5k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
60.5k
  /* 858 */ 's', 't', 'd', 32, 0,
622
60.5k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
60.5k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
60.5k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
60.5k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
60.5k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
60.5k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
60.5k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
60.5k
  /* 917 */ 's', 't', 'h', 32, 0,
630
60.5k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
60.5k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
60.5k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
60.5k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
60.5k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
60.5k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
60.5k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
60.5k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
60.5k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
60.5k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
60.5k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
60.5k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
60.5k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
60.5k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
60.5k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
60.5k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
60.5k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
60.5k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
60.5k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
60.5k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
60.5k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
60.5k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
60.5k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
60.5k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
60.5k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
60.5k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
60.5k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
60.5k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
60.5k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
60.5k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
60.5k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
60.5k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
60.5k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
60.5k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
60.5k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
60.5k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
60.5k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
60.5k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
60.5k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
60.5k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
60.5k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
60.5k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
60.5k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
60.5k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
60.5k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
60.5k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
60.5k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
60.5k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
60.5k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
60.5k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
60.5k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
60.5k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
60.5k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
60.5k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
60.5k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
60.5k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
60.5k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
60.5k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
60.5k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
60.5k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
60.5k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
60.5k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
60.5k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
60.5k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
60.5k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
60.5k
  /* 1435 */ 'w', 'r', 32, 0,
696
60.5k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
60.5k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
60.5k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
60.5k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
60.5k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
60.5k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
60.5k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
60.5k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
60.5k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
60.5k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
60.5k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
60.5k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
60.5k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
60.5k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
60.5k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
60.5k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
60.5k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
60.5k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
60.5k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
60.5k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
60.5k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
60.5k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
60.5k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
60.5k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
60.5k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
60.5k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
60.5k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
60.5k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
60.5k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
60.5k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
60.5k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
60.5k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
60.5k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
60.5k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
60.5k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
60.5k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
60.5k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
60.5k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
60.5k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
60.5k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
60.5k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
60.5k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
60.5k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
60.5k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
60.5k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
60.5k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
60.5k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
60.5k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
60.5k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
60.5k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
60.5k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
60.5k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
60.5k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
60.5k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
60.5k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
60.5k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
60.5k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
60.5k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
60.5k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
60.5k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
60.5k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
60.5k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
60.5k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
60.5k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
60.5k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
60.5k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
60.5k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
60.5k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
60.5k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
60.5k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
60.5k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
60.5k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
60.5k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
60.5k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
60.5k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
60.5k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
60.5k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
60.5k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
60.5k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
60.5k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
60.5k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
60.5k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
60.5k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
60.5k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
60.5k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
60.5k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
60.5k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
60.5k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
60.5k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
60.5k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
60.5k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
60.5k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
60.5k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
60.5k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
60.5k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
60.5k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
60.5k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
60.5k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
60.5k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
60.5k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
60.5k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
60.5k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
60.5k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
60.5k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
60.5k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
60.5k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
60.5k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
60.5k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
60.5k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
60.5k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
60.5k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
60.5k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
60.5k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
60.5k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
60.5k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
60.5k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
60.5k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
60.5k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
60.5k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
60.5k
  /* 2554 */ 'f', 'b', 0,
816
60.5k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
60.5k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
60.5k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
60.5k
  /* 2577 */ 'n', 'o', 'p', 0,
820
60.5k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
60.5k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
60.5k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
60.5k
  /* 2599 */ 't', 0,
824
60.5k
  /* 2601 */ 'm', 'o', 'v', 0,
825
60.5k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
60.5k
  };
827
60.5k
#endif
828
829
  // Emit the opcode for the instruction.
830
60.5k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
60.5k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
60.5k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
60.5k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
60.5k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
246
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
246
    return;
844
0
    break;
845
10.8k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
10.8k
    printOperand(MI, 1, O); 
848
10.8k
    break;
849
36.1k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
36.1k
    printOperand(MI, 0, O); 
852
36.1k
    break;
853
6.44k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
6.44k
    printCCOperand(MI, 1, O); 
856
6.44k
    break;
857
146
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
146
    printMemOperand(MI, 0, O, NULL); 
860
146
    return;
861
0
    break;
862
1.58k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
1.58k
    printCCOperand(MI, 3, O); 
865
1.58k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.85k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.85k
    printMemOperand(MI, 1, O, NULL); 
874
2.85k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
887
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
887
    printOperand(MI, 2, O); 
885
887
    SStream_concat0(O, ", ["); 
886
887
    printMemOperand(MI, 0, O, NULL); 
887
887
    SStream_concat0(O, "]"); 
888
887
    return;
889
0
    break;
890
216
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
216
    printCCOperand(MI, 2, O); 
893
216
    break;
894
1.17k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.17k
    printCCOperand(MI, 4, O); 
897
1.17k
    SStream_concat0(O, " "); 
898
1.17k
    printOperand(MI, 1, O); 
899
1.17k
    SStream_concat0(O, ", "); 
900
1.17k
    printOperand(MI, 2, O); 
901
1.17k
    SStream_concat0(O, ", "); 
902
1.17k
    printOperand(MI, 0, O); 
903
1.17k
    return;
904
0
    break;
905
60.5k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
58.1k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
18.2k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
18.2k
    SStream_concat0(O, ", "); 
915
18.2k
    break;
916
29.0k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
29.0k
    return;
919
0
    break;
920
2.65k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
2.65k
    SStream_concat0(O, " "); 
923
2.65k
    break;
924
2.06k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
2.06k
    SStream_concat0(O, ",a ");
927
2.06k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
2.06k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.24k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.24k
    SStream_concat0(O, " %icc, ");
950
1.24k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.24k
    break;
952
390
  case 7:
953
    // BPICCA
954
390
    SStream_concat0(O, ",a %icc, ");
955
390
  Sparc_add_hint(MI, SPARC_HINT_A);
956
390
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
390
    printOperand(MI, 0, O); 
958
390
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.06k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.06k
    SStream_concat0(O, " %xcc, ");
979
1.06k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.06k
    break;
981
280
  case 11:
982
    // BPXCCA
983
280
    SStream_concat0(O, ",a %xcc, ");
984
280
  Sparc_add_hint(MI, SPARC_HINT_A);
985
280
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
280
    printOperand(MI, 0, O); 
987
280
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.52k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.52k
    SStream_concat0(O, "], "); 
1008
2.52k
    break;
1009
552
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
552
    SStream_concat0(O, " %fcc0, ");
1012
552
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
552
    printOperand(MI, 1, O); 
1014
552
    SStream_concat0(O, ", "); 
1015
552
    printOperand(MI, 0, O); 
1016
552
    return;
1017
0
    break;
1018
58.1k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
27.8k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
7.18k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
7.18k
    printOperand(MI, 2, O); 
1028
7.18k
    SStream_concat0(O, ", "); 
1029
7.18k
    printOperand(MI, 0, O); 
1030
7.18k
    break;
1031
12.5k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
12.5k
    printOperand(MI, 0, O); 
1034
12.5k
    break;
1035
8.12k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
8.12k
    printOperand(MI, 1, O); 
1038
8.12k
    break;
1039
27.8k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
27.8k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
24.2k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
24.2k
    return;
1049
0
    break;
1050
3.09k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
3.09k
    SStream_concat0(O, ", "); 
1053
3.09k
    break;
1054
216
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
216
    SStream_concat0(O, " + ");  // qq
1057
216
    printOperand(MI, 1, O); 
1058
216
    return;
1059
0
    break;
1060
294
  case 3:
1061
    // WRYri, WRYrr
1062
294
    SStream_concat0(O, ", %y");
1063
294
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
294
    return;
1065
0
    break;
1066
27.8k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
3.09k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
2.05k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
2.05k
    printOperand(MI, 2, O); 
1076
2.05k
    return;
1077
0
    break;
1078
1.03k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.03k
    printOperand(MI, 0, O); 
1081
1.03k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
3.09k
  }
1089
3.09k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
74.3k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
74.3k
#ifndef CAPSTONE_DIET
1100
74.3k
  static const char AsmStrs[] = {
1101
74.3k
  /* 0 */ 'f', '1', '0', 0,
1102
74.3k
  /* 4 */ 'f', '2', '0', 0,
1103
74.3k
  /* 8 */ 'f', '3', '0', 0,
1104
74.3k
  /* 12 */ 'f', '4', '0', 0,
1105
74.3k
  /* 16 */ 'f', '5', '0', 0,
1106
74.3k
  /* 20 */ 'f', '6', '0', 0,
1107
74.3k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
74.3k
  /* 29 */ 'f', '0', 0,
1109
74.3k
  /* 32 */ 'g', '0', 0,
1110
74.3k
  /* 35 */ 'i', '0', 0,
1111
74.3k
  /* 38 */ 'l', '0', 0,
1112
74.3k
  /* 41 */ 'o', '0', 0,
1113
74.3k
  /* 44 */ 'f', '1', '1', 0,
1114
74.3k
  /* 48 */ 'f', '2', '1', 0,
1115
74.3k
  /* 52 */ 'f', '3', '1', 0,
1116
74.3k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
74.3k
  /* 61 */ 'f', '1', 0,
1118
74.3k
  /* 64 */ 'g', '1', 0,
1119
74.3k
  /* 67 */ 'i', '1', 0,
1120
74.3k
  /* 70 */ 'l', '1', 0,
1121
74.3k
  /* 73 */ 'o', '1', 0,
1122
74.3k
  /* 76 */ 'f', '1', '2', 0,
1123
74.3k
  /* 80 */ 'f', '2', '2', 0,
1124
74.3k
  /* 84 */ 'f', '3', '2', 0,
1125
74.3k
  /* 88 */ 'f', '4', '2', 0,
1126
74.3k
  /* 92 */ 'f', '5', '2', 0,
1127
74.3k
  /* 96 */ 'f', '6', '2', 0,
1128
74.3k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
74.3k
  /* 105 */ 'f', '2', 0,
1130
74.3k
  /* 108 */ 'g', '2', 0,
1131
74.3k
  /* 111 */ 'i', '2', 0,
1132
74.3k
  /* 114 */ 'l', '2', 0,
1133
74.3k
  /* 117 */ 'o', '2', 0,
1134
74.3k
  /* 120 */ 'f', '1', '3', 0,
1135
74.3k
  /* 124 */ 'f', '2', '3', 0,
1136
74.3k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
74.3k
  /* 133 */ 'f', '3', 0,
1138
74.3k
  /* 136 */ 'g', '3', 0,
1139
74.3k
  /* 139 */ 'i', '3', 0,
1140
74.3k
  /* 142 */ 'l', '3', 0,
1141
74.3k
  /* 145 */ 'o', '3', 0,
1142
74.3k
  /* 148 */ 'f', '1', '4', 0,
1143
74.3k
  /* 152 */ 'f', '2', '4', 0,
1144
74.3k
  /* 156 */ 'f', '3', '4', 0,
1145
74.3k
  /* 160 */ 'f', '4', '4', 0,
1146
74.3k
  /* 164 */ 'f', '5', '4', 0,
1147
74.3k
  /* 168 */ 'f', '4', 0,
1148
74.3k
  /* 171 */ 'g', '4', 0,
1149
74.3k
  /* 174 */ 'i', '4', 0,
1150
74.3k
  /* 177 */ 'l', '4', 0,
1151
74.3k
  /* 180 */ 'o', '4', 0,
1152
74.3k
  /* 183 */ 'f', '1', '5', 0,
1153
74.3k
  /* 187 */ 'f', '2', '5', 0,
1154
74.3k
  /* 191 */ 'f', '5', 0,
1155
74.3k
  /* 194 */ 'g', '5', 0,
1156
74.3k
  /* 197 */ 'i', '5', 0,
1157
74.3k
  /* 200 */ 'l', '5', 0,
1158
74.3k
  /* 203 */ 'o', '5', 0,
1159
74.3k
  /* 206 */ 'f', '1', '6', 0,
1160
74.3k
  /* 210 */ 'f', '2', '6', 0,
1161
74.3k
  /* 214 */ 'f', '3', '6', 0,
1162
74.3k
  /* 218 */ 'f', '4', '6', 0,
1163
74.3k
  /* 222 */ 'f', '5', '6', 0,
1164
74.3k
  /* 226 */ 'f', '6', 0,
1165
74.3k
  /* 229 */ 'g', '6', 0,
1166
74.3k
  /* 232 */ 'l', '6', 0,
1167
74.3k
  /* 235 */ 'f', '1', '7', 0,
1168
74.3k
  /* 239 */ 'f', '2', '7', 0,
1169
74.3k
  /* 243 */ 'f', '7', 0,
1170
74.3k
  /* 246 */ 'g', '7', 0,
1171
74.3k
  /* 249 */ 'i', '7', 0,
1172
74.3k
  /* 252 */ 'l', '7', 0,
1173
74.3k
  /* 255 */ 'o', '7', 0,
1174
74.3k
  /* 258 */ 'f', '1', '8', 0,
1175
74.3k
  /* 262 */ 'f', '2', '8', 0,
1176
74.3k
  /* 266 */ 'f', '3', '8', 0,
1177
74.3k
  /* 270 */ 'f', '4', '8', 0,
1178
74.3k
  /* 274 */ 'f', '5', '8', 0,
1179
74.3k
  /* 278 */ 'f', '8', 0,
1180
74.3k
  /* 281 */ 'f', '1', '9', 0,
1181
74.3k
  /* 285 */ 'f', '2', '9', 0,
1182
74.3k
  /* 289 */ 'f', '9', 0,
1183
74.3k
  /* 292 */ 'i', 'c', 'c', 0,
1184
74.3k
  /* 296 */ 'f', 'p', 0,
1185
74.3k
  /* 299 */ 's', 'p', 0,
1186
74.3k
  /* 302 */ 'y', 0,
1187
74.3k
  };
1188
1189
74.3k
  static const uint16_t RegAsmOffset[] = {
1190
74.3k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
74.3k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
74.3k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
74.3k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
74.3k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
74.3k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
74.3k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
74.3k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
74.3k
    12, 160, 270, 92, 222, 20, 
1199
74.3k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
74.3k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
74.3k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
101k
{
1221
374k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
101k
  const char *AsmString;
1223
101k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
101k
  int OpIdx, PrintMethodIdx;
1225
101k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
101k
  switch (MCInst_getOpcode(MI)) {
1227
58.1k
  default: return NULL;
1228
3.30k
  case SP_BCOND:
1229
3.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
3.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
3.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
3.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
3.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
3.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
1.03k
      AsmString = "bn $\x01";
1241
1.03k
      break;
1242
1.03k
    }
1243
2.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
133
      AsmString = "bne $\x01";
1248
133
      break;
1249
133
    }
1250
2.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
128
      AsmString = "be $\x01";
1255
128
      break;
1256
128
    }
1257
2.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
78
      AsmString = "bg $\x01";
1262
78
      break;
1263
78
    }
1264
1.92k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
230
      AsmString = "ble $\x01";
1269
230
      break;
1270
230
    }
1271
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
200
      AsmString = "bge $\x01";
1276
200
      break;
1277
200
    }
1278
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
125
      AsmString = "bl $\x01";
1283
125
      break;
1284
125
    }
1285
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
151
      AsmString = "bgu $\x01";
1290
151
      break;
1291
151
    }
1292
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
148
      AsmString = "bleu $\x01";
1297
148
      break;
1298
148
    }
1299
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
112
      AsmString = "bcc $\x01";
1304
112
      break;
1305
112
    }
1306
961
    if (MCInst_getNumOperands(MI) == 2 &&
1307
961
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
961
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
205
      AsmString = "bcs $\x01";
1311
205
      break;
1312
205
    }
1313
756
    if (MCInst_getNumOperands(MI) == 2 &&
1314
756
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
756
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
69
      AsmString = "bpos $\x01";
1318
69
      break;
1319
69
    }
1320
687
    if (MCInst_getNumOperands(MI) == 2 &&
1321
687
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
687
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
171
      AsmString = "bneg $\x01";
1325
171
      break;
1326
171
    }
1327
516
    if (MCInst_getNumOperands(MI) == 2 &&
1328
516
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
516
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
234
      AsmString = "bvc $\x01";
1332
234
      break;
1333
234
    }
1334
282
    if (MCInst_getNumOperands(MI) == 2 &&
1335
282
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
282
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
282
      AsmString = "bvs $\x01";
1339
282
      break;
1340
282
    }
1341
0
    return NULL;
1342
3.10k
  case SP_BCONDA:
1343
3.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
3.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
3.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
375
      AsmString = "ba,a $\x01";
1348
375
      break;
1349
375
    }
1350
2.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
354
      AsmString = "bn,a $\x01";
1355
354
      break;
1356
354
    }
1357
2.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
110
      AsmString = "bne,a $\x01";
1362
110
      break;
1363
110
    }
1364
2.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
146
      AsmString = "be,a $\x01";
1369
146
      break;
1370
146
    }
1371
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
188
      AsmString = "bg,a $\x01";
1376
188
      break;
1377
188
    }
1378
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
118
      AsmString = "ble,a $\x01";
1383
118
      break;
1384
118
    }
1385
1.81k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
102
      AsmString = "bge,a $\x01";
1390
102
      break;
1391
102
    }
1392
1.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
265
      AsmString = "bl,a $\x01";
1397
265
      break;
1398
265
    }
1399
1.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
118
      AsmString = "bgu,a $\x01";
1404
118
      break;
1405
118
    }
1406
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
228
      AsmString = "bleu,a $\x01";
1411
228
      break;
1412
228
    }
1413
1.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1414
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
89
      AsmString = "bcc,a $\x01";
1418
89
      break;
1419
89
    }
1420
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1421
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
166
      AsmString = "bcs,a $\x01";
1425
166
      break;
1426
166
    }
1427
849
    if (MCInst_getNumOperands(MI) == 2 &&
1428
849
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
849
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
225
      AsmString = "bpos,a $\x01";
1432
225
      break;
1433
225
    }
1434
624
    if (MCInst_getNumOperands(MI) == 2 &&
1435
624
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
624
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
134
      AsmString = "bneg,a $\x01";
1439
134
      break;
1440
134
    }
1441
490
    if (MCInst_getNumOperands(MI) == 2 &&
1442
490
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
490
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
323
      AsmString = "bvc,a $\x01";
1446
323
      break;
1447
323
    }
1448
167
    if (MCInst_getNumOperands(MI) == 2 &&
1449
167
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
167
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
167
      AsmString = "bvs,a $\x01";
1453
167
      break;
1454
167
    }
1455
0
    return NULL;
1456
4.97k
  case SP_BPFCCANT:
1457
4.97k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
4.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
4.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
4.97k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
4.97k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
291
      AsmString = "fba,a,pn $\x03, $\x01";
1464
291
      break;
1465
291
    }
1466
4.67k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
4.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
4.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
4.67k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
4.67k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
392
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
392
      break;
1474
392
    }
1475
4.28k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
4.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
4.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
4.28k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
4.28k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
130
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
130
      break;
1483
130
    }
1484
4.15k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
4.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
4.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
4.15k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
4.15k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
335
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
335
      break;
1492
335
    }
1493
3.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
3.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
3.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
3.82k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
3.82k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
500
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
500
      break;
1501
500
    }
1502
3.32k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
3.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
3.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
3.32k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
3.32k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
132
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
132
      break;
1510
132
    }
1511
3.19k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
3.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
3.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
3.19k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
3.19k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
232
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
232
      break;
1519
232
    }
1520
2.95k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.95k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.95k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
291
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
291
      break;
1528
291
    }
1529
2.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
2.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
2.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
2.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
2.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
1.31k
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
1.31k
      break;
1537
1.31k
    }
1538
1.35k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.35k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.35k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
88
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
88
      break;
1546
88
    }
1547
1.26k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.26k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
79
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
79
      break;
1555
79
    }
1556
1.18k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.18k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.18k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
165
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
165
      break;
1564
165
    }
1565
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1566
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
1.02k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
75
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
75
      break;
1573
75
    }
1574
945
    if (MCInst_getNumOperands(MI) == 3 &&
1575
945
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
945
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
945
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
945
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
259
      AsmString = "fble,a,pn $\x03, $\x01";
1581
259
      break;
1582
259
    }
1583
686
    if (MCInst_getNumOperands(MI) == 3 &&
1584
686
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
686
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
686
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
686
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
408
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
408
      break;
1591
408
    }
1592
278
    if (MCInst_getNumOperands(MI) == 3 &&
1593
278
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
278
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
278
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
278
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
278
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
278
      break;
1600
278
    }
1601
0
    return NULL;
1602
5.60k
  case SP_BPFCCNT:
1603
5.60k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
5.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
5.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
5.60k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
5.60k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
476
      AsmString = "fba,pn $\x03, $\x01";
1610
476
      break;
1611
476
    }
1612
5.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
5.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
5.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
5.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
5.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
229
      AsmString = "fbn,pn $\x03, $\x01";
1619
229
      break;
1620
229
    }
1621
4.90k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
4.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
4.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
4.90k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
4.90k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
358
      AsmString = "fbu,pn $\x03, $\x01";
1628
358
      break;
1629
358
    }
1630
4.54k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
4.54k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
4.54k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
4.54k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
4.54k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
279
      AsmString = "fbg,pn $\x03, $\x01";
1637
279
      break;
1638
279
    }
1639
4.26k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
4.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
4.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
4.26k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
4.26k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
280
      AsmString = "fbug,pn $\x03, $\x01";
1646
280
      break;
1647
280
    }
1648
3.98k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
3.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
3.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
3.98k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
3.98k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
134
      AsmString = "fbl,pn $\x03, $\x01";
1655
134
      break;
1656
134
    }
1657
3.85k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
3.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
3.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
3.85k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
3.85k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
249
      AsmString = "fbul,pn $\x03, $\x01";
1664
249
      break;
1665
249
    }
1666
3.60k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
3.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
3.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
3.60k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
3.60k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
487
      AsmString = "fblg,pn $\x03, $\x01";
1673
487
      break;
1674
487
    }
1675
3.11k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
3.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
3.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
3.11k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
3.11k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
169
      AsmString = "fbne,pn $\x03, $\x01";
1682
169
      break;
1683
169
    }
1684
2.94k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
2.94k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
2.94k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
2.94k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
2.94k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
928
      AsmString = "fbe,pn $\x03, $\x01";
1691
928
      break;
1692
928
    }
1693
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
2.01k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
528
      AsmString = "fbue,pn $\x03, $\x01";
1700
528
      break;
1701
528
    }
1702
1.49k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
1.49k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
1.49k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
414
      AsmString = "fbge,pn $\x03, $\x01";
1709
414
      break;
1710
414
    }
1711
1.07k
    if (MCInst_getNumOperands(MI) == 3 &&
1712
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
1.07k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
1.07k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
297
      AsmString = "fbuge,pn $\x03, $\x01";
1718
297
      break;
1719
297
    }
1720
780
    if (MCInst_getNumOperands(MI) == 3 &&
1721
780
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
780
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
780
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
780
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
112
      AsmString = "fble,pn $\x03, $\x01";
1727
112
      break;
1728
112
    }
1729
668
    if (MCInst_getNumOperands(MI) == 3 &&
1730
668
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
668
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
668
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
668
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
509
      AsmString = "fbule,pn $\x03, $\x01";
1736
509
      break;
1737
509
    }
1738
159
    if (MCInst_getNumOperands(MI) == 3 &&
1739
159
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
159
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
159
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
159
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
159
      AsmString = "fbo,pn $\x03, $\x01";
1745
159
      break;
1746
159
    }
1747
0
    return NULL;
1748
3.15k
  case SP_BPICCANT:
1749
3.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
3.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
3.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
261
      AsmString = "ba,a,pn %icc, $\x01";
1754
261
      break;
1755
261
    }
1756
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
235
      AsmString = "bn,a,pn %icc, $\x01";
1761
235
      break;
1762
235
    }
1763
2.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
25
      AsmString = "bne,a,pn %icc, $\x01";
1768
25
      break;
1769
25
    }
1770
2.62k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
287
      AsmString = "be,a,pn %icc, $\x01";
1775
287
      break;
1776
287
    }
1777
2.34k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
2.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
2.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
91
      AsmString = "bg,a,pn %icc, $\x01";
1782
91
      break;
1783
91
    }
1784
2.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
2.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
2.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
631
      AsmString = "ble,a,pn %icc, $\x01";
1789
631
      break;
1790
631
    }
1791
1.62k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
287
      AsmString = "bge,a,pn %icc, $\x01";
1796
287
      break;
1797
287
    }
1798
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
90
      AsmString = "bl,a,pn %icc, $\x01";
1803
90
      break;
1804
90
    }
1805
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
169
      AsmString = "bgu,a,pn %icc, $\x01";
1810
169
      break;
1811
169
    }
1812
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
207
      AsmString = "bleu,a,pn %icc, $\x01";
1817
207
      break;
1818
207
    }
1819
867
    if (MCInst_getNumOperands(MI) == 2 &&
1820
867
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
867
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
135
      AsmString = "bcc,a,pn %icc, $\x01";
1824
135
      break;
1825
135
    }
1826
732
    if (MCInst_getNumOperands(MI) == 2 &&
1827
732
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
732
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
85
      AsmString = "bcs,a,pn %icc, $\x01";
1831
85
      break;
1832
85
    }
1833
647
    if (MCInst_getNumOperands(MI) == 2 &&
1834
647
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
647
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
89
      AsmString = "bpos,a,pn %icc, $\x01";
1838
89
      break;
1839
89
    }
1840
558
    if (MCInst_getNumOperands(MI) == 2 &&
1841
558
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
558
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
255
      AsmString = "bneg,a,pn %icc, $\x01";
1845
255
      break;
1846
255
    }
1847
303
    if (MCInst_getNumOperands(MI) == 2 &&
1848
303
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
303
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
120
      AsmString = "bvc,a,pn %icc, $\x01";
1852
120
      break;
1853
120
    }
1854
183
    if (MCInst_getNumOperands(MI) == 2 &&
1855
183
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
183
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
183
      AsmString = "bvs,a,pn %icc, $\x01";
1859
183
      break;
1860
183
    }
1861
0
    return NULL;
1862
4.70k
  case SP_BPICCNT:
1863
4.70k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
4.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
4.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
93
      AsmString = "ba,pn %icc, $\x01";
1868
93
      break;
1869
93
    }
1870
4.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
4.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
4.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
429
      AsmString = "bn,pn %icc, $\x01";
1875
429
      break;
1876
429
    }
1877
4.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
4.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
4.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
177
      AsmString = "bne,pn %icc, $\x01";
1882
177
      break;
1883
177
    }
1884
4.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
4.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
4.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
272
      AsmString = "be,pn %icc, $\x01";
1889
272
      break;
1890
272
    }
1891
3.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
3.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
3.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
516
      AsmString = "bg,pn %icc, $\x01";
1896
516
      break;
1897
516
    }
1898
3.21k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
3.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
3.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
154
      AsmString = "ble,pn %icc, $\x01";
1903
154
      break;
1904
154
    }
1905
3.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
762
      AsmString = "bge,pn %icc, $\x01";
1910
762
      break;
1911
762
    }
1912
2.29k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
2.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
2.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
104
      AsmString = "bl,pn %icc, $\x01";
1917
104
      break;
1918
104
    }
1919
2.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
537
      AsmString = "bgu,pn %icc, $\x01";
1924
537
      break;
1925
537
    }
1926
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
224
      AsmString = "bleu,pn %icc, $\x01";
1931
224
      break;
1932
224
    }
1933
1.43k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
464
      AsmString = "bcc,pn %icc, $\x01";
1938
464
      break;
1939
464
    }
1940
970
    if (MCInst_getNumOperands(MI) == 2 &&
1941
970
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
970
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
96
      AsmString = "bcs,pn %icc, $\x01";
1945
96
      break;
1946
96
    }
1947
874
    if (MCInst_getNumOperands(MI) == 2 &&
1948
874
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
874
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
116
      AsmString = "bpos,pn %icc, $\x01";
1952
116
      break;
1953
116
    }
1954
758
    if (MCInst_getNumOperands(MI) == 2 &&
1955
758
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
758
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
98
      AsmString = "bneg,pn %icc, $\x01";
1959
98
      break;
1960
98
    }
1961
660
    if (MCInst_getNumOperands(MI) == 2 &&
1962
660
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
660
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
447
      AsmString = "bvc,pn %icc, $\x01";
1966
447
      break;
1967
447
    }
1968
213
    if (MCInst_getNumOperands(MI) == 2 &&
1969
213
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
213
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
213
      AsmString = "bvs,pn %icc, $\x01";
1973
213
      break;
1974
213
    }
1975
0
    return NULL;
1976
2.30k
  case SP_BPXCCANT:
1977
2.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
2.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
2.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
103
      AsmString = "ba,a,pn %xcc, $\x01";
1982
103
      break;
1983
103
    }
1984
2.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
233
      AsmString = "bn,a,pn %xcc, $\x01";
1989
233
      break;
1990
233
    }
1991
1.97k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
38
      AsmString = "bne,a,pn %xcc, $\x01";
1996
38
      break;
1997
38
    }
1998
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
113
      AsmString = "be,a,pn %xcc, $\x01";
2003
113
      break;
2004
113
    }
2005
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
205
      AsmString = "bg,a,pn %xcc, $\x01";
2010
205
      break;
2011
205
    }
2012
1.61k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
251
      AsmString = "ble,a,pn %xcc, $\x01";
2017
251
      break;
2018
251
    }
2019
1.36k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
100
      AsmString = "bge,a,pn %xcc, $\x01";
2024
100
      break;
2025
100
    }
2026
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
54
      AsmString = "bl,a,pn %xcc, $\x01";
2031
54
      break;
2032
54
    }
2033
1.21k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
227
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
227
      break;
2039
227
    }
2040
985
    if (MCInst_getNumOperands(MI) == 2 &&
2041
985
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
985
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
91
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
91
      break;
2046
91
    }
2047
894
    if (MCInst_getNumOperands(MI) == 2 &&
2048
894
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
894
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
119
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
119
      break;
2053
119
    }
2054
775
    if (MCInst_getNumOperands(MI) == 2 &&
2055
775
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
775
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
132
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
132
      break;
2060
132
    }
2061
643
    if (MCInst_getNumOperands(MI) == 2 &&
2062
643
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
643
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
125
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
125
      break;
2067
125
    }
2068
518
    if (MCInst_getNumOperands(MI) == 2 &&
2069
518
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
518
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
195
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
195
      break;
2074
195
    }
2075
323
    if (MCInst_getNumOperands(MI) == 2 &&
2076
323
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
323
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
96
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
96
      break;
2081
96
    }
2082
227
    if (MCInst_getNumOperands(MI) == 2 &&
2083
227
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
227
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
227
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
227
      break;
2088
227
    }
2089
0
    return NULL;
2090
2.62k
  case SP_BPXCCNT:
2091
2.62k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
134
      AsmString = "ba,pn %xcc, $\x01";
2096
134
      break;
2097
134
    }
2098
2.48k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
360
      AsmString = "bn,pn %xcc, $\x01";
2103
360
      break;
2104
360
    }
2105
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
197
      AsmString = "bne,pn %xcc, $\x01";
2110
197
      break;
2111
197
    }
2112
1.92k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
77
      AsmString = "be,pn %xcc, $\x01";
2117
77
      break;
2118
77
    }
2119
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
188
      AsmString = "bg,pn %xcc, $\x01";
2124
188
      break;
2125
188
    }
2126
1.66k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
124
      AsmString = "ble,pn %xcc, $\x01";
2131
124
      break;
2132
124
    }
2133
1.54k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.54k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.54k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
125
      AsmString = "bge,pn %xcc, $\x01";
2138
125
      break;
2139
125
    }
2140
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
79
      AsmString = "bl,pn %xcc, $\x01";
2145
79
      break;
2146
79
    }
2147
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
337
      AsmString = "bgu,pn %xcc, $\x01";
2152
337
      break;
2153
337
    }
2154
999
    if (MCInst_getNumOperands(MI) == 2 &&
2155
999
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
999
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
146
      AsmString = "bleu,pn %xcc, $\x01";
2159
146
      break;
2160
146
    }
2161
853
    if (MCInst_getNumOperands(MI) == 2 &&
2162
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
115
      AsmString = "bcc,pn %xcc, $\x01";
2166
115
      break;
2167
115
    }
2168
738
    if (MCInst_getNumOperands(MI) == 2 &&
2169
738
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
738
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
242
      AsmString = "bcs,pn %xcc, $\x01";
2173
242
      break;
2174
242
    }
2175
496
    if (MCInst_getNumOperands(MI) == 2 &&
2176
496
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
496
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
44
      AsmString = "bpos,pn %xcc, $\x01";
2180
44
      break;
2181
44
    }
2182
452
    if (MCInst_getNumOperands(MI) == 2 &&
2183
452
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
452
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
111
      AsmString = "bneg,pn %xcc, $\x01";
2187
111
      break;
2188
111
    }
2189
341
    if (MCInst_getNumOperands(MI) == 2 &&
2190
341
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
341
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
261
      AsmString = "bvc,pn %xcc, $\x01";
2194
261
      break;
2195
261
    }
2196
80
    if (MCInst_getNumOperands(MI) == 2 &&
2197
80
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
80
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
80
      AsmString = "bvs,pn %xcc, $\x01";
2201
80
      break;
2202
80
    }
2203
0
    return NULL;
2204
109
  case SP_FMOVD_ICC:
2205
109
    if (MCInst_getNumOperands(MI) == 3 &&
2206
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
109
    if (MCInst_getNumOperands(MI) == 3 &&
2217
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
109
    if (MCInst_getNumOperands(MI) == 3 &&
2228
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
109
    if (MCInst_getNumOperands(MI) == 3 &&
2239
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
109
    if (MCInst_getNumOperands(MI) == 3 &&
2250
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
109
    if (MCInst_getNumOperands(MI) == 3 &&
2261
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
109
    if (MCInst_getNumOperands(MI) == 3 &&
2272
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
109
    if (MCInst_getNumOperands(MI) == 3 &&
2283
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
109
    if (MCInst_getNumOperands(MI) == 3 &&
2294
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
109
    if (MCInst_getNumOperands(MI) == 3 &&
2305
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
109
    if (MCInst_getNumOperands(MI) == 3 &&
2316
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
109
    if (MCInst_getNumOperands(MI) == 3 &&
2327
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
109
    if (MCInst_getNumOperands(MI) == 3 &&
2338
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
109
    if (MCInst_getNumOperands(MI) == 3 &&
2349
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
109
    if (MCInst_getNumOperands(MI) == 3 &&
2360
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
109
    if (MCInst_getNumOperands(MI) == 3 &&
2371
109
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
109
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
109
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
109
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
109
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
109
    return NULL;
2382
261
  case SP_FMOVD_XCC:
2383
261
    if (MCInst_getNumOperands(MI) == 3 &&
2384
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
261
    if (MCInst_getNumOperands(MI) == 3 &&
2395
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
261
    if (MCInst_getNumOperands(MI) == 3 &&
2406
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
261
    if (MCInst_getNumOperands(MI) == 3 &&
2417
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
261
    if (MCInst_getNumOperands(MI) == 3 &&
2428
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
261
    if (MCInst_getNumOperands(MI) == 3 &&
2439
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
261
    if (MCInst_getNumOperands(MI) == 3 &&
2450
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
261
    if (MCInst_getNumOperands(MI) == 3 &&
2461
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
261
    if (MCInst_getNumOperands(MI) == 3 &&
2472
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
261
    if (MCInst_getNumOperands(MI) == 3 &&
2483
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
261
    if (MCInst_getNumOperands(MI) == 3 &&
2494
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
261
    if (MCInst_getNumOperands(MI) == 3 &&
2505
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
261
    if (MCInst_getNumOperands(MI) == 3 &&
2516
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
261
    if (MCInst_getNumOperands(MI) == 3 &&
2527
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
261
    if (MCInst_getNumOperands(MI) == 3 &&
2538
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
261
    if (MCInst_getNumOperands(MI) == 3 &&
2549
261
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
261
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
261
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
261
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
261
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
261
    return NULL;
2560
103
  case SP_FMOVQ_ICC:
2561
103
    if (MCInst_getNumOperands(MI) == 3 &&
2562
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
103
    if (MCInst_getNumOperands(MI) == 3 &&
2573
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
103
    if (MCInst_getNumOperands(MI) == 3 &&
2584
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
103
    if (MCInst_getNumOperands(MI) == 3 &&
2595
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
103
    if (MCInst_getNumOperands(MI) == 3 &&
2606
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
103
    if (MCInst_getNumOperands(MI) == 3 &&
2617
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
103
    if (MCInst_getNumOperands(MI) == 3 &&
2628
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
103
    if (MCInst_getNumOperands(MI) == 3 &&
2639
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
103
    if (MCInst_getNumOperands(MI) == 3 &&
2650
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
103
    if (MCInst_getNumOperands(MI) == 3 &&
2661
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
103
    if (MCInst_getNumOperands(MI) == 3 &&
2672
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
103
    if (MCInst_getNumOperands(MI) == 3 &&
2683
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
103
    if (MCInst_getNumOperands(MI) == 3 &&
2694
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
103
    if (MCInst_getNumOperands(MI) == 3 &&
2705
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
103
    if (MCInst_getNumOperands(MI) == 3 &&
2716
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
103
    if (MCInst_getNumOperands(MI) == 3 &&
2727
103
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
103
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
103
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
103
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
103
    return NULL;
2738
91
  case SP_FMOVQ_XCC:
2739
91
    if (MCInst_getNumOperands(MI) == 3 &&
2740
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
91
    if (MCInst_getNumOperands(MI) == 3 &&
2751
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
91
    if (MCInst_getNumOperands(MI) == 3 &&
2762
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
91
    if (MCInst_getNumOperands(MI) == 3 &&
2773
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
91
    if (MCInst_getNumOperands(MI) == 3 &&
2784
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
91
    if (MCInst_getNumOperands(MI) == 3 &&
2795
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
91
    if (MCInst_getNumOperands(MI) == 3 &&
2806
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
91
    if (MCInst_getNumOperands(MI) == 3 &&
2817
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
91
    if (MCInst_getNumOperands(MI) == 3 &&
2828
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
91
    if (MCInst_getNumOperands(MI) == 3 &&
2839
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
91
    if (MCInst_getNumOperands(MI) == 3 &&
2850
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
91
    if (MCInst_getNumOperands(MI) == 3 &&
2861
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
91
    if (MCInst_getNumOperands(MI) == 3 &&
2872
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
91
    if (MCInst_getNumOperands(MI) == 3 &&
2883
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
91
    if (MCInst_getNumOperands(MI) == 3 &&
2894
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
91
    if (MCInst_getNumOperands(MI) == 3 &&
2905
91
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
91
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
91
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
91
    return NULL;
2916
59
  case SP_FMOVS_ICC:
2917
59
    if (MCInst_getNumOperands(MI) == 3 &&
2918
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
59
    if (MCInst_getNumOperands(MI) == 3 &&
2929
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
59
    if (MCInst_getNumOperands(MI) == 3 &&
2940
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
59
    if (MCInst_getNumOperands(MI) == 3 &&
2951
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
59
    if (MCInst_getNumOperands(MI) == 3 &&
2962
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
59
    if (MCInst_getNumOperands(MI) == 3 &&
2973
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
59
    if (MCInst_getNumOperands(MI) == 3 &&
2984
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
59
    if (MCInst_getNumOperands(MI) == 3 &&
2995
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
59
    if (MCInst_getNumOperands(MI) == 3 &&
3006
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
59
    if (MCInst_getNumOperands(MI) == 3 &&
3017
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
59
    if (MCInst_getNumOperands(MI) == 3 &&
3028
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
59
    if (MCInst_getNumOperands(MI) == 3 &&
3039
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
59
    if (MCInst_getNumOperands(MI) == 3 &&
3050
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
59
    if (MCInst_getNumOperands(MI) == 3 &&
3061
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
59
    if (MCInst_getNumOperands(MI) == 3 &&
3072
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
59
    if (MCInst_getNumOperands(MI) == 3 &&
3083
59
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
59
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
59
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
59
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
59
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
59
    return NULL;
3094
25
  case SP_FMOVS_XCC:
3095
25
    if (MCInst_getNumOperands(MI) == 3 &&
3096
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
25
    if (MCInst_getNumOperands(MI) == 3 &&
3107
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
25
    if (MCInst_getNumOperands(MI) == 3 &&
3118
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
25
    if (MCInst_getNumOperands(MI) == 3 &&
3129
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
25
    if (MCInst_getNumOperands(MI) == 3 &&
3140
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
25
    if (MCInst_getNumOperands(MI) == 3 &&
3151
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
25
    if (MCInst_getNumOperands(MI) == 3 &&
3162
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
25
    if (MCInst_getNumOperands(MI) == 3 &&
3173
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
25
    if (MCInst_getNumOperands(MI) == 3 &&
3184
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
25
    if (MCInst_getNumOperands(MI) == 3 &&
3195
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
25
    if (MCInst_getNumOperands(MI) == 3 &&
3206
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
25
    if (MCInst_getNumOperands(MI) == 3 &&
3217
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
25
    if (MCInst_getNumOperands(MI) == 3 &&
3228
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
25
    if (MCInst_getNumOperands(MI) == 3 &&
3239
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
25
    if (MCInst_getNumOperands(MI) == 3 &&
3250
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
25
    if (MCInst_getNumOperands(MI) == 3 &&
3261
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
25
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
25
    return NULL;
3272
92
  case SP_MOVICCri:
3273
92
    if (MCInst_getNumOperands(MI) == 3 &&
3274
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
92
    if (MCInst_getNumOperands(MI) == 3 &&
3283
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
92
    if (MCInst_getNumOperands(MI) == 3 &&
3292
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
92
    if (MCInst_getNumOperands(MI) == 3 &&
3301
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
92
    if (MCInst_getNumOperands(MI) == 3 &&
3310
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
92
    if (MCInst_getNumOperands(MI) == 3 &&
3319
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
92
    if (MCInst_getNumOperands(MI) == 3 &&
3328
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
92
    if (MCInst_getNumOperands(MI) == 3 &&
3337
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
92
    if (MCInst_getNumOperands(MI) == 3 &&
3346
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
92
    if (MCInst_getNumOperands(MI) == 3 &&
3355
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
92
    if (MCInst_getNumOperands(MI) == 3 &&
3364
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
92
    if (MCInst_getNumOperands(MI) == 3 &&
3373
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
92
    if (MCInst_getNumOperands(MI) == 3 &&
3382
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
92
    if (MCInst_getNumOperands(MI) == 3 &&
3391
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
92
    if (MCInst_getNumOperands(MI) == 3 &&
3400
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
92
    if (MCInst_getNumOperands(MI) == 3 &&
3409
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
92
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
92
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
92
    return NULL;
3418
140
  case SP_MOVICCrr:
3419
140
    if (MCInst_getNumOperands(MI) == 3 &&
3420
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
140
    if (MCInst_getNumOperands(MI) == 3 &&
3431
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
140
    if (MCInst_getNumOperands(MI) == 3 &&
3442
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
140
    if (MCInst_getNumOperands(MI) == 3 &&
3453
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
140
    if (MCInst_getNumOperands(MI) == 3 &&
3464
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
140
    if (MCInst_getNumOperands(MI) == 3 &&
3475
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
140
    if (MCInst_getNumOperands(MI) == 3 &&
3486
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
140
    if (MCInst_getNumOperands(MI) == 3 &&
3497
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
140
    if (MCInst_getNumOperands(MI) == 3 &&
3508
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
140
    if (MCInst_getNumOperands(MI) == 3 &&
3519
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
140
    if (MCInst_getNumOperands(MI) == 3 &&
3530
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
140
    if (MCInst_getNumOperands(MI) == 3 &&
3541
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
140
    if (MCInst_getNumOperands(MI) == 3 &&
3552
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
140
    if (MCInst_getNumOperands(MI) == 3 &&
3563
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
140
    if (MCInst_getNumOperands(MI) == 3 &&
3574
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
140
    if (MCInst_getNumOperands(MI) == 3 &&
3585
140
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
140
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
140
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
140
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
140
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
140
    return NULL;
3596
121
  case SP_MOVXCCri:
3597
121
    if (MCInst_getNumOperands(MI) == 3 &&
3598
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
121
    if (MCInst_getNumOperands(MI) == 3 &&
3607
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
121
    if (MCInst_getNumOperands(MI) == 3 &&
3616
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
121
    if (MCInst_getNumOperands(MI) == 3 &&
3625
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
121
    if (MCInst_getNumOperands(MI) == 3 &&
3634
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
121
    if (MCInst_getNumOperands(MI) == 3 &&
3643
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
121
    if (MCInst_getNumOperands(MI) == 3 &&
3652
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
121
    if (MCInst_getNumOperands(MI) == 3 &&
3661
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
121
    if (MCInst_getNumOperands(MI) == 3 &&
3670
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
121
    if (MCInst_getNumOperands(MI) == 3 &&
3679
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
121
    if (MCInst_getNumOperands(MI) == 3 &&
3688
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
121
    if (MCInst_getNumOperands(MI) == 3 &&
3697
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
121
    if (MCInst_getNumOperands(MI) == 3 &&
3706
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
121
    if (MCInst_getNumOperands(MI) == 3 &&
3715
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
121
    if (MCInst_getNumOperands(MI) == 3 &&
3724
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
121
    if (MCInst_getNumOperands(MI) == 3 &&
3733
121
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
121
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
121
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
121
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
121
    return NULL;
3742
32
  case SP_MOVXCCrr:
3743
32
    if (MCInst_getNumOperands(MI) == 3 &&
3744
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
32
    if (MCInst_getNumOperands(MI) == 3 &&
3755
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
32
    if (MCInst_getNumOperands(MI) == 3 &&
3766
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
32
    if (MCInst_getNumOperands(MI) == 3 &&
3777
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
32
    if (MCInst_getNumOperands(MI) == 3 &&
3788
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
32
    if (MCInst_getNumOperands(MI) == 3 &&
3799
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
32
    if (MCInst_getNumOperands(MI) == 3 &&
3810
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
32
    if (MCInst_getNumOperands(MI) == 3 &&
3821
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
32
    if (MCInst_getNumOperands(MI) == 3 &&
3832
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
32
    if (MCInst_getNumOperands(MI) == 3 &&
3843
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
32
    if (MCInst_getNumOperands(MI) == 3 &&
3854
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
32
    if (MCInst_getNumOperands(MI) == 3 &&
3865
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
32
    if (MCInst_getNumOperands(MI) == 3 &&
3876
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
32
    if (MCInst_getNumOperands(MI) == 3 &&
3887
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
32
    if (MCInst_getNumOperands(MI) == 3 &&
3898
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
32
    if (MCInst_getNumOperands(MI) == 3 &&
3909
32
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
32
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
32
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
32
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
32
    return NULL;
3920
364
  case SP_ORri:
3921
364
    if (MCInst_getNumOperands(MI) == 3 &&
3922
364
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
364
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
364
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
118
      AsmString = "mov $\x03, $\x01";
3927
118
      break;
3928
118
    }
3929
246
    return NULL;
3930
158
  case SP_ORrr:
3931
158
    if (MCInst_getNumOperands(MI) == 3 &&
3932
158
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
158
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
158
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
158
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
158
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
62
      AsmString = "mov $\x03, $\x01";
3939
62
      break;
3940
62
    }
3941
96
    return NULL;
3942
569
  case SP_RESTORErr:
3943
569
    if (MCInst_getNumOperands(MI) == 3 &&
3944
569
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
569
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
569
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
302
      AsmString = "restore";
3949
302
      break;
3950
302
    }
3951
267
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
4.22k
  case SP_TXCCri:
3971
4.22k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
4.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
4.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
4.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
4.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
54
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
54
      break;
3979
54
    }
3980
4.16k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
4.16k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
4.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
4.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
4.16k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
4.16k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
4.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
4.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
4.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
124
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
124
      break;
3996
124
    }
3997
4.04k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
4.04k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
4.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
4.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
4.04k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
4.04k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
4.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
4.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
4.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
74
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
74
      break;
4013
74
    }
4014
3.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
3.97k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
3.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
3.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
3.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
3.97k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
3.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
3.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
3.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
51
      AsmString = "te %xcc, $\x01 + $\x02";
4029
51
      break;
4030
51
    }
4031
3.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
3.92k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
3.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
3.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
3.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
3.92k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
3.92k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
3.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
3.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
582
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
582
      break;
4047
582
    }
4048
3.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
3.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
3.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
3.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
3.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
3.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
3.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
3.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
3.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
85
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
85
      break;
4064
85
    }
4065
3.25k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
3.25k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
3.25k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
3.25k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
3.25k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
3.25k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
3.25k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
3.25k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
3.25k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
166
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
166
      break;
4081
166
    }
4082
3.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
3.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
3.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
3.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
3.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
3.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
3.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
3.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
3.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
21
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
21
      break;
4098
21
    }
4099
3.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
3.06k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
3.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
3.06k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
3.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
50
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
50
      break;
4115
50
    }
4116
3.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
3.01k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
3.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
3.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
3.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
3.01k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
3.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
3.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
3.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
1.24k
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
1.24k
      break;
4132
1.24k
    }
4133
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.77k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.77k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.77k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
205
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
205
      break;
4149
205
    }
4150
1.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.57k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.57k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
197
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
197
      break;
4166
197
    }
4167
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
1.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
1.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
753
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
753
      break;
4183
753
    }
4184
621
    if (MCInst_getNumOperands(MI) == 3 &&
4185
621
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
621
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
621
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
621
    if (MCInst_getNumOperands(MI) == 3 &&
4193
621
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
621
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
621
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
621
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
167
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
167
      break;
4200
167
    }
4201
454
    if (MCInst_getNumOperands(MI) == 3 &&
4202
454
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
454
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
454
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
454
    if (MCInst_getNumOperands(MI) == 3 &&
4210
454
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
454
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
454
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
454
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
186
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
186
      break;
4217
186
    }
4218
268
    if (MCInst_getNumOperands(MI) == 3 &&
4219
268
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
268
    if (MCInst_getNumOperands(MI) == 3 &&
4227
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
268
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
268
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
268
      break;
4234
268
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
3.43k
  case SP_TXCCrr:
4245
3.43k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
3.43k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
3.43k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
3.43k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
3.43k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
3.43k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
3.43k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
75
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
75
      break;
4255
75
    }
4256
3.35k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
3.35k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
3.35k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
3.35k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
3.35k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
3.35k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
3.35k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
3.35k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
3.35k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
3.35k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
3.35k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
3.35k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
3.35k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
71
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
71
      break;
4276
71
    }
4277
3.28k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
3.28k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
3.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
3.28k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
3.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
3.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
39
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
39
      break;
4297
39
    }
4298
3.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
3.24k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
3.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
3.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
3.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
3.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
3.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
3.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
3.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
3.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
3.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
3.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
3.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
129
      AsmString = "te %xcc, $\x01 + $\x02";
4317
129
      break;
4318
129
    }
4319
3.11k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
3.11k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
3.11k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
3.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
3.11k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
3.11k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
3.11k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
3.11k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
3.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
3.11k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
3.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
3.11k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
3.11k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
171
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
171
      break;
4339
171
    }
4340
2.94k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.94k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.94k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.94k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.94k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.94k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.94k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.94k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.94k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.94k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.94k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.94k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.94k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
43
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
43
      break;
4360
43
    }
4361
2.90k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.90k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.90k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.90k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.90k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.90k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.90k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.90k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.90k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
201
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
201
      break;
4381
201
    }
4382
2.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.70k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
52
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
52
      break;
4402
52
    }
4403
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
2.65k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
1.00k
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
1.00k
      break;
4423
1.00k
    }
4424
1.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.64k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
429
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
429
      break;
4444
429
    }
4445
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.22k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
129
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
129
      break;
4465
129
    }
4466
1.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.09k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
138
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
138
      break;
4486
138
    }
4487
953
    if (MCInst_getNumOperands(MI) == 3 &&
4488
953
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
953
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
953
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
953
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
953
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
953
    if (MCInst_getNumOperands(MI) == 3 &&
4498
953
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
953
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
953
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
953
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
953
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
953
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
46
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
46
      break;
4507
46
    }
4508
907
    if (MCInst_getNumOperands(MI) == 3 &&
4509
907
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
907
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
907
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
907
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
907
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
907
    if (MCInst_getNumOperands(MI) == 3 &&
4519
907
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
907
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
907
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
907
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
907
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
907
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
34
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
34
      break;
4528
34
    }
4529
873
    if (MCInst_getNumOperands(MI) == 3 &&
4530
873
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
873
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
873
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
873
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
873
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
873
    if (MCInst_getNumOperands(MI) == 3 &&
4540
873
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
873
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
873
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
873
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
873
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
873
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
628
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
628
      break;
4549
628
    }
4550
245
    if (MCInst_getNumOperands(MI) == 3 &&
4551
245
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
245
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
245
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
245
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
245
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
245
    if (MCInst_getNumOperands(MI) == 3 &&
4561
245
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
245
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
245
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
245
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
245
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
245
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
245
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
245
      break;
4570
245
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
319
  case SP_V9FCMPD:
4583
319
    if (MCInst_getNumOperands(MI) == 3 &&
4584
319
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
319
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
319
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
319
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
319
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
76
      AsmString = "fcmpd $\x02, $\x03";
4591
76
      break;
4592
76
    }
4593
243
    return NULL;
4594
329
  case SP_V9FCMPED:
4595
329
    if (MCInst_getNumOperands(MI) == 3 &&
4596
329
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
329
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
329
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
60
      AsmString = "fcmped $\x02, $\x03";
4603
60
      break;
4604
60
    }
4605
269
    return NULL;
4606
114
  case SP_V9FCMPEQ:
4607
114
    if (MCInst_getNumOperands(MI) == 3 &&
4608
114
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
114
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
114
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
41
      AsmString = "fcmpeq $\x02, $\x03";
4615
41
      break;
4616
41
    }
4617
73
    return NULL;
4618
643
  case SP_V9FCMPES:
4619
643
    if (MCInst_getNumOperands(MI) == 3 &&
4620
643
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
643
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
643
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
643
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
643
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
76
      AsmString = "fcmpes $\x02, $\x03";
4627
76
      break;
4628
76
    }
4629
567
    return NULL;
4630
891
  case SP_V9FCMPQ:
4631
891
    if (MCInst_getNumOperands(MI) == 3 &&
4632
891
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
891
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
891
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
891
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
891
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
225
      AsmString = "fcmpq $\x02, $\x03";
4639
225
      break;
4640
225
    }
4641
666
    return NULL;
4642
301
  case SP_V9FCMPS:
4643
301
    if (MCInst_getNumOperands(MI) == 3 &&
4644
301
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
301
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
301
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
301
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
301
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
61
      AsmString = "fcmps $\x02, $\x03";
4651
61
      break;
4652
61
    }
4653
240
    return NULL;
4654
50
  case SP_V9FMOVD_FCC:
4655
50
    if (MCInst_getNumOperands(MI) == 4 &&
4656
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
50
    if (MCInst_getNumOperands(MI) == 4 &&
4669
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
50
    if (MCInst_getNumOperands(MI) == 4 &&
4682
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
50
    if (MCInst_getNumOperands(MI) == 4 &&
4695
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
50
    if (MCInst_getNumOperands(MI) == 4 &&
4708
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
50
    if (MCInst_getNumOperands(MI) == 4 &&
4721
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
50
    if (MCInst_getNumOperands(MI) == 4 &&
4734
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
50
    if (MCInst_getNumOperands(MI) == 4 &&
4747
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
50
    if (MCInst_getNumOperands(MI) == 4 &&
4760
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
50
    if (MCInst_getNumOperands(MI) == 4 &&
4773
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
50
    if (MCInst_getNumOperands(MI) == 4 &&
4786
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
50
    if (MCInst_getNumOperands(MI) == 4 &&
4799
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
50
    if (MCInst_getNumOperands(MI) == 4 &&
4812
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
50
    if (MCInst_getNumOperands(MI) == 4 &&
4825
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
50
    if (MCInst_getNumOperands(MI) == 4 &&
4838
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
50
    if (MCInst_getNumOperands(MI) == 4 &&
4851
50
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
50
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
50
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
50
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
50
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
50
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
50
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
50
    return NULL;
4864
51
  case SP_V9FMOVQ_FCC:
4865
51
    if (MCInst_getNumOperands(MI) == 4 &&
4866
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
51
    if (MCInst_getNumOperands(MI) == 4 &&
4879
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
51
    if (MCInst_getNumOperands(MI) == 4 &&
4892
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
51
    if (MCInst_getNumOperands(MI) == 4 &&
4905
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
51
    if (MCInst_getNumOperands(MI) == 4 &&
4918
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
51
    if (MCInst_getNumOperands(MI) == 4 &&
4931
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
51
    if (MCInst_getNumOperands(MI) == 4 &&
4944
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
51
    if (MCInst_getNumOperands(MI) == 4 &&
4957
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
51
    if (MCInst_getNumOperands(MI) == 4 &&
4970
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
51
    if (MCInst_getNumOperands(MI) == 4 &&
4983
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
51
    if (MCInst_getNumOperands(MI) == 4 &&
4996
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
51
    if (MCInst_getNumOperands(MI) == 4 &&
5009
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
51
    if (MCInst_getNumOperands(MI) == 4 &&
5022
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
51
    if (MCInst_getNumOperands(MI) == 4 &&
5035
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
51
    if (MCInst_getNumOperands(MI) == 4 &&
5048
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
51
    if (MCInst_getNumOperands(MI) == 4 &&
5061
51
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
51
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
51
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
51
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
51
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
51
    return NULL;
5074
362
  case SP_V9FMOVS_FCC:
5075
362
    if (MCInst_getNumOperands(MI) == 4 &&
5076
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
362
    if (MCInst_getNumOperands(MI) == 4 &&
5089
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
362
    if (MCInst_getNumOperands(MI) == 4 &&
5102
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
362
    if (MCInst_getNumOperands(MI) == 4 &&
5115
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
362
    if (MCInst_getNumOperands(MI) == 4 &&
5128
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
362
    if (MCInst_getNumOperands(MI) == 4 &&
5141
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
362
    if (MCInst_getNumOperands(MI) == 4 &&
5154
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
362
    if (MCInst_getNumOperands(MI) == 4 &&
5167
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
362
    if (MCInst_getNumOperands(MI) == 4 &&
5180
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
362
    if (MCInst_getNumOperands(MI) == 4 &&
5193
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
362
    if (MCInst_getNumOperands(MI) == 4 &&
5206
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
362
    if (MCInst_getNumOperands(MI) == 4 &&
5219
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
362
    if (MCInst_getNumOperands(MI) == 4 &&
5232
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
362
    if (MCInst_getNumOperands(MI) == 4 &&
5245
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
362
    if (MCInst_getNumOperands(MI) == 4 &&
5258
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
362
    if (MCInst_getNumOperands(MI) == 4 &&
5271
362
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
362
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
362
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
362
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
362
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
362
    return NULL;
5284
378
  case SP_V9MOVFCCri:
5285
378
    if (MCInst_getNumOperands(MI) == 4 &&
5286
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
378
    if (MCInst_getNumOperands(MI) == 4 &&
5297
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
378
    if (MCInst_getNumOperands(MI) == 4 &&
5308
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
378
    if (MCInst_getNumOperands(MI) == 4 &&
5319
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
378
    if (MCInst_getNumOperands(MI) == 4 &&
5330
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
378
    if (MCInst_getNumOperands(MI) == 4 &&
5341
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
378
    if (MCInst_getNumOperands(MI) == 4 &&
5352
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
378
    if (MCInst_getNumOperands(MI) == 4 &&
5363
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
378
    if (MCInst_getNumOperands(MI) == 4 &&
5374
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
378
    if (MCInst_getNumOperands(MI) == 4 &&
5385
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
378
    if (MCInst_getNumOperands(MI) == 4 &&
5396
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
378
    if (MCInst_getNumOperands(MI) == 4 &&
5407
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
378
    if (MCInst_getNumOperands(MI) == 4 &&
5418
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
378
    if (MCInst_getNumOperands(MI) == 4 &&
5429
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
378
    if (MCInst_getNumOperands(MI) == 4 &&
5440
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
378
    if (MCInst_getNumOperands(MI) == 4 &&
5451
378
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
378
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
378
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
378
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
378
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
378
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
378
    return NULL;
5462
337
  case SP_V9MOVFCCrr:
5463
337
    if (MCInst_getNumOperands(MI) == 4 &&
5464
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
337
    if (MCInst_getNumOperands(MI) == 4 &&
5477
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
337
    if (MCInst_getNumOperands(MI) == 4 &&
5490
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
337
    if (MCInst_getNumOperands(MI) == 4 &&
5503
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
337
    if (MCInst_getNumOperands(MI) == 4 &&
5516
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
337
    if (MCInst_getNumOperands(MI) == 4 &&
5529
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
337
    if (MCInst_getNumOperands(MI) == 4 &&
5542
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
337
    if (MCInst_getNumOperands(MI) == 4 &&
5555
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
337
    if (MCInst_getNumOperands(MI) == 4 &&
5568
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
337
    if (MCInst_getNumOperands(MI) == 4 &&
5581
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
337
    if (MCInst_getNumOperands(MI) == 4 &&
5594
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
337
    if (MCInst_getNumOperands(MI) == 4 &&
5607
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
337
    if (MCInst_getNumOperands(MI) == 4 &&
5620
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
337
    if (MCInst_getNumOperands(MI) == 4 &&
5633
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
337
    if (MCInst_getNumOperands(MI) == 4 &&
5646
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
337
    if (MCInst_getNumOperands(MI) == 4 &&
5659
337
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
337
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
337
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
337
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
337
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
337
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
337
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
337
    return NULL;
5672
101k
  }
5673
5674
38.4k
  tmp = cs_strdup(AsmString);
5675
38.4k
  AsmMnem = tmp;
5676
258k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
258k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
38.1k
      *AsmOps = '\0';
5679
38.1k
      AsmOps++;
5680
38.1k
      break;
5681
38.1k
    }
5682
258k
  }
5683
38.4k
  SStream_concat0(OS, AsmMnem);
5684
38.4k
  if (*AsmOps) {
5685
38.1k
    SStream_concat0(OS, "\t");
5686
38.1k
    if (strstr(AsmOps, "icc"))
5687
7.85k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
38.1k
    if (strstr(AsmOps, "xcc"))
5689
12.5k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
263k
    for (c = AsmOps; *c; c++) {
5691
225k
      if (*c == '$') {
5692
57.0k
        c += 1;
5693
57.0k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
57.0k
          printOperand(MI, *c - 1, OS);
5701
168k
      } else {
5702
168k
        SStream_concat(OS, "%c", *c);
5703
168k
      }
5704
225k
    }
5705
38.1k
  }
5706
38.4k
  return tmp;
5707
101k
}
5708
5709
#endif // PRINT_ALIAS_INSTR