Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/TMS320C64x/TMS320C64xInstPrinter.c
Line
Count
Source (jump to first uncovered line)
1
/* Capstone Disassembly Engine */
2
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4
#ifdef CAPSTONE_HAS_TMS320C64X
5
6
#ifdef _MSC_VER
7
// Disable security warnings for strcpy
8
#ifndef _CRT_SECURE_NO_WARNINGS
9
#define _CRT_SECURE_NO_WARNINGS
10
#endif
11
12
// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
13
// security purposes.
14
#pragma warning(disable:28719)
15
#endif
16
17
#include <ctype.h>
18
#include <string.h>
19
20
#include "TMS320C64xInstPrinter.h"
21
#include "../../MCInst.h"
22
#include "../../utils.h"
23
#include "../../SStream.h"
24
#include "../../MCRegisterInfo.h"
25
#include "../../MathExtras.h"
26
#include "TMS320C64xMapping.h"
27
28
#include "capstone/tms320c64x.h"
29
30
static const char *getRegisterName(unsigned RegNo);
31
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
32
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
33
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
34
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);
35
36
void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
37
57.3k
{
38
57.3k
  SStream ss;
39
57.3k
  char *p, *p2, tmp[8];
40
57.3k
  unsigned int unit = 0;
41
57.3k
  int i;
42
57.3k
  cs_tms320c64x *tms320c64x;
43
44
57.3k
  if (mci->csh->detail) {
45
57.3k
    tms320c64x = &mci->flat_insn->detail->tms320c64x;
46
47
57.3k
    for (i = 0; i < insn->detail->groups_count; i++) {
48
57.3k
      switch(insn->detail->groups[i]) {
49
18.3k
        case TMS320C64X_GRP_FUNIT_D:
50
18.3k
          unit = TMS320C64X_FUNIT_D;
51
18.3k
          break;
52
11.9k
        case TMS320C64X_GRP_FUNIT_L:
53
11.9k
          unit = TMS320C64X_FUNIT_L;
54
11.9k
          break;
55
4.23k
        case TMS320C64X_GRP_FUNIT_M:
56
4.23k
          unit = TMS320C64X_FUNIT_M;
57
4.23k
          break;
58
21.2k
        case TMS320C64X_GRP_FUNIT_S:
59
21.2k
          unit = TMS320C64X_FUNIT_S;
60
21.2k
          break;
61
1.60k
        case TMS320C64X_GRP_FUNIT_NO:
62
1.60k
          unit = TMS320C64X_FUNIT_NO;
63
1.60k
          break;
64
57.3k
      }
65
57.3k
      if (unit != 0)
66
57.3k
        break;
67
57.3k
    }
68
57.3k
    tms320c64x->funit.unit = unit;
69
70
57.3k
    SStream_Init(&ss);
71
57.3k
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
72
35.2k
      SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));
73
74
57.3k
    p = strchr(insn_asm, '\t');
75
57.3k
    if (p != NULL)
76
56.0k
      *p++ = '\0';
77
78
57.3k
    SStream_concat0(&ss, insn_asm);
79
57.3k
    if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
80
63.6k
      while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
81
48.6k
        p2--;
82
14.9k
      if (p2 == p) {
83
0
        strcpy(insn_asm, "Invalid!");
84
0
        return;
85
0
      }
86
14.9k
      if (*p2 == 'a')
87
8.49k
        strcpy(tmp, "1T");
88
6.44k
      else
89
6.44k
        strcpy(tmp, "2T");
90
42.3k
    } else {
91
42.3k
      tmp[0] = '\0';
92
42.3k
    }
93
57.3k
    switch(tms320c64x->funit.unit) {
94
18.3k
      case TMS320C64X_FUNIT_D:
95
18.3k
        SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
96
18.3k
        break;
97
11.9k
      case TMS320C64X_FUNIT_L:
98
11.9k
        SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
99
11.9k
        break;
100
4.23k
      case TMS320C64X_FUNIT_M:
101
4.23k
        SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
102
4.23k
        break;
103
21.2k
      case TMS320C64X_FUNIT_S:
104
21.2k
        SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
105
21.2k
        break;
106
57.3k
    }
107
57.3k
    if (tms320c64x->funit.crosspath > 0)
108
13.0k
      SStream_concat0(&ss, "X");
109
110
57.3k
    if (p != NULL)
111
56.0k
      SStream_concat(&ss, "\t%s", p);
112
113
57.3k
    if (tms320c64x->parallel != 0)
114
25.4k
      SStream_concat0(&ss, "\t||");
115
116
    /* insn_asm is a buffer from an SStream, so there should be enough space */
117
57.3k
    strcpy(insn_asm, ss.buffer);
118
57.3k
  }
119
57.3k
}
120
121
#define PRINT_ALIAS_INSTR
122
#include "TMS320C64xGenAsmWriter.inc"
123
124
#define GET_INSTRINFO_ENUM
125
#include "TMS320C64xGenInstrInfo.inc"
126
127
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
128
102k
{
129
102k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
130
102k
  unsigned reg;
131
132
102k
  if (MCOperand_isReg(Op)) {
133
75.4k
    reg = MCOperand_getReg(Op);
134
75.4k
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
135
869
      switch(reg) {
136
220
        case TMS320C64X_REG_EFR:
137
220
          SStream_concat0(O, "EFR");
138
220
          break;
139
333
        case TMS320C64X_REG_IFR:
140
333
          SStream_concat0(O, "IFR");
141
333
          break;
142
316
        default:
143
316
          SStream_concat0(O, getRegisterName(reg));
144
316
          break;
145
869
      }
146
74.6k
    } else {
147
74.6k
      SStream_concat0(O, getRegisterName(reg));
148
74.6k
    }
149
150
75.4k
    if (MI->csh->detail) {
151
75.4k
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
152
75.4k
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
153
75.4k
      MI->flat_insn->detail->tms320c64x.op_count++;
154
75.4k
    }
155
75.4k
  } else if (MCOperand_isImm(Op)) {
156
27.3k
    int64_t Imm = MCOperand_getImm(Op);
157
158
27.3k
    if (Imm >= 0) {
159
22.5k
      if (Imm > HEX_THRESHOLD)
160
13.8k
        SStream_concat(O, "0x%"PRIx64, Imm);
161
8.67k
      else
162
8.67k
        SStream_concat(O, "%"PRIu64, Imm);
163
22.5k
    } else {
164
4.74k
      if (Imm < -HEX_THRESHOLD)
165
3.69k
        SStream_concat(O, "-0x%"PRIx64, -Imm);
166
1.05k
      else
167
1.05k
        SStream_concat(O, "-%"PRIu64, -Imm);
168
4.74k
    }
169
170
27.3k
    if (MI->csh->detail) {
171
27.3k
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
172
27.3k
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
173
27.3k
      MI->flat_insn->detail->tms320c64x.op_count++;
174
27.3k
    }
175
27.3k
  }
176
102k
}
177
178
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
179
8.49k
{
180
8.49k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
181
8.49k
  int64_t Val = MCOperand_getImm(Op);
182
8.49k
  unsigned scaled, base, offset, mode, unit;
183
8.49k
  cs_tms320c64x *tms320c64x;
184
8.49k
  char st, nd;
185
186
8.49k
  scaled = (Val >> 19) & 1;
187
8.49k
  base = (Val >> 12) & 0x7f;
188
8.49k
  offset = (Val >> 5) & 0x7f;
189
8.49k
  mode = (Val >> 1) & 0xf;
190
8.49k
  unit = Val & 1;
191
192
8.49k
  if (scaled) {
193
7.94k
    st = '[';
194
7.94k
    nd = ']';
195
7.94k
  } else {
196
558
    st = '(';
197
558
    nd = ')';
198
558
  }
199
200
8.49k
  switch(mode) {
201
920
    case 0:
202
920
      SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
203
920
      break;
204
588
    case 1:
205
588
      SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
206
588
      break;
207
429
    case 4:
208
429
      SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
209
429
      break;
210
132
    case 5:
211
132
      SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
212
132
      break;
213
411
    case 8:
214
411
      SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
215
411
      break;
216
2.29k
    case 9:
217
2.29k
      SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
218
2.29k
      break;
219
1.32k
    case 10:
220
1.32k
      SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
221
1.32k
      break;
222
1.09k
    case 11:
223
1.09k
      SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
224
1.09k
      break;
225
157
    case 12:
226
157
      SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
227
157
      break;
228
351
    case 13:
229
351
      SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
230
351
      break;
231
395
    case 14:
232
395
      SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
233
395
      break;
234
406
    case 15:
235
406
      SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
236
406
      break;
237
8.49k
  }
238
239
8.49k
  if (MI->csh->detail) {
240
8.49k
    tms320c64x = &MI->flat_insn->detail->tms320c64x;
241
242
8.49k
    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
243
8.49k
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
244
8.49k
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
245
8.49k
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
246
8.49k
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
247
8.49k
    switch(mode) {
248
920
      case 0:
249
920
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
250
920
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
251
920
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
252
920
        break;
253
588
      case 1:
254
588
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
255
588
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
256
588
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
257
588
        break;
258
429
      case 4:
259
429
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
260
429
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
261
429
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
262
429
        break;
263
132
      case 5:
264
132
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
265
132
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
266
132
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
267
132
        break;
268
411
      case 8:
269
411
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
270
411
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
271
411
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
272
411
        break;
273
2.29k
      case 9:
274
2.29k
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
275
2.29k
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
276
2.29k
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
277
2.29k
        break;
278
1.32k
      case 10:
279
1.32k
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
280
1.32k
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
281
1.32k
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
282
1.32k
        break;
283
1.09k
      case 11:
284
1.09k
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
285
1.09k
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
286
1.09k
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
287
1.09k
        break;
288
157
      case 12:
289
157
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
290
157
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
291
157
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
292
157
        break;
293
351
      case 13:
294
351
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
295
351
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
296
351
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
297
351
        break;
298
395
      case 14:
299
395
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
300
395
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
301
395
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
302
395
        break;
303
406
      case 15:
304
406
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
305
406
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
306
406
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
307
406
        break;
308
8.49k
    }
309
8.49k
    tms320c64x->op_count++;
310
8.49k
  }
311
8.49k
}
312
313
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
314
6.44k
{
315
6.44k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
316
6.44k
  int64_t Val = MCOperand_getImm(Op);
317
6.44k
  uint16_t offset;
318
6.44k
  unsigned basereg;
319
6.44k
  cs_tms320c64x *tms320c64x;
320
321
6.44k
  basereg = Val & 0x7f;
322
6.44k
  offset = (Val >> 7) & 0x7fff;
323
6.44k
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
324
325
6.44k
  if (MI->csh->detail) {
326
6.44k
    tms320c64x = &MI->flat_insn->detail->tms320c64x;
327
328
6.44k
    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
329
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
330
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
331
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
332
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
333
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
334
6.44k
    tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
335
6.44k
    tms320c64x->op_count++;
336
6.44k
  }
337
6.44k
}
338
339
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
340
17.7k
{
341
17.7k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
342
17.7k
  unsigned reg = MCOperand_getReg(Op);
343
17.7k
  cs_tms320c64x *tms320c64x;
344
345
17.7k
  SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
346
347
17.7k
  if (MI->csh->detail) {
348
17.7k
    tms320c64x = &MI->flat_insn->detail->tms320c64x;
349
350
17.7k
    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
351
17.7k
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
352
17.7k
    tms320c64x->op_count++;
353
17.7k
  }
354
17.7k
}
355
356
static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
357
57.3k
{
358
57.3k
  unsigned opcode = MCInst_getOpcode(MI);
359
57.3k
  MCOperand *op;
360
361
57.3k
  switch(opcode) {
362
    /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
363
374
    case TMS320C64x_ADD_d2_rir:
364
    /* ADD.L -i, x, y -> SUB.L x, i, y */
365
685
    case TMS320C64x_ADD_l1_irr:
366
1.48k
    case TMS320C64x_ADD_l1_ipp:
367
    /* ADD.S -i, x, y -> SUB.S x, i, y */
368
2.04k
    case TMS320C64x_ADD_s1_irr:
369
2.04k
      if ((MCInst_getNumOperands(MI) == 3) &&
370
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
371
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
372
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
373
2.04k
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
374
375
820
        MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
376
820
        op = MCInst_getOperand(MI, 2);
377
820
        MCOperand_setImm(op, -MCOperand_getImm(op));
378
379
820
        SStream_concat0(O, "SUB\t");
380
820
        printOperand(MI, 1, O);
381
820
        SStream_concat0(O, ", ");
382
820
        printOperand(MI, 2, O);
383
820
        SStream_concat0(O, ", ");
384
820
        printOperand(MI, 0, O);
385
386
820
        return true;
387
820
      }
388
1.22k
      break;
389
57.3k
  }
390
56.5k
  switch(opcode) {
391
    /* ADD.D 0, x, y -> MV.D x, y */
392
347
    case TMS320C64x_ADD_d1_rir:
393
    /* OR.D x, 0, y -> MV.D x, y */
394
613
    case TMS320C64x_OR_d2_rir:
395
    /* ADD.L 0, x, y -> MV.L x, y */
396
874
    case TMS320C64x_ADD_l1_irr:
397
1.27k
    case TMS320C64x_ADD_l1_ipp:
398
    /* OR.L 0, x, y -> MV.L x, y */
399
1.37k
    case TMS320C64x_OR_l1_irr:
400
    /* ADD.S 0, x, y -> MV.S x, y */
401
1.78k
    case TMS320C64x_ADD_s1_irr:
402
    /* OR.S 0, x, y -> MV.S x, y */
403
1.95k
    case TMS320C64x_OR_s1_irr:
404
1.95k
      if ((MCInst_getNumOperands(MI) == 3) &&
405
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
406
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
407
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
408
1.95k
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
409
410
134
        MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
411
134
        MI->size--;
412
413
134
        SStream_concat0(O, "MV\t");
414
134
        printOperand(MI, 1, O);
415
134
        SStream_concat0(O, ", ");
416
134
        printOperand(MI, 0, O);
417
418
134
        return true;
419
134
      }
420
1.82k
      break;
421
56.5k
  }
422
56.3k
  switch(opcode) {
423
    /* XOR.D -1, x, y -> NOT.D x, y */
424
316
    case TMS320C64x_XOR_d2_rir:
425
    /* XOR.L -1, x, y -> NOT.L x, y */
426
509
    case TMS320C64x_XOR_l1_irr:
427
    /* XOR.S -1, x, y -> NOT.S x, y */
428
1.08k
    case TMS320C64x_XOR_s1_irr:
429
1.08k
      if ((MCInst_getNumOperands(MI) == 3) &&
430
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
431
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
432
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
433
1.08k
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
434
435
252
        MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
436
252
        MI->size--;
437
438
252
        SStream_concat0(O, "NOT\t");
439
252
        printOperand(MI, 1, O);
440
252
        SStream_concat0(O, ", ");
441
252
        printOperand(MI, 0, O);
442
443
252
        return true;
444
252
      }
445
834
      break;
446
56.3k
  }
447
56.1k
  switch(opcode) {
448
    /* MVK.D 0, x -> ZERO.D x */
449
463
    case TMS320C64x_MVK_d1_rr:
450
    /* MVK.L 0, x -> ZERO.L x */
451
661
    case TMS320C64x_MVK_l2_ir:
452
661
      if ((MCInst_getNumOperands(MI) == 2) &&
453
661
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
454
661
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
455
661
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
456
457
437
        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
458
437
        MI->size--;
459
460
437
        SStream_concat0(O, "ZERO\t");
461
437
        printOperand(MI, 0, O);
462
463
437
        return true;
464
437
      }
465
224
      break;
466
56.1k
  }
467
55.6k
  switch(opcode) {
468
    /* SUB.L x, x, y -> ZERO.L y */
469
425
    case TMS320C64x_SUB_l1_rrp_x1:
470
    /* SUB.S x, x, y -> ZERO.S y */
471
564
    case TMS320C64x_SUB_s1_rrr:
472
564
      if ((MCInst_getNumOperands(MI) == 3) &&
473
564
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
474
564
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
475
564
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
476
564
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
477
478
240
        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
479
240
        MI->size -= 2;
480
481
240
        SStream_concat0(O, "ZERO\t");
482
240
        printOperand(MI, 0, O);
483
484
240
        return true;
485
240
      }
486
324
      break;
487
55.6k
  }
488
55.4k
  switch(opcode) {
489
    /* SUB.L 0, x, y -> NEG.L x, y */
490
343
    case TMS320C64x_SUB_l1_irr:
491
500
    case TMS320C64x_SUB_l1_ipp:
492
    /* SUB.S 0, x, y -> NEG.S x, y */
493
598
    case TMS320C64x_SUB_s1_irr:
494
598
      if ((MCInst_getNumOperands(MI) == 3) &&
495
598
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
496
598
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
497
598
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
498
598
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
499
500
166
        MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
501
166
        MI->size--;
502
503
166
        SStream_concat0(O, "NEG\t");
504
166
        printOperand(MI, 1, O);
505
166
        SStream_concat0(O, ", ");
506
166
        printOperand(MI, 0, O);
507
508
166
        return true;
509
166
      }
510
432
      break;
511
55.4k
  }
512
55.2k
  switch(opcode) {
513
    /* PACKLH2.L x, x, y -> SWAP2.L x, y */
514
512
    case TMS320C64x_PACKLH2_l1_rrr_x2:
515
    /* PACKLH2.S x, x, y -> SWAP2.S x, y */
516
634
    case TMS320C64x_PACKLH2_s1_rrr:
517
634
      if ((MCInst_getNumOperands(MI) == 3) &&
518
634
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
519
634
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
520
634
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
521
634
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
522
523
122
        MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
524
122
        MI->size--;
525
526
122
        SStream_concat0(O, "SWAP2\t");
527
122
        printOperand(MI, 1, O);
528
122
        SStream_concat0(O, ", ");
529
122
        printOperand(MI, 0, O);
530
531
122
        return true;
532
122
      }
533
512
      break;
534
55.2k
  }
535
55.1k
  switch(opcode) {
536
    /* NOP 16 -> IDLE */
537
    /* NOP 1 -> NOP */
538
1.60k
    case TMS320C64x_NOP_n:
539
1.60k
      if ((MCInst_getNumOperands(MI) == 1) &&
540
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
541
1.60k
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
542
543
215
        MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
544
215
        MI->size--;
545
546
215
        SStream_concat0(O, "IDLE");
547
548
215
        return true;
549
215
      }
550
1.39k
      if ((MCInst_getNumOperands(MI) == 1) &&
551
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
552
1.39k
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
553
554
1.04k
        MI->size--;
555
556
1.04k
        SStream_concat0(O, "NOP");
557
558
1.04k
        return true;
559
1.04k
      }
560
349
      break;
561
55.1k
  }
562
563
53.9k
  return false;
564
55.1k
}
565
566
void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
567
57.3k
{
568
57.3k
  if (!printAliasInstruction(MI, O, Info))
569
53.9k
    printInstruction(MI, O, Info);
570
57.3k
}
571
572
#endif