Coverage Report

Created: 2023-12-08 06:05

/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
72.7k
{
20
72.7k
  static const uint32_t OpInfo[] = {
21
72.7k
    0U, // PHI
22
72.7k
    0U, // INLINEASM
23
72.7k
    0U, // CFI_INSTRUCTION
24
72.7k
    0U, // EH_LABEL
25
72.7k
    0U, // GC_LABEL
26
72.7k
    0U, // KILL
27
72.7k
    0U, // EXTRACT_SUBREG
28
72.7k
    0U, // INSERT_SUBREG
29
72.7k
    0U, // IMPLICIT_DEF
30
72.7k
    0U, // SUBREG_TO_REG
31
72.7k
    0U, // COPY_TO_REGCLASS
32
72.7k
    2452U,  // DBG_VALUE
33
72.7k
    0U, // REG_SEQUENCE
34
72.7k
    0U, // COPY
35
72.7k
    2445U,  // BUNDLE
36
72.7k
    2462U,  // LIFETIME_START
37
72.7k
    2432U,  // LIFETIME_END
38
72.7k
    0U, // STACKMAP
39
72.7k
    0U, // PATCHPOINT
40
72.7k
    0U, // LOAD_STACK_GUARD
41
72.7k
    0U, // STATEPOINT
42
72.7k
    0U, // FRAME_ALLOC
43
72.7k
    4688U,  // ADDCCri
44
72.7k
    4688U,  // ADDCCrr
45
72.7k
    5925U,  // ADDCri
46
72.7k
    5925U,  // ADDCrr
47
72.7k
    4772U,  // ADDEri
48
72.7k
    4772U,  // ADDErr
49
72.7k
    4786U,  // ADDXC
50
72.7k
    4678U,  // ADDXCCC
51
72.7k
    4808U,  // ADDXri
52
72.7k
    4808U,  // ADDXrr
53
72.7k
    4808U,  // ADDri
54
72.7k
    4808U,  // ADDrr
55
72.7k
    74166U, // ADJCALLSTACKDOWN
56
72.7k
    74185U, // ADJCALLSTACKUP
57
72.7k
    5497U,  // ALIGNADDR
58
72.7k
    5127U,  // ALIGNADDRL
59
72.7k
    4695U,  // ANDCCri
60
72.7k
    4695U,  // ANDCCrr
61
72.7k
    4718U,  // ANDNCCri
62
72.7k
    4718U,  // ANDNCCrr
63
72.7k
    5182U,  // ANDNri
64
72.7k
    5182U,  // ANDNrr
65
72.7k
    5182U,  // ANDXNrr
66
72.7k
    4876U,  // ANDXri
67
72.7k
    4876U,  // ANDXrr
68
72.7k
    4876U,  // ANDri
69
72.7k
    4876U,  // ANDrr
70
72.7k
    4502U,  // ARRAY16
71
72.7k
    4255U,  // ARRAY32
72
72.7k
    4526U,  // ARRAY8
73
72.7k
    0U, // ATOMIC_LOAD_ADD_32
74
72.7k
    0U, // ATOMIC_LOAD_ADD_64
75
72.7k
    0U, // ATOMIC_LOAD_AND_32
76
72.7k
    0U, // ATOMIC_LOAD_AND_64
77
72.7k
    0U, // ATOMIC_LOAD_MAX_32
78
72.7k
    0U, // ATOMIC_LOAD_MAX_64
79
72.7k
    0U, // ATOMIC_LOAD_MIN_32
80
72.7k
    0U, // ATOMIC_LOAD_MIN_64
81
72.7k
    0U, // ATOMIC_LOAD_NAND_32
82
72.7k
    0U, // ATOMIC_LOAD_NAND_64
83
72.7k
    0U, // ATOMIC_LOAD_OR_32
84
72.7k
    0U, // ATOMIC_LOAD_OR_64
85
72.7k
    0U, // ATOMIC_LOAD_SUB_32
86
72.7k
    0U, // ATOMIC_LOAD_SUB_64
87
72.7k
    0U, // ATOMIC_LOAD_UMAX_32
88
72.7k
    0U, // ATOMIC_LOAD_UMAX_64
89
72.7k
    0U, // ATOMIC_LOAD_UMIN_32
90
72.7k
    0U, // ATOMIC_LOAD_UMIN_64
91
72.7k
    0U, // ATOMIC_LOAD_XOR_32
92
72.7k
    0U, // ATOMIC_LOAD_XOR_64
93
72.7k
    0U, // ATOMIC_SWAP_64
94
72.7k
    74271U, // BA
95
72.7k
    1194492U, // BCOND
96
72.7k
    1260028U, // BCONDA
97
72.7k
    17659U, // BINDri
98
72.7k
    17659U, // BINDrr
99
72.7k
    5065U,  // BMASK
100
72.7k
    145915U,  // BPFCC
101
72.7k
    211451U,  // BPFCCA
102
72.7k
    276987U,  // BPFCCANT
103
72.7k
    342523U,  // BPFCCNT
104
72.7k
    2106465U, // BPGEZapn
105
72.7k
    2105838U, // BPGEZapt
106
72.7k
    2106532U, // BPGEZnapn
107
72.7k
    2107288U, // BPGEZnapt
108
72.7k
    2106489U, // BPGZapn
109
72.7k
    2105856U, // BPGZapt
110
72.7k
    2106552U, // BPGZnapn
111
72.7k
    2107384U, // BPGZnapt
112
72.7k
    1456636U, // BPICC
113
72.7k
    473596U,  // BPICCA
114
72.7k
    539132U,  // BPICCANT
115
72.7k
    604668U,  // BPICCNT
116
72.7k
    2106477U, // BPLEZapn
117
72.7k
    2105847U, // BPLEZapt
118
72.7k
    2106542U, // BPLEZnapn
119
72.7k
    2107337U, // BPLEZnapt
120
72.7k
    2106500U, // BPLZapn
121
72.7k
    2105864U, // BPLZapt
122
72.7k
    2106561U, // BPLZnapn
123
72.7k
    2107428U, // BPLZnapt
124
72.7k
    2106511U, // BPNZapn
125
72.7k
    2105872U, // BPNZapt
126
72.7k
    2106570U, // BPNZnapn
127
72.7k
    2107472U, // BPNZnapt
128
72.7k
    1718780U, // BPXCC
129
72.7k
    735740U,  // BPXCCA
130
72.7k
    801276U,  // BPXCCANT
131
72.7k
    866812U,  // BPXCCNT
132
72.7k
    2106522U, // BPZapn
133
72.7k
    2105880U, // BPZapt
134
72.7k
    2106579U, // BPZnapn
135
72.7k
    2107505U, // BPZnapt
136
72.7k
    4983U,  // BSHUFFLE
137
72.7k
    74742U, // CALL
138
72.7k
    17398U, // CALLri
139
72.7k
    17398U, // CALLrr
140
72.7k
    924148U,  // CASXrr
141
72.7k
    924129U,  // CASrr
142
72.7k
    74001U, // CMASK16
143
72.7k
    73833U, // CMASK32
144
72.7k
    74150U, // CMASK8
145
72.7k
    2106607U, // CMPri
146
72.7k
    2106607U, // CMPrr
147
72.7k
    4332U,  // EDGE16
148
72.7k
    5081U,  // EDGE16L
149
72.7k
    5198U,  // EDGE16LN
150
72.7k
    5165U,  // EDGE16N
151
72.7k
    4164U,  // EDGE32
152
72.7k
    5072U,  // EDGE32L
153
72.7k
    5188U,  // EDGE32LN
154
72.7k
    5156U,  // EDGE32N
155
72.7k
    4511U,  // EDGE8
156
72.7k
    5090U,  // EDGE8L
157
72.7k
    5208U,  // EDGE8LN
158
72.7k
    5174U,  // EDGE8N
159
72.7k
    1053516U, // FABSD
160
72.7k
    1054031U, // FABSQ
161
72.7k
    1054376U, // FABSS
162
72.7k
    4813U,  // FADDD
163
72.7k
    5383U,  // FADDQ
164
72.7k
    5645U,  // FADDS
165
72.7k
    4648U,  // FALIGNADATA
166
72.7k
    4875U,  // FAND
167
72.7k
    4112U,  // FANDNOT1
168
72.7k
    5544U,  // FANDNOT1S
169
72.7k
    4271U,  // FANDNOT2
170
72.7k
    5591U,  // FANDNOT2S
171
72.7k
    5677U,  // FANDS
172
72.7k
    1194491U, // FBCOND
173
72.7k
    1260027U, // FBCONDA
174
72.7k
    4394U,  // FCHKSM16
175
72.7k
    2106173U, // FCMPD
176
72.7k
    4413U,  // FCMPEQ16
177
72.7k
    4226U,  // FCMPEQ32
178
72.7k
    4432U,  // FCMPGT16
179
72.7k
    4245U,  // FCMPGT32
180
72.7k
    4340U,  // FCMPLE16
181
72.7k
    4172U,  // FCMPLE32
182
72.7k
    4350U,  // FCMPNE16
183
72.7k
    4182U,  // FCMPNE32
184
72.7k
    2106696U, // FCMPQ
185
72.7k
    2107005U, // FCMPS
186
72.7k
    4960U,  // FDIVD
187
72.7k
    5475U,  // FDIVQ
188
72.7k
    5815U,  // FDIVS
189
72.7k
    5405U,  // FDMULQ
190
72.7k
    1053620U, // FDTOI
191
72.7k
    1053996U, // FDTOQ
192
72.7k
    1054305U, // FDTOS
193
72.7k
    1054536U, // FDTOX
194
72.7k
    1053464U, // FEXPAND
195
72.7k
    4820U,  // FHADDD
196
72.7k
    5652U,  // FHADDS
197
72.7k
    4800U,  // FHSUBD
198
72.7k
    5637U,  // FHSUBS
199
72.7k
    1053473U, // FITOD
200
72.7k
    1054003U, // FITOQ
201
72.7k
    1054312U, // FITOS
202
72.7k
    6300484U, // FLCMPD
203
72.7k
    6301316U, // FLCMPS
204
72.7k
    2606U,  // FLUSHW
205
72.7k
    4404U,  // FMEAN16
206
72.7k
    1053543U, // FMOVD
207
72.7k
    1006078U, // FMOVD_FCC
208
72.7k
    23484926U,  // FMOVD_ICC
209
72.7k
    23747070U,  // FMOVD_XCC
210
72.7k
    1054058U, // FMOVQ
211
72.7k
    1006102U, // FMOVQ_FCC
212
72.7k
    23484950U,  // FMOVQ_ICC
213
72.7k
    23747094U,  // FMOVQ_XCC
214
72.7k
    6018U,  // FMOVRGEZD
215
72.7k
    6029U,  // FMOVRGEZQ
216
72.7k
    6056U,  // FMOVRGEZS
217
72.7k
    6116U,  // FMOVRGZD
218
72.7k
    6126U,  // FMOVRGZQ
219
72.7k
    6150U,  // FMOVRGZS
220
72.7k
    6067U,  // FMOVRLEZD
221
72.7k
    6078U,  // FMOVRLEZQ
222
72.7k
    6105U,  // FMOVRLEZS
223
72.7k
    6160U,  // FMOVRLZD
224
72.7k
    6170U,  // FMOVRLZQ
225
72.7k
    6194U,  // FMOVRLZS
226
72.7k
    6204U,  // FMOVRNZD
227
72.7k
    6214U,  // FMOVRNZQ
228
72.7k
    6238U,  // FMOVRNZS
229
72.7k
    6009U,  // FMOVRZD
230
72.7k
    6248U,  // FMOVRZQ
231
72.7k
    6269U,  // FMOVRZS
232
72.7k
    1054398U, // FMOVS
233
72.7k
    1006114U, // FMOVS_FCC
234
72.7k
    23484962U,  // FMOVS_ICC
235
72.7k
    23747106U,  // FMOVS_XCC
236
72.7k
    4490U,  // FMUL8SUX16
237
72.7k
    4465U,  // FMUL8ULX16
238
72.7k
    4442U,  // FMUL8X16
239
72.7k
    5098U,  // FMUL8X16AL
240
72.7k
    5849U,  // FMUL8X16AU
241
72.7k
    4860U,  // FMULD
242
72.7k
    4477U,  // FMULD8SUX16
243
72.7k
    4452U,  // FMULD8ULX16
244
72.7k
    5413U,  // FMULQ
245
72.7k
    5714U,  // FMULS
246
72.7k
    4837U,  // FNADDD
247
72.7k
    5669U,  // FNADDS
248
72.7k
    4881U,  // FNAND
249
72.7k
    5684U,  // FNANDS
250
72.7k
    1053429U, // FNEGD
251
72.7k
    1053974U, // FNEGQ
252
72.7k
    1054283U, // FNEGS
253
72.7k
    4828U,  // FNHADDD
254
72.7k
    5660U,  // FNHADDS
255
72.7k
    4828U,  // FNMULD
256
72.7k
    5660U,  // FNMULS
257
72.7k
    5513U,  // FNOR
258
72.7k
    5778U,  // FNORS
259
72.7k
    1052698U, // FNOT1
260
72.7k
    1054131U, // FNOT1S
261
72.7k
    1052857U, // FNOT2
262
72.7k
    1054178U, // FNOT2S
263
72.7k
    5660U,  // FNSMULD
264
72.7k
    74625U, // FONE
265
72.7k
    75324U, // FONES
266
72.7k
    5508U,  // FOR
267
72.7k
    4129U,  // FORNOT1
268
72.7k
    5563U,  // FORNOT1S
269
72.7k
    4288U,  // FORNOT2
270
72.7k
    5610U,  // FORNOT2S
271
72.7k
    5772U,  // FORS
272
72.7k
    1052936U, // FPACK16
273
72.7k
    4192U,  // FPACK32
274
72.7k
    1054507U, // FPACKFIX
275
72.7k
    4323U,  // FPADD16
276
72.7k
    5620U,  // FPADD16S
277
72.7k
    4155U,  // FPADD32
278
72.7k
    5573U,  // FPADD32S
279
72.7k
    4297U,  // FPADD64
280
72.7k
    4974U,  // FPMERGE
281
72.7k
    4314U,  // FPSUB16
282
72.7k
    4580U,  // FPSUB16S
283
72.7k
    4146U,  // FPSUB32
284
72.7k
    4570U,  // FPSUB32S
285
72.7k
    1053480U, // FQTOD
286
72.7k
    1053627U, // FQTOI
287
72.7k
    1054319U, // FQTOS
288
72.7k
    1054552U, // FQTOX
289
72.7k
    4423U,  // FSLAS16
290
72.7k
    4236U,  // FSLAS32
291
72.7k
    4378U,  // FSLL16
292
72.7k
    4210U,  // FSLL32
293
72.7k
    4867U,  // FSMULD
294
72.7k
    1053523U, // FSQRTD
295
72.7k
    1054038U, // FSQRTQ
296
72.7k
    1054383U, // FSQRTS
297
72.7k
    4306U,  // FSRA16
298
72.7k
    4138U,  // FSRA32
299
72.7k
    1052681U, // FSRC1
300
72.7k
    1054112U, // FSRC1S
301
72.7k
    1052840U, // FSRC2
302
72.7k
    1054159U, // FSRC2S
303
72.7k
    4386U,  // FSRL16
304
72.7k
    4218U,  // FSRL32
305
72.7k
    1053487U, // FSTOD
306
72.7k
    1053634U, // FSTOI
307
72.7k
    1054010U, // FSTOQ
308
72.7k
    1054559U, // FSTOX
309
72.7k
    4793U,  // FSUBD
310
72.7k
    5376U,  // FSUBQ
311
72.7k
    5630U,  // FSUBS
312
72.7k
    5519U,  // FXNOR
313
72.7k
    5785U,  // FXNORS
314
72.7k
    5526U,  // FXOR
315
72.7k
    5793U,  // FXORS
316
72.7k
    1053494U, // FXTOD
317
72.7k
    1054017U, // FXTOQ
318
72.7k
    1054326U, // FXTOS
319
72.7k
    74984U, // FZERO
320
72.7k
    75353U, // FZEROS
321
72.7k
    24584U, // GETPCX
322
72.7k
    1078273U, // JMPLri
323
72.7k
    1078273U, // JMPLrr
324
72.7k
    1997243U, // LDDFri
325
72.7k
    1997243U, // LDDFrr
326
72.7k
    1997249U, // LDFri
327
72.7k
    1997249U, // LDFrr
328
72.7k
    1997275U, // LDQFri
329
72.7k
    1997275U, // LDQFrr
330
72.7k
    1997229U, // LDSBri
331
72.7k
    1997229U, // LDSBrr
332
72.7k
    1997254U, // LDSHri
333
72.7k
    1997254U, // LDSHrr
334
72.7k
    1997287U, // LDSWri
335
72.7k
    1997287U, // LDSWrr
336
72.7k
    1997236U, // LDUBri
337
72.7k
    1997236U, // LDUBrr
338
72.7k
    1997261U, // LDUHri
339
72.7k
    1997261U, // LDUHrr
340
72.7k
    1997294U, // LDXri
341
72.7k
    1997294U, // LDXrr
342
72.7k
    1997249U, // LDri
343
72.7k
    1997249U, // LDrr
344
72.7k
    33480U, // LEAX_ADDri
345
72.7k
    33480U, // LEA_ADDri
346
72.7k
    1054405U, // LZCNT
347
72.7k
    75121U, // MEMBARi
348
72.7k
    1054543U, // MOVDTOX
349
72.7k
    1006122U, // MOVFCCri
350
72.7k
    1006122U, // MOVFCCrr
351
72.7k
    23484970U,  // MOVICCri
352
72.7k
    23484970U,  // MOVICCrr
353
72.7k
    6047U,  // MOVRGEZri
354
72.7k
    6047U,  // MOVRGEZrr
355
72.7k
    6142U,  // MOVRGZri
356
72.7k
    6142U,  // MOVRGZrr
357
72.7k
    6096U,  // MOVRLEZri
358
72.7k
    6096U,  // MOVRLEZrr
359
72.7k
    6186U,  // MOVRLZri
360
72.7k
    6186U,  // MOVRLZrr
361
72.7k
    6230U,  // MOVRNZri
362
72.7k
    6230U,  // MOVRNZrr
363
72.7k
    6262U,  // MOVRRZri
364
72.7k
    6262U,  // MOVRRZrr
365
72.7k
    1054469U, // MOVSTOSW
366
72.7k
    1054479U, // MOVSTOUW
367
72.7k
    1054543U, // MOVWTOS
368
72.7k
    23747114U,  // MOVXCCri
369
72.7k
    23747114U,  // MOVXCCrr
370
72.7k
    1054543U, // MOVXTOD
371
72.7k
    5954U,  // MULXri
372
72.7k
    5954U,  // MULXrr
373
72.7k
    2578U,  // NOP
374
72.7k
    4735U,  // ORCCri
375
72.7k
    4735U,  // ORCCrr
376
72.7k
    4726U,  // ORNCCri
377
72.7k
    4726U,  // ORNCCrr
378
72.7k
    5339U,  // ORNri
379
72.7k
    5339U,  // ORNrr
380
72.7k
    5339U,  // ORXNrr
381
72.7k
    5509U,  // ORXri
382
72.7k
    5509U,  // ORXrr
383
72.7k
    5509U,  // ORri
384
72.7k
    5509U,  // ORrr
385
72.7k
    5836U,  // PDIST
386
72.7k
    5344U,  // PDISTN
387
72.7k
    1053356U, // POPCrr
388
72.7k
    73729U, // RDY
389
72.7k
    4999U,  // RESTOREri
390
72.7k
    4999U,  // RESTORErr
391
72.7k
    76132U, // RET
392
72.7k
    76141U, // RETL
393
72.7k
    18131U, // RETTri
394
72.7k
    18131U, // RETTrr
395
72.7k
    5008U,  // SAVEri
396
72.7k
    5008U,  // SAVErr
397
72.7k
    4748U,  // SDIVCCri
398
72.7k
    4748U,  // SDIVCCrr
399
72.7k
    5995U,  // SDIVXri
400
72.7k
    5995U,  // SDIVXrr
401
72.7k
    5861U,  // SDIVri
402
72.7k
    5861U,  // SDIVrr
403
72.7k
    2182U,  // SELECT_CC_DFP_FCC
404
72.7k
    2293U,  // SELECT_CC_DFP_ICC
405
72.7k
    2238U,  // SELECT_CC_FP_FCC
406
72.7k
    2349U,  // SELECT_CC_FP_ICC
407
72.7k
    2265U,  // SELECT_CC_Int_FCC
408
72.7k
    2376U,  // SELECT_CC_Int_ICC
409
72.7k
    2210U,  // SELECT_CC_QFP_FCC
410
72.7k
    2321U,  // SELECT_CC_QFP_ICC
411
72.7k
    1053595U, // SETHIXi
412
72.7k
    1053595U, // SETHIi
413
72.7k
    2569U,  // SHUTDOWN
414
72.7k
    2564U,  // SIAM
415
72.7k
    5941U,  // SLLXri
416
72.7k
    5941U,  // SLLXrr
417
72.7k
    5116U,  // SLLri
418
72.7k
    5116U,  // SLLrr
419
72.7k
    4702U,  // SMULCCri
420
72.7k
    4702U,  // SMULCCrr
421
72.7k
    5144U,  // SMULri
422
72.7k
    5144U,  // SMULrr
423
72.7k
    5913U,  // SRAXri
424
72.7k
    5913U,  // SRAXrr
425
72.7k
    4643U,  // SRAri
426
72.7k
    4643U,  // SRArr
427
72.7k
    5947U,  // SRLXri
428
72.7k
    5947U,  // SRLXrr
429
72.7k
    5139U,  // SRLri
430
72.7k
    5139U,  // SRLrr
431
72.7k
    2588U,  // STBAR
432
72.7k
    37428U, // STBri
433
72.7k
    37428U, // STBrr
434
72.7k
    37723U, // STDFri
435
72.7k
    37723U, // STDFrr
436
72.7k
    38607U, // STFri
437
72.7k
    38607U, // STFrr
438
72.7k
    37782U, // STHri
439
72.7k
    37782U, // STHrr
440
72.7k
    38238U, // STQFri
441
72.7k
    38238U, // STQFrr
442
72.7k
    38758U, // STXri
443
72.7k
    38758U, // STXrr
444
72.7k
    38607U, // STri
445
72.7k
    38607U, // STrr
446
72.7k
    4671U,  // SUBCCri
447
72.7k
    4671U,  // SUBCCrr
448
72.7k
    5919U,  // SUBCri
449
72.7k
    5919U,  // SUBCrr
450
72.7k
    4764U,  // SUBEri
451
72.7k
    4764U,  // SUBErr
452
72.7k
    4665U,  // SUBXri
453
72.7k
    4665U,  // SUBXrr
454
72.7k
    4665U,  // SUBri
455
72.7k
    4665U,  // SUBrr
456
72.7k
    1997268U, // SWAPri
457
72.7k
    1997268U, // SWAPrr
458
72.7k
    2422U,  // TA3
459
72.7k
    2427U,  // TA5
460
72.7k
    5883U,  // TADDCCTVri
461
72.7k
    5883U,  // TADDCCTVrr
462
72.7k
    4687U,  // TADDCCri
463
72.7k
    4687U,  // TADDCCrr
464
72.7k
    9873960U, // TICCri
465
72.7k
    9873960U, // TICCrr
466
72.7k
    37753544U,  // TLS_ADDXrr
467
72.7k
    37753544U,  // TLS_ADDrr
468
72.7k
    2106358U, // TLS_CALL
469
72.7k
    39746030U,  // TLS_LDXrr
470
72.7k
    39745985U,  // TLS_LDrr
471
72.7k
    5873U,  // TSUBCCTVri
472
72.7k
    5873U,  // TSUBCCTVrr
473
72.7k
    4670U,  // TSUBCCri
474
72.7k
    4670U,  // TSUBCCrr
475
72.7k
    10136104U,  // TXCCri
476
72.7k
    10136104U,  // TXCCrr
477
72.7k
    4756U,  // UDIVCCri
478
72.7k
    4756U,  // UDIVCCrr
479
72.7k
    6002U,  // UDIVXri
480
72.7k
    6002U,  // UDIVXrr
481
72.7k
    5867U,  // UDIVri
482
72.7k
    5867U,  // UDIVrr
483
72.7k
    4710U,  // UMULCCri
484
72.7k
    4710U,  // UMULCCrr
485
72.7k
    5026U,  // UMULXHI
486
72.7k
    5150U,  // UMULri
487
72.7k
    5150U,  // UMULrr
488
72.7k
    74996U, // UNIMP
489
72.7k
    6300477U, // V9FCMPD
490
72.7k
    6300397U, // V9FCMPED
491
72.7k
    6300942U, // V9FCMPEQ
492
72.7k
    6301251U, // V9FCMPES
493
72.7k
    6301000U, // V9FCMPQ
494
72.7k
    6301309U, // V9FCMPS
495
72.7k
    47614U, // V9FMOVD_FCC
496
72.7k
    47638U, // V9FMOVQ_FCC
497
72.7k
    47650U, // V9FMOVS_FCC
498
72.7k
    47658U, // V9MOVFCCri
499
72.7k
    47658U, // V9MOVFCCrr
500
72.7k
    14689692U,  // WRYri
501
72.7k
    14689692U,  // WRYrr
502
72.7k
    5953U,  // XMULX
503
72.7k
    5035U,  // XMULXHI
504
72.7k
    4733U,  // XNORCCri
505
72.7k
    4733U,  // XNORCCrr
506
72.7k
    5520U,  // XNORXrr
507
72.7k
    5520U,  // XNORri
508
72.7k
    5520U,  // XNORrr
509
72.7k
    4741U,  // XORCCri
510
72.7k
    4741U,  // XORCCrr
511
72.7k
    5527U,  // XORXri
512
72.7k
    5527U,  // XORXrr
513
72.7k
    5527U,  // XORri
514
72.7k
    5527U,  // XORrr
515
72.7k
    0U
516
72.7k
  };
517
518
72.7k
#ifndef CAPSTONE_DIET
519
72.7k
  static const char AsmStrs[] = {
520
72.7k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
72.7k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
72.7k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
72.7k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
72.7k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
72.7k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
72.7k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
72.7k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
72.7k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
72.7k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
72.7k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
72.7k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
72.7k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
72.7k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
72.7k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
72.7k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
72.7k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
72.7k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
72.7k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
72.7k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
72.7k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
72.7k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
72.7k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
72.7k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
72.7k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
72.7k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
72.7k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
72.7k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
72.7k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
72.7k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
72.7k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
72.7k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
72.7k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
72.7k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
72.7k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
72.7k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
72.7k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
72.7k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
72.7k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
72.7k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
72.7k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
72.7k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
72.7k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
72.7k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
72.7k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
72.7k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
72.7k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
72.7k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
72.7k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
72.7k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
72.7k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
72.7k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
72.7k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
72.7k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
72.7k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
72.7k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
72.7k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
72.7k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
72.7k
  /* 542 */ 'b', 'a', 32, 0,
579
72.7k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
72.7k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
72.7k
  /* 563 */ 's', 't', 'b', 32, 0,
582
72.7k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
72.7k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
72.7k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
72.7k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
72.7k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
72.7k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
72.7k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
72.7k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
72.7k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
72.7k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
72.7k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
72.7k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
72.7k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
72.7k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
72.7k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
72.7k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
72.7k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
72.7k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
72.7k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
72.7k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
72.7k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
72.7k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
72.7k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
72.7k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
72.7k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
72.7k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
72.7k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
72.7k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
72.7k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
72.7k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
72.7k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
72.7k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
72.7k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
72.7k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
72.7k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
72.7k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
72.7k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
72.7k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
72.7k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
72.7k
  /* 858 */ 's', 't', 'd', 32, 0,
622
72.7k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
72.7k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
72.7k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
72.7k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
72.7k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
72.7k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
72.7k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
72.7k
  /* 917 */ 's', 't', 'h', 32, 0,
630
72.7k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
72.7k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
72.7k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
72.7k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
72.7k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
72.7k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
72.7k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
72.7k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
72.7k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
72.7k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
72.7k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
72.7k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
72.7k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
72.7k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
72.7k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
72.7k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
72.7k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
72.7k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
72.7k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
72.7k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
72.7k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
72.7k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
72.7k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
72.7k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
72.7k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
72.7k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
72.7k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
72.7k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
72.7k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
72.7k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
72.7k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
72.7k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
72.7k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
72.7k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
72.7k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
72.7k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
72.7k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
72.7k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
72.7k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
72.7k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
72.7k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
72.7k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
72.7k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
72.7k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
72.7k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
72.7k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
72.7k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
72.7k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
72.7k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
72.7k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
72.7k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
72.7k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
72.7k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
72.7k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
72.7k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
72.7k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
72.7k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
72.7k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
72.7k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
72.7k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
72.7k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
72.7k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
72.7k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
72.7k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
72.7k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
72.7k
  /* 1435 */ 'w', 'r', 32, 0,
696
72.7k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
72.7k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
72.7k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
72.7k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
72.7k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
72.7k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
72.7k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
72.7k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
72.7k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
72.7k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
72.7k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
72.7k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
72.7k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
72.7k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
72.7k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
72.7k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
72.7k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
72.7k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
72.7k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
72.7k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
72.7k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
72.7k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
72.7k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
72.7k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
72.7k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
72.7k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
72.7k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
72.7k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
72.7k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
72.7k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
72.7k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
72.7k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
72.7k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
72.7k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
72.7k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
72.7k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
72.7k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
72.7k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
72.7k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
72.7k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
72.7k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
72.7k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
72.7k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
72.7k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
72.7k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
72.7k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
72.7k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
72.7k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
72.7k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
72.7k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
72.7k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
72.7k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
72.7k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
72.7k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
72.7k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
72.7k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
72.7k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
72.7k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
72.7k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
72.7k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
72.7k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
72.7k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
72.7k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
72.7k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
72.7k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
72.7k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
72.7k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
72.7k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
72.7k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
72.7k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
72.7k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
72.7k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
72.7k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
72.7k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
72.7k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
72.7k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
72.7k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
72.7k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
72.7k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
72.7k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
72.7k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
72.7k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
72.7k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
72.7k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
72.7k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
72.7k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
72.7k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
72.7k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
72.7k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
72.7k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
72.7k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
72.7k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
72.7k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
72.7k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
72.7k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
72.7k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
72.7k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
72.7k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
72.7k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
72.7k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
72.7k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
72.7k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
72.7k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
72.7k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
72.7k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
72.7k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
72.7k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
72.7k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
72.7k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
72.7k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
72.7k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
72.7k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
72.7k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
72.7k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
72.7k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
72.7k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
72.7k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
72.7k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
72.7k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
72.7k
  /* 2554 */ 'f', 'b', 0,
816
72.7k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
72.7k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
72.7k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
72.7k
  /* 2577 */ 'n', 'o', 'p', 0,
820
72.7k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
72.7k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
72.7k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
72.7k
  /* 2599 */ 't', 0,
824
72.7k
  /* 2601 */ 'm', 'o', 'v', 0,
825
72.7k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
72.7k
  };
827
72.7k
#endif
828
829
  // Emit the opcode for the instruction.
830
72.7k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
72.7k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
72.7k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
72.7k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
72.7k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
162
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
162
    return;
844
0
    break;
845
15.3k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
15.3k
    printOperand(MI, 1, O); 
848
15.3k
    break;
849
43.5k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
43.5k
    printOperand(MI, 0, O); 
852
43.5k
    break;
853
5.37k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
5.37k
    printCCOperand(MI, 1, O); 
856
5.37k
    break;
857
185
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
185
    printMemOperand(MI, 0, O, NULL); 
860
185
    return;
861
0
    break;
862
1.65k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
1.65k
    printCCOperand(MI, 3, O); 
865
1.65k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
3.45k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
3.45k
    printMemOperand(MI, 1, O, NULL); 
874
3.45k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.40k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.40k
    printOperand(MI, 2, O); 
885
1.40k
    SStream_concat0(O, ", ["); 
886
1.40k
    printMemOperand(MI, 0, O, NULL); 
887
1.40k
    SStream_concat0(O, "]"); 
888
1.40k
    return;
889
0
    break;
890
93
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
93
    printCCOperand(MI, 2, O); 
893
93
    break;
894
1.61k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.61k
    printCCOperand(MI, 4, O); 
897
1.61k
    SStream_concat0(O, " "); 
898
1.61k
    printOperand(MI, 1, O); 
899
1.61k
    SStream_concat0(O, ", "); 
900
1.61k
    printOperand(MI, 2, O); 
901
1.61k
    SStream_concat0(O, ", "); 
902
1.61k
    printOperand(MI, 0, O); 
903
1.61k
    return;
904
0
    break;
905
72.7k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
69.4k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
22.5k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
22.5k
    SStream_concat0(O, ", "); 
915
22.5k
    break;
916
36.4k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
36.4k
    return;
919
0
    break;
920
1.28k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.28k
    SStream_concat0(O, " "); 
923
1.28k
    break;
924
1.98k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.98k
    SStream_concat0(O, ",a ");
927
1.98k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.98k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.37k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.37k
    SStream_concat0(O, " %icc, ");
950
1.37k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.37k
    break;
952
309
  case 7:
953
    // BPICCA
954
309
    SStream_concat0(O, ",a %icc, ");
955
309
  Sparc_add_hint(MI, SPARC_HINT_A);
956
309
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
309
    printOperand(MI, 0, O); 
958
309
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.48k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.48k
    SStream_concat0(O, " %xcc, ");
979
1.48k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.48k
    break;
981
214
  case 11:
982
    // BPXCCA
983
214
    SStream_concat0(O, ",a %xcc, ");
984
214
  Sparc_add_hint(MI, SPARC_HINT_A);
985
214
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
214
    printOperand(MI, 0, O); 
987
214
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
3.39k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
3.39k
    SStream_concat0(O, "], "); 
1008
3.39k
    break;
1009
461
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
461
    SStream_concat0(O, " %fcc0, ");
1012
461
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
461
    printOperand(MI, 1, O); 
1014
461
    SStream_concat0(O, ", "); 
1015
461
    printOperand(MI, 0, O); 
1016
461
    return;
1017
0
    break;
1018
69.4k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
32.0k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
8.53k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
8.53k
    printOperand(MI, 2, O); 
1028
8.53k
    SStream_concat0(O, ", "); 
1029
8.53k
    printOperand(MI, 0, O); 
1030
8.53k
    break;
1031
15.2k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
15.2k
    printOperand(MI, 0, O); 
1034
15.2k
    break;
1035
8.29k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
8.29k
    printOperand(MI, 1, O); 
1038
8.29k
    break;
1039
32.0k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
32.0k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
28.1k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
28.1k
    return;
1049
0
    break;
1050
3.74k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
3.74k
    SStream_concat0(O, ", "); 
1053
3.74k
    break;
1054
93
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
93
    SStream_concat0(O, " + ");  // qq
1057
93
    printOperand(MI, 1, O); 
1058
93
    return;
1059
0
    break;
1060
83
  case 3:
1061
    // WRYri, WRYrr
1062
83
    SStream_concat0(O, ", %y");
1063
83
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
83
    return;
1065
0
    break;
1066
32.0k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
3.74k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
2.55k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
2.55k
    printOperand(MI, 2, O); 
1076
2.55k
    return;
1077
0
    break;
1078
1.19k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.19k
    printOperand(MI, 0, O); 
1081
1.19k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
3.74k
  }
1089
3.74k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
81.0k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
81.0k
#ifndef CAPSTONE_DIET
1100
81.0k
  static const char AsmStrs[] = {
1101
81.0k
  /* 0 */ 'f', '1', '0', 0,
1102
81.0k
  /* 4 */ 'f', '2', '0', 0,
1103
81.0k
  /* 8 */ 'f', '3', '0', 0,
1104
81.0k
  /* 12 */ 'f', '4', '0', 0,
1105
81.0k
  /* 16 */ 'f', '5', '0', 0,
1106
81.0k
  /* 20 */ 'f', '6', '0', 0,
1107
81.0k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
81.0k
  /* 29 */ 'f', '0', 0,
1109
81.0k
  /* 32 */ 'g', '0', 0,
1110
81.0k
  /* 35 */ 'i', '0', 0,
1111
81.0k
  /* 38 */ 'l', '0', 0,
1112
81.0k
  /* 41 */ 'o', '0', 0,
1113
81.0k
  /* 44 */ 'f', '1', '1', 0,
1114
81.0k
  /* 48 */ 'f', '2', '1', 0,
1115
81.0k
  /* 52 */ 'f', '3', '1', 0,
1116
81.0k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
81.0k
  /* 61 */ 'f', '1', 0,
1118
81.0k
  /* 64 */ 'g', '1', 0,
1119
81.0k
  /* 67 */ 'i', '1', 0,
1120
81.0k
  /* 70 */ 'l', '1', 0,
1121
81.0k
  /* 73 */ 'o', '1', 0,
1122
81.0k
  /* 76 */ 'f', '1', '2', 0,
1123
81.0k
  /* 80 */ 'f', '2', '2', 0,
1124
81.0k
  /* 84 */ 'f', '3', '2', 0,
1125
81.0k
  /* 88 */ 'f', '4', '2', 0,
1126
81.0k
  /* 92 */ 'f', '5', '2', 0,
1127
81.0k
  /* 96 */ 'f', '6', '2', 0,
1128
81.0k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
81.0k
  /* 105 */ 'f', '2', 0,
1130
81.0k
  /* 108 */ 'g', '2', 0,
1131
81.0k
  /* 111 */ 'i', '2', 0,
1132
81.0k
  /* 114 */ 'l', '2', 0,
1133
81.0k
  /* 117 */ 'o', '2', 0,
1134
81.0k
  /* 120 */ 'f', '1', '3', 0,
1135
81.0k
  /* 124 */ 'f', '2', '3', 0,
1136
81.0k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
81.0k
  /* 133 */ 'f', '3', 0,
1138
81.0k
  /* 136 */ 'g', '3', 0,
1139
81.0k
  /* 139 */ 'i', '3', 0,
1140
81.0k
  /* 142 */ 'l', '3', 0,
1141
81.0k
  /* 145 */ 'o', '3', 0,
1142
81.0k
  /* 148 */ 'f', '1', '4', 0,
1143
81.0k
  /* 152 */ 'f', '2', '4', 0,
1144
81.0k
  /* 156 */ 'f', '3', '4', 0,
1145
81.0k
  /* 160 */ 'f', '4', '4', 0,
1146
81.0k
  /* 164 */ 'f', '5', '4', 0,
1147
81.0k
  /* 168 */ 'f', '4', 0,
1148
81.0k
  /* 171 */ 'g', '4', 0,
1149
81.0k
  /* 174 */ 'i', '4', 0,
1150
81.0k
  /* 177 */ 'l', '4', 0,
1151
81.0k
  /* 180 */ 'o', '4', 0,
1152
81.0k
  /* 183 */ 'f', '1', '5', 0,
1153
81.0k
  /* 187 */ 'f', '2', '5', 0,
1154
81.0k
  /* 191 */ 'f', '5', 0,
1155
81.0k
  /* 194 */ 'g', '5', 0,
1156
81.0k
  /* 197 */ 'i', '5', 0,
1157
81.0k
  /* 200 */ 'l', '5', 0,
1158
81.0k
  /* 203 */ 'o', '5', 0,
1159
81.0k
  /* 206 */ 'f', '1', '6', 0,
1160
81.0k
  /* 210 */ 'f', '2', '6', 0,
1161
81.0k
  /* 214 */ 'f', '3', '6', 0,
1162
81.0k
  /* 218 */ 'f', '4', '6', 0,
1163
81.0k
  /* 222 */ 'f', '5', '6', 0,
1164
81.0k
  /* 226 */ 'f', '6', 0,
1165
81.0k
  /* 229 */ 'g', '6', 0,
1166
81.0k
  /* 232 */ 'l', '6', 0,
1167
81.0k
  /* 235 */ 'f', '1', '7', 0,
1168
81.0k
  /* 239 */ 'f', '2', '7', 0,
1169
81.0k
  /* 243 */ 'f', '7', 0,
1170
81.0k
  /* 246 */ 'g', '7', 0,
1171
81.0k
  /* 249 */ 'i', '7', 0,
1172
81.0k
  /* 252 */ 'l', '7', 0,
1173
81.0k
  /* 255 */ 'o', '7', 0,
1174
81.0k
  /* 258 */ 'f', '1', '8', 0,
1175
81.0k
  /* 262 */ 'f', '2', '8', 0,
1176
81.0k
  /* 266 */ 'f', '3', '8', 0,
1177
81.0k
  /* 270 */ 'f', '4', '8', 0,
1178
81.0k
  /* 274 */ 'f', '5', '8', 0,
1179
81.0k
  /* 278 */ 'f', '8', 0,
1180
81.0k
  /* 281 */ 'f', '1', '9', 0,
1181
81.0k
  /* 285 */ 'f', '2', '9', 0,
1182
81.0k
  /* 289 */ 'f', '9', 0,
1183
81.0k
  /* 292 */ 'i', 'c', 'c', 0,
1184
81.0k
  /* 296 */ 'f', 'p', 0,
1185
81.0k
  /* 299 */ 's', 'p', 0,
1186
81.0k
  /* 302 */ 'y', 0,
1187
81.0k
  };
1188
1189
81.0k
  static const uint16_t RegAsmOffset[] = {
1190
81.0k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
81.0k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
81.0k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
81.0k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
81.0k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
81.0k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
81.0k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
81.0k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
81.0k
    12, 160, 270, 92, 222, 20, 
1199
81.0k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
81.0k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
81.0k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
116k
{
1221
345k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
116k
  const char *AsmString;
1223
116k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
116k
  int OpIdx, PrintMethodIdx;
1225
116k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
116k
  switch (MCInst_getOpcode(MI)) {
1227
67.6k
  default: return NULL;
1228
5.96k
  case SP_BCOND:
1229
5.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
5.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
5.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
5.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
5.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
5.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
1.74k
      AsmString = "bn $\x01";
1241
1.74k
      break;
1242
1.74k
    }
1243
4.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
4.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
4.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
48
      AsmString = "bne $\x01";
1248
48
      break;
1249
48
    }
1250
4.17k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
4.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
4.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
439
      AsmString = "be $\x01";
1255
439
      break;
1256
439
    }
1257
3.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
3.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
3.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
312
      AsmString = "bg $\x01";
1262
312
      break;
1263
312
    }
1264
3.42k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
3.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
3.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
938
      AsmString = "ble $\x01";
1269
938
      break;
1270
938
    }
1271
2.48k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
2.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
2.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
80
      AsmString = "bge $\x01";
1276
80
      break;
1277
80
    }
1278
2.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
399
      AsmString = "bl $\x01";
1283
399
      break;
1284
399
    }
1285
2.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
135
      AsmString = "bgu $\x01";
1290
135
      break;
1291
135
    }
1292
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
312
      AsmString = "bleu $\x01";
1297
312
      break;
1298
312
    }
1299
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
111
      AsmString = "bcc $\x01";
1304
111
      break;
1305
111
    }
1306
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
191
      AsmString = "bcs $\x01";
1311
191
      break;
1312
191
    }
1313
1.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1314
1.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
1.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
87
      AsmString = "bpos $\x01";
1318
87
      break;
1319
87
    }
1320
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1321
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
406
      AsmString = "bneg $\x01";
1325
406
      break;
1326
406
    }
1327
762
    if (MCInst_getNumOperands(MI) == 2 &&
1328
762
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
762
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
556
      AsmString = "bvc $\x01";
1332
556
      break;
1333
556
    }
1334
206
    if (MCInst_getNumOperands(MI) == 2 &&
1335
206
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
206
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
206
      AsmString = "bvs $\x01";
1339
206
      break;
1340
206
    }
1341
0
    return NULL;
1342
5.06k
  case SP_BCONDA:
1343
5.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
5.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
5.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
356
      AsmString = "ba,a $\x01";
1348
356
      break;
1349
356
    }
1350
4.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
4.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
4.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
297
      AsmString = "bn,a $\x01";
1355
297
      break;
1356
297
    }
1357
4.41k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
4.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
4.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
173
      AsmString = "bne,a $\x01";
1362
173
      break;
1363
173
    }
1364
4.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
4.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
4.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
565
      AsmString = "be,a $\x01";
1369
565
      break;
1370
565
    }
1371
3.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
3.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
3.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
407
      AsmString = "bg,a $\x01";
1376
407
      break;
1377
407
    }
1378
3.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
3.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
3.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
439
      AsmString = "ble,a $\x01";
1383
439
      break;
1384
439
    }
1385
2.83k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
2.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
2.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
313
      AsmString = "bge,a $\x01";
1390
313
      break;
1391
313
    }
1392
2.51k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
2.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
2.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
126
      AsmString = "bl,a $\x01";
1397
126
      break;
1398
126
    }
1399
2.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
126
      AsmString = "bgu,a $\x01";
1404
126
      break;
1405
126
    }
1406
2.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
126
      AsmString = "bleu,a $\x01";
1411
126
      break;
1412
126
    }
1413
2.14k
    if (MCInst_getNumOperands(MI) == 2 &&
1414
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
263
      AsmString = "bcc,a $\x01";
1418
263
      break;
1419
263
    }
1420
1.87k
    if (MCInst_getNumOperands(MI) == 2 &&
1421
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
117
      AsmString = "bcs,a $\x01";
1425
117
      break;
1426
117
    }
1427
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
1428
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
292
      AsmString = "bpos,a $\x01";
1432
292
      break;
1433
292
    }
1434
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1435
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
284
      AsmString = "bneg,a $\x01";
1439
284
      break;
1440
284
    }
1441
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1442
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
724
      AsmString = "bvc,a $\x01";
1446
724
      break;
1447
724
    }
1448
461
    if (MCInst_getNumOperands(MI) == 2 &&
1449
461
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
461
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
461
      AsmString = "bvs,a $\x01";
1453
461
      break;
1454
461
    }
1455
0
    return NULL;
1456
4.69k
  case SP_BPFCCANT:
1457
4.69k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
4.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
4.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
4.69k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
4.69k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
537
      AsmString = "fba,a,pn $\x03, $\x01";
1464
537
      break;
1465
537
    }
1466
4.16k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
4.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
4.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
4.16k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
4.16k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
299
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
299
      break;
1474
299
    }
1475
3.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.86k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.86k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
261
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
261
      break;
1483
261
    }
1484
3.60k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
3.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
3.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
3.60k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
3.60k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
406
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
406
      break;
1492
406
    }
1493
3.19k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
3.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
3.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
3.19k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
3.19k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
295
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
295
      break;
1501
295
    }
1502
2.89k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.89k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.89k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
388
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
388
      break;
1510
388
    }
1511
2.51k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
2.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
2.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
2.51k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
2.51k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
274
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
274
      break;
1519
274
    }
1520
2.23k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.23k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.23k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
345
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
345
      break;
1528
345
    }
1529
1.89k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.89k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.89k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
122
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
122
      break;
1537
122
    }
1538
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.77k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.77k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
202
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
202
      break;
1546
202
    }
1547
1.56k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.56k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.56k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
67
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
67
      break;
1555
67
    }
1556
1.50k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.50k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.50k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
279
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
279
      break;
1564
279
    }
1565
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1566
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
1.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
174
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
174
      break;
1573
174
    }
1574
1.04k
    if (MCInst_getNumOperands(MI) == 3 &&
1575
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
1.04k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
1.04k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
376
      AsmString = "fble,a,pn $\x03, $\x01";
1581
376
      break;
1582
376
    }
1583
672
    if (MCInst_getNumOperands(MI) == 3 &&
1584
672
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
672
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
672
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
672
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
367
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
367
      break;
1591
367
    }
1592
305
    if (MCInst_getNumOperands(MI) == 3 &&
1593
305
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
305
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
305
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
305
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
305
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
305
      break;
1600
305
    }
1601
0
    return NULL;
1602
4.90k
  case SP_BPFCCNT:
1603
4.90k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
4.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
4.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
4.90k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
4.90k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
338
      AsmString = "fba,pn $\x03, $\x01";
1610
338
      break;
1611
338
    }
1612
4.57k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
4.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
4.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
4.57k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
4.57k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
578
      AsmString = "fbn,pn $\x03, $\x01";
1619
578
      break;
1620
578
    }
1621
3.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
3.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
3.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
3.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
3.99k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
500
      AsmString = "fbu,pn $\x03, $\x01";
1628
500
      break;
1629
500
    }
1630
3.49k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
3.49k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
3.49k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
549
      AsmString = "fbg,pn $\x03, $\x01";
1637
549
      break;
1638
549
    }
1639
2.94k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.94k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.94k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.94k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.94k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
78
      AsmString = "fbug,pn $\x03, $\x01";
1646
78
      break;
1647
78
    }
1648
2.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
2.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
2.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
2.86k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
2.86k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
145
      AsmString = "fbl,pn $\x03, $\x01";
1655
145
      break;
1656
145
    }
1657
2.72k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
2.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
2.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
2.72k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
2.72k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
324
      AsmString = "fbul,pn $\x03, $\x01";
1664
324
      break;
1665
324
    }
1666
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
2.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
280
      AsmString = "fblg,pn $\x03, $\x01";
1673
280
      break;
1674
280
    }
1675
2.11k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
2.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
2.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
2.11k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
2.11k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
310
      AsmString = "fbne,pn $\x03, $\x01";
1682
310
      break;
1683
310
    }
1684
1.80k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.80k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.80k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.80k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.80k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
575
      AsmString = "fbe,pn $\x03, $\x01";
1691
575
      break;
1692
575
    }
1693
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
1.23k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
284
      AsmString = "fbue,pn $\x03, $\x01";
1700
284
      break;
1701
284
    }
1702
948
    if (MCInst_getNumOperands(MI) == 3 &&
1703
948
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
948
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
948
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
948
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
202
      AsmString = "fbge,pn $\x03, $\x01";
1709
202
      break;
1710
202
    }
1711
746
    if (MCInst_getNumOperands(MI) == 3 &&
1712
746
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
746
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
746
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
746
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
241
      AsmString = "fbuge,pn $\x03, $\x01";
1718
241
      break;
1719
241
    }
1720
505
    if (MCInst_getNumOperands(MI) == 3 &&
1721
505
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
505
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
505
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
505
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
145
      AsmString = "fble,pn $\x03, $\x01";
1727
145
      break;
1728
145
    }
1729
360
    if (MCInst_getNumOperands(MI) == 3 &&
1730
360
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
360
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
360
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
360
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
223
      AsmString = "fbule,pn $\x03, $\x01";
1736
223
      break;
1737
223
    }
1738
137
    if (MCInst_getNumOperands(MI) == 3 &&
1739
137
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
137
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
137
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
137
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
137
      AsmString = "fbo,pn $\x03, $\x01";
1745
137
      break;
1746
137
    }
1747
0
    return NULL;
1748
4.25k
  case SP_BPICCANT:
1749
4.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
4.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
4.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
188
      AsmString = "ba,a,pn %icc, $\x01";
1754
188
      break;
1755
188
    }
1756
4.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
4.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
4.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
658
      AsmString = "bn,a,pn %icc, $\x01";
1761
658
      break;
1762
658
    }
1763
3.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
3.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
3.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
90
      AsmString = "bne,a,pn %icc, $\x01";
1768
90
      break;
1769
90
    }
1770
3.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
3.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
3.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
253
      AsmString = "be,a,pn %icc, $\x01";
1775
253
      break;
1776
253
    }
1777
3.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
600
      AsmString = "bg,a,pn %icc, $\x01";
1782
600
      break;
1783
600
    }
1784
2.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
623
      AsmString = "ble,a,pn %icc, $\x01";
1789
623
      break;
1790
623
    }
1791
1.83k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
100
      AsmString = "bge,a,pn %icc, $\x01";
1796
100
      break;
1797
100
    }
1798
1.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
58
      AsmString = "bl,a,pn %icc, $\x01";
1803
58
      break;
1804
58
    }
1805
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
125
      AsmString = "bgu,a,pn %icc, $\x01";
1810
125
      break;
1811
125
    }
1812
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
540
      AsmString = "bleu,a,pn %icc, $\x01";
1817
540
      break;
1818
540
    }
1819
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1820
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
127
      AsmString = "bcc,a,pn %icc, $\x01";
1824
127
      break;
1825
127
    }
1826
888
    if (MCInst_getNumOperands(MI) == 2 &&
1827
888
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
888
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
138
      AsmString = "bcs,a,pn %icc, $\x01";
1831
138
      break;
1832
138
    }
1833
750
    if (MCInst_getNumOperands(MI) == 2 &&
1834
750
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
750
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
201
      AsmString = "bpos,a,pn %icc, $\x01";
1838
201
      break;
1839
201
    }
1840
549
    if (MCInst_getNumOperands(MI) == 2 &&
1841
549
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
549
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
168
      AsmString = "bneg,a,pn %icc, $\x01";
1845
168
      break;
1846
168
    }
1847
381
    if (MCInst_getNumOperands(MI) == 2 &&
1848
381
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
381
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
273
      AsmString = "bvc,a,pn %icc, $\x01";
1852
273
      break;
1853
273
    }
1854
108
    if (MCInst_getNumOperands(MI) == 2 &&
1855
108
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
108
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
108
      AsmString = "bvs,a,pn %icc, $\x01";
1859
108
      break;
1860
108
    }
1861
0
    return NULL;
1862
3.83k
  case SP_BPICCNT:
1863
3.83k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
3.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
3.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
192
      AsmString = "ba,pn %icc, $\x01";
1868
192
      break;
1869
192
    }
1870
3.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
3.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
3.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
662
      AsmString = "bn,pn %icc, $\x01";
1875
662
      break;
1876
662
    }
1877
2.97k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
230
      AsmString = "bne,pn %icc, $\x01";
1882
230
      break;
1883
230
    }
1884
2.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
279
      AsmString = "be,pn %icc, $\x01";
1889
279
      break;
1890
279
    }
1891
2.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
325
      AsmString = "bg,pn %icc, $\x01";
1896
325
      break;
1897
325
    }
1898
2.14k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
169
      AsmString = "ble,pn %icc, $\x01";
1903
169
      break;
1904
169
    }
1905
1.97k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
145
      AsmString = "bge,pn %icc, $\x01";
1910
145
      break;
1911
145
    }
1912
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
147
      AsmString = "bl,pn %icc, $\x01";
1917
147
      break;
1918
147
    }
1919
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
152
      AsmString = "bgu,pn %icc, $\x01";
1924
152
      break;
1925
152
    }
1926
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
142
      AsmString = "bleu,pn %icc, $\x01";
1931
142
      break;
1932
142
    }
1933
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
37
      AsmString = "bcc,pn %icc, $\x01";
1938
37
      break;
1939
37
    }
1940
1.35k
    if (MCInst_getNumOperands(MI) == 2 &&
1941
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
397
      AsmString = "bcs,pn %icc, $\x01";
1945
397
      break;
1946
397
    }
1947
954
    if (MCInst_getNumOperands(MI) == 2 &&
1948
954
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
954
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
101
      AsmString = "bpos,pn %icc, $\x01";
1952
101
      break;
1953
101
    }
1954
853
    if (MCInst_getNumOperands(MI) == 2 &&
1955
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
386
      AsmString = "bneg,pn %icc, $\x01";
1959
386
      break;
1960
386
    }
1961
467
    if (MCInst_getNumOperands(MI) == 2 &&
1962
467
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
467
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
263
      AsmString = "bvc,pn %icc, $\x01";
1966
263
      break;
1967
263
    }
1968
204
    if (MCInst_getNumOperands(MI) == 2 &&
1969
204
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
204
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
204
      AsmString = "bvs,pn %icc, $\x01";
1973
204
      break;
1974
204
    }
1975
0
    return NULL;
1976
3.13k
  case SP_BPXCCANT:
1977
3.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
3.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
3.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
385
      AsmString = "ba,a,pn %xcc, $\x01";
1982
385
      break;
1983
385
    }
1984
2.75k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
2.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
2.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
354
      AsmString = "bn,a,pn %xcc, $\x01";
1989
354
      break;
1990
354
    }
1991
2.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
96
      AsmString = "bne,a,pn %xcc, $\x01";
1996
96
      break;
1997
96
    }
1998
2.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
2.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
2.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
343
      AsmString = "be,a,pn %xcc, $\x01";
2003
343
      break;
2004
343
    }
2005
1.95k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
98
      AsmString = "bg,a,pn %xcc, $\x01";
2010
98
      break;
2011
98
    }
2012
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
117
      AsmString = "ble,a,pn %xcc, $\x01";
2017
117
      break;
2018
117
    }
2019
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
175
      AsmString = "bge,a,pn %xcc, $\x01";
2024
175
      break;
2025
175
    }
2026
1.56k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
89
      AsmString = "bl,a,pn %xcc, $\x01";
2031
89
      break;
2032
89
    }
2033
1.48k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
102
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
102
      break;
2039
102
    }
2040
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
2041
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
72
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
72
      break;
2046
72
    }
2047
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
2048
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
126
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
126
      break;
2053
126
    }
2054
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
2055
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
403
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
403
      break;
2060
403
    }
2061
777
    if (MCInst_getNumOperands(MI) == 2 &&
2062
777
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
777
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
136
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
136
      break;
2067
136
    }
2068
641
    if (MCInst_getNumOperands(MI) == 2 &&
2069
641
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
641
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
227
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
227
      break;
2074
227
    }
2075
414
    if (MCInst_getNumOperands(MI) == 2 &&
2076
414
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
414
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
177
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
177
      break;
2081
177
    }
2082
237
    if (MCInst_getNumOperands(MI) == 2 &&
2083
237
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
237
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
237
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
237
      break;
2088
237
    }
2089
0
    return NULL;
2090
3.42k
  case SP_BPXCCNT:
2091
3.42k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
3.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
3.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
374
      AsmString = "ba,pn %xcc, $\x01";
2096
374
      break;
2097
374
    }
2098
3.04k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
3.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
3.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
587
      AsmString = "bn,pn %xcc, $\x01";
2103
587
      break;
2104
587
    }
2105
2.45k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
2.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
2.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
464
      AsmString = "bne,pn %xcc, $\x01";
2110
464
      break;
2111
464
    }
2112
1.99k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
107
      AsmString = "be,pn %xcc, $\x01";
2117
107
      break;
2118
107
    }
2119
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
75
      AsmString = "bg,pn %xcc, $\x01";
2124
75
      break;
2125
75
    }
2126
1.81k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
118
      AsmString = "ble,pn %xcc, $\x01";
2131
118
      break;
2132
118
    }
2133
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
138
      AsmString = "bge,pn %xcc, $\x01";
2138
138
      break;
2139
138
    }
2140
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
247
      AsmString = "bl,pn %xcc, $\x01";
2145
247
      break;
2146
247
    }
2147
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
253
      AsmString = "bgu,pn %xcc, $\x01";
2152
253
      break;
2153
253
    }
2154
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
2155
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
60
      AsmString = "bleu,pn %xcc, $\x01";
2159
60
      break;
2160
60
    }
2161
997
    if (MCInst_getNumOperands(MI) == 2 &&
2162
997
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
997
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
105
      AsmString = "bcc,pn %xcc, $\x01";
2166
105
      break;
2167
105
    }
2168
892
    if (MCInst_getNumOperands(MI) == 2 &&
2169
892
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
892
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
407
      AsmString = "bcs,pn %xcc, $\x01";
2173
407
      break;
2174
407
    }
2175
485
    if (MCInst_getNumOperands(MI) == 2 &&
2176
485
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
485
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
96
      AsmString = "bpos,pn %xcc, $\x01";
2180
96
      break;
2181
96
    }
2182
389
    if (MCInst_getNumOperands(MI) == 2 &&
2183
389
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
389
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
171
      AsmString = "bneg,pn %xcc, $\x01";
2187
171
      break;
2188
171
    }
2189
218
    if (MCInst_getNumOperands(MI) == 2 &&
2190
218
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
218
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
90
      AsmString = "bvc,pn %xcc, $\x01";
2194
90
      break;
2195
90
    }
2196
128
    if (MCInst_getNumOperands(MI) == 2 &&
2197
128
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
128
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
128
      AsmString = "bvs,pn %xcc, $\x01";
2201
128
      break;
2202
128
    }
2203
0
    return NULL;
2204
83
  case SP_FMOVD_ICC:
2205
83
    if (MCInst_getNumOperands(MI) == 3 &&
2206
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
83
    if (MCInst_getNumOperands(MI) == 3 &&
2217
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
83
    if (MCInst_getNumOperands(MI) == 3 &&
2228
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
83
    if (MCInst_getNumOperands(MI) == 3 &&
2239
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
83
    if (MCInst_getNumOperands(MI) == 3 &&
2250
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
83
    if (MCInst_getNumOperands(MI) == 3 &&
2261
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
83
    if (MCInst_getNumOperands(MI) == 3 &&
2272
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
83
    if (MCInst_getNumOperands(MI) == 3 &&
2283
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
83
    if (MCInst_getNumOperands(MI) == 3 &&
2294
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
83
    if (MCInst_getNumOperands(MI) == 3 &&
2305
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
83
    if (MCInst_getNumOperands(MI) == 3 &&
2316
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
83
    if (MCInst_getNumOperands(MI) == 3 &&
2327
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
83
    if (MCInst_getNumOperands(MI) == 3 &&
2338
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
83
    if (MCInst_getNumOperands(MI) == 3 &&
2349
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
83
    if (MCInst_getNumOperands(MI) == 3 &&
2360
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
83
    if (MCInst_getNumOperands(MI) == 3 &&
2371
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
83
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
83
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
83
    return NULL;
2382
62
  case SP_FMOVD_XCC:
2383
62
    if (MCInst_getNumOperands(MI) == 3 &&
2384
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
62
    if (MCInst_getNumOperands(MI) == 3 &&
2395
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
62
    if (MCInst_getNumOperands(MI) == 3 &&
2406
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
62
    if (MCInst_getNumOperands(MI) == 3 &&
2417
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
62
    if (MCInst_getNumOperands(MI) == 3 &&
2428
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
62
    if (MCInst_getNumOperands(MI) == 3 &&
2439
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
62
    if (MCInst_getNumOperands(MI) == 3 &&
2450
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
62
    if (MCInst_getNumOperands(MI) == 3 &&
2461
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
62
    if (MCInst_getNumOperands(MI) == 3 &&
2472
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
62
    if (MCInst_getNumOperands(MI) == 3 &&
2483
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
62
    if (MCInst_getNumOperands(MI) == 3 &&
2494
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
62
    if (MCInst_getNumOperands(MI) == 3 &&
2505
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
62
    if (MCInst_getNumOperands(MI) == 3 &&
2516
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
62
    if (MCInst_getNumOperands(MI) == 3 &&
2527
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
62
    if (MCInst_getNumOperands(MI) == 3 &&
2538
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
62
    if (MCInst_getNumOperands(MI) == 3 &&
2549
62
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
62
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
62
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
62
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
62
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
62
    return NULL;
2560
461
  case SP_FMOVQ_ICC:
2561
461
    if (MCInst_getNumOperands(MI) == 3 &&
2562
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
461
    if (MCInst_getNumOperands(MI) == 3 &&
2573
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
461
    if (MCInst_getNumOperands(MI) == 3 &&
2584
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
461
    if (MCInst_getNumOperands(MI) == 3 &&
2595
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
461
    if (MCInst_getNumOperands(MI) == 3 &&
2606
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
461
    if (MCInst_getNumOperands(MI) == 3 &&
2617
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
461
    if (MCInst_getNumOperands(MI) == 3 &&
2628
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
461
    if (MCInst_getNumOperands(MI) == 3 &&
2639
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
461
    if (MCInst_getNumOperands(MI) == 3 &&
2650
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
461
    if (MCInst_getNumOperands(MI) == 3 &&
2661
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
461
    if (MCInst_getNumOperands(MI) == 3 &&
2672
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
461
    if (MCInst_getNumOperands(MI) == 3 &&
2683
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
461
    if (MCInst_getNumOperands(MI) == 3 &&
2694
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
461
    if (MCInst_getNumOperands(MI) == 3 &&
2705
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
461
    if (MCInst_getNumOperands(MI) == 3 &&
2716
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
461
    if (MCInst_getNumOperands(MI) == 3 &&
2727
461
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
461
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
461
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
461
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
461
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
461
    return NULL;
2738
94
  case SP_FMOVQ_XCC:
2739
94
    if (MCInst_getNumOperands(MI) == 3 &&
2740
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
94
    if (MCInst_getNumOperands(MI) == 3 &&
2751
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
94
    if (MCInst_getNumOperands(MI) == 3 &&
2762
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
94
    if (MCInst_getNumOperands(MI) == 3 &&
2773
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
94
    if (MCInst_getNumOperands(MI) == 3 &&
2784
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
94
    if (MCInst_getNumOperands(MI) == 3 &&
2795
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
94
    if (MCInst_getNumOperands(MI) == 3 &&
2806
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
94
    if (MCInst_getNumOperands(MI) == 3 &&
2817
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
94
    if (MCInst_getNumOperands(MI) == 3 &&
2828
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
94
    if (MCInst_getNumOperands(MI) == 3 &&
2839
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
94
    if (MCInst_getNumOperands(MI) == 3 &&
2850
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
94
    if (MCInst_getNumOperands(MI) == 3 &&
2861
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
94
    if (MCInst_getNumOperands(MI) == 3 &&
2872
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
94
    if (MCInst_getNumOperands(MI) == 3 &&
2883
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
94
    if (MCInst_getNumOperands(MI) == 3 &&
2894
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
94
    if (MCInst_getNumOperands(MI) == 3 &&
2905
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
94
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
94
    return NULL;
2916
63
  case SP_FMOVS_ICC:
2917
63
    if (MCInst_getNumOperands(MI) == 3 &&
2918
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
63
    if (MCInst_getNumOperands(MI) == 3 &&
2929
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
63
    if (MCInst_getNumOperands(MI) == 3 &&
2940
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
63
    if (MCInst_getNumOperands(MI) == 3 &&
2951
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
63
    if (MCInst_getNumOperands(MI) == 3 &&
2962
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
63
    if (MCInst_getNumOperands(MI) == 3 &&
2973
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
63
    if (MCInst_getNumOperands(MI) == 3 &&
2984
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
63
    if (MCInst_getNumOperands(MI) == 3 &&
2995
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
63
    if (MCInst_getNumOperands(MI) == 3 &&
3006
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
63
    if (MCInst_getNumOperands(MI) == 3 &&
3017
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
63
    if (MCInst_getNumOperands(MI) == 3 &&
3028
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
63
    if (MCInst_getNumOperands(MI) == 3 &&
3039
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
63
    if (MCInst_getNumOperands(MI) == 3 &&
3050
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
63
    if (MCInst_getNumOperands(MI) == 3 &&
3061
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
63
    if (MCInst_getNumOperands(MI) == 3 &&
3072
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
63
    if (MCInst_getNumOperands(MI) == 3 &&
3083
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
63
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
63
    return NULL;
3094
21
  case SP_FMOVS_XCC:
3095
21
    if (MCInst_getNumOperands(MI) == 3 &&
3096
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
21
    if (MCInst_getNumOperands(MI) == 3 &&
3107
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
21
    if (MCInst_getNumOperands(MI) == 3 &&
3118
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
21
    if (MCInst_getNumOperands(MI) == 3 &&
3129
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
21
    if (MCInst_getNumOperands(MI) == 3 &&
3140
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
21
    if (MCInst_getNumOperands(MI) == 3 &&
3151
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
21
    if (MCInst_getNumOperands(MI) == 3 &&
3162
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
21
    if (MCInst_getNumOperands(MI) == 3 &&
3173
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
21
    if (MCInst_getNumOperands(MI) == 3 &&
3184
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
21
    if (MCInst_getNumOperands(MI) == 3 &&
3195
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
21
    if (MCInst_getNumOperands(MI) == 3 &&
3206
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
21
    if (MCInst_getNumOperands(MI) == 3 &&
3217
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
21
    if (MCInst_getNumOperands(MI) == 3 &&
3228
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
21
    if (MCInst_getNumOperands(MI) == 3 &&
3239
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
21
    if (MCInst_getNumOperands(MI) == 3 &&
3250
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
21
    if (MCInst_getNumOperands(MI) == 3 &&
3261
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
21
    return NULL;
3272
108
  case SP_MOVICCri:
3273
108
    if (MCInst_getNumOperands(MI) == 3 &&
3274
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
108
    if (MCInst_getNumOperands(MI) == 3 &&
3283
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
108
    if (MCInst_getNumOperands(MI) == 3 &&
3292
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
108
    if (MCInst_getNumOperands(MI) == 3 &&
3301
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
108
    if (MCInst_getNumOperands(MI) == 3 &&
3310
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
108
    if (MCInst_getNumOperands(MI) == 3 &&
3319
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
108
    if (MCInst_getNumOperands(MI) == 3 &&
3328
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
108
    if (MCInst_getNumOperands(MI) == 3 &&
3337
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
108
    if (MCInst_getNumOperands(MI) == 3 &&
3346
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
108
    if (MCInst_getNumOperands(MI) == 3 &&
3355
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
108
    if (MCInst_getNumOperands(MI) == 3 &&
3364
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
108
    if (MCInst_getNumOperands(MI) == 3 &&
3373
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
108
    if (MCInst_getNumOperands(MI) == 3 &&
3382
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
108
    if (MCInst_getNumOperands(MI) == 3 &&
3391
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
108
    if (MCInst_getNumOperands(MI) == 3 &&
3400
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
108
    if (MCInst_getNumOperands(MI) == 3 &&
3409
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
108
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
108
    return NULL;
3418
94
  case SP_MOVICCrr:
3419
94
    if (MCInst_getNumOperands(MI) == 3 &&
3420
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
94
    if (MCInst_getNumOperands(MI) == 3 &&
3431
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
94
    if (MCInst_getNumOperands(MI) == 3 &&
3442
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
94
    if (MCInst_getNumOperands(MI) == 3 &&
3453
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
94
    if (MCInst_getNumOperands(MI) == 3 &&
3464
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
94
    if (MCInst_getNumOperands(MI) == 3 &&
3475
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
94
    if (MCInst_getNumOperands(MI) == 3 &&
3486
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
94
    if (MCInst_getNumOperands(MI) == 3 &&
3497
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
94
    if (MCInst_getNumOperands(MI) == 3 &&
3508
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
94
    if (MCInst_getNumOperands(MI) == 3 &&
3519
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
94
    if (MCInst_getNumOperands(MI) == 3 &&
3530
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
94
    if (MCInst_getNumOperands(MI) == 3 &&
3541
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
94
    if (MCInst_getNumOperands(MI) == 3 &&
3552
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
94
    if (MCInst_getNumOperands(MI) == 3 &&
3563
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
94
    if (MCInst_getNumOperands(MI) == 3 &&
3574
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
94
    if (MCInst_getNumOperands(MI) == 3 &&
3585
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
94
    return NULL;
3596
120
  case SP_MOVXCCri:
3597
120
    if (MCInst_getNumOperands(MI) == 3 &&
3598
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
120
    if (MCInst_getNumOperands(MI) == 3 &&
3607
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
120
    if (MCInst_getNumOperands(MI) == 3 &&
3616
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
120
    if (MCInst_getNumOperands(MI) == 3 &&
3625
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
120
    if (MCInst_getNumOperands(MI) == 3 &&
3634
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
120
    if (MCInst_getNumOperands(MI) == 3 &&
3643
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
120
    if (MCInst_getNumOperands(MI) == 3 &&
3652
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
120
    if (MCInst_getNumOperands(MI) == 3 &&
3661
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
120
    if (MCInst_getNumOperands(MI) == 3 &&
3670
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
120
    if (MCInst_getNumOperands(MI) == 3 &&
3679
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
120
    if (MCInst_getNumOperands(MI) == 3 &&
3688
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
120
    if (MCInst_getNumOperands(MI) == 3 &&
3697
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
120
    if (MCInst_getNumOperands(MI) == 3 &&
3706
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
120
    if (MCInst_getNumOperands(MI) == 3 &&
3715
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
120
    if (MCInst_getNumOperands(MI) == 3 &&
3724
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
120
    if (MCInst_getNumOperands(MI) == 3 &&
3733
120
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
120
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
120
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
120
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
120
    return NULL;
3742
87
  case SP_MOVXCCrr:
3743
87
    if (MCInst_getNumOperands(MI) == 3 &&
3744
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
87
    if (MCInst_getNumOperands(MI) == 3 &&
3755
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
87
    if (MCInst_getNumOperands(MI) == 3 &&
3766
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
87
    if (MCInst_getNumOperands(MI) == 3 &&
3777
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
87
    if (MCInst_getNumOperands(MI) == 3 &&
3788
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
87
    if (MCInst_getNumOperands(MI) == 3 &&
3799
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
87
    if (MCInst_getNumOperands(MI) == 3 &&
3810
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
87
    if (MCInst_getNumOperands(MI) == 3 &&
3821
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
87
    if (MCInst_getNumOperands(MI) == 3 &&
3832
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
87
    if (MCInst_getNumOperands(MI) == 3 &&
3843
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
87
    if (MCInst_getNumOperands(MI) == 3 &&
3854
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
87
    if (MCInst_getNumOperands(MI) == 3 &&
3865
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
87
    if (MCInst_getNumOperands(MI) == 3 &&
3876
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
87
    if (MCInst_getNumOperands(MI) == 3 &&
3887
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
87
    if (MCInst_getNumOperands(MI) == 3 &&
3898
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
87
    if (MCInst_getNumOperands(MI) == 3 &&
3909
87
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
87
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
87
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
87
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
87
    return NULL;
3920
324
  case SP_ORri:
3921
324
    if (MCInst_getNumOperands(MI) == 3 &&
3922
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
324
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
57
      AsmString = "mov $\x03, $\x01";
3927
57
      break;
3928
57
    }
3929
267
    return NULL;
3930
325
  case SP_ORrr:
3931
325
    if (MCInst_getNumOperands(MI) == 3 &&
3932
325
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
325
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
325
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
325
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
325
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
94
      AsmString = "mov $\x03, $\x01";
3939
94
      break;
3940
94
    }
3941
231
    return NULL;
3942
208
  case SP_RESTORErr:
3943
208
    if (MCInst_getNumOperands(MI) == 3 &&
3944
208
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
208
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
208
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
25
      AsmString = "restore";
3949
25
      break;
3950
25
    }
3951
183
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
2.86k
  case SP_TXCCri:
3971
2.86k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
2.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
2.86k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
2.86k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
2.86k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
99
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
99
      break;
3979
99
    }
3980
2.76k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
2.76k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
2.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
2.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
2.76k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
2.76k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
2.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
2.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
2.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
108
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
108
      break;
3996
108
    }
3997
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
2.65k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
259
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
259
      break;
4013
259
    }
4014
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
2.39k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
2.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
23
      AsmString = "te %xcc, $\x01 + $\x02";
4029
23
      break;
4030
23
    }
4031
2.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
2.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
2.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
2.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
2.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
203
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
203
      break;
4047
203
    }
4048
2.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
2.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
2.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
2.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
2.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
79
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
79
      break;
4064
79
    }
4065
2.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
2.09k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
2.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
2.09k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
2.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
161
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
161
      break;
4081
161
    }
4082
1.93k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
1.93k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
1.93k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
1.93k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
1.93k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
89
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
89
      break;
4098
89
    }
4099
1.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
1.84k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
1.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
1.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
1.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
1.84k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
1.84k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
1.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
1.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
44
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
44
      break;
4115
44
    }
4116
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
1.79k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
1.79k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
463
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
463
      break;
4132
463
    }
4133
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
195
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
195
      break;
4149
195
    }
4150
1.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.14k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.14k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
170
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
170
      break;
4166
170
    }
4167
970
    if (MCInst_getNumOperands(MI) == 3 &&
4168
970
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
970
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
970
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
970
    if (MCInst_getNumOperands(MI) == 3 &&
4176
970
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
970
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
970
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
970
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
423
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
423
      break;
4183
423
    }
4184
547
    if (MCInst_getNumOperands(MI) == 3 &&
4185
547
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
547
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
547
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
547
    if (MCInst_getNumOperands(MI) == 3 &&
4193
547
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
547
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
547
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
547
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
79
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
79
      break;
4200
79
    }
4201
468
    if (MCInst_getNumOperands(MI) == 3 &&
4202
468
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
468
    if (MCInst_getNumOperands(MI) == 3 &&
4210
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
468
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
176
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
176
      break;
4217
176
    }
4218
292
    if (MCInst_getNumOperands(MI) == 3 &&
4219
292
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
292
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
292
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
292
    if (MCInst_getNumOperands(MI) == 3 &&
4227
292
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
292
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
292
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
292
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
292
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
292
      break;
4234
292
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
3.03k
  case SP_TXCCrr:
4245
3.03k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
3.03k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
3.03k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
3.03k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
3.03k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
3.03k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
3.03k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
193
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
193
      break;
4255
193
    }
4256
2.83k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.83k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.83k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.83k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.83k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.83k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.83k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.83k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.83k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.83k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.83k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.83k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.83k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
96
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
96
      break;
4276
96
    }
4277
2.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.74k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.74k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.74k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.74k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
40
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
40
      break;
4297
40
    }
4298
2.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.70k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
50
      AsmString = "te %xcc, $\x01 + $\x02";
4317
50
      break;
4318
50
    }
4319
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.65k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
104
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
104
      break;
4339
104
    }
4340
2.54k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.54k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.54k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.54k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.54k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.54k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.54k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.54k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.54k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.54k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
53
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
53
      break;
4360
53
    }
4361
2.49k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.49k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.49k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.49k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.49k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.49k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.49k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.49k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.49k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.49k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.49k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.49k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.49k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
46
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
46
      break;
4381
46
    }
4382
2.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.44k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
70
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
70
      break;
4402
70
    }
4403
2.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
2.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
2.37k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
2.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
2.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
2.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
2.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
2.37k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
2.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
856
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
856
      break;
4423
856
    }
4424
1.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.52k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.52k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.52k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.52k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
193
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
193
      break;
4444
193
    }
4445
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
63
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
63
      break;
4465
63
    }
4466
1.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.26k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
59
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
59
      break;
4486
59
    }
4487
1.20k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.20k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.20k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
56
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
56
      break;
4507
56
    }
4508
1.15k
    if (MCInst_getNumOperands(MI) == 3 &&
4509
1.15k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
1.15k
    if (MCInst_getNumOperands(MI) == 3 &&
4519
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
44
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
44
      break;
4528
44
    }
4529
1.10k
    if (MCInst_getNumOperands(MI) == 3 &&
4530
1.10k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
1.10k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
1.10k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
1.10k
    if (MCInst_getNumOperands(MI) == 3 &&
4540
1.10k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
1.10k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
1.10k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
1.10k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
394
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
394
      break;
4549
394
    }
4550
714
    if (MCInst_getNumOperands(MI) == 3 &&
4551
714
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
714
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
714
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
714
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
714
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
714
    if (MCInst_getNumOperands(MI) == 3 &&
4561
714
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
714
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
714
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
714
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
714
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
714
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
714
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
714
      break;
4570
714
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
1.25k
  case SP_V9FCMPD:
4583
1.25k
    if (MCInst_getNumOperands(MI) == 3 &&
4584
1.25k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
1.25k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
1.25k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
1.25k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
1.25k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
445
      AsmString = "fcmpd $\x02, $\x03";
4591
445
      break;
4592
445
    }
4593
810
    return NULL;
4594
654
  case SP_V9FCMPED:
4595
654
    if (MCInst_getNumOperands(MI) == 3 &&
4596
654
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
654
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
654
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
654
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
654
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
129
      AsmString = "fcmped $\x02, $\x03";
4603
129
      break;
4604
129
    }
4605
525
    return NULL;
4606
484
  case SP_V9FCMPEQ:
4607
484
    if (MCInst_getNumOperands(MI) == 3 &&
4608
484
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
484
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
484
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
484
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
484
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
170
      AsmString = "fcmpeq $\x02, $\x03";
4615
170
      break;
4616
170
    }
4617
314
    return NULL;
4618
662
  case SP_V9FCMPES:
4619
662
    if (MCInst_getNumOperands(MI) == 3 &&
4620
662
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
662
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
662
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
662
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
662
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
249
      AsmString = "fcmpes $\x02, $\x03";
4627
249
      break;
4628
249
    }
4629
413
    return NULL;
4630
146
  case SP_V9FCMPQ:
4631
146
    if (MCInst_getNumOperands(MI) == 3 &&
4632
146
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
146
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
146
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
146
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
146
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
48
      AsmString = "fcmpq $\x02, $\x03";
4639
48
      break;
4640
48
    }
4641
98
    return NULL;
4642
459
  case SP_V9FCMPS:
4643
459
    if (MCInst_getNumOperands(MI) == 3 &&
4644
459
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
459
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
459
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
459
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
459
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
68
      AsmString = "fcmps $\x02, $\x03";
4651
68
      break;
4652
68
    }
4653
391
    return NULL;
4654
114
  case SP_V9FMOVD_FCC:
4655
114
    if (MCInst_getNumOperands(MI) == 4 &&
4656
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
114
    if (MCInst_getNumOperands(MI) == 4 &&
4669
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
114
    if (MCInst_getNumOperands(MI) == 4 &&
4682
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
114
    if (MCInst_getNumOperands(MI) == 4 &&
4695
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
114
    if (MCInst_getNumOperands(MI) == 4 &&
4708
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
114
    if (MCInst_getNumOperands(MI) == 4 &&
4721
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
114
    if (MCInst_getNumOperands(MI) == 4 &&
4734
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
114
    if (MCInst_getNumOperands(MI) == 4 &&
4747
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
114
    if (MCInst_getNumOperands(MI) == 4 &&
4760
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
114
    if (MCInst_getNumOperands(MI) == 4 &&
4773
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
114
    if (MCInst_getNumOperands(MI) == 4 &&
4786
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
114
    if (MCInst_getNumOperands(MI) == 4 &&
4799
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
114
    if (MCInst_getNumOperands(MI) == 4 &&
4812
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
114
    if (MCInst_getNumOperands(MI) == 4 &&
4825
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
114
    if (MCInst_getNumOperands(MI) == 4 &&
4838
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
114
    if (MCInst_getNumOperands(MI) == 4 &&
4851
114
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
114
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
114
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
114
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
114
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
114
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
114
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
114
    return NULL;
4864
53
  case SP_V9FMOVQ_FCC:
4865
53
    if (MCInst_getNumOperands(MI) == 4 &&
4866
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
53
    if (MCInst_getNumOperands(MI) == 4 &&
4879
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
53
    if (MCInst_getNumOperands(MI) == 4 &&
4892
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
53
    if (MCInst_getNumOperands(MI) == 4 &&
4905
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
53
    if (MCInst_getNumOperands(MI) == 4 &&
4918
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
53
    if (MCInst_getNumOperands(MI) == 4 &&
4931
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
53
    if (MCInst_getNumOperands(MI) == 4 &&
4944
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
53
    if (MCInst_getNumOperands(MI) == 4 &&
4957
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
53
    if (MCInst_getNumOperands(MI) == 4 &&
4970
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
53
    if (MCInst_getNumOperands(MI) == 4 &&
4983
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
53
    if (MCInst_getNumOperands(MI) == 4 &&
4996
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
53
    if (MCInst_getNumOperands(MI) == 4 &&
5009
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
53
    if (MCInst_getNumOperands(MI) == 4 &&
5022
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
53
    if (MCInst_getNumOperands(MI) == 4 &&
5035
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
53
    if (MCInst_getNumOperands(MI) == 4 &&
5048
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
53
    if (MCInst_getNumOperands(MI) == 4 &&
5061
53
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
53
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
53
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
53
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
53
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
53
    return NULL;
5074
230
  case SP_V9FMOVS_FCC:
5075
230
    if (MCInst_getNumOperands(MI) == 4 &&
5076
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
230
    if (MCInst_getNumOperands(MI) == 4 &&
5089
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
230
    if (MCInst_getNumOperands(MI) == 4 &&
5102
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
230
    if (MCInst_getNumOperands(MI) == 4 &&
5115
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
230
    if (MCInst_getNumOperands(MI) == 4 &&
5128
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
230
    if (MCInst_getNumOperands(MI) == 4 &&
5141
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
230
    if (MCInst_getNumOperands(MI) == 4 &&
5154
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
230
    if (MCInst_getNumOperands(MI) == 4 &&
5167
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
230
    if (MCInst_getNumOperands(MI) == 4 &&
5180
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
230
    if (MCInst_getNumOperands(MI) == 4 &&
5193
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
230
    if (MCInst_getNumOperands(MI) == 4 &&
5206
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
230
    if (MCInst_getNumOperands(MI) == 4 &&
5219
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
230
    if (MCInst_getNumOperands(MI) == 4 &&
5232
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
230
    if (MCInst_getNumOperands(MI) == 4 &&
5245
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
230
    if (MCInst_getNumOperands(MI) == 4 &&
5258
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
230
    if (MCInst_getNumOperands(MI) == 4 &&
5271
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
230
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
230
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
230
    return NULL;
5284
915
  case SP_V9MOVFCCri:
5285
915
    if (MCInst_getNumOperands(MI) == 4 &&
5286
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
915
    if (MCInst_getNumOperands(MI) == 4 &&
5297
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
915
    if (MCInst_getNumOperands(MI) == 4 &&
5308
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
915
    if (MCInst_getNumOperands(MI) == 4 &&
5319
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
915
    if (MCInst_getNumOperands(MI) == 4 &&
5330
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
915
    if (MCInst_getNumOperands(MI) == 4 &&
5341
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
915
    if (MCInst_getNumOperands(MI) == 4 &&
5352
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
915
    if (MCInst_getNumOperands(MI) == 4 &&
5363
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
915
    if (MCInst_getNumOperands(MI) == 4 &&
5374
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
915
    if (MCInst_getNumOperands(MI) == 4 &&
5385
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
915
    if (MCInst_getNumOperands(MI) == 4 &&
5396
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
915
    if (MCInst_getNumOperands(MI) == 4 &&
5407
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
915
    if (MCInst_getNumOperands(MI) == 4 &&
5418
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
915
    if (MCInst_getNumOperands(MI) == 4 &&
5429
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
915
    if (MCInst_getNumOperands(MI) == 4 &&
5440
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
915
    if (MCInst_getNumOperands(MI) == 4 &&
5451
915
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
915
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
915
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
915
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
915
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
915
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
915
    return NULL;
5462
303
  case SP_V9MOVFCCrr:
5463
303
    if (MCInst_getNumOperands(MI) == 4 &&
5464
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
303
    if (MCInst_getNumOperands(MI) == 4 &&
5477
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
303
    if (MCInst_getNumOperands(MI) == 4 &&
5490
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
303
    if (MCInst_getNumOperands(MI) == 4 &&
5503
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
303
    if (MCInst_getNumOperands(MI) == 4 &&
5516
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
303
    if (MCInst_getNumOperands(MI) == 4 &&
5529
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
303
    if (MCInst_getNumOperands(MI) == 4 &&
5542
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
303
    if (MCInst_getNumOperands(MI) == 4 &&
5555
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
303
    if (MCInst_getNumOperands(MI) == 4 &&
5568
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
303
    if (MCInst_getNumOperands(MI) == 4 &&
5581
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
303
    if (MCInst_getNumOperands(MI) == 4 &&
5594
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
303
    if (MCInst_getNumOperands(MI) == 4 &&
5607
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
303
    if (MCInst_getNumOperands(MI) == 4 &&
5620
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
303
    if (MCInst_getNumOperands(MI) == 4 &&
5633
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
303
    if (MCInst_getNumOperands(MI) == 4 &&
5646
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
303
    if (MCInst_getNumOperands(MI) == 4 &&
5659
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
303
    return NULL;
5672
116k
  }
5673
5674
42.4k
  tmp = cs_strdup(AsmString);
5675
42.4k
  AsmMnem = tmp;
5676
278k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
278k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
42.4k
      *AsmOps = '\0';
5679
42.4k
      AsmOps++;
5680
42.4k
      break;
5681
42.4k
    }
5682
278k
  }
5683
42.4k
  SStream_concat0(OS, AsmMnem);
5684
42.4k
  if (*AsmOps) {
5685
42.4k
    SStream_concat0(OS, "\t");
5686
42.4k
    if (strstr(AsmOps, "icc"))
5687
8.08k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
42.4k
    if (strstr(AsmOps, "xcc"))
5689
12.4k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
264k
    for (c = AsmOps; *c; c++) {
5691
221k
      if (*c == '$') {
5692
59.1k
        c += 1;
5693
59.1k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
59.1k
          printOperand(MI, *c - 1, OS);
5701
162k
      } else {
5702
162k
        SStream_concat(OS, "%c", *c);
5703
162k
      }
5704
221k
    }
5705
42.4k
  }
5706
42.4k
  return tmp;
5707
116k
}
5708
5709
#endif // PRINT_ALIAS_INSTR