/src/capstonev5/arch/ARM/ARMDisassembler.c
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1 | | //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | /* Capstone Disassembly Engine */ |
11 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
12 | | |
13 | | #ifdef CAPSTONE_HAS_ARM |
14 | | |
15 | | #include <stdio.h> |
16 | | #include <string.h> |
17 | | #include <stdlib.h> |
18 | | #include <capstone/platform.h> |
19 | | |
20 | | #include "ARMAddressingModes.h" |
21 | | #include "ARMBaseInfo.h" |
22 | | #include "../../MCFixedLenDisassembler.h" |
23 | | #include "../../MCInst.h" |
24 | | #include "../../MCInstrDesc.h" |
25 | | #include "../../MCRegisterInfo.h" |
26 | | #include "../../LEB128.h" |
27 | | #include "../../MCDisassembler.h" |
28 | | #include "../../cs_priv.h" |
29 | | #include "../../utils.h" |
30 | | |
31 | | #include "ARMDisassembler.h" |
32 | | #include "ARMMapping.h" |
33 | | |
34 | | #define GET_SUBTARGETINFO_ENUM |
35 | | #include "ARMGenSubtargetInfo.inc" |
36 | | |
37 | | #define GET_INSTRINFO_MC_DESC |
38 | | #include "ARMGenInstrInfo.inc" |
39 | | |
40 | | #define GET_INSTRINFO_ENUM |
41 | | #include "ARMGenInstrInfo.inc" |
42 | | |
43 | | static bool ITStatus_push_back(ARM_ITStatus *it, char v) |
44 | 14.2k | { |
45 | 14.2k | if (it->size >= sizeof(it->ITStates)) { |
46 | | // TODO: consider warning user. |
47 | 0 | it->size = 0; |
48 | 0 | } |
49 | 14.2k | it->ITStates[it->size] = v; |
50 | 14.2k | it->size++; |
51 | | |
52 | 14.2k | return true; |
53 | 14.2k | } |
54 | | |
55 | | // Returns true if the current instruction is in an IT block |
56 | | static bool ITStatus_instrInITBlock(ARM_ITStatus *it) |
57 | 1.70M | { |
58 | | //return !ITStates.empty(); |
59 | 1.70M | return (it->size > 0); |
60 | 1.70M | } |
61 | | |
62 | | // Returns true if current instruction is the last instruction in an IT block |
63 | | static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) |
64 | 584 | { |
65 | 584 | return (it->size == 1); |
66 | 584 | } |
67 | | |
68 | | // Handles the condition code status of instructions in IT blocks |
69 | | |
70 | | // Returns the condition code for instruction in IT block |
71 | | static unsigned ITStatus_getITCC(ARM_ITStatus *it) |
72 | 688k | { |
73 | 688k | unsigned CC = ARMCC_AL; |
74 | | |
75 | 688k | if (ITStatus_instrInITBlock(it)) |
76 | | //CC = ITStates.back(); |
77 | 13.9k | CC = it->ITStates[it->size-1]; |
78 | | |
79 | 688k | return CC; |
80 | 688k | } |
81 | | |
82 | | // Advances the IT block state to the next T or E |
83 | | static void ITStatus_advanceITState(ARM_ITStatus *it) |
84 | 13.9k | { |
85 | | //ITStates.pop_back(); |
86 | 13.9k | it->size--; |
87 | 13.9k | } |
88 | | |
89 | | // Called when decoding an IT instruction. Sets the IT state for the following |
90 | | // instructions that for the IT block. Firstcond and Mask correspond to the |
91 | | // fields in the IT instruction encoding. |
92 | | static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) |
93 | 4.48k | { |
94 | | // (3 - the number of trailing zeros) is the number of then / else. |
95 | 4.48k | unsigned CondBit0 = Firstcond & 1; |
96 | 4.48k | unsigned NumTZ = CountTrailingZeros_32(Mask); |
97 | 4.48k | unsigned char CCBits = (unsigned char)Firstcond & 0xf; |
98 | 4.48k | unsigned Pos; |
99 | | |
100 | | //assert(NumTZ <= 3 && "Invalid IT mask!"); |
101 | | // push condition codes onto the stack the correct order for the pops |
102 | 14.2k | for (Pos = NumTZ + 1; Pos <= 3; ++Pos) { |
103 | 9.77k | bool T = ((Mask >> Pos) & 1) == (int)CondBit0; |
104 | | |
105 | 9.77k | if (T) |
106 | 4.82k | ITStatus_push_back(it, CCBits); |
107 | 4.94k | else |
108 | 4.94k | ITStatus_push_back(it, CCBits ^ 1); |
109 | 9.77k | } |
110 | | |
111 | 4.48k | ITStatus_push_back(it, CCBits); |
112 | 4.48k | } |
113 | | |
114 | | /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. |
115 | | |
116 | | static bool Check(DecodeStatus *Out, DecodeStatus In) |
117 | 4.13M | { |
118 | 4.13M | switch (In) { |
119 | 3.98M | case MCDisassembler_Success: |
120 | | // Out stays the same. |
121 | 3.98M | return true; |
122 | 131k | case MCDisassembler_SoftFail: |
123 | 131k | *Out = In; |
124 | 131k | return true; |
125 | 14.5k | case MCDisassembler_Fail: |
126 | 14.5k | *Out = In; |
127 | 14.5k | return false; |
128 | 0 | default: // never reached |
129 | 0 | return false; |
130 | 4.13M | } |
131 | 4.13M | } |
132 | | |
133 | | // Forward declare these because the autogenerated code will reference them. |
134 | | // Definitions are further down. |
135 | | static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
136 | | uint64_t Address, const void *Decoder); |
137 | | static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, |
138 | | unsigned RegNo, uint64_t Address, const void *Decoder); |
139 | | static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, |
140 | | unsigned RegNo, uint64_t Address, const void *Decoder); |
141 | | static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
142 | | uint64_t Address, const void *Decoder); |
143 | | static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
144 | | uint64_t Address, const void *Decoder); |
145 | | static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
146 | | uint64_t Address, const void *Decoder); |
147 | | static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, |
148 | | uint64_t Address, const void *Decoder); |
149 | | static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, |
150 | | uint64_t Address, const void *Decoder); |
151 | | static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, |
152 | | uint64_t Address, const void *Decoder); |
153 | | static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, |
154 | | uint64_t Address, const void *Decoder); |
155 | | static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, |
156 | | unsigned RegNo, uint64_t Address, const void *Decoder); |
157 | | static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, |
158 | | uint64_t Address, const void *Decoder); |
159 | | static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, |
160 | | uint64_t Address, const void *Decoder); |
161 | | static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, |
162 | | unsigned RegNo, uint64_t Address, const void *Decoder); |
163 | | static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, |
164 | | uint64_t Address, const void *Decoder); |
165 | | static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, |
166 | | uint64_t Address, const void *Decoder); |
167 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, |
168 | | uint64_t Address, const void *Decoder); |
169 | | static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, |
170 | | uint64_t Address, const void *Decoder); |
171 | | static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, |
172 | | uint64_t Address, const void *Decoder); |
173 | | static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, |
174 | | uint64_t Address, const void *Decoder); |
175 | | static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, |
176 | | uint64_t Address, const void *Decoder); |
177 | | static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, |
178 | | unsigned Insn, uint64_t Address, const void *Decoder); |
179 | | static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, |
180 | | uint64_t Address, const void *Decoder); |
181 | | static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, |
182 | | uint64_t Address, const void *Decoder); |
183 | | static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, |
184 | | uint64_t Address, const void *Decoder); |
185 | | static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, |
186 | | uint64_t Address, const void *Decoder); |
187 | | static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, |
188 | | unsigned Insn, uint64_t Adddress, const void *Decoder); |
189 | | static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, |
190 | | uint64_t Address, const void *Decoder); |
191 | | static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, |
192 | | uint64_t Address, const void *Decoder); |
193 | | static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, |
194 | | uint64_t Address, const void *Decoder); |
195 | | static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, |
196 | | uint64_t Address, const void *Decoder); |
197 | | static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, |
198 | | uint64_t Address, const void *Decoder); |
199 | | static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, |
200 | | uint64_t Address, const void *Decoder); |
201 | | static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, |
202 | | uint64_t Address, const void *Decoder); |
203 | | static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, |
204 | | uint64_t Address, const void *Decoder); |
205 | | static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, |
206 | | uint64_t Address, const void *Decoder); |
207 | | static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, |
208 | | uint64_t Address, const void *Decoder); |
209 | | static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, |
210 | | uint64_t Address, const void *Decoder); |
211 | | static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, |
212 | | uint64_t Address, const void *Decoder); |
213 | | static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, |
214 | | uint64_t Address, const void *Decoder); |
215 | | static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, |
216 | | uint64_t Address, const void *Decoder); |
217 | | static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, |
218 | | uint64_t Address, const void *Decoder); |
219 | | static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, |
220 | | uint64_t Address, const void *Decoder); |
221 | | static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, |
222 | | uint64_t Address, const void *Decoder); |
223 | | static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, |
224 | | uint64_t Address, const void *Decoder); |
225 | | static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, |
226 | | uint64_t Address, const void *Decoder); |
227 | | static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, |
228 | | uint64_t Address, const void *Decoder); |
229 | | static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, |
230 | | uint64_t Address, const void *Decoder); |
231 | | static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, |
232 | | uint64_t Address, const void *Decoder); |
233 | | static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, |
234 | | uint64_t Address, const void *Decoder); |
235 | | static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, |
236 | | uint64_t Address, const void *Decoder); |
237 | | static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, |
238 | | uint64_t Address, const void *Decoder); |
239 | | static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, |
240 | | uint64_t Address, const void *Decoder); |
241 | | static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, |
242 | | uint64_t Address, const void *Decoder); |
243 | | static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, |
244 | | uint64_t Address, const void *Decoder); |
245 | | static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, |
246 | | uint64_t Address, const void *Decoder); |
247 | | static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, |
248 | | uint64_t Address, const void *Decoder); |
249 | | static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, |
250 | | uint64_t Address, const void *Decoder); |
251 | | static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, |
252 | | uint64_t Address, const void *Decoder); |
253 | | static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, |
254 | | uint64_t Address, const void *Decoder); |
255 | | static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, |
256 | | uint64_t Address, const void *Decoder); |
257 | | static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, |
258 | | uint64_t Address, const void *Decoder); |
259 | | static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, |
260 | | uint64_t Address, const void *Decoder); |
261 | | static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, |
262 | | uint64_t Address, const void *Decoder); |
263 | | static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, |
264 | | uint64_t Address, const void *Decoder); |
265 | | static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, |
266 | | uint64_t Address, const void *Decoder); |
267 | | static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, |
268 | | uint64_t Address, const void *Decoder); |
269 | | static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, |
270 | | uint64_t Address, const void *Decoder); |
271 | | static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, |
272 | | uint64_t Address, const void *Decoder); |
273 | | static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, |
274 | | uint64_t Address, const void *Decoder); |
275 | | static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, |
276 | | uint64_t Address, const void *Decoder); |
277 | | static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, |
278 | | uint64_t Address, const void *Decoder); |
279 | | static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, |
280 | | uint64_t Address, const void *Decoder); |
281 | | static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, |
282 | | uint64_t Address, const void *Decoder); |
283 | | static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, |
284 | | uint64_t Address, const void *Decoder); |
285 | | static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, |
286 | | uint64_t Address, const void *Decoder); |
287 | | static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, |
288 | | uint64_t Address, const void *Decoder); |
289 | | static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, |
290 | | uint64_t Address, const void *Decoder); |
291 | | static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, |
292 | | uint64_t Address, const void *Decoder); |
293 | | static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, |
294 | | uint64_t Address, const void *Decoder); |
295 | | static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, |
296 | | uint64_t Address, const void *Decoder); |
297 | | static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, |
298 | | uint64_t Address, const void *Decoder); |
299 | | static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, |
300 | | uint64_t Address, const void *Decoder); |
301 | | static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, |
302 | | uint64_t Address, const void *Decoder); |
303 | | static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, |
304 | | uint64_t Address, const void *Decoder); |
305 | | static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, |
306 | | uint64_t Address, const void *Decoder); |
307 | | static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, |
308 | | uint64_t Address, const void *Decoder); |
309 | | static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, |
310 | | uint64_t Address, const void *Decoder); |
311 | | static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, |
312 | | uint64_t Address, const void *Decoder); |
313 | | static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, |
314 | | uint64_t Address, const void *Decoder); |
315 | | static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, |
316 | | uint64_t Address, const void* Decoder); |
317 | | static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, |
318 | | uint64_t Address, const void* Decoder); |
319 | | static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, |
320 | | uint64_t Address, const void* Decoder); |
321 | | static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, |
322 | | uint64_t Address, const void* Decoder); |
323 | | static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, |
324 | | uint64_t Address, const void *Decoder); |
325 | | static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, |
326 | | uint64_t Address, const void *Decoder); |
327 | | static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, |
328 | | uint64_t Address, const void *Decoder); |
329 | | static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, |
330 | | uint64_t Address, const void *Decoder); |
331 | | static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, |
332 | | uint64_t Address, const void *Decoder); |
333 | | static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, |
334 | | uint64_t Address, const void *Decoder); |
335 | | static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, |
336 | | uint64_t Address, const void *Decoder); |
337 | | static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, |
338 | | uint64_t Address, const void *Decoder); |
339 | | static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, |
340 | | uint64_t Address, const void *Decoder); |
341 | | static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, |
342 | | uint64_t Address, const void *Decoder); |
343 | | static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, |
344 | | uint64_t Address, const void *Decoder); |
345 | | static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, |
346 | | uint64_t Address, const void *Decoder); |
347 | | static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, |
348 | | uint64_t Address, const void *Decoder); |
349 | | static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, |
350 | | uint64_t Address, const void *Decoder); |
351 | | static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, |
352 | | uint64_t Address, const void *Decoder); |
353 | | static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, |
354 | | uint64_t Address, const void *Decoder); |
355 | | static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, |
356 | | uint64_t Address, const void *Decoder); |
357 | | static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, |
358 | | uint64_t Address, const void *Decoder); |
359 | | static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, |
360 | | uint64_t Address, const void *Decoder); |
361 | | static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, |
362 | | uint64_t Address, const void *Decoder); |
363 | | static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, |
364 | | uint64_t Address, const void *Decoder); |
365 | | static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, |
366 | | uint64_t Address, const void *Decoder); |
367 | | static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, |
368 | | uint64_t Address, const void *Decoder); |
369 | | static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, |
370 | | uint64_t Address, const void *Decoder); |
371 | | static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, |
372 | | uint64_t Address, const void *Decoder); |
373 | | static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, |
374 | | uint64_t Address, const void *Decoder); |
375 | | static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, |
376 | | uint64_t Address, const void *Decoder); |
377 | | static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, |
378 | | uint64_t Address, const void *Decoder); |
379 | | static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, |
380 | | uint64_t Address, const void *Decoder); |
381 | | static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, |
382 | | uint64_t Address, const void *Decoder); |
383 | | static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, |
384 | | uint64_t Address, const void *Decoder); |
385 | | |
386 | | // Hacky: enable all features for disassembler |
387 | | bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) |
388 | 2.84M | { |
389 | 2.84M | if ((mode & CS_MODE_V8) == 0) { |
390 | | // not V8 mode |
391 | 2.21M | if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps || |
392 | 2.21M | feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps) |
393 | | // HasV8MBaselineOps |
394 | 121k | return false; |
395 | 2.21M | } |
396 | 2.72M | if (feature == ARM_FeatureVFPOnlySP) |
397 | 10.5k | return false; |
398 | | |
399 | 2.71M | if ((mode & CS_MODE_MCLASS) == 0) { |
400 | 1.91M | if (feature == ARM_FeatureMClass) |
401 | 88.8k | return false; |
402 | 1.91M | } |
403 | | |
404 | 2.62M | if ((mode & CS_MODE_THUMB) == 0) { |
405 | | // not Thumb |
406 | 336k | if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb) |
407 | 242k | return false; |
408 | | // FIXME: what mode enables D16? |
409 | 94.7k | if (feature == ARM_FeatureD16) |
410 | 26.5k | return false; |
411 | 2.29M | } else { |
412 | | // Thumb |
413 | 2.29M | if (feature == ARM_FeatureD16) |
414 | 164k | return false; |
415 | 2.29M | } |
416 | | |
417 | 2.19M | if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) |
418 | 0 | return false; |
419 | | |
420 | | // we support everything |
421 | 2.19M | return true; |
422 | 2.19M | } |
423 | | |
424 | | #include "ARMGenDisassemblerTables.inc" |
425 | | |
426 | | static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, |
427 | | uint64_t Address, const void *Decoder) |
428 | 205k | { |
429 | 205k | if (Val == 0xF) return MCDisassembler_Fail; |
430 | | |
431 | | // AL predicate is not allowed on Thumb1 branches. |
432 | 197k | if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) |
433 | 0 | return MCDisassembler_Fail; |
434 | | |
435 | 197k | MCOperand_CreateImm0(Inst, Val); |
436 | | |
437 | 197k | if (Val == ARMCC_AL) { |
438 | 29.4k | MCOperand_CreateReg0(Inst, 0); |
439 | 29.4k | } else |
440 | 167k | MCOperand_CreateReg0(Inst, ARM_CPSR); |
441 | | |
442 | 197k | return MCDisassembler_Success; |
443 | 197k | } |
444 | | |
445 | | #define GET_REGINFO_MC_DESC |
446 | | #include "ARMGenRegisterInfo.inc" |
447 | | void ARM_init(MCRegisterInfo *MRI) |
448 | 10.9k | { |
449 | | /* |
450 | | InitMCRegisterInfo(ARMRegDesc, 289, |
451 | | RA, PC, |
452 | | ARMMCRegisterClasses, 103, |
453 | | ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, |
454 | | ARMSubRegIdxLists, 57, |
455 | | ARMSubRegIdxRanges, ARMRegEncodingTable); |
456 | | */ |
457 | | |
458 | 10.9k | MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, |
459 | 10.9k | 0, 0, |
460 | 10.9k | ARMMCRegisterClasses, 103, |
461 | 10.9k | 0, 0, ARMRegDiffLists, 0, |
462 | 10.9k | ARMSubRegIdxLists, 57, |
463 | 10.9k | 0); |
464 | 10.9k | } |
465 | | |
466 | | // Post-decoding checks |
467 | | static DecodeStatus checkDecodedInstruction(MCInst *MI, |
468 | | uint32_t Insn, |
469 | | DecodeStatus Result) |
470 | 167k | { |
471 | 167k | switch (MCInst_getOpcode(MI)) { |
472 | 279 | case ARM_HVC: { |
473 | | // HVC is undefined if condition = 0xf otherwise upredictable |
474 | | // if condition != 0xe |
475 | 279 | uint32_t Cond = (Insn >> 28) & 0xF; |
476 | | |
477 | 279 | if (Cond == 0xF) |
478 | 1 | return MCDisassembler_Fail; |
479 | | |
480 | 278 | if (Cond != 0xE) |
481 | 210 | return MCDisassembler_SoftFail; |
482 | | |
483 | 68 | return Result; |
484 | 278 | } |
485 | 167k | default: |
486 | 167k | return Result; |
487 | 167k | } |
488 | 167k | } |
489 | | |
490 | | static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, |
491 | | uint16_t *Size, uint64_t Address) |
492 | 183k | { |
493 | 183k | uint32_t insn; |
494 | 183k | DecodeStatus result; |
495 | | |
496 | 183k | *Size = 0; |
497 | | |
498 | 183k | if (code_len < 4) |
499 | | // not enough data |
500 | 1.69k | return MCDisassembler_Fail; |
501 | | |
502 | 181k | if (MI->flat_insn->detail) { |
503 | 181k | unsigned int i; |
504 | | |
505 | 181k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); |
506 | | |
507 | 6.71M | for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { |
508 | 6.53M | MI->flat_insn->detail->arm.operands[i].vector_index = -1; |
509 | 6.53M | MI->flat_insn->detail->arm.operands[i].neon_lane = -1; |
510 | 6.53M | } |
511 | 181k | } |
512 | | |
513 | 181k | if (MODE_IS_BIG_ENDIAN(ud->mode)) |
514 | 0 | insn = (code[3] << 0) | (code[2] << 8) | |
515 | 0 | (code[1] << 16) | ((uint32_t) code[0] << 24); |
516 | 181k | else |
517 | 181k | insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | |
518 | 181k | (code[1] << 8) | (code[0] << 0); |
519 | | |
520 | | // Calling the auto-generated decoder function. |
521 | 181k | result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address); |
522 | 181k | if (result != MCDisassembler_Fail) { |
523 | 146k | result = checkDecodedInstruction(MI, insn, result); |
524 | 146k | if (result != MCDisassembler_Fail) |
525 | 146k | *Size = 4; |
526 | | |
527 | 146k | return result; |
528 | 146k | } |
529 | | |
530 | | // VFP and NEON instructions, similarly, are shared between ARM |
531 | | // and Thumb modes. |
532 | 34.7k | MCInst_clear(MI); |
533 | 34.7k | result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address); |
534 | 34.7k | if (result != MCDisassembler_Fail) { |
535 | 5.22k | *Size = 4; |
536 | 5.22k | return result; |
537 | 5.22k | } |
538 | | |
539 | 29.4k | MCInst_clear(MI); |
540 | 29.4k | result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address); |
541 | 29.4k | if (result != MCDisassembler_Fail) { |
542 | 2.22k | *Size = 4; |
543 | 2.22k | return result; |
544 | 2.22k | } |
545 | | |
546 | 27.2k | MCInst_clear(MI); |
547 | 27.2k | result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address); |
548 | 27.2k | if (result != MCDisassembler_Fail) { |
549 | 2.51k | *Size = 4; |
550 | | // Add a fake predicate operand, because we share these instruction |
551 | | // definitions with Thumb2 where these instructions are predicable. |
552 | 2.51k | if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) |
553 | 0 | return MCDisassembler_Fail; |
554 | 2.51k | return result; |
555 | 2.51k | } |
556 | | |
557 | 24.7k | MCInst_clear(MI); |
558 | 24.7k | result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address); |
559 | 24.7k | if (result != MCDisassembler_Fail) { |
560 | 2.13k | *Size = 4; |
561 | | // Add a fake predicate operand, because we share these instruction |
562 | | // definitions with Thumb2 where these instructions are predicable. |
563 | 2.13k | if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) |
564 | 0 | return MCDisassembler_Fail; |
565 | 2.13k | return result; |
566 | 2.13k | } |
567 | | |
568 | 22.6k | MCInst_clear(MI); |
569 | 22.6k | result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address); |
570 | 22.6k | if (result != MCDisassembler_Fail) { |
571 | 445 | *Size = 4; |
572 | | // Add a fake predicate operand, because we share these instruction |
573 | | // definitions with Thumb2 where these instructions are predicable. |
574 | 445 | if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) |
575 | 0 | return MCDisassembler_Fail; |
576 | 445 | return result; |
577 | 445 | } |
578 | | |
579 | 22.1k | MCInst_clear(MI); |
580 | 22.1k | result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address); |
581 | 22.1k | if (result != MCDisassembler_Fail) { |
582 | 235 | *Size = 4; |
583 | 235 | return result; |
584 | 235 | } |
585 | | |
586 | 21.9k | MCInst_clear(MI); |
587 | 21.9k | result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address); |
588 | 21.9k | if (result != MCDisassembler_Fail) { |
589 | 18 | *Size = 4; |
590 | 18 | return result; |
591 | 18 | } |
592 | | |
593 | 21.9k | result = decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address); |
594 | 21.9k | if (result != MCDisassembler_Fail) { |
595 | 21.1k | result = checkDecodedInstruction(MI, insn, result); |
596 | 21.1k | if (result != MCDisassembler_Fail) |
597 | 21.1k | *Size = 4; |
598 | | |
599 | 21.1k | return result; |
600 | 21.1k | } |
601 | | |
602 | 743 | MCInst_clear(MI); |
603 | 743 | *Size = 0; |
604 | 743 | return MCDisassembler_Fail; |
605 | 21.9k | } |
606 | | |
607 | | // Thumb1 instructions don't have explicit S bits. Rather, they |
608 | | // implicitly set CPSR. Since it's not represented in the encoding, the |
609 | | // auto-generated decoder won't inject the CPSR operand. We need to fix |
610 | | // that as a post-pass. |
611 | | static void AddThumb1SBit(MCInst *MI, bool InITBlock) |
612 | 473k | { |
613 | 473k | const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; |
614 | 473k | unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; |
615 | 473k | unsigned i; |
616 | | |
617 | 962k | for (i = 0; i < NumOps; ++i) { |
618 | 954k | if (i == MCInst_getNumOperands(MI)) break; |
619 | | |
620 | 954k | if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { |
621 | 466k | if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) continue; |
622 | 466k | MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); |
623 | 466k | return; |
624 | 466k | } |
625 | 954k | } |
626 | | |
627 | | //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); |
628 | 7.56k | MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); |
629 | 7.56k | } |
630 | | |
631 | | // Most Thumb instructions don't have explicit predicates in the |
632 | | // encoding, but rather get their predicates from IT context. We need |
633 | | // to fix up the predicate operands using this context information as a |
634 | | // post-pass. |
635 | | static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) |
636 | 787k | { |
637 | 787k | DecodeStatus S = MCDisassembler_Success; |
638 | 787k | const MCOperandInfo *OpInfo; |
639 | 787k | unsigned short NumOps; |
640 | 787k | unsigned int i; |
641 | 787k | unsigned CC; |
642 | | |
643 | | // A few instructions actually have predicates encoded in them. Don't |
644 | | // try to overwrite it if we're seeing one of those. |
645 | 787k | switch (MCInst_getOpcode(MI)) { |
646 | 21.2k | case ARM_tBcc: |
647 | 23.6k | case ARM_t2Bcc: |
648 | 26.3k | case ARM_tCBZ: |
649 | 31.0k | case ARM_tCBNZ: |
650 | 31.5k | case ARM_tCPS: |
651 | 31.7k | case ARM_t2CPS3p: |
652 | 31.8k | case ARM_t2CPS2p: |
653 | 31.9k | case ARM_t2CPS1p: |
654 | 109k | case ARM_tMOVSr: |
655 | 110k | case ARM_tSETEND: |
656 | | // Some instructions (mostly conditional branches) are not |
657 | | // allowed in IT blocks. |
658 | 110k | if (ITStatus_instrInITBlock(&(ud->ITBlock))) |
659 | 1.56k | S = MCDisassembler_SoftFail; |
660 | 108k | else |
661 | 108k | return MCDisassembler_Success; |
662 | 1.56k | break; |
663 | | |
664 | 1.56k | case ARM_t2HINT: |
665 | 1.37k | if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10) |
666 | 34 | S = MCDisassembler_SoftFail; |
667 | 1.37k | break; |
668 | | |
669 | 11.3k | case ARM_tB: |
670 | 12.1k | case ARM_t2B: |
671 | 12.3k | case ARM_t2TBB: |
672 | 12.4k | case ARM_t2TBH: |
673 | | // Some instructions (mostly unconditional branches) can |
674 | | // only appears at the end of, or outside of, an IT. |
675 | | // if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) |
676 | 12.4k | if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) |
677 | 438 | S = MCDisassembler_SoftFail; |
678 | 12.4k | break; |
679 | 663k | default: |
680 | 663k | break; |
681 | 787k | } |
682 | | |
683 | | // If we're in an IT block, base the predicate on that. Otherwise, |
684 | | // assume a predicate of AL. |
685 | 678k | CC = ITStatus_getITCC(&(ud->ITBlock)); |
686 | 678k | if (CC == 0xF) |
687 | 1.53k | CC = ARMCC_AL; |
688 | | |
689 | 678k | if (ITStatus_instrInITBlock(&(ud->ITBlock))) |
690 | 13.3k | ITStatus_advanceITState(&(ud->ITBlock)); |
691 | | |
692 | 678k | OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; |
693 | 678k | NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; |
694 | | |
695 | 2.70M | for (i = 0; i < NumOps; ++i) { |
696 | 2.69M | if (i == MCInst_getNumOperands(MI)) break; |
697 | | |
698 | 2.07M | if (MCOperandInfo_isPredicate(&OpInfo[i])) { |
699 | 50.2k | MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); |
700 | | |
701 | 50.2k | if (CC == ARMCC_AL) |
702 | 48.8k | MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); |
703 | 1.44k | else |
704 | 1.44k | MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); |
705 | | |
706 | 50.2k | return S; |
707 | 50.2k | } |
708 | 2.07M | } |
709 | | |
710 | 628k | MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); |
711 | | |
712 | 628k | if (CC == ARMCC_AL) |
713 | 620k | MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); |
714 | 8.10k | else |
715 | 8.10k | MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); |
716 | | |
717 | 628k | return S; |
718 | 678k | } |
719 | | |
720 | | // Thumb VFP instructions are a special case. Because we share their |
721 | | // encodings between ARM and Thumb modes, and they are predicable in ARM |
722 | | // mode, the auto-generated decoder will give them an (incorrect) |
723 | | // predicate operand. We need to rewrite these operands based on the IT |
724 | | // context as a post-pass. |
725 | | static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) |
726 | 9.68k | { |
727 | 9.68k | unsigned CC; |
728 | 9.68k | unsigned short NumOps; |
729 | 9.68k | const MCOperandInfo *OpInfo; |
730 | 9.68k | unsigned i; |
731 | | |
732 | 9.68k | CC = ITStatus_getITCC(&(ud->ITBlock)); |
733 | 9.68k | if (ITStatus_instrInITBlock(&(ud->ITBlock))) |
734 | 582 | ITStatus_advanceITState(&(ud->ITBlock)); |
735 | | |
736 | 9.68k | OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; |
737 | 9.68k | NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; |
738 | | |
739 | 31.5k | for (i = 0; i < NumOps; ++i) { |
740 | 31.5k | if (MCOperandInfo_isPredicate(&OpInfo[i])) { |
741 | 9.68k | MCOperand_setImm(MCInst_getOperand(MI, i), CC); |
742 | | |
743 | 9.68k | if (CC == ARMCC_AL) |
744 | 9.12k | MCOperand_setReg(MCInst_getOperand(MI, i + 1), 0); |
745 | 558 | else |
746 | 558 | MCOperand_setReg(MCInst_getOperand(MI, i + 1), ARM_CPSR); |
747 | | |
748 | 9.68k | return; |
749 | 9.68k | } |
750 | 31.5k | } |
751 | 9.68k | } |
752 | | |
753 | | static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, |
754 | | uint16_t *Size, uint64_t Address) |
755 | 806k | { |
756 | 806k | uint16_t insn16; |
757 | 806k | DecodeStatus result; |
758 | 806k | bool InITBlock; |
759 | 806k | unsigned Firstcond, Mask; |
760 | 806k | uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; |
761 | 806k | size_t i; |
762 | | |
763 | | // We want to read exactly 2 bytes of data. |
764 | 806k | if (code_len < 2) |
765 | | // not enough data |
766 | 2.06k | return MCDisassembler_Fail; |
767 | | |
768 | 803k | if (MI->flat_insn->detail) { |
769 | 803k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm)); |
770 | 29.7M | for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { |
771 | 28.9M | MI->flat_insn->detail->arm.operands[i].vector_index = -1; |
772 | 28.9M | MI->flat_insn->detail->arm.operands[i].neon_lane = -1; |
773 | 28.9M | } |
774 | 803k | } |
775 | | |
776 | 803k | if (MODE_IS_BIG_ENDIAN(ud->mode)) |
777 | 0 | insn16 = (code[0] << 8) | code[1]; |
778 | 803k | else |
779 | 803k | insn16 = (code[1] << 8) | code[0]; |
780 | | |
781 | 803k | result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address); |
782 | 803k | if (result != MCDisassembler_Fail) { |
783 | 400k | *Size = 2; |
784 | 400k | Check(&result, AddThumbPredicate(ud, MI)); |
785 | 400k | return result; |
786 | 400k | } |
787 | | |
788 | 403k | MCInst_clear(MI); |
789 | 403k | result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address); |
790 | 403k | if (result) { |
791 | 197k | *Size = 2; |
792 | 197k | InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); |
793 | 197k | Check(&result, AddThumbPredicate(ud, MI)); |
794 | 197k | AddThumb1SBit(MI, InITBlock); |
795 | 197k | return result; |
796 | 197k | } |
797 | | |
798 | 206k | MCInst_clear(MI); |
799 | 206k | result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address); |
800 | 206k | if (result != MCDisassembler_Fail) { |
801 | 6.49k | *Size = 2; |
802 | | |
803 | | // Nested IT blocks are UNPREDICTABLE. Must be checked before we add |
804 | | // the Thumb predicate. |
805 | 6.49k | if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) |
806 | 2.00k | return MCDisassembler_SoftFail; |
807 | | |
808 | 4.48k | Check(&result, AddThumbPredicate(ud, MI)); |
809 | | |
810 | | // If we find an IT instruction, we need to parse its condition |
811 | | // code and mask operands so that we can apply them correctly |
812 | | // to the subsequent instructions. |
813 | 4.48k | if (MCInst_getOpcode(MI) == ARM_t2IT) { |
814 | 4.48k | Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); |
815 | 4.48k | Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); |
816 | 4.48k | ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); |
817 | | |
818 | | // An IT instruction that would give a 'NV' predicate is unpredictable. |
819 | | // if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) |
820 | | // CS << "unpredictable IT predicate sequence"; |
821 | 4.48k | } |
822 | | |
823 | 4.48k | return result; |
824 | 6.49k | } |
825 | | |
826 | | // We want to read exactly 4 bytes of data. |
827 | 199k | if (code_len < 4) |
828 | | // not enough data |
829 | 499 | return MCDisassembler_Fail; |
830 | | |
831 | 199k | if (MODE_IS_BIG_ENDIAN(ud->mode)) |
832 | 0 | insn32 = (code[3] << 0) | (code[2] << 8) | |
833 | 0 | (code[1] << 16) | ((uint32_t) code[0] << 24); |
834 | 199k | else |
835 | 199k | insn32 = (code[3] << 8) | (code[2] << 0) | |
836 | 199k | ((uint32_t) code[1] << 24) | (code[0] << 16); |
837 | | |
838 | 199k | MCInst_clear(MI); |
839 | 199k | result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address); |
840 | 199k | if (result != MCDisassembler_Fail) { |
841 | 3.90k | *Size = 4; |
842 | 3.90k | InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); |
843 | 3.90k | Check(&result, AddThumbPredicate(ud, MI)); |
844 | 3.90k | AddThumb1SBit(MI, InITBlock); |
845 | | |
846 | 3.90k | return result; |
847 | 3.90k | } |
848 | | |
849 | 195k | MCInst_clear(MI); |
850 | 195k | result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address); |
851 | 195k | if (result != MCDisassembler_Fail) { |
852 | 86.1k | *Size = 4; |
853 | 86.1k | Check(&result, AddThumbPredicate(ud, MI)); |
854 | 86.1k | return result; |
855 | 86.1k | } |
856 | | |
857 | 109k | if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { |
858 | 27.9k | MCInst_clear(MI); |
859 | 27.9k | result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address); |
860 | 27.9k | if (result != MCDisassembler_Fail) { |
861 | 9.68k | *Size = 4; |
862 | 9.68k | UpdateThumbVFPPredicate(ud, MI); |
863 | 9.68k | return result; |
864 | 9.68k | } |
865 | 27.9k | } |
866 | | |
867 | 99.3k | MCInst_clear(MI); |
868 | 99.3k | result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address); |
869 | 99.3k | if (result != MCDisassembler_Fail) { |
870 | 1.26k | *Size = 4; |
871 | 1.26k | return result; |
872 | 1.26k | } |
873 | | |
874 | 98.0k | if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { |
875 | 18.2k | MCInst_clear(MI); |
876 | 18.2k | result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address); |
877 | 18.2k | if (result != MCDisassembler_Fail) { |
878 | 1.51k | *Size = 4; |
879 | 1.51k | Check(&result, AddThumbPredicate(ud, MI)); |
880 | 1.51k | return result; |
881 | 1.51k | } |
882 | 18.2k | } |
883 | | |
884 | 96.5k | if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { |
885 | 51.1k | MCInst_clear(MI); |
886 | 51.1k | NEONLdStInsn = insn32; |
887 | 51.1k | NEONLdStInsn &= 0xF0FFFFFF; |
888 | 51.1k | NEONLdStInsn |= 0x04000000; |
889 | 51.1k | result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address); |
890 | 51.1k | if (result != MCDisassembler_Fail) { |
891 | 50.7k | *Size = 4; |
892 | 50.7k | Check(&result, AddThumbPredicate(ud, MI)); |
893 | 50.7k | return result; |
894 | 50.7k | } |
895 | 51.1k | } |
896 | | |
897 | 45.8k | if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { |
898 | 24.0k | MCInst_clear(MI); |
899 | 24.0k | NEONDataInsn = insn32; |
900 | 24.0k | NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 |
901 | 24.0k | NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 |
902 | 24.0k | NEONDataInsn |= 0x12000000; // Set bits 28 and 25 |
903 | 24.0k | result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address); |
904 | 24.0k | if (result != MCDisassembler_Fail) { |
905 | 23.7k | *Size = 4; |
906 | 23.7k | Check(&result, AddThumbPredicate(ud, MI)); |
907 | 23.7k | return result; |
908 | 23.7k | } |
909 | 24.0k | } |
910 | | |
911 | 22.1k | MCInst_clear(MI); |
912 | 22.1k | NEONCryptoInsn = insn32; |
913 | 22.1k | NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 |
914 | 22.1k | NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 |
915 | 22.1k | NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 |
916 | 22.1k | result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address); |
917 | 22.1k | if (result != MCDisassembler_Fail) { |
918 | 222 | *Size = 4; |
919 | 222 | return result; |
920 | 222 | } |
921 | | |
922 | 21.8k | MCInst_clear(MI); |
923 | 21.8k | NEONv8Insn = insn32; |
924 | 21.8k | NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 |
925 | 21.8k | result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address); |
926 | 21.8k | if (result != MCDisassembler_Fail) { |
927 | 2.13k | *Size = 4; |
928 | 2.13k | return result; |
929 | 2.13k | } |
930 | | |
931 | 19.7k | MCInst_clear(MI); |
932 | 19.7k | result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address); |
933 | 19.7k | if (result != MCDisassembler_Fail) { |
934 | 18.7k | *Size = 4; |
935 | 18.7k | Check(&result, AddThumbPredicate(ud, MI)); |
936 | 18.7k | return result; |
937 | 18.7k | } |
938 | | |
939 | 957 | MCInst_clear(MI); |
940 | 957 | *Size = 0; |
941 | | |
942 | 957 | return MCDisassembler_Fail; |
943 | 19.7k | } |
944 | | |
945 | | bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, |
946 | | uint16_t *size, uint64_t address, void *info) |
947 | 806k | { |
948 | 806k | DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); |
949 | | |
950 | | // TODO: fix table gen to eliminate these special cases |
951 | 806k | if (instr->Opcode == ARM_t__brkdiv0) |
952 | 2 | return false; |
953 | | |
954 | | //return status == MCDisassembler_Success; |
955 | 806k | return status != MCDisassembler_Fail; |
956 | 806k | } |
957 | | |
958 | | bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, |
959 | | uint16_t *size, uint64_t address, void *info) |
960 | 183k | { |
961 | 183k | DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); |
962 | | |
963 | | //return status == MCDisassembler_Success; |
964 | 183k | return status != MCDisassembler_Fail; |
965 | 183k | } |
966 | | |
967 | | static const uint16_t GPRDecoderTable[] = { |
968 | | ARM_R0, ARM_R1, ARM_R2, ARM_R3, |
969 | | ARM_R4, ARM_R5, ARM_R6, ARM_R7, |
970 | | ARM_R8, ARM_R9, ARM_R10, ARM_R11, |
971 | | ARM_R12, ARM_SP, ARM_LR, ARM_PC |
972 | | }; |
973 | | |
974 | | static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
975 | | uint64_t Address, const void *Decoder) |
976 | 4.04M | { |
977 | 4.04M | unsigned Register; |
978 | | |
979 | 4.04M | if (RegNo > 15) |
980 | 26 | return MCDisassembler_Fail; |
981 | | |
982 | 4.04M | Register = GPRDecoderTable[RegNo]; |
983 | 4.04M | MCOperand_CreateReg0(Inst, Register); |
984 | | |
985 | 4.04M | return MCDisassembler_Success; |
986 | 4.04M | } |
987 | | |
988 | | static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, |
989 | | uint64_t Address, const void *Decoder) |
990 | 170k | { |
991 | 170k | DecodeStatus S = MCDisassembler_Success; |
992 | | |
993 | 170k | if (RegNo == 15) |
994 | 33.8k | S = MCDisassembler_SoftFail; |
995 | | |
996 | 170k | Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
997 | | |
998 | 170k | return S; |
999 | 170k | } |
1000 | | |
1001 | | static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, |
1002 | | uint64_t Address, const void *Decoder) |
1003 | 7.71k | { |
1004 | 7.71k | DecodeStatus S = MCDisassembler_Success; |
1005 | | |
1006 | 7.71k | if (RegNo == 15) { |
1007 | 2.53k | MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); |
1008 | | |
1009 | 2.53k | return MCDisassembler_Success; |
1010 | 2.53k | } |
1011 | | |
1012 | 5.17k | Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
1013 | 5.17k | return S; |
1014 | 7.71k | } |
1015 | | |
1016 | | static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1017 | | uint64_t Address, const void *Decoder) |
1018 | 2.33M | { |
1019 | 2.33M | if (RegNo > 7) |
1020 | 0 | return MCDisassembler_Fail; |
1021 | | |
1022 | 2.33M | return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); |
1023 | 2.33M | } |
1024 | | |
1025 | | static const uint16_t GPRPairDecoderTable[] = { |
1026 | | ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, |
1027 | | ARM_R8_R9, ARM_R10_R11, ARM_R12_SP |
1028 | | }; |
1029 | | |
1030 | | static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, |
1031 | | uint64_t Address, const void *Decoder) |
1032 | 784 | { |
1033 | 784 | unsigned RegisterPair; |
1034 | 784 | DecodeStatus S = MCDisassembler_Success; |
1035 | | |
1036 | 784 | if (RegNo > 13) |
1037 | 3 | return MCDisassembler_Fail; |
1038 | | |
1039 | 781 | if ((RegNo & 1) || RegNo == 0xe) |
1040 | 394 | S = MCDisassembler_SoftFail; |
1041 | | |
1042 | 781 | RegisterPair = GPRPairDecoderTable[RegNo / 2]; |
1043 | 781 | MCOperand_CreateReg0(Inst, RegisterPair); |
1044 | | |
1045 | 781 | return S; |
1046 | 784 | } |
1047 | | |
1048 | | static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1049 | | uint64_t Address, const void *Decoder) |
1050 | 273 | { |
1051 | 273 | unsigned Register = 0; |
1052 | | |
1053 | 273 | switch (RegNo) { |
1054 | 186 | case 0: |
1055 | 186 | Register = ARM_R0; |
1056 | 186 | break; |
1057 | 66 | case 1: |
1058 | 66 | Register = ARM_R1; |
1059 | 66 | break; |
1060 | 4 | case 2: |
1061 | 4 | Register = ARM_R2; |
1062 | 4 | break; |
1063 | 0 | case 3: |
1064 | 0 | Register = ARM_R3; |
1065 | 0 | break; |
1066 | 7 | case 9: |
1067 | 7 | Register = ARM_R9; |
1068 | 7 | break; |
1069 | 0 | case 12: |
1070 | 0 | Register = ARM_R12; |
1071 | 0 | break; |
1072 | 10 | default: |
1073 | 10 | return MCDisassembler_Fail; |
1074 | 273 | } |
1075 | | |
1076 | 263 | MCOperand_CreateReg0(Inst, Register); |
1077 | | |
1078 | 263 | return MCDisassembler_Success; |
1079 | 273 | } |
1080 | | |
1081 | | static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1082 | | uint64_t Address, const void *Decoder) |
1083 | 259k | { |
1084 | 259k | DecodeStatus S = MCDisassembler_Success; |
1085 | | |
1086 | 259k | if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || RegNo == 15) |
1087 | 74.7k | S = MCDisassembler_SoftFail; |
1088 | | |
1089 | 259k | Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
1090 | | |
1091 | 259k | return S; |
1092 | 259k | } |
1093 | | |
1094 | | static const uint16_t SPRDecoderTable[] = { |
1095 | | ARM_S0, ARM_S1, ARM_S2, ARM_S3, |
1096 | | ARM_S4, ARM_S5, ARM_S6, ARM_S7, |
1097 | | ARM_S8, ARM_S9, ARM_S10, ARM_S11, |
1098 | | ARM_S12, ARM_S13, ARM_S14, ARM_S15, |
1099 | | ARM_S16, ARM_S17, ARM_S18, ARM_S19, |
1100 | | ARM_S20, ARM_S21, ARM_S22, ARM_S23, |
1101 | | ARM_S24, ARM_S25, ARM_S26, ARM_S27, |
1102 | | ARM_S28, ARM_S29, ARM_S30, ARM_S31 |
1103 | | }; |
1104 | | |
1105 | | static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1106 | | uint64_t Address, const void *Decoder) |
1107 | 74.5k | { |
1108 | 74.5k | unsigned Register; |
1109 | | |
1110 | 74.5k | if (RegNo > 31) |
1111 | 6 | return MCDisassembler_Fail; |
1112 | | |
1113 | 74.5k | Register = SPRDecoderTable[RegNo]; |
1114 | 74.5k | MCOperand_CreateReg0(Inst, Register); |
1115 | | |
1116 | 74.5k | return MCDisassembler_Success; |
1117 | 74.5k | } |
1118 | | |
1119 | | static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1120 | | uint64_t Address, const void *Decoder) |
1121 | 15.4k | { |
1122 | 15.4k | return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); |
1123 | 15.4k | } |
1124 | | |
1125 | | static const uint16_t DPRDecoderTable[] = { |
1126 | | ARM_D0, ARM_D1, ARM_D2, ARM_D3, |
1127 | | ARM_D4, ARM_D5, ARM_D6, ARM_D7, |
1128 | | ARM_D8, ARM_D9, ARM_D10, ARM_D11, |
1129 | | ARM_D12, ARM_D13, ARM_D14, ARM_D15, |
1130 | | ARM_D16, ARM_D17, ARM_D18, ARM_D19, |
1131 | | ARM_D20, ARM_D21, ARM_D22, ARM_D23, |
1132 | | ARM_D24, ARM_D25, ARM_D26, ARM_D27, |
1133 | | ARM_D28, ARM_D29, ARM_D30, ARM_D31 |
1134 | | }; |
1135 | | |
1136 | | static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1137 | | uint64_t Address, const void *Decoder) |
1138 | 191k | { |
1139 | 191k | unsigned Register; |
1140 | | |
1141 | 191k | if (RegNo > 31 || (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD16) && RegNo > 15)) |
1142 | 20 | return MCDisassembler_Fail; |
1143 | | |
1144 | 191k | Register = DPRDecoderTable[RegNo]; |
1145 | 191k | MCOperand_CreateReg0(Inst, Register); |
1146 | | |
1147 | 191k | return MCDisassembler_Success; |
1148 | 191k | } |
1149 | | |
1150 | | static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, |
1151 | | uint64_t Address, const void *Decoder) |
1152 | 2.77k | { |
1153 | 2.77k | if (RegNo > 7) |
1154 | 0 | return MCDisassembler_Fail; |
1155 | | |
1156 | 2.77k | return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); |
1157 | 2.77k | } |
1158 | | |
1159 | | static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, |
1160 | | uint64_t Address, const void *Decoder) |
1161 | 4.66k | { |
1162 | 4.66k | if (RegNo > 15) |
1163 | 0 | return MCDisassembler_Fail; |
1164 | | |
1165 | 4.66k | return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); |
1166 | 4.66k | } |
1167 | | |
1168 | | static const uint16_t QPRDecoderTable[] = { |
1169 | | ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, |
1170 | | ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, |
1171 | | ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, |
1172 | | ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 |
1173 | | }; |
1174 | | |
1175 | | static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1176 | | uint64_t Address, const void *Decoder) |
1177 | 57.9k | { |
1178 | 57.9k | unsigned Register; |
1179 | | |
1180 | 57.9k | if (RegNo > 31 || (RegNo & 1) != 0) |
1181 | 2.53k | return MCDisassembler_Fail; |
1182 | | |
1183 | 55.3k | RegNo >>= 1; |
1184 | | |
1185 | 55.3k | Register = QPRDecoderTable[RegNo]; |
1186 | 55.3k | MCOperand_CreateReg0(Inst, Register); |
1187 | | |
1188 | 55.3k | return MCDisassembler_Success; |
1189 | 57.9k | } |
1190 | | |
1191 | | static const uint16_t DPairDecoderTable[] = { |
1192 | | ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, |
1193 | | ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, |
1194 | | ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, |
1195 | | ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, |
1196 | | ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, |
1197 | | ARM_Q15 |
1198 | | }; |
1199 | | |
1200 | | static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, |
1201 | | uint64_t Address, const void *Decoder) |
1202 | 15.1k | { |
1203 | 15.1k | unsigned Register; |
1204 | | |
1205 | 15.1k | if (RegNo > 30) |
1206 | 14 | return MCDisassembler_Fail; |
1207 | | |
1208 | 15.0k | Register = DPairDecoderTable[RegNo]; |
1209 | 15.0k | MCOperand_CreateReg0(Inst, Register); |
1210 | | |
1211 | 15.0k | return MCDisassembler_Success; |
1212 | 15.1k | } |
1213 | | |
1214 | | static const uint16_t DPairSpacedDecoderTable[] = { |
1215 | | ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, |
1216 | | ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, |
1217 | | ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, |
1218 | | ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, |
1219 | | ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, |
1220 | | ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, |
1221 | | ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, |
1222 | | ARM_D28_D30, ARM_D29_D31 |
1223 | | }; |
1224 | | |
1225 | | static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, |
1226 | | unsigned RegNo, uint64_t Address, const void *Decoder) |
1227 | 9.43k | { |
1228 | 9.43k | unsigned Register; |
1229 | | |
1230 | 9.43k | if (RegNo > 29) |
1231 | 24 | return MCDisassembler_Fail; |
1232 | | |
1233 | 9.41k | Register = DPairSpacedDecoderTable[RegNo]; |
1234 | 9.41k | MCOperand_CreateReg0(Inst, Register); |
1235 | | |
1236 | 9.41k | return MCDisassembler_Success; |
1237 | 9.43k | } |
1238 | | |
1239 | | static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, |
1240 | | uint64_t Address, const void *Decoder) |
1241 | 92.3k | { |
1242 | 92.3k | if (Val) |
1243 | 33.2k | MCOperand_CreateReg0(Inst, ARM_CPSR); |
1244 | 59.1k | else |
1245 | 59.1k | MCOperand_CreateReg0(Inst, 0); |
1246 | | |
1247 | 92.3k | return MCDisassembler_Success; |
1248 | 92.3k | } |
1249 | | |
1250 | | static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, |
1251 | | uint64_t Address, const void *Decoder) |
1252 | 34.8k | { |
1253 | 34.8k | DecodeStatus S = MCDisassembler_Success; |
1254 | 34.8k | ARM_AM_ShiftOpc Shift; |
1255 | 34.8k | unsigned Op; |
1256 | 34.8k | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
1257 | 34.8k | unsigned type = fieldFromInstruction_4(Val, 5, 2); |
1258 | 34.8k | unsigned imm = fieldFromInstruction_4(Val, 7, 5); |
1259 | | |
1260 | | // Register-immediate |
1261 | 34.8k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
1262 | 0 | return MCDisassembler_Fail; |
1263 | | |
1264 | 34.8k | Shift = ARM_AM_lsl; |
1265 | 34.8k | switch (type) { |
1266 | 11.2k | case 0: |
1267 | 11.2k | Shift = ARM_AM_lsl; |
1268 | 11.2k | break; |
1269 | 5.66k | case 1: |
1270 | 5.66k | Shift = ARM_AM_lsr; |
1271 | 5.66k | break; |
1272 | 7.99k | case 2: |
1273 | 7.99k | Shift = ARM_AM_asr; |
1274 | 7.99k | break; |
1275 | 9.94k | case 3: |
1276 | 9.94k | Shift = ARM_AM_ror; |
1277 | 9.94k | break; |
1278 | 34.8k | } |
1279 | | |
1280 | 34.8k | if (Shift == ARM_AM_ror && imm == 0) |
1281 | 1.95k | Shift = ARM_AM_rrx; |
1282 | | |
1283 | 34.8k | Op = Shift | (imm << 3); |
1284 | 34.8k | MCOperand_CreateImm0(Inst, Op); |
1285 | | |
1286 | 34.8k | return S; |
1287 | 34.8k | } |
1288 | | |
1289 | | static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, |
1290 | | uint64_t Address, const void *Decoder) |
1291 | 12.4k | { |
1292 | 12.4k | DecodeStatus S = MCDisassembler_Success; |
1293 | 12.4k | ARM_AM_ShiftOpc Shift; |
1294 | | |
1295 | 12.4k | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
1296 | 12.4k | unsigned type = fieldFromInstruction_4(Val, 5, 2); |
1297 | 12.4k | unsigned Rs = fieldFromInstruction_4(Val, 8, 4); |
1298 | | |
1299 | | // Register-register |
1300 | 12.4k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
1301 | 0 | return MCDisassembler_Fail; |
1302 | 12.4k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) |
1303 | 0 | return MCDisassembler_Fail; |
1304 | | |
1305 | 12.4k | Shift = ARM_AM_lsl; |
1306 | 12.4k | switch (type) { |
1307 | 3.22k | case 0: |
1308 | 3.22k | Shift = ARM_AM_lsl; |
1309 | 3.22k | break; |
1310 | 2.00k | case 1: |
1311 | 2.00k | Shift = ARM_AM_lsr; |
1312 | 2.00k | break; |
1313 | 3.58k | case 2: |
1314 | 3.58k | Shift = ARM_AM_asr; |
1315 | 3.58k | break; |
1316 | 3.59k | case 3: |
1317 | 3.59k | Shift = ARM_AM_ror; |
1318 | 3.59k | break; |
1319 | 12.4k | } |
1320 | | |
1321 | 12.4k | MCOperand_CreateImm0(Inst, Shift); |
1322 | | |
1323 | 12.4k | return S; |
1324 | 12.4k | } |
1325 | | |
1326 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, |
1327 | | uint64_t Address, const void *Decoder) |
1328 | 38.1k | { |
1329 | 38.1k | unsigned i; |
1330 | 38.1k | DecodeStatus S = MCDisassembler_Success; |
1331 | 38.1k | unsigned opcode; |
1332 | 38.1k | bool NeedDisjointWriteback = false; |
1333 | 38.1k | unsigned WritebackReg = 0; |
1334 | | |
1335 | 38.1k | opcode = MCInst_getOpcode(Inst); |
1336 | 38.1k | switch (opcode) { |
1337 | 33.8k | default: |
1338 | 33.8k | break; |
1339 | | |
1340 | 33.8k | case ARM_LDMIA_UPD: |
1341 | 859 | case ARM_LDMDB_UPD: |
1342 | 1.51k | case ARM_LDMIB_UPD: |
1343 | 1.95k | case ARM_LDMDA_UPD: |
1344 | 2.53k | case ARM_t2LDMIA_UPD: |
1345 | 2.90k | case ARM_t2LDMDB_UPD: |
1346 | 3.21k | case ARM_t2STMIA_UPD: |
1347 | 4.26k | case ARM_t2STMDB_UPD: |
1348 | 4.26k | NeedDisjointWriteback = true; |
1349 | 4.26k | WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); |
1350 | 4.26k | break; |
1351 | 38.1k | } |
1352 | | |
1353 | | // Empty register lists are not allowed. |
1354 | 38.1k | if (Val == 0) return MCDisassembler_Fail; |
1355 | | |
1356 | 646k | for (i = 0; i < 16; ++i) { |
1357 | 608k | if (Val & (1 << i)) { |
1358 | 199k | if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) |
1359 | 0 | return MCDisassembler_Fail; |
1360 | | |
1361 | | // Writeback not allowed if Rn is in the target list. |
1362 | 199k | if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1]))) |
1363 | 1.12k | Check(&S, MCDisassembler_SoftFail); |
1364 | 199k | } |
1365 | 608k | } |
1366 | | |
1367 | 38.0k | return S; |
1368 | 38.0k | } |
1369 | | |
1370 | | static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, |
1371 | | uint64_t Address, const void *Decoder) |
1372 | 2.72k | { |
1373 | 2.72k | DecodeStatus S = MCDisassembler_Success; |
1374 | 2.72k | unsigned i; |
1375 | 2.72k | unsigned Vd = fieldFromInstruction_4(Val, 8, 5); |
1376 | 2.72k | unsigned regs = fieldFromInstruction_4(Val, 0, 8); |
1377 | | |
1378 | | // In case of unpredictable encoding, tweak the operands. |
1379 | 2.72k | if (regs == 0 || (Vd + regs) > 32) { |
1380 | 1.83k | regs = Vd + regs > 32 ? 32 - Vd : regs; |
1381 | 1.83k | regs = (1u > regs? 1u : regs); |
1382 | 1.83k | S = MCDisassembler_SoftFail; |
1383 | 1.83k | } |
1384 | | |
1385 | 2.72k | if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) |
1386 | 0 | return MCDisassembler_Fail; |
1387 | | |
1388 | 26.2k | for (i = 0; i < (regs - 1); ++i) { |
1389 | 23.4k | if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) |
1390 | 0 | return MCDisassembler_Fail; |
1391 | 23.4k | } |
1392 | | |
1393 | 2.72k | return S; |
1394 | 2.72k | } |
1395 | | |
1396 | | static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, |
1397 | | uint64_t Address, const void *Decoder) |
1398 | 2.19k | { |
1399 | 2.19k | DecodeStatus S = MCDisassembler_Success; |
1400 | 2.19k | unsigned i; |
1401 | 2.19k | unsigned Vd = fieldFromInstruction_4(Val, 8, 5); |
1402 | 2.19k | unsigned regs = fieldFromInstruction_4(Val, 1, 7); |
1403 | | |
1404 | | // In case of unpredictable encoding, tweak the operands. |
1405 | 2.19k | if (regs == 0 || regs > 16 || (Vd + regs) > 32) { |
1406 | 1.75k | regs = Vd + regs > 32 ? 32 - Vd : regs; |
1407 | 1.75k | regs = (1u > regs? 1u : regs); |
1408 | 1.75k | regs = (16u > regs? regs : 16u); |
1409 | 1.75k | S = MCDisassembler_SoftFail; |
1410 | 1.75k | } |
1411 | | |
1412 | 2.19k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
1413 | 0 | return MCDisassembler_Fail; |
1414 | | |
1415 | 20.6k | for (i = 0; i < (regs - 1); ++i) { |
1416 | 18.4k | if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) |
1417 | 0 | return MCDisassembler_Fail; |
1418 | 18.4k | } |
1419 | | |
1420 | 2.19k | return S; |
1421 | 2.19k | } |
1422 | | |
1423 | | static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, |
1424 | | uint64_t Address, const void *Decoder) |
1425 | 2.16k | { |
1426 | | // This operand encodes a mask of contiguous zeros between a specified MSB |
1427 | | // and LSB. To decode it, we create the mask of all bits MSB-and-lower, |
1428 | | // the mask of all bits LSB-and-lower, and then xor them to create |
1429 | | // the mask of that's all ones on [msb, lsb]. Finally we not it to |
1430 | | // create the final mask. |
1431 | 2.16k | unsigned msb = fieldFromInstruction_4(Val, 5, 5); |
1432 | 2.16k | unsigned lsb = fieldFromInstruction_4(Val, 0, 5); |
1433 | 2.16k | uint32_t lsb_mask, msb_mask; |
1434 | | |
1435 | 2.16k | DecodeStatus S = MCDisassembler_Success; |
1436 | 2.16k | if (lsb > msb) { |
1437 | 769 | Check(&S, MCDisassembler_SoftFail); |
1438 | | // The check above will cause the warning for the "potentially undefined |
1439 | | // instruction encoding" but we can't build a bad MCOperand value here |
1440 | | // with a lsb > msb or else printing the MCInst will cause a crash. |
1441 | 769 | lsb = msb; |
1442 | 769 | } |
1443 | | |
1444 | 2.16k | msb_mask = 0xFFFFFFFF; |
1445 | 2.16k | if (msb != 31) msb_mask = (1U << (msb + 1)) - 1; |
1446 | 2.16k | lsb_mask = (1U << lsb) - 1; |
1447 | | |
1448 | 2.16k | MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); |
1449 | 2.16k | return S; |
1450 | 2.16k | } |
1451 | | |
1452 | | static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, |
1453 | | uint64_t Address, const void *Decoder) |
1454 | 29.0k | { |
1455 | 29.0k | DecodeStatus S = MCDisassembler_Success; |
1456 | | |
1457 | 29.0k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
1458 | 29.0k | unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); |
1459 | 29.0k | unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); |
1460 | 29.0k | unsigned imm = fieldFromInstruction_4(Insn, 0, 8); |
1461 | 29.0k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
1462 | 29.0k | unsigned U = fieldFromInstruction_4(Insn, 23, 1); |
1463 | | |
1464 | 29.0k | switch (MCInst_getOpcode(Inst)) { |
1465 | 1.22k | case ARM_LDC_OFFSET: |
1466 | 1.69k | case ARM_LDC_PRE: |
1467 | 2.27k | case ARM_LDC_POST: |
1468 | 2.76k | case ARM_LDC_OPTION: |
1469 | 3.23k | case ARM_LDCL_OFFSET: |
1470 | 3.89k | case ARM_LDCL_PRE: |
1471 | 5.02k | case ARM_LDCL_POST: |
1472 | 5.55k | case ARM_LDCL_OPTION: |
1473 | 6.76k | case ARM_STC_OFFSET: |
1474 | 7.37k | case ARM_STC_PRE: |
1475 | 7.86k | case ARM_STC_POST: |
1476 | 8.38k | case ARM_STC_OPTION: |
1477 | 8.81k | case ARM_STCL_OFFSET: |
1478 | 9.51k | case ARM_STCL_PRE: |
1479 | 10.2k | case ARM_STCL_POST: |
1480 | 10.4k | case ARM_STCL_OPTION: |
1481 | 10.9k | case ARM_t2LDC_OFFSET: |
1482 | 11.1k | case ARM_t2LDC_PRE: |
1483 | 11.4k | case ARM_t2LDC_POST: |
1484 | 11.8k | case ARM_t2LDC_OPTION: |
1485 | 12.3k | case ARM_t2LDCL_OFFSET: |
1486 | 12.6k | case ARM_t2LDCL_PRE: |
1487 | 13.1k | case ARM_t2LDCL_POST: |
1488 | 13.3k | case ARM_t2LDCL_OPTION: |
1489 | 13.6k | case ARM_t2STC_OFFSET: |
1490 | 14.0k | case ARM_t2STC_PRE: |
1491 | 14.3k | case ARM_t2STC_POST: |
1492 | 14.7k | case ARM_t2STC_OPTION: |
1493 | 14.9k | case ARM_t2STCL_OFFSET: |
1494 | 16.2k | case ARM_t2STCL_PRE: |
1495 | 16.6k | case ARM_t2STCL_POST: |
1496 | 16.8k | case ARM_t2STCL_OPTION: |
1497 | 16.8k | if (coproc == 0xA || coproc == 0xB) |
1498 | 11 | return MCDisassembler_Fail; |
1499 | 16.8k | break; |
1500 | 16.8k | default: |
1501 | 12.2k | break; |
1502 | 29.0k | } |
1503 | | |
1504 | 29.0k | if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14)) |
1505 | 32 | return MCDisassembler_Fail; |
1506 | | |
1507 | 28.9k | MCOperand_CreateImm0(Inst, coproc); |
1508 | 28.9k | MCOperand_CreateImm0(Inst, CRd); |
1509 | 28.9k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1510 | 0 | return MCDisassembler_Fail; |
1511 | | |
1512 | 28.9k | switch (MCInst_getOpcode(Inst)) { |
1513 | 247 | case ARM_t2LDC2_OFFSET: |
1514 | 1.04k | case ARM_t2LDC2L_OFFSET: |
1515 | 1.31k | case ARM_t2LDC2_PRE: |
1516 | 1.63k | case ARM_t2LDC2L_PRE: |
1517 | 2.40k | case ARM_t2STC2_OFFSET: |
1518 | 2.78k | case ARM_t2STC2L_OFFSET: |
1519 | 3.22k | case ARM_t2STC2_PRE: |
1520 | 3.93k | case ARM_t2STC2L_PRE: |
1521 | 4.03k | case ARM_LDC2_OFFSET: |
1522 | 4.44k | case ARM_LDC2L_OFFSET: |
1523 | 4.54k | case ARM_LDC2_PRE: |
1524 | 5.09k | case ARM_LDC2L_PRE: |
1525 | 5.48k | case ARM_STC2_OFFSET: |
1526 | 5.78k | case ARM_STC2L_OFFSET: |
1527 | 6.37k | case ARM_STC2_PRE: |
1528 | 6.68k | case ARM_STC2L_PRE: |
1529 | 7.12k | case ARM_t2LDC_OFFSET: |
1530 | 7.56k | case ARM_t2LDCL_OFFSET: |
1531 | 7.79k | case ARM_t2LDC_PRE: |
1532 | 8.15k | case ARM_t2LDCL_PRE: |
1533 | 8.51k | case ARM_t2STC_OFFSET: |
1534 | 8.75k | case ARM_t2STCL_OFFSET: |
1535 | 9.11k | case ARM_t2STC_PRE: |
1536 | 10.3k | case ARM_t2STCL_PRE: |
1537 | 11.5k | case ARM_LDC_OFFSET: |
1538 | 12.0k | case ARM_LDCL_OFFSET: |
1539 | 12.5k | case ARM_LDC_PRE: |
1540 | 13.1k | case ARM_LDCL_PRE: |
1541 | 14.3k | case ARM_STC_OFFSET: |
1542 | 14.7k | case ARM_STCL_OFFSET: |
1543 | 15.4k | case ARM_STC_PRE: |
1544 | 16.1k | case ARM_STCL_PRE: |
1545 | 16.1k | imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); |
1546 | 16.1k | MCOperand_CreateImm0(Inst, imm); |
1547 | 16.1k | break; |
1548 | 340 | case ARM_t2LDC2_POST: |
1549 | 1.19k | case ARM_t2LDC2L_POST: |
1550 | 1.81k | case ARM_t2STC2_POST: |
1551 | 2.22k | case ARM_t2STC2L_POST: |
1552 | 2.67k | case ARM_LDC2_POST: |
1553 | 3.76k | case ARM_LDC2L_POST: |
1554 | 4.51k | case ARM_STC2_POST: |
1555 | 4.73k | case ARM_STC2L_POST: |
1556 | 5.05k | case ARM_t2LDC_POST: |
1557 | 5.56k | case ARM_t2LDCL_POST: |
1558 | 5.87k | case ARM_t2STC_POST: |
1559 | 6.28k | case ARM_t2STCL_POST: |
1560 | 6.86k | case ARM_LDC_POST: |
1561 | 7.98k | case ARM_LDCL_POST: |
1562 | 8.47k | case ARM_STC_POST: |
1563 | 9.21k | case ARM_STCL_POST: |
1564 | 9.21k | imm |= U << 8; |
1565 | | // fall through. |
1566 | 12.8k | default: |
1567 | | // The 'option' variant doesn't encode 'U' in the immediate since |
1568 | | // the immediate is unsigned [0,255]. |
1569 | 12.8k | MCOperand_CreateImm0(Inst, imm); |
1570 | 12.8k | break; |
1571 | 28.9k | } |
1572 | | |
1573 | 28.9k | switch (MCInst_getOpcode(Inst)) { |
1574 | 1.21k | case ARM_LDC_OFFSET: |
1575 | 1.69k | case ARM_LDC_PRE: |
1576 | 2.27k | case ARM_LDC_POST: |
1577 | 2.76k | case ARM_LDC_OPTION: |
1578 | 3.22k | case ARM_LDCL_OFFSET: |
1579 | 3.87k | case ARM_LDCL_PRE: |
1580 | 5.00k | case ARM_LDCL_POST: |
1581 | 5.53k | case ARM_LDCL_OPTION: |
1582 | 6.74k | case ARM_STC_OFFSET: |
1583 | 7.34k | case ARM_STC_PRE: |
1584 | 7.83k | case ARM_STC_POST: |
1585 | 8.35k | case ARM_STC_OPTION: |
1586 | 8.78k | case ARM_STCL_OFFSET: |
1587 | 9.48k | case ARM_STCL_PRE: |
1588 | 10.2k | case ARM_STCL_POST: |
1589 | 10.4k | case ARM_STCL_OPTION: |
1590 | 10.4k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
1591 | 1 | return MCDisassembler_Fail; |
1592 | 10.4k | break; |
1593 | 18.5k | default: |
1594 | 18.5k | break; |
1595 | 28.9k | } |
1596 | | |
1597 | 28.9k | return S; |
1598 | 28.9k | } |
1599 | | |
1600 | | static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, |
1601 | | uint64_t Address, const void *Decoder) |
1602 | 22.4k | { |
1603 | 22.4k | DecodeStatus S = MCDisassembler_Success; |
1604 | 22.4k | ARM_AM_AddrOpc Op; |
1605 | 22.4k | ARM_AM_ShiftOpc Opc; |
1606 | 22.4k | bool writeback; |
1607 | 22.4k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
1608 | 22.4k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
1609 | 22.4k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
1610 | 22.4k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
1611 | 22.4k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
1612 | 22.4k | unsigned reg = fieldFromInstruction_4(Insn, 25, 1); |
1613 | 22.4k | unsigned P = fieldFromInstruction_4(Insn, 24, 1); |
1614 | 22.4k | unsigned W = fieldFromInstruction_4(Insn, 21, 1); |
1615 | 22.4k | unsigned idx_mode = 0, amt, tmp; |
1616 | | |
1617 | | // On stores, the writeback operand precedes Rt. |
1618 | 22.4k | switch (MCInst_getOpcode(Inst)) { |
1619 | 2.80k | case ARM_STR_POST_IMM: |
1620 | 4.14k | case ARM_STR_POST_REG: |
1621 | 5.73k | case ARM_STRB_POST_IMM: |
1622 | 6.74k | case ARM_STRB_POST_REG: |
1623 | 8.27k | case ARM_STRT_POST_REG: |
1624 | 10.4k | case ARM_STRT_POST_IMM: |
1625 | 11.7k | case ARM_STRBT_POST_REG: |
1626 | 13.4k | case ARM_STRBT_POST_IMM: |
1627 | 13.4k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1628 | 0 | return MCDisassembler_Fail; |
1629 | 13.4k | break; |
1630 | 13.4k | default: |
1631 | 8.92k | break; |
1632 | 22.4k | } |
1633 | | |
1634 | 22.4k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
1635 | 0 | return MCDisassembler_Fail; |
1636 | | |
1637 | | // On loads, the writeback operand comes after Rt. |
1638 | 22.4k | switch (MCInst_getOpcode(Inst)) { |
1639 | 1.57k | case ARM_LDR_POST_IMM: |
1640 | 2.37k | case ARM_LDR_POST_REG: |
1641 | 3.76k | case ARM_LDRB_POST_IMM: |
1642 | 4.45k | case ARM_LDRB_POST_REG: |
1643 | 5.16k | case ARM_LDRBT_POST_REG: |
1644 | 6.69k | case ARM_LDRBT_POST_IMM: |
1645 | 7.68k | case ARM_LDRT_POST_REG: |
1646 | 8.92k | case ARM_LDRT_POST_IMM: |
1647 | 8.92k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1648 | 0 | return MCDisassembler_Fail; |
1649 | 8.92k | break; |
1650 | 13.4k | default: |
1651 | 13.4k | break; |
1652 | 22.4k | } |
1653 | | |
1654 | 22.4k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1655 | 0 | return MCDisassembler_Fail; |
1656 | | |
1657 | 22.4k | Op = ARM_AM_add; |
1658 | 22.4k | if (!fieldFromInstruction_4(Insn, 23, 1)) |
1659 | 13.0k | Op = ARM_AM_sub; |
1660 | | |
1661 | 22.4k | writeback = (P == 0) || (W == 1); |
1662 | 22.4k | if (P && writeback) |
1663 | 0 | idx_mode = ARMII_IndexModePre; |
1664 | 22.4k | else if (!P && writeback) |
1665 | 22.4k | idx_mode = ARMII_IndexModePost; |
1666 | | |
1667 | 22.4k | if (writeback && (Rn == 15 || Rn == Rt)) |
1668 | 3.62k | S = MCDisassembler_SoftFail; // UNPREDICTABLE |
1669 | | |
1670 | 22.4k | if (reg) { |
1671 | 8.29k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
1672 | 0 | return MCDisassembler_Fail; |
1673 | | |
1674 | 8.29k | Opc = ARM_AM_lsl; |
1675 | 8.29k | switch(fieldFromInstruction_4(Insn, 5, 2)) { |
1676 | 3.26k | case 0: |
1677 | 3.26k | Opc = ARM_AM_lsl; |
1678 | 3.26k | break; |
1679 | 1.77k | case 1: |
1680 | 1.77k | Opc = ARM_AM_lsr; |
1681 | 1.77k | break; |
1682 | 1.41k | case 2: |
1683 | 1.41k | Opc = ARM_AM_asr; |
1684 | 1.41k | break; |
1685 | 1.84k | case 3: |
1686 | 1.84k | Opc = ARM_AM_ror; |
1687 | 1.84k | break; |
1688 | 0 | default: |
1689 | 0 | return MCDisassembler_Fail; |
1690 | 8.29k | } |
1691 | | |
1692 | 8.29k | amt = fieldFromInstruction_4(Insn, 7, 5); |
1693 | 8.29k | if (Opc == ARM_AM_ror && amt == 0) |
1694 | 311 | Opc = ARM_AM_rrx; |
1695 | | |
1696 | 8.29k | imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); |
1697 | | |
1698 | 8.29k | MCOperand_CreateImm0(Inst, imm); |
1699 | 14.1k | } else { |
1700 | 14.1k | MCOperand_CreateReg0(Inst, 0); |
1701 | 14.1k | tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); |
1702 | 14.1k | MCOperand_CreateImm0(Inst, tmp); |
1703 | 14.1k | } |
1704 | | |
1705 | 22.4k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
1706 | 2.64k | return MCDisassembler_Fail; |
1707 | | |
1708 | 19.7k | return S; |
1709 | 22.4k | } |
1710 | | |
1711 | | static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, |
1712 | | uint64_t Address, const void *Decoder) |
1713 | 8.72k | { |
1714 | 8.72k | DecodeStatus S = MCDisassembler_Success; |
1715 | 8.72k | ARM_AM_ShiftOpc ShOp; |
1716 | 8.72k | unsigned shift; |
1717 | 8.72k | unsigned Rn = fieldFromInstruction_4(Val, 13, 4); |
1718 | 8.72k | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
1719 | 8.72k | unsigned type = fieldFromInstruction_4(Val, 5, 2); |
1720 | 8.72k | unsigned imm = fieldFromInstruction_4(Val, 7, 5); |
1721 | 8.72k | unsigned U = fieldFromInstruction_4(Val, 12, 1); |
1722 | | |
1723 | 8.72k | ShOp = ARM_AM_lsl; |
1724 | 8.72k | switch (type) { |
1725 | 2.92k | case 0: |
1726 | 2.92k | ShOp = ARM_AM_lsl; |
1727 | 2.92k | break; |
1728 | 1.36k | case 1: |
1729 | 1.36k | ShOp = ARM_AM_lsr; |
1730 | 1.36k | break; |
1731 | 1.57k | case 2: |
1732 | 1.57k | ShOp = ARM_AM_asr; |
1733 | 1.57k | break; |
1734 | 2.84k | case 3: |
1735 | 2.84k | ShOp = ARM_AM_ror; |
1736 | 2.84k | break; |
1737 | 8.72k | } |
1738 | | |
1739 | 8.72k | if (ShOp == ARM_AM_ror && imm == 0) |
1740 | 393 | ShOp = ARM_AM_rrx; |
1741 | | |
1742 | 8.72k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1743 | 0 | return MCDisassembler_Fail; |
1744 | | |
1745 | 8.72k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
1746 | 0 | return MCDisassembler_Fail; |
1747 | | |
1748 | 8.72k | if (U) |
1749 | 4.14k | shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); |
1750 | 4.57k | else |
1751 | 4.57k | shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); |
1752 | | |
1753 | 8.72k | MCOperand_CreateImm0(Inst, shift); |
1754 | | |
1755 | 8.72k | return S; |
1756 | 8.72k | } |
1757 | | |
1758 | | static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, |
1759 | | uint64_t Address, const void *Decoder) |
1760 | 24.7k | { |
1761 | 24.7k | DecodeStatus S = MCDisassembler_Success; |
1762 | | |
1763 | 24.7k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
1764 | 24.7k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
1765 | 24.7k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
1766 | 24.7k | unsigned type = fieldFromInstruction_4(Insn, 22, 1); |
1767 | 24.7k | unsigned imm = fieldFromInstruction_4(Insn, 8, 4); |
1768 | 24.7k | unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; |
1769 | 24.7k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
1770 | 24.7k | unsigned W = fieldFromInstruction_4(Insn, 21, 1); |
1771 | 24.7k | unsigned P = fieldFromInstruction_4(Insn, 24, 1); |
1772 | 24.7k | unsigned Rt2 = Rt + 1; |
1773 | | |
1774 | 24.7k | bool writeback = (W == 1) | (P == 0); |
1775 | | |
1776 | | // For {LD,ST}RD, Rt must be even, else undefined. |
1777 | 24.7k | switch (MCInst_getOpcode(Inst)) { |
1778 | 930 | case ARM_STRD: |
1779 | 1.68k | case ARM_STRD_PRE: |
1780 | 4.07k | case ARM_STRD_POST: |
1781 | 5.20k | case ARM_LDRD: |
1782 | 5.97k | case ARM_LDRD_PRE: |
1783 | 8.55k | case ARM_LDRD_POST: |
1784 | 8.55k | if (Rt & 0x1) |
1785 | 2.10k | S = MCDisassembler_SoftFail; |
1786 | 8.55k | break; |
1787 | 16.2k | default: |
1788 | 16.2k | break; |
1789 | 24.7k | } |
1790 | | |
1791 | 24.7k | switch (MCInst_getOpcode(Inst)) { |
1792 | 930 | case ARM_STRD: |
1793 | 1.68k | case ARM_STRD_PRE: |
1794 | 4.07k | case ARM_STRD_POST: |
1795 | 4.07k | if (P == 0 && W == 1) |
1796 | 0 | S = MCDisassembler_SoftFail; |
1797 | | |
1798 | 4.07k | if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) |
1799 | 1.33k | S = MCDisassembler_SoftFail; |
1800 | | |
1801 | 4.07k | if (type && Rm == 15) |
1802 | 253 | S = MCDisassembler_SoftFail; |
1803 | | |
1804 | 4.07k | if (Rt2 == 15) |
1805 | 547 | S = MCDisassembler_SoftFail; |
1806 | | |
1807 | 4.07k | if (!type && fieldFromInstruction_4(Insn, 8, 4)) |
1808 | 1.94k | S = MCDisassembler_SoftFail; |
1809 | | |
1810 | 4.07k | break; |
1811 | | |
1812 | 1.42k | case ARM_STRH: |
1813 | 2.22k | case ARM_STRH_PRE: |
1814 | 4.77k | case ARM_STRH_POST: |
1815 | 4.77k | if (Rt == 15) |
1816 | 1.80k | S = MCDisassembler_SoftFail; |
1817 | | |
1818 | 4.77k | if (writeback && (Rn == 15 || Rn == Rt)) |
1819 | 744 | S = MCDisassembler_SoftFail; |
1820 | | |
1821 | 4.77k | if (!type && Rm == 15) |
1822 | 350 | S = MCDisassembler_SoftFail; |
1823 | | |
1824 | 4.77k | break; |
1825 | | |
1826 | 1.13k | case ARM_LDRD: |
1827 | 1.90k | case ARM_LDRD_PRE: |
1828 | 4.48k | case ARM_LDRD_POST: |
1829 | 4.48k | if (type && Rn == 15) { |
1830 | 818 | if (Rt2 == 15) |
1831 | 657 | S = MCDisassembler_SoftFail; |
1832 | 818 | break; |
1833 | 818 | } |
1834 | | |
1835 | 3.66k | if (P == 0 && W == 1) |
1836 | 0 | S = MCDisassembler_SoftFail; |
1837 | | |
1838 | 3.66k | if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) |
1839 | 1.45k | S = MCDisassembler_SoftFail; |
1840 | | |
1841 | 3.66k | if (!type && writeback && Rn == 15) |
1842 | 634 | S = MCDisassembler_SoftFail; |
1843 | | |
1844 | 3.66k | if (writeback && (Rn == Rt || Rn == Rt2)) |
1845 | 586 | S = MCDisassembler_SoftFail; |
1846 | | |
1847 | 3.66k | break; |
1848 | | |
1849 | 732 | case ARM_LDRH: |
1850 | 1.91k | case ARM_LDRH_PRE: |
1851 | 3.37k | case ARM_LDRH_POST: |
1852 | 3.37k | if (type && Rn == 15) { |
1853 | 725 | if (Rt == 15) |
1854 | 125 | S = MCDisassembler_SoftFail; |
1855 | 725 | break; |
1856 | 725 | } |
1857 | | |
1858 | 2.65k | if (Rt == 15) |
1859 | 166 | S = MCDisassembler_SoftFail; |
1860 | | |
1861 | 2.65k | if (!type && Rm == 15) |
1862 | 168 | S = MCDisassembler_SoftFail; |
1863 | | |
1864 | 2.65k | if (!type && writeback && (Rn == 15 || Rn == Rt)) |
1865 | 662 | S = MCDisassembler_SoftFail; |
1866 | 2.65k | break; |
1867 | | |
1868 | 693 | case ARM_LDRSH: |
1869 | 2.09k | case ARM_LDRSH_PRE: |
1870 | 3.27k | case ARM_LDRSH_POST: |
1871 | 4.92k | case ARM_LDRSB: |
1872 | 6.72k | case ARM_LDRSB_PRE: |
1873 | 8.09k | case ARM_LDRSB_POST: |
1874 | 8.09k | if (type && Rn == 15){ |
1875 | 649 | if (Rt == 15) |
1876 | 61 | S = MCDisassembler_SoftFail; |
1877 | 649 | break; |
1878 | 649 | } |
1879 | | |
1880 | 7.44k | if (type && (Rt == 15 || (writeback && Rn == Rt))) |
1881 | 690 | S = MCDisassembler_SoftFail; |
1882 | | |
1883 | 7.44k | if (!type && (Rt == 15 || Rm == 15)) |
1884 | 1.02k | S = MCDisassembler_SoftFail; |
1885 | | |
1886 | 7.44k | if (!type && writeback && (Rn == 15 || Rn == Rt)) |
1887 | 1.25k | S = MCDisassembler_SoftFail; |
1888 | | |
1889 | 7.44k | break; |
1890 | | |
1891 | 0 | default: |
1892 | 0 | break; |
1893 | 24.7k | } |
1894 | | |
1895 | 24.7k | if (writeback) { // Writeback |
1896 | 18.2k | Inst->writeback = true; |
1897 | | |
1898 | 18.2k | if (P) |
1899 | 6.71k | U |= ARMII_IndexModePre << 9; |
1900 | 11.5k | else |
1901 | 11.5k | U |= ARMII_IndexModePost << 9; |
1902 | | |
1903 | | // On stores, the writeback operand precedes Rt. |
1904 | 18.2k | switch (MCInst_getOpcode(Inst)) { |
1905 | 0 | case ARM_STRD: |
1906 | 758 | case ARM_STRD_PRE: |
1907 | 3.14k | case ARM_STRD_POST: |
1908 | 3.14k | case ARM_STRH: |
1909 | 3.94k | case ARM_STRH_PRE: |
1910 | 6.49k | case ARM_STRH_POST: |
1911 | 6.49k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1912 | 0 | return MCDisassembler_Fail; |
1913 | 6.49k | break; |
1914 | 11.7k | default: |
1915 | 11.7k | break; |
1916 | 18.2k | } |
1917 | 18.2k | } |
1918 | | |
1919 | 24.7k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
1920 | 0 | return MCDisassembler_Fail; |
1921 | | |
1922 | 24.7k | switch (MCInst_getOpcode(Inst)) { |
1923 | 930 | case ARM_STRD: |
1924 | 1.68k | case ARM_STRD_PRE: |
1925 | 4.07k | case ARM_STRD_POST: |
1926 | 5.20k | case ARM_LDRD: |
1927 | 5.97k | case ARM_LDRD_PRE: |
1928 | 8.55k | case ARM_LDRD_POST: |
1929 | 8.55k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) |
1930 | 26 | return MCDisassembler_Fail; |
1931 | 8.52k | break; |
1932 | 16.2k | default: |
1933 | 16.2k | break; |
1934 | 24.7k | } |
1935 | | |
1936 | 24.7k | if (writeback) { |
1937 | | // On loads, the writeback operand comes after Rt. |
1938 | 18.2k | switch (MCInst_getOpcode(Inst)) { |
1939 | 0 | case ARM_LDRD: |
1940 | 767 | case ARM_LDRD_PRE: |
1941 | 3.34k | case ARM_LDRD_POST: |
1942 | 3.34k | case ARM_LDRH: |
1943 | 4.52k | case ARM_LDRH_PRE: |
1944 | 5.98k | case ARM_LDRH_POST: |
1945 | 5.98k | case ARM_LDRSH: |
1946 | 7.39k | case ARM_LDRSH_PRE: |
1947 | 8.56k | case ARM_LDRSH_POST: |
1948 | 8.56k | case ARM_LDRSB: |
1949 | 10.3k | case ARM_LDRSB_PRE: |
1950 | 11.7k | case ARM_LDRSB_POST: |
1951 | 11.7k | case ARM_LDRHTr: |
1952 | 11.7k | case ARM_LDRSBTr: |
1953 | 11.7k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1954 | 0 | return MCDisassembler_Fail; |
1955 | 11.7k | break; |
1956 | 11.7k | default: |
1957 | 6.48k | break; |
1958 | 18.2k | } |
1959 | 18.2k | } |
1960 | | |
1961 | 24.7k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
1962 | 0 | return MCDisassembler_Fail; |
1963 | | |
1964 | 24.7k | if (type) { |
1965 | 10.7k | MCOperand_CreateReg0(Inst, 0); |
1966 | 10.7k | MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); |
1967 | 13.9k | } else { |
1968 | 13.9k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
1969 | 0 | return MCDisassembler_Fail; |
1970 | | |
1971 | 13.9k | MCOperand_CreateImm0(Inst, U); |
1972 | 13.9k | } |
1973 | | |
1974 | 24.7k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
1975 | 23 | return MCDisassembler_Fail; |
1976 | | |
1977 | 24.7k | return S; |
1978 | 24.7k | } |
1979 | | |
1980 | | static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, |
1981 | | uint64_t Address, const void *Decoder) |
1982 | 991 | { |
1983 | 991 | DecodeStatus S = MCDisassembler_Success; |
1984 | | |
1985 | 991 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
1986 | 991 | unsigned mode = fieldFromInstruction_4(Insn, 23, 2); |
1987 | | |
1988 | 991 | switch (mode) { |
1989 | 288 | case 0: |
1990 | 288 | mode = ARM_AM_da; |
1991 | 288 | break; |
1992 | 121 | case 1: |
1993 | 121 | mode = ARM_AM_ia; |
1994 | 121 | break; |
1995 | 416 | case 2: |
1996 | 416 | mode = ARM_AM_db; |
1997 | 416 | break; |
1998 | 166 | case 3: |
1999 | 166 | mode = ARM_AM_ib; |
2000 | 166 | break; |
2001 | 991 | } |
2002 | | |
2003 | 991 | MCOperand_CreateImm0(Inst, mode); |
2004 | | |
2005 | 991 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2006 | 0 | return MCDisassembler_Fail; |
2007 | | |
2008 | 991 | return S; |
2009 | 991 | } |
2010 | | |
2011 | | static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, |
2012 | | uint64_t Address, const void *Decoder) |
2013 | 1.29k | { |
2014 | 1.29k | DecodeStatus S = MCDisassembler_Success; |
2015 | | |
2016 | 1.29k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
2017 | 1.29k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
2018 | 1.29k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
2019 | 1.29k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2020 | | |
2021 | 1.29k | if (pred == 0xF) |
2022 | 959 | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
2023 | | |
2024 | 340 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
2025 | 0 | return MCDisassembler_Fail; |
2026 | | |
2027 | 340 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
2028 | 0 | return MCDisassembler_Fail; |
2029 | | |
2030 | 340 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
2031 | 0 | return MCDisassembler_Fail; |
2032 | | |
2033 | 340 | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2034 | 0 | return MCDisassembler_Fail; |
2035 | | |
2036 | 340 | return S; |
2037 | 340 | } |
2038 | | |
2039 | | static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, |
2040 | | unsigned Insn, uint64_t Address, const void *Decoder) |
2041 | 12.6k | { |
2042 | 12.6k | DecodeStatus S = MCDisassembler_Success; |
2043 | | |
2044 | 12.6k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
2045 | 12.6k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2046 | 12.6k | unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); |
2047 | | |
2048 | 12.6k | if (pred == 0xF) { |
2049 | | // Ambiguous with RFE and SRS |
2050 | 1.02k | switch (MCInst_getOpcode(Inst)) { |
2051 | 0 | case ARM_LDMDA: |
2052 | 0 | MCInst_setOpcode(Inst, ARM_RFEDA); |
2053 | 0 | break; |
2054 | 288 | case ARM_LDMDA_UPD: |
2055 | 288 | MCInst_setOpcode(Inst, ARM_RFEDA_UPD); |
2056 | 288 | break; |
2057 | 0 | case ARM_LDMDB: |
2058 | 0 | MCInst_setOpcode(Inst, ARM_RFEDB); |
2059 | 0 | break; |
2060 | 416 | case ARM_LDMDB_UPD: |
2061 | 416 | MCInst_setOpcode(Inst, ARM_RFEDB_UPD); |
2062 | 416 | break; |
2063 | 0 | case ARM_LDMIA: |
2064 | 0 | MCInst_setOpcode(Inst, ARM_RFEIA); |
2065 | 0 | break; |
2066 | 121 | case ARM_LDMIA_UPD: |
2067 | 121 | MCInst_setOpcode(Inst, ARM_RFEIA_UPD); |
2068 | 121 | break; |
2069 | 0 | case ARM_LDMIB: |
2070 | 0 | MCInst_setOpcode(Inst, ARM_RFEIB); |
2071 | 0 | break; |
2072 | 166 | case ARM_LDMIB_UPD: |
2073 | 166 | MCInst_setOpcode(Inst, ARM_RFEIB_UPD); |
2074 | 166 | break; |
2075 | 0 | case ARM_STMDA: |
2076 | 0 | MCInst_setOpcode(Inst, ARM_SRSDA); |
2077 | 0 | break; |
2078 | 2 | case ARM_STMDA_UPD: |
2079 | 2 | MCInst_setOpcode(Inst, ARM_SRSDA_UPD); |
2080 | 2 | break; |
2081 | 0 | case ARM_STMDB: |
2082 | 0 | MCInst_setOpcode(Inst, ARM_SRSDB); |
2083 | 0 | break; |
2084 | 5 | case ARM_STMDB_UPD: |
2085 | 5 | MCInst_setOpcode(Inst, ARM_SRSDB_UPD); |
2086 | 5 | break; |
2087 | 0 | case ARM_STMIA: |
2088 | 0 | MCInst_setOpcode(Inst, ARM_SRSIA); |
2089 | 0 | break; |
2090 | 4 | case ARM_STMIA_UPD: |
2091 | 4 | MCInst_setOpcode(Inst, ARM_SRSIA_UPD); |
2092 | 4 | break; |
2093 | 0 | case ARM_STMIB: |
2094 | 0 | MCInst_setOpcode(Inst, ARM_SRSIB); |
2095 | 0 | break; |
2096 | 4 | case ARM_STMIB_UPD: |
2097 | 4 | MCInst_setOpcode(Inst, ARM_SRSIB_UPD); |
2098 | 4 | break; |
2099 | 22 | default: |
2100 | 22 | return MCDisassembler_Fail; |
2101 | 1.02k | } |
2102 | | |
2103 | | // For stores (which become SRS's, the only operand is the mode. |
2104 | 1.00k | if (fieldFromInstruction_4(Insn, 20, 1) == 0) { |
2105 | | // Check SRS encoding constraints |
2106 | 15 | if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && |
2107 | 15 | fieldFromInstruction_4(Insn, 20, 1) == 0)) |
2108 | 15 | return MCDisassembler_Fail; |
2109 | | |
2110 | 0 | MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); |
2111 | 0 | return S; |
2112 | 15 | } |
2113 | | |
2114 | 991 | return DecodeRFEInstruction(Inst, Insn, Address, Decoder); |
2115 | 1.00k | } |
2116 | | |
2117 | 11.6k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2118 | 0 | return MCDisassembler_Fail; |
2119 | | |
2120 | 11.6k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2121 | 0 | return MCDisassembler_Fail; // Tied |
2122 | | |
2123 | 11.6k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2124 | 0 | return MCDisassembler_Fail; |
2125 | | |
2126 | 11.6k | if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) |
2127 | 13 | return MCDisassembler_Fail; |
2128 | | |
2129 | 11.6k | return S; |
2130 | 11.6k | } |
2131 | | |
2132 | | // Check for UNPREDICTABLE predicated ESB instruction |
2133 | | static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, |
2134 | | uint64_t Address, const void *Decoder) |
2135 | 614 | { |
2136 | 614 | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2137 | 614 | unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); |
2138 | 614 | DecodeStatus result = MCDisassembler_Success; |
2139 | | |
2140 | 614 | MCOperand_CreateImm0(Inst, imm8); |
2141 | | |
2142 | 614 | if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2143 | 68 | return MCDisassembler_Fail; |
2144 | | |
2145 | | // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, |
2146 | | // so all predicates should be allowed. |
2147 | 546 | if (imm8 == 0x10 && pred != 0xe && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) |
2148 | 34 | result = MCDisassembler_SoftFail; |
2149 | | |
2150 | 546 | return result; |
2151 | 614 | } |
2152 | | |
2153 | | static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, |
2154 | | uint64_t Address, const void *Decoder) |
2155 | 4.32k | { |
2156 | 4.32k | unsigned imod = fieldFromInstruction_4(Insn, 18, 2); |
2157 | 4.32k | unsigned M = fieldFromInstruction_4(Insn, 17, 1); |
2158 | 4.32k | unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); |
2159 | 4.32k | unsigned mode = fieldFromInstruction_4(Insn, 0, 5); |
2160 | | |
2161 | 4.32k | DecodeStatus S = MCDisassembler_Success; |
2162 | | |
2163 | | // This decoder is called from multiple location that do not check |
2164 | | // the full encoding is valid before they do. |
2165 | 4.32k | if (fieldFromInstruction_4(Insn, 5, 1) != 0 || |
2166 | 4.32k | fieldFromInstruction_4(Insn, 16, 1) != 0 || |
2167 | 4.32k | fieldFromInstruction_4(Insn, 20, 8) != 0x10) |
2168 | 13 | return MCDisassembler_Fail; |
2169 | | |
2170 | | // imod == '01' --> UNPREDICTABLE |
2171 | | // NOTE: Even though this is technically UNPREDICTABLE, we choose to |
2172 | | // return failure here. The '01' imod value is unprintable, so there's |
2173 | | // nothing useful we could do even if we returned UNPREDICTABLE. |
2174 | | |
2175 | 4.30k | if (imod == 1) return MCDisassembler_Fail; |
2176 | | |
2177 | 4.30k | if (imod && M) { |
2178 | 429 | MCInst_setOpcode(Inst, ARM_CPS3p); |
2179 | 429 | MCOperand_CreateImm0(Inst, imod); |
2180 | 429 | MCOperand_CreateImm0(Inst, iflags); |
2181 | 429 | MCOperand_CreateImm0(Inst, mode); |
2182 | 3.87k | } else if (imod && !M) { |
2183 | 1.27k | MCInst_setOpcode(Inst, ARM_CPS2p); |
2184 | 1.27k | MCOperand_CreateImm0(Inst, imod); |
2185 | 1.27k | MCOperand_CreateImm0(Inst, iflags); |
2186 | 1.27k | if (mode) S = MCDisassembler_SoftFail; |
2187 | 2.60k | } else if (!imod && M) { |
2188 | 1.70k | MCInst_setOpcode(Inst, ARM_CPS1p); |
2189 | 1.70k | MCOperand_CreateImm0(Inst, mode); |
2190 | 1.70k | if (iflags) S = MCDisassembler_SoftFail; |
2191 | 1.70k | } else { |
2192 | | // imod == '00' && M == '0' --> UNPREDICTABLE |
2193 | 902 | MCInst_setOpcode(Inst, ARM_CPS1p); |
2194 | 902 | MCOperand_CreateImm0(Inst, mode); |
2195 | 902 | S = MCDisassembler_SoftFail; |
2196 | 902 | } |
2197 | | |
2198 | 4.30k | return S; |
2199 | 4.30k | } |
2200 | | |
2201 | | static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, |
2202 | | uint64_t Address, const void *Decoder) |
2203 | 1.78k | { |
2204 | 1.78k | unsigned imod = fieldFromInstruction_4(Insn, 9, 2); |
2205 | 1.78k | unsigned M = fieldFromInstruction_4(Insn, 8, 1); |
2206 | 1.78k | unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); |
2207 | 1.78k | unsigned mode = fieldFromInstruction_4(Insn, 0, 5); |
2208 | | |
2209 | 1.78k | DecodeStatus S = MCDisassembler_Success; |
2210 | | |
2211 | | // imod == '01' --> UNPREDICTABLE |
2212 | | // NOTE: Even though this is technically UNPREDICTABLE, we choose to |
2213 | | // return failure here. The '01' imod value is unprintable, so there's |
2214 | | // nothing useful we could do even if we returned UNPREDICTABLE. |
2215 | | |
2216 | 1.78k | if (imod == 1) return MCDisassembler_Fail; |
2217 | | |
2218 | 1.78k | if (imod && M) { |
2219 | 309 | MCInst_setOpcode(Inst, ARM_t2CPS3p); |
2220 | 309 | MCOperand_CreateImm0(Inst, imod); |
2221 | 309 | MCOperand_CreateImm0(Inst, iflags); |
2222 | 309 | MCOperand_CreateImm0(Inst, mode); |
2223 | 1.47k | } else if (imod && !M) { |
2224 | 118 | MCInst_setOpcode(Inst, ARM_t2CPS2p); |
2225 | 118 | MCOperand_CreateImm0(Inst, imod); |
2226 | 118 | MCOperand_CreateImm0(Inst, iflags); |
2227 | 118 | if (mode) S = MCDisassembler_SoftFail; |
2228 | 1.35k | } else if (!imod && M) { |
2229 | 1.35k | MCInst_setOpcode(Inst, ARM_t2CPS1p); |
2230 | 1.35k | MCOperand_CreateImm0(Inst, mode); |
2231 | 1.35k | if (iflags) S = MCDisassembler_SoftFail; |
2232 | 1.35k | } else { |
2233 | | // imod == '00' && M == '0' --> this is a HINT instruction |
2234 | 0 | int imm = fieldFromInstruction_4(Insn, 0, 8); |
2235 | | // HINT are defined only for immediate in [0..4] |
2236 | 0 | if (imm > 4) return MCDisassembler_Fail; |
2237 | | |
2238 | 0 | MCInst_setOpcode(Inst, ARM_t2HINT); |
2239 | 0 | MCOperand_CreateImm0(Inst, imm); |
2240 | 0 | } |
2241 | | |
2242 | 1.78k | return S; |
2243 | 1.78k | } |
2244 | | |
2245 | | static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, |
2246 | | uint64_t Address, const void *Decoder) |
2247 | 1.00k | { |
2248 | 1.00k | DecodeStatus S = MCDisassembler_Success; |
2249 | | |
2250 | 1.00k | unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); |
2251 | 1.00k | unsigned imm = 0; |
2252 | | |
2253 | 1.00k | imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); |
2254 | 1.00k | imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); |
2255 | 1.00k | imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); |
2256 | 1.00k | imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); |
2257 | | |
2258 | 1.00k | if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) |
2259 | 725 | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) |
2260 | 0 | return MCDisassembler_Fail; |
2261 | | |
2262 | 1.00k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) |
2263 | 0 | return MCDisassembler_Fail; |
2264 | | |
2265 | 1.00k | MCOperand_CreateImm0(Inst, imm); |
2266 | | |
2267 | 1.00k | return S; |
2268 | 1.00k | } |
2269 | | |
2270 | | static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, |
2271 | | uint64_t Address, const void *Decoder) |
2272 | 1.68k | { |
2273 | 1.68k | DecodeStatus S = MCDisassembler_Success; |
2274 | | |
2275 | 1.68k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
2276 | 1.68k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2277 | 1.68k | unsigned imm = 0; |
2278 | | |
2279 | 1.68k | imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); |
2280 | 1.68k | imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); |
2281 | | |
2282 | 1.68k | if (MCInst_getOpcode(Inst) == ARM_MOVTi16) |
2283 | 947 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
2284 | 0 | return MCDisassembler_Fail; |
2285 | | |
2286 | 1.68k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
2287 | 0 | return MCDisassembler_Fail; |
2288 | | |
2289 | 1.68k | MCOperand_CreateImm0(Inst, imm); |
2290 | | |
2291 | 1.68k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2292 | 130 | return MCDisassembler_Fail; |
2293 | | |
2294 | 1.55k | return S; |
2295 | 1.68k | } |
2296 | | |
2297 | | static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, |
2298 | | uint64_t Address, const void *Decoder) |
2299 | 3.42k | { |
2300 | 3.42k | DecodeStatus S = MCDisassembler_Success; |
2301 | | |
2302 | 3.42k | unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); |
2303 | 3.42k | unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); |
2304 | 3.42k | unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); |
2305 | 3.42k | unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); |
2306 | 3.42k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2307 | | |
2308 | 3.42k | if (pred == 0xF) |
2309 | 1.23k | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
2310 | | |
2311 | 2.18k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
2312 | 0 | return MCDisassembler_Fail; |
2313 | | |
2314 | 2.18k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
2315 | 0 | return MCDisassembler_Fail; |
2316 | | |
2317 | 2.18k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
2318 | 0 | return MCDisassembler_Fail; |
2319 | | |
2320 | 2.18k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) |
2321 | 0 | return MCDisassembler_Fail; |
2322 | | |
2323 | 2.18k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2324 | 0 | return MCDisassembler_Fail; |
2325 | | |
2326 | 2.18k | return S; |
2327 | 2.18k | } |
2328 | | |
2329 | | static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, |
2330 | | uint64_t Address, const void *Decoder) |
2331 | 501 | { |
2332 | 501 | DecodeStatus S = MCDisassembler_Success; |
2333 | 501 | unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); |
2334 | 501 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
2335 | 501 | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
2336 | | |
2337 | 501 | if (Pred == 0xF) |
2338 | 280 | return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); |
2339 | | |
2340 | 221 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2341 | 0 | return MCDisassembler_Fail; |
2342 | | |
2343 | 221 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
2344 | 0 | return MCDisassembler_Fail; |
2345 | | |
2346 | 221 | if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) |
2347 | 0 | return MCDisassembler_Fail; |
2348 | | |
2349 | 221 | return S; |
2350 | 221 | } |
2351 | | |
2352 | | static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, |
2353 | | uint64_t Address, const void *Decoder) |
2354 | 280 | { |
2355 | 280 | DecodeStatus S = MCDisassembler_Success; |
2356 | 280 | unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); |
2357 | | |
2358 | 280 | if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) |
2359 | 2 | return MCDisassembler_Fail; |
2360 | | |
2361 | | // Decoder can be called from DecodeTST, which does not check the full |
2362 | | // encoding is valid. |
2363 | 278 | if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || |
2364 | 278 | fieldFromInstruction_4(Insn, 4, 4) != 0) |
2365 | 0 | return MCDisassembler_Fail; |
2366 | | |
2367 | 278 | if (fieldFromInstruction_4(Insn, 10, 10) != 0 || |
2368 | 278 | fieldFromInstruction_4(Insn, 0, 4) != 0) |
2369 | 165 | S = MCDisassembler_SoftFail; |
2370 | | |
2371 | 278 | MCInst_setOpcode(Inst, ARM_SETPAN); |
2372 | 278 | MCOperand_CreateImm0(Inst, Imm); |
2373 | | |
2374 | 278 | return S; |
2375 | 278 | } |
2376 | | |
2377 | | static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, |
2378 | | uint64_t Address, const void *Decoder) |
2379 | 7.99k | { |
2380 | 7.99k | DecodeStatus S = MCDisassembler_Success; |
2381 | 7.99k | unsigned add = fieldFromInstruction_4(Val, 12, 1); |
2382 | 7.99k | unsigned imm = fieldFromInstruction_4(Val, 0, 12); |
2383 | 7.99k | unsigned Rn = fieldFromInstruction_4(Val, 13, 4); |
2384 | | |
2385 | 7.99k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2386 | 0 | return MCDisassembler_Fail; |
2387 | | |
2388 | 7.99k | if (!add) imm *= (unsigned int)-1; |
2389 | 7.99k | if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; |
2390 | | |
2391 | 7.99k | MCOperand_CreateImm0(Inst, imm); |
2392 | | //if (Rn == 15) |
2393 | | // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); |
2394 | | |
2395 | 7.99k | return S; |
2396 | 7.99k | } |
2397 | | |
2398 | | static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, |
2399 | | uint64_t Address, const void *Decoder) |
2400 | 2.10k | { |
2401 | 2.10k | DecodeStatus S = MCDisassembler_Success; |
2402 | 2.10k | unsigned Rn = fieldFromInstruction_4(Val, 9, 4); |
2403 | | // U == 1 to add imm, 0 to subtract it. |
2404 | 2.10k | unsigned U = fieldFromInstruction_4(Val, 8, 1); |
2405 | 2.10k | unsigned imm = fieldFromInstruction_4(Val, 0, 8); |
2406 | | |
2407 | 2.10k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2408 | 0 | return MCDisassembler_Fail; |
2409 | | |
2410 | 2.10k | if (U) |
2411 | 905 | MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); |
2412 | 1.20k | else |
2413 | 1.20k | MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); |
2414 | | |
2415 | 2.10k | return S; |
2416 | 2.10k | } |
2417 | | |
2418 | | static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, |
2419 | | uint64_t Address, const void *Decoder) |
2420 | 1.61k | { |
2421 | 1.61k | DecodeStatus S = MCDisassembler_Success; |
2422 | 1.61k | unsigned Rn = fieldFromInstruction_4(Val, 9, 4); |
2423 | | // U == 1 to add imm, 0 to subtract it. |
2424 | 1.61k | unsigned U = fieldFromInstruction_4(Val, 8, 1); |
2425 | 1.61k | unsigned imm = fieldFromInstruction_4(Val, 0, 8); |
2426 | | |
2427 | 1.61k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
2428 | 0 | return MCDisassembler_Fail; |
2429 | | |
2430 | 1.61k | if (U) |
2431 | 538 | MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm)); |
2432 | 1.07k | else |
2433 | 1.07k | MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm)); |
2434 | | |
2435 | 1.61k | return S; |
2436 | 1.61k | } |
2437 | | |
2438 | | static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, |
2439 | | uint64_t Address, const void *Decoder) |
2440 | 12.5k | { |
2441 | 12.5k | return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); |
2442 | 12.5k | } |
2443 | | |
2444 | | static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, |
2445 | | uint64_t Address, const void *Decoder) |
2446 | 783 | { |
2447 | 783 | DecodeStatus Status = MCDisassembler_Success; |
2448 | | |
2449 | | // Note the J1 and J2 values are from the encoded instruction. So here |
2450 | | // change them to I1 and I2 values via as documented: |
2451 | | // I1 = NOT(J1 EOR S); |
2452 | | // I2 = NOT(J2 EOR S); |
2453 | | // and build the imm32 with one trailing zero as documented: |
2454 | | // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); |
2455 | 783 | unsigned S = fieldFromInstruction_4(Insn, 26, 1); |
2456 | 783 | unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); |
2457 | 783 | unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); |
2458 | 783 | unsigned I1 = !(J1 ^ S); |
2459 | 783 | unsigned I2 = !(J2 ^ S); |
2460 | 783 | unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); |
2461 | 783 | unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); |
2462 | 783 | unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; |
2463 | 783 | int imm32 = SignExtend32(tmp << 1, 25); |
2464 | | |
2465 | 783 | MCOperand_CreateImm0(Inst, imm32); |
2466 | | |
2467 | 783 | return Status; |
2468 | 783 | } |
2469 | | |
2470 | | static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, |
2471 | | uint64_t Address, const void *Decoder) |
2472 | 8.35k | { |
2473 | 8.35k | DecodeStatus S = MCDisassembler_Success; |
2474 | | |
2475 | 8.35k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
2476 | 8.35k | unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; |
2477 | | |
2478 | 8.35k | if (pred == 0xF) { |
2479 | 1.41k | MCInst_setOpcode(Inst, ARM_BLXi); |
2480 | 1.41k | imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; |
2481 | 1.41k | MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); |
2482 | 1.41k | return S; |
2483 | 1.41k | } |
2484 | | |
2485 | 6.93k | MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); |
2486 | | |
2487 | 6.93k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
2488 | 0 | return MCDisassembler_Fail; |
2489 | | |
2490 | 6.93k | return S; |
2491 | 6.93k | } |
2492 | | |
2493 | | |
2494 | | static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, |
2495 | | uint64_t Address, const void *Decoder) |
2496 | 59.6k | { |
2497 | 59.6k | DecodeStatus S = MCDisassembler_Success; |
2498 | | |
2499 | 59.6k | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
2500 | 59.6k | unsigned align = fieldFromInstruction_4(Val, 4, 2); |
2501 | | |
2502 | 59.6k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
2503 | 0 | return MCDisassembler_Fail; |
2504 | | |
2505 | 59.6k | if (!align) |
2506 | 30.6k | MCOperand_CreateImm0(Inst, 0); |
2507 | 29.0k | else |
2508 | 29.0k | MCOperand_CreateImm0(Inst, 4 << align); |
2509 | | |
2510 | 59.6k | return S; |
2511 | 59.6k | } |
2512 | | |
2513 | | static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, |
2514 | | uint64_t Address, const void *Decoder) |
2515 | 16.7k | { |
2516 | 16.7k | DecodeStatus S = MCDisassembler_Success; |
2517 | 16.7k | unsigned wb, Rn, Rm; |
2518 | 16.7k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
2519 | 16.7k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
2520 | 16.7k | wb = fieldFromInstruction_4(Insn, 16, 4); |
2521 | 16.7k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
2522 | 16.7k | Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; |
2523 | 16.7k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
2524 | | |
2525 | | // First output register |
2526 | 16.7k | switch (MCInst_getOpcode(Inst)) { |
2527 | 449 | case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: |
2528 | 1.20k | case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: |
2529 | 1.44k | case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: |
2530 | 1.59k | case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: |
2531 | 1.79k | case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: |
2532 | 2.25k | case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: |
2533 | 2.54k | case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: |
2534 | 2.89k | case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: |
2535 | 3.72k | case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: |
2536 | 3.72k | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
2537 | 1 | return MCDisassembler_Fail; |
2538 | 3.72k | break; |
2539 | | |
2540 | 3.72k | case ARM_VLD2b16: |
2541 | 185 | case ARM_VLD2b32: |
2542 | 258 | case ARM_VLD2b8: |
2543 | 544 | case ARM_VLD2b16wb_fixed: |
2544 | 910 | case ARM_VLD2b16wb_register: |
2545 | 1.03k | case ARM_VLD2b32wb_fixed: |
2546 | 1.29k | case ARM_VLD2b32wb_register: |
2547 | 1.33k | case ARM_VLD2b8wb_fixed: |
2548 | 1.62k | case ARM_VLD2b8wb_register: |
2549 | 1.62k | if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
2550 | 4 | return MCDisassembler_Fail; |
2551 | 1.62k | break; |
2552 | | |
2553 | 11.3k | default: |
2554 | 11.3k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
2555 | 0 | return MCDisassembler_Fail; |
2556 | 16.7k | } |
2557 | | |
2558 | | // Second output register |
2559 | 16.7k | switch (MCInst_getOpcode(Inst)) { |
2560 | 69 | case ARM_VLD3d8: |
2561 | 273 | case ARM_VLD3d16: |
2562 | 291 | case ARM_VLD3d32: |
2563 | 581 | case ARM_VLD3d8_UPD: |
2564 | 675 | case ARM_VLD3d16_UPD: |
2565 | 1.05k | case ARM_VLD3d32_UPD: |
2566 | 1.18k | case ARM_VLD4d8: |
2567 | 1.36k | case ARM_VLD4d16: |
2568 | 1.68k | case ARM_VLD4d32: |
2569 | 2.16k | case ARM_VLD4d8_UPD: |
2570 | 2.49k | case ARM_VLD4d16_UPD: |
2571 | 2.74k | case ARM_VLD4d32_UPD: |
2572 | 2.74k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) |
2573 | 0 | return MCDisassembler_Fail; |
2574 | 2.74k | break; |
2575 | | |
2576 | 2.74k | case ARM_VLD3q8: |
2577 | 192 | case ARM_VLD3q16: |
2578 | 264 | case ARM_VLD3q32: |
2579 | 582 | case ARM_VLD3q8_UPD: |
2580 | 916 | case ARM_VLD3q16_UPD: |
2581 | 1.05k | case ARM_VLD3q32_UPD: |
2582 | 1.38k | case ARM_VLD4q8: |
2583 | 1.56k | case ARM_VLD4q16: |
2584 | 1.67k | case ARM_VLD4q32: |
2585 | 1.81k | case ARM_VLD4q8_UPD: |
2586 | 1.94k | case ARM_VLD4q16_UPD: |
2587 | 2.19k | case ARM_VLD4q32_UPD: |
2588 | 2.19k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) |
2589 | 0 | return MCDisassembler_Fail; |
2590 | | |
2591 | 13.9k | default: |
2592 | 13.9k | break; |
2593 | 16.7k | } |
2594 | | |
2595 | | // Third output register |
2596 | 16.7k | switch(MCInst_getOpcode(Inst)) { |
2597 | 69 | case ARM_VLD3d8: |
2598 | 273 | case ARM_VLD3d16: |
2599 | 291 | case ARM_VLD3d32: |
2600 | 581 | case ARM_VLD3d8_UPD: |
2601 | 675 | case ARM_VLD3d16_UPD: |
2602 | 1.05k | case ARM_VLD3d32_UPD: |
2603 | 1.18k | case ARM_VLD4d8: |
2604 | 1.36k | case ARM_VLD4d16: |
2605 | 1.68k | case ARM_VLD4d32: |
2606 | 2.16k | case ARM_VLD4d8_UPD: |
2607 | 2.49k | case ARM_VLD4d16_UPD: |
2608 | 2.74k | case ARM_VLD4d32_UPD: |
2609 | 2.74k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) |
2610 | 0 | return MCDisassembler_Fail; |
2611 | 2.74k | break; |
2612 | 2.74k | case ARM_VLD3q8: |
2613 | 192 | case ARM_VLD3q16: |
2614 | 264 | case ARM_VLD3q32: |
2615 | 582 | case ARM_VLD3q8_UPD: |
2616 | 916 | case ARM_VLD3q16_UPD: |
2617 | 1.05k | case ARM_VLD3q32_UPD: |
2618 | 1.38k | case ARM_VLD4q8: |
2619 | 1.56k | case ARM_VLD4q16: |
2620 | 1.67k | case ARM_VLD4q32: |
2621 | 1.81k | case ARM_VLD4q8_UPD: |
2622 | 1.94k | case ARM_VLD4q16_UPD: |
2623 | 2.19k | case ARM_VLD4q32_UPD: |
2624 | 2.19k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) |
2625 | 0 | return MCDisassembler_Fail; |
2626 | 2.19k | break; |
2627 | 11.7k | default: |
2628 | 11.7k | break; |
2629 | 16.7k | } |
2630 | | |
2631 | | // Fourth output register |
2632 | 16.7k | switch (MCInst_getOpcode(Inst)) { |
2633 | 130 | case ARM_VLD4d8: |
2634 | 312 | case ARM_VLD4d16: |
2635 | 632 | case ARM_VLD4d32: |
2636 | 1.11k | case ARM_VLD4d8_UPD: |
2637 | 1.44k | case ARM_VLD4d16_UPD: |
2638 | 1.69k | case ARM_VLD4d32_UPD: |
2639 | 1.69k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) |
2640 | 0 | return MCDisassembler_Fail; |
2641 | 1.69k | break; |
2642 | 1.69k | case ARM_VLD4q8: |
2643 | 514 | case ARM_VLD4q16: |
2644 | 628 | case ARM_VLD4q32: |
2645 | 760 | case ARM_VLD4q8_UPD: |
2646 | 889 | case ARM_VLD4q16_UPD: |
2647 | 1.14k | case ARM_VLD4q32_UPD: |
2648 | 1.14k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) |
2649 | 0 | return MCDisassembler_Fail; |
2650 | 1.14k | break; |
2651 | 13.8k | default: |
2652 | 13.8k | break; |
2653 | 16.7k | } |
2654 | | |
2655 | | // Writeback operand |
2656 | 16.7k | switch (MCInst_getOpcode(Inst)) { |
2657 | 104 | case ARM_VLD1d8wb_fixed: |
2658 | 189 | case ARM_VLD1d16wb_fixed: |
2659 | 426 | case ARM_VLD1d32wb_fixed: |
2660 | 573 | case ARM_VLD1d64wb_fixed: |
2661 | 1.03k | case ARM_VLD1d8wb_register: |
2662 | 1.62k | case ARM_VLD1d16wb_register: |
2663 | 1.75k | case ARM_VLD1d32wb_register: |
2664 | 1.84k | case ARM_VLD1d64wb_register: |
2665 | 1.90k | case ARM_VLD1q8wb_fixed: |
2666 | 2.54k | case ARM_VLD1q16wb_fixed: |
2667 | 2.58k | case ARM_VLD1q32wb_fixed: |
2668 | 2.66k | case ARM_VLD1q64wb_fixed: |
2669 | 2.80k | case ARM_VLD1q8wb_register: |
2670 | 2.91k | case ARM_VLD1q16wb_register: |
2671 | 3.12k | case ARM_VLD1q32wb_register: |
2672 | 3.19k | case ARM_VLD1q64wb_register: |
2673 | 3.87k | case ARM_VLD1d8Twb_fixed: |
2674 | 4.02k | case ARM_VLD1d8Twb_register: |
2675 | 4.16k | case ARM_VLD1d16Twb_fixed: |
2676 | 4.46k | case ARM_VLD1d16Twb_register: |
2677 | 4.53k | case ARM_VLD1d32Twb_fixed: |
2678 | 4.68k | case ARM_VLD1d32Twb_register: |
2679 | 4.75k | case ARM_VLD1d64Twb_fixed: |
2680 | 4.81k | case ARM_VLD1d64Twb_register: |
2681 | 5.11k | case ARM_VLD1d8Qwb_fixed: |
2682 | 5.35k | case ARM_VLD1d8Qwb_register: |
2683 | 5.64k | case ARM_VLD1d16Qwb_fixed: |
2684 | 5.84k | case ARM_VLD1d16Qwb_register: |
2685 | 5.88k | case ARM_VLD1d32Qwb_fixed: |
2686 | 6.38k | case ARM_VLD1d32Qwb_register: |
2687 | 6.65k | case ARM_VLD1d64Qwb_fixed: |
2688 | 6.72k | case ARM_VLD1d64Qwb_register: |
2689 | 6.80k | case ARM_VLD2d8wb_fixed: |
2690 | 6.91k | case ARM_VLD2d16wb_fixed: |
2691 | 7.16k | case ARM_VLD2d32wb_fixed: |
2692 | 7.26k | case ARM_VLD2q8wb_fixed: |
2693 | 7.43k | case ARM_VLD2q16wb_fixed: |
2694 | 7.52k | case ARM_VLD2q32wb_fixed: |
2695 | 8.28k | case ARM_VLD2d8wb_register: |
2696 | 8.45k | case ARM_VLD2d16wb_register: |
2697 | 8.55k | case ARM_VLD2d32wb_register: |
2698 | 8.71k | case ARM_VLD2q8wb_register: |
2699 | 8.89k | case ARM_VLD2q16wb_register: |
2700 | 9.11k | case ARM_VLD2q32wb_register: |
2701 | 9.15k | case ARM_VLD2b8wb_fixed: |
2702 | 9.43k | case ARM_VLD2b16wb_fixed: |
2703 | 9.55k | case ARM_VLD2b32wb_fixed: |
2704 | 9.84k | case ARM_VLD2b8wb_register: |
2705 | 10.2k | case ARM_VLD2b16wb_register: |
2706 | 10.4k | case ARM_VLD2b32wb_register: |
2707 | 10.4k | MCOperand_CreateImm0(Inst, 0); |
2708 | 10.4k | break; |
2709 | | |
2710 | 290 | case ARM_VLD3d8_UPD: |
2711 | 384 | case ARM_VLD3d16_UPD: |
2712 | 759 | case ARM_VLD3d32_UPD: |
2713 | 1.07k | case ARM_VLD3q8_UPD: |
2714 | 1.41k | case ARM_VLD3q16_UPD: |
2715 | 1.54k | case ARM_VLD3q32_UPD: |
2716 | 2.03k | case ARM_VLD4d8_UPD: |
2717 | 2.36k | case ARM_VLD4d16_UPD: |
2718 | 2.60k | case ARM_VLD4d32_UPD: |
2719 | 2.73k | case ARM_VLD4q8_UPD: |
2720 | 2.86k | case ARM_VLD4q16_UPD: |
2721 | 3.12k | case ARM_VLD4q32_UPD: |
2722 | 3.12k | if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) |
2723 | 0 | return MCDisassembler_Fail; |
2724 | 3.12k | break; |
2725 | | |
2726 | 3.12k | default: |
2727 | 3.12k | break; |
2728 | 16.7k | } |
2729 | | |
2730 | | // AddrMode6 Base (register+alignment) |
2731 | 16.7k | if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) |
2732 | 0 | return MCDisassembler_Fail; |
2733 | | |
2734 | | // AddrMode6 Offset (register) |
2735 | 16.7k | switch (MCInst_getOpcode(Inst)) { |
2736 | 10.4k | default: |
2737 | | // The below have been updated to have explicit am6offset split |
2738 | | // between fixed and register offset. For those instructions not |
2739 | | // yet updated, we need to add an additional reg0 operand for the |
2740 | | // fixed variant. |
2741 | | // |
2742 | | // The fixed offset encodes as Rm == 0xd, so we check for that. |
2743 | 10.4k | if (Rm == 0xd) { |
2744 | 477 | MCOperand_CreateReg0(Inst, 0); |
2745 | 477 | break; |
2746 | 477 | } |
2747 | | // Fall through to handle the register offset variant. |
2748 | | |
2749 | 10.0k | case ARM_VLD1d8wb_fixed: |
2750 | 10.1k | case ARM_VLD1d16wb_fixed: |
2751 | 10.3k | case ARM_VLD1d32wb_fixed: |
2752 | 10.5k | case ARM_VLD1d64wb_fixed: |
2753 | 11.1k | case ARM_VLD1d8Twb_fixed: |
2754 | 11.3k | case ARM_VLD1d16Twb_fixed: |
2755 | 11.3k | case ARM_VLD1d32Twb_fixed: |
2756 | 11.4k | case ARM_VLD1d64Twb_fixed: |
2757 | 11.7k | case ARM_VLD1d8Qwb_fixed: |
2758 | 12.0k | case ARM_VLD1d16Qwb_fixed: |
2759 | 12.1k | case ARM_VLD1d32Qwb_fixed: |
2760 | 12.3k | case ARM_VLD1d64Qwb_fixed: |
2761 | 12.8k | case ARM_VLD1d8wb_register: |
2762 | 13.4k | case ARM_VLD1d16wb_register: |
2763 | 13.5k | case ARM_VLD1d32wb_register: |
2764 | 13.6k | case ARM_VLD1d64wb_register: |
2765 | 13.7k | case ARM_VLD1q8wb_fixed: |
2766 | 14.3k | case ARM_VLD1q16wb_fixed: |
2767 | 14.4k | case ARM_VLD1q32wb_fixed: |
2768 | 14.4k | case ARM_VLD1q64wb_fixed: |
2769 | 14.6k | case ARM_VLD1q8wb_register: |
2770 | 14.7k | case ARM_VLD1q16wb_register: |
2771 | 14.9k | case ARM_VLD1q32wb_register: |
2772 | 15.0k | case ARM_VLD1q64wb_register: |
2773 | | // The fixed offset post-increment encodes Rm == 0xd. The no-writeback |
2774 | | // variant encodes Rm == 0xf. Anything else is a register offset post- |
2775 | | // increment and we need to add the register operand to the instruction. |
2776 | 15.0k | if (Rm != 0xD && Rm != 0xF && |
2777 | 15.0k | !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
2778 | 0 | return MCDisassembler_Fail; |
2779 | 15.0k | break; |
2780 | | |
2781 | 15.0k | case ARM_VLD2d8wb_fixed: |
2782 | 191 | case ARM_VLD2d16wb_fixed: |
2783 | 437 | case ARM_VLD2d32wb_fixed: |
2784 | 475 | case ARM_VLD2b8wb_fixed: |
2785 | 760 | case ARM_VLD2b16wb_fixed: |
2786 | 880 | case ARM_VLD2b32wb_fixed: |
2787 | 980 | case ARM_VLD2q8wb_fixed: |
2788 | 1.15k | case ARM_VLD2q16wb_fixed: |
2789 | 1.23k | case ARM_VLD2q32wb_fixed: |
2790 | 1.23k | break; |
2791 | 16.7k | } |
2792 | | |
2793 | 16.7k | return S; |
2794 | 16.7k | } |
2795 | | |
2796 | | static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, |
2797 | | uint64_t Address, const void *Decoder) |
2798 | 24.0k | { |
2799 | 24.0k | unsigned load; |
2800 | 24.0k | unsigned type = fieldFromInstruction_4(Insn, 8, 4); |
2801 | 24.0k | unsigned align = fieldFromInstruction_4(Insn, 4, 2); |
2802 | 24.0k | if (type == 6 && (align & 2)) return MCDisassembler_Fail; |
2803 | 24.0k | if (type == 7 && (align & 2)) return MCDisassembler_Fail; |
2804 | 24.0k | if (type == 10 && align == 3) return MCDisassembler_Fail; |
2805 | | |
2806 | 24.0k | load = fieldFromInstruction_4(Insn, 21, 1); |
2807 | | |
2808 | 24.0k | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
2809 | 24.0k | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
2810 | 24.0k | } |
2811 | | |
2812 | | static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, |
2813 | | uint64_t Address, const void *Decoder) |
2814 | 17.2k | { |
2815 | 17.2k | unsigned type, align, load; |
2816 | 17.2k | unsigned size = fieldFromInstruction_4(Insn, 6, 2); |
2817 | 17.2k | if (size == 3) return MCDisassembler_Fail; |
2818 | | |
2819 | 17.2k | type = fieldFromInstruction_4(Insn, 8, 4); |
2820 | 17.2k | align = fieldFromInstruction_4(Insn, 4, 2); |
2821 | 17.2k | if (type == 8 && align == 3) return MCDisassembler_Fail; |
2822 | 17.2k | if (type == 9 && align == 3) return MCDisassembler_Fail; |
2823 | | |
2824 | 17.2k | load = fieldFromInstruction_4(Insn, 21, 1); |
2825 | | |
2826 | 17.2k | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
2827 | 17.2k | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
2828 | 17.2k | } |
2829 | | |
2830 | | static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, |
2831 | | uint64_t Address, const void *Decoder) |
2832 | 8.00k | { |
2833 | 8.00k | unsigned align, load; |
2834 | 8.00k | unsigned size = fieldFromInstruction_4(Insn, 6, 2); |
2835 | 8.00k | if (size == 3) return MCDisassembler_Fail; |
2836 | | |
2837 | 8.00k | align = fieldFromInstruction_4(Insn, 4, 2); |
2838 | 8.00k | if (align & 2) return MCDisassembler_Fail; |
2839 | | |
2840 | 8.00k | load = fieldFromInstruction_4(Insn, 21, 1); |
2841 | | |
2842 | 8.00k | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
2843 | 8.00k | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
2844 | 8.00k | } |
2845 | | |
2846 | | static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, |
2847 | | uint64_t Address, const void *Decoder) |
2848 | 10.4k | { |
2849 | 10.4k | unsigned load; |
2850 | 10.4k | unsigned size = fieldFromInstruction_4(Insn, 6, 2); |
2851 | 10.4k | if (size == 3) return MCDisassembler_Fail; |
2852 | | |
2853 | 10.4k | load = fieldFromInstruction_4(Insn, 21, 1); |
2854 | | |
2855 | 10.4k | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
2856 | 10.4k | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
2857 | 10.4k | } |
2858 | | |
2859 | | static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, |
2860 | | uint64_t Address, const void *Decoder) |
2861 | 31.3k | { |
2862 | 31.3k | DecodeStatus S = MCDisassembler_Success; |
2863 | 31.3k | unsigned wb, Rn, Rm; |
2864 | 31.3k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
2865 | 31.3k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
2866 | 31.3k | wb = fieldFromInstruction_4(Insn, 16, 4); |
2867 | 31.3k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
2868 | 31.3k | Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; |
2869 | 31.3k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
2870 | | |
2871 | | // Writeback Operand |
2872 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
2873 | 898 | case ARM_VST1d8wb_fixed: |
2874 | 1.01k | case ARM_VST1d16wb_fixed: |
2875 | 1.11k | case ARM_VST1d32wb_fixed: |
2876 | 1.19k | case ARM_VST1d64wb_fixed: |
2877 | 1.71k | case ARM_VST1d8wb_register: |
2878 | 2.36k | case ARM_VST1d16wb_register: |
2879 | 2.48k | case ARM_VST1d32wb_register: |
2880 | 2.86k | case ARM_VST1d64wb_register: |
2881 | 3.44k | case ARM_VST1q8wb_fixed: |
2882 | 3.52k | case ARM_VST1q16wb_fixed: |
2883 | 4.07k | case ARM_VST1q32wb_fixed: |
2884 | 4.41k | case ARM_VST1q64wb_fixed: |
2885 | 4.88k | case ARM_VST1q8wb_register: |
2886 | 5.05k | case ARM_VST1q16wb_register: |
2887 | 5.29k | case ARM_VST1q32wb_register: |
2888 | 5.55k | case ARM_VST1q64wb_register: |
2889 | 6.36k | case ARM_VST1d8Twb_fixed: |
2890 | 6.49k | case ARM_VST1d16Twb_fixed: |
2891 | 6.67k | case ARM_VST1d32Twb_fixed: |
2892 | 6.90k | case ARM_VST1d64Twb_fixed: |
2893 | 7.75k | case ARM_VST1d8Twb_register: |
2894 | 8.15k | case ARM_VST1d16Twb_register: |
2895 | 8.55k | case ARM_VST1d32Twb_register: |
2896 | 8.98k | case ARM_VST1d64Twb_register: |
2897 | 9.23k | case ARM_VST1d8Qwb_fixed: |
2898 | 9.40k | case ARM_VST1d16Qwb_fixed: |
2899 | 9.82k | case ARM_VST1d32Qwb_fixed: |
2900 | 9.89k | case ARM_VST1d64Qwb_fixed: |
2901 | 10.1k | case ARM_VST1d8Qwb_register: |
2902 | 10.4k | case ARM_VST1d16Qwb_register: |
2903 | 10.5k | case ARM_VST1d32Qwb_register: |
2904 | 11.1k | case ARM_VST1d64Qwb_register: |
2905 | 11.4k | case ARM_VST2d8wb_fixed: |
2906 | 11.5k | case ARM_VST2d16wb_fixed: |
2907 | 11.7k | case ARM_VST2d32wb_fixed: |
2908 | 12.2k | case ARM_VST2d8wb_register: |
2909 | 12.4k | case ARM_VST2d16wb_register: |
2910 | 12.6k | case ARM_VST2d32wb_register: |
2911 | 13.0k | case ARM_VST2q8wb_fixed: |
2912 | 13.5k | case ARM_VST2q16wb_fixed: |
2913 | 13.6k | case ARM_VST2q32wb_fixed: |
2914 | 14.1k | case ARM_VST2q8wb_register: |
2915 | 14.8k | case ARM_VST2q16wb_register: |
2916 | 15.0k | case ARM_VST2q32wb_register: |
2917 | 15.2k | case ARM_VST2b8wb_fixed: |
2918 | 15.5k | case ARM_VST2b16wb_fixed: |
2919 | 15.8k | case ARM_VST2b32wb_fixed: |
2920 | 16.5k | case ARM_VST2b8wb_register: |
2921 | 17.5k | case ARM_VST2b16wb_register: |
2922 | 17.7k | case ARM_VST2b32wb_register: |
2923 | 17.7k | if (Rm == 0xF) |
2924 | 0 | return MCDisassembler_Fail; |
2925 | 17.7k | MCOperand_CreateImm0(Inst, 0); |
2926 | 17.7k | break; |
2927 | 170 | case ARM_VST3d8_UPD: |
2928 | 829 | case ARM_VST3d16_UPD: |
2929 | 1.05k | case ARM_VST3d32_UPD: |
2930 | 1.55k | case ARM_VST3q8_UPD: |
2931 | 2.11k | case ARM_VST3q16_UPD: |
2932 | 2.27k | case ARM_VST3q32_UPD: |
2933 | 3.28k | case ARM_VST4d8_UPD: |
2934 | 3.85k | case ARM_VST4d16_UPD: |
2935 | 4.39k | case ARM_VST4d32_UPD: |
2936 | 4.84k | case ARM_VST4q8_UPD: |
2937 | 5.03k | case ARM_VST4q16_UPD: |
2938 | 5.30k | case ARM_VST4q32_UPD: |
2939 | 5.30k | if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) |
2940 | 0 | return MCDisassembler_Fail; |
2941 | 5.30k | break; |
2942 | 8.28k | default: |
2943 | 8.28k | break; |
2944 | 31.3k | } |
2945 | | |
2946 | | // AddrMode6 Base (register+alignment) |
2947 | 31.3k | if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) |
2948 | 0 | return MCDisassembler_Fail; |
2949 | | |
2950 | | // AddrMode6 Offset (register) |
2951 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
2952 | 23.9k | default: |
2953 | 23.9k | if (Rm == 0xD) |
2954 | 1.30k | MCOperand_CreateReg0(Inst, 0); |
2955 | 22.6k | else if (Rm != 0xF) { |
2956 | 14.3k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
2957 | 0 | return MCDisassembler_Fail; |
2958 | 14.3k | } |
2959 | 23.9k | break; |
2960 | | |
2961 | 23.9k | case ARM_VST1d8wb_fixed: |
2962 | 1.01k | case ARM_VST1d16wb_fixed: |
2963 | 1.11k | case ARM_VST1d32wb_fixed: |
2964 | 1.19k | case ARM_VST1d64wb_fixed: |
2965 | 1.77k | case ARM_VST1q8wb_fixed: |
2966 | 1.85k | case ARM_VST1q16wb_fixed: |
2967 | 2.39k | case ARM_VST1q32wb_fixed: |
2968 | 2.74k | case ARM_VST1q64wb_fixed: |
2969 | 3.55k | case ARM_VST1d8Twb_fixed: |
2970 | 3.68k | case ARM_VST1d16Twb_fixed: |
2971 | 3.86k | case ARM_VST1d32Twb_fixed: |
2972 | 4.09k | case ARM_VST1d64Twb_fixed: |
2973 | 4.34k | case ARM_VST1d8Qwb_fixed: |
2974 | 4.51k | case ARM_VST1d16Qwb_fixed: |
2975 | 4.93k | case ARM_VST1d32Qwb_fixed: |
2976 | 5.00k | case ARM_VST1d64Qwb_fixed: |
2977 | 5.26k | case ARM_VST2d8wb_fixed: |
2978 | 5.44k | case ARM_VST2d16wb_fixed: |
2979 | 5.58k | case ARM_VST2d32wb_fixed: |
2980 | 5.92k | case ARM_VST2q8wb_fixed: |
2981 | 6.46k | case ARM_VST2q16wb_fixed: |
2982 | 6.58k | case ARM_VST2q32wb_fixed: |
2983 | 6.83k | case ARM_VST2b8wb_fixed: |
2984 | 7.07k | case ARM_VST2b16wb_fixed: |
2985 | 7.39k | case ARM_VST2b32wb_fixed: |
2986 | 7.39k | break; |
2987 | 31.3k | } |
2988 | | |
2989 | | |
2990 | | // First input register |
2991 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
2992 | 411 | case ARM_VST1q16: |
2993 | 643 | case ARM_VST1q32: |
2994 | 710 | case ARM_VST1q64: |
2995 | 1.01k | case ARM_VST1q8: |
2996 | 1.09k | case ARM_VST1q16wb_fixed: |
2997 | 1.27k | case ARM_VST1q16wb_register: |
2998 | 1.81k | case ARM_VST1q32wb_fixed: |
2999 | 2.05k | case ARM_VST1q32wb_register: |
3000 | 2.39k | case ARM_VST1q64wb_fixed: |
3001 | 2.65k | case ARM_VST1q64wb_register: |
3002 | 3.23k | case ARM_VST1q8wb_fixed: |
3003 | 3.69k | case ARM_VST1q8wb_register: |
3004 | 4.22k | case ARM_VST2d16: |
3005 | 4.75k | case ARM_VST2d32: |
3006 | 4.93k | case ARM_VST2d8: |
3007 | 5.12k | case ARM_VST2d16wb_fixed: |
3008 | 5.26k | case ARM_VST2d16wb_register: |
3009 | 5.40k | case ARM_VST2d32wb_fixed: |
3010 | 5.64k | case ARM_VST2d32wb_register: |
3011 | 5.91k | case ARM_VST2d8wb_fixed: |
3012 | 6.46k | case ARM_VST2d8wb_register: |
3013 | 6.46k | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
3014 | 3 | return MCDisassembler_Fail; |
3015 | 6.46k | break; |
3016 | | |
3017 | 6.46k | case ARM_VST2b16: |
3018 | 779 | case ARM_VST2b32: |
3019 | 1.33k | case ARM_VST2b8: |
3020 | 1.57k | case ARM_VST2b16wb_fixed: |
3021 | 2.53k | case ARM_VST2b16wb_register: |
3022 | 2.85k | case ARM_VST2b32wb_fixed: |
3023 | 3.10k | case ARM_VST2b32wb_register: |
3024 | 3.35k | case ARM_VST2b8wb_fixed: |
3025 | 4.06k | case ARM_VST2b8wb_register: |
3026 | 4.06k | if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
3027 | 14 | return MCDisassembler_Fail; |
3028 | 4.05k | break; |
3029 | | |
3030 | 20.8k | default: |
3031 | 20.8k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3032 | 0 | return MCDisassembler_Fail; |
3033 | 31.3k | } |
3034 | | |
3035 | | // Second input register |
3036 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
3037 | 137 | case ARM_VST3d8: |
3038 | 473 | case ARM_VST3d16: |
3039 | 600 | case ARM_VST3d32: |
3040 | 770 | case ARM_VST3d8_UPD: |
3041 | 1.42k | case ARM_VST3d16_UPD: |
3042 | 1.65k | case ARM_VST3d32_UPD: |
3043 | 2.09k | case ARM_VST4d8: |
3044 | 2.28k | case ARM_VST4d16: |
3045 | 2.55k | case ARM_VST4d32: |
3046 | 3.56k | case ARM_VST4d8_UPD: |
3047 | 4.13k | case ARM_VST4d16_UPD: |
3048 | 4.67k | case ARM_VST4d32_UPD: |
3049 | 4.67k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) |
3050 | 0 | return MCDisassembler_Fail; |
3051 | 4.67k | break; |
3052 | | |
3053 | 4.67k | case ARM_VST3q8: |
3054 | 636 | case ARM_VST3q16: |
3055 | 738 | case ARM_VST3q32: |
3056 | 1.23k | case ARM_VST3q8_UPD: |
3057 | 1.80k | case ARM_VST3q16_UPD: |
3058 | 1.95k | case ARM_VST3q32_UPD: |
3059 | 2.56k | case ARM_VST4q8: |
3060 | 3.04k | case ARM_VST4q16: |
3061 | 3.30k | case ARM_VST4q32: |
3062 | 3.75k | case ARM_VST4q8_UPD: |
3063 | 3.94k | case ARM_VST4q16_UPD: |
3064 | 4.21k | case ARM_VST4q32_UPD: |
3065 | 4.21k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) |
3066 | 0 | return MCDisassembler_Fail; |
3067 | 4.21k | break; |
3068 | 22.4k | default: |
3069 | 22.4k | break; |
3070 | 31.3k | } |
3071 | | |
3072 | | // Third input register |
3073 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
3074 | 137 | case ARM_VST3d8: |
3075 | 473 | case ARM_VST3d16: |
3076 | 600 | case ARM_VST3d32: |
3077 | 770 | case ARM_VST3d8_UPD: |
3078 | 1.42k | case ARM_VST3d16_UPD: |
3079 | 1.65k | case ARM_VST3d32_UPD: |
3080 | 2.09k | case ARM_VST4d8: |
3081 | 2.28k | case ARM_VST4d16: |
3082 | 2.55k | case ARM_VST4d32: |
3083 | 3.56k | case ARM_VST4d8_UPD: |
3084 | 4.13k | case ARM_VST4d16_UPD: |
3085 | 4.67k | case ARM_VST4d32_UPD: |
3086 | 4.67k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) |
3087 | 0 | return MCDisassembler_Fail; |
3088 | 4.67k | break; |
3089 | | |
3090 | 4.67k | case ARM_VST3q8: |
3091 | 636 | case ARM_VST3q16: |
3092 | 738 | case ARM_VST3q32: |
3093 | 1.23k | case ARM_VST3q8_UPD: |
3094 | 1.80k | case ARM_VST3q16_UPD: |
3095 | 1.95k | case ARM_VST3q32_UPD: |
3096 | 2.56k | case ARM_VST4q8: |
3097 | 3.04k | case ARM_VST4q16: |
3098 | 3.30k | case ARM_VST4q32: |
3099 | 3.75k | case ARM_VST4q8_UPD: |
3100 | 3.94k | case ARM_VST4q16_UPD: |
3101 | 4.21k | case ARM_VST4q32_UPD: |
3102 | 4.21k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) |
3103 | 0 | return MCDisassembler_Fail; |
3104 | 4.21k | break; |
3105 | 22.4k | default: |
3106 | 22.4k | break; |
3107 | 31.3k | } |
3108 | | |
3109 | | // Fourth input register |
3110 | 31.3k | switch (MCInst_getOpcode(Inst)) { |
3111 | 439 | case ARM_VST4d8: |
3112 | 629 | case ARM_VST4d16: |
3113 | 902 | case ARM_VST4d32: |
3114 | 1.90k | case ARM_VST4d8_UPD: |
3115 | 2.48k | case ARM_VST4d16_UPD: |
3116 | 3.02k | case ARM_VST4d32_UPD: |
3117 | 3.02k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) |
3118 | 0 | return MCDisassembler_Fail; |
3119 | 3.02k | break; |
3120 | | |
3121 | 3.02k | case ARM_VST4q8: |
3122 | 1.08k | case ARM_VST4q16: |
3123 | 1.34k | case ARM_VST4q32: |
3124 | 1.79k | case ARM_VST4q8_UPD: |
3125 | 1.98k | case ARM_VST4q16_UPD: |
3126 | 2.25k | case ARM_VST4q32_UPD: |
3127 | 2.25k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) |
3128 | 0 | return MCDisassembler_Fail; |
3129 | 2.25k | break; |
3130 | 26.0k | default: |
3131 | 26.0k | break; |
3132 | 31.3k | } |
3133 | | |
3134 | 31.3k | return S; |
3135 | 31.3k | } |
3136 | | |
3137 | | static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, |
3138 | | uint64_t Address, const void *Decoder) |
3139 | 1.08k | { |
3140 | 1.08k | DecodeStatus S = MCDisassembler_Success; |
3141 | 1.08k | unsigned Rn, Rm, align, size; |
3142 | 1.08k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3143 | 1.08k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3144 | 1.08k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
3145 | 1.08k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3146 | 1.08k | align = fieldFromInstruction_4(Insn, 4, 1); |
3147 | 1.08k | size = fieldFromInstruction_4(Insn, 6, 2); |
3148 | | |
3149 | 1.08k | if (size == 0 && align == 1) |
3150 | 2 | return MCDisassembler_Fail; |
3151 | | |
3152 | 1.07k | align *= (1 << size); |
3153 | | |
3154 | 1.07k | switch (MCInst_getOpcode(Inst)) { |
3155 | 22 | case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: |
3156 | 87 | case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: |
3157 | 105 | case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: |
3158 | 259 | case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: |
3159 | 259 | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
3160 | 2 | return MCDisassembler_Fail; |
3161 | 257 | break; |
3162 | | |
3163 | 820 | default: |
3164 | 820 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3165 | 0 | return MCDisassembler_Fail; |
3166 | 820 | break; |
3167 | 1.07k | } |
3168 | | |
3169 | 1.07k | if (Rm != 0xF) { |
3170 | 657 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3171 | 0 | return MCDisassembler_Fail; |
3172 | 657 | } |
3173 | | |
3174 | 1.07k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3175 | 0 | return MCDisassembler_Fail; |
3176 | | |
3177 | 1.07k | MCOperand_CreateImm0(Inst, align); |
3178 | | |
3179 | | // The fixed offset post-increment encodes Rm == 0xd. The no-writeback |
3180 | | // variant encodes Rm == 0xf. Anything else is a register offset post- |
3181 | | // increment and we need to add the register operand to the instruction. |
3182 | 1.07k | if (Rm != 0xD && Rm != 0xF && |
3183 | 1.07k | !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3184 | 0 | return MCDisassembler_Fail; |
3185 | | |
3186 | 1.07k | return S; |
3187 | 1.07k | } |
3188 | | |
3189 | | static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, |
3190 | | uint64_t Address, const void *Decoder) |
3191 | 4.72k | { |
3192 | 4.72k | DecodeStatus S = MCDisassembler_Success; |
3193 | 4.72k | unsigned Rn, Rm, align, size; |
3194 | 4.72k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3195 | 4.72k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3196 | 4.72k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
3197 | 4.72k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3198 | 4.72k | align = fieldFromInstruction_4(Insn, 4, 1); |
3199 | 4.72k | size = 1 << fieldFromInstruction_4(Insn, 6, 2); |
3200 | 4.72k | align *= 2 * size; |
3201 | | |
3202 | 4.72k | switch (MCInst_getOpcode(Inst)) { |
3203 | 432 | case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: |
3204 | 841 | case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: |
3205 | 1.23k | case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: |
3206 | 2.06k | case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: |
3207 | 2.06k | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
3208 | 3 | return MCDisassembler_Fail; |
3209 | 2.05k | break; |
3210 | | |
3211 | 2.05k | case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: |
3212 | 1.29k | case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: |
3213 | 1.95k | case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: |
3214 | 2.66k | case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: |
3215 | 2.66k | if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
3216 | 2 | return MCDisassembler_Fail; |
3217 | 2.65k | break; |
3218 | | |
3219 | 2.65k | default: |
3220 | 0 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3221 | 0 | return MCDisassembler_Fail; |
3222 | 0 | break; |
3223 | 4.72k | } |
3224 | | |
3225 | 4.71k | if (Rm != 0xF) |
3226 | 3.32k | MCOperand_CreateImm0(Inst, 0); |
3227 | | |
3228 | 4.71k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3229 | 0 | return MCDisassembler_Fail; |
3230 | | |
3231 | 4.71k | MCOperand_CreateImm0(Inst, align); |
3232 | | |
3233 | 4.71k | if (Rm != 0xD && Rm != 0xF) { |
3234 | 1.73k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3235 | 0 | return MCDisassembler_Fail; |
3236 | 1.73k | } |
3237 | | |
3238 | 4.71k | return S; |
3239 | 4.71k | } |
3240 | | |
3241 | | static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, |
3242 | | uint64_t Address, const void *Decoder) |
3243 | 1.09k | { |
3244 | 1.09k | DecodeStatus S = MCDisassembler_Success; |
3245 | 1.09k | unsigned Rn, Rm, inc; |
3246 | 1.09k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3247 | 1.09k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3248 | 1.09k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
3249 | 1.09k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3250 | 1.09k | inc = fieldFromInstruction_4(Insn, 5, 1) + 1; |
3251 | | |
3252 | 1.09k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3253 | 0 | return MCDisassembler_Fail; |
3254 | | |
3255 | 1.09k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) |
3256 | 0 | return MCDisassembler_Fail; |
3257 | | |
3258 | 1.09k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) |
3259 | 0 | return MCDisassembler_Fail; |
3260 | | |
3261 | 1.09k | if (Rm != 0xF) { |
3262 | 804 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3263 | 0 | return MCDisassembler_Fail; |
3264 | 804 | } |
3265 | | |
3266 | 1.09k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3267 | 0 | return MCDisassembler_Fail; |
3268 | | |
3269 | 1.09k | MCOperand_CreateImm0(Inst, 0); |
3270 | | |
3271 | 1.09k | if (Rm == 0xD) |
3272 | 454 | MCOperand_CreateReg0(Inst, 0); |
3273 | 645 | else if (Rm != 0xF) { |
3274 | 350 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3275 | 0 | return MCDisassembler_Fail; |
3276 | 350 | } |
3277 | | |
3278 | 1.09k | return S; |
3279 | 1.09k | } |
3280 | | |
3281 | | static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, |
3282 | | uint64_t Address, const void *Decoder) |
3283 | 1.61k | { |
3284 | 1.61k | DecodeStatus S = MCDisassembler_Success; |
3285 | 1.61k | unsigned Rn, Rm, size, inc, align; |
3286 | 1.61k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3287 | 1.61k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3288 | 1.61k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
3289 | 1.61k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3290 | 1.61k | size = fieldFromInstruction_4(Insn, 6, 2); |
3291 | 1.61k | inc = fieldFromInstruction_4(Insn, 5, 1) + 1; |
3292 | 1.61k | align = fieldFromInstruction_4(Insn, 4, 1); |
3293 | | |
3294 | 1.61k | if (size == 0x3) { |
3295 | 289 | if (align == 0) |
3296 | 2 | return MCDisassembler_Fail; |
3297 | 287 | align = 16; |
3298 | 1.32k | } else { |
3299 | 1.32k | if (size == 2) { |
3300 | 558 | align *= 8; |
3301 | 764 | } else { |
3302 | 764 | size = 1 << size; |
3303 | 764 | align *= 4 * size; |
3304 | 764 | } |
3305 | 1.32k | } |
3306 | | |
3307 | 1.60k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3308 | 0 | return MCDisassembler_Fail; |
3309 | | |
3310 | 1.60k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) |
3311 | 0 | return MCDisassembler_Fail; |
3312 | | |
3313 | 1.60k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) |
3314 | 0 | return MCDisassembler_Fail; |
3315 | | |
3316 | 1.60k | if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3*inc) % 32, Address, Decoder))) |
3317 | 0 | return MCDisassembler_Fail; |
3318 | | |
3319 | 1.60k | if (Rm != 0xF) { |
3320 | 1.06k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3321 | 0 | return MCDisassembler_Fail; |
3322 | 1.06k | } |
3323 | | |
3324 | 1.60k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3325 | 0 | return MCDisassembler_Fail; |
3326 | | |
3327 | 1.60k | MCOperand_CreateImm0(Inst, align); |
3328 | | |
3329 | 1.60k | if (Rm == 0xD) |
3330 | 223 | MCOperand_CreateReg0(Inst, 0); |
3331 | 1.38k | else if (Rm != 0xF) { |
3332 | 838 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3333 | 0 | return MCDisassembler_Fail; |
3334 | 838 | } |
3335 | | |
3336 | 1.60k | return S; |
3337 | 1.60k | } |
3338 | | |
3339 | | static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, |
3340 | | uint64_t Address, const void *Decoder) |
3341 | 4.26k | { |
3342 | 4.26k | DecodeStatus S = MCDisassembler_Success; |
3343 | 4.26k | unsigned imm, Q; |
3344 | 4.26k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3345 | 4.26k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3346 | 4.26k | imm = fieldFromInstruction_4(Insn, 0, 4); |
3347 | 4.26k | imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; |
3348 | 4.26k | imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; |
3349 | 4.26k | imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; |
3350 | 4.26k | imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; |
3351 | 4.26k | Q = fieldFromInstruction_4(Insn, 6, 1); |
3352 | | |
3353 | 4.26k | if (Q) { |
3354 | 804 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
3355 | 3 | return MCDisassembler_Fail; |
3356 | 3.45k | } else { |
3357 | 3.45k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3358 | 0 | return MCDisassembler_Fail; |
3359 | 3.45k | } |
3360 | | |
3361 | 4.25k | MCOperand_CreateImm0(Inst, imm); |
3362 | | |
3363 | 4.25k | switch (MCInst_getOpcode(Inst)) { |
3364 | 395 | case ARM_VORRiv4i16: |
3365 | 606 | case ARM_VORRiv2i32: |
3366 | 986 | case ARM_VBICiv4i16: |
3367 | 1.68k | case ARM_VBICiv2i32: |
3368 | 1.68k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3369 | 0 | return MCDisassembler_Fail; |
3370 | 1.68k | break; |
3371 | 1.68k | case ARM_VORRiv8i16: |
3372 | 133 | case ARM_VORRiv4i32: |
3373 | 238 | case ARM_VBICiv8i16: |
3374 | 313 | case ARM_VBICiv4i32: |
3375 | 313 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
3376 | 0 | return MCDisassembler_Fail; |
3377 | 313 | break; |
3378 | 2.26k | default: |
3379 | 2.26k | break; |
3380 | 4.25k | } |
3381 | | |
3382 | 4.25k | return S; |
3383 | 4.25k | } |
3384 | | |
3385 | | static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, |
3386 | | uint64_t Address, const void *Decoder) |
3387 | 114 | { |
3388 | 114 | DecodeStatus S = MCDisassembler_Success; |
3389 | 114 | unsigned Rm, size; |
3390 | 114 | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3391 | 114 | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3392 | 114 | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3393 | 114 | Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; |
3394 | 114 | size = fieldFromInstruction_4(Insn, 18, 2); |
3395 | | |
3396 | 114 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
3397 | 3 | return MCDisassembler_Fail; |
3398 | | |
3399 | 111 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) |
3400 | 0 | return MCDisassembler_Fail; |
3401 | | |
3402 | 111 | MCOperand_CreateImm0(Inst, 8 << size); |
3403 | | |
3404 | 111 | return S; |
3405 | 111 | } |
3406 | | |
3407 | | static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, |
3408 | | uint64_t Address, const void *Decoder) |
3409 | 1.68k | { |
3410 | 1.68k | MCOperand_CreateImm0(Inst, 8 - Val); |
3411 | | |
3412 | 1.68k | return MCDisassembler_Success; |
3413 | 1.68k | } |
3414 | | |
3415 | | static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, |
3416 | | uint64_t Address, const void *Decoder) |
3417 | 1.92k | { |
3418 | 1.92k | MCOperand_CreateImm0(Inst, 16 - Val); |
3419 | | |
3420 | 1.92k | return MCDisassembler_Success; |
3421 | 1.92k | } |
3422 | | |
3423 | | static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, |
3424 | | uint64_t Address, const void *Decoder) |
3425 | 3.59k | { |
3426 | 3.59k | MCOperand_CreateImm0(Inst, 32 - Val); |
3427 | | |
3428 | 3.59k | return MCDisassembler_Success; |
3429 | 3.59k | } |
3430 | | |
3431 | | static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, |
3432 | | uint64_t Address, const void *Decoder) |
3433 | 1.42k | { |
3434 | 1.42k | MCOperand_CreateImm0(Inst, 64 - Val); |
3435 | | |
3436 | 1.42k | return MCDisassembler_Success; |
3437 | 1.42k | } |
3438 | | |
3439 | | static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, |
3440 | | uint64_t Address, const void *Decoder) |
3441 | 2.37k | { |
3442 | 2.37k | DecodeStatus S = MCDisassembler_Success; |
3443 | 2.37k | unsigned Rn, Rm, op; |
3444 | 2.37k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
3445 | 2.37k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
3446 | 2.37k | Rn = fieldFromInstruction_4(Insn, 16, 4); |
3447 | 2.37k | Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; |
3448 | 2.37k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
3449 | 2.37k | Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; |
3450 | 2.37k | op = fieldFromInstruction_4(Insn, 6, 1); |
3451 | | |
3452 | 2.37k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3453 | 0 | return MCDisassembler_Fail; |
3454 | | |
3455 | 2.37k | if (op) { |
3456 | 954 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
3457 | 0 | return MCDisassembler_Fail; // Writeback |
3458 | 954 | } |
3459 | | |
3460 | 2.37k | switch (MCInst_getOpcode(Inst)) { |
3461 | 507 | case ARM_VTBL2: |
3462 | 630 | case ARM_VTBX2: |
3463 | 630 | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) |
3464 | 2 | return MCDisassembler_Fail; |
3465 | 628 | break; |
3466 | 1.74k | default: |
3467 | 1.74k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) |
3468 | 0 | return MCDisassembler_Fail; |
3469 | 2.37k | } |
3470 | | |
3471 | 2.37k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) |
3472 | 0 | return MCDisassembler_Fail; |
3473 | | |
3474 | 2.37k | return S; |
3475 | 2.37k | } |
3476 | | |
3477 | | static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, |
3478 | | uint64_t Address, const void *Decoder) |
3479 | 70.9k | { |
3480 | 70.9k | DecodeStatus S = MCDisassembler_Success; |
3481 | 70.9k | unsigned dst = fieldFromInstruction_2(Insn, 8, 3); |
3482 | 70.9k | unsigned imm = fieldFromInstruction_2(Insn, 0, 8); |
3483 | | |
3484 | 70.9k | if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) |
3485 | 0 | return MCDisassembler_Fail; |
3486 | | |
3487 | 70.9k | switch(MCInst_getOpcode(Inst)) { |
3488 | 0 | default: |
3489 | 0 | return MCDisassembler_Fail; |
3490 | 35.8k | case ARM_tADR: |
3491 | 35.8k | break; // tADR does not explicitly represent the PC as an operand. |
3492 | 35.1k | case ARM_tADDrSPi: |
3493 | 35.1k | MCOperand_CreateReg0(Inst, ARM_SP); |
3494 | 35.1k | break; |
3495 | 70.9k | } |
3496 | | |
3497 | 70.9k | MCOperand_CreateImm0(Inst, imm); |
3498 | | |
3499 | 70.9k | return S; |
3500 | 70.9k | } |
3501 | | |
3502 | | static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, |
3503 | | uint64_t Address, const void *Decoder) |
3504 | 11.3k | { |
3505 | 11.3k | MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); |
3506 | | |
3507 | 11.3k | return MCDisassembler_Success; |
3508 | 11.3k | } |
3509 | | |
3510 | | static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, |
3511 | | uint64_t Address, const void *Decoder) |
3512 | 2.41k | { |
3513 | 2.41k | MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); |
3514 | | |
3515 | 2.41k | return MCDisassembler_Success; |
3516 | 2.41k | } |
3517 | | |
3518 | | static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, |
3519 | | uint64_t Address, const void *Decoder) |
3520 | 7.38k | { |
3521 | 7.38k | MCOperand_CreateImm0(Inst, Val << 1); |
3522 | | |
3523 | 7.38k | return MCDisassembler_Success; |
3524 | 7.38k | } |
3525 | | |
3526 | | static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, |
3527 | | uint64_t Address, const void *Decoder) |
3528 | 51.7k | { |
3529 | 51.7k | DecodeStatus S = MCDisassembler_Success; |
3530 | 51.7k | unsigned Rn = fieldFromInstruction_4(Val, 0, 3); |
3531 | 51.7k | unsigned Rm = fieldFromInstruction_4(Val, 3, 3); |
3532 | | |
3533 | 51.7k | if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3534 | 0 | return MCDisassembler_Fail; |
3535 | | |
3536 | 51.7k | if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3537 | 0 | return MCDisassembler_Fail; |
3538 | | |
3539 | 51.7k | return S; |
3540 | 51.7k | } |
3541 | | |
3542 | | static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, |
3543 | | uint64_t Address, const void *Decoder) |
3544 | 293k | { |
3545 | 293k | DecodeStatus S = MCDisassembler_Success; |
3546 | 293k | unsigned Rn = fieldFromInstruction_4(Val, 0, 3); |
3547 | 293k | unsigned imm = fieldFromInstruction_4(Val, 3, 5); |
3548 | | |
3549 | 293k | if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3550 | 0 | return MCDisassembler_Fail; |
3551 | | |
3552 | 293k | MCOperand_CreateImm0(Inst, imm); |
3553 | | |
3554 | 293k | return S; |
3555 | 293k | } |
3556 | | |
3557 | | static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, |
3558 | | uint64_t Address, const void *Decoder) |
3559 | 33.9k | { |
3560 | 33.9k | unsigned imm = Val << 2; |
3561 | | |
3562 | 33.9k | MCOperand_CreateImm0(Inst, imm); |
3563 | | //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); |
3564 | | |
3565 | 33.9k | return MCDisassembler_Success; |
3566 | 33.9k | } |
3567 | | |
3568 | | static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, |
3569 | | uint64_t Address, const void *Decoder) |
3570 | 43.8k | { |
3571 | 43.8k | MCOperand_CreateReg0(Inst, ARM_SP); |
3572 | 43.8k | MCOperand_CreateImm0(Inst, Val); |
3573 | | |
3574 | 43.8k | return MCDisassembler_Success; |
3575 | 43.8k | } |
3576 | | |
3577 | | static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, |
3578 | | uint64_t Address, const void *Decoder) |
3579 | 3.45k | { |
3580 | 3.45k | DecodeStatus S = MCDisassembler_Success; |
3581 | 3.45k | unsigned Rn = fieldFromInstruction_4(Val, 6, 4); |
3582 | 3.45k | unsigned Rm = fieldFromInstruction_4(Val, 2, 4); |
3583 | 3.45k | unsigned imm = fieldFromInstruction_4(Val, 0, 2); |
3584 | | |
3585 | | // Thumb stores cannot use PC as dest register. |
3586 | 3.45k | switch (MCInst_getOpcode(Inst)) { |
3587 | 117 | case ARM_t2STRHs: |
3588 | 1.67k | case ARM_t2STRBs: |
3589 | 1.84k | case ARM_t2STRs: |
3590 | 1.84k | if (Rn == 15) |
3591 | 2 | return MCDisassembler_Fail; |
3592 | 3.45k | default: |
3593 | 3.45k | break; |
3594 | 3.45k | } |
3595 | | |
3596 | 3.45k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3597 | 0 | return MCDisassembler_Fail; |
3598 | | |
3599 | 3.45k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
3600 | 0 | return MCDisassembler_Fail; |
3601 | | |
3602 | 3.45k | MCOperand_CreateImm0(Inst, imm); |
3603 | | |
3604 | 3.45k | return S; |
3605 | 3.45k | } |
3606 | | |
3607 | | static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, |
3608 | | uint64_t Address, const void *Decoder) |
3609 | 2.53k | { |
3610 | 2.53k | DecodeStatus S = MCDisassembler_Success; |
3611 | 2.53k | unsigned addrmode; |
3612 | 2.53k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
3613 | 2.53k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
3614 | 2.53k | bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); |
3615 | 2.53k | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
3616 | | |
3617 | 2.53k | if (Rn == 15) { |
3618 | 926 | switch (MCInst_getOpcode(Inst)) { |
3619 | 87 | case ARM_t2LDRBs: |
3620 | 87 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
3621 | 87 | break; |
3622 | 113 | case ARM_t2LDRHs: |
3623 | 113 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
3624 | 113 | break; |
3625 | 277 | case ARM_t2LDRSHs: |
3626 | 277 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
3627 | 277 | break; |
3628 | 74 | case ARM_t2LDRSBs: |
3629 | 74 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
3630 | 74 | break; |
3631 | 171 | case ARM_t2LDRs: |
3632 | 171 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
3633 | 171 | break; |
3634 | 166 | case ARM_t2PLDs: |
3635 | 166 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
3636 | 166 | break; |
3637 | 37 | case ARM_t2PLIs: |
3638 | 37 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
3639 | 37 | break; |
3640 | 1 | default: |
3641 | 1 | return MCDisassembler_Fail; |
3642 | 926 | } |
3643 | | |
3644 | 925 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
3645 | 926 | } |
3646 | | |
3647 | 1.61k | if (Rt == 15) { |
3648 | 589 | switch (MCInst_getOpcode(Inst)) { |
3649 | 1 | case ARM_t2LDRSHs: |
3650 | 1 | return MCDisassembler_Fail; |
3651 | 0 | case ARM_t2LDRHs: |
3652 | 0 | MCInst_setOpcode(Inst, ARM_t2PLDWs); |
3653 | 0 | break; |
3654 | 0 | case ARM_t2LDRSBs: |
3655 | 0 | MCInst_setOpcode(Inst, ARM_t2PLIs); |
3656 | 588 | default: |
3657 | 588 | break; |
3658 | 589 | } |
3659 | 589 | } |
3660 | | |
3661 | 1.61k | switch (MCInst_getOpcode(Inst)) { |
3662 | 76 | case ARM_t2PLDs: |
3663 | 76 | break; |
3664 | 471 | case ARM_t2PLIs: |
3665 | 471 | if (!hasV7Ops) |
3666 | 0 | return MCDisassembler_Fail; |
3667 | 471 | break; |
3668 | 471 | case ARM_t2PLDWs: |
3669 | 37 | if (!hasV7Ops || !hasMP) |
3670 | 0 | return MCDisassembler_Fail; |
3671 | 37 | break; |
3672 | 1.02k | default: |
3673 | 1.02k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
3674 | 0 | return MCDisassembler_Fail; |
3675 | 1.61k | } |
3676 | | |
3677 | 1.61k | addrmode = fieldFromInstruction_4(Insn, 4, 2); |
3678 | 1.61k | addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; |
3679 | 1.61k | addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; |
3680 | | |
3681 | 1.61k | if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) |
3682 | 0 | return MCDisassembler_Fail; |
3683 | | |
3684 | 1.61k | return S; |
3685 | 1.61k | } |
3686 | | |
3687 | | static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, |
3688 | | uint64_t Address, const void* Decoder) |
3689 | 2.91k | { |
3690 | 2.91k | DecodeStatus S = MCDisassembler_Success; |
3691 | 2.91k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
3692 | 2.91k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
3693 | 2.91k | unsigned U = fieldFromInstruction_4(Insn, 9, 1); |
3694 | 2.91k | unsigned imm = fieldFromInstruction_4(Insn, 0, 8); |
3695 | 2.91k | unsigned add = fieldFromInstruction_4(Insn, 9, 1); |
3696 | 2.91k | bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); |
3697 | 2.91k | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
3698 | | |
3699 | 2.91k | imm |= (U << 8); |
3700 | 2.91k | imm |= (Rn << 9); |
3701 | | |
3702 | 2.91k | if (Rn == 15) { |
3703 | 1.79k | switch (MCInst_getOpcode(Inst)) { |
3704 | 85 | case ARM_t2LDRi8: |
3705 | 85 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
3706 | 85 | break; |
3707 | 367 | case ARM_t2LDRBi8: |
3708 | 367 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
3709 | 367 | break; |
3710 | 170 | case ARM_t2LDRSBi8: |
3711 | 170 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
3712 | 170 | break; |
3713 | 182 | case ARM_t2LDRHi8: |
3714 | 182 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
3715 | 182 | break; |
3716 | 117 | case ARM_t2LDRSHi8: |
3717 | 117 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
3718 | 117 | break; |
3719 | 626 | case ARM_t2PLDi8: |
3720 | 626 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
3721 | 626 | break; |
3722 | 242 | case ARM_t2PLIi8: |
3723 | 242 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
3724 | 242 | break; |
3725 | 2 | default: |
3726 | 2 | return MCDisassembler_Fail; |
3727 | 1.79k | } |
3728 | | |
3729 | 1.78k | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
3730 | 1.79k | } |
3731 | | |
3732 | 1.11k | if (Rt == 15) { |
3733 | 614 | switch (MCInst_getOpcode(Inst)) { |
3734 | 2 | case ARM_t2LDRSHi8: |
3735 | 2 | return MCDisassembler_Fail; |
3736 | 0 | case ARM_t2LDRHi8: |
3737 | 0 | if (!add) |
3738 | 0 | MCInst_setOpcode(Inst, ARM_t2PLDWi8); |
3739 | 0 | break; |
3740 | 0 | case ARM_t2LDRSBi8: |
3741 | 0 | MCInst_setOpcode(Inst, ARM_t2PLIi8); |
3742 | 0 | break; |
3743 | 612 | default: |
3744 | 612 | break; |
3745 | 614 | } |
3746 | 614 | } |
3747 | | |
3748 | 1.11k | switch (MCInst_getOpcode(Inst)) { |
3749 | 256 | case ARM_t2PLDi8: |
3750 | 256 | break; |
3751 | 196 | case ARM_t2PLIi8: |
3752 | 196 | if (!hasV7Ops) |
3753 | 0 | return MCDisassembler_Fail; |
3754 | 196 | break; |
3755 | 196 | case ARM_t2PLDWi8: |
3756 | 159 | if (!hasV7Ops || !hasMP) |
3757 | 0 | return MCDisassembler_Fail; |
3758 | 159 | break; |
3759 | 506 | default: |
3760 | 506 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
3761 | 0 | return MCDisassembler_Fail; |
3762 | 1.11k | } |
3763 | | |
3764 | 1.11k | if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) |
3765 | 0 | return MCDisassembler_Fail; |
3766 | | |
3767 | 1.11k | return S; |
3768 | 1.11k | } |
3769 | | |
3770 | | static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, |
3771 | | uint64_t Address, const void* Decoder) |
3772 | 4.11k | { |
3773 | 4.11k | DecodeStatus S = MCDisassembler_Success; |
3774 | 4.11k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
3775 | 4.11k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
3776 | 4.11k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
3777 | 4.11k | bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); |
3778 | 4.11k | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
3779 | | |
3780 | 4.11k | imm |= (Rn << 13); |
3781 | | |
3782 | 4.11k | if (Rn == 15) { |
3783 | 2.24k | switch (MCInst_getOpcode(Inst)) { |
3784 | 256 | case ARM_t2LDRi12: |
3785 | 256 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
3786 | 256 | break; |
3787 | 168 | case ARM_t2LDRHi12: |
3788 | 168 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
3789 | 168 | break; |
3790 | 450 | case ARM_t2LDRSHi12: |
3791 | 450 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
3792 | 450 | break; |
3793 | 317 | case ARM_t2LDRBi12: |
3794 | 317 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
3795 | 317 | break; |
3796 | 597 | case ARM_t2LDRSBi12: |
3797 | 597 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
3798 | 597 | break; |
3799 | 82 | case ARM_t2PLDi12: |
3800 | 82 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
3801 | 82 | break; |
3802 | 376 | case ARM_t2PLIi12: |
3803 | 376 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
3804 | 376 | break; |
3805 | 2 | default: |
3806 | 2 | return MCDisassembler_Fail; |
3807 | 2.24k | } |
3808 | 2.24k | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
3809 | 2.24k | } |
3810 | | |
3811 | 1.86k | if (Rt == 15) { |
3812 | 648 | switch (MCInst_getOpcode(Inst)) { |
3813 | 2 | case ARM_t2LDRSHi12: |
3814 | 2 | return MCDisassembler_Fail; |
3815 | 0 | case ARM_t2LDRHi12: |
3816 | 0 | MCInst_setOpcode(Inst, ARM_t2PLDWi12); |
3817 | 0 | break; |
3818 | 0 | case ARM_t2LDRSBi12: |
3819 | 0 | MCInst_setOpcode(Inst, ARM_t2PLIi12); |
3820 | 0 | break; |
3821 | 646 | default: |
3822 | 646 | break; |
3823 | 648 | } |
3824 | 648 | } |
3825 | | |
3826 | 1.86k | switch (MCInst_getOpcode(Inst)) { |
3827 | 374 | case ARM_t2PLDi12: |
3828 | 374 | break; |
3829 | 118 | case ARM_t2PLIi12: |
3830 | 118 | if (!hasV7Ops) |
3831 | 0 | return MCDisassembler_Fail; |
3832 | 118 | break; |
3833 | 137 | case ARM_t2PLDWi12: |
3834 | 137 | if (!hasV7Ops || !hasMP) |
3835 | 0 | return MCDisassembler_Fail; |
3836 | 137 | break; |
3837 | 1.23k | default: |
3838 | 1.23k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
3839 | 0 | return MCDisassembler_Fail; |
3840 | 1.86k | } |
3841 | | |
3842 | 1.86k | if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) |
3843 | 0 | return MCDisassembler_Fail; |
3844 | | |
3845 | 1.86k | return S; |
3846 | 1.86k | } |
3847 | | |
3848 | | static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, |
3849 | | uint64_t Address, const void* Decoder) |
3850 | 3.38k | { |
3851 | 3.38k | DecodeStatus S = MCDisassembler_Success; |
3852 | | |
3853 | 3.38k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
3854 | 3.38k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
3855 | 3.38k | unsigned imm = fieldFromInstruction_4(Insn, 0, 8); |
3856 | 3.38k | imm |= (Rn << 9); |
3857 | | |
3858 | 3.38k | if (Rn == 15) { |
3859 | 1.50k | switch (MCInst_getOpcode(Inst)) { |
3860 | 294 | case ARM_t2LDRT: |
3861 | 294 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
3862 | 294 | break; |
3863 | 398 | case ARM_t2LDRBT: |
3864 | 398 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
3865 | 398 | break; |
3866 | 244 | case ARM_t2LDRHT: |
3867 | 244 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
3868 | 244 | break; |
3869 | 377 | case ARM_t2LDRSBT: |
3870 | 377 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
3871 | 377 | break; |
3872 | 192 | case ARM_t2LDRSHT: |
3873 | 192 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
3874 | 192 | break; |
3875 | 0 | default: |
3876 | 0 | return MCDisassembler_Fail; |
3877 | 1.50k | } |
3878 | | |
3879 | 1.50k | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
3880 | 1.50k | } |
3881 | | |
3882 | 1.87k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
3883 | 0 | return MCDisassembler_Fail; |
3884 | | |
3885 | 1.87k | if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) |
3886 | 0 | return MCDisassembler_Fail; |
3887 | | |
3888 | 1.87k | return S; |
3889 | 1.87k | } |
3890 | | |
3891 | | static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, |
3892 | | uint64_t Address, const void* Decoder) |
3893 | 11.2k | { |
3894 | 11.2k | DecodeStatus S = MCDisassembler_Success; |
3895 | 11.2k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
3896 | 11.2k | unsigned U = fieldFromInstruction_4(Insn, 23, 1); |
3897 | 11.2k | int imm = fieldFromInstruction_4(Insn, 0, 12); |
3898 | 11.2k | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
3899 | | |
3900 | 11.2k | if (Rt == 15) { |
3901 | 3.50k | switch (MCInst_getOpcode(Inst)) { |
3902 | 420 | case ARM_t2LDRBpci: |
3903 | 779 | case ARM_t2LDRHpci: |
3904 | 779 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
3905 | 779 | break; |
3906 | 361 | case ARM_t2LDRSBpci: |
3907 | 361 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
3908 | 361 | break; |
3909 | 10 | case ARM_t2LDRSHpci: |
3910 | 10 | return MCDisassembler_Fail; |
3911 | 2.35k | default: |
3912 | 2.35k | break; |
3913 | 3.50k | } |
3914 | 3.50k | } |
3915 | | |
3916 | 11.2k | switch(MCInst_getOpcode(Inst)) { |
3917 | 1.80k | case ARM_t2PLDpci: |
3918 | 1.80k | break; |
3919 | 1.62k | case ARM_t2PLIpci: |
3920 | 1.62k | if (!hasV7Ops) |
3921 | 0 | return MCDisassembler_Fail; |
3922 | 1.62k | break; |
3923 | 7.82k | default: |
3924 | 7.82k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
3925 | 0 | return MCDisassembler_Fail; |
3926 | 11.2k | } |
3927 | | |
3928 | 11.2k | if (!U) { |
3929 | | // Special case for #-0. |
3930 | 8.99k | if (imm == 0) |
3931 | 342 | imm = INT32_MIN; |
3932 | 8.65k | else |
3933 | 8.65k | imm = -imm; |
3934 | 8.99k | } |
3935 | | |
3936 | 11.2k | MCOperand_CreateImm0(Inst, imm); |
3937 | | |
3938 | 11.2k | return S; |
3939 | 11.2k | } |
3940 | | |
3941 | | static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, |
3942 | | uint64_t Address, const void *Decoder) |
3943 | 19.2k | { |
3944 | 19.2k | if (Val == 0) |
3945 | 1.68k | MCOperand_CreateImm0(Inst, INT32_MIN); |
3946 | 17.5k | else { |
3947 | 17.5k | int imm = Val & 0xFF; |
3948 | | |
3949 | 17.5k | if (!(Val & 0x100)) imm *= -1; |
3950 | | |
3951 | 17.5k | MCOperand_CreateImm0(Inst, imm * 4); |
3952 | 17.5k | } |
3953 | | |
3954 | 19.2k | return MCDisassembler_Success; |
3955 | 19.2k | } |
3956 | | |
3957 | | static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, |
3958 | | uint64_t Address, const void *Decoder) |
3959 | 15.3k | { |
3960 | 15.3k | DecodeStatus S = MCDisassembler_Success; |
3961 | 15.3k | unsigned Rn = fieldFromInstruction_4(Val, 9, 4); |
3962 | 15.3k | unsigned imm = fieldFromInstruction_4(Val, 0, 9); |
3963 | | |
3964 | 15.3k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
3965 | 0 | return MCDisassembler_Fail; |
3966 | | |
3967 | 15.3k | if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) |
3968 | 0 | return MCDisassembler_Fail; |
3969 | | |
3970 | 15.3k | return S; |
3971 | 15.3k | } |
3972 | | |
3973 | | static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, |
3974 | | uint64_t Address, const void *Decoder) |
3975 | 2.85k | { |
3976 | 2.85k | DecodeStatus S = MCDisassembler_Success; |
3977 | 2.85k | unsigned Rn = fieldFromInstruction_4(Val, 8, 4); |
3978 | 2.85k | unsigned imm = fieldFromInstruction_4(Val, 0, 8); |
3979 | | |
3980 | 2.85k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
3981 | 0 | return MCDisassembler_Fail; |
3982 | | |
3983 | 2.85k | MCOperand_CreateImm0(Inst, imm); |
3984 | | |
3985 | 2.85k | return S; |
3986 | 2.85k | } |
3987 | | |
3988 | | static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, |
3989 | | uint64_t Address, const void *Decoder) |
3990 | 9.14k | { |
3991 | 9.14k | int imm = Val & 0xFF; |
3992 | | |
3993 | 9.14k | if (Val == 0) |
3994 | 370 | imm = INT32_MIN; |
3995 | 8.77k | else if (!(Val & 0x100)) |
3996 | 4.15k | imm *= -1; |
3997 | | |
3998 | 9.14k | MCOperand_CreateImm0(Inst, imm); |
3999 | | |
4000 | 9.14k | return MCDisassembler_Success; |
4001 | 9.14k | } |
4002 | | |
4003 | | static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, |
4004 | | uint64_t Address, const void *Decoder) |
4005 | 9.14k | { |
4006 | 9.14k | DecodeStatus S = MCDisassembler_Success; |
4007 | | |
4008 | 9.14k | unsigned Rn = fieldFromInstruction_4(Val, 9, 4); |
4009 | 9.14k | unsigned imm = fieldFromInstruction_4(Val, 0, 9); |
4010 | | |
4011 | | // Thumb stores cannot use PC as dest register. |
4012 | 9.14k | switch (MCInst_getOpcode(Inst)) { |
4013 | 247 | case ARM_t2STRT: |
4014 | 476 | case ARM_t2STRBT: |
4015 | 720 | case ARM_t2STRHT: |
4016 | 2.00k | case ARM_t2STRi8: |
4017 | 2.31k | case ARM_t2STRHi8: |
4018 | 2.65k | case ARM_t2STRBi8: |
4019 | 2.65k | if (Rn == 15) |
4020 | 8 | return MCDisassembler_Fail; |
4021 | 2.64k | break; |
4022 | 6.49k | default: |
4023 | 6.49k | break; |
4024 | 9.14k | } |
4025 | | |
4026 | | // Some instructions always use an additive offset. |
4027 | 9.14k | switch (MCInst_getOpcode(Inst)) { |
4028 | 136 | case ARM_t2LDRT: |
4029 | 401 | case ARM_t2LDRBT: |
4030 | 609 | case ARM_t2LDRHT: |
4031 | 1.48k | case ARM_t2LDRSBT: |
4032 | 1.87k | case ARM_t2LDRSHT: |
4033 | 2.12k | case ARM_t2STRT: |
4034 | 2.35k | case ARM_t2STRBT: |
4035 | 2.59k | case ARM_t2STRHT: |
4036 | 2.59k | imm |= 0x100; |
4037 | 2.59k | break; |
4038 | 6.54k | default: |
4039 | 6.54k | break; |
4040 | 9.14k | } |
4041 | | |
4042 | 9.14k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4043 | 0 | return MCDisassembler_Fail; |
4044 | | |
4045 | 9.14k | if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) |
4046 | 0 | return MCDisassembler_Fail; |
4047 | | |
4048 | 9.14k | return S; |
4049 | 9.14k | } |
4050 | | |
4051 | | static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, |
4052 | | uint64_t Address, const void *Decoder) |
4053 | 6.50k | { |
4054 | 6.50k | DecodeStatus S = MCDisassembler_Success; |
4055 | 6.50k | unsigned load; |
4056 | 6.50k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4057 | 6.50k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4058 | 6.50k | unsigned addr = fieldFromInstruction_4(Insn, 0, 8); |
4059 | 6.50k | addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; |
4060 | 6.50k | addr |= Rn << 9; |
4061 | 6.50k | load = fieldFromInstruction_4(Insn, 20, 1); |
4062 | | |
4063 | 6.50k | if (Rn == 15) { |
4064 | 2.99k | switch (MCInst_getOpcode(Inst)) { |
4065 | 356 | case ARM_t2LDR_PRE: |
4066 | 472 | case ARM_t2LDR_POST: |
4067 | 472 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
4068 | 472 | break; |
4069 | 237 | case ARM_t2LDRB_PRE: |
4070 | 504 | case ARM_t2LDRB_POST: |
4071 | 504 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
4072 | 504 | break; |
4073 | 315 | case ARM_t2LDRH_PRE: |
4074 | 642 | case ARM_t2LDRH_POST: |
4075 | 642 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
4076 | 642 | break; |
4077 | 446 | case ARM_t2LDRSB_PRE: |
4078 | 809 | case ARM_t2LDRSB_POST: |
4079 | 809 | if (Rt == 15) |
4080 | 586 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
4081 | 223 | else |
4082 | 223 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
4083 | 809 | break; |
4084 | 333 | case ARM_t2LDRSH_PRE: |
4085 | 560 | case ARM_t2LDRSH_POST: |
4086 | 560 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
4087 | 560 | break; |
4088 | 8 | default: |
4089 | 8 | return MCDisassembler_Fail; |
4090 | 2.99k | } |
4091 | | |
4092 | 2.98k | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
4093 | 2.99k | } |
4094 | | |
4095 | 3.50k | if (!load) { |
4096 | 1.37k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4097 | 0 | return MCDisassembler_Fail; |
4098 | 1.37k | } |
4099 | | |
4100 | 3.50k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
4101 | 0 | return MCDisassembler_Fail; |
4102 | | |
4103 | 3.50k | if (load) { |
4104 | 2.12k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4105 | 0 | return MCDisassembler_Fail; |
4106 | 2.12k | } |
4107 | | |
4108 | 3.50k | if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) |
4109 | 0 | return MCDisassembler_Fail; |
4110 | | |
4111 | 3.50k | return S; |
4112 | 3.50k | } |
4113 | | |
4114 | | static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, |
4115 | | uint64_t Address, const void *Decoder) |
4116 | 2.43k | { |
4117 | 2.43k | DecodeStatus S = MCDisassembler_Success; |
4118 | 2.43k | unsigned Rn = fieldFromInstruction_4(Val, 13, 4); |
4119 | 2.43k | unsigned imm = fieldFromInstruction_4(Val, 0, 12); |
4120 | | |
4121 | | // Thumb stores cannot use PC as dest register. |
4122 | 2.43k | switch (MCInst_getOpcode(Inst)) { |
4123 | 296 | case ARM_t2STRi12: |
4124 | 756 | case ARM_t2STRBi12: |
4125 | 1.18k | case ARM_t2STRHi12: |
4126 | 1.18k | if (Rn == 15) |
4127 | 4 | return MCDisassembler_Fail; |
4128 | 2.42k | default: |
4129 | 2.42k | break; |
4130 | 2.43k | } |
4131 | | |
4132 | 2.42k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4133 | 0 | return MCDisassembler_Fail; |
4134 | | |
4135 | 2.42k | MCOperand_CreateImm0(Inst, imm); |
4136 | | |
4137 | 2.42k | return S; |
4138 | 2.42k | } |
4139 | | |
4140 | | static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, |
4141 | | uint64_t Address, const void *Decoder) |
4142 | 5.16k | { |
4143 | 5.16k | unsigned imm = fieldFromInstruction_2(Insn, 0, 7); |
4144 | | |
4145 | 5.16k | MCOperand_CreateReg0(Inst, ARM_SP); |
4146 | 5.16k | MCOperand_CreateReg0(Inst, ARM_SP); |
4147 | 5.16k | MCOperand_CreateImm0(Inst, imm); |
4148 | | |
4149 | 5.16k | return MCDisassembler_Success; |
4150 | 5.16k | } |
4151 | | |
4152 | | static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, |
4153 | | uint64_t Address, const void *Decoder) |
4154 | 2.20k | { |
4155 | 2.20k | DecodeStatus S = MCDisassembler_Success; |
4156 | | |
4157 | 2.20k | if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { |
4158 | 795 | unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); |
4159 | 795 | Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; |
4160 | | |
4161 | 795 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) |
4162 | 0 | return MCDisassembler_Fail; |
4163 | | |
4164 | 795 | MCOperand_CreateReg0(Inst, ARM_SP); |
4165 | | |
4166 | 795 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) |
4167 | 0 | return MCDisassembler_Fail; |
4168 | 1.41k | } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { |
4169 | 1.41k | unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); |
4170 | | |
4171 | 1.41k | MCOperand_CreateReg0(Inst, ARM_SP); |
4172 | 1.41k | MCOperand_CreateReg0(Inst, ARM_SP); |
4173 | | |
4174 | 1.41k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4175 | 0 | return MCDisassembler_Fail; |
4176 | 1.41k | } |
4177 | | |
4178 | 2.20k | return S; |
4179 | 2.20k | } |
4180 | | |
4181 | | static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, |
4182 | | uint64_t Address, const void *Decoder) |
4183 | 648 | { |
4184 | 648 | unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; |
4185 | 648 | unsigned flags = fieldFromInstruction_2(Insn, 0, 3); |
4186 | | |
4187 | 648 | MCOperand_CreateImm0(Inst, imod); |
4188 | 648 | MCOperand_CreateImm0(Inst, flags); |
4189 | | |
4190 | 648 | return MCDisassembler_Success; |
4191 | 648 | } |
4192 | | |
4193 | | static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, |
4194 | | uint64_t Address, const void *Decoder) |
4195 | 4.17k | { |
4196 | 4.17k | DecodeStatus S = MCDisassembler_Success; |
4197 | 4.17k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4198 | 4.17k | unsigned add = fieldFromInstruction_4(Insn, 4, 1); |
4199 | | |
4200 | 4.17k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
4201 | 0 | return MCDisassembler_Fail; |
4202 | | |
4203 | 4.17k | MCOperand_CreateImm0(Inst, add); |
4204 | | |
4205 | 4.17k | return S; |
4206 | 4.17k | } |
4207 | | |
4208 | | static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, |
4209 | | uint64_t Address, const void *Decoder) |
4210 | 739 | { |
4211 | | // Val is passed in as S:J1:J2:imm10H:imm10L:'0' |
4212 | | // Note only one trailing zero not two. Also the J1 and J2 values are from |
4213 | | // the encoded instruction. So here change to I1 and I2 values via: |
4214 | | // I1 = NOT(J1 EOR S); |
4215 | | // I2 = NOT(J2 EOR S); |
4216 | | // and build the imm32 with two trailing zeros as documented: |
4217 | | // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); |
4218 | 739 | unsigned S = (Val >> 23) & 1; |
4219 | 739 | unsigned J1 = (Val >> 22) & 1; |
4220 | 739 | unsigned J2 = (Val >> 21) & 1; |
4221 | 739 | unsigned I1 = !(J1 ^ S); |
4222 | 739 | unsigned I2 = !(J2 ^ S); |
4223 | 739 | unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); |
4224 | 739 | int imm32 = SignExtend32(tmp << 1, 25); |
4225 | | |
4226 | 739 | MCOperand_CreateImm0(Inst, imm32); |
4227 | | |
4228 | 739 | return MCDisassembler_Success; |
4229 | 739 | } |
4230 | | |
4231 | | static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, |
4232 | | uint64_t Address, const void *Decoder) |
4233 | 12.7k | { |
4234 | 12.7k | if (Val == 0xA || Val == 0xB) |
4235 | 691 | return MCDisassembler_Fail; |
4236 | | |
4237 | 12.0k | if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && !(Val == 14 || Val == 15)) |
4238 | 14 | return MCDisassembler_Fail; |
4239 | | |
4240 | 12.0k | MCOperand_CreateImm0(Inst, Val); |
4241 | | |
4242 | 12.0k | return MCDisassembler_Success; |
4243 | 12.0k | } |
4244 | | |
4245 | | static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, |
4246 | | uint64_t Address, const void *Decoder) |
4247 | 283 | { |
4248 | 283 | DecodeStatus S = MCDisassembler_Success; |
4249 | 283 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4250 | 283 | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4251 | | |
4252 | 283 | if (Rn == ARM_SP) S = MCDisassembler_SoftFail; |
4253 | | |
4254 | 283 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4255 | 0 | return MCDisassembler_Fail; |
4256 | | |
4257 | 283 | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4258 | 0 | return MCDisassembler_Fail; |
4259 | | |
4260 | 283 | return S; |
4261 | 283 | } |
4262 | | |
4263 | | static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, |
4264 | | uint64_t Address, const void *Decoder) |
4265 | 5.72k | { |
4266 | 5.72k | DecodeStatus S = MCDisassembler_Success; |
4267 | 5.72k | unsigned brtarget; |
4268 | 5.72k | unsigned pred = fieldFromInstruction_4(Insn, 22, 4); |
4269 | | |
4270 | 5.72k | if (pred == 0xE || pred == 0xF) { |
4271 | 1.53k | unsigned imm; |
4272 | 1.53k | unsigned opc = fieldFromInstruction_4(Insn, 4, 28); |
4273 | 1.53k | switch (opc) { |
4274 | 1.53k | default: |
4275 | 1.53k | return MCDisassembler_Fail; |
4276 | 0 | case 0xf3bf8f4: |
4277 | 0 | MCInst_setOpcode(Inst, ARM_t2DSB); |
4278 | 0 | break; |
4279 | 0 | case 0xf3bf8f5: |
4280 | 0 | MCInst_setOpcode(Inst, ARM_t2DMB); |
4281 | 0 | break; |
4282 | 0 | case 0xf3bf8f6: |
4283 | 0 | MCInst_setOpcode(Inst, ARM_t2ISB); |
4284 | 0 | break; |
4285 | 1.53k | } |
4286 | | |
4287 | 0 | imm = fieldFromInstruction_4(Insn, 0, 4); |
4288 | 0 | return DecodeMemBarrierOption(Inst, imm, Address, Decoder); |
4289 | 1.53k | } |
4290 | | |
4291 | 4.19k | brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; |
4292 | 4.19k | brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; |
4293 | 4.19k | brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; |
4294 | 4.19k | brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; |
4295 | 4.19k | brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; |
4296 | | |
4297 | 4.19k | if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) |
4298 | 0 | return MCDisassembler_Fail; |
4299 | | |
4300 | 4.19k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4301 | 0 | return MCDisassembler_Fail; |
4302 | | |
4303 | 4.19k | return S; |
4304 | 4.19k | } |
4305 | | |
4306 | | // Decode a shifted immediate operand. These basically consist |
4307 | | // of an 8-bit value, and a 4-bit directive that specifies either |
4308 | | // a splat operation or a rotation. |
4309 | | static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, |
4310 | | uint64_t Address, const void *Decoder) |
4311 | 10.1k | { |
4312 | 10.1k | unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); |
4313 | | |
4314 | 10.1k | if (ctrl == 0) { |
4315 | 6.18k | unsigned byte = fieldFromInstruction_4(Val, 8, 2); |
4316 | 6.18k | unsigned imm = fieldFromInstruction_4(Val, 0, 8); |
4317 | | |
4318 | 6.18k | switch (byte) { |
4319 | 2.57k | case 0: |
4320 | 2.57k | MCOperand_CreateImm0(Inst, imm); |
4321 | 2.57k | break; |
4322 | 921 | case 1: |
4323 | 921 | MCOperand_CreateImm0(Inst, (imm << 16) | imm); |
4324 | 921 | break; |
4325 | 1.49k | case 2: |
4326 | 1.49k | MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); |
4327 | 1.49k | break; |
4328 | 1.19k | case 3: |
4329 | 1.19k | MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); |
4330 | 1.19k | break; |
4331 | 6.18k | } |
4332 | 6.18k | } else { |
4333 | 3.99k | unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; |
4334 | 3.99k | unsigned rot = fieldFromInstruction_4(Val, 7, 5); |
4335 | 3.99k | unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); |
4336 | | |
4337 | 3.99k | MCOperand_CreateImm0(Inst, imm); |
4338 | 3.99k | } |
4339 | | |
4340 | 10.1k | return MCDisassembler_Success; |
4341 | 10.1k | } |
4342 | | |
4343 | | static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, |
4344 | | uint64_t Address, const void *Decoder) |
4345 | 21.2k | { |
4346 | 21.2k | MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); |
4347 | | |
4348 | 21.2k | return MCDisassembler_Success; |
4349 | 21.2k | } |
4350 | | |
4351 | | static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, |
4352 | | uint64_t Address, const void *Decoder) |
4353 | 3.16k | { |
4354 | | // Val is passed in as S:J1:J2:imm10:imm11 |
4355 | | // Note no trailing zero after imm11. Also the J1 and J2 values are from |
4356 | | // the encoded instruction. So here change to I1 and I2 values via: |
4357 | | // I1 = NOT(J1 EOR S); |
4358 | | // I2 = NOT(J2 EOR S); |
4359 | | // and build the imm32 with one trailing zero as documented: |
4360 | | // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); |
4361 | 3.16k | unsigned S = (Val >> 23) & 1; |
4362 | 3.16k | unsigned J1 = (Val >> 22) & 1; |
4363 | 3.16k | unsigned J2 = (Val >> 21) & 1; |
4364 | 3.16k | unsigned I1 = !(J1 ^ S); |
4365 | 3.16k | unsigned I2 = !(J2 ^ S); |
4366 | 3.16k | unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); |
4367 | 3.16k | int imm32 = SignExtend32(tmp << 1, 25); |
4368 | | |
4369 | 3.16k | MCOperand_CreateImm0(Inst, imm32); |
4370 | | |
4371 | 3.16k | return MCDisassembler_Success; |
4372 | 3.16k | } |
4373 | | |
4374 | | static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, |
4375 | | uint64_t Address, const void *Decoder) |
4376 | 3.82k | { |
4377 | 3.82k | if (Val & ~0xf) |
4378 | 0 | return MCDisassembler_Fail; |
4379 | | |
4380 | 3.82k | MCOperand_CreateImm0(Inst, Val); |
4381 | | |
4382 | 3.82k | return MCDisassembler_Success; |
4383 | 3.82k | } |
4384 | | |
4385 | | static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, |
4386 | | uint64_t Address, const void *Decoder) |
4387 | 232 | { |
4388 | 232 | if (Val & ~0xf) |
4389 | 0 | return MCDisassembler_Fail; |
4390 | | |
4391 | 232 | MCOperand_CreateImm0(Inst, Val); |
4392 | | |
4393 | 232 | return MCDisassembler_Success; |
4394 | 232 | } |
4395 | | |
4396 | | static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, |
4397 | | uint64_t Address, const void *Decoder) |
4398 | 8.88k | { |
4399 | 8.88k | DecodeStatus S = MCDisassembler_Success; |
4400 | | |
4401 | 8.88k | if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) { |
4402 | 7.35k | unsigned ValLow = Val & 0xff; |
4403 | | |
4404 | | // Validate the SYSm value first. |
4405 | 7.35k | switch (ValLow) { |
4406 | 81 | case 0: // apsr |
4407 | 185 | case 1: // iapsr |
4408 | 653 | case 2: // eapsr |
4409 | 1.31k | case 3: // xpsr |
4410 | 1.37k | case 5: // ipsr |
4411 | 2.38k | case 6: // epsr |
4412 | 2.50k | case 7: // iepsr |
4413 | 2.96k | case 8: // msp |
4414 | 3.03k | case 9: // psp |
4415 | 3.10k | case 16: // primask |
4416 | 3.30k | case 20: // control |
4417 | 3.30k | break; |
4418 | 74 | case 17: // basepri |
4419 | 160 | case 18: // basepri_max |
4420 | 270 | case 19: // faultmask |
4421 | 270 | if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) |
4422 | | // Values basepri, basepri_max and faultmask are only valid for v7m. |
4423 | 0 | return MCDisassembler_Fail; |
4424 | 270 | break; |
4425 | 270 | case 0x8a: // msplim_ns |
4426 | 127 | case 0x8b: // psplim_ns |
4427 | 275 | case 0x91: // basepri_ns |
4428 | 520 | case 0x93: // faultmask_ns |
4429 | 520 | if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps)) |
4430 | 0 | return MCDisassembler_Fail; |
4431 | | // LLVM_FALLTHROUGH; |
4432 | 957 | case 10: // msplim |
4433 | 1.06k | case 11: // psplim |
4434 | 1.66k | case 0x88: // msp_ns |
4435 | 1.70k | case 0x89: // psp_ns |
4436 | 1.98k | case 0x90: // primask_ns |
4437 | 2.05k | case 0x94: // control_ns |
4438 | 2.25k | case 0x98: // sp_ns |
4439 | 2.25k | if (!ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt)) |
4440 | 0 | return MCDisassembler_Fail; |
4441 | 2.25k | break; |
4442 | 2.25k | default: |
4443 | 1.52k | return MCDisassembler_SoftFail; |
4444 | 7.35k | } |
4445 | | |
4446 | 5.82k | if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { |
4447 | 5.24k | unsigned Mask = fieldFromInstruction_4(Val, 10, 2); |
4448 | 5.24k | if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) { |
4449 | | // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are |
4450 | | // unpredictable. |
4451 | 0 | if (Mask != 2) |
4452 | 0 | S = MCDisassembler_SoftFail; |
4453 | 5.24k | } else { |
4454 | | // The ARMv7-M architecture stores an additional 2-bit mask value in |
4455 | | // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and |
4456 | | // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if |
4457 | | // the NZCVQ bits should be moved by the instruction. Bit mask{0} |
4458 | | // indicates the move for the GE{3:0} bits, the mask{0} bit can be set |
4459 | | // only if the processor includes the DSP extension. |
4460 | 5.24k | if (Mask == 0 || (Mask != 2 && ValLow > 3) || |
4461 | 5.24k | (!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (Mask & 1))) |
4462 | 3.15k | S = MCDisassembler_SoftFail; |
4463 | 5.24k | } |
4464 | 5.24k | } |
4465 | 5.82k | } else { |
4466 | | // A/R class |
4467 | 1.52k | if (Val == 0) |
4468 | 80 | return MCDisassembler_Fail; |
4469 | 1.52k | } |
4470 | | |
4471 | 7.27k | MCOperand_CreateImm0(Inst, Val); |
4472 | 7.27k | return S; |
4473 | 8.88k | } |
4474 | | |
4475 | | static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, |
4476 | | uint64_t Address, const void *Decoder) |
4477 | 1.35k | { |
4478 | 1.35k | unsigned R = fieldFromInstruction_4(Val, 5, 1); |
4479 | 1.35k | unsigned SysM = fieldFromInstruction_4(Val, 0, 5); |
4480 | | |
4481 | | // The table of encodings for these banked registers comes from B9.2.3 of the |
4482 | | // ARM ARM. There are patterns, but nothing regular enough to make this logic |
4483 | | // neater. So by fiat, these values are UNPREDICTABLE: |
4484 | 1.35k | if (!lookupBankedRegByEncoding((R << 5) | SysM)) |
4485 | 165 | return MCDisassembler_Fail; |
4486 | | |
4487 | 1.18k | MCOperand_CreateImm0(Inst, Val); |
4488 | | |
4489 | 1.18k | return MCDisassembler_Success; |
4490 | 1.35k | } |
4491 | | |
4492 | | static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, |
4493 | | uint64_t Address, const void *Decoder) |
4494 | 591 | { |
4495 | 591 | DecodeStatus S = MCDisassembler_Success; |
4496 | 591 | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4497 | 591 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4498 | 591 | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
4499 | | |
4500 | 591 | if (Rn == 0xF) |
4501 | 464 | S = MCDisassembler_SoftFail; |
4502 | | |
4503 | 591 | if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) |
4504 | 2 | return MCDisassembler_Fail; |
4505 | | |
4506 | 589 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4507 | 0 | return MCDisassembler_Fail; |
4508 | | |
4509 | 589 | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4510 | 2 | return MCDisassembler_Fail; |
4511 | | |
4512 | 587 | return S; |
4513 | 589 | } |
4514 | | |
4515 | | static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, |
4516 | | uint64_t Address, const void *Decoder) |
4517 | 584 | { |
4518 | 584 | DecodeStatus S = MCDisassembler_Success; |
4519 | 584 | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4520 | 584 | unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); |
4521 | 584 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4522 | 584 | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
4523 | | |
4524 | 584 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
4525 | 0 | return MCDisassembler_Fail; |
4526 | | |
4527 | 584 | if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) |
4528 | 439 | S = MCDisassembler_SoftFail; |
4529 | | |
4530 | 584 | if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) |
4531 | 3 | return MCDisassembler_Fail; |
4532 | | |
4533 | 581 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4534 | 0 | return MCDisassembler_Fail; |
4535 | | |
4536 | 581 | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4537 | 3 | return MCDisassembler_Fail; |
4538 | | |
4539 | 578 | return S; |
4540 | 581 | } |
4541 | | |
4542 | | static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, |
4543 | | uint64_t Address, const void *Decoder) |
4544 | 4.38k | { |
4545 | 4.38k | DecodeStatus S = MCDisassembler_Success; |
4546 | 4.38k | unsigned pred; |
4547 | 4.38k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4548 | 4.38k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4549 | 4.38k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
4550 | 4.38k | imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; |
4551 | 4.38k | imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; |
4552 | 4.38k | pred = fieldFromInstruction_4(Insn, 28, 4); |
4553 | | |
4554 | 4.38k | if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; |
4555 | | |
4556 | 4.38k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
4557 | 0 | return MCDisassembler_Fail; |
4558 | | |
4559 | 4.38k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4560 | 0 | return MCDisassembler_Fail; |
4561 | | |
4562 | 4.38k | if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) |
4563 | 0 | return MCDisassembler_Fail; |
4564 | | |
4565 | 4.38k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4566 | 16 | return MCDisassembler_Fail; |
4567 | | |
4568 | 4.37k | return S; |
4569 | 4.38k | } |
4570 | | |
4571 | | static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, |
4572 | | uint64_t Address, const void *Decoder) |
4573 | 1.70k | { |
4574 | 1.70k | DecodeStatus S = MCDisassembler_Success; |
4575 | 1.70k | unsigned pred, Rm; |
4576 | 1.70k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4577 | 1.70k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4578 | 1.70k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
4579 | 1.70k | imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; |
4580 | 1.70k | imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; |
4581 | 1.70k | pred = fieldFromInstruction_4(Insn, 28, 4); |
4582 | 1.70k | Rm = fieldFromInstruction_4(Insn, 0, 4); |
4583 | | |
4584 | 1.70k | if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; |
4585 | 1.70k | if (Rm == 0xF) S = MCDisassembler_SoftFail; |
4586 | | |
4587 | 1.70k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
4588 | 0 | return MCDisassembler_Fail; |
4589 | | |
4590 | 1.70k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4591 | 0 | return MCDisassembler_Fail; |
4592 | | |
4593 | 1.70k | if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) |
4594 | 0 | return MCDisassembler_Fail; |
4595 | | |
4596 | 1.70k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4597 | 5 | return MCDisassembler_Fail; |
4598 | | |
4599 | 1.70k | return S; |
4600 | 1.70k | } |
4601 | | |
4602 | | static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, |
4603 | | uint64_t Address, const void *Decoder) |
4604 | 4.86k | { |
4605 | 4.86k | DecodeStatus S = MCDisassembler_Success; |
4606 | 4.86k | unsigned pred; |
4607 | 4.86k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4608 | 4.86k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4609 | 4.86k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
4610 | 4.86k | imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; |
4611 | 4.86k | imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; |
4612 | 4.86k | pred = fieldFromInstruction_4(Insn, 28, 4); |
4613 | | |
4614 | 4.86k | if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; |
4615 | | |
4616 | 4.86k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4617 | 0 | return MCDisassembler_Fail; |
4618 | | |
4619 | 4.86k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
4620 | 0 | return MCDisassembler_Fail; |
4621 | | |
4622 | 4.86k | if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) |
4623 | 0 | return MCDisassembler_Fail; |
4624 | | |
4625 | 4.86k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4626 | 5 | return MCDisassembler_Fail; |
4627 | | |
4628 | 4.86k | return S; |
4629 | 4.86k | } |
4630 | | |
4631 | | static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, |
4632 | | uint64_t Address, const void *Decoder) |
4633 | 3.24k | { |
4634 | 3.24k | DecodeStatus S = MCDisassembler_Success; |
4635 | 3.24k | unsigned pred; |
4636 | 3.24k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4637 | 3.24k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
4638 | 3.24k | unsigned imm = fieldFromInstruction_4(Insn, 0, 12); |
4639 | 3.24k | imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; |
4640 | 3.24k | imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; |
4641 | 3.24k | pred = fieldFromInstruction_4(Insn, 28, 4); |
4642 | | |
4643 | 3.24k | if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; |
4644 | | |
4645 | 3.24k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4646 | 0 | return MCDisassembler_Fail; |
4647 | | |
4648 | 3.24k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
4649 | 0 | return MCDisassembler_Fail; |
4650 | | |
4651 | 3.24k | if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) |
4652 | 0 | return MCDisassembler_Fail; |
4653 | | |
4654 | 3.24k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
4655 | 4 | return MCDisassembler_Fail; |
4656 | | |
4657 | 3.24k | return S; |
4658 | 3.24k | } |
4659 | | |
4660 | | static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, |
4661 | | uint64_t Address, const void *Decoder) |
4662 | 2.85k | { |
4663 | 2.85k | DecodeStatus S = MCDisassembler_Success; |
4664 | 2.85k | unsigned size, align = 0, index = 0; |
4665 | 2.85k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4666 | 2.85k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4667 | 2.85k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4668 | 2.85k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
4669 | 2.85k | size = fieldFromInstruction_4(Insn, 10, 2); |
4670 | | |
4671 | 2.85k | switch (size) { |
4672 | 0 | default: |
4673 | 0 | return MCDisassembler_Fail; |
4674 | 1.07k | case 0: |
4675 | 1.07k | if (fieldFromInstruction_4(Insn, 4, 1)) |
4676 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4677 | 1.07k | index = fieldFromInstruction_4(Insn, 5, 3); |
4678 | 1.07k | break; |
4679 | 1.12k | case 1: |
4680 | 1.12k | if (fieldFromInstruction_4(Insn, 5, 1)) |
4681 | 2 | return MCDisassembler_Fail; // UNDEFINED |
4682 | 1.12k | index = fieldFromInstruction_4(Insn, 6, 2); |
4683 | 1.12k | if (fieldFromInstruction_4(Insn, 4, 1)) |
4684 | 315 | align = 2; |
4685 | 1.12k | break; |
4686 | 655 | case 2: |
4687 | 655 | if (fieldFromInstruction_4(Insn, 6, 1)) |
4688 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4689 | | |
4690 | 655 | index = fieldFromInstruction_4(Insn, 7, 1); |
4691 | | |
4692 | 655 | switch (fieldFromInstruction_4(Insn, 4, 2)) { |
4693 | 497 | case 0 : |
4694 | 497 | align = 0; break; |
4695 | 151 | case 3: |
4696 | 151 | align = 4; break; |
4697 | 7 | default: |
4698 | 7 | return MCDisassembler_Fail; |
4699 | 655 | } |
4700 | 648 | break; |
4701 | 2.85k | } |
4702 | | |
4703 | 2.84k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4704 | 0 | return MCDisassembler_Fail; |
4705 | | |
4706 | 2.84k | if (Rm != 0xF) { // Writeback |
4707 | 2.02k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4708 | 0 | return MCDisassembler_Fail; |
4709 | 2.02k | } |
4710 | | |
4711 | 2.84k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4712 | 0 | return MCDisassembler_Fail; |
4713 | | |
4714 | 2.84k | MCOperand_CreateImm0(Inst, align); |
4715 | | |
4716 | 2.84k | if (Rm != 0xF) { |
4717 | 2.02k | if (Rm != 0xD) { |
4718 | 1.11k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4719 | 0 | return MCDisassembler_Fail; |
4720 | 1.11k | } else |
4721 | 908 | MCOperand_CreateReg0(Inst, 0); |
4722 | 2.02k | } |
4723 | | |
4724 | 2.84k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4725 | 0 | return MCDisassembler_Fail; |
4726 | | |
4727 | 2.84k | MCOperand_CreateImm0(Inst, index); |
4728 | | |
4729 | 2.84k | return S; |
4730 | 2.84k | } |
4731 | | |
4732 | | static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, |
4733 | | uint64_t Address, const void *Decoder) |
4734 | 2.24k | { |
4735 | 2.24k | DecodeStatus S = MCDisassembler_Success; |
4736 | 2.24k | unsigned size, align = 0, index = 0; |
4737 | 2.24k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4738 | 2.24k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4739 | 2.24k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4740 | 2.24k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
4741 | 2.24k | size = fieldFromInstruction_4(Insn, 10, 2); |
4742 | | |
4743 | 2.24k | switch (size) { |
4744 | 0 | default: |
4745 | 0 | return MCDisassembler_Fail; |
4746 | 938 | case 0: |
4747 | 938 | if (fieldFromInstruction_4(Insn, 4, 1)) |
4748 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4749 | | |
4750 | 938 | index = fieldFromInstruction_4(Insn, 5, 3); |
4751 | 938 | break; |
4752 | 683 | case 1: |
4753 | 683 | if (fieldFromInstruction_4(Insn, 5, 1)) |
4754 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4755 | | |
4756 | 683 | index = fieldFromInstruction_4(Insn, 6, 2); |
4757 | 683 | if (fieldFromInstruction_4(Insn, 4, 1)) |
4758 | 165 | align = 2; |
4759 | 683 | break; |
4760 | 624 | case 2: |
4761 | 624 | if (fieldFromInstruction_4(Insn, 6, 1)) |
4762 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4763 | | |
4764 | 624 | index = fieldFromInstruction_4(Insn, 7, 1); |
4765 | | |
4766 | 624 | switch (fieldFromInstruction_4(Insn, 4, 2)) { |
4767 | 466 | case 0: |
4768 | 466 | align = 0; break; |
4769 | 154 | case 3: |
4770 | 154 | align = 4; break; |
4771 | 4 | default: |
4772 | 4 | return MCDisassembler_Fail; |
4773 | 624 | } |
4774 | 620 | break; |
4775 | 2.24k | } |
4776 | | |
4777 | 2.24k | if (Rm != 0xF) { // Writeback |
4778 | 1.35k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4779 | 0 | return MCDisassembler_Fail; |
4780 | 1.35k | } |
4781 | | |
4782 | 2.24k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4783 | 0 | return MCDisassembler_Fail; |
4784 | | |
4785 | 2.24k | MCOperand_CreateImm0(Inst, align); |
4786 | | |
4787 | 2.24k | if (Rm != 0xF) { |
4788 | 1.35k | if (Rm != 0xD) { |
4789 | 912 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4790 | 0 | return MCDisassembler_Fail; |
4791 | 912 | } else |
4792 | 441 | MCOperand_CreateReg0(Inst, 0); |
4793 | 1.35k | } |
4794 | | |
4795 | 2.24k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4796 | 0 | return MCDisassembler_Fail; |
4797 | | |
4798 | 2.24k | MCOperand_CreateImm0(Inst, index); |
4799 | | |
4800 | 2.24k | return S; |
4801 | 2.24k | } |
4802 | | |
4803 | | static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, |
4804 | | uint64_t Address, const void *Decoder) |
4805 | 3.47k | { |
4806 | 3.47k | DecodeStatus S = MCDisassembler_Success; |
4807 | 3.47k | unsigned size, align = 0, index = 0, inc = 1; |
4808 | 3.47k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4809 | 3.47k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4810 | 3.47k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4811 | 3.47k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
4812 | 3.47k | size = fieldFromInstruction_4(Insn, 10, 2); |
4813 | | |
4814 | 3.47k | switch (size) { |
4815 | 0 | default: |
4816 | 0 | return MCDisassembler_Fail; |
4817 | 931 | case 0: |
4818 | 931 | index = fieldFromInstruction_4(Insn, 5, 3); |
4819 | 931 | if (fieldFromInstruction_4(Insn, 4, 1)) |
4820 | 584 | align = 2; |
4821 | 931 | break; |
4822 | 1.40k | case 1: |
4823 | 1.40k | index = fieldFromInstruction_4(Insn, 6, 2); |
4824 | 1.40k | if (fieldFromInstruction_4(Insn, 4, 1)) |
4825 | 760 | align = 4; |
4826 | 1.40k | if (fieldFromInstruction_4(Insn, 5, 1)) |
4827 | 860 | inc = 2; |
4828 | 1.40k | break; |
4829 | 1.14k | case 2: |
4830 | 1.14k | if (fieldFromInstruction_4(Insn, 5, 1)) |
4831 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4832 | | |
4833 | 1.14k | index = fieldFromInstruction_4(Insn, 7, 1); |
4834 | 1.14k | if (fieldFromInstruction_4(Insn, 4, 1) != 0) |
4835 | 787 | align = 8; |
4836 | 1.14k | if (fieldFromInstruction_4(Insn, 6, 1)) |
4837 | 272 | inc = 2; |
4838 | 1.14k | break; |
4839 | 3.47k | } |
4840 | | |
4841 | 3.47k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4842 | 0 | return MCDisassembler_Fail; |
4843 | | |
4844 | 3.47k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
4845 | 4 | return MCDisassembler_Fail; |
4846 | | |
4847 | 3.47k | if (Rm != 0xF) { // Writeback |
4848 | 2.58k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4849 | 0 | return MCDisassembler_Fail; |
4850 | 2.58k | } |
4851 | | |
4852 | 3.47k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4853 | 0 | return MCDisassembler_Fail; |
4854 | | |
4855 | 3.47k | MCOperand_CreateImm0(Inst, align); |
4856 | | |
4857 | 3.47k | if (Rm != 0xF) { |
4858 | 2.58k | if (Rm != 0xD) { |
4859 | 1.64k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4860 | 0 | return MCDisassembler_Fail; |
4861 | 1.64k | } else |
4862 | 943 | MCOperand_CreateReg0(Inst, 0); |
4863 | 2.58k | } |
4864 | | |
4865 | 3.47k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4866 | 0 | return MCDisassembler_Fail; |
4867 | | |
4868 | 3.47k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
4869 | 0 | return MCDisassembler_Fail; |
4870 | | |
4871 | 3.47k | MCOperand_CreateImm0(Inst, index); |
4872 | | |
4873 | 3.47k | return S; |
4874 | 3.47k | } |
4875 | | |
4876 | | static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, |
4877 | | uint64_t Address, const void *Decoder) |
4878 | 3.79k | { |
4879 | 3.79k | DecodeStatus S = MCDisassembler_Success; |
4880 | 3.79k | unsigned size, align = 0, index = 0, inc = 1; |
4881 | 3.79k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4882 | 3.79k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4883 | 3.79k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4884 | 3.79k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
4885 | 3.79k | size = fieldFromInstruction_4(Insn, 10, 2); |
4886 | | |
4887 | 3.79k | switch (size) { |
4888 | 0 | default: |
4889 | 0 | return MCDisassembler_Fail; |
4890 | 1.79k | case 0: |
4891 | 1.79k | index = fieldFromInstruction_4(Insn, 5, 3); |
4892 | 1.79k | if (fieldFromInstruction_4(Insn, 4, 1)) |
4893 | 777 | align = 2; |
4894 | 1.79k | break; |
4895 | 1.13k | case 1: |
4896 | 1.13k | index = fieldFromInstruction_4(Insn, 6, 2); |
4897 | 1.13k | if (fieldFromInstruction_4(Insn, 4, 1)) |
4898 | 688 | align = 4; |
4899 | 1.13k | if (fieldFromInstruction_4(Insn, 5, 1)) |
4900 | 451 | inc = 2; |
4901 | 1.13k | break; |
4902 | 869 | case 2: |
4903 | 869 | if (fieldFromInstruction_4(Insn, 5, 1)) |
4904 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4905 | | |
4906 | 869 | index = fieldFromInstruction_4(Insn, 7, 1); |
4907 | 869 | if (fieldFromInstruction_4(Insn, 4, 1) != 0) |
4908 | 483 | align = 8; |
4909 | 869 | if (fieldFromInstruction_4(Insn, 6, 1)) |
4910 | 341 | inc = 2; |
4911 | 869 | break; |
4912 | 3.79k | } |
4913 | | |
4914 | 3.79k | if (Rm != 0xF) { // Writeback |
4915 | 2.47k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4916 | 0 | return MCDisassembler_Fail; |
4917 | 2.47k | } |
4918 | | |
4919 | 3.79k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4920 | 0 | return MCDisassembler_Fail; |
4921 | | |
4922 | 3.79k | MCOperand_CreateImm0(Inst, align); |
4923 | | |
4924 | 3.79k | if (Rm != 0xF) { |
4925 | 2.47k | if (Rm != 0xD) { |
4926 | 1.64k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4927 | 0 | return MCDisassembler_Fail; |
4928 | 1.64k | } else |
4929 | 828 | MCOperand_CreateReg0(Inst, 0); |
4930 | 2.47k | } |
4931 | | |
4932 | 3.79k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4933 | 0 | return MCDisassembler_Fail; |
4934 | | |
4935 | 3.79k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
4936 | 5 | return MCDisassembler_Fail; |
4937 | | |
4938 | 3.78k | MCOperand_CreateImm0(Inst, index); |
4939 | | |
4940 | 3.78k | return S; |
4941 | 3.79k | } |
4942 | | |
4943 | | static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, |
4944 | | uint64_t Address, const void *Decoder) |
4945 | 2.49k | { |
4946 | 2.49k | DecodeStatus S = MCDisassembler_Success; |
4947 | 2.49k | unsigned size, align = 0, index = 0, inc = 1; |
4948 | 2.49k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
4949 | 2.49k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
4950 | 2.49k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
4951 | 2.49k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
4952 | 2.49k | size = fieldFromInstruction_4(Insn, 10, 2); |
4953 | | |
4954 | 2.49k | switch (size) { |
4955 | 0 | default: |
4956 | 0 | return MCDisassembler_Fail; |
4957 | 706 | case 0: |
4958 | 706 | if (fieldFromInstruction_4(Insn, 4, 1)) |
4959 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4960 | 706 | index = fieldFromInstruction_4(Insn, 5, 3); |
4961 | 706 | break; |
4962 | 678 | case 1: |
4963 | 678 | if (fieldFromInstruction_4(Insn, 4, 1)) |
4964 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4965 | 678 | index = fieldFromInstruction_4(Insn, 6, 2); |
4966 | 678 | if (fieldFromInstruction_4(Insn, 5, 1)) |
4967 | 380 | inc = 2; |
4968 | 678 | break; |
4969 | 1.11k | case 2: |
4970 | 1.11k | if (fieldFromInstruction_4(Insn, 4, 2)) |
4971 | 0 | return MCDisassembler_Fail; // UNDEFINED |
4972 | 1.11k | index = fieldFromInstruction_4(Insn, 7, 1); |
4973 | 1.11k | if (fieldFromInstruction_4(Insn, 6, 1)) |
4974 | 291 | inc = 2; |
4975 | 1.11k | break; |
4976 | 2.49k | } |
4977 | | |
4978 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
4979 | 0 | return MCDisassembler_Fail; |
4980 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
4981 | 2 | return MCDisassembler_Fail; |
4982 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
4983 | 2 | return MCDisassembler_Fail; |
4984 | | |
4985 | 2.49k | if (Rm != 0xF) { // Writeback |
4986 | 1.33k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4987 | 0 | return MCDisassembler_Fail; |
4988 | 1.33k | } |
4989 | | |
4990 | 2.49k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
4991 | 0 | return MCDisassembler_Fail; |
4992 | | |
4993 | 2.49k | MCOperand_CreateImm0(Inst, align); |
4994 | | |
4995 | 2.49k | if (Rm != 0xF) { |
4996 | 1.33k | if (Rm != 0xD) { |
4997 | 731 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
4998 | 0 | return MCDisassembler_Fail; |
4999 | 731 | } else |
5000 | 604 | MCOperand_CreateReg0(Inst, 0); |
5001 | 1.33k | } |
5002 | | |
5003 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
5004 | 0 | return MCDisassembler_Fail; |
5005 | | |
5006 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
5007 | 0 | return MCDisassembler_Fail; |
5008 | | |
5009 | 2.49k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
5010 | 0 | return MCDisassembler_Fail; |
5011 | | |
5012 | 2.49k | MCOperand_CreateImm0(Inst, index); |
5013 | | |
5014 | 2.49k | return S; |
5015 | 2.49k | } |
5016 | | |
5017 | | static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, |
5018 | | uint64_t Address, const void *Decoder) |
5019 | 2.43k | { |
5020 | 2.43k | DecodeStatus S = MCDisassembler_Success; |
5021 | 2.43k | unsigned size, align = 0, index = 0, inc = 1; |
5022 | 2.43k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5023 | 2.43k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
5024 | 2.43k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
5025 | 2.43k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
5026 | 2.43k | size = fieldFromInstruction_4(Insn, 10, 2); |
5027 | | |
5028 | 2.43k | switch (size) { |
5029 | 0 | default: |
5030 | 0 | return MCDisassembler_Fail; |
5031 | 243 | case 0: |
5032 | 243 | if (fieldFromInstruction_4(Insn, 4, 1)) |
5033 | 0 | return MCDisassembler_Fail; // UNDEFINED |
5034 | 243 | index = fieldFromInstruction_4(Insn, 5, 3); |
5035 | 243 | break; |
5036 | 1.38k | case 1: |
5037 | 1.38k | if (fieldFromInstruction_4(Insn, 4, 1)) |
5038 | 0 | return MCDisassembler_Fail; // UNDEFINED |
5039 | 1.38k | index = fieldFromInstruction_4(Insn, 6, 2); |
5040 | 1.38k | if (fieldFromInstruction_4(Insn, 5, 1)) |
5041 | 334 | inc = 2; |
5042 | 1.38k | break; |
5043 | 807 | case 2: |
5044 | 807 | if (fieldFromInstruction_4(Insn, 4, 2)) |
5045 | 0 | return MCDisassembler_Fail; // UNDEFINED |
5046 | 807 | index = fieldFromInstruction_4(Insn, 7, 1); |
5047 | 807 | if (fieldFromInstruction_4(Insn, 6, 1)) |
5048 | 126 | inc = 2; |
5049 | 807 | break; |
5050 | 2.43k | } |
5051 | | |
5052 | 2.43k | if (Rm != 0xF) { // Writeback |
5053 | 1.27k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5054 | 0 | return MCDisassembler_Fail; |
5055 | 1.27k | } |
5056 | | |
5057 | 2.43k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5058 | 0 | return MCDisassembler_Fail; |
5059 | | |
5060 | 2.43k | MCOperand_CreateImm0(Inst, align); |
5061 | | |
5062 | 2.43k | if (Rm != 0xF) { |
5063 | 1.27k | if (Rm != 0xD) { |
5064 | 934 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
5065 | 0 | return MCDisassembler_Fail; |
5066 | 934 | } else |
5067 | 342 | MCOperand_CreateReg0(Inst, 0); |
5068 | 1.27k | } |
5069 | | |
5070 | 2.43k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
5071 | 0 | return MCDisassembler_Fail; |
5072 | | |
5073 | 2.43k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
5074 | 2 | return MCDisassembler_Fail; |
5075 | | |
5076 | 2.43k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
5077 | 3 | return MCDisassembler_Fail; |
5078 | | |
5079 | 2.43k | MCOperand_CreateImm0(Inst, index); |
5080 | | |
5081 | 2.43k | return S; |
5082 | 2.43k | } |
5083 | | |
5084 | | static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, |
5085 | | uint64_t Address, const void *Decoder) |
5086 | 5.18k | { |
5087 | 5.18k | DecodeStatus S = MCDisassembler_Success; |
5088 | 5.18k | unsigned size, align = 0, index = 0, inc = 1; |
5089 | 5.18k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5090 | 5.18k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
5091 | 5.18k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
5092 | 5.18k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
5093 | 5.18k | size = fieldFromInstruction_4(Insn, 10, 2); |
5094 | | |
5095 | 5.18k | switch (size) { |
5096 | 0 | default: |
5097 | 0 | return MCDisassembler_Fail; |
5098 | 2.57k | case 0: |
5099 | 2.57k | if (fieldFromInstruction_4(Insn, 4, 1)) |
5100 | 440 | align = 4; |
5101 | 2.57k | index = fieldFromInstruction_4(Insn, 5, 3); |
5102 | 2.57k | break; |
5103 | 1.16k | case 1: |
5104 | 1.16k | if (fieldFromInstruction_4(Insn, 4, 1)) |
5105 | 573 | align = 8; |
5106 | 1.16k | index = fieldFromInstruction_4(Insn, 6, 2); |
5107 | 1.16k | if (fieldFromInstruction_4(Insn, 5, 1)) |
5108 | 394 | inc = 2; |
5109 | 1.16k | break; |
5110 | 1.44k | case 2: |
5111 | 1.44k | switch (fieldFromInstruction_4(Insn, 4, 2)) { |
5112 | 601 | case 0: |
5113 | 601 | align = 0; break; |
5114 | 3 | case 3: |
5115 | 3 | return MCDisassembler_Fail; |
5116 | 845 | default: |
5117 | 845 | align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; |
5118 | 1.44k | } |
5119 | | |
5120 | 1.44k | index = fieldFromInstruction_4(Insn, 7, 1); |
5121 | 1.44k | if (fieldFromInstruction_4(Insn, 6, 1)) |
5122 | 952 | inc = 2; |
5123 | 1.44k | break; |
5124 | 5.18k | } |
5125 | | |
5126 | 5.18k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
5127 | 0 | return MCDisassembler_Fail; |
5128 | | |
5129 | 5.18k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
5130 | 3 | return MCDisassembler_Fail; |
5131 | | |
5132 | 5.18k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
5133 | 3 | return MCDisassembler_Fail; |
5134 | | |
5135 | 5.17k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) |
5136 | 3 | return MCDisassembler_Fail; |
5137 | | |
5138 | 5.17k | if (Rm != 0xF) { // Writeback |
5139 | 3.86k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5140 | 0 | return MCDisassembler_Fail; |
5141 | 3.86k | } |
5142 | | |
5143 | 5.17k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5144 | 0 | return MCDisassembler_Fail; |
5145 | | |
5146 | 5.17k | MCOperand_CreateImm0(Inst, align); |
5147 | | |
5148 | 5.17k | if (Rm != 0xF) { |
5149 | 3.86k | if (Rm != 0xD) { |
5150 | 2.13k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
5151 | 0 | return MCDisassembler_Fail; |
5152 | 2.13k | } else |
5153 | 1.72k | MCOperand_CreateReg0(Inst, 0); |
5154 | 3.86k | } |
5155 | | |
5156 | 5.17k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
5157 | 0 | return MCDisassembler_Fail; |
5158 | | |
5159 | 5.17k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
5160 | 0 | return MCDisassembler_Fail; |
5161 | | |
5162 | 5.17k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
5163 | 0 | return MCDisassembler_Fail; |
5164 | | |
5165 | 5.17k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) |
5166 | 0 | return MCDisassembler_Fail; |
5167 | | |
5168 | 5.17k | MCOperand_CreateImm0(Inst, index); |
5169 | | |
5170 | 5.17k | return S; |
5171 | 5.17k | } |
5172 | | |
5173 | | static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, |
5174 | | uint64_t Address, const void *Decoder) |
5175 | 2.31k | { |
5176 | 2.31k | DecodeStatus S = MCDisassembler_Success; |
5177 | 2.31k | unsigned size, align = 0, index = 0, inc = 1; |
5178 | 2.31k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5179 | 2.31k | unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); |
5180 | 2.31k | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
5181 | 2.31k | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
5182 | 2.31k | size = fieldFromInstruction_4(Insn, 10, 2); |
5183 | | |
5184 | 2.31k | switch (size) { |
5185 | 0 | default: |
5186 | 0 | return MCDisassembler_Fail; |
5187 | 915 | case 0: |
5188 | 915 | if (fieldFromInstruction_4(Insn, 4, 1)) |
5189 | 279 | align = 4; |
5190 | 915 | index = fieldFromInstruction_4(Insn, 5, 3); |
5191 | 915 | break; |
5192 | 584 | case 1: |
5193 | 584 | if (fieldFromInstruction_4(Insn, 4, 1)) |
5194 | 260 | align = 8; |
5195 | 584 | index = fieldFromInstruction_4(Insn, 6, 2); |
5196 | 584 | if (fieldFromInstruction_4(Insn, 5, 1)) |
5197 | 193 | inc = 2; |
5198 | 584 | break; |
5199 | 815 | case 2: |
5200 | 815 | switch (fieldFromInstruction_4(Insn, 4, 2)) { |
5201 | 412 | case 0: |
5202 | 412 | align = 0; break; |
5203 | 4 | case 3: |
5204 | 4 | return MCDisassembler_Fail; |
5205 | 399 | default: |
5206 | 399 | align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; |
5207 | 815 | } |
5208 | | |
5209 | 811 | index = fieldFromInstruction_4(Insn, 7, 1); |
5210 | 811 | if (fieldFromInstruction_4(Insn, 6, 1)) |
5211 | 343 | inc = 2; |
5212 | 811 | break; |
5213 | 2.31k | } |
5214 | | |
5215 | 2.31k | if (Rm != 0xF) { // Writeback |
5216 | 1.61k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5217 | 0 | return MCDisassembler_Fail; |
5218 | 1.61k | } |
5219 | | |
5220 | 2.31k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5221 | 0 | return MCDisassembler_Fail; |
5222 | | |
5223 | 2.31k | MCOperand_CreateImm0(Inst, align); |
5224 | | |
5225 | 2.31k | if (Rm != 0xF) { |
5226 | 1.61k | if (Rm != 0xD) { |
5227 | 1.16k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
5228 | 0 | return MCDisassembler_Fail; |
5229 | 1.16k | } else |
5230 | 448 | MCOperand_CreateReg0(Inst, 0); |
5231 | 1.61k | } |
5232 | | |
5233 | 2.31k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
5234 | 0 | return MCDisassembler_Fail; |
5235 | | |
5236 | 2.31k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) |
5237 | 4 | return MCDisassembler_Fail; |
5238 | | |
5239 | 2.30k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) |
5240 | 2 | return MCDisassembler_Fail; |
5241 | | |
5242 | 2.30k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) |
5243 | 2 | return MCDisassembler_Fail; |
5244 | | |
5245 | 2.30k | MCOperand_CreateImm0(Inst, index); |
5246 | | |
5247 | 2.30k | return S; |
5248 | 2.30k | } |
5249 | | |
5250 | | static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, |
5251 | | uint64_t Address, const void *Decoder) |
5252 | 251 | { |
5253 | 251 | DecodeStatus S = MCDisassembler_Success; |
5254 | 251 | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
5255 | 251 | unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); |
5256 | 251 | unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); |
5257 | 251 | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
5258 | 251 | Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; |
5259 | | |
5260 | 251 | if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) |
5261 | 189 | S = MCDisassembler_SoftFail; |
5262 | | |
5263 | 251 | if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) |
5264 | 0 | return MCDisassembler_Fail; |
5265 | | |
5266 | 251 | if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) |
5267 | 2 | return MCDisassembler_Fail; |
5268 | | |
5269 | 249 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) |
5270 | 0 | return MCDisassembler_Fail; |
5271 | | |
5272 | 249 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) |
5273 | 0 | return MCDisassembler_Fail; |
5274 | | |
5275 | 249 | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
5276 | 2 | return MCDisassembler_Fail; |
5277 | | |
5278 | 247 | return S; |
5279 | 249 | } |
5280 | | |
5281 | | static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, |
5282 | | uint64_t Address, const void *Decoder) |
5283 | 1.56k | { |
5284 | 1.56k | DecodeStatus S = MCDisassembler_Success; |
5285 | 1.56k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
5286 | 1.56k | unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); |
5287 | 1.56k | unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); |
5288 | 1.56k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
5289 | 1.56k | Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; |
5290 | | |
5291 | 1.56k | if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) |
5292 | 1.33k | S = MCDisassembler_SoftFail; |
5293 | | |
5294 | 1.56k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) |
5295 | 0 | return MCDisassembler_Fail; |
5296 | | |
5297 | 1.56k | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) |
5298 | 0 | return MCDisassembler_Fail; |
5299 | | |
5300 | 1.56k | if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) |
5301 | 0 | return MCDisassembler_Fail; |
5302 | | |
5303 | 1.56k | if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) |
5304 | 4 | return MCDisassembler_Fail; |
5305 | | |
5306 | 1.56k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
5307 | 2 | return MCDisassembler_Fail; |
5308 | | |
5309 | 1.55k | return S; |
5310 | 1.56k | } |
5311 | | |
5312 | | static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, |
5313 | | uint64_t Address, const void *Decoder) |
5314 | 6.49k | { |
5315 | 6.49k | DecodeStatus S = MCDisassembler_Success; |
5316 | 6.49k | unsigned pred = fieldFromInstruction_4(Insn, 4, 4); |
5317 | 6.49k | unsigned mask = fieldFromInstruction_4(Insn, 0, 4); |
5318 | | |
5319 | 6.49k | if (pred == 0xF) { |
5320 | 1.08k | pred = 0xE; |
5321 | 1.08k | S = MCDisassembler_SoftFail; |
5322 | 1.08k | } |
5323 | | |
5324 | 6.49k | if (mask == 0x0) |
5325 | 0 | return MCDisassembler_Fail; |
5326 | | |
5327 | 6.49k | MCOperand_CreateImm0(Inst, pred); |
5328 | 6.49k | MCOperand_CreateImm0(Inst, mask); |
5329 | | |
5330 | 6.49k | return S; |
5331 | 6.49k | } |
5332 | | |
5333 | | static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, |
5334 | | uint64_t Address, const void *Decoder) |
5335 | 6.03k | { |
5336 | 6.03k | DecodeStatus S = MCDisassembler_Success; |
5337 | 6.03k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
5338 | 6.03k | unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); |
5339 | 6.03k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5340 | 6.03k | unsigned addr = fieldFromInstruction_4(Insn, 0, 8); |
5341 | 6.03k | unsigned W = fieldFromInstruction_4(Insn, 21, 1); |
5342 | 6.03k | unsigned U = fieldFromInstruction_4(Insn, 23, 1); |
5343 | 6.03k | unsigned P = fieldFromInstruction_4(Insn, 24, 1); |
5344 | 6.03k | bool writeback = (W == 1) | (P == 0); |
5345 | | |
5346 | 6.03k | addr |= (U << 8) | (Rn << 9); |
5347 | | |
5348 | 6.03k | if (writeback && (Rn == Rt || Rn == Rt2)) |
5349 | 3.33k | Check(&S, MCDisassembler_SoftFail); |
5350 | | |
5351 | 6.03k | if (Rt == Rt2) |
5352 | 1.03k | Check(&S, MCDisassembler_SoftFail); |
5353 | | |
5354 | | // Rt |
5355 | 6.03k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
5356 | 0 | return MCDisassembler_Fail; |
5357 | | |
5358 | | // Rt2 |
5359 | 6.03k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) |
5360 | 0 | return MCDisassembler_Fail; |
5361 | | |
5362 | | // Writeback operand |
5363 | 6.03k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5364 | 0 | return MCDisassembler_Fail; |
5365 | | |
5366 | | // addr |
5367 | 6.03k | if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) |
5368 | 0 | return MCDisassembler_Fail; |
5369 | | |
5370 | 6.03k | return S; |
5371 | 6.03k | } |
5372 | | |
5373 | | static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, |
5374 | | uint64_t Address, const void *Decoder) |
5375 | 7.14k | { |
5376 | 7.14k | DecodeStatus S = MCDisassembler_Success; |
5377 | 7.14k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
5378 | 7.14k | unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); |
5379 | 7.14k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5380 | 7.14k | unsigned addr = fieldFromInstruction_4(Insn, 0, 8); |
5381 | 7.14k | unsigned W = fieldFromInstruction_4(Insn, 21, 1); |
5382 | 7.14k | unsigned U = fieldFromInstruction_4(Insn, 23, 1); |
5383 | 7.14k | unsigned P = fieldFromInstruction_4(Insn, 24, 1); |
5384 | 7.14k | bool writeback = (W == 1) | (P == 0); |
5385 | | |
5386 | 7.14k | addr |= (U << 8) | (Rn << 9); |
5387 | | |
5388 | 7.14k | if (writeback && (Rn == Rt || Rn == Rt2)) |
5389 | 3.11k | Check(&S, MCDisassembler_SoftFail); |
5390 | | |
5391 | | // Writeback operand |
5392 | 7.14k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) |
5393 | 0 | return MCDisassembler_Fail; |
5394 | | |
5395 | | // Rt |
5396 | 7.14k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
5397 | 0 | return MCDisassembler_Fail; |
5398 | | |
5399 | | // Rt2 |
5400 | 7.14k | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) |
5401 | 0 | return MCDisassembler_Fail; |
5402 | | |
5403 | | // addr |
5404 | 7.14k | if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) |
5405 | 0 | return MCDisassembler_Fail; |
5406 | | |
5407 | 7.14k | return S; |
5408 | 7.14k | } |
5409 | | |
5410 | | static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, |
5411 | | uint64_t Address, const void *Decoder) |
5412 | 1 | { |
5413 | 1 | unsigned Val; |
5414 | 1 | unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); |
5415 | 1 | unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); |
5416 | | |
5417 | 1 | if (sign1 != sign2) return MCDisassembler_Fail; |
5418 | | |
5419 | 0 | Val = fieldFromInstruction_4(Insn, 0, 8); |
5420 | 0 | Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; |
5421 | 0 | Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; |
5422 | 0 | Val |= sign1 << 12; |
5423 | |
|
5424 | 0 | MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); |
5425 | |
|
5426 | 0 | return MCDisassembler_Success; |
5427 | 1 | } |
5428 | | |
5429 | | static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, |
5430 | | uint64_t Address, const void *Decoder) |
5431 | 3.00k | { |
5432 | | // Shift of "asr #32" is not allowed in Thumb2 mode. |
5433 | 3.00k | if (Val == 0x20) |
5434 | 436 | return MCDisassembler_Fail; |
5435 | | |
5436 | 2.56k | MCOperand_CreateImm0(Inst, Val); |
5437 | | |
5438 | 2.56k | return MCDisassembler_Success; |
5439 | 3.00k | } |
5440 | | |
5441 | | static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, |
5442 | | uint64_t Address, const void *Decoder) |
5443 | 2.92k | { |
5444 | 2.92k | DecodeStatus S; |
5445 | 2.92k | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
5446 | 2.92k | unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); |
5447 | 2.92k | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
5448 | 2.92k | unsigned pred = fieldFromInstruction_4(Insn, 28, 4); |
5449 | | |
5450 | 2.92k | if (pred == 0xF) |
5451 | 341 | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
5452 | | |
5453 | 2.58k | S = MCDisassembler_Success; |
5454 | | |
5455 | 2.58k | if (Rt == Rn || Rn == Rt2) |
5456 | 659 | S = MCDisassembler_SoftFail; |
5457 | | |
5458 | 2.58k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
5459 | 0 | return MCDisassembler_Fail; |
5460 | | |
5461 | 2.58k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
5462 | 0 | return MCDisassembler_Fail; |
5463 | | |
5464 | 2.58k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
5465 | 0 | return MCDisassembler_Fail; |
5466 | | |
5467 | 2.58k | if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
5468 | 0 | return MCDisassembler_Fail; |
5469 | | |
5470 | 2.58k | return S; |
5471 | 2.58k | } |
5472 | | |
5473 | | static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, |
5474 | | uint64_t Address, const void *Decoder) |
5475 | 2.89k | { |
5476 | 2.89k | DecodeStatus S = MCDisassembler_Success; |
5477 | 2.89k | bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); |
5478 | 2.89k | unsigned Vm, imm, cmode, op; |
5479 | 2.89k | unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); |
5480 | | |
5481 | 2.89k | Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); |
5482 | 2.89k | Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); |
5483 | 2.89k | Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); |
5484 | 2.89k | imm = fieldFromInstruction_4(Insn, 16, 6); |
5485 | 2.89k | cmode = fieldFromInstruction_4(Insn, 8, 4); |
5486 | 2.89k | op = fieldFromInstruction_4(Insn, 5, 1); |
5487 | | |
5488 | | // If the top 3 bits of imm are clear, this is a VMOV (immediate) |
5489 | 2.89k | if (!(imm & 0x38)) { |
5490 | 1.13k | if (cmode == 0xF) { |
5491 | 171 | if (op == 1) return MCDisassembler_Fail; |
5492 | 168 | MCInst_setOpcode(Inst, ARM_VMOVv2f32); |
5493 | 168 | } |
5494 | | |
5495 | 1.12k | if (hasFullFP16) { |
5496 | 1.12k | if (cmode == 0xE) { |
5497 | 0 | if (op == 1) { |
5498 | 0 | MCInst_setOpcode(Inst, ARM_VMOVv1i64); |
5499 | 0 | } else { |
5500 | 0 | MCInst_setOpcode(Inst, ARM_VMOVv8i8); |
5501 | 0 | } |
5502 | 0 | } |
5503 | | |
5504 | 1.12k | if (cmode == 0xD) { |
5505 | 776 | if (op == 1) { |
5506 | 666 | MCInst_setOpcode(Inst, ARM_VMVNv2i32); |
5507 | 666 | } else { |
5508 | 110 | MCInst_setOpcode(Inst, ARM_VMOVv2i32); |
5509 | 110 | } |
5510 | 776 | } |
5511 | | |
5512 | 1.12k | if (cmode == 0xC) { |
5513 | 185 | if (op == 1) { |
5514 | 102 | MCInst_setOpcode(Inst, ARM_VMVNv2i32); |
5515 | 102 | } else { |
5516 | 83 | MCInst_setOpcode(Inst, ARM_VMOVv2i32); |
5517 | 83 | } |
5518 | 185 | } |
5519 | 1.12k | } |
5520 | | |
5521 | 1.12k | return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); |
5522 | 1.13k | } |
5523 | | |
5524 | 1.76k | if (!(imm & 0x20)) return MCDisassembler_Fail; |
5525 | | |
5526 | 1.75k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
5527 | 0 | return MCDisassembler_Fail; |
5528 | | |
5529 | 1.75k | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) |
5530 | 0 | return MCDisassembler_Fail; |
5531 | | |
5532 | 1.75k | MCOperand_CreateImm0(Inst, 64 - imm); |
5533 | | |
5534 | 1.75k | return S; |
5535 | 1.75k | } |
5536 | | |
5537 | | static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, |
5538 | | uint64_t Address, const void *Decoder) |
5539 | 594 | { |
5540 | 594 | DecodeStatus S = MCDisassembler_Success; |
5541 | 594 | bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); |
5542 | 594 | unsigned Vm, imm, cmode, op; |
5543 | 594 | unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); |
5544 | | |
5545 | 594 | Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); |
5546 | 594 | Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); |
5547 | 594 | Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); |
5548 | 594 | imm = fieldFromInstruction_4(Insn, 16, 6); |
5549 | 594 | cmode = fieldFromInstruction_4(Insn, 8, 4); |
5550 | 594 | op = fieldFromInstruction_4(Insn, 5, 1); |
5551 | | |
5552 | | // VMOVv4f32 is ambiguous with these decodings. |
5553 | 594 | if (!(imm & 0x38) && cmode == 0xF) { |
5554 | 70 | if (op == 1) return MCDisassembler_Fail; |
5555 | 69 | MCInst_setOpcode(Inst, ARM_VMOVv4f32); |
5556 | 69 | return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); |
5557 | 70 | } |
5558 | | |
5559 | | // If the top 3 bits of imm are clear, this is a VMOV (immediate) |
5560 | 524 | if (!(imm & 0x38)) { |
5561 | 293 | if (cmode == 0xF) { |
5562 | 0 | if (op == 1) return MCDisassembler_Fail; |
5563 | 0 | MCInst_setOpcode(Inst, ARM_VMOVv4f32); |
5564 | 0 | } |
5565 | | |
5566 | 293 | if (hasFullFP16) { |
5567 | 293 | if (cmode == 0xE) { |
5568 | 0 | if (op == 1) { |
5569 | 0 | MCInst_setOpcode(Inst, ARM_VMOVv2i64); |
5570 | 0 | } else { |
5571 | 0 | MCInst_setOpcode(Inst, ARM_VMOVv16i8); |
5572 | 0 | } |
5573 | 0 | } |
5574 | | |
5575 | 293 | if (cmode == 0xD) { |
5576 | 156 | if (op == 1) { |
5577 | 66 | MCInst_setOpcode(Inst, ARM_VMVNv4i32); |
5578 | 90 | } else { |
5579 | 90 | MCInst_setOpcode(Inst, ARM_VMOVv4i32); |
5580 | 90 | } |
5581 | 156 | } |
5582 | | |
5583 | 293 | if (cmode == 0xC) { |
5584 | 137 | if (op == 1) { |
5585 | 70 | MCInst_setOpcode(Inst, ARM_VMVNv4i32); |
5586 | 70 | } else { |
5587 | 67 | MCInst_setOpcode(Inst, ARM_VMOVv4i32); |
5588 | 67 | } |
5589 | 137 | } |
5590 | 293 | } |
5591 | | |
5592 | 293 | return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); |
5593 | 293 | } |
5594 | | |
5595 | 231 | if (!(imm & 0x20)) return MCDisassembler_Fail; |
5596 | | |
5597 | 230 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) |
5598 | 2 | return MCDisassembler_Fail; |
5599 | | |
5600 | 228 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) |
5601 | 3 | return MCDisassembler_Fail; |
5602 | | |
5603 | 225 | MCOperand_CreateImm0(Inst, 64 - imm); |
5604 | | |
5605 | 225 | return S; |
5606 | 228 | } |
5607 | | |
5608 | | static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, |
5609 | | uint64_t Address, const void *Decoder) |
5610 | 104 | { |
5611 | 104 | DecodeStatus S = MCDisassembler_Success; |
5612 | 104 | unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); |
5613 | 104 | unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); |
5614 | 104 | unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); |
5615 | 104 | unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); |
5616 | 104 | unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); |
5617 | | |
5618 | 104 | Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); |
5619 | 104 | Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); |
5620 | 104 | Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); |
5621 | | |
5622 | 104 | if (q) { |
5623 | 36 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) |
5624 | 1 | return MCDisassembler_Fail; |
5625 | | |
5626 | 35 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) |
5627 | 0 | return MCDisassembler_Fail; |
5628 | | |
5629 | 35 | if (!Check(&S, DecodeQPRRegisterClass(Inst, Vn, Address, Decoder))) |
5630 | 1 | return MCDisassembler_Fail; |
5631 | 68 | } else { |
5632 | 68 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
5633 | 0 | return MCDisassembler_Fail; |
5634 | | |
5635 | 68 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
5636 | 0 | return MCDisassembler_Fail; |
5637 | | |
5638 | 68 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vn, Address, Decoder))) |
5639 | 0 | return MCDisassembler_Fail; |
5640 | 68 | } |
5641 | | |
5642 | 102 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) |
5643 | 0 | return MCDisassembler_Fail; |
5644 | | |
5645 | | // The lane index does not have any bits in the encoding, because it can only |
5646 | | // be 0. |
5647 | 102 | MCOperand_CreateImm0(Inst, 0); |
5648 | 102 | MCOperand_CreateImm0(Inst, rotate); |
5649 | | |
5650 | 102 | return S; |
5651 | 102 | } |
5652 | | |
5653 | | static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, |
5654 | | uint64_t Address, const void *Decoder) |
5655 | 3.89k | { |
5656 | 3.89k | DecodeStatus S = MCDisassembler_Success; |
5657 | 3.89k | unsigned Cond; |
5658 | 3.89k | unsigned Rn = fieldFromInstruction_4(Val, 16, 4); |
5659 | 3.89k | unsigned Rt = fieldFromInstruction_4(Val, 12, 4); |
5660 | 3.89k | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
5661 | | |
5662 | 3.89k | Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); |
5663 | 3.89k | Cond = fieldFromInstruction_4(Val, 28, 4); |
5664 | | |
5665 | 3.89k | if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) |
5666 | 1.72k | S = MCDisassembler_SoftFail; |
5667 | | |
5668 | 3.89k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
5669 | 0 | return MCDisassembler_Fail; |
5670 | | |
5671 | 3.89k | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
5672 | 0 | return MCDisassembler_Fail; |
5673 | | |
5674 | 3.89k | if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) |
5675 | 0 | return MCDisassembler_Fail; |
5676 | | |
5677 | 3.89k | if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) |
5678 | 0 | return MCDisassembler_Fail; |
5679 | | |
5680 | 3.89k | if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) |
5681 | 2 | return MCDisassembler_Fail; |
5682 | | |
5683 | 3.89k | return S; |
5684 | 3.89k | } |
5685 | | |
5686 | | static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, |
5687 | | uint64_t Address, const void *Decoder) |
5688 | 2.56k | { |
5689 | 2.56k | DecodeStatus result = MCDisassembler_Success; |
5690 | 2.56k | unsigned CRm = fieldFromInstruction_4(Val, 0, 4); |
5691 | 2.56k | unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); |
5692 | 2.56k | unsigned cop = fieldFromInstruction_4(Val, 8, 4); |
5693 | 2.56k | unsigned Rt = fieldFromInstruction_4(Val, 12, 4); |
5694 | 2.56k | unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); |
5695 | | |
5696 | 2.56k | if ((cop & ~0x1) == 0xa) |
5697 | 8 | return MCDisassembler_Fail; |
5698 | | |
5699 | 2.56k | if (Rt == Rt2) |
5700 | 467 | result = MCDisassembler_SoftFail; |
5701 | | |
5702 | | // We have to check if the instruction is MRRC2 |
5703 | | // or MCRR2 when constructing the operands for |
5704 | | // Inst. Reason is because MRRC2 stores to two |
5705 | | // registers so it's tablegen desc has has two |
5706 | | // outputs whereas MCRR doesn't store to any |
5707 | | // registers so all of it's operands are listed |
5708 | | // as inputs, therefore the operand order for |
5709 | | // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] |
5710 | | // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] |
5711 | | |
5712 | 2.56k | if (MCInst_getOpcode(Inst) == ARM_MRRC2) { |
5713 | 813 | if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
5714 | 0 | return MCDisassembler_Fail; |
5715 | | |
5716 | 813 | if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
5717 | 0 | return MCDisassembler_Fail; |
5718 | 813 | } |
5719 | | |
5720 | 2.56k | MCOperand_CreateImm0(Inst, cop); |
5721 | 2.56k | MCOperand_CreateImm0(Inst, opc1); |
5722 | | |
5723 | 2.56k | if (MCInst_getOpcode(Inst) == ARM_MCRR2) { |
5724 | 1.74k | if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
5725 | 0 | return MCDisassembler_Fail; |
5726 | | |
5727 | 1.74k | if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
5728 | 0 | return MCDisassembler_Fail; |
5729 | 1.74k | } |
5730 | | |
5731 | 2.56k | MCOperand_CreateImm0(Inst, CRm); |
5732 | | |
5733 | 2.56k | return result; |
5734 | 2.56k | } |
5735 | | |
5736 | | static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, |
5737 | | uint64_t Address, const void *Decoder) |
5738 | 1.93k | { |
5739 | 1.93k | DecodeStatus result = MCDisassembler_Success; |
5740 | 1.93k | bool HasV8Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops); |
5741 | 1.93k | unsigned Rt = fieldFromInstruction_4(Val, 12, 4); |
5742 | | |
5743 | 1.93k | if ((Inst->csh->mode & CS_MODE_THUMB) && !HasV8Ops) { |
5744 | 1.26k | if (Rt == 13 || Rt == 15) |
5745 | 753 | result = MCDisassembler_SoftFail; |
5746 | | |
5747 | 1.26k | Check(&result, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); |
5748 | 1.26k | } else |
5749 | 672 | Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); |
5750 | | |
5751 | 1.93k | if (Inst->csh->mode & CS_MODE_THUMB) { |
5752 | 1.67k | MCOperand_CreateImm0(Inst, ARMCC_AL); |
5753 | 1.67k | MCOperand_CreateReg0(Inst, 0); |
5754 | 1.67k | } else { |
5755 | 263 | unsigned pred = fieldFromInstruction_4(Val, 28, 4); |
5756 | 263 | if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
5757 | 1 | return MCDisassembler_Fail; |
5758 | 263 | } |
5759 | | |
5760 | 1.93k | return result; |
5761 | 1.93k | } |
5762 | | |
5763 | | #endif |