Coverage Report

Created: 2023-12-08 06:05

/src/capstonev5/arch/M680X/M680XDisassembler.c
Line
Count
Source (jump to first uncovered line)
1
/* Capstone Disassembly Engine */
2
/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
3
4
/* ======================================================================== */
5
/* ================================ INCLUDES ============================== */
6
/* ======================================================================== */
7
8
#include <stdlib.h>
9
#include <stdio.h>
10
#include <string.h>
11
12
#include "../../cs_priv.h"
13
#include "../../utils.h"
14
15
#include "../../MCInst.h"
16
#include "../../MCInstrDesc.h"
17
#include "../../MCRegisterInfo.h"
18
#include "M680XInstPrinter.h"
19
#include "M680XDisassembler.h"
20
#include "M680XDisassemblerInternals.h"
21
22
#ifdef CAPSTONE_HAS_M680X
23
24
#ifndef DECL_SPEC
25
#ifdef _MSC_VER
26
#define DECL_SPEC __cdecl
27
#else
28
#define DECL_SPEC
29
#endif  // _MSC_VER
30
#endif  // DECL_SPEC
31
32
/* ======================================================================== */
33
/* ============================ GENERAL DEFINES =========================== */
34
/* ======================================================================== */
35
36
/* ======================================================================== */
37
/* =============================== PROTOTYPES ============================= */
38
/* ======================================================================== */
39
40
typedef enum insn_hdlr_id {
41
  illgl_hid,
42
  rel8_hid,
43
  rel16_hid,
44
  imm8_hid,
45
  imm16_hid,
46
  imm32_hid,
47
  dir_hid,
48
  ext_hid,
49
  idxX_hid,
50
  idxY_hid,
51
  idx09_hid,
52
  inh_hid,
53
  rr09_hid,
54
  rbits_hid,
55
  bitmv_hid,
56
  tfm_hid,
57
  opidx_hid,
58
  opidxdr_hid,
59
  idxX0_hid,
60
  idxX16_hid,
61
  imm8rel_hid,
62
  idxS_hid,
63
  idxS16_hid,
64
  idxXp_hid,
65
  idxX0p_hid,
66
  idx12_hid,
67
  idx12s_hid,
68
  rr12_hid,
69
  loop_hid,
70
  index_hid,
71
  imm8i12x_hid,
72
  imm16i12x_hid,
73
  exti12x_hid,
74
  HANDLER_ID_ENDING,
75
} insn_hdlr_id;
76
77
// Access modes for the first 4 operands. If there are more than
78
// four operands they use the same access mode as the 4th operand.
79
//
80
// u: unchanged
81
// r: (r)read access
82
// w: (w)write access
83
// m: (m)odify access (= read + write)
84
//
85
typedef enum e_access_mode {
86
87
  uuuu,
88
  rrrr,
89
  wwww,
90
  rwww,
91
  rrrm,
92
  rmmm,
93
  wrrr,
94
  mrrr,
95
  mwww,
96
  mmmm,
97
  mwrr,
98
  mmrr,
99
  wmmm,
100
  rruu,
101
  muuu,
102
  ACCESS_MODE_ENDING,
103
} e_access_mode;
104
105
// Access type values are compatible with enum cs_ac_type:
106
typedef enum e_access {
107
  UNCHANGED = CS_AC_INVALID,
108
  READ = CS_AC_READ,
109
  WRITE = CS_AC_WRITE,
110
  MODIFY = (CS_AC_READ | CS_AC_WRITE),
111
} e_access;
112
113
/* Properties of one instruction in PAGE1 (without prefix) */
114
typedef struct inst_page1 {
115
  unsigned insn : 9;        // A value of type m680x_insn
116
  unsigned handler_id1 : 6; // Type insn_hdlr_id, first instr. handler id
117
  unsigned handler_id2 : 6; // Type insn_hdlr_id, second instr. handler id
118
} inst_page1;
119
120
/* Properties of one instruction in any other PAGE X */
121
typedef struct inst_pageX {
122
  unsigned opcode : 8;      // The opcode byte
123
  unsigned insn : 9;        // A value of type m680x_insn
124
  unsigned handler_id1 : 6; // Type insn_hdlr_id, first instr. handler id
125
  unsigned handler_id2 : 6; // Type insn_hdlr_id, second instr. handler id
126
} inst_pageX;
127
128
typedef struct insn_props {
129
  unsigned group : 4;
130
  unsigned access_mode : 5; // A value of type e_access_mode
131
  unsigned reg0 : 5;        // A value of type m680x_reg
132
  unsigned reg1 : 5;        // A value of type m680x_reg
133
  bool cc_modified : 1;
134
  bool update_reg_access : 1;
135
} insn_props;
136
137
#include "m6800.inc"
138
#include "m6801.inc"
139
#include "hd6301.inc"
140
#include "m6811.inc"
141
#include "cpu12.inc"
142
#include "m6805.inc"
143
#include "m6808.inc"
144
#include "hcs08.inc"
145
#include "m6809.inc"
146
#include "hd6309.inc"
147
148
#include "insn_props.inc"
149
150
//////////////////////////////////////////////////////////////////////////////
151
152
// M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2).
153
// A reader is needed to read a byte or word from a given memory address.
154
// See also X86 reader(...)
155
static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address)
156
1.11M
{
157
1.11M
  if (address < info->offset ||
158
1.11M
    (uint32_t)(address - info->offset) >= info->size)
159
    // out of code buffer range
160
2.00k
    return false;
161
162
1.11M
  *byte = info->code[address - info->offset];
163
164
1.11M
  return true;
165
1.11M
}
166
167
static bool read_byte_sign_extended(const m680x_info *info, int16_t *word,
168
  uint16_t address)
169
64.4k
{
170
64.4k
  if (address < info->offset ||
171
64.4k
    (uint32_t)(address - info->offset) >= info->size)
172
    // out of code buffer range
173
0
    return false;
174
175
64.4k
  *word = (int16_t) info->code[address - info->offset];
176
177
64.4k
  if (*word & 0x80)
178
22.8k
    *word |= 0xFF00;
179
180
64.4k
  return true;
181
64.4k
}
182
183
static bool read_word(const m680x_info *info, uint16_t *word, uint16_t address)
184
83.5k
{
185
83.5k
  if (address < info->offset ||
186
83.5k
    (uint32_t)(address + 1 - info->offset) >= info->size)
187
    // out of code buffer range
188
15
    return false;
189
190
83.5k
  *word = (uint16_t)info->code[address - info->offset] << 8;
191
83.5k
  *word |= (uint16_t)info->code[address + 1 - info->offset];
192
193
83.5k
  return true;
194
83.5k
}
195
196
static bool read_sdword(const m680x_info *info, int32_t *sdword,
197
  uint16_t address)
198
1.44k
{
199
1.44k
  if (address < info->offset ||
200
1.44k
    (uint32_t)(address + 3 - info->offset) >= info->size)
201
    // out of code buffer range
202
0
    return false;
203
204
1.44k
  *sdword = (uint32_t)info->code[address - info->offset] << 24;
205
1.44k
  *sdword |= (uint32_t)info->code[address + 1 - info->offset] << 16;
206
1.44k
  *sdword |= (uint32_t)info->code[address + 2 - info->offset] << 8;
207
1.44k
  *sdword |= (uint32_t)info->code[address + 3 - info->offset];
208
209
1.44k
  return true;
210
1.44k
}
211
212
// For PAGE2 and PAGE3 opcodes when using an an array of inst_page1 most
213
// entries have M680X_INS_ILLGL. To avoid wasting memory an inst_pageX is
214
// used which contains the opcode. Using a binary search for the right opcode
215
// is much faster (= O(log n) ) in comparison to a linear search ( = O(n) ).
216
static int binary_search(const inst_pageX *const inst_pageX_table,
217
  size_t table_size, unsigned int opcode)
218
188k
{
219
  // As part of the algorithm last may get negative.
220
  // => signed integer has to be used.
221
188k
  int first = 0;
222
188k
  int last = (int)table_size - 1;
223
188k
  int middle = (first + last) / 2;
224
225
949k
  while (first <= last) {
226
873k
    if (inst_pageX_table[middle].opcode < opcode) {
227
287k
      first = middle + 1;
228
287k
    }
229
585k
    else if (inst_pageX_table[middle].opcode == opcode) {
230
112k
      return middle;  /* item found */
231
112k
    }
232
473k
    else
233
473k
      last = middle - 1;
234
235
761k
    middle = (first + last) / 2;
236
761k
  }
237
238
76.1k
  if (first > last)
239
76.1k
    return -1;  /* item not found */
240
241
0
  return -2;
242
76.1k
}
243
244
void M680X_get_insn_id(cs_struct *handle, cs_insn *insn, unsigned int id)
245
470k
{
246
470k
  const m680x_info *const info = (const m680x_info *)handle->printer_info;
247
470k
  const cpu_tables *cpu = info->cpu;
248
470k
  uint8_t insn_prefix = (id >> 8) & 0xff;
249
  // opcode is the first instruction byte without the prefix.
250
470k
  uint8_t opcode = id & 0xff;
251
470k
  int index;
252
470k
  int i;
253
254
470k
  insn->id = M680X_INS_ILLGL;
255
256
1.11M
  for (i = 0; i < ARR_SIZE(cpu->pageX_prefix); ++i) {
257
1.08M
    if (cpu->pageX_table_size[i] == 0 ||
258
1.08M
      (cpu->inst_pageX_table[i] == NULL))
259
401k
      break;
260
261
688k
    if (cpu->pageX_prefix[i] == insn_prefix) {
262
45.2k
      index = binary_search(cpu->inst_pageX_table[i],
263
45.2k
          cpu->pageX_table_size[i], opcode);
264
45.2k
      insn->id = (index >= 0) ?
265
27.9k
        cpu->inst_pageX_table[i][index].insn :
266
45.2k
        M680X_INS_ILLGL;
267
45.2k
      return;
268
45.2k
    }
269
688k
  }
270
271
424k
  if (insn_prefix != 0)
272
0
    return;
273
274
424k
  insn->id = cpu->inst_page1_table[id].insn;
275
276
424k
  if (insn->id != M680X_INS_ILLGL)
277
373k
    return;
278
279
  // Check if opcode byte is present in an overlay table
280
72.5k
  for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) {
281
71.4k
    if (cpu->overlay_table_size[i] == 0 ||
282
71.4k
      (cpu->inst_overlay_table[i] == NULL))
283
22.4k
      break;
284
285
48.9k
    if ((index = binary_search(cpu->inst_overlay_table[i],
286
48.9k
            cpu->overlay_table_size[i],
287
48.9k
            opcode)) >= 0) {
288
28.1k
      insn->id = cpu->inst_overlay_table[i][index].insn;
289
28.1k
      return;
290
28.1k
    }
291
48.9k
  }
292
51.6k
}
293
294
static void add_insn_group(cs_detail *detail, m680x_group_type group)
295
451k
{
296
451k
  if (detail != NULL &&
297
451k
    (group != M680X_GRP_INVALID) && (group != M680X_GRP_ENDING))
298
103k
    detail->groups[detail->groups_count++] = (uint8_t)group;
299
451k
}
300
301
static bool exists_reg_list(uint16_t *regs, uint8_t count, m680x_reg reg)
302
1.24M
{
303
1.24M
  uint8_t i;
304
305
2.06M
  for (i = 0; i < count; ++i) {
306
863k
    if (regs[i] == (uint16_t)reg)
307
36.4k
      return true;
308
863k
  }
309
310
1.20M
  return false;
311
1.24M
}
312
313
static void add_reg_to_rw_list(MCInst *MI, m680x_reg reg, e_access access)
314
821k
{
315
821k
  cs_detail *detail = MI->flat_insn->detail;
316
317
821k
  if (detail == NULL || (reg == M680X_REG_INVALID))
318
0
    return;
319
320
821k
  switch (access) {
321
420k
  case MODIFY:
322
420k
    if (!exists_reg_list(detail->regs_read,
323
420k
        detail->regs_read_count, reg))
324
412k
      detail->regs_read[detail->regs_read_count++] =
325
412k
        (uint16_t)reg;
326
327
  // intentionally fall through
328
329
535k
  case WRITE:
330
535k
    if (!exists_reg_list(detail->regs_write,
331
535k
        detail->regs_write_count, reg))
332
525k
      detail->regs_write[detail->regs_write_count++] =
333
525k
        (uint16_t)reg;
334
335
535k
    break;
336
337
285k
  case READ:
338
285k
    if (!exists_reg_list(detail->regs_read,
339
285k
        detail->regs_read_count, reg))
340
266k
      detail->regs_read[detail->regs_read_count++] =
341
266k
        (uint16_t)reg;
342
343
285k
    break;
344
345
0
  case UNCHANGED:
346
0
  default:
347
0
    break;
348
821k
  }
349
821k
}
350
351
static void update_am_reg_list(MCInst *MI, m680x_info *info, cs_m680x_op *op,
352
  e_access access)
353
580k
{
354
580k
  if (MI->flat_insn->detail == NULL)
355
0
    return;
356
357
580k
  switch (op->type) {
358
256k
  case M680X_OP_REGISTER:
359
256k
    add_reg_to_rw_list(MI, op->reg, access);
360
256k
    break;
361
362
113k
  case M680X_OP_INDEXED:
363
113k
    add_reg_to_rw_list(MI, op->idx.base_reg, READ);
364
365
113k
    if (op->idx.base_reg == M680X_REG_X &&
366
113k
      info->cpu->reg_byte_size[M680X_REG_H])
367
15.8k
      add_reg_to_rw_list(MI, M680X_REG_H, READ);
368
369
370
113k
    if (op->idx.offset_reg != M680X_REG_INVALID)
371
11.3k
      add_reg_to_rw_list(MI, op->idx.offset_reg, READ);
372
373
113k
    if (op->idx.inc_dec) {
374
25.8k
      add_reg_to_rw_list(MI, op->idx.base_reg, WRITE);
375
376
25.8k
      if (op->idx.base_reg == M680X_REG_X &&
377
25.8k
        info->cpu->reg_byte_size[M680X_REG_H])
378
3.85k
        add_reg_to_rw_list(MI, M680X_REG_H, WRITE);
379
25.8k
    }
380
381
113k
    break;
382
383
211k
  default:
384
211k
    break;
385
580k
  }
386
580k
}
387
388
static const e_access g_access_mode_to_access[4][15] = {
389
  {
390
    UNCHANGED, READ, WRITE, READ,  READ, READ,   WRITE, MODIFY,
391
    MODIFY, MODIFY, MODIFY, MODIFY, WRITE, READ, MODIFY,
392
  },
393
  {
394
    UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ,  READ,
395
    WRITE, MODIFY, WRITE, MODIFY, MODIFY, READ, UNCHANGED,
396
  },
397
  {
398
    UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ,  READ,
399
    WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED,
400
  },
401
  {
402
    UNCHANGED, READ, WRITE, WRITE, MODIFY, MODIFY, READ, READ,
403
    WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED,
404
  },
405
};
406
407
static e_access get_access(int operator_index, e_access_mode access_mode)
408
1.22M
{
409
1.22M
  int idx = (operator_index > 3) ? 3 : operator_index;
410
411
1.22M
  return g_access_mode_to_access[idx][access_mode];
412
1.22M
}
413
414
static void build_regs_read_write_counts(MCInst *MI, m680x_info *info,
415
  e_access_mode access_mode)
416
410k
{
417
410k
  cs_m680x *m680x = &info->m680x;
418
410k
  int i;
419
420
410k
  if (MI->flat_insn->detail == NULL || (!m680x->op_count))
421
66.6k
    return;
422
423
924k
  for (i = 0; i < m680x->op_count; ++i) {
424
425
580k
    e_access access = get_access(i, access_mode);
426
580k
    update_am_reg_list(MI, info, &m680x->operands[i], access);
427
580k
  }
428
343k
}
429
430
static void add_operators_access(MCInst *MI, m680x_info *info,
431
  e_access_mode access_mode)
432
410k
{
433
410k
  cs_m680x *m680x = &info->m680x;
434
410k
  int offset = 0;
435
410k
  int i;
436
437
410k
  if (MI->flat_insn->detail == NULL || (!m680x->op_count) ||
438
410k
    (access_mode == uuuu))
439
106k
    return;
440
441
843k
  for (i = 0; i < m680x->op_count; ++i) {
442
539k
    e_access access;
443
444
    // Ugly fix: MULD has a register operand, an immediate operand
445
    // AND an implicitly changed register W
446
539k
    if (info->insn == M680X_INS_MULD && (i == 1))
447
481
      offset = 1;
448
449
539k
    access = get_access(i + offset, access_mode);
450
539k
    m680x->operands[i].access = access;
451
539k
  }
452
303k
}
453
454
typedef struct insn_to_changed_regs {
455
  m680x_insn insn;
456
  e_access_mode access_mode;
457
  m680x_reg regs[10];
458
} insn_to_changed_regs;
459
460
static void set_changed_regs_read_write_counts(MCInst *MI, m680x_info *info)
461
37.8k
{
462
  //TABLE
463
2.08M
#define EOL M680X_REG_INVALID
464
37.8k
  static const insn_to_changed_regs changed_regs[] = {
465
37.8k
    { M680X_INS_BSR, mmmm, { M680X_REG_S, EOL } },
466
37.8k
    { M680X_INS_CALL, mmmm, { M680X_REG_S, EOL } },
467
37.8k
    {
468
37.8k
      M680X_INS_CWAI, mrrr, {
469
37.8k
        M680X_REG_S, M680X_REG_PC, M680X_REG_U,
470
37.8k
        M680X_REG_Y, M680X_REG_X, M680X_REG_DP,
471
37.8k
        M680X_REG_D, M680X_REG_CC, EOL
472
37.8k
      },
473
37.8k
    },
474
37.8k
    { M680X_INS_DAA, mrrr, { M680X_REG_A, EOL } },
475
37.8k
    {
476
37.8k
      M680X_INS_DIV, mmrr, {
477
37.8k
        M680X_REG_A, M680X_REG_H, M680X_REG_X, EOL
478
37.8k
      }
479
37.8k
    },
480
37.8k
    {
481
37.8k
      M680X_INS_EDIV, mmrr, {
482
37.8k
        M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL
483
37.8k
      }
484
37.8k
    },
485
37.8k
    {
486
37.8k
      M680X_INS_EDIVS, mmrr, {
487
37.8k
        M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL
488
37.8k
      }
489
37.8k
    },
490
37.8k
    { M680X_INS_EMACS, mrrr, { M680X_REG_X, M680X_REG_Y, EOL } },
491
37.8k
    { M680X_INS_EMAXM, rrrr, { M680X_REG_D, EOL } },
492
37.8k
    { M680X_INS_EMINM, rrrr, { M680X_REG_D, EOL } },
493
37.8k
    { M680X_INS_EMUL, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } },
494
37.8k
    { M680X_INS_EMULS, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } },
495
37.8k
    { M680X_INS_ETBL, wmmm, { M680X_REG_A, M680X_REG_B, EOL } },
496
37.8k
    { M680X_INS_FDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } },
497
37.8k
    { M680X_INS_IDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } },
498
37.8k
    { M680X_INS_IDIVS, mmmm, { M680X_REG_D, M680X_REG_X, EOL } },
499
37.8k
    { M680X_INS_JSR, mmmm, { M680X_REG_S, EOL } },
500
37.8k
    { M680X_INS_LBSR, mmmm, { M680X_REG_S, EOL } },
501
37.8k
    { M680X_INS_MAXM, rrrr, { M680X_REG_A, EOL } },
502
37.8k
    { M680X_INS_MINM, rrrr, { M680X_REG_A, EOL } },
503
37.8k
    {
504
37.8k
      M680X_INS_MEM, mmrr, {
505
37.8k
        M680X_REG_X, M680X_REG_Y, M680X_REG_A, EOL
506
37.8k
      }
507
37.8k
    },
508
37.8k
    { M680X_INS_MUL, mmmm, { M680X_REG_A, M680X_REG_B, EOL } },
509
37.8k
    { M680X_INS_MULD, mwrr, { M680X_REG_D, M680X_REG_W, EOL } },
510
37.8k
    { M680X_INS_PSHA, rmmm, { M680X_REG_A, M680X_REG_S, EOL } },
511
37.8k
    { M680X_INS_PSHB, rmmm, { M680X_REG_B, M680X_REG_S, EOL } },
512
37.8k
    { M680X_INS_PSHC, rmmm, { M680X_REG_CC, M680X_REG_S, EOL } },
513
37.8k
    { M680X_INS_PSHD, rmmm, { M680X_REG_D, M680X_REG_S, EOL } },
514
37.8k
    { M680X_INS_PSHH, rmmm, { M680X_REG_H, M680X_REG_S, EOL } },
515
37.8k
    { M680X_INS_PSHX, rmmm, { M680X_REG_X, M680X_REG_S, EOL } },
516
37.8k
    { M680X_INS_PSHY, rmmm, { M680X_REG_Y, M680X_REG_S, EOL } },
517
37.8k
    { M680X_INS_PULA, wmmm, { M680X_REG_A, M680X_REG_S, EOL } },
518
37.8k
    { M680X_INS_PULB, wmmm, { M680X_REG_B, M680X_REG_S, EOL } },
519
37.8k
    { M680X_INS_PULC, wmmm, { M680X_REG_CC, M680X_REG_S, EOL } },
520
37.8k
    { M680X_INS_PULD, wmmm, { M680X_REG_D, M680X_REG_S, EOL } },
521
37.8k
    { M680X_INS_PULH, wmmm, { M680X_REG_H, M680X_REG_S, EOL } },
522
37.8k
    { M680X_INS_PULX, wmmm, { M680X_REG_X, M680X_REG_S, EOL } },
523
37.8k
    { M680X_INS_PULY, wmmm, { M680X_REG_Y, M680X_REG_S, EOL } },
524
37.8k
    {
525
37.8k
      M680X_INS_REV, mmrr, {
526
37.8k
        M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL
527
37.8k
      }
528
37.8k
    },
529
37.8k
    {
530
37.8k
      M680X_INS_REVW, mmmm, {
531
37.8k
        M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL
532
37.8k
      }
533
37.8k
    },
534
37.8k
    { M680X_INS_RTC, mwww, { M680X_REG_S, M680X_REG_PC, EOL } },
535
37.8k
    {
536
37.8k
      M680X_INS_RTI, mwww, {
537
37.8k
        M680X_REG_S, M680X_REG_CC, M680X_REG_B,
538
37.8k
        M680X_REG_A, M680X_REG_DP, M680X_REG_X,
539
37.8k
        M680X_REG_Y, M680X_REG_U, M680X_REG_PC,
540
37.8k
        EOL
541
37.8k
      },
542
37.8k
    },
543
37.8k
    { M680X_INS_RTS, mwww, { M680X_REG_S, M680X_REG_PC, EOL } },
544
37.8k
    { M680X_INS_SEX, wrrr, { M680X_REG_A, M680X_REG_B, EOL } },
545
37.8k
    { M680X_INS_SEXW, rwww, { M680X_REG_W, M680X_REG_D, EOL } },
546
37.8k
    {
547
37.8k
      M680X_INS_SWI, mmrr, {
548
37.8k
        M680X_REG_S, M680X_REG_PC, M680X_REG_U,
549
37.8k
        M680X_REG_Y, M680X_REG_X, M680X_REG_DP,
550
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_CC,
551
37.8k
        EOL
552
37.8k
      }
553
37.8k
    },
554
37.8k
    {
555
37.8k
      M680X_INS_SWI2, mmrr, {
556
37.8k
        M680X_REG_S, M680X_REG_PC, M680X_REG_U,
557
37.8k
        M680X_REG_Y, M680X_REG_X, M680X_REG_DP,
558
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_CC,
559
37.8k
        EOL
560
37.8k
      },
561
37.8k
    },
562
37.8k
    {
563
37.8k
      M680X_INS_SWI3, mmrr, {
564
37.8k
        M680X_REG_S, M680X_REG_PC, M680X_REG_U,
565
37.8k
        M680X_REG_Y, M680X_REG_X, M680X_REG_DP,
566
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_CC,
567
37.8k
        EOL
568
37.8k
      },
569
37.8k
    },
570
37.8k
    { M680X_INS_TBL, wrrr, { M680X_REG_A, M680X_REG_B, EOL } },
571
37.8k
    {
572
37.8k
      M680X_INS_WAI, mrrr, {
573
37.8k
        M680X_REG_S, M680X_REG_PC, M680X_REG_X,
574
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_CC,
575
37.8k
        EOL
576
37.8k
      }
577
37.8k
    },
578
37.8k
    {
579
37.8k
      M680X_INS_WAV, rmmm, {
580
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_X,
581
37.8k
        M680X_REG_Y, EOL
582
37.8k
      }
583
37.8k
    },
584
37.8k
    {
585
37.8k
      M680X_INS_WAVR, rmmm, {
586
37.8k
        M680X_REG_A, M680X_REG_B, M680X_REG_X,
587
37.8k
        M680X_REG_Y, EOL
588
37.8k
      }
589
37.8k
    },
590
37.8k
  };
591
592
37.8k
  int i, j;
593
594
37.8k
  if (MI->flat_insn->detail == NULL)
595
0
    return;
596
597
1.96M
  for (i = 0; i < ARR_SIZE(changed_regs); ++i) {
598
1.92M
    if (info->insn == changed_regs[i].insn) {
599
37.8k
      e_access_mode access_mode = changed_regs[i].access_mode;
600
601
152k
      for (j = 0; changed_regs[i].regs[j] != EOL; ++j) {
602
114k
        e_access access;
603
604
114k
        m680x_reg reg = changed_regs[i].regs[j];
605
606
114k
        if (!info->cpu->reg_byte_size[reg]) {
607
9.29k
          if (info->insn != M680X_INS_MUL)
608
8.69k
            continue;
609
610
          // Hack for M68HC05: MUL uses reg. A,X
611
601
          reg = M680X_REG_X;
612
601
        }
613
614
106k
        access = get_access(j, access_mode);
615
106k
        add_reg_to_rw_list(MI, reg, access);
616
106k
      }
617
37.8k
    }
618
1.92M
  }
619
620
37.8k
#undef EOL
621
37.8k
}
622
623
typedef struct insn_desc {
624
  uint32_t opcode;
625
  m680x_insn insn;
626
  insn_hdlr_id hid[2];
627
  uint16_t insn_size;
628
} insn_desc;
629
630
// If successfull return the additional byte size needed for M6809
631
// indexed addressing mode (including the indexed addressing post_byte).
632
// On error return -1.
633
static int get_indexed09_post_byte_size(const m680x_info *info,
634
          uint16_t address)
635
53.4k
{
636
53.4k
  uint8_t ir = 0;
637
53.4k
  uint8_t post_byte;
638
639
  // Read the indexed addressing post byte.
640
53.4k
  if (!read_byte(info, &post_byte, address))
641
196
    return -1;
642
643
  // Depending on the indexed addressing mode more bytes have to be read.
644
53.2k
  switch (post_byte & 0x9F) {
645
1.46k
  case 0x87:
646
2.81k
  case 0x8A:
647
4.89k
  case 0x8E:
648
6.12k
  case 0x8F:
649
6.77k
  case 0x90:
650
7.58k
  case 0x92:
651
8.11k
  case 0x97:
652
8.58k
  case 0x9A:
653
9.31k
  case 0x9E:
654
9.31k
    return -1; // illegal indexed post bytes
655
656
1.26k
  case 0x88: // n8,R
657
2.40k
  case 0x8C: // n8,PCR
658
2.94k
  case 0x98: // [n8,R]
659
3.93k
  case 0x9C: // [n8,PCR]
660
3.93k
    if (!read_byte(info, &ir, address + 1))
661
25
      return -1;
662
3.90k
    return 2;
663
664
1.68k
  case 0x89: // n16,R
665
2.59k
  case 0x8D: // n16,PCR
666
3.52k
  case 0x99: // [n16,R]
667
4.53k
  case 0x9D: // [n16,PCR]
668
4.53k
    if (!read_byte(info, &ir, address + 2))
669
52
      return -1;
670
4.48k
    return 3;
671
672
2.44k
  case 0x9F: // [n]
673
2.44k
    if ((post_byte & 0x60) != 0 ||
674
2.44k
      !read_byte(info, &ir, address + 2))
675
1.55k
      return -1;
676
891
    return  3;
677
53.2k
  }
678
679
  // Any other indexed post byte is valid and
680
  // no additional bytes have to be read.
681
33.0k
  return 1;
682
53.2k
}
683
684
// If successfull return the additional byte size needed for CPU12
685
// indexed addressing mode (including the indexed addressing post_byte).
686
// On error return -1.
687
static int get_indexed12_post_byte_size(const m680x_info *info,
688
          uint16_t address, bool is_subset)
689
43.3k
{
690
43.3k
  uint8_t ir;
691
43.3k
  uint8_t post_byte;
692
693
  // Read the indexed addressing post byte.
694
43.3k
  if (!read_byte(info, &post_byte, address))
695
171
    return -1;
696
697
  // Depending on the indexed addressing mode more bytes have to be read.
698
43.1k
  if (!(post_byte & 0x20)) // n5,R
699
12.7k
    return 1;
700
701
30.3k
  switch (post_byte & 0xe7) {
702
2.18k
  case 0xe0:
703
5.70k
  case 0xe1: // n9,R
704
5.70k
    if (is_subset)
705
430
      return -1;
706
707
5.27k
    if (!read_byte(info, &ir, address))
708
0
      return -1;
709
5.27k
    return 2;
710
711
3.63k
  case 0xe2: // n16,R
712
6.92k
  case 0xe3: // [n16,R]
713
6.92k
    if (is_subset)
714
605
      return -1;
715
716
6.32k
    if (!read_byte(info, &ir, address + 1))
717
31
      return -1;
718
6.29k
    return 3;
719
720
1.21k
  case 0xe4: // A,R
721
2.21k
  case 0xe5: // B,R
722
3.28k
  case 0xe6: // D,R
723
4.67k
  case 0xe7: // [D,R]
724
17.7k
  default: // n,-r n,+r n,r- n,r+
725
17.7k
    break;
726
30.3k
  }
727
728
17.7k
  return 1;
729
30.3k
}
730
731
// Check for M6809/HD6309 TFR/EXG instruction for valid register
732
static bool is_tfr09_reg_valid(const m680x_info *info, uint8_t reg_nibble)
733
6.67k
{
734
6.67k
  if (info->cpu->tfr_reg_valid != NULL)
735
4.06k
    return info->cpu->tfr_reg_valid[reg_nibble];
736
737
2.60k
  return true; // e.g. for the M6309 all registers are valid
738
6.67k
}
739
740
// Check for CPU12 TFR/EXG instruction for valid register
741
static bool is_exg_tfr12_post_byte_valid(const m680x_info *info,
742
  uint8_t post_byte)
743
2.21k
{
744
2.21k
  return !(post_byte & 0x08);
745
2.21k
}
746
747
static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble)
748
3.58k
{
749
  // HD6809 TFM instruction: Only register X,Y,U,S,D is allowed
750
3.58k
  return reg_nibble <= 4;
751
3.58k
}
752
753
// If successfull return the additional byte size needed for CPU12
754
// loop instructions DBEQ/DBNE/IBEQ/IBNE/TBEQ/TBNE (including the post byte).
755
// On error return -1.
756
static int get_loop_post_byte_size(const m680x_info *info, uint16_t address)
757
4.04k
{
758
4.04k
  uint8_t post_byte;
759
4.04k
  uint8_t rr;
760
761
4.04k
  if (!read_byte(info, &post_byte, address))
762
19
    return -1;
763
764
  // According to documentation bit 3 is don't care and not checked here.
765
4.02k
  if ((post_byte >= 0xc0) ||
766
4.02k
    ((post_byte & 0x07) == 2) || ((post_byte & 0x07) == 3))
767
1.92k
    return -1;
768
769
2.10k
  if (!read_byte(info, &rr, address + 1))
770
8
    return -1;
771
772
2.09k
  return 2;
773
2.10k
}
774
775
// If successfull return the additional byte size needed for HD6309
776
// bit move instructions BAND/BEOR/BIAND/BIEOR/BIOR/BOR/LDBT/STBT
777
// (including the post byte).
778
// On error return -1.
779
static int get_bitmv_post_byte_size(const m680x_info *info, uint16_t address)
780
1.40k
{
781
1.40k
  uint8_t post_byte;
782
1.40k
  uint8_t rr;
783
784
1.40k
  if (!read_byte(info, &post_byte, address))
785
4
    return -1;
786
787
1.40k
  if ((post_byte & 0xc0) == 0xc0)
788
624
    return -1; // Invalid register specified
789
781
  else {
790
781
    if (!read_byte(info, &rr, address + 1))
791
4
      return -1;
792
781
  }
793
794
777
  return 2;
795
1.40k
}
796
797
static bool is_sufficient_code_size(const m680x_info *info, uint16_t address,
798
  insn_desc *insn_description)
799
429k
{
800
429k
  int i;
801
429k
  bool retval = true;
802
429k
  uint16_t size = 0;
803
429k
  int sz;
804
805
1.25M
  for (i = 0; i < 2; i++) {
806
839k
    uint8_t ir = 0;
807
839k
    bool is_subset = false;
808
809
839k
    switch (insn_description->hid[i]) {
810
811
1.47k
    case imm32_hid:
812
1.47k
      if ((retval = read_byte(info, &ir, address + size + 3)))
813
1.44k
        size += 4;
814
1.47k
      break;
815
816
55.2k
    case ext_hid:
817
61.1k
    case imm16_hid:
818
63.6k
    case rel16_hid:
819
65.9k
    case imm8rel_hid:
820
71.1k
    case opidxdr_hid:
821
73.5k
    case idxX16_hid:
822
74.1k
    case idxS16_hid:
823
74.1k
      if ((retval = read_byte(info, &ir, address + size + 1)))
824
73.4k
        size += 2;
825
74.1k
      break;
826
827
27.2k
    case rel8_hid:
828
84.5k
    case dir_hid:
829
90.3k
    case rbits_hid:
830
114k
    case imm8_hid:
831
124k
    case idxX_hid:
832
126k
    case idxXp_hid:
833
128k
    case idxY_hid:
834
129k
    case idxS_hid:
835
130k
    case index_hid:
836
130k
      if ((retval = read_byte(info, &ir, address + size)))
837
129k
        size++;
838
130k
      break;
839
840
0
    case illgl_hid:
841
511k
    case inh_hid:
842
520k
    case idxX0_hid:
843
521k
    case idxX0p_hid:
844
523k
    case opidx_hid:
845
523k
      retval = true;
846
523k
      break;
847
848
53.4k
    case idx09_hid:
849
53.4k
      sz = get_indexed09_post_byte_size(info, address + size);
850
53.4k
      if (sz >= 0)
851
42.2k
        size += sz;
852
11.1k
      else
853
11.1k
        retval = false;
854
53.4k
      break;
855
856
1.32k
    case idx12s_hid:
857
1.32k
      is_subset = true;
858
859
    // intentionally fall through
860
861
32.1k
    case idx12_hid:
862
32.1k
      sz = get_indexed12_post_byte_size(info,
863
32.1k
          address + size, is_subset);
864
32.1k
      if (sz >= 0)
865
30.9k
        size += sz;
866
1.20k
      else
867
1.20k
        retval = false;
868
32.1k
      break;
869
870
2.03k
    case exti12x_hid:
871
5.84k
    case imm16i12x_hid:
872
5.84k
      sz = get_indexed12_post_byte_size(info,
873
5.84k
          address + size, false);
874
5.84k
      if (sz >= 0) {
875
5.82k
        size += sz;
876
5.82k
        if ((retval = read_byte(info, &ir,
877
5.82k
            address + size + 1)))
878
5.79k
          size += 2;
879
5.82k
      } else
880
23
        retval = false;
881
5.84k
      break;
882
883
5.36k
    case imm8i12x_hid:
884
5.36k
      sz = get_indexed12_post_byte_size(info,
885
5.36k
          address + size, false);
886
5.36k
      if (sz >= 0) {
887
5.35k
        size += sz;
888
5.35k
        if ((retval = read_byte(info, &ir,
889
5.35k
            address + size)))
890
5.31k
          size++;
891
5.35k
      } else
892
9
        retval = false;
893
5.36k
      break;
894
895
2.45k
    case tfm_hid:
896
2.45k
      if ((retval = read_byte(info, &ir, address + size))) {
897
2.44k
        size++;
898
2.44k
        retval = is_tfm_reg_valid(info, (ir >> 4) & 0x0F) &&
899
2.44k
          is_tfm_reg_valid(info, ir & 0x0F);
900
2.44k
      }
901
2.45k
      break;
902
903
3.61k
    case rr09_hid:
904
3.61k
      if ((retval = read_byte(info, &ir, address + size))) {
905
3.60k
        size++;
906
3.60k
        retval = is_tfr09_reg_valid(info, (ir >> 4) & 0x0F) &&
907
3.60k
          is_tfr09_reg_valid(info, ir & 0x0F);
908
3.60k
      }
909
3.61k
      break;
910
911
2.22k
    case rr12_hid:
912
2.22k
      if ((retval = read_byte(info, &ir, address + size))) {
913
2.21k
        size++;
914
2.21k
        retval = is_exg_tfr12_post_byte_valid(info, ir);
915
2.21k
      }
916
2.22k
      break;
917
918
1.40k
    case bitmv_hid:
919
1.40k
      sz = get_bitmv_post_byte_size(info, address + size);
920
1.40k
      if (sz >= 0)
921
777
        size += sz;
922
632
      else
923
632
        retval = false;
924
1.40k
      break;
925
926
4.04k
    case loop_hid:
927
4.04k
      sz = get_loop_post_byte_size(info, address + size);
928
4.04k
      if (sz >= 0)
929
2.09k
        size += sz;
930
1.95k
      else
931
1.95k
        retval = false;
932
4.04k
      break;
933
934
0
    default:
935
0
      CS_ASSERT(0 && "Unexpected instruction handler id");
936
0
      retval = false;
937
0
      break;
938
839k
    }
939
940
839k
    if (!retval)
941
19.0k
      return false;
942
839k
  }
943
944
410k
  insn_description->insn_size += size;
945
946
410k
  return retval;
947
429k
}
948
949
// Check for a valid M680X instruction AND for enough bytes in the code buffer
950
// Return an instruction description in insn_desc.
951
static bool decode_insn(const m680x_info *info, uint16_t address,
952
  insn_desc *insn_description)
953
470k
{
954
470k
  const inst_pageX *inst_table = NULL;
955
470k
  const cpu_tables *cpu = info->cpu;
956
470k
  size_t table_size = 0;
957
470k
  uint16_t base_address = address;
958
470k
  uint8_t ir; // instruction register
959
470k
  int i;
960
470k
  int index;
961
962
470k
  if (!read_byte(info, &ir, address++))
963
0
    return false;
964
965
470k
  insn_description->insn = M680X_INS_ILLGL;
966
470k
  insn_description->opcode = ir;
967
968
  // Check if a page prefix byte is present
969
1.11M
  for (i = 0; i < ARR_SIZE(cpu->pageX_table_size); ++i) {
970
1.08M
    if (cpu->pageX_table_size[i] == 0 ||
971
1.08M
      (cpu->inst_pageX_table[i] == NULL))
972
401k
      break;
973
974
688k
    if ((cpu->pageX_prefix[i] == ir)) {
975
      // Get pageX instruction and handler id.
976
      // Abort for illegal instr.
977
45.2k
      inst_table = cpu->inst_pageX_table[i];
978
45.2k
      table_size = cpu->pageX_table_size[i];
979
980
45.2k
      if (!read_byte(info, &ir, address++))
981
48
        return false;
982
983
45.2k
      insn_description->opcode =
984
45.2k
        (insn_description->opcode << 8) | ir;
985
986
45.2k
      if ((index = binary_search(inst_table, table_size,
987
45.2k
        ir)) < 0)
988
17.2k
        return false;
989
990
27.9k
      insn_description->hid[0] =
991
27.9k
        inst_table[index].handler_id1;
992
27.9k
      insn_description->hid[1] =
993
27.9k
        inst_table[index].handler_id2;
994
27.9k
      insn_description->insn = inst_table[index].insn;
995
27.9k
      break;
996
45.2k
    }
997
688k
  }
998
999
452k
  if (insn_description->insn == M680X_INS_ILLGL) {
1000
    // Get page1 insn description
1001
424k
    insn_description->insn = cpu->inst_page1_table[ir].insn;
1002
424k
    insn_description->hid[0] =
1003
424k
      cpu->inst_page1_table[ir].handler_id1;
1004
424k
    insn_description->hid[1] =
1005
424k
      cpu->inst_page1_table[ir].handler_id2;
1006
424k
  }
1007
1008
452k
  if (insn_description->insn == M680X_INS_ILLGL) {
1009
    // Check if opcode byte is present in an overlay table
1010
72.4k
    for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) {
1011
71.3k
      if (cpu->overlay_table_size[i] == 0 ||
1012
71.3k
        (cpu->inst_overlay_table[i] == NULL))
1013
22.4k
        break;
1014
1015
48.9k
      inst_table = cpu->inst_overlay_table[i];
1016
48.9k
      table_size = cpu->overlay_table_size[i];
1017
1018
48.9k
      if ((index = binary_search(inst_table, table_size,
1019
48.9k
              ir)) >= 0) {
1020
28.1k
        insn_description->hid[0] =
1021
28.1k
          inst_table[index].handler_id1;
1022
28.1k
        insn_description->hid[1] =
1023
28.1k
          inst_table[index].handler_id2;
1024
28.1k
        insn_description->insn = inst_table[index].insn;
1025
28.1k
        break;
1026
28.1k
      }
1027
48.9k
    }
1028
51.6k
  }
1029
1030
452k
  insn_description->insn_size = address - base_address;
1031
1032
452k
  return (insn_description->insn != M680X_INS_ILLGL) &&
1033
452k
    (insn_description->insn != M680X_INS_INVLD) &&
1034
452k
    is_sufficient_code_size(info, address, insn_description);
1035
470k
}
1036
1037
static void illegal_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1038
59.8k
{
1039
59.8k
  cs_m680x_op *op0 = &info->m680x.operands[info->m680x.op_count++];
1040
59.8k
  uint8_t temp8 = 0;
1041
1042
59.8k
  info->insn = M680X_INS_ILLGL;
1043
59.8k
  read_byte(info, &temp8, (*address)++);
1044
59.8k
  op0->imm = (int32_t)temp8 & 0xff;
1045
59.8k
  op0->type = M680X_OP_IMMEDIATE;
1046
59.8k
  op0->size = 1;
1047
59.8k
}
1048
1049
static void inherent_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1050
511k
{
1051
  // There is nothing to do here :-)
1052
511k
}
1053
1054
static void add_reg_operand(m680x_info *info, m680x_reg reg)
1055
256k
{
1056
256k
  cs_m680x *m680x = &info->m680x;
1057
256k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1058
1059
256k
  op->type = M680X_OP_REGISTER;
1060
256k
  op->reg = reg;
1061
256k
  op->size = info->cpu->reg_byte_size[reg];
1062
256k
}
1063
1064
static void set_operand_size(m680x_info *info, cs_m680x_op *op,
1065
  uint8_t default_size)
1066
276k
{
1067
276k
  cs_m680x *m680x = &info->m680x;
1068
1069
276k
  if (info->insn == M680X_INS_JMP || info->insn == M680X_INS_JSR)
1070
13.7k
    op->size = 0;
1071
262k
  else if (info->insn == M680X_INS_DIVD ||
1072
262k
    ((info->insn == M680X_INS_AIS || info->insn == M680X_INS_AIX) &&
1073
259k
      op->type != M680X_OP_REGISTER))
1074
4.57k
    op->size = 1;
1075
257k
  else if (info->insn == M680X_INS_DIVQ ||
1076
257k
    info->insn == M680X_INS_MOVW)
1077
11.3k
    op->size = 2;
1078
246k
  else if (info->insn == M680X_INS_EMACS)
1079
295
    op->size = 4;
1080
246k
  else if ((m680x->op_count > 0) &&
1081
246k
    (m680x->operands[0].type == M680X_OP_REGISTER))
1082
150k
    op->size = m680x->operands[0].size;
1083
95.7k
  else
1084
95.7k
    op->size = default_size;
1085
276k
}
1086
1087
static const m680x_reg reg_s_reg_ids[] = {
1088
  M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP,
1089
  M680X_REG_X,  M680X_REG_Y, M680X_REG_U, M680X_REG_PC,
1090
};
1091
1092
static const m680x_reg reg_u_reg_ids[] = {
1093
  M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP,
1094
  M680X_REG_X,  M680X_REG_Y, M680X_REG_S, M680X_REG_PC,
1095
};
1096
1097
static void reg_bits_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1098
5.79k
{
1099
5.79k
  cs_m680x_op *op0 = &info->m680x.operands[0];
1100
5.79k
  uint8_t reg_bits = 0;
1101
5.79k
  uint16_t bit_index;
1102
5.79k
  const m680x_reg *reg_to_reg_ids = NULL;
1103
1104
5.79k
  read_byte(info, &reg_bits, (*address)++);
1105
1106
5.79k
  switch (op0->reg) {
1107
3.34k
  case M680X_REG_U:
1108
3.34k
    reg_to_reg_ids = &reg_u_reg_ids[0];
1109
3.34k
    break;
1110
1111
2.45k
  case M680X_REG_S:
1112
2.45k
    reg_to_reg_ids = &reg_s_reg_ids[0];
1113
2.45k
    break;
1114
1115
0
  default:
1116
0
    CS_ASSERT(0 && "Unexpected operand0 register");
1117
0
    break;
1118
5.79k
  }
1119
1120
5.79k
  if ((info->insn == M680X_INS_PULU ||
1121
5.79k
      (info->insn == M680X_INS_PULS)) &&
1122
5.79k
    ((reg_bits & 0x80) != 0))
1123
    // PULS xxx,PC or PULU xxx,PC which is like return from
1124
    // subroutine (RTS)
1125
579
    add_insn_group(MI->flat_insn->detail, M680X_GRP_RET);
1126
1127
52.1k
  for (bit_index = 0; bit_index < 8; ++bit_index) {
1128
46.3k
    if (reg_bits & (1 << bit_index))
1129
24.4k
      add_reg_operand(info, reg_to_reg_ids[bit_index]);
1130
46.3k
  }
1131
5.79k
}
1132
1133
static const m680x_reg g_tfr_exg_reg_ids[] = {
1134
  /* 16-bit registers */
1135
  M680X_REG_D, M680X_REG_X,  M680X_REG_Y,  M680X_REG_U,
1136
  M680X_REG_S, M680X_REG_PC, M680X_REG_W,  M680X_REG_V,
1137
  /* 8-bit registers */
1138
  M680X_REG_A, M680X_REG_B,  M680X_REG_CC, M680X_REG_DP,
1139
  M680X_REG_0, M680X_REG_0,  M680X_REG_E,  M680X_REG_F,
1140
};
1141
1142
static void reg_reg09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1143
2.34k
{
1144
2.34k
  uint8_t regs = 0;
1145
1146
2.34k
  read_byte(info, &regs, (*address)++);
1147
1148
2.34k
  add_reg_operand(info, g_tfr_exg_reg_ids[regs >> 4]);
1149
2.34k
  add_reg_operand(info, g_tfr_exg_reg_ids[regs & 0x0f]);
1150
1151
2.34k
  if ((regs & 0x0f) == 0x05) {
1152
    // EXG xxx,PC or TFR xxx,PC which is like a JMP
1153
1.46k
    add_insn_group(MI->flat_insn->detail, M680X_GRP_JUMP);
1154
1.46k
  }
1155
2.34k
}
1156
1157
1158
static void reg_reg12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1159
2.13k
{
1160
2.13k
  static const m680x_reg g_tfr_exg12_reg0_ids[] = {
1161
2.13k
    M680X_REG_A, M680X_REG_B,  M680X_REG_CC,  M680X_REG_TMP3,
1162
2.13k
    M680X_REG_D, M680X_REG_X, M680X_REG_Y,  M680X_REG_S,
1163
2.13k
  };
1164
2.13k
  static const m680x_reg g_tfr_exg12_reg1_ids[] = {
1165
2.13k
    M680X_REG_A, M680X_REG_B,  M680X_REG_CC,  M680X_REG_TMP2,
1166
2.13k
    M680X_REG_D, M680X_REG_X, M680X_REG_Y,  M680X_REG_S,
1167
2.13k
  };
1168
2.13k
  uint8_t regs = 0;
1169
1170
2.13k
  read_byte(info, &regs, (*address)++);
1171
1172
  // The opcode of this instruction depends on
1173
  // the msb of its post byte.
1174
2.13k
  if (regs & 0x80)
1175
1.53k
    info->insn = M680X_INS_EXG;
1176
607
  else
1177
607
    info->insn = M680X_INS_TFR;
1178
1179
2.13k
  add_reg_operand(info, g_tfr_exg12_reg0_ids[(regs >> 4) & 0x07]);
1180
2.13k
  add_reg_operand(info, g_tfr_exg12_reg1_ids[regs & 0x07]);
1181
2.13k
}
1182
1183
static void add_rel_operand(m680x_info *info, int16_t offset, uint16_t address)
1184
36.9k
{
1185
36.9k
  cs_m680x *m680x = &info->m680x;
1186
36.9k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1187
1188
36.9k
  op->type = M680X_OP_RELATIVE;
1189
36.9k
  op->size = 0;
1190
36.9k
  op->rel.offset = offset;
1191
36.9k
  op->rel.address = address;
1192
36.9k
}
1193
1194
static void relative8_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1195
34.4k
{
1196
34.4k
  int16_t offset = 0;
1197
1198
34.4k
  read_byte_sign_extended(info, &offset, (*address)++);
1199
34.4k
  add_rel_operand(info, offset, *address + offset);
1200
34.4k
  add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL);
1201
1202
34.4k
  if ((info->insn != M680X_INS_BRA) &&
1203
34.4k
    (info->insn != M680X_INS_BSR) &&
1204
34.4k
    (info->insn != M680X_INS_BRN))
1205
29.1k
    add_reg_to_rw_list(MI, M680X_REG_CC, READ);
1206
34.4k
}
1207
1208
static void relative16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1209
2.49k
{
1210
2.49k
  uint16_t offset = 0;
1211
1212
2.49k
  read_word(info, &offset, *address);
1213
2.49k
  *address += 2;
1214
2.49k
  add_rel_operand(info, (int16_t)offset, *address + offset);
1215
2.49k
  add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL);
1216
1217
2.49k
  if ((info->insn != M680X_INS_LBRA) &&
1218
2.49k
    (info->insn != M680X_INS_LBSR) &&
1219
2.49k
    (info->insn != M680X_INS_LBRN))
1220
904
    add_reg_to_rw_list(MI, M680X_REG_CC, READ);
1221
2.49k
}
1222
1223
static const m680x_reg g_rr5_to_reg_ids[] = {
1224
  M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_S,
1225
};
1226
1227
static void add_indexed_operand(m680x_info *info, m680x_reg base_reg,
1228
  bool post_inc_dec, uint8_t inc_dec, uint8_t offset_bits,
1229
  uint16_t offset, bool no_comma)
1230
29.8k
{
1231
29.8k
  cs_m680x *m680x = &info->m680x;
1232
29.8k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1233
1234
29.8k
  op->type = M680X_OP_INDEXED;
1235
29.8k
  set_operand_size(info, op, 1);
1236
29.8k
  op->idx.base_reg = base_reg;
1237
29.8k
  op->idx.offset_reg = M680X_REG_INVALID;
1238
29.8k
  op->idx.inc_dec = inc_dec;
1239
1240
29.8k
  if (inc_dec && post_inc_dec)
1241
5.41k
    op->idx.flags |= M680X_IDX_POST_INC_DEC;
1242
1243
29.8k
  if (offset_bits != M680X_OFFSET_NONE) {
1244
18.0k
    op->idx.offset = offset;
1245
18.0k
    op->idx.offset_addr = 0;
1246
18.0k
  }
1247
1248
29.8k
  op->idx.offset_bits = offset_bits;
1249
29.8k
  op->idx.flags |= (no_comma ? M680X_IDX_NO_COMMA : 0);
1250
29.8k
}
1251
1252
// M6800/1/2/3 indexed mode handler
1253
static void indexedX_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1254
9.44k
{
1255
9.44k
  uint8_t offset = 0;
1256
1257
9.44k
  read_byte(info, &offset, (*address)++);
1258
1259
9.44k
  add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_8,
1260
9.44k
    (uint16_t)offset, false);
1261
9.44k
}
1262
1263
static void indexedY_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1264
1.86k
{
1265
1.86k
  uint8_t offset = 0;
1266
1267
1.86k
  read_byte(info, &offset, (*address)++);
1268
1269
1.86k
  add_indexed_operand(info, M680X_REG_Y, false, 0, M680X_OFFSET_BITS_8,
1270
1.86k
    (uint16_t)offset, false);
1271
1.86k
}
1272
1273
// M6809/M6309 indexed mode handler
1274
static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1275
42.2k
{
1276
42.2k
  cs_m680x *m680x = &info->m680x;
1277
42.2k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1278
42.2k
  uint8_t post_byte = 0;
1279
42.2k
  uint16_t offset = 0;
1280
42.2k
  int16_t soffset = 0;
1281
1282
42.2k
  read_byte(info, &post_byte, (*address)++);
1283
1284
42.2k
  op->type = M680X_OP_INDEXED;
1285
42.2k
  set_operand_size(info, op, 1);
1286
42.2k
  op->idx.base_reg = g_rr5_to_reg_ids[(post_byte >> 5) & 0x03];
1287
42.2k
  op->idx.offset_reg = M680X_REG_INVALID;
1288
1289
42.2k
  if (!(post_byte & 0x80)) {
1290
    // n5,R
1291
17.5k
    if ((post_byte & 0x10) == 0x10)
1292
8.09k
      op->idx.offset = post_byte | 0xfff0;
1293
9.50k
    else
1294
9.50k
      op->idx.offset = post_byte & 0x0f;
1295
1296
17.5k
    op->idx.offset_addr = op->idx.offset + *address;
1297
17.5k
    op->idx.offset_bits = M680X_OFFSET_BITS_5;
1298
17.5k
  }
1299
24.6k
  else {
1300
24.6k
    if ((post_byte & 0x10) == 0x10)
1301
8.69k
      op->idx.flags |= M680X_IDX_INDIRECT;
1302
1303
    // indexed addressing
1304
24.6k
    switch (post_byte & 0x1f) {
1305
2.03k
    case 0x00: // ,R+
1306
2.03k
      op->idx.inc_dec = 1;
1307
2.03k
      op->idx.flags |= M680X_IDX_POST_INC_DEC;
1308
2.03k
      break;
1309
1310
983
    case 0x11: // [,R++]
1311
2.29k
    case 0x01: // ,R++
1312
2.29k
      op->idx.inc_dec = 2;
1313
2.29k
      op->idx.flags |= M680X_IDX_POST_INC_DEC;
1314
2.29k
      break;
1315
1316
1.37k
    case 0x02: // ,-R
1317
1.37k
      op->idx.inc_dec = -1;
1318
1.37k
      break;
1319
1320
896
    case 0x13: // [,--R]
1321
1.63k
    case 0x03: // ,--R
1322
1.63k
      op->idx.inc_dec = -2;
1323
1.63k
      break;
1324
1325
582
    case 0x14: // [,R]
1326
1.35k
    case 0x04: // ,R
1327
1.35k
      break;
1328
1329
681
    case 0x15: // [B,R]
1330
2.06k
    case 0x05: // B,R
1331
2.06k
      op->idx.offset_reg = M680X_REG_B;
1332
2.06k
      break;
1333
1334
602
    case 0x16: // [A,R]
1335
2.84k
    case 0x06: // A,R
1336
2.84k
      op->idx.offset_reg = M680X_REG_A;
1337
2.84k
      break;
1338
1339
980
    case 0x1c: // [n8,PCR]
1340
2.11k
    case 0x0c: // n8,PCR
1341
2.11k
      op->idx.base_reg = M680X_REG_PC;
1342
2.11k
      read_byte_sign_extended(info, &soffset, (*address)++);
1343
2.11k
      op->idx.offset_addr = offset + *address;
1344
2.11k
      op->idx.offset = soffset;
1345
2.11k
      op->idx.offset_bits = M680X_OFFSET_BITS_8;
1346
2.11k
      break;
1347
1348
536
    case 0x18: // [n8,R]
1349
1.79k
    case 0x08: // n8,R
1350
1.79k
      read_byte_sign_extended(info, &soffset, (*address)++);
1351
1.79k
      op->idx.offset = soffset;
1352
1.79k
      op->idx.offset_bits = M680X_OFFSET_BITS_8;
1353
1.79k
      break;
1354
1355
1.00k
    case 0x1d: // [n16,PCR]
1356
1.89k
    case 0x0d: // n16,PCR
1357
1.89k
      op->idx.base_reg = M680X_REG_PC;
1358
1.89k
      read_word(info, &offset, *address);
1359
1.89k
      *address += 2;
1360
1.89k
      op->idx.offset_addr = offset + *address;
1361
1.89k
      op->idx.offset = (int16_t)offset;
1362
1.89k
      op->idx.offset_bits = M680X_OFFSET_BITS_16;
1363
1.89k
      break;
1364
1365
923
    case 0x19: // [n16,R]
1366
2.58k
    case 0x09: // n16,R
1367
2.58k
      read_word(info, &offset, *address);
1368
2.58k
      *address += 2;
1369
2.58k
      op->idx.offset = (int16_t)offset;
1370
2.58k
      op->idx.offset_bits = M680X_OFFSET_BITS_16;
1371
2.58k
      break;
1372
1373
620
    case 0x1b: // [D,R]
1374
1.82k
    case 0x0b: // D,R
1375
1.82k
      op->idx.offset_reg = M680X_REG_D;
1376
1.82k
      break;
1377
1378
891
    case 0x1f: // [n16]
1379
891
      op->type = M680X_OP_EXTENDED;
1380
891
      op->ext.indirect = true;
1381
891
      read_word(info, &op->ext.address, *address);
1382
891
      *address += 2;
1383
891
      break;
1384
1385
0
    default:
1386
0
      op->idx.base_reg = M680X_REG_INVALID;
1387
0
      break;
1388
24.6k
    }
1389
24.6k
  }
1390
1391
42.2k
  if (((info->insn == M680X_INS_LEAU) ||
1392
42.2k
      (info->insn == M680X_INS_LEAS) ||
1393
42.2k
      (info->insn == M680X_INS_LEAX) ||
1394
42.2k
      (info->insn == M680X_INS_LEAY)) &&
1395
42.2k
    (m680x->operands[0].reg == M680X_REG_X ||
1396
6.26k
      (m680x->operands[0].reg == M680X_REG_Y)))
1397
    // Only LEAX and LEAY modify CC register
1398
3.26k
    add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY);
1399
42.2k
}
1400
1401
1402
static const m680x_reg g_idx12_to_reg_ids[4] = {
1403
  M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC,
1404
};
1405
1406
static const m680x_reg g_or12_to_reg_ids[3] = {
1407
  M680X_REG_A, M680X_REG_B, M680X_REG_D
1408
};
1409
1410
// CPU12 indexed mode handler
1411
static void indexed12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1412
42.0k
{
1413
42.0k
  cs_m680x *m680x = &info->m680x;
1414
42.0k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1415
42.0k
  uint8_t post_byte = 0;
1416
42.0k
  uint8_t offset8 = 0;
1417
1418
42.0k
  read_byte(info, &post_byte, (*address)++);
1419
1420
42.0k
  op->type = M680X_OP_INDEXED;
1421
42.0k
  set_operand_size(info, op, 1);
1422
42.0k
  op->idx.offset_reg = M680X_REG_INVALID;
1423
1424
42.0k
  if (!(post_byte & 0x20)) {
1425
    // n5,R      n5 is a 5-bit signed offset
1426
12.7k
    op->idx.base_reg = g_idx12_to_reg_ids[(post_byte >> 6) & 0x03];
1427
1428
12.7k
    if ((post_byte & 0x10) == 0x10)
1429
4.50k
      op->idx.offset = post_byte | 0xfff0;
1430
8.24k
    else
1431
8.24k
      op->idx.offset = post_byte & 0x0f;
1432
1433
12.7k
    op->idx.offset_addr = op->idx.offset + *address;
1434
12.7k
    op->idx.offset_bits = M680X_OFFSET_BITS_5;
1435
12.7k
  }
1436
29.2k
  else {
1437
29.2k
    if ((post_byte & 0xe0) == 0xe0)
1438
16.1k
      op->idx.base_reg =
1439
16.1k
        g_idx12_to_reg_ids[(post_byte >> 3) & 0x03];
1440
1441
29.2k
    switch (post_byte & 0xe7) {
1442
2.15k
    case 0xe0:
1443
5.25k
    case 0xe1: // n9,R
1444
5.25k
      read_byte(info, &offset8, (*address)++);
1445
5.25k
      op->idx.offset = offset8;
1446
1447
5.25k
      if (post_byte & 0x01) // sign extension
1448
3.09k
        op->idx.offset |= 0xff00;
1449
1450
5.25k
      op->idx.offset_bits = M680X_OFFSET_BITS_9;
1451
1452
5.25k
      if (op->idx.base_reg == M680X_REG_PC)
1453
1.87k
        op->idx.offset_addr = op->idx.offset + *address;
1454
1455
5.25k
      break;
1456
1457
3.25k
    case 0xe3: // [n16,R]
1458
3.25k
      op->idx.flags |= M680X_IDX_INDIRECT;
1459
1460
    // intentionally fall through
1461
6.26k
    case 0xe2: // n16,R
1462
6.26k
      read_word(info, (uint16_t *)&op->idx.offset, *address);
1463
6.26k
      (*address) += 2;
1464
6.26k
      op->idx.offset_bits = M680X_OFFSET_BITS_16;
1465
1466
6.26k
      if (op->idx.base_reg == M680X_REG_PC)
1467
1.40k
        op->idx.offset_addr = op->idx.offset + *address;
1468
1469
6.26k
      break;
1470
1471
1.21k
    case 0xe4: // A,R
1472
2.21k
    case 0xe5: // B,R
1473
3.28k
    case 0xe6: // D,R
1474
3.28k
      op->idx.offset_reg =
1475
3.28k
        g_or12_to_reg_ids[post_byte & 0x03];
1476
3.28k
      break;
1477
1478
1.38k
    case 0xe7: // [D,R]
1479
1.38k
      op->idx.offset_reg = M680X_REG_D;
1480
1.38k
      op->idx.flags |= M680X_IDX_INDIRECT;
1481
1.38k
      break;
1482
1483
13.0k
    default: // n,-r n,+r n,r- n,r+
1484
      // PC is not allowed in this mode
1485
13.0k
      op->idx.base_reg =
1486
13.0k
        g_idx12_to_reg_ids[(post_byte >> 6) & 0x03];
1487
13.0k
      op->idx.inc_dec = post_byte & 0x0f;
1488
1489
13.0k
      if (op->idx.inc_dec & 0x08) // evtl. sign extend value
1490
5.75k
        op->idx.inc_dec |= 0xf0;
1491
1492
13.0k
      if (op->idx.inc_dec >= 0)
1493
7.32k
        op->idx.inc_dec++;
1494
1495
13.0k
      if (post_byte & 0x10)
1496
3.58k
        op->idx.flags |= M680X_IDX_POST_INC_DEC;
1497
1498
13.0k
      break;
1499
1500
29.2k
    }
1501
29.2k
  }
1502
42.0k
}
1503
1504
static void index_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1505
794
{
1506
794
  cs_m680x *m680x = &info->m680x;
1507
794
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1508
1509
794
  op->type = M680X_OP_CONSTANT;
1510
794
  read_byte(info, &op->const_val, (*address)++);
1511
794
};
1512
1513
static void direct_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1514
62.8k
{
1515
62.8k
  cs_m680x *m680x = &info->m680x;
1516
62.8k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1517
1518
62.8k
  op->type = M680X_OP_DIRECT;
1519
62.8k
  set_operand_size(info, op, 1);
1520
62.8k
  read_byte(info, &op->direct_addr, (*address)++);
1521
62.8k
};
1522
1523
static void extended_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1524
54.7k
{
1525
54.7k
  cs_m680x *m680x = &info->m680x;
1526
54.7k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1527
1528
54.7k
  op->type = M680X_OP_EXTENDED;
1529
54.7k
  set_operand_size(info, op, 1);
1530
54.7k
  read_word(info, &op->ext.address, *address);
1531
54.7k
  *address += 2;
1532
54.7k
}
1533
1534
static void immediate_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1535
33.4k
{
1536
33.4k
  cs_m680x *m680x = &info->m680x;
1537
33.4k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1538
33.4k
  uint16_t word = 0;
1539
33.4k
  int16_t sword = 0;
1540
1541
33.4k
  op->type = M680X_OP_IMMEDIATE;
1542
33.4k
  set_operand_size(info, op, 1);
1543
1544
33.4k
  switch (op->size) {
1545
26.1k
  case 1:
1546
26.1k
    read_byte_sign_extended(info, &sword, *address);
1547
26.1k
    op->imm = sword;
1548
26.1k
    break;
1549
1550
5.85k
  case 2:
1551
5.85k
    read_word(info, &word, *address);
1552
5.85k
    op->imm = (int16_t)word;
1553
5.85k
    break;
1554
1555
1.44k
  case 4:
1556
1.44k
    read_sdword(info, &op->imm, *address);
1557
1.44k
    break;
1558
1559
0
  default:
1560
0
    op->imm = 0;
1561
0
    CS_ASSERT(0 && "Unexpected immediate byte size");
1562
33.4k
  }
1563
1564
33.4k
  *address += op->size;
1565
33.4k
}
1566
1567
// handler for bit move instructions, e.g: BAND A,5,1,$40  Used by HD6309
1568
static void bit_move_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1569
777
{
1570
777
  static const m680x_reg m680x_reg[] = {
1571
777
    M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_INVALID,
1572
777
  };
1573
1574
777
  uint8_t post_byte = 0;
1575
777
  cs_m680x *m680x = &info->m680x;
1576
777
  cs_m680x_op *op;
1577
1578
777
  read_byte(info, &post_byte, *address);
1579
777
  (*address)++;
1580
1581
  // operand[0] = register
1582
777
  add_reg_operand(info, m680x_reg[post_byte >> 6]);
1583
1584
  // operand[1] = bit index in source operand
1585
777
  op = &m680x->operands[m680x->op_count++];
1586
777
  op->type = M680X_OP_CONSTANT;
1587
777
  op->const_val = (post_byte >> 3) & 0x07;
1588
1589
  // operand[2] = bit index in destination operand
1590
777
  op = &m680x->operands[m680x->op_count++];
1591
777
  op->type = M680X_OP_CONSTANT;
1592
777
  op->const_val = post_byte & 0x07;
1593
1594
777
  direct_hdlr(MI, info, address);
1595
777
}
1596
1597
// handler for TFM instruction, e.g: TFM X+,Y+  Used by HD6309
1598
static void tfm_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1599
1.07k
{
1600
1.07k
  static const uint8_t inc_dec_r0[] = {
1601
1.07k
    1, -1, 1, 0,
1602
1.07k
  };
1603
1.07k
  static const uint8_t inc_dec_r1[] = {
1604
1.07k
    1, -1, 0, 1,
1605
1.07k
  };
1606
1.07k
  uint8_t regs = 0;
1607
1.07k
  uint8_t index = (MI->Opcode & 0xff) - 0x38;
1608
1609
1.07k
  read_byte(info, &regs, *address);
1610
1611
1.07k
  add_indexed_operand(info, g_tfr_exg_reg_ids[regs >> 4], true,
1612
1.07k
    inc_dec_r0[index], M680X_OFFSET_NONE, 0, true);
1613
1.07k
  add_indexed_operand(info, g_tfr_exg_reg_ids[regs & 0x0f], true,
1614
1.07k
    inc_dec_r1[index], M680X_OFFSET_NONE, 0, true);
1615
1616
1.07k
  add_reg_to_rw_list(MI, M680X_REG_W, READ | WRITE);
1617
1.07k
}
1618
1619
static void opidx_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1620
1.85k
{
1621
1.85k
  cs_m680x *m680x = &info->m680x;
1622
1.85k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1623
1624
  // bit index is coded in Opcode
1625
1.85k
  op->type = M680X_OP_CONSTANT;
1626
1.85k
  op->const_val = (MI->Opcode & 0x0e) >> 1;
1627
1.85k
}
1628
1629
// handler for bit test and branch instruction. Used by M6805.
1630
// The bit index is part of the opcode.
1631
// Example: BRSET 3,<$40,LOOP
1632
static void opidx_dir_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1633
5.08k
{
1634
5.08k
  cs_m680x *m680x = &info->m680x;
1635
5.08k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1636
1637
  // bit index is coded in Opcode
1638
5.08k
  op->type = M680X_OP_CONSTANT;
1639
5.08k
  op->const_val = (MI->Opcode & 0x0e) >> 1;
1640
5.08k
  direct_hdlr(MI, info, address);
1641
5.08k
  relative8_hdlr(MI, info, address);
1642
1643
5.08k
  add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY);
1644
5.08k
}
1645
1646
static void indexedX0_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1647
8.56k
{
1648
8.56k
  add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_NONE,
1649
8.56k
    0, false);
1650
8.56k
}
1651
1652
static void indexedX16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1653
2.38k
{
1654
2.38k
  uint16_t offset = 0;
1655
1656
2.38k
  read_word(info, &offset, *address);
1657
2.38k
  *address += 2;
1658
2.38k
  add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_16,
1659
2.38k
    offset, false);
1660
2.38k
}
1661
1662
static void imm_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1663
2.22k
{
1664
2.22k
  immediate_hdlr(MI, info, address);
1665
2.22k
  relative8_hdlr(MI, info, address);
1666
2.22k
}
1667
1668
static void indexedS_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1669
925
{
1670
925
  uint8_t offset = 0;
1671
1672
925
  read_byte(info, &offset, (*address)++);
1673
1674
925
  add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_8,
1675
925
    (uint16_t)offset, false);
1676
925
}
1677
1678
static void indexedS16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1679
637
{
1680
637
  uint16_t offset = 0;
1681
1682
637
  read_word(info, &offset, *address);
1683
637
  address += 2;
1684
1685
637
  add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_16,
1686
637
    offset, false);
1687
637
}
1688
1689
static void indexedX0p_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1690
1.01k
{
1691
1.01k
  add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_NONE,
1692
1.01k
    0, true);
1693
1.01k
}
1694
1695
static void indexedXp_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1696
2.83k
{
1697
2.83k
  uint8_t offset = 0;
1698
1699
2.83k
  read_byte(info, &offset, (*address)++);
1700
1701
2.83k
  add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_BITS_8,
1702
2.83k
    (uint16_t)offset, false);
1703
2.83k
}
1704
1705
static void imm_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1706
9.09k
{
1707
9.09k
  cs_m680x *m680x = &info->m680x;
1708
9.09k
  cs_m680x_op *op = &m680x->operands[m680x->op_count++];
1709
1710
9.09k
  indexed12_hdlr(MI, info, address);
1711
9.09k
  op->type = M680X_OP_IMMEDIATE;
1712
1713
9.09k
  if (info->insn == M680X_INS_MOVW) {
1714
3.77k
    uint16_t imm16 = 0;
1715
1716
3.77k
    read_word(info, &imm16, *address);
1717
3.77k
    op->imm = (int16_t)imm16;
1718
3.77k
    op->size = 2;
1719
3.77k
  }
1720
5.31k
  else {
1721
5.31k
    uint8_t imm8 = 0;
1722
1723
5.31k
    read_byte(info, &imm8, *address);
1724
5.31k
    op->imm = (int8_t)imm8;
1725
5.31k
    op->size = 1;
1726
5.31k
  }
1727
1728
9.09k
  set_operand_size(info, op, 1);
1729
9.09k
}
1730
1731
static void ext_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1732
2.01k
{
1733
2.01k
  cs_m680x *m680x = &info->m680x;
1734
2.01k
  cs_m680x_op *op0 = &m680x->operands[m680x->op_count++];
1735
2.01k
  uint16_t imm16 = 0;
1736
1737
2.01k
  indexed12_hdlr(MI, info, address);
1738
2.01k
  read_word(info, &imm16, *address);
1739
2.01k
  op0->type = M680X_OP_EXTENDED;
1740
2.01k
  op0->ext.address = (int16_t)imm16;
1741
2.01k
  set_operand_size(info, op0, 1);
1742
2.01k
}
1743
1744
// handler for CPU12 DBEQ/DNBE/IBEQ/IBNE/TBEQ/TBNE instructions.
1745
// Example: DBNE X,$1000
1746
static void loop_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
1747
2.09k
{
1748
2.09k
  static const m680x_reg index_to_reg_id[] = {
1749
2.09k
    M680X_REG_A, M680X_REG_B, M680X_REG_INVALID, M680X_REG_INVALID,
1750
2.09k
    M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S,
1751
2.09k
  };
1752
2.09k
  static const m680x_insn index_to_insn_id[] = {
1753
2.09k
    M680X_INS_DBEQ, M680X_INS_DBNE, M680X_INS_TBEQ, M680X_INS_TBNE,
1754
2.09k
    M680X_INS_IBEQ, M680X_INS_IBNE, M680X_INS_ILLGL, M680X_INS_ILLGL
1755
2.09k
  };
1756
2.09k
  cs_m680x *m680x = &info->m680x;
1757
2.09k
  uint8_t post_byte = 0;
1758
2.09k
  uint8_t rel = 0;
1759
2.09k
  cs_m680x_op *op;
1760
1761
2.09k
  read_byte(info, &post_byte, (*address)++);
1762
1763
2.09k
  info->insn = index_to_insn_id[(post_byte >> 5) & 0x07];
1764
1765
2.09k
  if (info->insn == M680X_INS_ILLGL) {
1766
0
    illegal_hdlr(MI, info, address);
1767
0
  };
1768
1769
2.09k
  read_byte(info, &rel, (*address)++);
1770
1771
2.09k
  add_reg_operand(info, index_to_reg_id[post_byte & 0x07]);
1772
1773
2.09k
  op = &m680x->operands[m680x->op_count++];
1774
1775
2.09k
  op->type = M680X_OP_RELATIVE;
1776
1777
2.09k
  op->rel.offset = (post_byte & 0x10) ? 0xff00 | rel : rel;
1778
1779
2.09k
  op->rel.address = *address + op->rel.offset;
1780
1781
2.09k
  add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL);
1782
2.09k
}
1783
1784
static void (*const g_insn_handler[])(MCInst *, m680x_info *, uint16_t *) = {
1785
  illegal_hdlr,
1786
  relative8_hdlr,
1787
  relative16_hdlr,
1788
  immediate_hdlr, // 8-bit
1789
  immediate_hdlr, // 16-bit
1790
  immediate_hdlr, // 32-bit
1791
  direct_hdlr,
1792
  extended_hdlr,
1793
  indexedX_hdlr,
1794
  indexedY_hdlr,
1795
  indexed09_hdlr,
1796
  inherent_hdlr,
1797
  reg_reg09_hdlr,
1798
  reg_bits_hdlr,
1799
  bit_move_hdlr,
1800
  tfm_hdlr,
1801
  opidx_hdlr,
1802
  opidx_dir_rel_hdlr,
1803
  indexedX0_hdlr,
1804
  indexedX16_hdlr,
1805
  imm_rel_hdlr,
1806
  indexedS_hdlr,
1807
  indexedS16_hdlr,
1808
  indexedXp_hdlr,
1809
  indexedX0p_hdlr,
1810
  indexed12_hdlr,
1811
  indexed12_hdlr, // subset of indexed12
1812
  reg_reg12_hdlr,
1813
  loop_hdlr,
1814
  index_hdlr,
1815
  imm_idx12_x_hdlr,
1816
  imm_idx12_x_hdlr,
1817
  ext_idx12_x_hdlr,
1818
}; /* handler function pointers */
1819
1820
/* Disasemble one instruction at address and store in str_buff */
1821
static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info,
1822
  uint16_t address)
1823
470k
{
1824
470k
  cs_m680x *m680x = &info->m680x;
1825
470k
  cs_detail *detail = MI->flat_insn->detail;
1826
470k
  uint16_t base_address = address;
1827
470k
  insn_desc insn_description;
1828
470k
  e_access_mode access_mode;
1829
1830
470k
  if (detail != NULL) {
1831
470k
    memset(detail, 0, offsetof(cs_detail, m680x)+sizeof(cs_m680x));
1832
470k
  }
1833
1834
470k
  memset(&insn_description, 0, sizeof(insn_description));
1835
470k
  memset(m680x, 0, sizeof(*m680x));
1836
470k
  info->insn_size = 1;
1837
1838
470k
  if (decode_insn(info, address, &insn_description)) {
1839
410k
    m680x_reg reg;
1840
1841
410k
    if (insn_description.opcode > 0xff)
1842
24.7k
      address += 2; // 8-bit opcode + page prefix
1843
385k
    else
1844
385k
      address++; // 8-bit opcode only
1845
1846
410k
    info->insn = insn_description.insn;
1847
1848
410k
    MCInst_setOpcode(MI, insn_description.opcode);
1849
1850
410k
    reg = g_insn_props[info->insn].reg0;
1851
1852
410k
    if (reg != M680X_REG_INVALID) {
1853
213k
      if (reg == M680X_REG_HX &&
1854
213k
        (!info->cpu->reg_byte_size[reg]))
1855
479
        reg = M680X_REG_X;
1856
1857
213k
      add_reg_operand(info, reg);
1858
      // First (or second) operand is a register which is
1859
      // part of the mnemonic
1860
213k
      m680x->flags |= M680X_FIRST_OP_IN_MNEM;
1861
213k
      reg = g_insn_props[info->insn].reg1;
1862
1863
213k
      if (reg != M680X_REG_INVALID) {
1864
6.50k
        if (reg == M680X_REG_HX &&
1865
6.50k
          (!info->cpu->reg_byte_size[reg]))
1866
719
          reg = M680X_REG_X;
1867
1868
6.50k
        add_reg_operand(info, reg);
1869
6.50k
        m680x->flags |= M680X_SECOND_OP_IN_MNEM;
1870
6.50k
      }
1871
213k
    }
1872
1873
    // Call addressing mode specific instruction handler
1874
410k
    (g_insn_handler[insn_description.hid[0]])(MI, info,
1875
410k
      &address);
1876
410k
    (g_insn_handler[insn_description.hid[1]])(MI, info,
1877
410k
      &address);
1878
1879
410k
    add_insn_group(detail, g_insn_props[info->insn].group);
1880
1881
410k
    if (g_insn_props[info->insn].cc_modified &&
1882
410k
      (info->cpu->insn_cc_not_modified[0] != info->insn) &&
1883
410k
      (info->cpu->insn_cc_not_modified[1] != info->insn))
1884
249k
      add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY);
1885
1886
410k
    access_mode = g_insn_props[info->insn].access_mode;
1887
1888
    // Fix for M6805 BSET/BCLR. It has a differnt operand order
1889
    // in comparison to the M6811
1890
410k
    if ((info->cpu->insn_cc_not_modified[0] == info->insn) ||
1891
410k
      (info->cpu->insn_cc_not_modified[1] == info->insn))
1892
1.85k
      access_mode = rmmm;
1893
1894
410k
    build_regs_read_write_counts(MI, info, access_mode);
1895
410k
    add_operators_access(MI, info, access_mode);
1896
1897
410k
    if (g_insn_props[info->insn].update_reg_access)
1898
37.8k
      set_changed_regs_read_write_counts(MI, info);
1899
1900
410k
    info->insn_size = (uint8_t)insn_description.insn_size;
1901
1902
410k
    return info->insn_size;
1903
410k
  }
1904
59.8k
  else
1905
59.8k
    MCInst_setOpcode(MI, insn_description.opcode);
1906
1907
  // Illegal instruction
1908
59.8k
  address = base_address;
1909
59.8k
  illegal_hdlr(MI, info, &address);
1910
59.8k
  return 1;
1911
470k
}
1912
1913
// Tables to get the byte size of a register on the CPU
1914
// based on an enum m680x_reg value.
1915
// Invalid registers return 0.
1916
static const uint8_t g_m6800_reg_byte_size[22] = {
1917
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1918
  0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0
1919
};
1920
1921
static const uint8_t g_m6805_reg_byte_size[22] = {
1922
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1923
  0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0, 2, 0, 0
1924
};
1925
1926
static const uint8_t g_m6808_reg_byte_size[22] = {
1927
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1928
  0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 1, 1, 0, 2, 0, 0, 0, 2, 0, 0
1929
};
1930
1931
static const uint8_t g_m6801_reg_byte_size[22] = {
1932
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1933
  0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0
1934
};
1935
1936
static const uint8_t g_m6811_reg_byte_size[22] = {
1937
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1938
  0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 0, 0
1939
};
1940
1941
static const uint8_t g_cpu12_reg_byte_size[22] = {
1942
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1943
  0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 2, 2
1944
};
1945
1946
static const uint8_t g_m6809_reg_byte_size[22] = {
1947
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1948
  0, 1, 1, 0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 2, 2, 2, 2, 0, 0, 2, 0, 0
1949
};
1950
1951
static const uint8_t g_hd6309_reg_byte_size[22] = {
1952
  // A  B  E  F  0  D  W  CC DP MD HX H  X  Y  S  U  V  Q  PC T2 T3
1953
  0, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 0, 0, 2, 2, 2, 2, 2, 4, 2, 0, 0
1954
};
1955
1956
// Table to check for a valid register nibble on the M6809 CPU
1957
// used for TFR and EXG instruction.
1958
static const bool m6809_tfr_reg_valid[16] = {
1959
  true, true, true, true, true,  true,  false, false,
1960
  true, true, true, true, false, false, false, false,
1961
};
1962
1963
static const cpu_tables g_cpu_tables[] = {
1964
  {
1965
    // M680X_CPU_TYPE_INVALID
1966
    NULL,
1967
    { NULL, NULL },
1968
    { 0, 0 },
1969
    { 0x00, 0x00, 0x00 },
1970
    { NULL, NULL, NULL },
1971
    { 0, 0, 0 },
1972
    NULL,
1973
    NULL,
1974
    { M680X_INS_INVLD, M680X_INS_INVLD }
1975
  },
1976
  {
1977
    // M680X_CPU_TYPE_6301
1978
    &g_m6800_inst_page1_table[0],
1979
    { &g_m6801_inst_overlay_table[0], &g_hd6301_inst_overlay_table[0] },
1980
    {
1981
      ARR_SIZE(g_m6801_inst_overlay_table),
1982
      ARR_SIZE(g_hd6301_inst_overlay_table)
1983
    },
1984
    { 0x00, 0x00, 0x00 },
1985
    { NULL, NULL, NULL },
1986
    { 0, 0, 0 },
1987
    &g_m6801_reg_byte_size[0],
1988
    NULL,
1989
    { M680X_INS_INVLD, M680X_INS_INVLD }
1990
  },
1991
  {
1992
    // M680X_CPU_TYPE_6309
1993
    &g_m6809_inst_page1_table[0],
1994
    { &g_hd6309_inst_overlay_table[0], NULL },
1995
    { ARR_SIZE(g_hd6309_inst_overlay_table), 0 },
1996
    { 0x10, 0x11, 0x00 },
1997
    { &g_hd6309_inst_page2_table[0], &g_hd6309_inst_page3_table[0], NULL },
1998
    {
1999
      ARR_SIZE(g_hd6309_inst_page2_table),
2000
      ARR_SIZE(g_hd6309_inst_page3_table),
2001
      0
2002
    },
2003
    &g_hd6309_reg_byte_size[0],
2004
    NULL,
2005
    { M680X_INS_INVLD, M680X_INS_INVLD }
2006
  },
2007
  {
2008
    // M680X_CPU_TYPE_6800
2009
    &g_m6800_inst_page1_table[0],
2010
    { NULL, NULL },
2011
    { 0, 0 },
2012
    { 0x00, 0x00, 0x00 },
2013
    { NULL, NULL, NULL },
2014
    { 0, 0, 0 },
2015
    &g_m6800_reg_byte_size[0],
2016
    NULL,
2017
    { M680X_INS_INVLD, M680X_INS_INVLD }
2018
  },
2019
  {
2020
    // M680X_CPU_TYPE_6801
2021
    &g_m6800_inst_page1_table[0],
2022
    { &g_m6801_inst_overlay_table[0], NULL },
2023
    { ARR_SIZE(g_m6801_inst_overlay_table), 0 },
2024
    { 0x00, 0x00, 0x00 },
2025
    { NULL, NULL, NULL },
2026
    { 0, 0, 0 },
2027
    &g_m6801_reg_byte_size[0],
2028
    NULL,
2029
    { M680X_INS_INVLD, M680X_INS_INVLD }
2030
  },
2031
  {
2032
    // M680X_CPU_TYPE_6805
2033
    &g_m6805_inst_page1_table[0],
2034
    { NULL, NULL },
2035
    { 0, 0 },
2036
    { 0x00, 0x00, 0x00 },
2037
    { NULL, NULL, NULL },
2038
    { 0, 0, 0 },
2039
    &g_m6805_reg_byte_size[0],
2040
    NULL,
2041
    { M680X_INS_BCLR, M680X_INS_BSET }
2042
  },
2043
  {
2044
    // M680X_CPU_TYPE_6808
2045
    &g_m6805_inst_page1_table[0],
2046
    { &g_m6808_inst_overlay_table[0], NULL },
2047
    { ARR_SIZE(g_m6808_inst_overlay_table), 0 },
2048
    { 0x9E, 0x00, 0x00 },
2049
    { &g_m6808_inst_page2_table[0], NULL, NULL },
2050
    { ARR_SIZE(g_m6808_inst_page2_table), 0, 0 },
2051
    &g_m6808_reg_byte_size[0],
2052
    NULL,
2053
    { M680X_INS_BCLR, M680X_INS_BSET }
2054
  },
2055
  {
2056
    // M680X_CPU_TYPE_6809
2057
    &g_m6809_inst_page1_table[0],
2058
    { NULL, NULL },
2059
    { 0, 0 },
2060
    { 0x10, 0x11, 0x00 },
2061
    {
2062
      &g_m6809_inst_page2_table[0],
2063
      &g_m6809_inst_page3_table[0],
2064
      NULL
2065
    },
2066
    {
2067
      ARR_SIZE(g_m6809_inst_page2_table),
2068
      ARR_SIZE(g_m6809_inst_page3_table),
2069
      0
2070
    },
2071
    &g_m6809_reg_byte_size[0],
2072
    &m6809_tfr_reg_valid[0],
2073
    { M680X_INS_INVLD, M680X_INS_INVLD }
2074
  },
2075
  {
2076
    // M680X_CPU_TYPE_6811
2077
    &g_m6800_inst_page1_table[0],
2078
    {
2079
      &g_m6801_inst_overlay_table[0],
2080
      &g_m6811_inst_overlay_table[0]
2081
    },
2082
    {
2083
      ARR_SIZE(g_m6801_inst_overlay_table),
2084
      ARR_SIZE(g_m6811_inst_overlay_table)
2085
    },
2086
    { 0x18, 0x1A, 0xCD },
2087
    {
2088
      &g_m6811_inst_page2_table[0],
2089
      &g_m6811_inst_page3_table[0],
2090
      &g_m6811_inst_page4_table[0]
2091
    },
2092
    {
2093
      ARR_SIZE(g_m6811_inst_page2_table),
2094
      ARR_SIZE(g_m6811_inst_page3_table),
2095
      ARR_SIZE(g_m6811_inst_page4_table)
2096
    },
2097
    &g_m6811_reg_byte_size[0],
2098
    NULL,
2099
    { M680X_INS_INVLD, M680X_INS_INVLD }
2100
  },
2101
  {
2102
    // M680X_CPU_TYPE_CPU12
2103
    &g_cpu12_inst_page1_table[0],
2104
    { NULL, NULL },
2105
    { 0, 0 },
2106
    { 0x18, 0x00, 0x00 },
2107
    { &g_cpu12_inst_page2_table[0], NULL, NULL },
2108
    { ARR_SIZE(g_cpu12_inst_page2_table), 0, 0 },
2109
    &g_cpu12_reg_byte_size[0],
2110
    NULL,
2111
    { M680X_INS_INVLD, M680X_INS_INVLD }
2112
  },
2113
  {
2114
    // M680X_CPU_TYPE_HCS08
2115
    &g_m6805_inst_page1_table[0],
2116
    {
2117
      &g_m6808_inst_overlay_table[0],
2118
      &g_hcs08_inst_overlay_table[0]
2119
    },
2120
    {
2121
      ARR_SIZE(g_m6808_inst_overlay_table),
2122
      ARR_SIZE(g_hcs08_inst_overlay_table)
2123
    },
2124
    { 0x9E, 0x00, 0x00 },
2125
    { &g_hcs08_inst_page2_table[0], NULL, NULL },
2126
    { ARR_SIZE(g_hcs08_inst_page2_table), 0, 0 },
2127
    &g_m6808_reg_byte_size[0],
2128
    NULL,
2129
    { M680X_INS_BCLR, M680X_INS_BSET }
2130
  },
2131
};
2132
2133
static bool m680x_setup_internals(m680x_info *info, e_cpu_type cpu_type,
2134
  uint16_t address,
2135
  const uint8_t *code, uint16_t code_len)
2136
470k
{
2137
470k
  if (cpu_type == M680X_CPU_TYPE_INVALID) {
2138
0
    return false;
2139
0
  }
2140
2141
470k
  info->code = code;
2142
470k
  info->size = code_len;
2143
470k
  info->offset = address;
2144
470k
  info->cpu_type = cpu_type;
2145
2146
470k
  info->cpu = &g_cpu_tables[info->cpu_type];
2147
2148
470k
  return true;
2149
470k
}
2150
2151
bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len,
2152
  MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
2153
470k
{
2154
470k
  unsigned int insn_size = 0;
2155
470k
  e_cpu_type cpu_type = M680X_CPU_TYPE_INVALID; // No default CPU type
2156
470k
  cs_struct *handle = (cs_struct *)ud;
2157
470k
  m680x_info *info = (m680x_info *)handle->printer_info;
2158
2159
470k
  MCInst_clear(MI);
2160
2161
470k
  if (handle->mode & CS_MODE_M680X_6800)
2162
10.9k
    cpu_type = M680X_CPU_TYPE_6800;
2163
2164
459k
  else if (handle->mode & CS_MODE_M680X_6801)
2165
1.59k
    cpu_type = M680X_CPU_TYPE_6801;
2166
2167
457k
  else if (handle->mode & CS_MODE_M680X_6805)
2168
11.8k
    cpu_type = M680X_CPU_TYPE_6805;
2169
2170
445k
  else if (handle->mode & CS_MODE_M680X_6808)
2171
18.0k
    cpu_type = M680X_CPU_TYPE_6808;
2172
2173
427k
  else if (handle->mode & CS_MODE_M680X_HCS08)
2174
24.0k
    cpu_type = M680X_CPU_TYPE_HCS08;
2175
2176
403k
  else if (handle->mode & CS_MODE_M680X_6809)
2177
46.1k
    cpu_type = M680X_CPU_TYPE_6809;
2178
2179
357k
  else if (handle->mode & CS_MODE_M680X_6301)
2180
1.44k
    cpu_type = M680X_CPU_TYPE_6301;
2181
2182
356k
  else if (handle->mode & CS_MODE_M680X_6309)
2183
150k
    cpu_type = M680X_CPU_TYPE_6309;
2184
2185
205k
  else if (handle->mode & CS_MODE_M680X_6811)
2186
29.4k
    cpu_type = M680X_CPU_TYPE_6811;
2187
2188
176k
  else if (handle->mode & CS_MODE_M680X_CPU12)
2189
176k
    cpu_type = M680X_CPU_TYPE_CPU12;
2190
2191
470k
  if (cpu_type != M680X_CPU_TYPE_INVALID &&
2192
470k
    m680x_setup_internals(info, cpu_type, (uint16_t)address, code,
2193
470k
      (uint16_t)code_len))
2194
470k
    insn_size = m680x_disassemble(MI, info, (uint16_t)address);
2195
2196
470k
  if (insn_size == 0) {
2197
0
    *size = 1;
2198
0
    return false;
2199
0
  }
2200
2201
  // Make sure we always stay within range
2202
470k
  if (insn_size > code_len) {
2203
33
    *size = (uint16_t)code_len;
2204
33
    return false;
2205
33
  }
2206
470k
  else
2207
470k
    *size = (uint16_t)insn_size;
2208
2209
470k
  return true;
2210
470k
}
2211
2212
cs_err M680X_disassembler_init(cs_struct *ud)
2213
3.57k
{
2214
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6800_reg_byte_size)) {
2215
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6800_reg_byte_size));
2216
2217
0
    return CS_ERR_MODE;
2218
0
  }
2219
2220
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6801_reg_byte_size)) {
2221
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6801_reg_byte_size));
2222
2223
0
    return CS_ERR_MODE;
2224
0
  }
2225
2226
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6805_reg_byte_size)) {
2227
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6805_reg_byte_size));
2228
2229
0
    return CS_ERR_MODE;
2230
0
  }
2231
2232
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6808_reg_byte_size)) {
2233
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6808_reg_byte_size));
2234
2235
0
    return CS_ERR_MODE;
2236
0
  }
2237
2238
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6811_reg_byte_size)) {
2239
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6811_reg_byte_size));
2240
2241
0
    return CS_ERR_MODE;
2242
0
  }
2243
2244
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_cpu12_reg_byte_size)) {
2245
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_cpu12_reg_byte_size));
2246
2247
0
    return CS_ERR_MODE;
2248
0
  }
2249
2250
3.57k
  if (M680X_REG_ENDING != ARR_SIZE(g_m6809_reg_byte_size)) {
2251
0
    CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6809_reg_byte_size));
2252
2253
0
    return CS_ERR_MODE;
2254
0
  }
2255
2256
3.57k
  if (M680X_INS_ENDING != ARR_SIZE(g_insn_props)) {
2257
0
    CS_ASSERT(M680X_INS_ENDING == ARR_SIZE(g_insn_props));
2258
2259
0
    return CS_ERR_MODE;
2260
0
  }
2261
2262
3.57k
  if (M680X_CPU_TYPE_ENDING != ARR_SIZE(g_cpu_tables)) {
2263
0
    CS_ASSERT(M680X_CPU_TYPE_ENDING == ARR_SIZE(g_cpu_tables));
2264
2265
0
    return CS_ERR_MODE;
2266
0
  }
2267
2268
3.57k
  if (HANDLER_ID_ENDING != ARR_SIZE(g_insn_handler)) {
2269
0
    CS_ASSERT(HANDLER_ID_ENDING == ARR_SIZE(g_insn_handler));
2270
2271
0
    return CS_ERR_MODE;
2272
0
  }
2273
2274
3.57k
  if (ACCESS_MODE_ENDING !=  MATRIX_SIZE(g_access_mode_to_access)) {
2275
0
    CS_ASSERT(ACCESS_MODE_ENDING ==
2276
0
      MATRIX_SIZE(g_access_mode_to_access));
2277
2278
0
    return CS_ERR_MODE;
2279
0
  }
2280
2281
3.57k
  return CS_ERR_OK;
2282
3.57k
}
2283
2284
#ifndef CAPSTONE_DIET
2285
void M680X_reg_access(const cs_insn *insn,
2286
  cs_regs regs_read, uint8_t *regs_read_count,
2287
  cs_regs regs_write, uint8_t *regs_write_count)
2288
0
{
2289
0
  if (insn->detail == NULL) {
2290
0
    *regs_read_count = 0;
2291
0
    *regs_write_count = 0;
2292
0
  }
2293
0
  else {
2294
0
    *regs_read_count = insn->detail->regs_read_count;
2295
0
    *regs_write_count = insn->detail->regs_write_count;
2296
2297
0
    memcpy(regs_read, insn->detail->regs_read,
2298
0
      *regs_read_count * sizeof(insn->detail->regs_read[0]));
2299
0
    memcpy(regs_write, insn->detail->regs_write,
2300
0
      *regs_write_count *
2301
0
      sizeof(insn->detail->regs_write[0]));
2302
0
  }
2303
0
}
2304
#endif
2305
2306
#endif
2307