/src/capstonenext/Mapping.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
3 | | /* Rot127 <unisono@quyllur.org>, 2022-2023 */ |
4 | | |
5 | | #include "Mapping.h" |
6 | | #include "capstone/capstone.h" |
7 | | #include "utils.h" |
8 | | |
9 | | // create a cache for fast id lookup |
10 | | static unsigned short *make_id2insn(const insn_map *insns, unsigned int size) |
11 | 29.7k | { |
12 | | // NOTE: assume that the max id is always put at the end of insns array |
13 | 29.7k | unsigned short max_id = insns[size - 1].id; |
14 | 29.7k | unsigned int i; |
15 | | |
16 | 29.7k | unsigned short *cache = |
17 | 29.7k | (unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache)); |
18 | | |
19 | 62.0M | for (i = 1; i < size; i++) |
20 | 61.9M | cache[insns[i].id] = i; |
21 | | |
22 | 29.7k | return cache; |
23 | 29.7k | } |
24 | | |
25 | | // look for @id in @insns, given its size in @max. first time call will update |
26 | | // @cache. return 0 if not found |
27 | | unsigned short insn_find(const insn_map *insns, unsigned int max, |
28 | | unsigned int id, unsigned short **cache) |
29 | 2.79M | { |
30 | 2.79M | if (id > insns[max - 1].id) |
31 | 0 | return 0; |
32 | | |
33 | 2.79M | if (*cache == NULL) |
34 | 29.7k | *cache = make_id2insn(insns, max); |
35 | | |
36 | 2.79M | return (*cache)[id]; |
37 | 2.79M | } |
38 | | |
39 | | // Gives the id for the given @name if it is saved in @map. |
40 | | // Returns the id or -1 if not found. |
41 | | int name2id(const name_map *map, int max, const char *name) |
42 | 151k | { |
43 | 151k | int i; |
44 | | |
45 | 24.7M | for (i = 0; i < max; i++) { |
46 | 24.6M | if (!strcmp(map[i].name, name)) { |
47 | 111k | return map[i].id; |
48 | 111k | } |
49 | 24.6M | } |
50 | | |
51 | | // nothing match |
52 | 40.2k | return -1; |
53 | 151k | } |
54 | | |
55 | | // Gives the name for the given @id if it is saved in @map. |
56 | | // Returns the name or NULL if not found. |
57 | | const char *id2name(const name_map *map, int max, const unsigned int id) |
58 | 5.82M | { |
59 | 5.82M | int i; |
60 | | |
61 | 127M | for (i = 0; i < max; i++) { |
62 | 127M | if (map[i].id == id) { |
63 | 5.82M | return map[i].name; |
64 | 5.82M | } |
65 | 127M | } |
66 | | |
67 | | // nothing match |
68 | 0 | return NULL; |
69 | 5.82M | } |
70 | | |
71 | | /// Adds a register to the implicit write register list. |
72 | | /// It will not add the same register twice. |
73 | | void map_add_implicit_write(MCInst *MI, uint32_t Reg) |
74 | 500k | { |
75 | 500k | if (!MI->flat_insn->detail) |
76 | 0 | return; |
77 | | |
78 | 500k | uint16_t *regs_write = MI->flat_insn->detail->regs_write; |
79 | 504k | for (int i = 0; i < MAX_IMPL_W_REGS; ++i) { |
80 | 504k | if (i == MI->flat_insn->detail->regs_write_count) { |
81 | 481k | regs_write[i] = Reg; |
82 | 481k | MI->flat_insn->detail->regs_write_count++; |
83 | 481k | return; |
84 | 481k | } |
85 | 23.1k | if (regs_write[i] == Reg) |
86 | 19.5k | return; |
87 | 23.1k | } |
88 | 500k | } |
89 | | |
90 | | /// Adds a register to the implicit read register list. |
91 | | /// It will not add the same register twice. |
92 | | void map_add_implicit_read(MCInst *MI, uint32_t Reg) |
93 | 203k | { |
94 | 203k | if (!MI->flat_insn->detail) |
95 | 0 | return; |
96 | | |
97 | 203k | uint16_t *regs_read = MI->flat_insn->detail->regs_read; |
98 | 215k | for (int i = 0; i < MAX_IMPL_R_REGS; ++i) { |
99 | 215k | if (i == MI->flat_insn->detail->regs_read_count) { |
100 | 187k | regs_read[i] = Reg; |
101 | 187k | MI->flat_insn->detail->regs_read_count++; |
102 | 187k | return; |
103 | 187k | } |
104 | 27.9k | if (regs_read[i] == Reg) |
105 | 16.3k | return; |
106 | 27.9k | } |
107 | 203k | } |
108 | | |
109 | | /// Removes a register from the implicit write register list. |
110 | | void map_remove_implicit_write(MCInst *MI, uint32_t Reg) |
111 | 39.0k | { |
112 | 39.0k | if (!MI->flat_insn->detail) |
113 | 0 | return; |
114 | | |
115 | 39.0k | uint16_t *regs_write = MI->flat_insn->detail->regs_write; |
116 | 39.0k | bool shorten_list = false; |
117 | 42.9k | for (int i = 0; i < MAX_IMPL_W_REGS; ++i) { |
118 | 42.9k | if (shorten_list) { |
119 | 3.86k | regs_write[i - 1] = regs_write[i]; |
120 | 3.86k | } |
121 | 42.9k | if (i >= MI->flat_insn->detail->regs_write_count) |
122 | 39.0k | return; |
123 | | |
124 | 3.86k | if (regs_write[i] == Reg) { |
125 | 3.86k | MI->flat_insn->detail->regs_write_count--; |
126 | | // The register should exist only once in the list. |
127 | 3.86k | assert(!shorten_list); |
128 | 3.86k | shorten_list = true; |
129 | 3.86k | } |
130 | 3.86k | } |
131 | 39.0k | } |
132 | | |
133 | | /// Copies the implicit read registers of @imap to @MI->flat_insn. |
134 | | /// Already present registers will be preserved. |
135 | | void map_implicit_reads(MCInst *MI, const insn_map *imap) |
136 | 1.90M | { |
137 | 1.90M | #ifndef CAPSTONE_DIET |
138 | 1.90M | if (!MI->flat_insn->detail) |
139 | 0 | return; |
140 | | |
141 | 1.90M | cs_detail *detail = MI->flat_insn->detail; |
142 | 1.90M | unsigned Opcode = MCInst_getOpcode(MI); |
143 | 1.90M | unsigned i = 0; |
144 | 1.90M | uint16_t reg = imap[Opcode].regs_use[i]; |
145 | 1.98M | while (reg != 0) { |
146 | 87.8k | if (i >= MAX_IMPL_R_REGS || |
147 | 87.8k | detail->regs_read_count >= MAX_IMPL_R_REGS) { |
148 | 0 | printf("ERROR: Too many implicit read register defined in " |
149 | 0 | "instruction mapping.\n"); |
150 | 0 | return; |
151 | 0 | } |
152 | 87.8k | detail->regs_read[detail->regs_read_count++] = reg; |
153 | 87.8k | reg = imap[Opcode].regs_use[++i]; |
154 | 87.8k | } |
155 | 1.90M | #endif // CAPSTONE_DIET |
156 | 1.90M | } |
157 | | |
158 | | /// Copies the implicit write registers of @imap to @MI->flat_insn. |
159 | | /// Already present registers will be preserved. |
160 | | void map_implicit_writes(MCInst *MI, const insn_map *imap) |
161 | 1.90M | { |
162 | 1.90M | #ifndef CAPSTONE_DIET |
163 | 1.90M | if (!MI->flat_insn->detail) |
164 | 0 | return; |
165 | | |
166 | 1.90M | cs_detail *detail = MI->flat_insn->detail; |
167 | 1.90M | unsigned Opcode = MCInst_getOpcode(MI); |
168 | 1.90M | unsigned i = 0; |
169 | 1.90M | uint16_t reg = imap[Opcode].regs_mod[i]; |
170 | 2.21M | while (reg != 0) { |
171 | 318k | if (i >= MAX_IMPL_W_REGS || |
172 | 318k | detail->regs_write_count >= MAX_IMPL_W_REGS) { |
173 | 0 | printf("ERROR: Too many implicit write register defined in " |
174 | 0 | "instruction mapping.\n"); |
175 | 0 | return; |
176 | 0 | } |
177 | 318k | detail->regs_write[detail->regs_write_count++] = reg; |
178 | 318k | reg = imap[Opcode].regs_mod[++i]; |
179 | 318k | } |
180 | 1.90M | #endif // CAPSTONE_DIET |
181 | 1.90M | } |
182 | | |
183 | | /// Adds a given group to @MI->flat_insn. |
184 | | /// A group is never added twice. |
185 | | void add_group(MCInst *MI, unsigned /* arch_group */ group) |
186 | 71.5k | { |
187 | 71.5k | #ifndef CAPSTONE_DIET |
188 | 71.5k | if (!MI->flat_insn->detail) |
189 | 0 | return; |
190 | | |
191 | 71.5k | cs_detail *detail = MI->flat_insn->detail; |
192 | 71.5k | if (detail->groups_count >= MAX_NUM_GROUPS) { |
193 | 0 | printf("ERROR: Too many groups defined.\n"); |
194 | 0 | return; |
195 | 0 | } |
196 | 185k | for (int i = 0; i < detail->groups_count; ++i) { |
197 | 114k | if (detail->groups[i] == group) { |
198 | 124 | return; |
199 | 124 | } |
200 | 114k | } |
201 | 71.3k | detail->groups[detail->groups_count++] = group; |
202 | 71.3k | #endif // CAPSTONE_DIET |
203 | 71.3k | } |
204 | | |
205 | | /// Copies the groups from @imap to @MI->flat_insn. |
206 | | /// Already present groups will be preserved. |
207 | | void map_groups(MCInst *MI, const insn_map *imap) |
208 | 1.90M | { |
209 | 1.90M | #ifndef CAPSTONE_DIET |
210 | 1.90M | if (!MI->flat_insn->detail) |
211 | 0 | return; |
212 | | |
213 | 1.90M | cs_detail *detail = MI->flat_insn->detail; |
214 | 1.90M | unsigned Opcode = MCInst_getOpcode(MI); |
215 | 1.90M | unsigned i = 0; |
216 | 1.90M | uint16_t group = imap[Opcode].groups[i]; |
217 | 3.95M | while (group != 0) { |
218 | 2.05M | if (detail->groups_count >= MAX_NUM_GROUPS) { |
219 | 0 | printf("ERROR: Too many groups defined in instruction mapping.\n"); |
220 | 0 | return; |
221 | 0 | } |
222 | 2.05M | detail->groups[detail->groups_count++] = group; |
223 | 2.05M | group = imap[Opcode].groups[++i]; |
224 | 2.05M | } |
225 | 1.90M | #endif // CAPSTONE_DIET |
226 | 1.90M | } |
227 | | |
228 | | /// Returns the pointer to the supllementary information in |
229 | | /// the instruction mapping table @imap or NULL in case of failure. |
230 | | const void *map_get_suppl_info(MCInst *MI, const insn_map *imap) |
231 | 70.7k | { |
232 | 70.7k | #ifndef CAPSTONE_DIET |
233 | 70.7k | if (!MI->flat_insn->detail) |
234 | 0 | return NULL; |
235 | | |
236 | 70.7k | unsigned Opcode = MCInst_getOpcode(MI); |
237 | 70.7k | return &imap[Opcode].suppl_info; |
238 | | #else |
239 | | return NULL; |
240 | | #endif // CAPSTONE_DIET |
241 | 70.7k | } |
242 | | |
243 | | // Search for the CS instruction id for the given @MC_Opcode in @imap. |
244 | | // return -1 if none is found. |
245 | | unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap, |
246 | | unsigned imap_size) |
247 | 1.90M | { |
248 | | // binary searching since the IDs are sorted in order |
249 | 1.90M | unsigned int left, right, m; |
250 | 1.90M | unsigned int max = imap_size; |
251 | | |
252 | 1.90M | right = max - 1; |
253 | | |
254 | 1.90M | if (MC_Opcode < imap[0].id || MC_Opcode > imap[right].id) |
255 | | // not found |
256 | 0 | return -1; |
257 | | |
258 | 1.90M | left = 0; |
259 | | |
260 | 21.6M | while (left <= right) { |
261 | 21.6M | m = (left + right) / 2; |
262 | 21.6M | if (MC_Opcode == imap[m].id) { |
263 | 1.90M | return m; |
264 | 1.90M | } |
265 | | |
266 | 19.7M | if (MC_Opcode < imap[m].id) |
267 | 6.25M | right = m - 1; |
268 | 13.4M | else |
269 | 13.4M | left = m + 1; |
270 | 19.7M | } |
271 | | |
272 | 0 | return -1; |
273 | 1.90M | } |
274 | | |
275 | | /// Sets the Capstone instruction id which maps to the @MI opcode. |
276 | | /// If no mapping is found the function returns and prints an error. |
277 | | void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size) |
278 | 1.90M | { |
279 | 1.90M | unsigned int i = find_cs_id(MCInst_getOpcode(MI), imap, imap_size); |
280 | 1.90M | if (i != -1) { |
281 | 1.90M | MI->flat_insn->id = imap[i].mapid; |
282 | 1.90M | return; |
283 | 1.90M | } |
284 | 0 | printf("ERROR: Could not find CS id for MCInst opcode: %d\n", |
285 | 0 | MCInst_getOpcode(MI)); |
286 | 0 | return; |
287 | 1.90M | } |
288 | | |
289 | | /// Returns the operand type information from the |
290 | | /// mapping table for instruction operands. |
291 | | /// Only usable by `auto-sync` archs! |
292 | | const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum, |
293 | | const map_insn_ops *insn_ops_map, |
294 | | size_t map_size) |
295 | 17.5M | { |
296 | 17.5M | assert(MI); |
297 | 17.5M | assert(MI->Opcode < map_size); |
298 | 17.5M | assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) / |
299 | 17.5M | sizeof(insn_ops_map[MI->Opcode].ops[0])); |
300 | | |
301 | 17.5M | return insn_ops_map[MI->Opcode].ops[OpNum].type; |
302 | 17.5M | } |
303 | | |
304 | | /// Returns the operand access flags from the |
305 | | /// mapping table for instruction operands. |
306 | | /// Only usable by `auto-sync` archs! |
307 | | const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum, |
308 | | const map_insn_ops *insn_ops_map, |
309 | | size_t map_size) |
310 | 5.75M | { |
311 | 5.75M | assert(MI); |
312 | 5.75M | assert(MI->Opcode < map_size); |
313 | 5.75M | assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) / |
314 | 5.75M | sizeof(insn_ops_map[MI->Opcode].ops[0])); |
315 | | |
316 | 5.75M | cs_ac_type access = insn_ops_map[MI->Opcode].ops[OpNum].access; |
317 | 5.75M | if (MCInst_opIsTied(MI, OpNum) || MCInst_opIsTying(MI, OpNum)) |
318 | 515k | access |= (access == CS_AC_READ) ? CS_AC_WRITE : CS_AC_READ; |
319 | 5.75M | return access; |
320 | 5.75M | } |
321 | | |
322 | | /// Returns the operand at detail->arch.operands[op_count + offset] |
323 | | /// Or NULL if detail is not set. |
324 | | #define DEFINE_get_detail_op(arch, ARCH) \ |
325 | | cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset) \ |
326 | 23.5M | { \ |
327 | 23.5M | if (!MI->flat_insn->detail) \ |
328 | 23.5M | return NULL; \ |
329 | 23.5M | int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \ |
330 | 23.5M | assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \ |
331 | 23.5M | return &MI->flat_insn->detail->arch.operands[OpIdx]; \ |
332 | 23.5M | } Line | Count | Source | 326 | 16.2M | { \ | 327 | 16.2M | if (!MI->flat_insn->detail) \ | 328 | 16.2M | return NULL; \ | 329 | 16.2M | int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \ | 330 | 16.2M | assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \ | 331 | 16.2M | return &MI->flat_insn->detail->arch.operands[OpIdx]; \ | 332 | 16.2M | } |
Line | Count | Source | 326 | 767k | { \ | 327 | 767k | if (!MI->flat_insn->detail) \ | 328 | 767k | return NULL; \ | 329 | 767k | int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \ | 330 | 767k | assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \ | 331 | 767k | return &MI->flat_insn->detail->arch.operands[OpIdx]; \ | 332 | 767k | } |
Unexecuted instantiation: TriCore_get_detail_op Line | Count | Source | 326 | 6.02M | { \ | 327 | 6.02M | if (!MI->flat_insn->detail) \ | 328 | 6.02M | return NULL; \ | 329 | 6.02M | int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \ | 330 | 6.02M | assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \ | 331 | 6.02M | return &MI->flat_insn->detail->arch.operands[OpIdx]; \ | 332 | 6.02M | } |
Unexecuted instantiation: Alpha_get_detail_op Unexecuted instantiation: HPPA_get_detail_op Unexecuted instantiation: LoongArch_get_detail_op Line | Count | Source | 326 | 525k | { \ | 327 | 525k | if (!MI->flat_insn->detail) \ | 328 | 525k | return NULL; \ | 329 | 525k | int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \ | 330 | 525k | assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \ | 331 | 525k | return &MI->flat_insn->detail->arch.operands[OpIdx]; \ | 332 | 525k | } |
|
333 | | |
334 | | DEFINE_get_detail_op(arm, ARM); |
335 | | DEFINE_get_detail_op(ppc, PPC); |
336 | | DEFINE_get_detail_op(tricore, TriCore); |
337 | | DEFINE_get_detail_op(aarch64, AArch64); |
338 | | DEFINE_get_detail_op(alpha, Alpha); |
339 | | DEFINE_get_detail_op(hppa, HPPA); |
340 | | DEFINE_get_detail_op(loongarch, LoongArch); |
341 | | DEFINE_get_detail_op(riscv, RISCV); |
342 | | |
343 | | /// Returns true if for this architecture the |
344 | | /// alias operands should be filled. |
345 | | /// TODO: Replace this with a proper option. |
346 | | /// So it can be toggled between disas() calls. |
347 | 3.76M | bool map_use_alias_details(const MCInst *MI) { |
348 | 3.76M | assert(MI); |
349 | 3.76M | return !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL); |
350 | 3.76M | } |
351 | | |
352 | | /// Sets the setDetailOps flag to @p Val. |
353 | | /// If detail == NULLit refuses to set the flag to true. |
354 | 3.70M | void map_set_fill_detail_ops(MCInst *MI, bool Val) { |
355 | 3.70M | assert(MI); |
356 | 3.70M | if (!detail_is_set(MI)) { |
357 | 0 | MI->fillDetailOps = false; |
358 | 0 | return; |
359 | 0 | } |
360 | | |
361 | 3.70M | MI->fillDetailOps = Val; |
362 | 3.70M | } |
363 | | |
364 | | /// Sets the instruction alias flags and the given alias id. |
365 | 0 | void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias) { |
366 | 0 | assert(MI); |
367 | 0 | MI->isAliasInstr = Val; |
368 | 0 | MI->flat_insn->is_alias = Val; |
369 | 0 | MI->flat_insn->alias_id = Alias; |
370 | 0 | } |
371 | | |
372 | 314k | static inline bool char_ends_mnem(const char c) { |
373 | 314k | return (!c || c == ' ' || c == '\t'); |
374 | 314k | } |
375 | | |
376 | | /// Sets an alternative id for some instruction. |
377 | | /// Or -1 if it fails. |
378 | | /// You must add (<ARCH>_INS_ALIAS_BEGIN + 1) to the id to get the real id. |
379 | 1.88M | void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size) { |
380 | 1.88M | if (!MCInst_isAlias(MI)) |
381 | 1.81M | return; |
382 | | |
383 | 65.0k | char alias_mnem[16] = { 0 }; |
384 | 65.0k | int i = 0, j = 0; |
385 | 65.0k | const char *asm_str_buf = O->buffer; |
386 | | // Skip spaces and tabs |
387 | 89.6k | while (is_blank_char(asm_str_buf[i])) { |
388 | 24.5k | if (!asm_str_buf[i]) { |
389 | 0 | MI->flat_insn->alias_id = -1; |
390 | 0 | return; |
391 | 0 | } |
392 | 24.5k | ++i; |
393 | 24.5k | } |
394 | 314k | for (; j < sizeof(alias_mnem) - 1; ++j, ++i) { |
395 | 314k | if (char_ends_mnem(asm_str_buf[i])) |
396 | 65.0k | break; |
397 | 249k | alias_mnem[j] = asm_str_buf[i]; |
398 | 249k | } |
399 | | |
400 | 65.0k | MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem); |
401 | 65.0k | } |
402 | | |