/src/capstonenext/arch/AArch64/AArch64AddressingModes.h
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1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This file contains the AArch64 addressing mode implementation stuff. |
24 | | // |
25 | | //===----------------------------------------------------------------------===// |
26 | | |
27 | | #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H |
28 | | #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H |
29 | | |
30 | | #include <stdio.h> |
31 | | #include <string.h> |
32 | | #include <stdlib.h> |
33 | | #include <capstone/platform.h> |
34 | | |
35 | | #include "../../MathExtras.h" |
36 | | #include <assert.h> |
37 | | #include "../../MathExtras.h" |
38 | | |
39 | 26.3k | #define CONCAT(a, b) CONCAT_(a, b) |
40 | 26.3k | #define CONCAT_(a, b) a##_##b |
41 | | |
42 | | /// AArch64_AM - AArch64 Addressing Mode Stuff |
43 | | // CS namespace begin: AArch64_AM |
44 | | |
45 | | //===----------------------------------------------------------------------===// |
46 | | // Shifts |
47 | | // |
48 | | typedef enum ShiftExtendType { |
49 | | AArch64_AM_InvalidShiftExtend = -1, |
50 | | AArch64_AM_LSL = 0, |
51 | | AArch64_AM_LSR, |
52 | | AArch64_AM_ASR, |
53 | | AArch64_AM_ROR, |
54 | | AArch64_AM_MSL, |
55 | | |
56 | | AArch64_AM_UXTB, |
57 | | AArch64_AM_UXTH, |
58 | | AArch64_AM_UXTW, |
59 | | AArch64_AM_UXTX, |
60 | | |
61 | | AArch64_AM_SXTB, |
62 | | AArch64_AM_SXTH, |
63 | | AArch64_AM_SXTW, |
64 | | AArch64_AM_SXTX, |
65 | | } AArch64_AM_ShiftExtendType; |
66 | | |
67 | | /// getShiftName - Get the string encoding for the shift type. |
68 | | static inline const char * |
69 | | AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) |
70 | 15.7k | { |
71 | 15.7k | switch (ST) { |
72 | 0 | default: |
73 | 0 | assert(0 && "unhandled shift type!"); |
74 | 5.88k | case AArch64_AM_LSL: |
75 | 5.88k | return "lsl"; |
76 | 2.26k | case AArch64_AM_LSR: |
77 | 2.26k | return "lsr"; |
78 | 3.38k | case AArch64_AM_ASR: |
79 | 3.38k | return "asr"; |
80 | 1.54k | case AArch64_AM_ROR: |
81 | 1.54k | return "ror"; |
82 | 1.21k | case AArch64_AM_MSL: |
83 | 1.21k | return "msl"; |
84 | 159 | case AArch64_AM_UXTB: |
85 | 159 | return "uxtb"; |
86 | 397 | case AArch64_AM_UXTH: |
87 | 397 | return "uxth"; |
88 | 154 | case AArch64_AM_UXTW: |
89 | 154 | return "uxtw"; |
90 | 446 | case AArch64_AM_UXTX: |
91 | 446 | return "uxtx"; |
92 | 71 | case AArch64_AM_SXTB: |
93 | 71 | return "sxtb"; |
94 | 59 | case AArch64_AM_SXTH: |
95 | 59 | return "sxth"; |
96 | 60 | case AArch64_AM_SXTW: |
97 | 60 | return "sxtw"; |
98 | 92 | case AArch64_AM_SXTX: |
99 | 92 | return "sxtx"; |
100 | 15.7k | } |
101 | 0 | return NULL; |
102 | 15.7k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getShiftExtendName Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getShiftExtendName Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getShiftExtendName AArch64InstPrinter.c:AArch64_AM_getShiftExtendName Line | Count | Source | 70 | 15.7k | { | 71 | 15.7k | switch (ST) { | 72 | 0 | default: | 73 | 0 | assert(0 && "unhandled shift type!"); | 74 | 5.88k | case AArch64_AM_LSL: | 75 | 5.88k | return "lsl"; | 76 | 2.26k | case AArch64_AM_LSR: | 77 | 2.26k | return "lsr"; | 78 | 3.38k | case AArch64_AM_ASR: | 79 | 3.38k | return "asr"; | 80 | 1.54k | case AArch64_AM_ROR: | 81 | 1.54k | return "ror"; | 82 | 1.21k | case AArch64_AM_MSL: | 83 | 1.21k | return "msl"; | 84 | 159 | case AArch64_AM_UXTB: | 85 | 159 | return "uxtb"; | 86 | 397 | case AArch64_AM_UXTH: | 87 | 397 | return "uxth"; | 88 | 154 | case AArch64_AM_UXTW: | 89 | 154 | return "uxtw"; | 90 | 446 | case AArch64_AM_UXTX: | 91 | 446 | return "uxtx"; | 92 | 71 | case AArch64_AM_SXTB: | 93 | 71 | return "sxtb"; | 94 | 59 | case AArch64_AM_SXTH: | 95 | 59 | return "sxth"; | 96 | 60 | case AArch64_AM_SXTW: | 97 | 60 | return "sxtw"; | 98 | 92 | case AArch64_AM_SXTX: | 99 | 92 | return "sxtx"; | 100 | 15.7k | } | 101 | 0 | return NULL; | 102 | 15.7k | } |
|
103 | | |
104 | | /// getShiftType - Extract the shift type. |
105 | | static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) |
106 | 63.9k | { |
107 | 63.9k | switch ((Imm >> 6) & 0x7) { |
108 | 0 | default: |
109 | 0 | return AArch64_AM_InvalidShiftExtend; |
110 | 28.0k | case 0: |
111 | 28.0k | return AArch64_AM_LSL; |
112 | 9.49k | case 1: |
113 | 9.49k | return AArch64_AM_LSR; |
114 | 15.7k | case 2: |
115 | 15.7k | return AArch64_AM_ASR; |
116 | 6.50k | case 3: |
117 | 6.50k | return AArch64_AM_ROR; |
118 | 4.23k | case 4: |
119 | 4.23k | return AArch64_AM_MSL; |
120 | 63.9k | } |
121 | 63.9k | } AArch64Mapping.c:AArch64_AM_getShiftType Line | Count | Source | 106 | 14.8k | { | 107 | 14.8k | switch ((Imm >> 6) & 0x7) { | 108 | 0 | default: | 109 | 0 | return AArch64_AM_InvalidShiftExtend; | 110 | 6.41k | case 0: | 111 | 6.41k | return AArch64_AM_LSL; | 112 | 2.26k | case 1: | 113 | 2.26k | return AArch64_AM_LSR; | 114 | 3.38k | case 2: | 115 | 3.38k | return AArch64_AM_ASR; | 116 | 1.54k | case 3: | 117 | 1.54k | return AArch64_AM_ROR; | 118 | 1.21k | case 4: | 119 | 1.21k | return AArch64_AM_MSL; | 120 | 14.8k | } | 121 | 14.8k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getShiftType Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getShiftType AArch64InstPrinter.c:AArch64_AM_getShiftType Line | Count | Source | 106 | 49.1k | { | 107 | 49.1k | switch ((Imm >> 6) & 0x7) { | 108 | 0 | default: | 109 | 0 | return AArch64_AM_InvalidShiftExtend; | 110 | 21.5k | case 0: | 111 | 21.5k | return AArch64_AM_LSL; | 112 | 7.22k | case 1: | 113 | 7.22k | return AArch64_AM_LSR; | 114 | 12.3k | case 2: | 115 | 12.3k | return AArch64_AM_ASR; | 116 | 4.95k | case 3: | 117 | 4.95k | return AArch64_AM_ROR; | 118 | 3.02k | case 4: | 119 | 3.02k | return AArch64_AM_MSL; | 120 | 49.1k | } | 121 | 49.1k | } |
|
122 | | |
123 | | /// getShiftValue - Extract the shift value. |
124 | | static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) |
125 | 66.9k | { |
126 | 66.9k | return Imm & 0x3f; |
127 | 66.9k | } AArch64Mapping.c:AArch64_AM_getShiftValue Line | Count | Source | 125 | 19.2k | { | 126 | 19.2k | return Imm & 0x3f; | 127 | 19.2k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getShiftValue Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getShiftValue AArch64InstPrinter.c:AArch64_AM_getShiftValue Line | Count | Source | 125 | 47.6k | { | 126 | 47.6k | return Imm & 0x3f; | 127 | 47.6k | } |
|
128 | | |
129 | | /// getShifterImm - Encode the shift type and amount: |
130 | | /// imm: 6-bit shift amount |
131 | | /// shifter: 000 ==> lsl |
132 | | /// 001 ==> lsr |
133 | | /// 010 ==> asr |
134 | | /// 011 ==> ror |
135 | | /// 100 ==> msl |
136 | | /// {8-6} = shifter |
137 | | /// {5-0} = imm |
138 | | static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, |
139 | | unsigned Imm) |
140 | 0 | { |
141 | 0 | unsigned STEnc = 0; |
142 | 0 | switch (ST) { |
143 | 0 | default: |
144 | 0 | assert(0 && "Invalid shift requested"); |
145 | 0 | case AArch64_AM_LSL: |
146 | 0 | STEnc = 0; |
147 | 0 | break; |
148 | 0 | case AArch64_AM_LSR: |
149 | 0 | STEnc = 1; |
150 | 0 | break; |
151 | 0 | case AArch64_AM_ASR: |
152 | 0 | STEnc = 2; |
153 | 0 | break; |
154 | 0 | case AArch64_AM_ROR: |
155 | 0 | STEnc = 3; |
156 | 0 | break; |
157 | 0 | case AArch64_AM_MSL: |
158 | 0 | STEnc = 4; |
159 | 0 | break; |
160 | 0 | } |
161 | 0 | return (STEnc << 6) | (Imm & 0x3f); |
162 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getShifterImm Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getShifterImm Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getShifterImm Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getShifterImm |
163 | | |
164 | | //===----------------------------------------------------------------------===// |
165 | | // Extends |
166 | | // |
167 | | /// getArithShiftValue - get the arithmetic shift value. |
168 | | static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) |
169 | 4.72k | { |
170 | 4.72k | return Imm & 0x7; |
171 | 4.72k | } AArch64Mapping.c:AArch64_AM_getArithShiftValue Line | Count | Source | 169 | 1.74k | { | 170 | 1.74k | return Imm & 0x7; | 171 | 1.74k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getArithShiftValue Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getArithShiftValue AArch64InstPrinter.c:AArch64_AM_getArithShiftValue Line | Count | Source | 169 | 2.98k | { | 170 | 2.98k | return Imm & 0x7; | 171 | 2.98k | } |
|
172 | | |
173 | | /// getExtendType - Extract the extend type for operands of arithmetic ops. |
174 | | static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) |
175 | 3.48k | { |
176 | 3.48k | switch (Imm) { |
177 | 0 | default: |
178 | 0 | assert(0 && "Compiler bug!"); |
179 | 318 | case 0: |
180 | 318 | return AArch64_AM_UXTB; |
181 | 794 | case 1: |
182 | 794 | return AArch64_AM_UXTH; |
183 | 884 | case 2: |
184 | 884 | return AArch64_AM_UXTW; |
185 | 922 | case 3: |
186 | 922 | return AArch64_AM_UXTX; |
187 | 142 | case 4: |
188 | 142 | return AArch64_AM_SXTB; |
189 | 118 | case 5: |
190 | 118 | return AArch64_AM_SXTH; |
191 | 120 | case 6: |
192 | 120 | return AArch64_AM_SXTW; |
193 | 184 | case 7: |
194 | 184 | return AArch64_AM_SXTX; |
195 | 3.48k | } |
196 | 3.48k | } AArch64Mapping.c:AArch64_AM_getExtendType Line | Count | Source | 175 | 1.74k | { | 176 | 1.74k | switch (Imm) { | 177 | 0 | default: | 178 | 0 | assert(0 && "Compiler bug!"); | 179 | 159 | case 0: | 180 | 159 | return AArch64_AM_UXTB; | 181 | 397 | case 1: | 182 | 397 | return AArch64_AM_UXTH; | 183 | 442 | case 2: | 184 | 442 | return AArch64_AM_UXTW; | 185 | 461 | case 3: | 186 | 461 | return AArch64_AM_UXTX; | 187 | 71 | case 4: | 188 | 71 | return AArch64_AM_SXTB; | 189 | 59 | case 5: | 190 | 59 | return AArch64_AM_SXTH; | 191 | 60 | case 6: | 192 | 60 | return AArch64_AM_SXTW; | 193 | 92 | case 7: | 194 | 92 | return AArch64_AM_SXTX; | 195 | 1.74k | } | 196 | 1.74k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getExtendType Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getExtendType AArch64InstPrinter.c:AArch64_AM_getExtendType Line | Count | Source | 175 | 1.74k | { | 176 | 1.74k | switch (Imm) { | 177 | 0 | default: | 178 | 0 | assert(0 && "Compiler bug!"); | 179 | 159 | case 0: | 180 | 159 | return AArch64_AM_UXTB; | 181 | 397 | case 1: | 182 | 397 | return AArch64_AM_UXTH; | 183 | 442 | case 2: | 184 | 442 | return AArch64_AM_UXTW; | 185 | 461 | case 3: | 186 | 461 | return AArch64_AM_UXTX; | 187 | 71 | case 4: | 188 | 71 | return AArch64_AM_SXTB; | 189 | 59 | case 5: | 190 | 59 | return AArch64_AM_SXTH; | 191 | 60 | case 6: | 192 | 60 | return AArch64_AM_SXTW; | 193 | 92 | case 7: | 194 | 92 | return AArch64_AM_SXTX; | 195 | 1.74k | } | 196 | 1.74k | } |
|
197 | | |
198 | | static inline AArch64_AM_ShiftExtendType |
199 | | AArch64_AM_getArithExtendType(unsigned Imm) |
200 | 4.72k | { |
201 | 4.72k | return AArch64_AM_getExtendType((Imm >> 3) & 0x7); |
202 | 4.72k | } AArch64Mapping.c:AArch64_AM_getArithExtendType Line | Count | Source | 200 | 1.74k | { | 201 | 1.74k | return AArch64_AM_getExtendType((Imm >> 3) & 0x7); | 202 | 1.74k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getArithExtendType Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getArithExtendType AArch64InstPrinter.c:AArch64_AM_getArithExtendType Line | Count | Source | 200 | 2.98k | { | 201 | 2.98k | return AArch64_AM_getExtendType((Imm >> 3) & 0x7); | 202 | 2.98k | } |
|
203 | | |
204 | | /// Mapping from extend bits to required operation: |
205 | | /// shifter: 000 ==> uxtb |
206 | | /// 001 ==> uxth |
207 | | /// 010 ==> uxtw |
208 | | /// 011 ==> uxtx |
209 | | /// 100 ==> sxtb |
210 | | /// 101 ==> sxth |
211 | | /// 110 ==> sxtw |
212 | | /// 111 ==> sxtx |
213 | | static inline unsigned |
214 | | AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET) |
215 | 0 | { |
216 | 0 | switch (ET) { |
217 | 0 | default: |
218 | 0 | assert(0 && "Invalid extend type requested"); |
219 | 0 | case AArch64_AM_UXTB: |
220 | 0 | return 0; |
221 | 0 | break; |
222 | 0 | case AArch64_AM_UXTH: |
223 | 0 | return 1; |
224 | 0 | break; |
225 | 0 | case AArch64_AM_UXTW: |
226 | 0 | return 2; |
227 | 0 | break; |
228 | 0 | case AArch64_AM_UXTX: |
229 | 0 | return 3; |
230 | 0 | break; |
231 | 0 | case AArch64_AM_SXTB: |
232 | 0 | return 4; |
233 | 0 | break; |
234 | 0 | case AArch64_AM_SXTH: |
235 | 0 | return 5; |
236 | 0 | break; |
237 | 0 | case AArch64_AM_SXTW: |
238 | 0 | return 6; |
239 | 0 | break; |
240 | 0 | case AArch64_AM_SXTX: |
241 | 0 | return 7; |
242 | 0 | break; |
243 | 0 | } |
244 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getExtendEncoding Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getExtendEncoding Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getExtendEncoding Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getExtendEncoding |
245 | | |
246 | | /// getArithExtendImm - Encode the extend type and shift amount for an |
247 | | /// arithmetic instruction: |
248 | | /// imm: 3-bit extend amount |
249 | | /// {5-3} = shifter |
250 | | /// {2-0} = imm3 |
251 | | static inline unsigned |
252 | | AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm) |
253 | 0 | { |
254 | 0 | return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7); |
255 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getArithExtendImm Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getArithExtendImm Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getArithExtendImm Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getArithExtendImm |
256 | | |
257 | | /// getMemDoShift - Extract the "do shift" flag value for load/store |
258 | | /// instructions. |
259 | | static inline bool AArch64_AM_getMemDoShift(unsigned Imm) |
260 | 0 | { |
261 | 0 | return (Imm & 0x1) != 0; |
262 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getMemDoShift Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getMemDoShift Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getMemDoShift Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getMemDoShift |
263 | | |
264 | | /// getExtendType - Extract the extend type for the offset operand of |
265 | | /// loads/stores. |
266 | | static inline AArch64_AM_ShiftExtendType |
267 | | AArch64_AM_getMemExtendType(unsigned Imm) |
268 | 0 | { |
269 | 0 | return AArch64_AM_getExtendType((Imm >> 1) & 0x7); |
270 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getMemExtendType Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getMemExtendType Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getMemExtendType Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getMemExtendType |
271 | | |
272 | | /// getExtendImm - Encode the extend type and amount for a load/store inst: |
273 | | /// doshift: should the offset be scaled by the access size |
274 | | /// shifter: 000 ==> uxtb |
275 | | /// 001 ==> uxth |
276 | | /// 010 ==> uxtw |
277 | | /// 011 ==> uxtx |
278 | | /// 100 ==> sxtb |
279 | | /// 101 ==> sxth |
280 | | /// 110 ==> sxtw |
281 | | /// 111 ==> sxtx |
282 | | /// {3-1} = shifter |
283 | | /// {0} = doshift |
284 | | static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET, |
285 | | bool DoShift) |
286 | 0 | { |
287 | 0 | return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift; |
288 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_getMemExtendImm Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getMemExtendImm Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getMemExtendImm Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_getMemExtendImm |
289 | | |
290 | | static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size) |
291 | 538k | { |
292 | 538k | return ((elt & 1) << (size - 1)) | (elt >> 1); |
293 | 538k | } AArch64Mapping.c:AArch64_AM_ror Line | Count | Source | 291 | 138k | { | 292 | 138k | return ((elt & 1) << (size - 1)) | (elt >> 1); | 293 | 138k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_ror Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_ror AArch64InstPrinter.c:AArch64_AM_ror Line | Count | Source | 291 | 399k | { | 292 | 399k | return ((elt & 1) << (size - 1)) | (elt >> 1); | 293 | 399k | } |
|
294 | | |
295 | | /// processLogicalImmediate - Determine if an immediate value can be encoded |
296 | | /// as the immediate operand of a logical instruction for the given register |
297 | | /// size. If so, return true with "encoding" set to the encoded value in |
298 | | /// the form N:immr:imms. |
299 | | static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, |
300 | | unsigned RegSize, |
301 | | uint64_t *Encoding) |
302 | 5.18k | { |
303 | 5.18k | if (Imm == 0ULL || Imm == ~0ULL || |
304 | 5.18k | (RegSize != 64 && |
305 | 5.18k | (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) |
306 | 0 | return false; |
307 | | |
308 | | // First, determine the element size. |
309 | 5.18k | unsigned Size = RegSize; |
310 | | |
311 | 9.41k | do { |
312 | 9.41k | Size /= 2; |
313 | 9.41k | uint64_t Mask = (1ULL << Size) - 1; |
314 | | |
315 | 9.41k | if ((Imm & Mask) != ((Imm >> Size) & Mask)) { |
316 | 5.18k | Size *= 2; |
317 | 5.18k | break; |
318 | 5.18k | } |
319 | 9.41k | } while (Size > 2); |
320 | | |
321 | | // Second, determine the rotation to make the element be: 0^m 1^n. |
322 | 0 | uint32_t CTO, I; |
323 | 5.18k | uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size); |
324 | 5.18k | Imm &= Mask; |
325 | | |
326 | 5.18k | if (isShiftedMask_64(Imm)) { |
327 | 3.81k | I = CountTrailingZeros_64(Imm); |
328 | | |
329 | 3.81k | CTO = CountTrailingOnes_64(Imm >> I); |
330 | 3.81k | } else { |
331 | 1.37k | Imm |= ~Mask; |
332 | 1.37k | if (!isShiftedMask_64(~Imm)) |
333 | 0 | return false; |
334 | | |
335 | 1.37k | unsigned CLO = CountLeadingOnes_64(Imm); |
336 | 1.37k | I = 64 - CLO; |
337 | 1.37k | CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size); |
338 | 1.37k | } |
339 | | |
340 | | // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n |
341 | | // to our target value, where I is the number of RORs to go the opposite |
342 | | // direction. |
343 | | |
344 | 5.18k | unsigned Immr = (Size - I) & (Size - 1); |
345 | | |
346 | | // If size has a 1 in the n'th bit, create a value that has zeroes in |
347 | | // bits [0, n] and ones above that. |
348 | 5.18k | uint64_t NImms = ~(Size - 1) << 1; |
349 | | |
350 | | // Or the CTO value into the low bits, which must be below the Nth bit |
351 | | // bit mentioned above. |
352 | 5.18k | NImms |= (CTO - 1); |
353 | | |
354 | | // Extract the seventh bit and toggle it to create the N field. |
355 | 5.18k | unsigned N = ((NImms >> 6) & 1) ^ 1; |
356 | | |
357 | 5.18k | *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); |
358 | 5.18k | return true; |
359 | 5.18k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_processLogicalImmediate Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_processLogicalImmediate Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_processLogicalImmediate AArch64InstPrinter.c:AArch64_AM_processLogicalImmediate Line | Count | Source | 302 | 5.18k | { | 303 | 5.18k | if (Imm == 0ULL || Imm == ~0ULL || | 304 | 5.18k | (RegSize != 64 && | 305 | 5.18k | (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) | 306 | 0 | return false; | 307 | | | 308 | | // First, determine the element size. | 309 | 5.18k | unsigned Size = RegSize; | 310 | | | 311 | 9.41k | do { | 312 | 9.41k | Size /= 2; | 313 | 9.41k | uint64_t Mask = (1ULL << Size) - 1; | 314 | | | 315 | 9.41k | if ((Imm & Mask) != ((Imm >> Size) & Mask)) { | 316 | 5.18k | Size *= 2; | 317 | 5.18k | break; | 318 | 5.18k | } | 319 | 9.41k | } while (Size > 2); | 320 | | | 321 | | // Second, determine the rotation to make the element be: 0^m 1^n. | 322 | 0 | uint32_t CTO, I; | 323 | 5.18k | uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size); | 324 | 5.18k | Imm &= Mask; | 325 | | | 326 | 5.18k | if (isShiftedMask_64(Imm)) { | 327 | 3.81k | I = CountTrailingZeros_64(Imm); | 328 | | | 329 | 3.81k | CTO = CountTrailingOnes_64(Imm >> I); | 330 | 3.81k | } else { | 331 | 1.37k | Imm |= ~Mask; | 332 | 1.37k | if (!isShiftedMask_64(~Imm)) | 333 | 0 | return false; | 334 | | | 335 | 1.37k | unsigned CLO = CountLeadingOnes_64(Imm); | 336 | 1.37k | I = 64 - CLO; | 337 | 1.37k | CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size); | 338 | 1.37k | } | 339 | | | 340 | | // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n | 341 | | // to our target value, where I is the number of RORs to go the opposite | 342 | | // direction. | 343 | | | 344 | 5.18k | unsigned Immr = (Size - I) & (Size - 1); | 345 | | | 346 | | // If size has a 1 in the n'th bit, create a value that has zeroes in | 347 | | // bits [0, n] and ones above that. | 348 | 5.18k | uint64_t NImms = ~(Size - 1) << 1; | 349 | | | 350 | | // Or the CTO value into the low bits, which must be below the Nth bit | 351 | | // bit mentioned above. | 352 | 5.18k | NImms |= (CTO - 1); | 353 | | | 354 | | // Extract the seventh bit and toggle it to create the N field. | 355 | 5.18k | unsigned N = ((NImms >> 6) & 1) ^ 1; | 356 | | | 357 | 5.18k | *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); | 358 | 5.18k | return true; | 359 | 5.18k | } |
|
360 | | |
361 | | /// isLogicalImmediate - Return true if the immediate is valid for a logical |
362 | | /// immediate instruction of the given register size. Return false otherwise. |
363 | | static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize) |
364 | 2.81k | { |
365 | 2.81k | uint64_t encoding = 0; |
366 | 2.81k | return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); |
367 | 2.81k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isLogicalImmediate Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isLogicalImmediate Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isLogicalImmediate AArch64InstPrinter.c:AArch64_AM_isLogicalImmediate Line | Count | Source | 364 | 2.81k | { | 365 | 2.81k | uint64_t encoding = 0; | 366 | 2.81k | return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); | 367 | 2.81k | } |
|
368 | | |
369 | | /// encodeLogicalImmediate - Return the encoded immediate value for a logical |
370 | | /// immediate instruction of the given register size. |
371 | | static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, |
372 | | unsigned regSize) |
373 | 0 | { |
374 | 0 | uint64_t encoding = 0; |
375 | 0 | bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); |
376 | 0 |
|
377 | 0 | (void)res; |
378 | 0 | return encoding; |
379 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeLogicalImmediate Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeLogicalImmediate Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeLogicalImmediate Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeLogicalImmediate |
380 | | |
381 | | /// decodeLogicalImmediate - Decode a logical immediate value in the form |
382 | | /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the |
383 | | /// integer value it represents with regSize bits. |
384 | | static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, |
385 | | unsigned regSize) |
386 | 37.2k | { |
387 | | // Extract the N, imms, and immr fields. |
388 | 37.2k | unsigned N = (val >> 12) & 1; |
389 | 37.2k | unsigned immr = (val >> 6) & 0x3f; |
390 | 37.2k | unsigned imms = val & 0x3f; |
391 | | |
392 | 37.2k | int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); |
393 | 37.2k | assert(len >= 1); |
394 | | |
395 | 37.2k | unsigned size = (1 << len); |
396 | 37.2k | unsigned R = immr & (size - 1); |
397 | 37.2k | unsigned S = imms & (size - 1); |
398 | | |
399 | 37.2k | uint64_t pattern = (1ULL << (S + 1)) - 1; |
400 | 575k | for (unsigned i = 0; i < R; ++i) |
401 | 538k | pattern = AArch64_AM_ror(pattern, size); |
402 | | |
403 | | // Replicate the pattern to fill the regSize. |
404 | 72.6k | while (size != regSize) { |
405 | 35.3k | pattern |= (pattern << size); |
406 | 35.3k | size *= 2; |
407 | 35.3k | } |
408 | 37.2k | return pattern; |
409 | 37.2k | } AArch64Mapping.c:AArch64_AM_decodeLogicalImmediate Line | Count | Source | 386 | 10.1k | { | 387 | | // Extract the N, imms, and immr fields. | 388 | 10.1k | unsigned N = (val >> 12) & 1; | 389 | 10.1k | unsigned immr = (val >> 6) & 0x3f; | 390 | 10.1k | unsigned imms = val & 0x3f; | 391 | | | 392 | 10.1k | int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); | 393 | 10.1k | assert(len >= 1); | 394 | | | 395 | 10.1k | unsigned size = (1 << len); | 396 | 10.1k | unsigned R = immr & (size - 1); | 397 | 10.1k | unsigned S = imms & (size - 1); | 398 | | | 399 | 10.1k | uint64_t pattern = (1ULL << (S + 1)) - 1; | 400 | 148k | for (unsigned i = 0; i < R; ++i) | 401 | 138k | pattern = AArch64_AM_ror(pattern, size); | 402 | | | 403 | | // Replicate the pattern to fill the regSize. | 404 | 16.0k | while (size != regSize) { | 405 | 5.95k | pattern |= (pattern << size); | 406 | 5.95k | size *= 2; | 407 | 5.95k | } | 408 | 10.1k | return pattern; | 409 | 10.1k | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeLogicalImmediate Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeLogicalImmediate AArch64InstPrinter.c:AArch64_AM_decodeLogicalImmediate Line | Count | Source | 386 | 27.1k | { | 387 | | // Extract the N, imms, and immr fields. | 388 | 27.1k | unsigned N = (val >> 12) & 1; | 389 | 27.1k | unsigned immr = (val >> 6) & 0x3f; | 390 | 27.1k | unsigned imms = val & 0x3f; | 391 | | | 392 | 27.1k | int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); | 393 | 27.1k | assert(len >= 1); | 394 | | | 395 | 27.1k | unsigned size = (1 << len); | 396 | 27.1k | unsigned R = immr & (size - 1); | 397 | 27.1k | unsigned S = imms & (size - 1); | 398 | | | 399 | 27.1k | uint64_t pattern = (1ULL << (S + 1)) - 1; | 400 | 426k | for (unsigned i = 0; i < R; ++i) | 401 | 399k | pattern = AArch64_AM_ror(pattern, size); | 402 | | | 403 | | // Replicate the pattern to fill the regSize. | 404 | 56.6k | while (size != regSize) { | 405 | 29.4k | pattern |= (pattern << size); | 406 | 29.4k | size *= 2; | 407 | 29.4k | } | 408 | 27.1k | return pattern; | 409 | 27.1k | } |
|
410 | | |
411 | | /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value |
412 | | /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) |
413 | | /// is a valid encoding for an integer value with regSize bits. |
414 | | static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, |
415 | | unsigned regSize) |
416 | 17.7k | { |
417 | | // Extract the N and imms fields needed for checking. |
418 | 17.7k | unsigned N = (val >> 12) & 1; |
419 | 17.7k | unsigned imms = val & 0x3f; |
420 | | |
421 | 17.7k | if (regSize == 32 && N != 0) // undefined logical immediate encoding |
422 | 0 | return false; |
423 | 17.7k | int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); |
424 | 17.7k | if (len < 0) // undefined logical immediate encoding |
425 | 9 | return false; |
426 | 17.7k | unsigned size = (1 << len); |
427 | 17.7k | unsigned S = imms & (size - 1); |
428 | 17.7k | if (S == size - 1) // undefined logical immediate encoding |
429 | 16 | return false; |
430 | | |
431 | 17.7k | return true; |
432 | 17.7k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isValidDecodeLogicalImmediate AArch64Disassembler.c:AArch64_AM_isValidDecodeLogicalImmediate Line | Count | Source | 416 | 17.7k | { | 417 | | // Extract the N and imms fields needed for checking. | 418 | 17.7k | unsigned N = (val >> 12) & 1; | 419 | 17.7k | unsigned imms = val & 0x3f; | 420 | | | 421 | 17.7k | if (regSize == 32 && N != 0) // undefined logical immediate encoding | 422 | 0 | return false; | 423 | 17.7k | int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); | 424 | 17.7k | if (len < 0) // undefined logical immediate encoding | 425 | 9 | return false; | 426 | 17.7k | unsigned size = (1 << len); | 427 | 17.7k | unsigned S = imms & (size - 1); | 428 | 17.7k | if (S == size - 1) // undefined logical immediate encoding | 429 | 16 | return false; | 430 | | | 431 | 17.7k | return true; | 432 | 17.7k | } |
Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isValidDecodeLogicalImmediate Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isValidDecodeLogicalImmediate |
433 | | |
434 | | //===----------------------------------------------------------------------===// |
435 | | // Floating-point Immediates |
436 | | // |
437 | | static inline float AArch64_AM_getFPImmFloat(unsigned Imm) |
438 | 2.18k | { |
439 | | // We expect an 8-bit binary encoding of a floating-point number here. |
440 | | |
441 | 2.18k | uint8_t Sign = (Imm >> 7) & 0x1; |
442 | 2.18k | uint8_t Exp = (Imm >> 4) & 0x7; |
443 | 2.18k | uint8_t Mantissa = Imm & 0xf; |
444 | | |
445 | | // 8-bit FP IEEE Float Encoding |
446 | | // abcd efgh aBbbbbbc defgh000 00000000 00000000 |
447 | | // |
448 | | // where B = NOT(b); |
449 | | |
450 | 2.18k | uint32_t I = 0; |
451 | 2.18k | I |= Sign << 31; |
452 | 2.18k | I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; |
453 | 2.18k | I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; |
454 | 2.18k | I |= (Exp & 0x3) << 23; |
455 | 2.18k | I |= Mantissa << 19; |
456 | 2.18k | return BitsToFloat(I); |
457 | 2.18k | } AArch64Mapping.c:AArch64_AM_getFPImmFloat Line | Count | Source | 438 | 957 | { | 439 | | // We expect an 8-bit binary encoding of a floating-point number here. | 440 | | | 441 | 957 | uint8_t Sign = (Imm >> 7) & 0x1; | 442 | 957 | uint8_t Exp = (Imm >> 4) & 0x7; | 443 | 957 | uint8_t Mantissa = Imm & 0xf; | 444 | | | 445 | | // 8-bit FP IEEE Float Encoding | 446 | | // abcd efgh aBbbbbbc defgh000 00000000 00000000 | 447 | | // | 448 | | // where B = NOT(b); | 449 | | | 450 | 957 | uint32_t I = 0; | 451 | 957 | I |= Sign << 31; | 452 | 957 | I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; | 453 | 957 | I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; | 454 | 957 | I |= (Exp & 0x3) << 23; | 455 | 957 | I |= Mantissa << 19; | 456 | 957 | return BitsToFloat(I); | 457 | 957 | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_getFPImmFloat Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_getFPImmFloat AArch64InstPrinter.c:AArch64_AM_getFPImmFloat Line | Count | Source | 438 | 1.22k | { | 439 | | // We expect an 8-bit binary encoding of a floating-point number here. | 440 | | | 441 | 1.22k | uint8_t Sign = (Imm >> 7) & 0x1; | 442 | 1.22k | uint8_t Exp = (Imm >> 4) & 0x7; | 443 | 1.22k | uint8_t Mantissa = Imm & 0xf; | 444 | | | 445 | | // 8-bit FP IEEE Float Encoding | 446 | | // abcd efgh aBbbbbbc defgh000 00000000 00000000 | 447 | | // | 448 | | // where B = NOT(b); | 449 | | | 450 | 1.22k | uint32_t I = 0; | 451 | 1.22k | I |= Sign << 31; | 452 | 1.22k | I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; | 453 | 1.22k | I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; | 454 | 1.22k | I |= (Exp & 0x3) << 23; | 455 | 1.22k | I |= Mantissa << 19; | 456 | 1.22k | return BitsToFloat(I); | 457 | 1.22k | } |
|
458 | | |
459 | | //===--------------------------------------------------------------------===// |
460 | | // AdvSIMD Modified Immediates |
461 | | //===--------------------------------------------------------------------===// |
462 | | // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh |
463 | | static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm) |
464 | 0 | { |
465 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
466 | 0 | ((Imm & 0xffffff00ffffff00ULL) == 0); |
467 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType1 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType1 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType1 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType1 |
468 | | |
469 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) |
470 | 0 | { |
471 | 0 | return (Imm & 0xffULL); |
472 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType1 |
473 | | |
474 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) |
475 | 0 | { |
476 | 0 | uint64_t EncVal = Imm; |
477 | 0 | return (EncVal << 32) | EncVal; |
478 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType1 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType1 |
479 | | |
480 | | // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 |
481 | | static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm) |
482 | 0 | { |
483 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
484 | 0 | ((Imm & 0xffff00ffffff00ffULL) == 0); |
485 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType2 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType2 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType2 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType2 |
486 | | |
487 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm) |
488 | 0 | { |
489 | 0 | return (Imm & 0xff00ULL) >> 8; |
490 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType2 |
491 | | |
492 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm) |
493 | 0 | { |
494 | 0 | uint64_t EncVal = Imm; |
495 | 0 | return (EncVal << 40) | (EncVal << 8); |
496 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType2 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType2 |
497 | | |
498 | | // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 |
499 | | static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm) |
500 | 0 | { |
501 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
502 | 0 | ((Imm & 0xff00ffffff00ffffULL) == 0); |
503 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType3 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType3 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType3 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType3 |
504 | | |
505 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm) |
506 | 0 | { |
507 | 0 | return (Imm & 0xff0000ULL) >> 16; |
508 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType3 |
509 | | |
510 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm) |
511 | 0 | { |
512 | 0 | uint64_t EncVal = Imm; |
513 | 0 | return (EncVal << 48) | (EncVal << 16); |
514 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType3 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType3 |
515 | | |
516 | | // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 |
517 | | static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm) |
518 | 0 | { |
519 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
520 | 0 | ((Imm & 0x00ffffff00ffffffULL) == 0); |
521 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType4 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType4 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType4 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType4 |
522 | | |
523 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm) |
524 | 0 | { |
525 | 0 | return (Imm & 0xff000000ULL) >> 24; |
526 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType4 |
527 | | |
528 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm) |
529 | 0 | { |
530 | 0 | uint64_t EncVal = Imm; |
531 | 0 | return (EncVal << 56) | (EncVal << 24); |
532 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType4 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType4 |
533 | | |
534 | | // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh |
535 | | static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm) |
536 | 0 | { |
537 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
538 | 0 | (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && |
539 | 0 | ((Imm & 0xff00ff00ff00ff00ULL) == 0); |
540 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType5 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType5 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType5 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType5 |
541 | | |
542 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm) |
543 | 0 | { |
544 | 0 | return (Imm & 0xffULL); |
545 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType5 |
546 | | |
547 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm) |
548 | 0 | { |
549 | 0 | uint64_t EncVal = Imm; |
550 | 0 | return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal; |
551 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType5 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType5 |
552 | | |
553 | | // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 |
554 | | static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm) |
555 | 0 | { |
556 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
557 | 0 | (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && |
558 | 0 | ((Imm & 0x00ff00ff00ff00ffULL) == 0); |
559 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType6 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType6 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType6 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType6 |
560 | | |
561 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm) |
562 | 0 | { |
563 | 0 | return (Imm & 0xff00ULL) >> 8; |
564 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType6 |
565 | | |
566 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm) |
567 | 0 | { |
568 | 0 | uint64_t EncVal = Imm; |
569 | 0 | return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8); |
570 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType6 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType6 |
571 | | |
572 | | // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF |
573 | | static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm) |
574 | 0 | { |
575 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
576 | 0 | ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); |
577 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType7 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType7 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType7 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType7 |
578 | | |
579 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm) |
580 | 0 | { |
581 | 0 | return (Imm & 0xff00ULL) >> 8; |
582 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType7 |
583 | | |
584 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm) |
585 | 0 | { |
586 | 0 | uint64_t EncVal = Imm; |
587 | 0 | return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL; |
588 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType7 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType7 |
589 | | |
590 | | // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF |
591 | | static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm) |
592 | 0 | { |
593 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
594 | 0 | ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); |
595 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType8 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType8 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType8 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType8 |
596 | | |
597 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm) |
598 | 0 | { |
599 | 0 | uint64_t EncVal = Imm; |
600 | 0 | return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL; |
601 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType8 |
602 | | |
603 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm) |
604 | 0 | { |
605 | 0 | return (Imm & 0x00ff0000ULL) >> 16; |
606 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType8 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType8 |
607 | | |
608 | | // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh |
609 | | static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm) |
610 | 0 | { |
611 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
612 | 0 | ((Imm >> 48) == (Imm & 0x0000ffffULL)) && |
613 | 0 | ((Imm >> 56) == (Imm & 0x000000ffULL)); |
614 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType9 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType9 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType9 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType9 |
615 | | |
616 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm) |
617 | 0 | { |
618 | 0 | return (Imm & 0xffULL); |
619 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType9 |
620 | | |
621 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm) |
622 | 0 | { |
623 | 0 | uint64_t EncVal = Imm; |
624 | 0 | EncVal |= (EncVal << 8); |
625 | 0 | EncVal |= (EncVal << 16); |
626 | 0 | EncVal |= (EncVal << 32); |
627 | 0 | return EncVal; |
628 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType9 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType9 |
629 | | |
630 | | // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh |
631 | | // cmode: 1110, op: 1 |
632 | | static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm) |
633 | 0 | { |
634 | 0 | #if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \ |
635 | 0 | defined(_M_ARM64) |
636 | 0 | // The MSVC compiler 19.37 for ARM64 has an optimization bug that |
637 | 0 | // causes an incorrect behavior with the orignal version. Work around |
638 | 0 | // by using a slightly different variation. |
639 | 0 | // https://developercommunity.visualstudio.com/t/C-ARM64-compiler-optimization-bug/10481261 |
640 | 0 | constexpr uint64_t Mask = 0xFFULL; |
641 | 0 | uint64_t ByteA = (Imm >> 56) & Mask; |
642 | 0 | uint64_t ByteB = (Imm >> 48) & Mask; |
643 | 0 | uint64_t ByteC = (Imm >> 40) & Mask; |
644 | 0 | uint64_t ByteD = (Imm >> 32) & Mask; |
645 | 0 | uint64_t ByteE = (Imm >> 24) & Mask; |
646 | 0 | uint64_t ByteF = (Imm >> 16) & Mask; |
647 | 0 | uint64_t ByteG = (Imm >> 8) & Mask; |
648 | 0 | uint64_t ByteH = Imm & Mask; |
649 | 0 |
|
650 | 0 | return (ByteA == 0ULL || ByteA == Mask) && |
651 | 0 | (ByteB == 0ULL || ByteB == Mask) && |
652 | 0 | (ByteC == 0ULL || ByteC == Mask) && |
653 | 0 | (ByteD == 0ULL || ByteD == Mask) && |
654 | 0 | (ByteE == 0ULL || ByteE == Mask) && |
655 | 0 | (ByteF == 0ULL || ByteF == Mask) && |
656 | 0 | (ByteG == 0ULL || ByteG == Mask) && |
657 | 0 | (ByteH == 0ULL || ByteH == Mask); |
658 | 0 | #else |
659 | 0 | uint64_t ByteA = Imm & 0xff00000000000000ULL; |
660 | 0 | uint64_t ByteB = Imm & 0x00ff000000000000ULL; |
661 | 0 | uint64_t ByteC = Imm & 0x0000ff0000000000ULL; |
662 | 0 | uint64_t ByteD = Imm & 0x000000ff00000000ULL; |
663 | 0 | uint64_t ByteE = Imm & 0x00000000ff000000ULL; |
664 | 0 | uint64_t ByteF = Imm & 0x0000000000ff0000ULL; |
665 | 0 | uint64_t ByteG = Imm & 0x000000000000ff00ULL; |
666 | 0 | uint64_t ByteH = Imm & 0x00000000000000ffULL; |
667 | 0 |
|
668 | 0 | return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) && |
669 | 0 | (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && |
670 | 0 | (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && |
671 | 0 | (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && |
672 | 0 | (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && |
673 | 0 | (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && |
674 | 0 | (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && |
675 | 0 | (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); |
676 | 0 | #endif |
677 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType10 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType10 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType10 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType10 |
678 | | |
679 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) |
680 | 0 | { |
681 | 0 | uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0; |
682 | 0 | uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0; |
683 | 0 | uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0; |
684 | 0 | uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0; |
685 | 0 | uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0; |
686 | 0 | uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0; |
687 | 0 | uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0; |
688 | 0 | uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; |
689 | 0 |
|
690 | 0 | uint8_t EncVal = BitA; |
691 | 0 | EncVal <<= 1; |
692 | 0 | EncVal |= BitB; |
693 | 0 | EncVal <<= 1; |
694 | 0 | EncVal |= BitC; |
695 | 0 | EncVal <<= 1; |
696 | 0 | EncVal |= BitD; |
697 | 0 | EncVal <<= 1; |
698 | 0 | EncVal |= BitE; |
699 | 0 | EncVal <<= 1; |
700 | 0 | EncVal |= BitF; |
701 | 0 | EncVal <<= 1; |
702 | 0 | EncVal |= BitG; |
703 | 0 | EncVal <<= 1; |
704 | 0 | EncVal |= BitH; |
705 | 0 | return EncVal; |
706 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType10 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType10 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType10 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType10 |
707 | | |
708 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) |
709 | 663 | { |
710 | 663 | uint64_t EncVal = 0; |
711 | 663 | if (Imm & 0x80) |
712 | 468 | EncVal |= 0xff00000000000000ULL; |
713 | 663 | if (Imm & 0x40) |
714 | 262 | EncVal |= 0x00ff000000000000ULL; |
715 | 663 | if (Imm & 0x20) |
716 | 465 | EncVal |= 0x0000ff0000000000ULL; |
717 | 663 | if (Imm & 0x10) |
718 | 260 | EncVal |= 0x000000ff00000000ULL; |
719 | 663 | if (Imm & 0x08) |
720 | 600 | EncVal |= 0x00000000ff000000ULL; |
721 | 663 | if (Imm & 0x04) |
722 | 81 | EncVal |= 0x0000000000ff0000ULL; |
723 | 663 | if (Imm & 0x02) |
724 | 253 | EncVal |= 0x000000000000ff00ULL; |
725 | 663 | if (Imm & 0x01) |
726 | 282 | EncVal |= 0x00000000000000ffULL; |
727 | 663 | return EncVal; |
728 | 663 | } AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType10 Line | Count | Source | 709 | 252 | { | 710 | 252 | uint64_t EncVal = 0; | 711 | 252 | if (Imm & 0x80) | 712 | 171 | EncVal |= 0xff00000000000000ULL; | 713 | 252 | if (Imm & 0x40) | 714 | 73 | EncVal |= 0x00ff000000000000ULL; | 715 | 252 | if (Imm & 0x20) | 716 | 174 | EncVal |= 0x0000ff0000000000ULL; | 717 | 252 | if (Imm & 0x10) | 718 | 56 | EncVal |= 0x000000ff00000000ULL; | 719 | 252 | if (Imm & 0x08) | 720 | 226 | EncVal |= 0x00000000ff000000ULL; | 721 | 252 | if (Imm & 0x04) | 722 | 27 | EncVal |= 0x0000000000ff0000ULL; | 723 | 252 | if (Imm & 0x02) | 724 | 109 | EncVal |= 0x000000000000ff00ULL; | 725 | 252 | if (Imm & 0x01) | 726 | 111 | EncVal |= 0x00000000000000ffULL; | 727 | 252 | return EncVal; | 728 | 252 | } |
Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType10 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType10 AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType10 Line | Count | Source | 709 | 411 | { | 710 | 411 | uint64_t EncVal = 0; | 711 | 411 | if (Imm & 0x80) | 712 | 297 | EncVal |= 0xff00000000000000ULL; | 713 | 411 | if (Imm & 0x40) | 714 | 189 | EncVal |= 0x00ff000000000000ULL; | 715 | 411 | if (Imm & 0x20) | 716 | 291 | EncVal |= 0x0000ff0000000000ULL; | 717 | 411 | if (Imm & 0x10) | 718 | 204 | EncVal |= 0x000000ff00000000ULL; | 719 | 411 | if (Imm & 0x08) | 720 | 374 | EncVal |= 0x00000000ff000000ULL; | 721 | 411 | if (Imm & 0x04) | 722 | 54 | EncVal |= 0x0000000000ff0000ULL; | 723 | 411 | if (Imm & 0x02) | 724 | 144 | EncVal |= 0x000000000000ff00ULL; | 725 | 411 | if (Imm & 0x01) | 726 | 171 | EncVal |= 0x00000000000000ffULL; | 727 | 411 | return EncVal; | 728 | 411 | } |
|
729 | | |
730 | | // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00 |
731 | | static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm) |
732 | 0 | { |
733 | 0 | uint64_t BString = (Imm & 0x7E000000ULL) >> 25; |
734 | 0 | return ((Imm >> 32) == (Imm & 0xffffffffULL)) && |
735 | 0 | (BString == 0x1f || BString == 0x20) && |
736 | 0 | ((Imm & 0x0007ffff0007ffffULL) == 0); |
737 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType11 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType11 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType11 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType11 |
738 | | |
739 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) |
740 | 0 | { |
741 | 0 | uint8_t BitA = (Imm & 0x80000000ULL) != 0; |
742 | 0 | uint8_t BitB = (Imm & 0x20000000ULL) != 0; |
743 | 0 | uint8_t BitC = (Imm & 0x01000000ULL) != 0; |
744 | 0 | uint8_t BitD = (Imm & 0x00800000ULL) != 0; |
745 | 0 | uint8_t BitE = (Imm & 0x00400000ULL) != 0; |
746 | 0 | uint8_t BitF = (Imm & 0x00200000ULL) != 0; |
747 | 0 | uint8_t BitG = (Imm & 0x00100000ULL) != 0; |
748 | 0 | uint8_t BitH = (Imm & 0x00080000ULL) != 0; |
749 | 0 |
|
750 | 0 | uint8_t EncVal = BitA; |
751 | 0 | EncVal <<= 1; |
752 | 0 | EncVal |= BitB; |
753 | 0 | EncVal <<= 1; |
754 | 0 | EncVal |= BitC; |
755 | 0 | EncVal <<= 1; |
756 | 0 | EncVal |= BitD; |
757 | 0 | EncVal <<= 1; |
758 | 0 | EncVal |= BitE; |
759 | 0 | EncVal <<= 1; |
760 | 0 | EncVal |= BitF; |
761 | 0 | EncVal <<= 1; |
762 | 0 | EncVal |= BitG; |
763 | 0 | EncVal <<= 1; |
764 | 0 | EncVal |= BitH; |
765 | 0 | return EncVal; |
766 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType11 |
767 | | |
768 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm) |
769 | 0 | { |
770 | 0 | uint64_t EncVal = 0; |
771 | 0 | if (Imm & 0x80) |
772 | 0 | EncVal |= 0x80000000ULL; |
773 | 0 | if (Imm & 0x40) |
774 | 0 | EncVal |= 0x3e000000ULL; |
775 | 0 | else |
776 | 0 | EncVal |= 0x40000000ULL; |
777 | 0 | if (Imm & 0x20) |
778 | 0 | EncVal |= 0x01000000ULL; |
779 | 0 | if (Imm & 0x10) |
780 | 0 | EncVal |= 0x00800000ULL; |
781 | 0 | if (Imm & 0x08) |
782 | 0 | EncVal |= 0x00400000ULL; |
783 | 0 | if (Imm & 0x04) |
784 | 0 | EncVal |= 0x00200000ULL; |
785 | 0 | if (Imm & 0x02) |
786 | 0 | EncVal |= 0x00100000ULL; |
787 | 0 | if (Imm & 0x01) |
788 | 0 | EncVal |= 0x00080000ULL; |
789 | 0 | return (EncVal << 32) | EncVal; |
790 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType11 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType11 |
791 | | |
792 | | // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00 |
793 | | static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm) |
794 | 0 | { |
795 | 0 | uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54; |
796 | 0 | return ((BString == 0xff || BString == 0x100) && |
797 | 0 | ((Imm & 0x0000ffffffffffffULL) == 0)); |
798 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAdvSIMDModImmType12 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAdvSIMDModImmType12 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAdvSIMDModImmType12 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_isAdvSIMDModImmType12 |
799 | | |
800 | | static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm) |
801 | 0 | { |
802 | 0 | uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0; |
803 | 0 | uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0; |
804 | 0 | uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0; |
805 | 0 | uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0; |
806 | 0 | uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0; |
807 | 0 | uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0; |
808 | 0 | uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0; |
809 | 0 | uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0; |
810 | 0 |
|
811 | 0 | uint8_t EncVal = BitA; |
812 | 0 | EncVal <<= 1; |
813 | 0 | EncVal |= BitB; |
814 | 0 | EncVal <<= 1; |
815 | 0 | EncVal |= BitC; |
816 | 0 | EncVal <<= 1; |
817 | 0 | EncVal |= BitD; |
818 | 0 | EncVal <<= 1; |
819 | 0 | EncVal |= BitE; |
820 | 0 | EncVal <<= 1; |
821 | 0 | EncVal |= BitF; |
822 | 0 | EncVal <<= 1; |
823 | 0 | EncVal |= BitG; |
824 | 0 | EncVal <<= 1; |
825 | 0 | EncVal |= BitH; |
826 | 0 | return EncVal; |
827 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_encodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_encodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_encodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_encodeAdvSIMDModImmType12 |
828 | | |
829 | | static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm) |
830 | 0 | { |
831 | 0 | uint64_t EncVal = 0; |
832 | 0 | if (Imm & 0x80) |
833 | 0 | EncVal |= 0x8000000000000000ULL; |
834 | 0 | if (Imm & 0x40) |
835 | 0 | EncVal |= 0x3fc0000000000000ULL; |
836 | 0 | else |
837 | 0 | EncVal |= 0x4000000000000000ULL; |
838 | 0 | if (Imm & 0x20) |
839 | 0 | EncVal |= 0x0020000000000000ULL; |
840 | 0 | if (Imm & 0x10) |
841 | 0 | EncVal |= 0x0010000000000000ULL; |
842 | 0 | if (Imm & 0x08) |
843 | 0 | EncVal |= 0x0008000000000000ULL; |
844 | 0 | if (Imm & 0x04) |
845 | 0 | EncVal |= 0x0004000000000000ULL; |
846 | 0 | if (Imm & 0x02) |
847 | 0 | EncVal |= 0x0002000000000000ULL; |
848 | 0 | if (Imm & 0x01) |
849 | 0 | EncVal |= 0x0001000000000000ULL; |
850 | 0 | return (EncVal << 32) | EncVal; |
851 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_decodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_decodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_decodeAdvSIMDModImmType12 Unexecuted instantiation: AArch64InstPrinter.c:AArch64_AM_decodeAdvSIMDModImmType12 |
852 | | |
853 | | /// Returns true if Imm is the concatenation of a repeating pattern of type T. |
854 | | #define DEFINE_isSVEMaskOfIdenticalElements(T) \ |
855 | | static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \ |
856 | | T)(int64_t Imm) \ |
857 | 31.4k | { \ |
858 | 31.4k | union { \ |
859 | 31.4k | int64_t In; \ |
860 | 31.4k | T Out[sizeof(int64_t) / sizeof(T)]; \ |
861 | 31.4k | } U_Parts; \ |
862 | 31.4k | U_Parts.In = Imm; \ |
863 | 31.4k | T *Parts = U_Parts.Out; \ |
864 | 105k | for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \ |
865 | 86.3k | if (Parts[i] != Parts[0]) \ |
866 | 86.3k | return false; \ |
867 | 86.3k | } \ |
868 | 31.4k | return true; \ |
869 | 31.4k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isSVEMaskOfIdenticalElements_int8_t Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isSVEMaskOfIdenticalElements_int16_t Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isSVEMaskOfIdenticalElements_int32_t Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isSVEMaskOfIdenticalElements_int64_t Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isSVEMaskOfIdenticalElements_int8_t Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isSVEMaskOfIdenticalElements_int16_t Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isSVEMaskOfIdenticalElements_int32_t Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isSVEMaskOfIdenticalElements_int64_t Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isSVEMaskOfIdenticalElements_int8_t Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isSVEMaskOfIdenticalElements_int16_t Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isSVEMaskOfIdenticalElements_int32_t Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isSVEMaskOfIdenticalElements_int64_t AArch64InstPrinter.c:AArch64_AM_isSVEMaskOfIdenticalElements_int8_t Line | Count | Source | 857 | 6.84k | { \ | 858 | 6.84k | union { \ | 859 | 6.84k | int64_t In; \ | 860 | 6.84k | T Out[sizeof(int64_t) / sizeof(T)]; \ | 861 | 6.84k | } U_Parts; \ | 862 | 6.84k | U_Parts.In = Imm; \ | 863 | 6.84k | T *Parts = U_Parts.Out; \ | 864 | 29.2k | for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \ | 865 | 27.2k | if (Parts[i] != Parts[0]) \ | 866 | 27.2k | return false; \ | 867 | 27.2k | } \ | 868 | 6.84k | return true; \ | 869 | 6.84k | } |
AArch64InstPrinter.c:AArch64_AM_isSVEMaskOfIdenticalElements_int16_t Line | Count | Source | 857 | 11.4k | { \ | 858 | 11.4k | union { \ | 859 | 11.4k | int64_t In; \ | 860 | 11.4k | T Out[sizeof(int64_t) / sizeof(T)]; \ | 861 | 11.4k | } U_Parts; \ | 862 | 11.4k | U_Parts.In = Imm; \ | 863 | 11.4k | T *Parts = U_Parts.Out; \ | 864 | 41.3k | for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \ | 865 | 35.2k | if (Parts[i] != Parts[0]) \ | 866 | 35.2k | return false; \ | 867 | 35.2k | } \ | 868 | 11.4k | return true; \ | 869 | 11.4k | } |
AArch64InstPrinter.c:AArch64_AM_isSVEMaskOfIdenticalElements_int32_t Line | Count | Source | 857 | 10.6k | { \ | 858 | 10.6k | union { \ | 859 | 10.6k | int64_t In; \ | 860 | 10.6k | T Out[sizeof(int64_t) / sizeof(T)]; \ | 861 | 10.6k | } U_Parts; \ | 862 | 10.6k | U_Parts.In = Imm; \ | 863 | 10.6k | T *Parts = U_Parts.Out; \ | 864 | 29.3k | for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \ | 865 | 21.2k | if (Parts[i] != Parts[0]) \ | 866 | 21.2k | return false; \ | 867 | 21.2k | } \ | 868 | 10.6k | return true; \ | 869 | 10.6k | } |
AArch64InstPrinter.c:AArch64_AM_isSVEMaskOfIdenticalElements_int64_t Line | Count | Source | 857 | 2.55k | { \ | 858 | 2.55k | union { \ | 859 | 2.55k | int64_t In; \ | 860 | 2.55k | T Out[sizeof(int64_t) / sizeof(T)]; \ | 861 | 2.55k | } U_Parts; \ | 862 | 2.55k | U_Parts.In = Imm; \ | 863 | 2.55k | T *Parts = U_Parts.Out; \ | 864 | 5.10k | for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \ | 865 | 2.55k | if (Parts[i] != Parts[0]) \ | 866 | 2.55k | return false; \ | 867 | 2.55k | } \ | 868 | 2.55k | return true; \ | 869 | 2.55k | } |
|
870 | | DEFINE_isSVEMaskOfIdenticalElements(int8_t); |
871 | | DEFINE_isSVEMaskOfIdenticalElements(int16_t); |
872 | | DEFINE_isSVEMaskOfIdenticalElements(int32_t); |
873 | | DEFINE_isSVEMaskOfIdenticalElements(int64_t); |
874 | | |
875 | | static inline bool isSVECpyImm8(int64_t Imm) |
876 | 1.62k | { |
877 | 1.62k | bool IsImm8 = (int8_t)Imm == Imm; |
878 | | |
879 | 1.62k | return IsImm8 || (uint8_t)Imm == Imm; |
880 | 1.62k | } Unexecuted instantiation: AArch64Mapping.c:isSVECpyImm8 Unexecuted instantiation: AArch64Disassembler.c:isSVECpyImm8 Unexecuted instantiation: AArch64DisassemblerExtension.c:isSVECpyImm8 AArch64InstPrinter.c:isSVECpyImm8 Line | Count | Source | 876 | 1.62k | { | 877 | 1.62k | bool IsImm8 = (int8_t)Imm == Imm; | 878 | | | 879 | 1.62k | return IsImm8 || (uint8_t)Imm == Imm; | 880 | 1.62k | } |
|
881 | | |
882 | | static inline bool isSVECpyImm16(int64_t Imm) |
883 | 4.29k | { |
884 | 4.29k | bool IsImm8 = (int8_t)Imm == Imm; |
885 | 4.29k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; |
886 | | |
887 | 4.29k | return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; |
888 | 4.29k | } Unexecuted instantiation: AArch64Mapping.c:isSVECpyImm16 Unexecuted instantiation: AArch64Disassembler.c:isSVECpyImm16 Unexecuted instantiation: AArch64DisassemblerExtension.c:isSVECpyImm16 AArch64InstPrinter.c:isSVECpyImm16 Line | Count | Source | 883 | 4.29k | { | 884 | 4.29k | bool IsImm8 = (int8_t)Imm == Imm; | 885 | 4.29k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; | 886 | | | 887 | 4.29k | return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; | 888 | 4.29k | } |
|
889 | | |
890 | | static inline bool isSVECpyImm32(int64_t Imm) |
891 | 9.07k | { |
892 | 9.07k | bool IsImm8 = (int8_t)Imm == Imm; |
893 | 9.07k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; |
894 | | |
895 | 9.07k | return IsImm8 || IsImm16; |
896 | 9.07k | } Unexecuted instantiation: AArch64Mapping.c:isSVECpyImm32 Unexecuted instantiation: AArch64Disassembler.c:isSVECpyImm32 Unexecuted instantiation: AArch64DisassemblerExtension.c:isSVECpyImm32 AArch64InstPrinter.c:isSVECpyImm32 Line | Count | Source | 891 | 9.07k | { | 892 | 9.07k | bool IsImm8 = (int8_t)Imm == Imm; | 893 | 9.07k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; | 894 | | | 895 | 9.07k | return IsImm8 || IsImm16; | 896 | 9.07k | } |
|
897 | | |
898 | | static inline bool isSVECpyImm64(int64_t Imm) |
899 | 11.4k | { |
900 | 11.4k | bool IsImm8 = (int8_t)Imm == Imm; |
901 | 11.4k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; |
902 | | |
903 | 11.4k | return IsImm8 || IsImm16; |
904 | 11.4k | } Unexecuted instantiation: AArch64Mapping.c:isSVECpyImm64 Unexecuted instantiation: AArch64Disassembler.c:isSVECpyImm64 Unexecuted instantiation: AArch64DisassemblerExtension.c:isSVECpyImm64 AArch64InstPrinter.c:isSVECpyImm64 Line | Count | Source | 899 | 11.4k | { | 900 | 11.4k | bool IsImm8 = (int8_t)Imm == Imm; | 901 | 11.4k | bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; | 902 | | | 903 | 11.4k | return IsImm8 || IsImm16; | 904 | 11.4k | } |
|
905 | | |
906 | | /// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. |
907 | | static inline bool |
908 | | AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) |
909 | 11.4k | { |
910 | 11.4k | if (isSVECpyImm64(Imm)) |
911 | 208 | return false; |
912 | | |
913 | 11.2k | union { |
914 | 11.2k | int64_t In; |
915 | 11.2k | int32_t Out[2]; |
916 | 11.2k | } U_S; |
917 | 11.2k | U_S.In = Imm; |
918 | 11.2k | int32_t *S = U_S.Out; |
919 | 11.2k | union { |
920 | 11.2k | int64_t In; |
921 | 11.2k | int16_t Out[4]; |
922 | 11.2k | } U_H; |
923 | 11.2k | U_H.In = Imm; |
924 | 11.2k | int16_t *H = U_H.Out; |
925 | 11.2k | union { |
926 | 11.2k | int64_t In; |
927 | 11.2k | int8_t Out[8]; |
928 | 11.2k | } U_B; |
929 | 11.2k | U_B.In = Imm; |
930 | 11.2k | int8_t *B = U_B.Out; |
931 | | |
932 | 11.2k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) && |
933 | 11.2k | isSVECpyImm32(S[0])) |
934 | 2.98k | return false; |
935 | 8.26k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) && |
936 | 8.26k | isSVECpyImm16(H[0])) |
937 | 1.45k | return false; |
938 | 6.80k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) && |
939 | 6.80k | isSVECpyImm8(B[0])) |
940 | 1.62k | return false; |
941 | 5.18k | return AArch64_AM_isLogicalImmediate(Imm, 64); |
942 | 6.80k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate AArch64InstPrinter.c:AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate Line | Count | Source | 909 | 11.4k | { | 910 | 11.4k | if (isSVECpyImm64(Imm)) | 911 | 208 | return false; | 912 | | | 913 | 11.2k | union { | 914 | 11.2k | int64_t In; | 915 | 11.2k | int32_t Out[2]; | 916 | 11.2k | } U_S; | 917 | 11.2k | U_S.In = Imm; | 918 | 11.2k | int32_t *S = U_S.Out; | 919 | 11.2k | union { | 920 | 11.2k | int64_t In; | 921 | 11.2k | int16_t Out[4]; | 922 | 11.2k | } U_H; | 923 | 11.2k | U_H.In = Imm; | 924 | 11.2k | int16_t *H = U_H.Out; | 925 | 11.2k | union { | 926 | 11.2k | int64_t In; | 927 | 11.2k | int8_t Out[8]; | 928 | 11.2k | } U_B; | 929 | 11.2k | U_B.In = Imm; | 930 | 11.2k | int8_t *B = U_B.Out; | 931 | | | 932 | 11.2k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) && | 933 | 11.2k | isSVECpyImm32(S[0])) | 934 | 2.98k | return false; | 935 | 8.26k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) && | 936 | 8.26k | isSVECpyImm16(H[0])) | 937 | 1.45k | return false; | 938 | 6.80k | if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) && | 939 | 6.80k | isSVECpyImm8(B[0])) | 940 | 1.62k | return false; | 941 | 5.18k | return AArch64_AM_isLogicalImmediate(Imm, 64); | 942 | 6.80k | } |
|
943 | | |
944 | | inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth) |
945 | 2.46k | { |
946 | 9.80k | for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) |
947 | 7.76k | if ((Value & ~(0xffffULL << Shift)) == 0) |
948 | 429 | return true; |
949 | | |
950 | 2.03k | return false; |
951 | 2.46k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAnyMOVZMovAlias Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAnyMOVZMovAlias Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAnyMOVZMovAlias AArch64InstPrinter.c:AArch64_AM_isAnyMOVZMovAlias Line | Count | Source | 945 | 2.46k | { | 946 | 9.80k | for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) | 947 | 7.76k | if ((Value & ~(0xffffULL << Shift)) == 0) | 948 | 429 | return true; | 949 | | | 950 | 2.03k | return false; | 951 | 2.46k | } |
|
952 | | |
953 | | inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift, |
954 | | int RegWidth) |
955 | 2.02k | { |
956 | 2.02k | if (RegWidth == 32) |
957 | 249 | Value &= 0xffffffffULL; |
958 | | |
959 | | // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0". |
960 | 2.02k | if (Value == 0 && Shift != 0) |
961 | 94 | return false; |
962 | | |
963 | 1.93k | return (Value & ~(0xffffULL << Shift)) == 0; |
964 | 2.02k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isMOVZMovAlias Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isMOVZMovAlias Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isMOVZMovAlias AArch64InstPrinter.c:AArch64_AM_isMOVZMovAlias Line | Count | Source | 955 | 2.02k | { | 956 | 2.02k | if (RegWidth == 32) | 957 | 249 | Value &= 0xffffffffULL; | 958 | | | 959 | | // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0". | 960 | 2.02k | if (Value == 0 && Shift != 0) | 961 | 94 | return false; | 962 | | | 963 | 1.93k | return (Value & ~(0xffffULL << Shift)) == 0; | 964 | 2.02k | } |
|
965 | | |
966 | | inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, |
967 | | int RegWidth) |
968 | 1.38k | { |
969 | | // MOVZ takes precedence over MOVN. |
970 | 1.38k | if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth)) |
971 | 95 | return false; |
972 | | |
973 | 1.28k | Value = ~Value; |
974 | 1.28k | if (RegWidth == 32) |
975 | 214 | Value &= 0xffffffffULL; |
976 | | |
977 | 1.28k | return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth); |
978 | 1.38k | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isMOVNMovAlias Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isMOVNMovAlias Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isMOVNMovAlias AArch64InstPrinter.c:AArch64_AM_isMOVNMovAlias Line | Count | Source | 968 | 1.38k | { | 969 | | // MOVZ takes precedence over MOVN. | 970 | 1.38k | if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth)) | 971 | 95 | return false; | 972 | | | 973 | 1.28k | Value = ~Value; | 974 | 1.28k | if (RegWidth == 32) | 975 | 214 | Value &= 0xffffffffULL; | 976 | | | 977 | 1.28k | return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth); | 978 | 1.38k | } |
|
979 | | |
980 | | inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth) |
981 | 867 | { |
982 | 867 | if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth)) |
983 | 219 | return true; |
984 | | |
985 | | // It's not a MOVZ, but it might be a MOVN. |
986 | 648 | Value = ~Value; |
987 | 648 | if (RegWidth == 32) |
988 | 245 | Value &= 0xffffffffULL; |
989 | | |
990 | 648 | return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth); |
991 | 867 | } Unexecuted instantiation: AArch64Mapping.c:AArch64_AM_isAnyMOVWMovAlias Unexecuted instantiation: AArch64Disassembler.c:AArch64_AM_isAnyMOVWMovAlias Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64_AM_isAnyMOVWMovAlias AArch64InstPrinter.c:AArch64_AM_isAnyMOVWMovAlias Line | Count | Source | 981 | 867 | { | 982 | 867 | if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth)) | 983 | 219 | return true; | 984 | | | 985 | | // It's not a MOVZ, but it might be a MOVN. | 986 | 648 | Value = ~Value; | 987 | 648 | if (RegWidth == 32) | 988 | 245 | Value &= 0xffffffffULL; | 989 | | | 990 | 648 | return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth); | 991 | 867 | } |
|
992 | | |
993 | | // CS namespace end: AArch64_AM |
994 | | |
995 | | // end namespace AArch64_AM |
996 | | |
997 | | // end namespace llvm |
998 | | |
999 | | #endif |