/src/capstonenext/arch/AArch64/AArch64BaseInfo.h
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This file contains small standalone helper functions and enum definitions for |
24 | | // the AArch64 target useful for the compiler back-end and the MC libraries. |
25 | | // As such, it deliberately does not include references to LLVM core |
26 | | // code gen types, passes, etc.. |
27 | | // |
28 | | //===----------------------------------------------------------------------===// |
29 | | |
30 | | #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H |
31 | | #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H |
32 | | |
33 | | // FIXME: Is it easiest to fix this layering violation by moving the .inc |
34 | | // #includes from AArch64MCTargetDesc.h to here? |
35 | | #include <capstone/platform.h> |
36 | | #include <stdio.h> |
37 | | #include <stdlib.h> |
38 | | #include <string.h> |
39 | | |
40 | | #include "../../MCInstPrinter.h" |
41 | | |
42 | | #include "../../utils.h" |
43 | | #include "capstone/aarch64.h" |
44 | | |
45 | | #define GET_SUBTARGETINFO_ENUM |
46 | | #include "AArch64GenSubtargetInfo.inc" |
47 | | |
48 | | #define GET_REGINFO_ENUM |
49 | | #define GET_REGINFO_MC_DESC |
50 | | #include "AArch64GenRegisterInfo.inc" |
51 | | |
52 | | #define GET_INSTRINFO_ENUM |
53 | | #include "AArch64GenInstrInfo.inc" |
54 | | |
55 | | #define CONCAT(a, b) CONCAT_(a, b) |
56 | | #define CONCAT_(a, b) a##_##b |
57 | | |
58 | | static inline unsigned getWRegFromXReg(unsigned Reg) |
59 | 16.5k | { |
60 | 16.5k | switch (Reg) { |
61 | 400 | case AArch64_X0: |
62 | 400 | return AArch64_W0; |
63 | 392 | case AArch64_X1: |
64 | 392 | return AArch64_W1; |
65 | 602 | case AArch64_X2: |
66 | 602 | return AArch64_W2; |
67 | 714 | case AArch64_X3: |
68 | 714 | return AArch64_W3; |
69 | 112 | case AArch64_X4: |
70 | 112 | return AArch64_W4; |
71 | 142 | case AArch64_X5: |
72 | 142 | return AArch64_W5; |
73 | 328 | case AArch64_X6: |
74 | 328 | return AArch64_W6; |
75 | 98 | case AArch64_X7: |
76 | 98 | return AArch64_W7; |
77 | 186 | case AArch64_X8: |
78 | 186 | return AArch64_W8; |
79 | 1.02k | case AArch64_X9: |
80 | 1.02k | return AArch64_W9; |
81 | 502 | case AArch64_X10: |
82 | 502 | return AArch64_W10; |
83 | 238 | case AArch64_X11: |
84 | 238 | return AArch64_W11; |
85 | 526 | case AArch64_X12: |
86 | 526 | return AArch64_W12; |
87 | 38 | case AArch64_X13: |
88 | 38 | return AArch64_W13; |
89 | 1.00k | case AArch64_X14: |
90 | 1.00k | return AArch64_W14; |
91 | 1.24k | case AArch64_X15: |
92 | 1.24k | return AArch64_W15; |
93 | 874 | case AArch64_X16: |
94 | 874 | return AArch64_W16; |
95 | 374 | case AArch64_X17: |
96 | 374 | return AArch64_W17; |
97 | 2.15k | case AArch64_X18: |
98 | 2.15k | return AArch64_W18; |
99 | 1.81k | case AArch64_X19: |
100 | 1.81k | return AArch64_W19; |
101 | 526 | case AArch64_X20: |
102 | 526 | return AArch64_W20; |
103 | 424 | case AArch64_X21: |
104 | 424 | return AArch64_W21; |
105 | 148 | case AArch64_X22: |
106 | 148 | return AArch64_W22; |
107 | 220 | case AArch64_X23: |
108 | 220 | return AArch64_W23; |
109 | 708 | case AArch64_X24: |
110 | 708 | return AArch64_W24; |
111 | 940 | case AArch64_X25: |
112 | 940 | return AArch64_W25; |
113 | 58 | case AArch64_X26: |
114 | 58 | return AArch64_W26; |
115 | 80 | case AArch64_X27: |
116 | 80 | return AArch64_W27; |
117 | 28 | case AArch64_X28: |
118 | 28 | return AArch64_W28; |
119 | 138 | case AArch64_FP: |
120 | 138 | return AArch64_W29; |
121 | 60 | case AArch64_LR: |
122 | 60 | return AArch64_W30; |
123 | 0 | case AArch64_SP: |
124 | 0 | return AArch64_WSP; |
125 | 268 | case AArch64_XZR: |
126 | 268 | return AArch64_WZR; |
127 | 16.5k | } |
128 | | // For anything else, return it unchanged. |
129 | 134 | return Reg; |
130 | 16.5k | } AArch64Mapping.c:getWRegFromXReg Line | Count | Source | 59 | 6.51k | { | 60 | 6.51k | switch (Reg) { | 61 | 190 | case AArch64_X0: | 62 | 190 | return AArch64_W0; | 63 | 81 | case AArch64_X1: | 64 | 81 | return AArch64_W1; | 65 | 273 | case AArch64_X2: | 66 | 273 | return AArch64_W2; | 67 | 356 | case AArch64_X3: | 68 | 356 | return AArch64_W3; | 69 | 56 | case AArch64_X4: | 70 | 56 | return AArch64_W4; | 71 | 71 | case AArch64_X5: | 72 | 71 | return AArch64_W5; | 73 | 156 | case AArch64_X6: | 74 | 156 | return AArch64_W6; | 75 | 47 | case AArch64_X7: | 76 | 47 | return AArch64_W7; | 77 | 89 | case AArch64_X8: | 78 | 89 | return AArch64_W8; | 79 | 152 | case AArch64_X9: | 80 | 152 | return AArch64_W9; | 81 | 250 | case AArch64_X10: | 82 | 250 | return AArch64_W10; | 83 | 118 | case AArch64_X11: | 84 | 118 | return AArch64_W11; | 85 | 263 | case AArch64_X12: | 86 | 263 | return AArch64_W12; | 87 | 10 | case AArch64_X13: | 88 | 10 | return AArch64_W13; | 89 | 503 | case AArch64_X14: | 90 | 503 | return AArch64_W14; | 91 | 621 | case AArch64_X15: | 92 | 621 | return AArch64_W15; | 93 | 65 | case AArch64_X16: | 94 | 65 | return AArch64_W16; | 95 | 143 | case AArch64_X17: | 96 | 143 | return AArch64_W17; | 97 | 1.07k | case AArch64_X18: | 98 | 1.07k | return AArch64_W18; | 99 | 907 | case AArch64_X19: | 100 | 907 | return AArch64_W19; | 101 | 263 | case AArch64_X20: | 102 | 263 | return AArch64_W20; | 103 | 204 | case AArch64_X21: | 104 | 204 | return AArch64_W21; | 105 | 74 | case AArch64_X22: | 106 | 74 | return AArch64_W22; | 107 | 105 | case AArch64_X23: | 108 | 105 | return AArch64_W23; | 109 | 12 | case AArch64_X24: | 110 | 12 | return AArch64_W24; | 111 | 133 | case AArch64_X25: | 112 | 133 | return AArch64_W25; | 113 | 25 | case AArch64_X26: | 114 | 25 | return AArch64_W26; | 115 | 39 | case AArch64_X27: | 116 | 39 | return AArch64_W27; | 117 | 9 | case AArch64_X28: | 118 | 9 | return AArch64_W28; | 119 | 69 | case AArch64_FP: | 120 | 69 | return AArch64_W29; | 121 | 27 | case AArch64_LR: | 122 | 27 | return AArch64_W30; | 123 | 0 | case AArch64_SP: | 124 | 0 | return AArch64_WSP; | 125 | 131 | case AArch64_XZR: | 126 | 131 | return AArch64_WZR; | 127 | 6.51k | } | 128 | | // For anything else, return it unchanged. | 129 | 0 | return Reg; | 130 | 6.51k | } |
Unexecuted instantiation: AArch64BaseInfo.c:getWRegFromXReg Unexecuted instantiation: AArch64Disassembler.c:getWRegFromXReg Unexecuted instantiation: AArch64DisassemblerExtension.c:getWRegFromXReg AArch64InstPrinter.c:getWRegFromXReg Line | Count | Source | 59 | 9.98k | { | 60 | 9.98k | switch (Reg) { | 61 | 210 | case AArch64_X0: | 62 | 210 | return AArch64_W0; | 63 | 311 | case AArch64_X1: | 64 | 311 | return AArch64_W1; | 65 | 329 | case AArch64_X2: | 66 | 329 | return AArch64_W2; | 67 | 358 | case AArch64_X3: | 68 | 358 | return AArch64_W3; | 69 | 56 | case AArch64_X4: | 70 | 56 | return AArch64_W4; | 71 | 71 | case AArch64_X5: | 72 | 71 | return AArch64_W5; | 73 | 172 | case AArch64_X6: | 74 | 172 | return AArch64_W6; | 75 | 51 | case AArch64_X7: | 76 | 51 | return AArch64_W7; | 77 | 97 | case AArch64_X8: | 78 | 97 | return AArch64_W8; | 79 | 874 | case AArch64_X9: | 80 | 874 | return AArch64_W9; | 81 | 252 | case AArch64_X10: | 82 | 252 | return AArch64_W10; | 83 | 120 | case AArch64_X11: | 84 | 120 | return AArch64_W11; | 85 | 263 | case AArch64_X12: | 86 | 263 | return AArch64_W12; | 87 | 28 | case AArch64_X13: | 88 | 28 | return AArch64_W13; | 89 | 503 | case AArch64_X14: | 90 | 503 | return AArch64_W14; | 91 | 621 | case AArch64_X15: | 92 | 621 | return AArch64_W15; | 93 | 809 | case AArch64_X16: | 94 | 809 | return AArch64_W16; | 95 | 231 | case AArch64_X17: | 96 | 231 | return AArch64_W17; | 97 | 1.07k | case AArch64_X18: | 98 | 1.07k | return AArch64_W18; | 99 | 909 | case AArch64_X19: | 100 | 909 | return AArch64_W19; | 101 | 263 | case AArch64_X20: | 102 | 263 | return AArch64_W20; | 103 | 220 | case AArch64_X21: | 104 | 220 | return AArch64_W21; | 105 | 74 | case AArch64_X22: | 106 | 74 | return AArch64_W22; | 107 | 115 | case AArch64_X23: | 108 | 115 | return AArch64_W23; | 109 | 696 | case AArch64_X24: | 110 | 696 | return AArch64_W24; | 111 | 807 | case AArch64_X25: | 112 | 807 | return AArch64_W25; | 113 | 33 | case AArch64_X26: | 114 | 33 | return AArch64_W26; | 115 | 41 | case AArch64_X27: | 116 | 41 | return AArch64_W27; | 117 | 19 | case AArch64_X28: | 118 | 19 | return AArch64_W28; | 119 | 69 | case AArch64_FP: | 120 | 69 | return AArch64_W29; | 121 | 33 | case AArch64_LR: | 122 | 33 | return AArch64_W30; | 123 | 0 | case AArch64_SP: | 124 | 0 | return AArch64_WSP; | 125 | 137 | case AArch64_XZR: | 126 | 137 | return AArch64_WZR; | 127 | 9.98k | } | 128 | | // For anything else, return it unchanged. | 129 | 134 | return Reg; | 130 | 9.98k | } |
|
131 | | |
132 | | static inline unsigned getXRegFromWReg(unsigned Reg) |
133 | 0 | { |
134 | 0 | switch (Reg) { |
135 | 0 | case AArch64_W0: |
136 | 0 | return AArch64_X0; |
137 | 0 | case AArch64_W1: |
138 | 0 | return AArch64_X1; |
139 | 0 | case AArch64_W2: |
140 | 0 | return AArch64_X2; |
141 | 0 | case AArch64_W3: |
142 | 0 | return AArch64_X3; |
143 | 0 | case AArch64_W4: |
144 | 0 | return AArch64_X4; |
145 | 0 | case AArch64_W5: |
146 | 0 | return AArch64_X5; |
147 | 0 | case AArch64_W6: |
148 | 0 | return AArch64_X6; |
149 | 0 | case AArch64_W7: |
150 | 0 | return AArch64_X7; |
151 | 0 | case AArch64_W8: |
152 | 0 | return AArch64_X8; |
153 | 0 | case AArch64_W9: |
154 | 0 | return AArch64_X9; |
155 | 0 | case AArch64_W10: |
156 | 0 | return AArch64_X10; |
157 | 0 | case AArch64_W11: |
158 | 0 | return AArch64_X11; |
159 | 0 | case AArch64_W12: |
160 | 0 | return AArch64_X12; |
161 | 0 | case AArch64_W13: |
162 | 0 | return AArch64_X13; |
163 | 0 | case AArch64_W14: |
164 | 0 | return AArch64_X14; |
165 | 0 | case AArch64_W15: |
166 | 0 | return AArch64_X15; |
167 | 0 | case AArch64_W16: |
168 | 0 | return AArch64_X16; |
169 | 0 | case AArch64_W17: |
170 | 0 | return AArch64_X17; |
171 | 0 | case AArch64_W18: |
172 | 0 | return AArch64_X18; |
173 | 0 | case AArch64_W19: |
174 | 0 | return AArch64_X19; |
175 | 0 | case AArch64_W20: |
176 | 0 | return AArch64_X20; |
177 | 0 | case AArch64_W21: |
178 | 0 | return AArch64_X21; |
179 | 0 | case AArch64_W22: |
180 | 0 | return AArch64_X22; |
181 | 0 | case AArch64_W23: |
182 | 0 | return AArch64_X23; |
183 | 0 | case AArch64_W24: |
184 | 0 | return AArch64_X24; |
185 | 0 | case AArch64_W25: |
186 | 0 | return AArch64_X25; |
187 | 0 | case AArch64_W26: |
188 | 0 | return AArch64_X26; |
189 | 0 | case AArch64_W27: |
190 | 0 | return AArch64_X27; |
191 | 0 | case AArch64_W28: |
192 | 0 | return AArch64_X28; |
193 | 0 | case AArch64_W29: |
194 | 0 | return AArch64_FP; |
195 | 0 | case AArch64_W30: |
196 | 0 | return AArch64_LR; |
197 | 0 | case AArch64_WSP: |
198 | 0 | return AArch64_SP; |
199 | 0 | case AArch64_WZR: |
200 | 0 | return AArch64_XZR; |
201 | 0 | } |
202 | 0 | // For anything else, return it unchanged. |
203 | 0 | return Reg; |
204 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getXRegFromWReg Unexecuted instantiation: AArch64BaseInfo.c:getXRegFromWReg Unexecuted instantiation: AArch64Disassembler.c:getXRegFromWReg Unexecuted instantiation: AArch64DisassemblerExtension.c:getXRegFromWReg Unexecuted instantiation: AArch64InstPrinter.c:getXRegFromWReg |
205 | | |
206 | | static inline unsigned getXRegFromXRegTuple(unsigned RegTuple) |
207 | 0 | { |
208 | 0 | switch (RegTuple) { |
209 | 0 | case AArch64_X0_X1_X2_X3_X4_X5_X6_X7: |
210 | 0 | return AArch64_X0; |
211 | 0 | case AArch64_X2_X3_X4_X5_X6_X7_X8_X9: |
212 | 0 | return AArch64_X2; |
213 | 0 | case AArch64_X4_X5_X6_X7_X8_X9_X10_X11: |
214 | 0 | return AArch64_X4; |
215 | 0 | case AArch64_X6_X7_X8_X9_X10_X11_X12_X13: |
216 | 0 | return AArch64_X6; |
217 | 0 | case AArch64_X8_X9_X10_X11_X12_X13_X14_X15: |
218 | 0 | return AArch64_X8; |
219 | 0 | case AArch64_X10_X11_X12_X13_X14_X15_X16_X17: |
220 | 0 | return AArch64_X10; |
221 | 0 | case AArch64_X12_X13_X14_X15_X16_X17_X18_X19: |
222 | 0 | return AArch64_X12; |
223 | 0 | case AArch64_X14_X15_X16_X17_X18_X19_X20_X21: |
224 | 0 | return AArch64_X14; |
225 | 0 | case AArch64_X16_X17_X18_X19_X20_X21_X22_X23: |
226 | 0 | return AArch64_X16; |
227 | 0 | case AArch64_X18_X19_X20_X21_X22_X23_X24_X25: |
228 | 0 | return AArch64_X18; |
229 | 0 | case AArch64_X20_X21_X22_X23_X24_X25_X26_X27: |
230 | 0 | return AArch64_X20; |
231 | 0 | case AArch64_X22_X23_X24_X25_X26_X27_X28_FP: |
232 | 0 | return AArch64_X22; |
233 | 0 | } |
234 | 0 | // For anything else, return it unchanged. |
235 | 0 | return RegTuple; |
236 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getXRegFromXRegTuple Unexecuted instantiation: AArch64BaseInfo.c:getXRegFromXRegTuple Unexecuted instantiation: AArch64Disassembler.c:getXRegFromXRegTuple Unexecuted instantiation: AArch64DisassemblerExtension.c:getXRegFromXRegTuple Unexecuted instantiation: AArch64InstPrinter.c:getXRegFromXRegTuple |
237 | | |
238 | | static inline unsigned getBRegFromDReg(unsigned Reg) |
239 | 0 | { |
240 | 0 | switch (Reg) { |
241 | 0 | case AArch64_D0: |
242 | 0 | return AArch64_B0; |
243 | 0 | case AArch64_D1: |
244 | 0 | return AArch64_B1; |
245 | 0 | case AArch64_D2: |
246 | 0 | return AArch64_B2; |
247 | 0 | case AArch64_D3: |
248 | 0 | return AArch64_B3; |
249 | 0 | case AArch64_D4: |
250 | 0 | return AArch64_B4; |
251 | 0 | case AArch64_D5: |
252 | 0 | return AArch64_B5; |
253 | 0 | case AArch64_D6: |
254 | 0 | return AArch64_B6; |
255 | 0 | case AArch64_D7: |
256 | 0 | return AArch64_B7; |
257 | 0 | case AArch64_D8: |
258 | 0 | return AArch64_B8; |
259 | 0 | case AArch64_D9: |
260 | 0 | return AArch64_B9; |
261 | 0 | case AArch64_D10: |
262 | 0 | return AArch64_B10; |
263 | 0 | case AArch64_D11: |
264 | 0 | return AArch64_B11; |
265 | 0 | case AArch64_D12: |
266 | 0 | return AArch64_B12; |
267 | 0 | case AArch64_D13: |
268 | 0 | return AArch64_B13; |
269 | 0 | case AArch64_D14: |
270 | 0 | return AArch64_B14; |
271 | 0 | case AArch64_D15: |
272 | 0 | return AArch64_B15; |
273 | 0 | case AArch64_D16: |
274 | 0 | return AArch64_B16; |
275 | 0 | case AArch64_D17: |
276 | 0 | return AArch64_B17; |
277 | 0 | case AArch64_D18: |
278 | 0 | return AArch64_B18; |
279 | 0 | case AArch64_D19: |
280 | 0 | return AArch64_B19; |
281 | 0 | case AArch64_D20: |
282 | 0 | return AArch64_B20; |
283 | 0 | case AArch64_D21: |
284 | 0 | return AArch64_B21; |
285 | 0 | case AArch64_D22: |
286 | 0 | return AArch64_B22; |
287 | 0 | case AArch64_D23: |
288 | 0 | return AArch64_B23; |
289 | 0 | case AArch64_D24: |
290 | 0 | return AArch64_B24; |
291 | 0 | case AArch64_D25: |
292 | 0 | return AArch64_B25; |
293 | 0 | case AArch64_D26: |
294 | 0 | return AArch64_B26; |
295 | 0 | case AArch64_D27: |
296 | 0 | return AArch64_B27; |
297 | 0 | case AArch64_D28: |
298 | 0 | return AArch64_B28; |
299 | 0 | case AArch64_D29: |
300 | 0 | return AArch64_B29; |
301 | 0 | case AArch64_D30: |
302 | 0 | return AArch64_B30; |
303 | 0 | case AArch64_D31: |
304 | 0 | return AArch64_B31; |
305 | 0 | } |
306 | 0 | // For anything else, return it unchanged. |
307 | 0 | return Reg; |
308 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getBRegFromDReg Unexecuted instantiation: AArch64BaseInfo.c:getBRegFromDReg Unexecuted instantiation: AArch64Disassembler.c:getBRegFromDReg Unexecuted instantiation: AArch64DisassemblerExtension.c:getBRegFromDReg Unexecuted instantiation: AArch64InstPrinter.c:getBRegFromDReg |
309 | | |
310 | | static inline unsigned getDRegFromBReg(unsigned Reg) |
311 | 0 | { |
312 | 0 | switch (Reg) { |
313 | 0 | case AArch64_B0: |
314 | 0 | return AArch64_D0; |
315 | 0 | case AArch64_B1: |
316 | 0 | return AArch64_D1; |
317 | 0 | case AArch64_B2: |
318 | 0 | return AArch64_D2; |
319 | 0 | case AArch64_B3: |
320 | 0 | return AArch64_D3; |
321 | 0 | case AArch64_B4: |
322 | 0 | return AArch64_D4; |
323 | 0 | case AArch64_B5: |
324 | 0 | return AArch64_D5; |
325 | 0 | case AArch64_B6: |
326 | 0 | return AArch64_D6; |
327 | 0 | case AArch64_B7: |
328 | 0 | return AArch64_D7; |
329 | 0 | case AArch64_B8: |
330 | 0 | return AArch64_D8; |
331 | 0 | case AArch64_B9: |
332 | 0 | return AArch64_D9; |
333 | 0 | case AArch64_B10: |
334 | 0 | return AArch64_D10; |
335 | 0 | case AArch64_B11: |
336 | 0 | return AArch64_D11; |
337 | 0 | case AArch64_B12: |
338 | 0 | return AArch64_D12; |
339 | 0 | case AArch64_B13: |
340 | 0 | return AArch64_D13; |
341 | 0 | case AArch64_B14: |
342 | 0 | return AArch64_D14; |
343 | 0 | case AArch64_B15: |
344 | 0 | return AArch64_D15; |
345 | 0 | case AArch64_B16: |
346 | 0 | return AArch64_D16; |
347 | 0 | case AArch64_B17: |
348 | 0 | return AArch64_D17; |
349 | 0 | case AArch64_B18: |
350 | 0 | return AArch64_D18; |
351 | 0 | case AArch64_B19: |
352 | 0 | return AArch64_D19; |
353 | 0 | case AArch64_B20: |
354 | 0 | return AArch64_D20; |
355 | 0 | case AArch64_B21: |
356 | 0 | return AArch64_D21; |
357 | 0 | case AArch64_B22: |
358 | 0 | return AArch64_D22; |
359 | 0 | case AArch64_B23: |
360 | 0 | return AArch64_D23; |
361 | 0 | case AArch64_B24: |
362 | 0 | return AArch64_D24; |
363 | 0 | case AArch64_B25: |
364 | 0 | return AArch64_D25; |
365 | 0 | case AArch64_B26: |
366 | 0 | return AArch64_D26; |
367 | 0 | case AArch64_B27: |
368 | 0 | return AArch64_D27; |
369 | 0 | case AArch64_B28: |
370 | 0 | return AArch64_D28; |
371 | 0 | case AArch64_B29: |
372 | 0 | return AArch64_D29; |
373 | 0 | case AArch64_B30: |
374 | 0 | return AArch64_D30; |
375 | 0 | case AArch64_B31: |
376 | 0 | return AArch64_D31; |
377 | 0 | } |
378 | 0 | // For anything else, return it unchanged. |
379 | 0 | return Reg; |
380 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getDRegFromBReg Unexecuted instantiation: AArch64BaseInfo.c:getDRegFromBReg Unexecuted instantiation: AArch64Disassembler.c:getDRegFromBReg Unexecuted instantiation: AArch64DisassemblerExtension.c:getDRegFromBReg Unexecuted instantiation: AArch64InstPrinter.c:getDRegFromBReg |
381 | | |
382 | | static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) |
383 | 0 | { |
384 | 0 | switch (Opcode) { |
385 | 0 | case AArch64_LDADDAB: |
386 | 0 | case AArch64_LDADDAH: |
387 | 0 | case AArch64_LDADDAW: |
388 | 0 | case AArch64_LDADDAX: |
389 | 0 | case AArch64_LDADDALB: |
390 | 0 | case AArch64_LDADDALH: |
391 | 0 | case AArch64_LDADDALW: |
392 | 0 | case AArch64_LDADDALX: |
393 | 0 | case AArch64_LDCLRAB: |
394 | 0 | case AArch64_LDCLRAH: |
395 | 0 | case AArch64_LDCLRAW: |
396 | 0 | case AArch64_LDCLRAX: |
397 | 0 | case AArch64_LDCLRALB: |
398 | 0 | case AArch64_LDCLRALH: |
399 | 0 | case AArch64_LDCLRALW: |
400 | 0 | case AArch64_LDCLRALX: |
401 | 0 | case AArch64_LDEORAB: |
402 | 0 | case AArch64_LDEORAH: |
403 | 0 | case AArch64_LDEORAW: |
404 | 0 | case AArch64_LDEORAX: |
405 | 0 | case AArch64_LDEORALB: |
406 | 0 | case AArch64_LDEORALH: |
407 | 0 | case AArch64_LDEORALW: |
408 | 0 | case AArch64_LDEORALX: |
409 | 0 | case AArch64_LDSETAB: |
410 | 0 | case AArch64_LDSETAH: |
411 | 0 | case AArch64_LDSETAW: |
412 | 0 | case AArch64_LDSETAX: |
413 | 0 | case AArch64_LDSETALB: |
414 | 0 | case AArch64_LDSETALH: |
415 | 0 | case AArch64_LDSETALW: |
416 | 0 | case AArch64_LDSETALX: |
417 | 0 | case AArch64_LDSMAXAB: |
418 | 0 | case AArch64_LDSMAXAH: |
419 | 0 | case AArch64_LDSMAXAW: |
420 | 0 | case AArch64_LDSMAXAX: |
421 | 0 | case AArch64_LDSMAXALB: |
422 | 0 | case AArch64_LDSMAXALH: |
423 | 0 | case AArch64_LDSMAXALW: |
424 | 0 | case AArch64_LDSMAXALX: |
425 | 0 | case AArch64_LDSMINAB: |
426 | 0 | case AArch64_LDSMINAH: |
427 | 0 | case AArch64_LDSMINAW: |
428 | 0 | case AArch64_LDSMINAX: |
429 | 0 | case AArch64_LDSMINALB: |
430 | 0 | case AArch64_LDSMINALH: |
431 | 0 | case AArch64_LDSMINALW: |
432 | 0 | case AArch64_LDSMINALX: |
433 | 0 | case AArch64_LDUMAXAB: |
434 | 0 | case AArch64_LDUMAXAH: |
435 | 0 | case AArch64_LDUMAXAW: |
436 | 0 | case AArch64_LDUMAXAX: |
437 | 0 | case AArch64_LDUMAXALB: |
438 | 0 | case AArch64_LDUMAXALH: |
439 | 0 | case AArch64_LDUMAXALW: |
440 | 0 | case AArch64_LDUMAXALX: |
441 | 0 | case AArch64_LDUMINAB: |
442 | 0 | case AArch64_LDUMINAH: |
443 | 0 | case AArch64_LDUMINAW: |
444 | 0 | case AArch64_LDUMINAX: |
445 | 0 | case AArch64_LDUMINALB: |
446 | 0 | case AArch64_LDUMINALH: |
447 | 0 | case AArch64_LDUMINALW: |
448 | 0 | case AArch64_LDUMINALX: |
449 | 0 | case AArch64_SWPAB: |
450 | 0 | case AArch64_SWPAH: |
451 | 0 | case AArch64_SWPAW: |
452 | 0 | case AArch64_SWPAX: |
453 | 0 | case AArch64_SWPALB: |
454 | 0 | case AArch64_SWPALH: |
455 | 0 | case AArch64_SWPALW: |
456 | 0 | case AArch64_SWPALX: |
457 | 0 | return true; |
458 | 0 | } |
459 | 0 | return false; |
460 | 0 | } Unexecuted instantiation: AArch64Mapping.c:atomicBarrierDroppedOnZero Unexecuted instantiation: AArch64BaseInfo.c:atomicBarrierDroppedOnZero Unexecuted instantiation: AArch64Disassembler.c:atomicBarrierDroppedOnZero Unexecuted instantiation: AArch64DisassemblerExtension.c:atomicBarrierDroppedOnZero Unexecuted instantiation: AArch64InstPrinter.c:atomicBarrierDroppedOnZero |
461 | | |
462 | | // MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h |
463 | | // MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h |
464 | | // MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h |
465 | | // MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h |
466 | | |
467 | | typedef struct SysAlias { |
468 | | const char *Name; |
469 | | aarch64_sysop_alias SysAlias; |
470 | | uint16_t Encoding; |
471 | | aarch64_insn_group FeaturesRequired[3]; |
472 | | } SysAlias; |
473 | | |
474 | | typedef struct SysAliasReg { |
475 | | const char *Name; |
476 | | aarch64_sysop_reg SysReg; |
477 | | uint16_t Encoding; |
478 | | bool NeedsReg; |
479 | | aarch64_insn_group FeaturesRequired[3]; |
480 | | } SysAliasReg; |
481 | | |
482 | | typedef struct SysAliasImm { |
483 | | const char *Name; |
484 | | aarch64_sysop_imm SysImm; |
485 | | uint16_t ImmValue; |
486 | | uint16_t Encoding; |
487 | | aarch64_insn_group FeaturesRequired[3]; |
488 | | } SysAliasImm; |
489 | | |
490 | | // CS namespace begin: AArch64SVCR |
491 | | |
492 | | #define AArch64SVCR_SVCR SysAlias |
493 | | |
494 | | #define GET_SVCR_DECL |
495 | | |
496 | | #include "AArch64GenSystemOperands.inc" |
497 | | |
498 | | // CS namespace end: AArch64SVCR |
499 | | |
500 | | // CS namespace begin: AArch64AT |
501 | | |
502 | | #define AArch64AT_AT SysAlias |
503 | | |
504 | | #define GET_AT_DECL |
505 | | |
506 | | #include "AArch64GenSystemOperands.inc" |
507 | | |
508 | | // CS namespace end: AArch64AT |
509 | | |
510 | | // CS namespace begin: AArch64DB |
511 | | |
512 | | #define AArch64DB_DB SysAlias |
513 | | |
514 | | #define GET_DB_DECL |
515 | | |
516 | | #include "AArch64GenSystemOperands.inc" |
517 | | |
518 | | // CS namespace end: AArch64DB |
519 | | |
520 | | // CS namespace begin: AArch64DBnXS |
521 | | |
522 | | #define AArch64DBnXS_DBnXS SysAliasImm |
523 | | |
524 | | #define GET_DBNXS_DECL |
525 | | |
526 | | #include "AArch64GenSystemOperands.inc" |
527 | | |
528 | | // CS namespace end: AArch64DBnXS |
529 | | |
530 | | // CS namespace begin: AArch64DC |
531 | | |
532 | | #define AArch64DC_DC SysAlias |
533 | | |
534 | | #define GET_DC_DECL |
535 | | |
536 | | #include "AArch64GenSystemOperands.inc" |
537 | | |
538 | | // CS namespace end: AArch64DC |
539 | | |
540 | | // CS namespace begin: AArch64IC |
541 | | |
542 | | #define AArch64IC_IC SysAliasReg |
543 | | |
544 | | #define GET_IC_DECL |
545 | | |
546 | | #include "AArch64GenSystemOperands.inc" |
547 | | |
548 | | // CS namespace end: AArch64IC |
549 | | |
550 | | // CS namespace begin: AArch64ISB |
551 | | |
552 | | #define AArch64ISB_ISB SysAlias |
553 | | |
554 | | #define GET_ISB_DECL |
555 | | |
556 | | #include "AArch64GenSystemOperands.inc" |
557 | | |
558 | | // CS namespace end: AArch64ISB |
559 | | |
560 | | // CS namespace begin: AArch64TSB |
561 | | |
562 | | #define AArch64TSB_TSB SysAlias |
563 | | |
564 | | #define GET_TSB_DECL |
565 | | |
566 | | #include "AArch64GenSystemOperands.inc" |
567 | | |
568 | | // CS namespace end: AArch64TSB |
569 | | |
570 | | // CS namespace begin: AArch64PRFM |
571 | | |
572 | | #define AArch64PRFM_PRFM SysAlias |
573 | | |
574 | | #define GET_PRFM_DECL |
575 | | |
576 | | #include "AArch64GenSystemOperands.inc" |
577 | | |
578 | | // CS namespace end: AArch64PRFM |
579 | | |
580 | | // CS namespace begin: AArch64SVEPRFM |
581 | | |
582 | | #define AArch64SVEPRFM_SVEPRFM SysAlias |
583 | | |
584 | | #define GET_SVEPRFM_DECL |
585 | | |
586 | | #include "AArch64GenSystemOperands.inc" |
587 | | |
588 | | // CS namespace end: AArch64SVEPRFM |
589 | | |
590 | | // CS namespace begin: AArch64RPRFM |
591 | | |
592 | | #define AArch64RPRFM_RPRFM SysAlias |
593 | | |
594 | | #define GET_RPRFM_DECL |
595 | | |
596 | | #include "AArch64GenSystemOperands.inc" |
597 | | |
598 | | // CS namespace end: AArch64RPRFM |
599 | | |
600 | | // CS namespace begin: AArch64SVEPredPattern |
601 | | |
602 | | typedef struct SVEPREDPAT { |
603 | | const char *Name; |
604 | | aarch64_sysop_alias SysAlias; |
605 | | uint16_t Encoding; |
606 | | } AArch64SVEPredPattern_SVEPREDPAT; |
607 | | |
608 | | #define GET_SVEPREDPAT_DECL |
609 | | |
610 | | #include "AArch64GenSystemOperands.inc" |
611 | | |
612 | | // CS namespace end: AArch64SVEPredPattern |
613 | | |
614 | | // CS namespace begin: AArch64SVEVecLenSpecifier |
615 | | |
616 | | typedef struct SVEVECLENSPECIFIER { |
617 | | const char *Name; |
618 | | aarch64_sysop_alias SysAlias; |
619 | | uint16_t Encoding; |
620 | | } AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER; |
621 | | |
622 | | #define GET_SVEVECLENSPECIFIER_DECL |
623 | | |
624 | | #include "AArch64GenSystemOperands.inc" |
625 | | |
626 | | // CS namespace end: AArch64SVEVecLenSpecifier |
627 | | |
628 | | // namespace AArch64SVEVecLenSpecifier |
629 | | |
630 | | /// Return the number of active elements for VL1 to VL256 predicate pattern, |
631 | | /// zero for all other patterns. |
632 | | static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) |
633 | 0 | { |
634 | 0 | switch (Pattern) { |
635 | 0 | default: |
636 | 0 | return 0; |
637 | 0 | case AARCH64_SVEPREDPAT_VL1: |
638 | 0 | case AARCH64_SVEPREDPAT_VL2: |
639 | 0 | case AARCH64_SVEPREDPAT_VL3: |
640 | 0 | case AARCH64_SVEPREDPAT_VL4: |
641 | 0 | case AARCH64_SVEPREDPAT_VL5: |
642 | 0 | case AARCH64_SVEPREDPAT_VL6: |
643 | 0 | case AARCH64_SVEPREDPAT_VL7: |
644 | 0 | case AARCH64_SVEPREDPAT_VL8: |
645 | 0 | return Pattern; |
646 | 0 | case AARCH64_SVEPREDPAT_VL16: |
647 | 0 | return 16; |
648 | 0 | case AARCH64_SVEPREDPAT_VL32: |
649 | 0 | return 32; |
650 | 0 | case AARCH64_SVEPREDPAT_VL64: |
651 | 0 | return 64; |
652 | 0 | case AARCH64_SVEPREDPAT_VL128: |
653 | 0 | return 128; |
654 | 0 | case AARCH64_SVEPREDPAT_VL256: |
655 | 0 | return 256; |
656 | 0 | } |
657 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getNumElementsFromSVEPredPattern Unexecuted instantiation: AArch64BaseInfo.c:getNumElementsFromSVEPredPattern Unexecuted instantiation: AArch64Disassembler.c:getNumElementsFromSVEPredPattern Unexecuted instantiation: AArch64DisassemblerExtension.c:getNumElementsFromSVEPredPattern Unexecuted instantiation: AArch64InstPrinter.c:getNumElementsFromSVEPredPattern |
658 | | |
659 | | /// Return specific VL predicate pattern based on the number of elements. |
660 | | static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts) |
661 | 0 | { |
662 | 0 | switch (MinNumElts) { |
663 | 0 | default: |
664 | 0 | return 0; |
665 | 0 | case 1: |
666 | 0 | case 2: |
667 | 0 | case 3: |
668 | 0 | case 4: |
669 | 0 | case 5: |
670 | 0 | case 6: |
671 | 0 | case 7: |
672 | 0 | case 8: |
673 | 0 | return MinNumElts; |
674 | 0 | case 16: |
675 | 0 | return AARCH64_SVEPREDPAT_VL16; |
676 | 0 | case 32: |
677 | 0 | return AARCH64_SVEPREDPAT_VL32; |
678 | 0 | case 64: |
679 | 0 | return AARCH64_SVEPREDPAT_VL64; |
680 | 0 | case 128: |
681 | 0 | return AARCH64_SVEPREDPAT_VL128; |
682 | 0 | case 256: |
683 | 0 | return AARCH64_SVEPREDPAT_VL256; |
684 | 0 | } |
685 | 0 | } Unexecuted instantiation: AArch64Mapping.c:getSVEPredPatternFromNumElements Unexecuted instantiation: AArch64BaseInfo.c:getSVEPredPatternFromNumElements Unexecuted instantiation: AArch64Disassembler.c:getSVEPredPatternFromNumElements Unexecuted instantiation: AArch64DisassemblerExtension.c:getSVEPredPatternFromNumElements Unexecuted instantiation: AArch64InstPrinter.c:getSVEPredPatternFromNumElements |
686 | | |
687 | | // CS namespace begin: AArch64ExactFPImm |
688 | | |
689 | | typedef struct ExactFPImm { |
690 | | const char *Name; |
691 | | aarch64_sysop_imm SysImm; |
692 | | int Enum; |
693 | | const char *Repr; |
694 | | } AArch64ExactFPImm_ExactFPImm; |
695 | | |
696 | | enum { |
697 | | AArch64ExactFPImm_half = 1, |
698 | | AArch64ExactFPImm_one = 2, |
699 | | AArch64ExactFPImm_two = 3, |
700 | | AArch64ExactFPImm_zero = 0, |
701 | | }; |
702 | | |
703 | | #define GET_EXACTFPIMM_DECL |
704 | | |
705 | | #include "AArch64GenSystemOperands.inc" |
706 | | |
707 | | // CS namespace end: AArch64ExactFPImm |
708 | | |
709 | | // CS namespace begin: AArch64PState |
710 | | |
711 | | #define AArch64PState_PStateImm0_15 SysAlias |
712 | | |
713 | | #define GET_PSTATEIMM0_15_DECL |
714 | | |
715 | | #include "AArch64GenSystemOperands.inc" |
716 | | |
717 | | #define AArch64PState_PStateImm0_1 SysAlias |
718 | | |
719 | | #define GET_PSTATEIMM0_1_DECL |
720 | | |
721 | | #include "AArch64GenSystemOperands.inc" |
722 | | |
723 | | // CS namespace end: AArch64PState |
724 | | |
725 | | // CS namespace begin: AArch64PSBHint |
726 | | |
727 | | #define AArch64PSBHint_PSB SysAlias |
728 | | |
729 | | #define GET_PSB_DECL |
730 | | |
731 | | #include "AArch64GenSystemOperands.inc" |
732 | | |
733 | | // CS namespace end: AArch64PSBHint |
734 | | |
735 | | // CS namespace begin: AArch64BTIHint |
736 | | |
737 | | #define AArch64BTIHint_BTI SysAlias |
738 | | |
739 | | #define GET_BTI_DECL |
740 | | |
741 | | #include "AArch64GenSystemOperands.inc" |
742 | | |
743 | | // CS namespace end: AArch64BTIHint |
744 | | |
745 | | // CS namespace begin: AArch64SE |
746 | | |
747 | | typedef enum ShiftExtSpecifiers { |
748 | | AArch64SE_Invalid = -1, |
749 | | AArch64SE_LSL, |
750 | | AArch64SE_MSL, |
751 | | AArch64SE_LSR, |
752 | | AArch64SE_ASR, |
753 | | AArch64SE_ROR, |
754 | | |
755 | | AArch64SE_UXTB, |
756 | | AArch64SE_UXTH, |
757 | | AArch64SE_UXTW, |
758 | | AArch64SE_UXTX, |
759 | | |
760 | | AArch64SE_SXTB, |
761 | | AArch64SE_SXTH, |
762 | | AArch64SE_SXTW, |
763 | | AArch64SE_SXTX |
764 | | } AArch64SE_ShiftExtSpecifiers; |
765 | | |
766 | | // CS namespace end: AArch64SE |
767 | | |
768 | | // CS namespace begin: AArch64Layout |
769 | | |
770 | | // MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h |
771 | | // MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h |
772 | | // MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h |
773 | | |
774 | | // CS namespace end: AArch64Layout |
775 | | |
776 | | // CS namespace begin: AArch64SysReg |
777 | | |
778 | | typedef struct SysReg { |
779 | | const char *Name; |
780 | | aarch64_sysop_reg SysReg; |
781 | | const char *AltName; |
782 | | aarch64_sysop_reg AliasReg; |
783 | | unsigned Encoding; |
784 | | bool Readable; |
785 | | bool Writeable; |
786 | | aarch64_insn_group FeaturesRequired[3]; |
787 | | } AArch64SysReg_SysReg; |
788 | | |
789 | | #define GET_SYSREG_DECL |
790 | | |
791 | | #include "AArch64GenSystemOperands.inc" |
792 | | |
793 | | const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name); |
794 | | const AArch64SysReg_SysReg * |
795 | | AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding); |
796 | 5.46k | #define AARCH64_GRS_LEN 128 |
797 | | void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result); |
798 | | |
799 | | // CS namespace end: AArch64SysReg |
800 | | |
801 | | // CS namespace begin: AArch64TLBI |
802 | | |
803 | | #define AArch64TLBI_TLBI SysAliasReg |
804 | | |
805 | | #define GET_TLBITable_DECL |
806 | | |
807 | | #include "AArch64GenSystemOperands.inc" |
808 | | |
809 | | // CS namespace end: AArch64TLBI |
810 | | |
811 | | // CS namespace begin: AArch64PRCTX |
812 | | |
813 | | #define AArch64PRCTX_PRCTX SysAliasReg |
814 | | |
815 | | #define GET_PRCTX_DECL |
816 | | |
817 | | #include "AArch64GenSystemOperands.inc" |
818 | | |
819 | | // CS namespace end: AArch64PRCTX |
820 | | |
821 | | // CS namespace begin: AArch64II |
822 | | |
823 | | /// Target Operand Flag enum. |
824 | | typedef enum TOF { |
825 | | //===------------------------------------------------------------------===// |
826 | | // AArch64 Specific MachineOperand flags. |
827 | | |
828 | | AArch64II_MO_NO_FLAG, |
829 | | |
830 | | AArch64II_MO_FRAGMENT = 0x7, |
831 | | |
832 | | /// MO_PAGE - A symbol operand with this flag represents the pc-relative |
833 | | /// offset of the 4K page containing the symbol. This is used with the |
834 | | /// ADRP instruction. |
835 | | AArch64II_MO_PAGE = 1, |
836 | | |
837 | | /// MO_PAGEOFF - A symbol operand with this flag represents the offset of |
838 | | /// that symbol within a 4K page. This offset is added to the page address |
839 | | /// to produce the complete address. |
840 | | AArch64II_MO_PAGEOFF = 2, |
841 | | |
842 | | /// MO_G3 - A symbol operand with this flag (granule 3) represents the high |
843 | | /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction |
844 | | AArch64II_MO_G3 = 3, |
845 | | |
846 | | /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits |
847 | | /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction |
848 | | AArch64II_MO_G2 = 4, |
849 | | |
850 | | /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits |
851 | | /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction |
852 | | AArch64II_MO_G1 = 5, |
853 | | |
854 | | /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits |
855 | | /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction |
856 | | AArch64II_MO_G0 = 6, |
857 | | |
858 | | /// MO_HI12 - This flag indicates that a symbol operand represents the bits |
859 | | /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- |
860 | | /// by-12-bits instruction. |
861 | | AArch64II_MO_HI12 = 7, |
862 | | |
863 | | /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the |
864 | | /// reference is actually to the ".refptr.FOO" symbol. This is used for |
865 | | /// stub symbols on windows. |
866 | | AArch64II_MO_COFFSTUB = 0x8, |
867 | | |
868 | | /// MO_GOT - This flag indicates that a symbol operand represents the |
869 | | /// address of the GOT entry for the symbol, rather than the address of |
870 | | /// the symbol itself. |
871 | | AArch64II_MO_GOT = 0x10, |
872 | | |
873 | | /// MO_NC - Indicates whether the linker is expected to check the symbol |
874 | | /// reference for overflow. For example in an ADRP/ADD pair of relocations |
875 | | /// the ADRP usually does check, but not the ADD. |
876 | | AArch64II_MO_NC = 0x20, |
877 | | |
878 | | /// MO_TLS - Indicates that the operand being accessed is some kind of |
879 | | /// thread-local symbol. On Darwin, only one type of thread-local access |
880 | | /// exists (pre linker-relaxation), but on ELF the TLSModel used for the |
881 | | /// referee will affect interpretation. |
882 | | AArch64II_MO_TLS = 0x40, |
883 | | |
884 | | /// MO_DLLIMPORT - On a symbol operand, this represents that the reference |
885 | | /// to the symbol is for an import stub. This is used for DLL import |
886 | | /// storage class indication on Windows. |
887 | | AArch64II_MO_DLLIMPORT = 0x80, |
888 | | |
889 | | /// MO_S - Indicates that the bits of the symbol operand represented by |
890 | | /// MO_G0 etc are signed. |
891 | | AArch64II_MO_S = 0x100, |
892 | | |
893 | | /// MO_PREL - Indicates that the bits of the symbol operand represented by |
894 | | /// MO_G0 etc are PC relative. |
895 | | AArch64II_MO_PREL = 0x200, |
896 | | |
897 | | /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag |
898 | | /// in bits 56-63. |
899 | | /// On a FrameIndex operand, indicates that the underlying memory is tagged |
900 | | /// with an unknown tag value (MTE); this needs to be lowered either to an |
901 | | /// SP-relative load or store instruction (which do not check tags), or to |
902 | | /// an LDG instruction to obtain the tag value. |
903 | | AArch64II_MO_TAGGED = 0x400, |
904 | | |
905 | | /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version |
906 | | /// of a symbol, not the original. For dllimport symbols, this means it |
907 | | /// uses "__imp_aux". For other symbols, this means it uses the mangled |
908 | | /// ("#" prefix for C) name. |
909 | | AArch64II_MO_ARM64EC_CALLMANGLE = 0x800, |
910 | | } AArch64II_TOF; |
911 | | |
912 | | // CS namespace end: AArch64II |
913 | | |
914 | | // end namespace AArch64II |
915 | | |
916 | | //===----------------------------------------------------------------------===// |
917 | | // v8.3a Pointer Authentication |
918 | | // |
919 | | |
920 | | // CS namespace begin: AArch64PACKey |
921 | | |
922 | | typedef enum ID { |
923 | | AArch64PACKey_IA = 0, |
924 | | AArch64PACKey_IB = 1, |
925 | | AArch64PACKey_DA = 2, |
926 | | AArch64PACKey_DB = 3, |
927 | | AArch64PACKey_LAST = AArch64PACKey_DB |
928 | | } AArch64PACKey_ID; |
929 | | |
930 | | // CS namespace end: AArch64PACKey |
931 | | |
932 | | // namespace AArch64PACKey |
933 | | |
934 | | /// Return 2-letter identifier string for numeric key ID. |
935 | | static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID) |
936 | 0 | { |
937 | 0 | switch (KeyID) { |
938 | 0 | case AArch64PACKey_IA: |
939 | 0 | return "ia"; |
940 | 0 | case AArch64PACKey_IB: |
941 | 0 | return "ib"; |
942 | 0 | case AArch64PACKey_DA: |
943 | 0 | return "da"; |
944 | 0 | case AArch64PACKey_DB: |
945 | 0 | return "db"; |
946 | 0 | } |
947 | 0 | return NULL; |
948 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64PACKeyIDToString Unexecuted instantiation: AArch64BaseInfo.c:AArch64PACKeyIDToString Unexecuted instantiation: AArch64Disassembler.c:AArch64PACKeyIDToString Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64PACKeyIDToString Unexecuted instantiation: AArch64InstPrinter.c:AArch64PACKeyIDToString |
949 | | |
950 | | /// Return numeric key ID for 2-letter identifier string. |
951 | | static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name) |
952 | 0 | { |
953 | 0 | if (strcmp(Name, "ia") == 0) |
954 | 0 | return AArch64PACKey_IA; |
955 | 0 | if (strcmp(Name, "ib") == 0) |
956 | 0 | return AArch64PACKey_IB; |
957 | 0 | if (strcmp(Name, "da") == 0) |
958 | 0 | return AArch64PACKey_DA; |
959 | 0 | if (strcmp(Name, "db") == 0) |
960 | 0 | return AArch64PACKey_DB; |
961 | 0 | assert(0 && "Invalid PAC key"); |
962 | 0 | return AArch64PACKey_LAST; |
963 | 0 | } Unexecuted instantiation: AArch64Mapping.c:AArch64StringToPACKeyID Unexecuted instantiation: AArch64BaseInfo.c:AArch64StringToPACKeyID Unexecuted instantiation: AArch64Disassembler.c:AArch64StringToPACKeyID Unexecuted instantiation: AArch64DisassemblerExtension.c:AArch64StringToPACKeyID Unexecuted instantiation: AArch64InstPrinter.c:AArch64StringToPACKeyID |
964 | | |
965 | | // CS namespace begin: AArch64 |
966 | | |
967 | | // The number of bits in a SVE register is architecturally defined |
968 | | // to be a multiple of this value. If <M x t> has this number of bits, |
969 | | // a <n x M x t> vector can be stored in a SVE register without any |
970 | | // redundant bits. If <M x t> has this number of bits divided by P, |
971 | | // a <n x M x t> vector is stored in a SVE register by placing index i |
972 | | // in index i*P of a <n x (M*P) x t> vector. The other elements of the |
973 | | // <n x (M*P) x t> vector (such as index 1) are undefined. |
974 | | static const unsigned SVEBitsPerBlock = 128; |
975 | | |
976 | | static const unsigned SVEMaxBitsPerVector = 2048; |
977 | | |
978 | | // CS namespace end: AArch64 |
979 | | |
980 | | // end namespace AArch64 |
981 | | // end namespace llvm |
982 | | |
983 | | #endif |