/src/capstonenext/arch/AArch64/AArch64InstPrinter.c
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1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This class prints an AArch64 MCInst to a .s file. |
24 | | // |
25 | | //===----------------------------------------------------------------------===// |
26 | | |
27 | | #include <stdio.h> |
28 | | #include <string.h> |
29 | | #include <stdlib.h> |
30 | | #include <capstone/platform.h> |
31 | | |
32 | | #include "../../Mapping.h" |
33 | | #include "../../MCInst.h" |
34 | | #include "../../MCInstPrinter.h" |
35 | | #include "../../MCRegisterInfo.h" |
36 | | #include "../../SStream.h" |
37 | | #include "../../utils.h" |
38 | | #include "AArch64AddressingModes.h" |
39 | | #include "AArch64BaseInfo.h" |
40 | | #include "AArch64DisassemblerExtension.h" |
41 | | #include "AArch64InstPrinter.h" |
42 | | #include "AArch64Linkage.h" |
43 | | #include "AArch64Mapping.h" |
44 | | |
45 | | #define GET_BANKEDREG_IMPL |
46 | | #include "AArch64GenSystemOperands.inc" |
47 | | |
48 | 507k | #define CONCAT(a, b) CONCAT_(a, b) |
49 | 507k | #define CONCAT_(a, b) a##_##b |
50 | | |
51 | | #define CONCATs(a, b) CONCATS(a, b) |
52 | | #define CONCATS(a, b) a##b |
53 | | |
54 | | #define DEBUG_TYPE "asm-printer" |
55 | | |
56 | | // BEGIN Static declarations. |
57 | | // These functions must be declared statically here, because they |
58 | | // are also defined in the ARM module. |
59 | | // If they are not static, we fail during linking. |
60 | | |
61 | | static void printCustomAliasOperand(MCInst *MI, uint64_t Address, |
62 | | unsigned OpIdx, unsigned PrintMethodIdx, |
63 | | SStream *OS); |
64 | | |
65 | | static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
66 | | |
67 | | #define DECLARE_printComplexRotationOp(Angle, Remainder) \ |
68 | | static void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \ |
69 | | MCInst * MI, unsigned OpNo, SStream *O); |
70 | | DECLARE_printComplexRotationOp(180, 90); |
71 | | DECLARE_printComplexRotationOp(90, 0); |
72 | | |
73 | | // END Static declarations. |
74 | | |
75 | | #define GET_INSTRUCTION_NAME |
76 | | #define PRINT_ALIAS_INSTR |
77 | | #include "AArch64GenAsmWriter.inc" |
78 | | |
79 | | void printRegName(SStream *OS, unsigned Reg) |
80 | 755k | { |
81 | 755k | SStream_concat(OS, "%s%s", markup("<reg:"), |
82 | 755k | getRegisterName(Reg, AArch64_NoRegAltName)); |
83 | 755k | SStream_concat0(OS, markup(">")); |
84 | 755k | } |
85 | | |
86 | | void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx) |
87 | 125k | { |
88 | 125k | SStream_concat(OS, "%s%s", markup("<reg:"), |
89 | 125k | getRegisterName(Reg, AltIdx)); |
90 | 125k | SStream_concat0(OS, markup(">")); |
91 | 125k | } |
92 | | |
93 | | const char *getRegName(unsigned Reg) |
94 | 0 | { |
95 | 0 | return getRegisterName(Reg, AArch64_NoRegAltName); |
96 | 0 | } |
97 | | |
98 | | void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) |
99 | 337k | { |
100 | 337k | bool isAlias = false; |
101 | 337k | bool useAliasDetails = map_use_alias_details(MI); |
102 | 337k | map_set_fill_detail_ops(MI, useAliasDetails); |
103 | | |
104 | 337k | unsigned Opcode = MCInst_getOpcode(MI); |
105 | | |
106 | 337k | if (Opcode == AArch64_SYSxt) { |
107 | 2.03k | if (printSysAlias(MI, O)) { |
108 | 398 | isAlias = true; |
109 | 398 | MCInst_setIsAlias(MI, isAlias); |
110 | 398 | if (useAliasDetails) |
111 | 398 | return; |
112 | 398 | } |
113 | 2.03k | } |
114 | | |
115 | 337k | if (Opcode == AArch64_SYSPxt || Opcode == AArch64_SYSPxt_XZR) { |
116 | 1.42k | if (printSyspAlias(MI, O)) { |
117 | 926 | isAlias = true; |
118 | 926 | MCInst_setIsAlias(MI, isAlias); |
119 | 926 | if (useAliasDetails) |
120 | 926 | return; |
121 | 926 | } |
122 | 1.42k | } |
123 | | |
124 | | // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here. |
125 | 336k | if ((Opcode == AArch64_PRFMroX) || (Opcode == AArch64_PRFMroW)) { |
126 | 716 | if (printRangePrefetchAlias(MI, O, Annot)) { |
127 | 0 | isAlias = true; |
128 | 0 | MCInst_setIsAlias(MI, isAlias); |
129 | 0 | if (useAliasDetails) |
130 | 0 | return; |
131 | 0 | } |
132 | 716 | } |
133 | | |
134 | | // SBFM/UBFM should print to a nicer aliased form if possible. |
135 | 336k | if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || |
136 | 336k | Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { |
137 | 3.24k | MCOperand *Op0 = MCInst_getOperand(MI, (0)); |
138 | 3.24k | MCOperand *Op1 = MCInst_getOperand(MI, (1)); |
139 | 3.24k | MCOperand *Op2 = MCInst_getOperand(MI, (2)); |
140 | 3.24k | MCOperand *Op3 = MCInst_getOperand(MI, (3)); |
141 | | |
142 | 3.24k | bool IsSigned = (Opcode == AArch64_SBFMXri || |
143 | 3.24k | Opcode == AArch64_SBFMWri); |
144 | 3.24k | bool Is64Bit = (Opcode == AArch64_SBFMXri || |
145 | 3.24k | Opcode == AArch64_UBFMXri); |
146 | 3.24k | if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && |
147 | 3.24k | MCOperand_isImm(Op3)) { |
148 | 2.04k | const char *AsmMnemonic = NULL; |
149 | | |
150 | 2.04k | switch (MCOperand_getImm(Op3)) { |
151 | 232 | default: |
152 | 232 | break; |
153 | 1.02k | case 7: |
154 | 1.02k | if (IsSigned) |
155 | 994 | AsmMnemonic = "sxtb"; |
156 | 28 | else if (!Is64Bit) |
157 | 10 | AsmMnemonic = "uxtb"; |
158 | 1.02k | break; |
159 | 346 | case 15: |
160 | 346 | if (IsSigned) |
161 | 280 | AsmMnemonic = "sxth"; |
162 | 66 | else if (!Is64Bit) |
163 | 54 | AsmMnemonic = "uxth"; |
164 | 346 | break; |
165 | 442 | case 31: |
166 | | // *xtw is only valid for signed 64-bit operations. |
167 | 442 | if (Is64Bit && IsSigned) |
168 | 396 | AsmMnemonic = "sxtw"; |
169 | 442 | break; |
170 | 2.04k | } |
171 | | |
172 | 2.04k | if (AsmMnemonic) { |
173 | 1.73k | SStream_concat(O, "%s", AsmMnemonic); |
174 | 1.73k | SStream_concat0(O, " "); |
175 | | |
176 | 1.73k | printRegName(O, MCOperand_getReg(Op0)); |
177 | 1.73k | SStream_concat0(O, ", "); |
178 | 1.73k | printRegName(O, getWRegFromXReg( |
179 | 1.73k | MCOperand_getReg(Op1))); |
180 | 1.73k | if (detail_is_set(MI) && useAliasDetails) { |
181 | 1.73k | AArch64_set_detail_op_reg( |
182 | 1.73k | MI, 0, MCOperand_getReg(Op0)); |
183 | 1.73k | AArch64_set_detail_op_reg( |
184 | 1.73k | MI, 1, |
185 | 1.73k | getWRegFromXReg( |
186 | 1.73k | MCOperand_getReg(Op1))); |
187 | 1.73k | if (strings_match(AsmMnemonic, "uxtb")) |
188 | 10 | AArch64_get_detail_op(MI, -1) |
189 | 10 | ->ext = |
190 | 10 | AARCH64_EXT_UXTB; |
191 | 1.72k | else if (strings_match(AsmMnemonic, |
192 | 1.72k | "sxtb")) |
193 | 994 | AArch64_get_detail_op(MI, -1) |
194 | 994 | ->ext = |
195 | 994 | AARCH64_EXT_SXTB; |
196 | 730 | else if (strings_match(AsmMnemonic, |
197 | 730 | "uxth")) |
198 | 54 | AArch64_get_detail_op(MI, -1) |
199 | 54 | ->ext = |
200 | 54 | AARCH64_EXT_UXTH; |
201 | 676 | else if (strings_match(AsmMnemonic, |
202 | 676 | "sxth")) |
203 | 280 | AArch64_get_detail_op(MI, -1) |
204 | 280 | ->ext = |
205 | 280 | AARCH64_EXT_SXTH; |
206 | 396 | else if (strings_match(AsmMnemonic, |
207 | 396 | "sxtw")) |
208 | 396 | AArch64_get_detail_op(MI, -1) |
209 | 396 | ->ext = |
210 | 396 | AARCH64_EXT_SXTW; |
211 | 0 | else |
212 | 0 | AArch64_get_detail_op(MI, -1) |
213 | 0 | ->ext = |
214 | 0 | AARCH64_EXT_INVALID; |
215 | 1.73k | } |
216 | 1.73k | isAlias = true; |
217 | 1.73k | MCInst_setIsAlias(MI, isAlias); |
218 | 1.73k | if (useAliasDetails) |
219 | 1.73k | return; |
220 | 0 | else |
221 | 0 | goto add_real_detail; |
222 | 1.73k | } |
223 | 2.04k | } |
224 | | |
225 | | // All immediate shifts are aliases, implemented using the Bitfield |
226 | | // instruction. In all cases the immediate shift amount shift must be in |
227 | | // the range 0 to (reg.size -1). |
228 | 1.50k | if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { |
229 | 1.50k | const char *AsmMnemonic = NULL; |
230 | 1.50k | int shift = 0; |
231 | 1.50k | int64_t immr = MCOperand_getImm(Op2); |
232 | 1.50k | int64_t imms = MCOperand_getImm(Op3); |
233 | 1.50k | if (Opcode == AArch64_UBFMWri && imms != 0x1F && |
234 | 1.50k | ((imms + 1) == immr)) { |
235 | 85 | AsmMnemonic = "lsl"; |
236 | 85 | shift = 31 - imms; |
237 | 1.42k | } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && |
238 | 1.42k | ((imms + 1 == immr))) { |
239 | 23 | AsmMnemonic = "lsl"; |
240 | 23 | shift = 63 - imms; |
241 | 1.40k | } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { |
242 | 29 | AsmMnemonic = "lsr"; |
243 | 29 | shift = immr; |
244 | 1.37k | } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { |
245 | 18 | AsmMnemonic = "lsr"; |
246 | 18 | shift = immr; |
247 | 1.35k | } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { |
248 | 16 | AsmMnemonic = "asr"; |
249 | 16 | shift = immr; |
250 | 1.33k | } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { |
251 | 17 | AsmMnemonic = "asr"; |
252 | 17 | shift = immr; |
253 | 17 | } |
254 | 1.50k | if (AsmMnemonic) { |
255 | 188 | SStream_concat(O, "%s", AsmMnemonic); |
256 | 188 | SStream_concat0(O, " "); |
257 | | |
258 | 188 | printRegName(O, MCOperand_getReg(Op0)); |
259 | 188 | SStream_concat0(O, ", "); |
260 | 188 | printRegName(O, MCOperand_getReg(Op1)); |
261 | 188 | SStream_concat(O, "%s%s#%d", ", ", |
262 | 188 | markup("<imm:"), shift); |
263 | 188 | SStream_concat0(O, markup(">")); |
264 | 188 | if (detail_is_set(MI) && useAliasDetails) { |
265 | 188 | AArch64_set_detail_op_reg( |
266 | 188 | MI, 0, MCOperand_getReg(Op0)); |
267 | 188 | AArch64_set_detail_op_reg( |
268 | 188 | MI, 1, MCOperand_getReg(Op1)); |
269 | 188 | if (strings_match(AsmMnemonic, "lsl")) |
270 | 108 | AArch64_get_detail_op(MI, -1) |
271 | 108 | ->shift.type = |
272 | 108 | AARCH64_SFT_LSL; |
273 | 80 | else if (strings_match(AsmMnemonic, |
274 | 80 | "lsr")) |
275 | 47 | AArch64_get_detail_op(MI, -1) |
276 | 47 | ->shift.type = |
277 | 47 | AARCH64_SFT_LSR; |
278 | 33 | else if (strings_match(AsmMnemonic, |
279 | 33 | "asr")) |
280 | 33 | AArch64_get_detail_op(MI, -1) |
281 | 33 | ->shift.type = |
282 | 33 | AARCH64_SFT_ASR; |
283 | 0 | else |
284 | 0 | AArch64_get_detail_op(MI, -1) |
285 | 0 | ->shift.type = |
286 | 0 | AARCH64_SFT_INVALID; |
287 | 188 | AArch64_get_detail_op(MI, -1) |
288 | 188 | ->shift.value = shift; |
289 | 188 | } |
290 | 188 | isAlias = true; |
291 | 188 | MCInst_setIsAlias(MI, isAlias); |
292 | 188 | if (useAliasDetails) |
293 | 188 | return; |
294 | 0 | else |
295 | 0 | goto add_real_detail; |
296 | 188 | } |
297 | 1.50k | } |
298 | | |
299 | | // SBFIZ/UBFIZ aliases |
300 | 1.32k | if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { |
301 | 845 | SStream_concat(O, "%s", (IsSigned ? "sbfiz" : "ubfiz")); |
302 | 845 | SStream_concat0(O, " "); |
303 | | |
304 | 845 | printRegName(O, MCOperand_getReg(Op0)); |
305 | 845 | SStream_concat0(O, ", "); |
306 | 845 | printRegName(O, MCOperand_getReg(Op1)); |
307 | 845 | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
308 | 845 | printUInt32Bang(O, (Is64Bit ? 64 : 32) - |
309 | 845 | MCOperand_getImm(Op2)); |
310 | 845 | SStream_concat(O, "%s%s%s", markup(">"), ", ", |
311 | 845 | markup("<imm:")); |
312 | 845 | printInt64Bang(O, MCOperand_getImm(Op3) + 1); |
313 | 845 | SStream_concat0(O, markup(">")); |
314 | 845 | if (detail_is_set(MI) && useAliasDetails) { |
315 | 845 | AArch64_set_detail_op_reg( |
316 | 845 | MI, 0, MCOperand_getReg(Op0)); |
317 | 845 | AArch64_set_detail_op_reg( |
318 | 845 | MI, 1, MCOperand_getReg(Op1)); |
319 | 845 | AArch64_set_detail_op_imm( |
320 | 845 | MI, 2, AARCH64_OP_IMM, |
321 | 845 | (Is64Bit ? 64 : 32) - |
322 | 845 | MCOperand_getImm(Op2)); |
323 | 845 | AArch64_set_detail_op_imm( |
324 | 845 | MI, 3, AARCH64_OP_IMM, |
325 | 845 | MCOperand_getImm(Op3) + 1); |
326 | 845 | } |
327 | 845 | isAlias = true; |
328 | 845 | MCInst_setIsAlias(MI, isAlias); |
329 | 845 | if (useAliasDetails) |
330 | 845 | return; |
331 | 0 | else |
332 | 0 | goto add_real_detail; |
333 | 845 | } |
334 | | |
335 | | // Otherwise SBFX/UBFX is the preferred form |
336 | 476 | SStream_concat(O, "%s", (IsSigned ? "sbfx" : "ubfx")); |
337 | 476 | SStream_concat0(O, " "); |
338 | | |
339 | 476 | printRegName(O, MCOperand_getReg(Op0)); |
340 | 476 | SStream_concat0(O, ", "); |
341 | 476 | printRegName(O, MCOperand_getReg(Op1)); |
342 | 476 | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
343 | 476 | printInt64Bang(O, MCOperand_getImm(Op2)); |
344 | 476 | SStream_concat(O, "%s%s%s", markup(">"), ", ", markup("<imm:")); |
345 | 476 | printInt64Bang(O, MCOperand_getImm(Op3) - |
346 | 476 | MCOperand_getImm(Op2) + 1); |
347 | 476 | SStream_concat0(O, markup(">")); |
348 | 476 | if (detail_is_set(MI) && useAliasDetails) { |
349 | 476 | AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0)); |
350 | 476 | AArch64_set_detail_op_reg(MI, 1, MCOperand_getReg(Op1)); |
351 | 476 | AArch64_set_detail_op_imm(MI, 2, AARCH64_OP_IMM, |
352 | 476 | MCOperand_getImm(Op2)); |
353 | 476 | AArch64_set_detail_op_imm( |
354 | 476 | MI, 3, AARCH64_OP_IMM, |
355 | 476 | MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + |
356 | 476 | 1); |
357 | 476 | } |
358 | 476 | isAlias = true; |
359 | 476 | MCInst_setIsAlias(MI, isAlias); |
360 | 476 | if (useAliasDetails) |
361 | 476 | return; |
362 | 0 | else |
363 | 0 | goto add_real_detail; |
364 | 476 | } |
365 | | |
366 | 332k | if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { |
367 | 561 | isAlias = true; |
368 | 561 | MCInst_setIsAlias(MI, isAlias); |
369 | 561 | MCOperand *Op0 = MCInst_getOperand(MI, (0)); // Op1 == Op0 |
370 | 561 | MCOperand *Op2 = MCInst_getOperand(MI, (2)); |
371 | 561 | int ImmR = MCOperand_getImm(MCInst_getOperand(MI, (3))); |
372 | 561 | int ImmS = MCOperand_getImm(MCInst_getOperand(MI, (4))); |
373 | | |
374 | 561 | if ((MCOperand_getReg(Op2) == AArch64_WZR || |
375 | 561 | MCOperand_getReg(Op2) == AArch64_XZR) && |
376 | 561 | (ImmR == 0 || ImmS < ImmR) && |
377 | 561 | (AArch64_getFeatureBits(MI->csh->mode, |
378 | 71 | AArch64_FeatureAll) || |
379 | 71 | AArch64_getFeatureBits(MI->csh->mode, |
380 | 71 | AArch64_HasV8_2aOps))) { |
381 | | // BFC takes precedence over its entire range, sligtly differently |
382 | | // to BFI. |
383 | 71 | int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; |
384 | 71 | int LSB = (BitWidth - ImmR) % BitWidth; |
385 | 71 | int Width = ImmS + 1; |
386 | | |
387 | 71 | SStream_concat0(O, "bfc "); |
388 | 71 | printRegName(O, MCOperand_getReg(Op0)); |
389 | 71 | SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), |
390 | 71 | LSB); |
391 | 71 | SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", |
392 | 71 | markup("<imm:"), Width); |
393 | 71 | SStream_concat0(O, markup(">")); |
394 | 71 | if (detail_is_set(MI) && useAliasDetails) { |
395 | 71 | AArch64_set_detail_op_reg( |
396 | 71 | MI, 0, MCOperand_getReg(Op0)); |
397 | 71 | AArch64_set_detail_op_imm(MI, 3, AARCH64_OP_IMM, |
398 | 71 | LSB); |
399 | 71 | AArch64_set_detail_op_imm(MI, 4, AARCH64_OP_IMM, |
400 | 71 | Width); |
401 | 71 | } |
402 | | |
403 | 71 | if (useAliasDetails) |
404 | 71 | return; |
405 | 0 | else |
406 | 0 | goto add_real_detail; |
407 | 490 | } else if (ImmS < ImmR) { |
408 | | // BFI alias |
409 | 128 | int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; |
410 | 128 | int LSB = (BitWidth - ImmR) % BitWidth; |
411 | 128 | int Width = ImmS + 1; |
412 | | |
413 | 128 | SStream_concat0(O, "bfi "); |
414 | 128 | printRegName(O, MCOperand_getReg(Op0)); |
415 | 128 | SStream_concat0(O, ", "); |
416 | 128 | printRegName(O, MCOperand_getReg(Op2)); |
417 | 128 | SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), |
418 | 128 | LSB); |
419 | 128 | SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", |
420 | 128 | markup("<imm:"), Width); |
421 | 128 | SStream_concat0(O, markup(">")); |
422 | 128 | if (detail_is_set(MI) && useAliasDetails) { |
423 | 128 | AArch64_set_detail_op_reg( |
424 | 128 | MI, 0, MCOperand_getReg(Op0)); |
425 | 128 | AArch64_set_detail_op_reg( |
426 | 128 | MI, 2, MCOperand_getReg(Op2)); |
427 | 128 | AArch64_set_detail_op_imm(MI, 3, AARCH64_OP_IMM, |
428 | 128 | LSB); |
429 | 128 | AArch64_set_detail_op_imm(MI, 4, AARCH64_OP_IMM, |
430 | 128 | Width); |
431 | 128 | } |
432 | 128 | if (useAliasDetails) |
433 | 128 | return; |
434 | 0 | else |
435 | 0 | goto add_real_detail; |
436 | 128 | } |
437 | | |
438 | 362 | int LSB = ImmR; |
439 | 362 | int Width = ImmS - ImmR + 1; |
440 | | // Otherwise BFXIL the preferred form |
441 | 362 | SStream_concat0(O, "bfxil "); |
442 | 362 | printRegName(O, MCOperand_getReg(Op0)); |
443 | 362 | SStream_concat0(O, ", "); |
444 | 362 | printRegName(O, MCOperand_getReg(Op2)); |
445 | 362 | SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), LSB); |
446 | 362 | SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", |
447 | 362 | markup("<imm:"), Width); |
448 | 362 | SStream_concat0(O, markup(">")); |
449 | 362 | if (detail_is_set(MI) && useAliasDetails) { |
450 | 362 | AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0)); |
451 | 362 | AArch64_set_detail_op_reg(MI, 2, MCOperand_getReg(Op2)); |
452 | 362 | AArch64_set_detail_op_imm(MI, 3, AARCH64_OP_IMM, LSB); |
453 | 362 | AArch64_set_detail_op_imm(MI, 4, AARCH64_OP_IMM, Width); |
454 | 362 | } |
455 | 362 | if (useAliasDetails) |
456 | 362 | return; |
457 | 362 | } |
458 | | |
459 | | // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift |
460 | | // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be |
461 | | // printed. |
462 | 332k | if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi || |
463 | 332k | Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && |
464 | 332k | MCOperand_isExpr(MCInst_getOperand(MI, (1)))) { |
465 | 0 | SStream_concat0(O, "<llvm-expr>"); |
466 | 0 | } |
467 | | |
468 | 332k | if ((Opcode == AArch64_MOVKXi || Opcode == AArch64_MOVKWi) && |
469 | 332k | MCOperand_isExpr(MCInst_getOperand(MI, (2)))) { |
470 | 0 | SStream_concat0(O, "<llvm-expr>"); |
471 | 0 | } |
472 | | |
473 | | // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but |
474 | | // their domains overlap so they need to be prioritized. The chain is "MOVZ |
475 | | // lsl #0 > MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest |
476 | | // instruction that can represent the move is the MOV alias, and the rest |
477 | | // get printed normally. |
478 | 332k | if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && |
479 | 332k | MCOperand_isImm(MCInst_getOperand(MI, (1))) && |
480 | 332k | MCOperand_isImm(MCInst_getOperand(MI, (2)))) { |
481 | 1.14k | int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; |
482 | 1.14k | int Shift = MCOperand_getImm(MCInst_getOperand(MI, (2))); |
483 | 1.14k | uint64_t Value = |
484 | 1.14k | (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, (1))) |
485 | 1.14k | << Shift; |
486 | | |
487 | 1.14k | if (AArch64_AM_isMOVZMovAlias( |
488 | 1.14k | Value, Shift, Opcode == AArch64_MOVZXi ? 64 : 32)) { |
489 | 1.06k | isAlias = true; |
490 | 1.06k | MCInst_setIsAlias(MI, isAlias); |
491 | 1.06k | SStream_concat0(O, "mov "); |
492 | 1.06k | printRegName(O, MCOperand_getReg( |
493 | 1.06k | MCInst_getOperand(MI, (0)))); |
494 | 1.06k | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
495 | 1.06k | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
496 | 1.06k | SStream_concat0(O, markup(">")); |
497 | 1.06k | if (detail_is_set(MI) && useAliasDetails) { |
498 | 1.06k | AArch64_set_detail_op_reg( |
499 | 1.06k | MI, 0, MCInst_getOpVal(MI, 0)); |
500 | 1.06k | AArch64_set_detail_op_imm( |
501 | 1.06k | MI, 1, AARCH64_OP_IMM, |
502 | 1.06k | SignExtend64(Value, RegWidth)); |
503 | 1.06k | } |
504 | 1.06k | if (useAliasDetails) |
505 | 1.06k | return; |
506 | 1.06k | } |
507 | 1.14k | } |
508 | | |
509 | 331k | if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && |
510 | 331k | MCOperand_isImm(MCInst_getOperand(MI, (1))) && |
511 | 331k | MCOperand_isImm(MCInst_getOperand(MI, (2)))) { |
512 | 953 | int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; |
513 | 953 | int Shift = MCOperand_getImm(MCInst_getOperand(MI, (2))); |
514 | 953 | uint64_t Value = |
515 | 953 | ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, (1))) |
516 | 953 | << Shift); |
517 | 953 | if (RegWidth == 32) |
518 | 218 | Value = Value & 0xffffffff; |
519 | | |
520 | 953 | if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { |
521 | 866 | isAlias = true; |
522 | 866 | MCInst_setIsAlias(MI, isAlias); |
523 | 866 | SStream_concat0(O, "mov "); |
524 | 866 | printRegName(O, MCOperand_getReg( |
525 | 866 | MCInst_getOperand(MI, (0)))); |
526 | 866 | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
527 | 866 | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
528 | 866 | SStream_concat0(O, markup(">")); |
529 | 866 | if (detail_is_set(MI) && useAliasDetails) { |
530 | 866 | AArch64_set_detail_op_reg( |
531 | 866 | MI, 0, MCInst_getOpVal(MI, 0)); |
532 | 866 | AArch64_set_detail_op_imm( |
533 | 866 | MI, 1, AARCH64_OP_IMM, |
534 | 866 | SignExtend64(Value, RegWidth)); |
535 | 866 | } |
536 | 866 | if (useAliasDetails) |
537 | 866 | return; |
538 | 866 | } |
539 | 953 | } |
540 | | |
541 | 330k | if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && |
542 | 330k | (MCOperand_getReg(MCInst_getOperand(MI, (1))) == AArch64_XZR || |
543 | 2.19k | MCOperand_getReg(MCInst_getOperand(MI, (1))) == AArch64_WZR) && |
544 | 330k | MCOperand_isImm(MCInst_getOperand(MI, (2)))) { |
545 | 867 | int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; |
546 | 867 | uint64_t Value = AArch64_AM_decodeLogicalImmediate( |
547 | 867 | MCOperand_getImm(MCInst_getOperand(MI, (2))), RegWidth); |
548 | 867 | if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) { |
549 | 511 | isAlias = true; |
550 | 511 | MCInst_setIsAlias(MI, isAlias); |
551 | 511 | SStream_concat0(O, "mov "); |
552 | 511 | printRegName(O, MCOperand_getReg( |
553 | 511 | MCInst_getOperand(MI, (0)))); |
554 | 511 | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
555 | 511 | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
556 | 511 | SStream_concat0(O, markup(">")); |
557 | 511 | if (detail_is_set(MI) && useAliasDetails) { |
558 | 511 | AArch64_set_detail_op_reg( |
559 | 511 | MI, 0, MCInst_getOpVal(MI, 0)); |
560 | 511 | AArch64_set_detail_op_imm( |
561 | 511 | MI, 2, AARCH64_OP_IMM, |
562 | 511 | SignExtend64(Value, RegWidth)); |
563 | 511 | } |
564 | 511 | if (useAliasDetails) |
565 | 511 | return; |
566 | 511 | } |
567 | 867 | } |
568 | | |
569 | 329k | if (Opcode == AArch64_SPACE) { |
570 | 0 | isAlias = true; |
571 | 0 | MCInst_setIsAlias(MI, isAlias); |
572 | 0 | SStream_concat1(O, ' '); |
573 | 0 | SStream_concat(O, "%s", " SPACE "); |
574 | 0 | printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (1)))); |
575 | 0 | if (detail_is_set(MI) && useAliasDetails) { |
576 | 0 | AArch64_set_detail_op_imm(MI, 1, AARCH64_OP_IMM, |
577 | 0 | MCInst_getOpVal(MI, 1)); |
578 | 0 | } |
579 | 0 | if (useAliasDetails) |
580 | 0 | return; |
581 | 0 | } |
582 | | |
583 | 329k | if (!isAlias) |
584 | 329k | isAlias |= printAliasInstr(MI, Address, O); |
585 | | |
586 | 329k | add_real_detail: |
587 | 329k | MCInst_setIsAlias(MI, isAlias); |
588 | | |
589 | 329k | if (!isAlias || !useAliasDetails) { |
590 | 308k | map_set_fill_detail_ops(MI, !(isAlias && useAliasDetails)); |
591 | 308k | if (isAlias) |
592 | 0 | SStream_Close(O); |
593 | 308k | printInstruction(MI, Address, O); |
594 | 308k | if (isAlias) |
595 | 0 | SStream_Open(O); |
596 | 308k | } |
597 | 329k | } |
598 | | |
599 | | bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot) |
600 | 716 | { |
601 | 716 | unsigned Opcode = MCInst_getOpcode(MI); |
602 | | |
603 | 716 | #ifndef NDEBUG |
604 | | |
605 | 716 | #endif |
606 | | |
607 | 716 | unsigned PRFOp = MCOperand_getImm(MCInst_getOperand(MI, (0))); |
608 | 716 | unsigned Mask = 0x18; // 0b11000 |
609 | 716 | if ((PRFOp & Mask) != Mask) |
610 | 716 | return false; // Rt != '11xxx', it's a PRFM instruction. |
611 | | |
612 | 0 | unsigned Rm = MCOperand_getReg(MCInst_getOperand(MI, (2))); |
613 | | |
614 | | // "Rm" must be a 64-bit GPR for RPRFM. |
615 | 0 | if (MCRegisterInfo_getRegClass(MI->MRI, Rm)) |
616 | 0 | Rm = MCRegisterInfo_getMatchingSuperReg( |
617 | 0 | MI->MRI, Rm, AArch64_sub_32, |
618 | 0 | MCRegisterInfo_getRegClass(MI->MRI, Rm)); |
619 | |
|
620 | 0 | unsigned SignExtend = MCOperand_getImm( |
621 | 0 | MCInst_getOperand(MI, (3))); // encoded in "option<2>". |
622 | 0 | unsigned Shift = |
623 | 0 | MCOperand_getImm(MCInst_getOperand(MI, (4))); // encoded in "S". |
624 | |
|
625 | 0 | unsigned Option0 = (Opcode == AArch64_PRFMroX) ? 1 : 0; |
626 | | |
627 | | // encoded in "option<2>:option<0>:S:Rt<2:0>". |
628 | 0 | unsigned RPRFOp = (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | |
629 | 0 | (PRFOp & 0x7); |
630 | |
|
631 | 0 | SStream_concat0(O, "rprfm "); |
632 | 0 | const AArch64RPRFM_RPRFM *RPRFM = |
633 | 0 | AArch64RPRFM_lookupRPRFMByEncoding(RPRFOp); |
634 | 0 | if (RPRFM) { |
635 | 0 | SStream_concat0(O, RPRFM->Name); |
636 | 0 | } else { |
637 | 0 | printUInt32Bang(O, RPRFOp); |
638 | 0 | SStream_concat(O, ", "); |
639 | 0 | } |
640 | 0 | SStream_concat0(O, getRegisterName(Rm, AArch64_NoRegAltName)); |
641 | 0 | SStream_concat0(O, ", ["); |
642 | 0 | printOperand(MI, 1, O); // "Rn". |
643 | 0 | SStream_concat0(O, "]"); |
644 | |
|
645 | 0 | return true; |
646 | 716 | } |
647 | | |
648 | | bool printSysAlias(MCInst *MI, SStream *O) |
649 | 2.03k | { |
650 | 2.03k | MCOperand *Op1 = MCInst_getOperand(MI, (0)); |
651 | 2.03k | MCOperand *Cn = MCInst_getOperand(MI, (1)); |
652 | 2.03k | MCOperand *Cm = MCInst_getOperand(MI, (2)); |
653 | 2.03k | MCOperand *Op2 = MCInst_getOperand(MI, (3)); |
654 | | |
655 | 2.03k | unsigned Op1Val = MCOperand_getImm(Op1); |
656 | 2.03k | unsigned CnVal = MCOperand_getImm(Cn); |
657 | 2.03k | unsigned CmVal = MCOperand_getImm(Cm); |
658 | 2.03k | unsigned Op2Val = MCOperand_getImm(Op2); |
659 | | |
660 | 2.03k | uint16_t Encoding = Op2Val; |
661 | 2.03k | Encoding |= CmVal << 3; |
662 | 2.03k | Encoding |= CnVal << 7; |
663 | 2.03k | Encoding |= Op1Val << 11; |
664 | | |
665 | 2.03k | bool NeedsReg; |
666 | 2.03k | const char *Ins; |
667 | 2.03k | const char *Name; |
668 | | |
669 | 2.03k | if (CnVal == 7) { |
670 | 1.21k | switch (CmVal) { |
671 | 59 | default: |
672 | 59 | return false; |
673 | | // Maybe IC, maybe Prediction Restriction |
674 | 135 | case 1: |
675 | 135 | switch (Op1Val) { |
676 | 12 | default: |
677 | 12 | return false; |
678 | 31 | case 0: |
679 | 31 | goto Search_IC; |
680 | 92 | case 3: |
681 | 92 | goto Search_PRCTX; |
682 | 135 | } |
683 | | // Prediction Restriction aliases |
684 | 244 | case 3: { |
685 | 336 | Search_PRCTX: |
686 | 336 | if (Op1Val != 3 || CnVal != 7 || CmVal != 3) |
687 | 97 | return false; |
688 | | |
689 | 239 | unsigned int Requires = |
690 | 239 | Op2Val == 6 ? AArch64_FeatureSPECRES2 : |
691 | 239 | AArch64_FeaturePredRes; |
692 | 239 | if (!(AArch64_getFeatureBits(MI->csh->mode, |
693 | 239 | AArch64_FeatureAll) || |
694 | 239 | AArch64_getFeatureBits(MI->csh->mode, Requires))) |
695 | 0 | return false; |
696 | | |
697 | 239 | NeedsReg = true; |
698 | 239 | switch (Op2Val) { |
699 | 53 | default: |
700 | 53 | return false; |
701 | 18 | case 4: |
702 | 18 | Ins = "cfp "; |
703 | 18 | break; |
704 | 0 | case 5: |
705 | 0 | Ins = "dvp "; |
706 | 0 | break; |
707 | 159 | case 6: |
708 | 159 | Ins = "cosp "; |
709 | 159 | break; |
710 | 9 | case 7: |
711 | 9 | Ins = "cpp "; |
712 | 9 | break; |
713 | 239 | } |
714 | 186 | Name = "RCTX"; |
715 | 186 | } break; |
716 | | // IC aliases |
717 | 414 | case 5: { |
718 | 445 | Search_IC: { |
719 | 445 | const AArch64IC_IC *IC = AArch64IC_lookupICByEncoding(Encoding); |
720 | 445 | if (!IC || |
721 | 445 | !AArch64_testFeatureList(MI->csh->mode, IC->FeaturesRequired)) |
722 | 431 | return false; |
723 | 14 | if (detail_is_set(MI)) { |
724 | 14 | aarch64_sysop sysop; |
725 | 14 | sysop.reg = IC->SysReg; |
726 | 14 | sysop.sub_type = AARCH64_OP_IC; |
727 | 14 | AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; |
728 | 14 | AArch64_get_detail_op(MI, 0)->sysop = sysop; |
729 | 14 | AArch64_inc_op_count(MI); |
730 | 14 | } |
731 | | |
732 | 14 | NeedsReg = IC->NeedsReg; |
733 | 14 | Ins = "ic "; |
734 | 14 | Name = IC->Name; |
735 | 14 | } |
736 | 14 | } break; |
737 | | // DC aliases |
738 | 20 | case 4: |
739 | 33 | case 6: |
740 | 138 | case 10: |
741 | 150 | case 11: |
742 | 163 | case 12: |
743 | 180 | case 13: |
744 | 191 | case 14: { |
745 | 191 | const AArch64DC_DC *DC = |
746 | 191 | AArch64DC_lookupDCByEncoding(Encoding); |
747 | 191 | if (!DC || !AArch64_testFeatureList( |
748 | 37 | MI->csh->mode, DC->FeaturesRequired)) |
749 | 154 | return false; |
750 | 37 | if (detail_is_set(MI)) { |
751 | 37 | aarch64_sysop sysop; |
752 | 37 | sysop.alias = DC->SysAlias; |
753 | 37 | sysop.sub_type = AARCH64_OP_DC; |
754 | 37 | AArch64_get_detail_op(MI, 0)->type = |
755 | 37 | AARCH64_OP_SYSALIAS; |
756 | 37 | AArch64_get_detail_op(MI, 0)->sysop = sysop; |
757 | 37 | AArch64_inc_op_count(MI); |
758 | 37 | } |
759 | | |
760 | 37 | NeedsReg = true; |
761 | 37 | Ins = "dc "; |
762 | 37 | Name = DC->Name; |
763 | 37 | } break; |
764 | | // AT aliases |
765 | 41 | case 8: |
766 | 175 | case 9: { |
767 | 175 | const AArch64AT_AT *AT = |
768 | 175 | AArch64AT_lookupATByEncoding(Encoding); |
769 | 175 | if (!AT || !AArch64_testFeatureList( |
770 | 41 | MI->csh->mode, AT->FeaturesRequired)) |
771 | 134 | return false; |
772 | | |
773 | 41 | if (detail_is_set(MI)) { |
774 | 41 | aarch64_sysop sysop; |
775 | 41 | sysop.alias = AT->SysAlias; |
776 | 41 | sysop.sub_type = AARCH64_OP_AT; |
777 | 41 | AArch64_get_detail_op(MI, 0)->type = |
778 | 41 | AARCH64_OP_SYSALIAS; |
779 | 41 | AArch64_get_detail_op(MI, 0)->sysop = sysop; |
780 | 41 | AArch64_inc_op_count(MI); |
781 | 41 | } |
782 | 41 | NeedsReg = true; |
783 | 41 | Ins = "at "; |
784 | 41 | Name = AT->Name; |
785 | 41 | } break; |
786 | 1.21k | } |
787 | 1.21k | } else if (CnVal == 8 || CnVal == 9) { |
788 | | // TLBI aliases |
789 | 259 | const AArch64TLBI_TLBI *TLBI = |
790 | 259 | AArch64TLBI_lookupTLBIByEncoding(Encoding); |
791 | 259 | if (!TLBI || !AArch64_testFeatureList(MI->csh->mode, |
792 | 120 | TLBI->FeaturesRequired)) |
793 | 139 | return false; |
794 | | |
795 | 120 | if (detail_is_set(MI)) { |
796 | 120 | aarch64_sysop sysop; |
797 | 120 | sysop.reg = TLBI->SysReg; |
798 | 120 | sysop.sub_type = AARCH64_OP_TLBI; |
799 | 120 | AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; |
800 | 120 | AArch64_get_detail_op(MI, 0)->sysop = sysop; |
801 | 120 | AArch64_inc_op_count(MI); |
802 | 120 | } |
803 | 120 | NeedsReg = TLBI->NeedsReg; |
804 | 120 | Ins = "tlbi "; |
805 | 120 | Name = TLBI->Name; |
806 | 120 | } else |
807 | 560 | return false; |
808 | | |
809 | 796 | #define TMP_STR_LEN 32 |
810 | 398 | char Str[TMP_STR_LEN] = { 0 }; |
811 | 398 | append_to_str_lower(Str, TMP_STR_LEN, Ins); |
812 | 398 | append_to_str_lower(Str, TMP_STR_LEN, Name); |
813 | 398 | #undef TMP_STR_LEN |
814 | | |
815 | 398 | SStream_concat1(O, ' '); |
816 | 398 | SStream_concat0(O, Str); |
817 | 398 | if (NeedsReg) { |
818 | 273 | SStream_concat0(O, ", "); |
819 | 273 | printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (4)))); |
820 | 273 | AArch64_set_detail_op_reg(MI, 4, MCInst_getOpVal(MI, 4)); |
821 | 273 | } |
822 | | |
823 | 398 | return true; |
824 | 2.03k | } |
825 | | |
826 | | bool printSyspAlias(MCInst *MI, SStream *O) |
827 | 1.42k | { |
828 | 1.42k | MCOperand *Op1 = MCInst_getOperand(MI, (0)); |
829 | 1.42k | MCOperand *Cn = MCInst_getOperand(MI, (1)); |
830 | 1.42k | MCOperand *Cm = MCInst_getOperand(MI, (2)); |
831 | 1.42k | MCOperand *Op2 = MCInst_getOperand(MI, (3)); |
832 | | |
833 | 1.42k | unsigned Op1Val = MCOperand_getImm(Op1); |
834 | 1.42k | unsigned CnVal = MCOperand_getImm(Cn); |
835 | 1.42k | unsigned CmVal = MCOperand_getImm(Cm); |
836 | 1.42k | unsigned Op2Val = MCOperand_getImm(Op2); |
837 | | |
838 | 1.42k | uint16_t Encoding = Op2Val; |
839 | 1.42k | Encoding |= CmVal << 3; |
840 | 1.42k | Encoding |= CnVal << 7; |
841 | 1.42k | Encoding |= Op1Val << 11; |
842 | | |
843 | 1.42k | const char *Ins; |
844 | 1.42k | const char *Name; |
845 | | |
846 | 1.42k | if (CnVal == 8 || CnVal == 9) { |
847 | | // TLBIP aliases |
848 | | |
849 | 1.08k | if (CnVal == 9) { |
850 | 236 | if (!AArch64_getFeatureBits(MI->csh->mode, |
851 | 236 | AArch64_FeatureAll) || |
852 | 236 | !AArch64_getFeatureBits(MI->csh->mode, |
853 | 236 | AArch64_FeatureXS)) |
854 | 0 | return false; |
855 | 236 | Encoding &= ~(1 << 7); |
856 | 236 | } |
857 | | |
858 | 1.08k | const AArch64TLBI_TLBI *TLBI = |
859 | 1.08k | AArch64TLBI_lookupTLBIByEncoding(Encoding); |
860 | 1.08k | if (!TLBI || !AArch64_testFeatureList(MI->csh->mode, |
861 | 926 | TLBI->FeaturesRequired)) |
862 | 159 | return false; |
863 | | |
864 | 926 | if (detail_is_set(MI)) { |
865 | 926 | aarch64_sysop sysop; |
866 | 926 | sysop.reg = TLBI->SysReg; |
867 | 926 | sysop.sub_type = AARCH64_OP_TLBI; |
868 | 926 | AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; |
869 | 926 | AArch64_get_detail_op(MI, 0)->sysop = sysop; |
870 | 926 | AArch64_inc_op_count(MI); |
871 | 926 | } |
872 | 926 | Ins = "tlbip "; |
873 | 926 | Name = TLBI->Name; |
874 | 926 | } else |
875 | 336 | return false; |
876 | | |
877 | 1.97k | #define TMP_STR_LEN 32 |
878 | 926 | char Str[TMP_STR_LEN] = { 0 }; |
879 | 926 | append_to_str_lower(Str, TMP_STR_LEN, Ins); |
880 | 926 | append_to_str_lower(Str, TMP_STR_LEN, Name); |
881 | | |
882 | 926 | if (CnVal == 9) { |
883 | 118 | append_to_str_lower(Str, TMP_STR_LEN, "nxs"); |
884 | 118 | } |
885 | 926 | #undef TMP_STR_LEN |
886 | | |
887 | 926 | SStream_concat1(O, ' '); |
888 | 926 | SStream_concat0(O, Str); |
889 | 926 | SStream_concat0(O, ", "); |
890 | 926 | if (MCOperand_getReg(MCInst_getOperand(MI, (4))) == AArch64_XZR) |
891 | 451 | printSyspXzrPair(MI, 4, O); |
892 | 475 | else |
893 | 475 | CONCAT(printGPRSeqPairsClassOperand, 64)(MI, 4, O); |
894 | | |
895 | 926 | return true; |
896 | 1.42k | } |
897 | | |
898 | | #define DEFINE_printMatrix(EltSize) \ |
899 | | void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \ |
900 | | SStream *O) \ |
901 | 7.61k | { \ |
902 | 7.61k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \ |
903 | 7.61k | OpNum, EltSize); \ |
904 | 7.61k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ |
905 | 7.61k | \ |
906 | 7.61k | printRegName(O, MCOperand_getReg(RegOp)); \ |
907 | 7.61k | switch (EltSize) { \ |
908 | 58 | case 0: \ |
909 | 58 | break; \ |
910 | 0 | case 8: \ |
911 | 0 | SStream_concat0(O, ".b"); \ |
912 | 0 | break; \ |
913 | 1.02k | case 16: \ |
914 | 1.02k | SStream_concat0(O, ".h"); \ |
915 | 1.02k | break; \ |
916 | 4.31k | case 32: \ |
917 | 4.31k | SStream_concat0(O, ".s"); \ |
918 | 4.31k | break; \ |
919 | 2.22k | case 64: \ |
920 | 2.22k | SStream_concat0(O, ".d"); \ |
921 | 2.22k | break; \ |
922 | 0 | case 128: \ |
923 | 0 | SStream_concat0(O, ".q"); \ |
924 | 0 | break; \ |
925 | 0 | default: \ |
926 | 0 | assert(0 && "Unsupported element size"); \ |
927 | 7.61k | } \ |
928 | 7.61k | } Line | Count | Source | 901 | 2.22k | { \ | 902 | 2.22k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \ | 903 | 2.22k | OpNum, EltSize); \ | 904 | 2.22k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 905 | 2.22k | \ | 906 | 2.22k | printRegName(O, MCOperand_getReg(RegOp)); \ | 907 | 2.22k | switch (EltSize) { \ | 908 | 0 | case 0: \ | 909 | 0 | break; \ | 910 | 0 | case 8: \ | 911 | 0 | SStream_concat0(O, ".b"); \ | 912 | 0 | break; \ | 913 | 0 | case 16: \ | 914 | 0 | SStream_concat0(O, ".h"); \ | 915 | 0 | break; \ | 916 | 0 | case 32: \ | 917 | 0 | SStream_concat0(O, ".s"); \ | 918 | 0 | break; \ | 919 | 2.22k | case 64: \ | 920 | 2.22k | SStream_concat0(O, ".d"); \ | 921 | 2.22k | break; \ | 922 | 0 | case 128: \ | 923 | 0 | SStream_concat0(O, ".q"); \ | 924 | 0 | break; \ | 925 | 0 | default: \ | 926 | 0 | assert(0 && "Unsupported element size"); \ | 927 | 2.22k | } \ | 928 | 2.22k | } |
Line | Count | Source | 901 | 4.31k | { \ | 902 | 4.31k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \ | 903 | 4.31k | OpNum, EltSize); \ | 904 | 4.31k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 905 | 4.31k | \ | 906 | 4.31k | printRegName(O, MCOperand_getReg(RegOp)); \ | 907 | 4.31k | switch (EltSize) { \ | 908 | 0 | case 0: \ | 909 | 0 | break; \ | 910 | 0 | case 8: \ | 911 | 0 | SStream_concat0(O, ".b"); \ | 912 | 0 | break; \ | 913 | 0 | case 16: \ | 914 | 0 | SStream_concat0(O, ".h"); \ | 915 | 0 | break; \ | 916 | 4.31k | case 32: \ | 917 | 4.31k | SStream_concat0(O, ".s"); \ | 918 | 4.31k | break; \ | 919 | 0 | case 64: \ | 920 | 0 | SStream_concat0(O, ".d"); \ | 921 | 0 | break; \ | 922 | 0 | case 128: \ | 923 | 0 | SStream_concat0(O, ".q"); \ | 924 | 0 | break; \ | 925 | 0 | default: \ | 926 | 0 | assert(0 && "Unsupported element size"); \ | 927 | 4.31k | } \ | 928 | 4.31k | } |
Line | Count | Source | 901 | 1.02k | { \ | 902 | 1.02k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \ | 903 | 1.02k | OpNum, EltSize); \ | 904 | 1.02k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 905 | 1.02k | \ | 906 | 1.02k | printRegName(O, MCOperand_getReg(RegOp)); \ | 907 | 1.02k | switch (EltSize) { \ | 908 | 0 | case 0: \ | 909 | 0 | break; \ | 910 | 0 | case 8: \ | 911 | 0 | SStream_concat0(O, ".b"); \ | 912 | 0 | break; \ | 913 | 1.02k | case 16: \ | 914 | 1.02k | SStream_concat0(O, ".h"); \ | 915 | 1.02k | break; \ | 916 | 0 | case 32: \ | 917 | 0 | SStream_concat0(O, ".s"); \ | 918 | 0 | break; \ | 919 | 0 | case 64: \ | 920 | 0 | SStream_concat0(O, ".d"); \ | 921 | 0 | break; \ | 922 | 0 | case 128: \ | 923 | 0 | SStream_concat0(O, ".q"); \ | 924 | 0 | break; \ | 925 | 0 | default: \ | 926 | 0 | assert(0 && "Unsupported element size"); \ | 927 | 1.02k | } \ | 928 | 1.02k | } |
Line | Count | Source | 901 | 58 | { \ | 902 | 58 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Matrix, EltSize), \ | 903 | 58 | OpNum, EltSize); \ | 904 | 58 | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 905 | 58 | \ | 906 | 58 | printRegName(O, MCOperand_getReg(RegOp)); \ | 907 | 58 | switch (EltSize) { \ | 908 | 58 | case 0: \ | 909 | 58 | break; \ | 910 | 0 | case 8: \ | 911 | 0 | SStream_concat0(O, ".b"); \ | 912 | 0 | break; \ | 913 | 0 | case 16: \ | 914 | 0 | SStream_concat0(O, ".h"); \ | 915 | 0 | break; \ | 916 | 0 | case 32: \ | 917 | 0 | SStream_concat0(O, ".s"); \ | 918 | 0 | break; \ | 919 | 0 | case 64: \ | 920 | 0 | SStream_concat0(O, ".d"); \ | 921 | 0 | break; \ | 922 | 0 | case 128: \ | 923 | 0 | SStream_concat0(O, ".q"); \ | 924 | 0 | break; \ | 925 | 0 | default: \ | 926 | 0 | assert(0 && "Unsupported element size"); \ | 927 | 58 | } \ | 928 | 58 | } |
|
929 | | DEFINE_printMatrix(64); |
930 | | DEFINE_printMatrix(32); |
931 | | DEFINE_printMatrix(16); |
932 | | DEFINE_printMatrix(0); |
933 | | |
934 | | #define DEFINE_printMatrixTileVector(IsVertical) \ |
935 | | void CONCAT(printMatrixTileVector, \ |
936 | | IsVertical)(MCInst * MI, unsigned OpNum, SStream *O) \ |
937 | 8.99k | { \ |
938 | 8.99k | add_cs_detail(MI, \ |
939 | 8.99k | CONCAT(AArch64_OP_GROUP_MatrixTileVector, \ |
940 | 8.99k | IsVertical), \ |
941 | 8.99k | OpNum, IsVertical); \ |
942 | 8.99k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ |
943 | 8.99k | \ |
944 | 8.99k | const char *RegName = getRegisterName(MCOperand_getReg(RegOp), \ |
945 | 8.99k | AArch64_NoRegAltName); \ |
946 | 8.99k | \ |
947 | 8.99k | unsigned buf_len = strlen(RegName) + 1; \ |
948 | 8.99k | char *Base = cs_mem_calloc(1, buf_len); \ |
949 | 8.99k | memcpy(Base, RegName, buf_len); \ |
950 | 8.99k | char *Dot = strchr(Base, '.'); \ |
951 | 8.99k | if (!Dot) { \ |
952 | 0 | SStream_concat0(O, RegName); \ |
953 | 0 | return; \ |
954 | 0 | } \ |
955 | 8.99k | *Dot = '\0'; /* Split string */ \ |
956 | 8.99k | char *Suffix = Dot + 1; \ |
957 | 8.99k | SStream_concat(O, "%s%s", Base, (IsVertical ? "v" : "h")); \ |
958 | 8.99k | SStream_concat1(O, '.'); \ |
959 | 8.99k | SStream_concat0(O, Suffix); \ |
960 | 8.99k | cs_mem_free(Base); \ |
961 | 8.99k | } Line | Count | Source | 937 | 4.25k | { \ | 938 | 4.25k | add_cs_detail(MI, \ | 939 | 4.25k | CONCAT(AArch64_OP_GROUP_MatrixTileVector, \ | 940 | 4.25k | IsVertical), \ | 941 | 4.25k | OpNum, IsVertical); \ | 942 | 4.25k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 943 | 4.25k | \ | 944 | 4.25k | const char *RegName = getRegisterName(MCOperand_getReg(RegOp), \ | 945 | 4.25k | AArch64_NoRegAltName); \ | 946 | 4.25k | \ | 947 | 4.25k | unsigned buf_len = strlen(RegName) + 1; \ | 948 | 4.25k | char *Base = cs_mem_calloc(1, buf_len); \ | 949 | 4.25k | memcpy(Base, RegName, buf_len); \ | 950 | 4.25k | char *Dot = strchr(Base, '.'); \ | 951 | 4.25k | if (!Dot) { \ | 952 | 0 | SStream_concat0(O, RegName); \ | 953 | 0 | return; \ | 954 | 0 | } \ | 955 | 4.25k | *Dot = '\0'; /* Split string */ \ | 956 | 4.25k | char *Suffix = Dot + 1; \ | 957 | 4.25k | SStream_concat(O, "%s%s", Base, (IsVertical ? "v" : "h")); \ | 958 | 4.25k | SStream_concat1(O, '.'); \ | 959 | 4.25k | SStream_concat0(O, Suffix); \ | 960 | 4.25k | cs_mem_free(Base); \ | 961 | 4.25k | } |
Line | Count | Source | 937 | 4.73k | { \ | 938 | 4.73k | add_cs_detail(MI, \ | 939 | 4.73k | CONCAT(AArch64_OP_GROUP_MatrixTileVector, \ | 940 | 4.73k | IsVertical), \ | 941 | 4.73k | OpNum, IsVertical); \ | 942 | 4.73k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); \ | 943 | 4.73k | \ | 944 | 4.73k | const char *RegName = getRegisterName(MCOperand_getReg(RegOp), \ | 945 | 4.73k | AArch64_NoRegAltName); \ | 946 | 4.73k | \ | 947 | 4.73k | unsigned buf_len = strlen(RegName) + 1; \ | 948 | 4.73k | char *Base = cs_mem_calloc(1, buf_len); \ | 949 | 4.73k | memcpy(Base, RegName, buf_len); \ | 950 | 4.73k | char *Dot = strchr(Base, '.'); \ | 951 | 4.73k | if (!Dot) { \ | 952 | 0 | SStream_concat0(O, RegName); \ | 953 | 0 | return; \ | 954 | 0 | } \ | 955 | 4.73k | *Dot = '\0'; /* Split string */ \ | 956 | 4.73k | char *Suffix = Dot + 1; \ | 957 | 4.73k | SStream_concat(O, "%s%s", Base, (IsVertical ? "v" : "h")); \ | 958 | 4.73k | SStream_concat1(O, '.'); \ | 959 | 4.73k | SStream_concat0(O, Suffix); \ | 960 | 4.73k | cs_mem_free(Base); \ | 961 | 4.73k | } |
|
962 | | DEFINE_printMatrixTileVector(0); |
963 | | DEFINE_printMatrixTileVector(1); |
964 | | |
965 | | void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O) |
966 | 3.13k | { |
967 | 3.13k | add_cs_detail(MI, AArch64_OP_GROUP_MatrixTile, OpNum); |
968 | 3.13k | MCOperand *RegOp = MCInst_getOperand(MI, (OpNum)); |
969 | | |
970 | 3.13k | printRegName(O, MCOperand_getReg(RegOp)); |
971 | 3.13k | } |
972 | | |
973 | | void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O) |
974 | 0 | { |
975 | 0 | add_cs_detail(MI, AArch64_OP_GROUP_SVCROp, OpNum); |
976 | 0 | MCOperand *MO = MCInst_getOperand(MI, (OpNum)); |
977 | |
|
978 | 0 | unsigned svcrop = MCOperand_getImm(MO); |
979 | 0 | const AArch64SVCR_SVCR *SVCR = AArch64SVCR_lookupSVCRByEncoding(svcrop); |
980 | |
|
981 | 0 | SStream_concat0(O, SVCR->Name); |
982 | 0 | } |
983 | | |
984 | | void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
985 | 404k | { |
986 | 404k | add_cs_detail(MI, AArch64_OP_GROUP_Operand, OpNo); |
987 | 404k | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
988 | 404k | if (MCOperand_isReg(Op)) { |
989 | 347k | unsigned Reg = MCOperand_getReg(Op); |
990 | 347k | printRegName(O, Reg); |
991 | 347k | } else if (MCOperand_isImm(Op)) { |
992 | 57.5k | Op = MCInst_getOperand(MI, (OpNo)); |
993 | 57.5k | SStream_concat(O, "%s", markup("<imm:")); |
994 | 57.5k | printInt64Bang(O, MCOperand_getImm(Op)); |
995 | 57.5k | SStream_concat0(O, markup(">")); |
996 | 57.5k | } else { |
997 | 0 | SStream_concat0(O, "<llvm-expr>"); |
998 | 0 | } |
999 | 404k | } |
1000 | | |
1001 | | void printImm(MCInst *MI, unsigned OpNo, SStream *O) |
1002 | 5.38k | { |
1003 | 5.38k | add_cs_detail(MI, AArch64_OP_GROUP_Imm, OpNo); |
1004 | 5.38k | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
1005 | 5.38k | SStream_concat(O, "%s", markup("<imm:")); |
1006 | 5.38k | printInt64Bang(O, MCOperand_getImm(Op)); |
1007 | 5.38k | SStream_concat0(O, markup(">")); |
1008 | 5.38k | } |
1009 | | |
1010 | | void printImmHex(MCInst *MI, unsigned OpNo, SStream *O) |
1011 | 86 | { |
1012 | 86 | add_cs_detail(MI, AArch64_OP_GROUP_ImmHex, OpNo); |
1013 | 86 | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
1014 | 86 | SStream_concat(O, "%s", markup("<imm:")); |
1015 | 86 | printInt64Bang(O, MCOperand_getImm(Op)); |
1016 | 86 | SStream_concat0(O, markup(">")); |
1017 | 86 | } |
1018 | | |
1019 | | #define DEFINE_printSImm(Size) \ |
1020 | | void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O) \ |
1021 | 888 | { \ |
1022 | 888 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SImm, Size), OpNo, \ |
1023 | 888 | Size); \ |
1024 | 888 | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); \ |
1025 | 888 | if (Size == 8) { \ |
1026 | 761 | SStream_concat(O, "%s", markup("<imm:")); \ |
1027 | 761 | printInt32Bang(O, MCOperand_getImm(Op)); \ |
1028 | 761 | SStream_concat0(O, markup(">")); \ |
1029 | 761 | } else if (Size == 16) { \ |
1030 | 127 | SStream_concat(O, "%s", markup("<imm:")); \ |
1031 | 127 | printInt32Bang(O, MCOperand_getImm(Op)); \ |
1032 | 127 | SStream_concat0(O, markup(">")); \ |
1033 | 127 | } else { \ |
1034 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ |
1035 | 0 | printInt64Bang(O, MCOperand_getImm(Op)); \ |
1036 | 0 | SStream_concat0(O, markup(">")); \ |
1037 | 0 | } \ |
1038 | 888 | } Line | Count | Source | 1021 | 127 | { \ | 1022 | 127 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SImm, Size), OpNo, \ | 1023 | 127 | Size); \ | 1024 | 127 | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); \ | 1025 | 127 | if (Size == 8) { \ | 1026 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 1027 | 0 | printInt32Bang(O, MCOperand_getImm(Op)); \ | 1028 | 0 | SStream_concat0(O, markup(">")); \ | 1029 | 127 | } else if (Size == 16) { \ | 1030 | 127 | SStream_concat(O, "%s", markup("<imm:")); \ | 1031 | 127 | printInt32Bang(O, MCOperand_getImm(Op)); \ | 1032 | 127 | SStream_concat0(O, markup(">")); \ | 1033 | 127 | } else { \ | 1034 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 1035 | 0 | printInt64Bang(O, MCOperand_getImm(Op)); \ | 1036 | 0 | SStream_concat0(O, markup(">")); \ | 1037 | 0 | } \ | 1038 | 127 | } |
Line | Count | Source | 1021 | 761 | { \ | 1022 | 761 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SImm, Size), OpNo, \ | 1023 | 761 | Size); \ | 1024 | 761 | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); \ | 1025 | 761 | if (Size == 8) { \ | 1026 | 761 | SStream_concat(O, "%s", markup("<imm:")); \ | 1027 | 761 | printInt32Bang(O, MCOperand_getImm(Op)); \ | 1028 | 761 | SStream_concat0(O, markup(">")); \ | 1029 | 761 | } else if (Size == 16) { \ | 1030 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 1031 | 0 | printInt32Bang(O, MCOperand_getImm(Op)); \ | 1032 | 0 | SStream_concat0(O, markup(">")); \ | 1033 | 0 | } else { \ | 1034 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 1035 | 0 | printInt64Bang(O, MCOperand_getImm(Op)); \ | 1036 | 0 | SStream_concat0(O, markup(">")); \ | 1037 | 0 | } \ | 1038 | 761 | } |
|
1039 | | DEFINE_printSImm(16); |
1040 | | DEFINE_printSImm(8); |
1041 | | |
1042 | | void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O) |
1043 | 9.29k | { |
1044 | 9.29k | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
1045 | 9.29k | if (MCOperand_isReg(Op)) { |
1046 | 9.29k | unsigned Reg = MCOperand_getReg(Op); |
1047 | 9.29k | if (Reg == AArch64_XZR) { |
1048 | 0 | SStream_concat(O, "%s", markup("<imm:")); |
1049 | 0 | printUInt64Bang(O, Imm); |
1050 | 0 | SStream_concat0(O, markup(">")); |
1051 | 0 | } else |
1052 | 9.29k | printRegName(O, Reg); |
1053 | 9.29k | } else |
1054 | 0 | assert(0 && "unknown operand kind in printPostIncOperand64"); |
1055 | 9.29k | } |
1056 | | |
1057 | | void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O) |
1058 | 64.2k | { |
1059 | 64.2k | add_cs_detail(MI, AArch64_OP_GROUP_VRegOperand, OpNo); |
1060 | 64.2k | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
1061 | | |
1062 | 64.2k | unsigned Reg = MCOperand_getReg(Op); |
1063 | 64.2k | printRegNameAlt(O, Reg, AArch64_vreg); |
1064 | 64.2k | } |
1065 | | |
1066 | | void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O) |
1067 | 4.41k | { |
1068 | 4.41k | add_cs_detail(MI, AArch64_OP_GROUP_SysCROperand, OpNo); |
1069 | 4.41k | MCOperand *Op = MCInst_getOperand(MI, (OpNo)); |
1070 | | |
1071 | 4.41k | SStream_concat(O, "%s", "c"); |
1072 | 4.41k | printUInt32(O, MCOperand_getImm(Op)); |
1073 | 4.41k | SStream_concat1(O, '\0'); |
1074 | 4.41k | } |
1075 | | |
1076 | | void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) |
1077 | 4.33k | { |
1078 | 4.33k | add_cs_detail(MI, AArch64_OP_GROUP_AddSubImm, OpNum); |
1079 | 4.33k | MCOperand *MO = MCInst_getOperand(MI, (OpNum)); |
1080 | 4.33k | if (MCOperand_isImm(MO)) { |
1081 | 4.33k | unsigned Val = (MCOperand_getImm(MO) & 0xfff); |
1082 | | |
1083 | 4.33k | unsigned Shift = AArch64_AM_getShiftValue( |
1084 | 4.33k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1)))); |
1085 | 4.33k | SStream_concat(O, "%s", markup("<imm:")); |
1086 | 4.33k | printUInt32Bang(O, (Val)); |
1087 | 4.33k | SStream_concat0(O, markup(">")); |
1088 | 4.33k | if (Shift != 0) { |
1089 | 2.27k | printShifter(MI, OpNum + 1, O); |
1090 | 2.27k | } |
1091 | 4.33k | } else { |
1092 | 0 | printShifter(MI, OpNum + 1, O); |
1093 | 0 | } |
1094 | 4.33k | } |
1095 | | |
1096 | | #define DEFINE_printLogicalImm(T) \ |
1097 | | void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \ |
1098 | | SStream *O) \ |
1099 | 7.30k | { \ |
1100 | 7.30k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \ |
1101 | 7.30k | OpNum, sizeof(T)); \ |
1102 | 7.30k | uint64_t Val = \ |
1103 | 7.30k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
1104 | 7.30k | SStream_concat(O, "%s", markup("<imm:")); \ |
1105 | 7.30k | printUInt64Bang(O, (AArch64_AM_decodeLogicalImmediate( \ |
1106 | 7.30k | Val, 8 * sizeof(T)))); \ |
1107 | 7.30k | SStream_concat0(O, markup(">")); \ |
1108 | 7.30k | } Line | Count | Source | 1099 | 2.13k | { \ | 1100 | 2.13k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \ | 1101 | 2.13k | OpNum, sizeof(T)); \ | 1102 | 2.13k | uint64_t Val = \ | 1103 | 2.13k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1104 | 2.13k | SStream_concat(O, "%s", markup("<imm:")); \ | 1105 | 2.13k | printUInt64Bang(O, (AArch64_AM_decodeLogicalImmediate( \ | 1106 | 2.13k | Val, 8 * sizeof(T)))); \ | 1107 | 2.13k | SStream_concat0(O, markup(">")); \ | 1108 | 2.13k | } |
Line | Count | Source | 1099 | 3.17k | { \ | 1100 | 3.17k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \ | 1101 | 3.17k | OpNum, sizeof(T)); \ | 1102 | 3.17k | uint64_t Val = \ | 1103 | 3.17k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1104 | 3.17k | SStream_concat(O, "%s", markup("<imm:")); \ | 1105 | 3.17k | printUInt64Bang(O, (AArch64_AM_decodeLogicalImmediate( \ | 1106 | 3.17k | Val, 8 * sizeof(T)))); \ | 1107 | 3.17k | SStream_concat0(O, markup(">")); \ | 1108 | 3.17k | } |
Line | Count | Source | 1099 | 921 | { \ | 1100 | 921 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \ | 1101 | 921 | OpNum, sizeof(T)); \ | 1102 | 921 | uint64_t Val = \ | 1103 | 921 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1104 | 921 | SStream_concat(O, "%s", markup("<imm:")); \ | 1105 | 921 | printUInt64Bang(O, (AArch64_AM_decodeLogicalImmediate( \ | 1106 | 921 | Val, 8 * sizeof(T)))); \ | 1107 | 921 | SStream_concat0(O, markup(">")); \ | 1108 | 921 | } |
Line | Count | Source | 1099 | 1.08k | { \ | 1100 | 1.08k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_LogicalImm, T), \ | 1101 | 1.08k | OpNum, sizeof(T)); \ | 1102 | 1.08k | uint64_t Val = \ | 1103 | 1.08k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1104 | 1.08k | SStream_concat(O, "%s", markup("<imm:")); \ | 1105 | 1.08k | printUInt64Bang(O, (AArch64_AM_decodeLogicalImmediate( \ | 1106 | 1.08k | Val, 8 * sizeof(T)))); \ | 1107 | 1.08k | SStream_concat0(O, markup(">")); \ | 1108 | 1.08k | } |
|
1109 | | DEFINE_printLogicalImm(int64_t); |
1110 | | DEFINE_printLogicalImm(int32_t); |
1111 | | DEFINE_printLogicalImm(int8_t); |
1112 | | DEFINE_printLogicalImm(int16_t); |
1113 | | |
1114 | | void printShifter(MCInst *MI, unsigned OpNum, SStream *O) |
1115 | 14.8k | { |
1116 | 14.8k | add_cs_detail(MI, AArch64_OP_GROUP_Shifter, OpNum); |
1117 | 14.8k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1118 | | // LSL #0 should not be printed. |
1119 | 14.8k | if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && |
1120 | 14.8k | AArch64_AM_getShiftValue(Val) == 0) |
1121 | 526 | return; |
1122 | 14.3k | SStream_concat( |
1123 | 14.3k | O, "%s%s%s%s#%d", ", ", |
1124 | 14.3k | AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)), |
1125 | 14.3k | " ", markup("<imm:"), AArch64_AM_getShiftValue(Val)); |
1126 | 14.3k | SStream_concat0(O, markup(">")); |
1127 | 14.3k | } |
1128 | | |
1129 | | void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) |
1130 | 9.61k | { |
1131 | 9.61k | add_cs_detail(MI, AArch64_OP_GROUP_ShiftedRegister, OpNum); |
1132 | 9.61k | printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); |
1133 | 9.61k | printShifter(MI, OpNum + 1, O); |
1134 | 9.61k | } |
1135 | | |
1136 | | void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) |
1137 | 1.52k | { |
1138 | 1.52k | add_cs_detail(MI, AArch64_OP_GROUP_ExtendedRegister, OpNum); |
1139 | 1.52k | printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); |
1140 | 1.52k | printArithExtend(MI, OpNum + 1, O); |
1141 | 1.52k | } |
1142 | | |
1143 | | void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) |
1144 | 1.74k | { |
1145 | 1.74k | add_cs_detail(MI, AArch64_OP_GROUP_ArithExtend, OpNum); |
1146 | 1.74k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1147 | 1.74k | AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); |
1148 | 1.74k | unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); |
1149 | | |
1150 | | // If the destination or first source register operand is [W]SP, print |
1151 | | // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at |
1152 | | // all. |
1153 | 1.74k | if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { |
1154 | 903 | unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, (0))); |
1155 | 903 | unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, (1))); |
1156 | 903 | if (((Dest == AArch64_SP || Src1 == AArch64_SP) && |
1157 | 903 | ExtType == AArch64_AM_UXTX) || |
1158 | 903 | ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && |
1159 | 888 | ExtType == AArch64_AM_UXTW)) { |
1160 | 303 | if (ShiftVal != 0) { |
1161 | 303 | SStream_concat(O, "%s%s", ", lsl ", |
1162 | 303 | markup("<imm:")); |
1163 | 303 | printUInt32Bang(O, ShiftVal); |
1164 | 303 | SStream_concat0(O, markup(">")); |
1165 | 303 | } |
1166 | 303 | return; |
1167 | 303 | } |
1168 | 903 | } |
1169 | 1.43k | SStream_concat(O, "%s", ", "); |
1170 | 1.43k | SStream_concat0(O, AArch64_AM_getShiftExtendName(ExtType)); |
1171 | 1.43k | if (ShiftVal != 0) { |
1172 | 1.27k | SStream_concat(O, "%s%s#%d", " ", markup("<imm:"), ShiftVal); |
1173 | 1.27k | SStream_concat0(O, markup(">")); |
1174 | 1.27k | } |
1175 | 1.43k | } |
1176 | | |
1177 | | static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, |
1178 | | char SrcRegKind, SStream *O, bool getUseMarkup) |
1179 | 14.7k | { |
1180 | | // sxtw, sxtx, uxtw or lsl (== uxtx) |
1181 | 14.7k | bool IsLSL = !SignExtend && SrcRegKind == 'x'; |
1182 | 14.7k | if (IsLSL) |
1183 | 6.61k | SStream_concat0(O, "lsl"); |
1184 | 8.16k | else { |
1185 | 8.16k | SStream_concat(O, "%c%s", (SignExtend ? 's' : 'u'), "xt"); |
1186 | 8.16k | SStream_concat1(O, SrcRegKind); |
1187 | 8.16k | } |
1188 | | |
1189 | 14.7k | if (DoShift || IsLSL) { |
1190 | 11.3k | SStream_concat0(O, " "); |
1191 | 11.3k | if (getUseMarkup) |
1192 | 0 | SStream_concat0(O, "<imm:"); |
1193 | 11.3k | unsigned ShiftAmount = DoShift ? Log2_32(Width / 8) : 0; |
1194 | 11.3k | SStream_concat(O, "%s%d", "#", ShiftAmount); |
1195 | 11.3k | if (getUseMarkup) |
1196 | 0 | SStream_concat0(O, ">"); |
1197 | 11.3k | } |
1198 | 14.7k | } |
1199 | | |
1200 | | void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, |
1201 | | unsigned Width) |
1202 | 2.08k | { |
1203 | 2.08k | bool SignExtend = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1204 | 2.08k | bool DoShift = MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); |
1205 | 2.08k | printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O, |
1206 | 2.08k | getUseMarkup()); |
1207 | 2.08k | } |
1208 | | |
1209 | | #define DEFINE_printRegWithShiftExtend(SignExtend, ExtWidth, SrcRegKind, \ |
1210 | | Suffix) \ |
1211 | | void CONCAT(printRegWithShiftExtend, \ |
1212 | | CONCAT(SignExtend, \ |
1213 | | CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \ |
1214 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
1215 | 14.7k | { \ |
1216 | 14.7k | add_cs_detail( \ |
1217 | 14.7k | MI, \ |
1218 | 14.7k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ |
1219 | 14.7k | SignExtend), \ |
1220 | 14.7k | ExtWidth), \ |
1221 | 14.7k | SrcRegKind), \ |
1222 | 14.7k | Suffix), \ |
1223 | 14.7k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ |
1224 | 14.7k | CHAR(Suffix)); \ |
1225 | 14.7k | printOperand(MI, OpNum, O); \ |
1226 | 14.7k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ |
1227 | 8.72k | SStream_concat1(O, '.'); \ |
1228 | 8.72k | SStream_concat1(O, CHAR(Suffix)); \ |
1229 | 8.72k | SStream_concat1(O, '\0'); \ |
1230 | 8.72k | } else \ |
1231 | 14.7k | assert((CHAR(Suffix) == '0') && \ |
1232 | 14.7k | "Unsupported suffix size"); \ |
1233 | 14.7k | bool DoShift = ExtWidth != 8; \ |
1234 | 14.7k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ |
1235 | 12.6k | SStream_concat0(O, ", "); \ |
1236 | 12.6k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ |
1237 | 12.6k | CHAR(SrcRegKind), O, \ |
1238 | 12.6k | getUseMarkup()); \ |
1239 | 12.6k | } \ |
1240 | 14.7k | } printRegWithShiftExtend_0_8_x_d Line | Count | Source | 1215 | 599 | { \ | 1216 | 599 | add_cs_detail( \ | 1217 | 599 | MI, \ | 1218 | 599 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 599 | SignExtend), \ | 1220 | 599 | ExtWidth), \ | 1221 | 599 | SrcRegKind), \ | 1222 | 599 | Suffix), \ | 1223 | 599 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 599 | CHAR(Suffix)); \ | 1225 | 599 | printOperand(MI, OpNum, O); \ | 1226 | 599 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 599 | SStream_concat1(O, '.'); \ | 1228 | 599 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 599 | SStream_concat1(O, '\0'); \ | 1230 | 599 | } else \ | 1231 | 599 | assert((CHAR(Suffix) == '0') && \ | 1232 | 599 | "Unsupported suffix size"); \ | 1233 | 599 | bool DoShift = ExtWidth != 8; \ | 1234 | 599 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 0 | SStream_concat0(O, ", "); \ | 1236 | 0 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 0 | CHAR(SrcRegKind), O, \ | 1238 | 0 | getUseMarkup()); \ | 1239 | 0 | } \ | 1240 | 599 | } |
printRegWithShiftExtend_1_8_w_d Line | Count | Source | 1215 | 1.12k | { \ | 1216 | 1.12k | add_cs_detail( \ | 1217 | 1.12k | MI, \ | 1218 | 1.12k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.12k | SignExtend), \ | 1220 | 1.12k | ExtWidth), \ | 1221 | 1.12k | SrcRegKind), \ | 1222 | 1.12k | Suffix), \ | 1223 | 1.12k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.12k | CHAR(Suffix)); \ | 1225 | 1.12k | printOperand(MI, OpNum, O); \ | 1226 | 1.12k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 1.12k | SStream_concat1(O, '.'); \ | 1228 | 1.12k | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 1.12k | SStream_concat1(O, '\0'); \ | 1230 | 1.12k | } else \ | 1231 | 1.12k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.12k | "Unsupported suffix size"); \ | 1233 | 1.12k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.12k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 1.12k | SStream_concat0(O, ", "); \ | 1236 | 1.12k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 1.12k | CHAR(SrcRegKind), O, \ | 1238 | 1.12k | getUseMarkup()); \ | 1239 | 1.12k | } \ | 1240 | 1.12k | } |
printRegWithShiftExtend_0_8_w_d Line | Count | Source | 1215 | 1.07k | { \ | 1216 | 1.07k | add_cs_detail( \ | 1217 | 1.07k | MI, \ | 1218 | 1.07k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.07k | SignExtend), \ | 1220 | 1.07k | ExtWidth), \ | 1221 | 1.07k | SrcRegKind), \ | 1222 | 1.07k | Suffix), \ | 1223 | 1.07k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.07k | CHAR(Suffix)); \ | 1225 | 1.07k | printOperand(MI, OpNum, O); \ | 1226 | 1.07k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 1.07k | SStream_concat1(O, '.'); \ | 1228 | 1.07k | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 1.07k | SStream_concat1(O, '\0'); \ | 1230 | 1.07k | } else \ | 1231 | 1.07k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.07k | "Unsupported suffix size"); \ | 1233 | 1.07k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.07k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 1.07k | SStream_concat0(O, ", "); \ | 1236 | 1.07k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 1.07k | CHAR(SrcRegKind), O, \ | 1238 | 1.07k | getUseMarkup()); \ | 1239 | 1.07k | } \ | 1240 | 1.07k | } |
printRegWithShiftExtend_0_8_x_0 Line | Count | Source | 1215 | 1.38k | { \ | 1216 | 1.38k | add_cs_detail( \ | 1217 | 1.38k | MI, \ | 1218 | 1.38k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.38k | SignExtend), \ | 1220 | 1.38k | ExtWidth), \ | 1221 | 1.38k | SrcRegKind), \ | 1222 | 1.38k | Suffix), \ | 1223 | 1.38k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.38k | CHAR(Suffix)); \ | 1225 | 1.38k | printOperand(MI, OpNum, O); \ | 1226 | 1.38k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 0 | SStream_concat1(O, '.'); \ | 1228 | 0 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 0 | SStream_concat1(O, '\0'); \ | 1230 | 0 | } else \ | 1231 | 1.38k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.38k | "Unsupported suffix size"); \ | 1233 | 1.38k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.38k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 0 | SStream_concat0(O, ", "); \ | 1236 | 0 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 0 | CHAR(SrcRegKind), O, \ | 1238 | 0 | getUseMarkup()); \ | 1239 | 0 | } \ | 1240 | 1.38k | } |
printRegWithShiftExtend_1_8_w_s Line | Count | Source | 1215 | 185 | { \ | 1216 | 185 | add_cs_detail( \ | 1217 | 185 | MI, \ | 1218 | 185 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 185 | SignExtend), \ | 1220 | 185 | ExtWidth), \ | 1221 | 185 | SrcRegKind), \ | 1222 | 185 | Suffix), \ | 1223 | 185 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 185 | CHAR(Suffix)); \ | 1225 | 185 | printOperand(MI, OpNum, O); \ | 1226 | 185 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 185 | SStream_concat1(O, '.'); \ | 1228 | 185 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 185 | SStream_concat1(O, '\0'); \ | 1230 | 185 | } else \ | 1231 | 185 | assert((CHAR(Suffix) == '0') && \ | 1232 | 185 | "Unsupported suffix size"); \ | 1233 | 185 | bool DoShift = ExtWidth != 8; \ | 1234 | 185 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 185 | SStream_concat0(O, ", "); \ | 1236 | 185 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 185 | CHAR(SrcRegKind), O, \ | 1238 | 185 | getUseMarkup()); \ | 1239 | 185 | } \ | 1240 | 185 | } |
printRegWithShiftExtend_0_8_w_s Line | Count | Source | 1215 | 420 | { \ | 1216 | 420 | add_cs_detail( \ | 1217 | 420 | MI, \ | 1218 | 420 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 420 | SignExtend), \ | 1220 | 420 | ExtWidth), \ | 1221 | 420 | SrcRegKind), \ | 1222 | 420 | Suffix), \ | 1223 | 420 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 420 | CHAR(Suffix)); \ | 1225 | 420 | printOperand(MI, OpNum, O); \ | 1226 | 420 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 420 | SStream_concat1(O, '.'); \ | 1228 | 420 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 420 | SStream_concat1(O, '\0'); \ | 1230 | 420 | } else \ | 1231 | 420 | assert((CHAR(Suffix) == '0') && \ | 1232 | 420 | "Unsupported suffix size"); \ | 1233 | 420 | bool DoShift = ExtWidth != 8; \ | 1234 | 420 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 420 | SStream_concat0(O, ", "); \ | 1236 | 420 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 420 | CHAR(SrcRegKind), O, \ | 1238 | 420 | getUseMarkup()); \ | 1239 | 420 | } \ | 1240 | 420 | } |
printRegWithShiftExtend_0_64_x_d Line | Count | Source | 1215 | 148 | { \ | 1216 | 148 | add_cs_detail( \ | 1217 | 148 | MI, \ | 1218 | 148 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 148 | SignExtend), \ | 1220 | 148 | ExtWidth), \ | 1221 | 148 | SrcRegKind), \ | 1222 | 148 | Suffix), \ | 1223 | 148 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 148 | CHAR(Suffix)); \ | 1225 | 148 | printOperand(MI, OpNum, O); \ | 1226 | 148 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 148 | SStream_concat1(O, '.'); \ | 1228 | 148 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 148 | SStream_concat1(O, '\0'); \ | 1230 | 148 | } else \ | 1231 | 148 | assert((CHAR(Suffix) == '0') && \ | 1232 | 148 | "Unsupported suffix size"); \ | 1233 | 148 | bool DoShift = ExtWidth != 8; \ | 1234 | 148 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 148 | SStream_concat0(O, ", "); \ | 1236 | 148 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 148 | CHAR(SrcRegKind), O, \ | 1238 | 148 | getUseMarkup()); \ | 1239 | 148 | } \ | 1240 | 148 | } |
printRegWithShiftExtend_1_64_w_d Line | Count | Source | 1215 | 297 | { \ | 1216 | 297 | add_cs_detail( \ | 1217 | 297 | MI, \ | 1218 | 297 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 297 | SignExtend), \ | 1220 | 297 | ExtWidth), \ | 1221 | 297 | SrcRegKind), \ | 1222 | 297 | Suffix), \ | 1223 | 297 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 297 | CHAR(Suffix)); \ | 1225 | 297 | printOperand(MI, OpNum, O); \ | 1226 | 297 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 297 | SStream_concat1(O, '.'); \ | 1228 | 297 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 297 | SStream_concat1(O, '\0'); \ | 1230 | 297 | } else \ | 1231 | 297 | assert((CHAR(Suffix) == '0') && \ | 1232 | 297 | "Unsupported suffix size"); \ | 1233 | 297 | bool DoShift = ExtWidth != 8; \ | 1234 | 297 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 297 | SStream_concat0(O, ", "); \ | 1236 | 297 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 297 | CHAR(SrcRegKind), O, \ | 1238 | 297 | getUseMarkup()); \ | 1239 | 297 | } \ | 1240 | 297 | } |
printRegWithShiftExtend_0_64_w_d Line | Count | Source | 1215 | 138 | { \ | 1216 | 138 | add_cs_detail( \ | 1217 | 138 | MI, \ | 1218 | 138 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 138 | SignExtend), \ | 1220 | 138 | ExtWidth), \ | 1221 | 138 | SrcRegKind), \ | 1222 | 138 | Suffix), \ | 1223 | 138 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 138 | CHAR(Suffix)); \ | 1225 | 138 | printOperand(MI, OpNum, O); \ | 1226 | 138 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 138 | SStream_concat1(O, '.'); \ | 1228 | 138 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 138 | SStream_concat1(O, '\0'); \ | 1230 | 138 | } else \ | 1231 | 138 | assert((CHAR(Suffix) == '0') && \ | 1232 | 138 | "Unsupported suffix size"); \ | 1233 | 138 | bool DoShift = ExtWidth != 8; \ | 1234 | 138 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 138 | SStream_concat0(O, ", "); \ | 1236 | 138 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 138 | CHAR(SrcRegKind), O, \ | 1238 | 138 | getUseMarkup()); \ | 1239 | 138 | } \ | 1240 | 138 | } |
printRegWithShiftExtend_0_64_x_0 Line | Count | Source | 1215 | 1.32k | { \ | 1216 | 1.32k | add_cs_detail( \ | 1217 | 1.32k | MI, \ | 1218 | 1.32k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.32k | SignExtend), \ | 1220 | 1.32k | ExtWidth), \ | 1221 | 1.32k | SrcRegKind), \ | 1222 | 1.32k | Suffix), \ | 1223 | 1.32k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.32k | CHAR(Suffix)); \ | 1225 | 1.32k | printOperand(MI, OpNum, O); \ | 1226 | 1.32k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 0 | SStream_concat1(O, '.'); \ | 1228 | 0 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 0 | SStream_concat1(O, '\0'); \ | 1230 | 0 | } else \ | 1231 | 1.32k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.32k | "Unsupported suffix size"); \ | 1233 | 1.32k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.32k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 1.32k | SStream_concat0(O, ", "); \ | 1236 | 1.32k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 1.32k | CHAR(SrcRegKind), O, \ | 1238 | 1.32k | getUseMarkup()); \ | 1239 | 1.32k | } \ | 1240 | 1.32k | } |
printRegWithShiftExtend_1_64_w_s Line | Count | Source | 1215 | 146 | { \ | 1216 | 146 | add_cs_detail( \ | 1217 | 146 | MI, \ | 1218 | 146 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 146 | SignExtend), \ | 1220 | 146 | ExtWidth), \ | 1221 | 146 | SrcRegKind), \ | 1222 | 146 | Suffix), \ | 1223 | 146 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 146 | CHAR(Suffix)); \ | 1225 | 146 | printOperand(MI, OpNum, O); \ | 1226 | 146 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 146 | SStream_concat1(O, '.'); \ | 1228 | 146 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 146 | SStream_concat1(O, '\0'); \ | 1230 | 146 | } else \ | 1231 | 146 | assert((CHAR(Suffix) == '0') && \ | 1232 | 146 | "Unsupported suffix size"); \ | 1233 | 146 | bool DoShift = ExtWidth != 8; \ | 1234 | 146 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 146 | SStream_concat0(O, ", "); \ | 1236 | 146 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 146 | CHAR(SrcRegKind), O, \ | 1238 | 146 | getUseMarkup()); \ | 1239 | 146 | } \ | 1240 | 146 | } |
printRegWithShiftExtend_0_64_w_s Line | Count | Source | 1215 | 36 | { \ | 1216 | 36 | add_cs_detail( \ | 1217 | 36 | MI, \ | 1218 | 36 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 36 | SignExtend), \ | 1220 | 36 | ExtWidth), \ | 1221 | 36 | SrcRegKind), \ | 1222 | 36 | Suffix), \ | 1223 | 36 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 36 | CHAR(Suffix)); \ | 1225 | 36 | printOperand(MI, OpNum, O); \ | 1226 | 36 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 36 | SStream_concat1(O, '.'); \ | 1228 | 36 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 36 | SStream_concat1(O, '\0'); \ | 1230 | 36 | } else \ | 1231 | 36 | assert((CHAR(Suffix) == '0') && \ | 1232 | 36 | "Unsupported suffix size"); \ | 1233 | 36 | bool DoShift = ExtWidth != 8; \ | 1234 | 36 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 36 | SStream_concat0(O, ", "); \ | 1236 | 36 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 36 | CHAR(SrcRegKind), O, \ | 1238 | 36 | getUseMarkup()); \ | 1239 | 36 | } \ | 1240 | 36 | } |
printRegWithShiftExtend_0_16_x_d Line | Count | Source | 1215 | 118 | { \ | 1216 | 118 | add_cs_detail( \ | 1217 | 118 | MI, \ | 1218 | 118 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 118 | SignExtend), \ | 1220 | 118 | ExtWidth), \ | 1221 | 118 | SrcRegKind), \ | 1222 | 118 | Suffix), \ | 1223 | 118 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 118 | CHAR(Suffix)); \ | 1225 | 118 | printOperand(MI, OpNum, O); \ | 1226 | 118 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 118 | SStream_concat1(O, '.'); \ | 1228 | 118 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 118 | SStream_concat1(O, '\0'); \ | 1230 | 118 | } else \ | 1231 | 118 | assert((CHAR(Suffix) == '0') && \ | 1232 | 118 | "Unsupported suffix size"); \ | 1233 | 118 | bool DoShift = ExtWidth != 8; \ | 1234 | 118 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 118 | SStream_concat0(O, ", "); \ | 1236 | 118 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 118 | CHAR(SrcRegKind), O, \ | 1238 | 118 | getUseMarkup()); \ | 1239 | 118 | } \ | 1240 | 118 | } |
printRegWithShiftExtend_1_16_w_d Line | Count | Source | 1215 | 214 | { \ | 1216 | 214 | add_cs_detail( \ | 1217 | 214 | MI, \ | 1218 | 214 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 214 | SignExtend), \ | 1220 | 214 | ExtWidth), \ | 1221 | 214 | SrcRegKind), \ | 1222 | 214 | Suffix), \ | 1223 | 214 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 214 | CHAR(Suffix)); \ | 1225 | 214 | printOperand(MI, OpNum, O); \ | 1226 | 214 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 214 | SStream_concat1(O, '.'); \ | 1228 | 214 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 214 | SStream_concat1(O, '\0'); \ | 1230 | 214 | } else \ | 1231 | 214 | assert((CHAR(Suffix) == '0') && \ | 1232 | 214 | "Unsupported suffix size"); \ | 1233 | 214 | bool DoShift = ExtWidth != 8; \ | 1234 | 214 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 214 | SStream_concat0(O, ", "); \ | 1236 | 214 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 214 | CHAR(SrcRegKind), O, \ | 1238 | 214 | getUseMarkup()); \ | 1239 | 214 | } \ | 1240 | 214 | } |
printRegWithShiftExtend_0_16_w_d Line | Count | Source | 1215 | 167 | { \ | 1216 | 167 | add_cs_detail( \ | 1217 | 167 | MI, \ | 1218 | 167 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 167 | SignExtend), \ | 1220 | 167 | ExtWidth), \ | 1221 | 167 | SrcRegKind), \ | 1222 | 167 | Suffix), \ | 1223 | 167 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 167 | CHAR(Suffix)); \ | 1225 | 167 | printOperand(MI, OpNum, O); \ | 1226 | 167 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 167 | SStream_concat1(O, '.'); \ | 1228 | 167 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 167 | SStream_concat1(O, '\0'); \ | 1230 | 167 | } else \ | 1231 | 167 | assert((CHAR(Suffix) == '0') && \ | 1232 | 167 | "Unsupported suffix size"); \ | 1233 | 167 | bool DoShift = ExtWidth != 8; \ | 1234 | 167 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 167 | SStream_concat0(O, ", "); \ | 1236 | 167 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 167 | CHAR(SrcRegKind), O, \ | 1238 | 167 | getUseMarkup()); \ | 1239 | 167 | } \ | 1240 | 167 | } |
printRegWithShiftExtend_0_16_x_0 Line | Count | Source | 1215 | 938 | { \ | 1216 | 938 | add_cs_detail( \ | 1217 | 938 | MI, \ | 1218 | 938 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 938 | SignExtend), \ | 1220 | 938 | ExtWidth), \ | 1221 | 938 | SrcRegKind), \ | 1222 | 938 | Suffix), \ | 1223 | 938 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 938 | CHAR(Suffix)); \ | 1225 | 938 | printOperand(MI, OpNum, O); \ | 1226 | 938 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 0 | SStream_concat1(O, '.'); \ | 1228 | 0 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 0 | SStream_concat1(O, '\0'); \ | 1230 | 0 | } else \ | 1231 | 938 | assert((CHAR(Suffix) == '0') && \ | 1232 | 938 | "Unsupported suffix size"); \ | 1233 | 938 | bool DoShift = ExtWidth != 8; \ | 1234 | 938 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 938 | SStream_concat0(O, ", "); \ | 1236 | 938 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 938 | CHAR(SrcRegKind), O, \ | 1238 | 938 | getUseMarkup()); \ | 1239 | 938 | } \ | 1240 | 938 | } |
printRegWithShiftExtend_1_16_w_s Line | Count | Source | 1215 | 151 | { \ | 1216 | 151 | add_cs_detail( \ | 1217 | 151 | MI, \ | 1218 | 151 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 151 | SignExtend), \ | 1220 | 151 | ExtWidth), \ | 1221 | 151 | SrcRegKind), \ | 1222 | 151 | Suffix), \ | 1223 | 151 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 151 | CHAR(Suffix)); \ | 1225 | 151 | printOperand(MI, OpNum, O); \ | 1226 | 151 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 151 | SStream_concat1(O, '.'); \ | 1228 | 151 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 151 | SStream_concat1(O, '\0'); \ | 1230 | 151 | } else \ | 1231 | 151 | assert((CHAR(Suffix) == '0') && \ | 1232 | 151 | "Unsupported suffix size"); \ | 1233 | 151 | bool DoShift = ExtWidth != 8; \ | 1234 | 151 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 151 | SStream_concat0(O, ", "); \ | 1236 | 151 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 151 | CHAR(SrcRegKind), O, \ | 1238 | 151 | getUseMarkup()); \ | 1239 | 151 | } \ | 1240 | 151 | } |
printRegWithShiftExtend_0_16_w_s Line | Count | Source | 1215 | 749 | { \ | 1216 | 749 | add_cs_detail( \ | 1217 | 749 | MI, \ | 1218 | 749 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 749 | SignExtend), \ | 1220 | 749 | ExtWidth), \ | 1221 | 749 | SrcRegKind), \ | 1222 | 749 | Suffix), \ | 1223 | 749 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 749 | CHAR(Suffix)); \ | 1225 | 749 | printOperand(MI, OpNum, O); \ | 1226 | 749 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 749 | SStream_concat1(O, '.'); \ | 1228 | 749 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 749 | SStream_concat1(O, '\0'); \ | 1230 | 749 | } else \ | 1231 | 749 | assert((CHAR(Suffix) == '0') && \ | 1232 | 749 | "Unsupported suffix size"); \ | 1233 | 749 | bool DoShift = ExtWidth != 8; \ | 1234 | 749 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 749 | SStream_concat0(O, ", "); \ | 1236 | 749 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 749 | CHAR(SrcRegKind), O, \ | 1238 | 749 | getUseMarkup()); \ | 1239 | 749 | } \ | 1240 | 749 | } |
printRegWithShiftExtend_0_32_x_d Line | Count | Source | 1215 | 754 | { \ | 1216 | 754 | add_cs_detail( \ | 1217 | 754 | MI, \ | 1218 | 754 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 754 | SignExtend), \ | 1220 | 754 | ExtWidth), \ | 1221 | 754 | SrcRegKind), \ | 1222 | 754 | Suffix), \ | 1223 | 754 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 754 | CHAR(Suffix)); \ | 1225 | 754 | printOperand(MI, OpNum, O); \ | 1226 | 754 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 754 | SStream_concat1(O, '.'); \ | 1228 | 754 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 754 | SStream_concat1(O, '\0'); \ | 1230 | 754 | } else \ | 1231 | 754 | assert((CHAR(Suffix) == '0') && \ | 1232 | 754 | "Unsupported suffix size"); \ | 1233 | 754 | bool DoShift = ExtWidth != 8; \ | 1234 | 754 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 754 | SStream_concat0(O, ", "); \ | 1236 | 754 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 754 | CHAR(SrcRegKind), O, \ | 1238 | 754 | getUseMarkup()); \ | 1239 | 754 | } \ | 1240 | 754 | } |
printRegWithShiftExtend_1_32_w_d Line | Count | Source | 1215 | 248 | { \ | 1216 | 248 | add_cs_detail( \ | 1217 | 248 | MI, \ | 1218 | 248 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 248 | SignExtend), \ | 1220 | 248 | ExtWidth), \ | 1221 | 248 | SrcRegKind), \ | 1222 | 248 | Suffix), \ | 1223 | 248 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 248 | CHAR(Suffix)); \ | 1225 | 248 | printOperand(MI, OpNum, O); \ | 1226 | 248 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 248 | SStream_concat1(O, '.'); \ | 1228 | 248 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 248 | SStream_concat1(O, '\0'); \ | 1230 | 248 | } else \ | 1231 | 248 | assert((CHAR(Suffix) == '0') && \ | 1232 | 248 | "Unsupported suffix size"); \ | 1233 | 248 | bool DoShift = ExtWidth != 8; \ | 1234 | 248 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 248 | SStream_concat0(O, ", "); \ | 1236 | 248 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 248 | CHAR(SrcRegKind), O, \ | 1238 | 248 | getUseMarkup()); \ | 1239 | 248 | } \ | 1240 | 248 | } |
printRegWithShiftExtend_0_32_w_d Line | Count | Source | 1215 | 970 | { \ | 1216 | 970 | add_cs_detail( \ | 1217 | 970 | MI, \ | 1218 | 970 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 970 | SignExtend), \ | 1220 | 970 | ExtWidth), \ | 1221 | 970 | SrcRegKind), \ | 1222 | 970 | Suffix), \ | 1223 | 970 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 970 | CHAR(Suffix)); \ | 1225 | 970 | printOperand(MI, OpNum, O); \ | 1226 | 970 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 970 | SStream_concat1(O, '.'); \ | 1228 | 970 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 970 | SStream_concat1(O, '\0'); \ | 1230 | 970 | } else \ | 1231 | 970 | assert((CHAR(Suffix) == '0') && \ | 1232 | 970 | "Unsupported suffix size"); \ | 1233 | 970 | bool DoShift = ExtWidth != 8; \ | 1234 | 970 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 970 | SStream_concat0(O, ", "); \ | 1236 | 970 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 970 | CHAR(SrcRegKind), O, \ | 1238 | 970 | getUseMarkup()); \ | 1239 | 970 | } \ | 1240 | 970 | } |
printRegWithShiftExtend_0_32_x_0 Line | Count | Source | 1215 | 1.32k | { \ | 1216 | 1.32k | add_cs_detail( \ | 1217 | 1.32k | MI, \ | 1218 | 1.32k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.32k | SignExtend), \ | 1220 | 1.32k | ExtWidth), \ | 1221 | 1.32k | SrcRegKind), \ | 1222 | 1.32k | Suffix), \ | 1223 | 1.32k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.32k | CHAR(Suffix)); \ | 1225 | 1.32k | printOperand(MI, OpNum, O); \ | 1226 | 1.32k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 0 | SStream_concat1(O, '.'); \ | 1228 | 0 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 0 | SStream_concat1(O, '\0'); \ | 1230 | 0 | } else \ | 1231 | 1.32k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.32k | "Unsupported suffix size"); \ | 1233 | 1.32k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.32k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 1.32k | SStream_concat0(O, ", "); \ | 1236 | 1.32k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 1.32k | CHAR(SrcRegKind), O, \ | 1238 | 1.32k | getUseMarkup()); \ | 1239 | 1.32k | } \ | 1240 | 1.32k | } |
printRegWithShiftExtend_1_32_w_s Line | Count | Source | 1215 | 381 | { \ | 1216 | 381 | add_cs_detail( \ | 1217 | 381 | MI, \ | 1218 | 381 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 381 | SignExtend), \ | 1220 | 381 | ExtWidth), \ | 1221 | 381 | SrcRegKind), \ | 1222 | 381 | Suffix), \ | 1223 | 381 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 381 | CHAR(Suffix)); \ | 1225 | 381 | printOperand(MI, OpNum, O); \ | 1226 | 381 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 381 | SStream_concat1(O, '.'); \ | 1228 | 381 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 381 | SStream_concat1(O, '\0'); \ | 1230 | 381 | } else \ | 1231 | 381 | assert((CHAR(Suffix) == '0') && \ | 1232 | 381 | "Unsupported suffix size"); \ | 1233 | 381 | bool DoShift = ExtWidth != 8; \ | 1234 | 381 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 381 | SStream_concat0(O, ", "); \ | 1236 | 381 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 381 | CHAR(SrcRegKind), O, \ | 1238 | 381 | getUseMarkup()); \ | 1239 | 381 | } \ | 1240 | 381 | } |
printRegWithShiftExtend_0_32_w_s Line | Count | Source | 1215 | 339 | { \ | 1216 | 339 | add_cs_detail( \ | 1217 | 339 | MI, \ | 1218 | 339 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 339 | SignExtend), \ | 1220 | 339 | ExtWidth), \ | 1221 | 339 | SrcRegKind), \ | 1222 | 339 | Suffix), \ | 1223 | 339 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 339 | CHAR(Suffix)); \ | 1225 | 339 | printOperand(MI, OpNum, O); \ | 1226 | 339 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 339 | SStream_concat1(O, '.'); \ | 1228 | 339 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 339 | SStream_concat1(O, '\0'); \ | 1230 | 339 | } else \ | 1231 | 339 | assert((CHAR(Suffix) == '0') && \ | 1232 | 339 | "Unsupported suffix size"); \ | 1233 | 339 | bool DoShift = ExtWidth != 8; \ | 1234 | 339 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 339 | SStream_concat0(O, ", "); \ | 1236 | 339 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 339 | CHAR(SrcRegKind), O, \ | 1238 | 339 | getUseMarkup()); \ | 1239 | 339 | } \ | 1240 | 339 | } |
printRegWithShiftExtend_0_8_x_s Line | Count | Source | 1215 | 111 | { \ | 1216 | 111 | add_cs_detail( \ | 1217 | 111 | MI, \ | 1218 | 111 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 111 | SignExtend), \ | 1220 | 111 | ExtWidth), \ | 1221 | 111 | SrcRegKind), \ | 1222 | 111 | Suffix), \ | 1223 | 111 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 111 | CHAR(Suffix)); \ | 1225 | 111 | printOperand(MI, OpNum, O); \ | 1226 | 111 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 111 | SStream_concat1(O, '.'); \ | 1228 | 111 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 111 | SStream_concat1(O, '\0'); \ | 1230 | 111 | } else \ | 1231 | 111 | assert((CHAR(Suffix) == '0') && \ | 1232 | 111 | "Unsupported suffix size"); \ | 1233 | 111 | bool DoShift = ExtWidth != 8; \ | 1234 | 111 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 0 | SStream_concat0(O, ", "); \ | 1236 | 0 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 0 | CHAR(SrcRegKind), O, \ | 1238 | 0 | getUseMarkup()); \ | 1239 | 0 | } \ | 1240 | 111 | } |
printRegWithShiftExtend_0_16_x_s Line | Count | Source | 1215 | 59 | { \ | 1216 | 59 | add_cs_detail( \ | 1217 | 59 | MI, \ | 1218 | 59 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 59 | SignExtend), \ | 1220 | 59 | ExtWidth), \ | 1221 | 59 | SrcRegKind), \ | 1222 | 59 | Suffix), \ | 1223 | 59 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 59 | CHAR(Suffix)); \ | 1225 | 59 | printOperand(MI, OpNum, O); \ | 1226 | 59 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 59 | SStream_concat1(O, '.'); \ | 1228 | 59 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 59 | SStream_concat1(O, '\0'); \ | 1230 | 59 | } else \ | 1231 | 59 | assert((CHAR(Suffix) == '0') && \ | 1232 | 59 | "Unsupported suffix size"); \ | 1233 | 59 | bool DoShift = ExtWidth != 8; \ | 1234 | 59 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 59 | SStream_concat0(O, ", "); \ | 1236 | 59 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 59 | CHAR(SrcRegKind), O, \ | 1238 | 59 | getUseMarkup()); \ | 1239 | 59 | } \ | 1240 | 59 | } |
printRegWithShiftExtend_0_32_x_s Line | Count | Source | 1215 | 280 | { \ | 1216 | 280 | add_cs_detail( \ | 1217 | 280 | MI, \ | 1218 | 280 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 280 | SignExtend), \ | 1220 | 280 | ExtWidth), \ | 1221 | 280 | SrcRegKind), \ | 1222 | 280 | Suffix), \ | 1223 | 280 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 280 | CHAR(Suffix)); \ | 1225 | 280 | printOperand(MI, OpNum, O); \ | 1226 | 280 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 280 | SStream_concat1(O, '.'); \ | 1228 | 280 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 280 | SStream_concat1(O, '\0'); \ | 1230 | 280 | } else \ | 1231 | 280 | assert((CHAR(Suffix) == '0') && \ | 1232 | 280 | "Unsupported suffix size"); \ | 1233 | 280 | bool DoShift = ExtWidth != 8; \ | 1234 | 280 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 280 | SStream_concat0(O, ", "); \ | 1236 | 280 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 280 | CHAR(SrcRegKind), O, \ | 1238 | 280 | getUseMarkup()); \ | 1239 | 280 | } \ | 1240 | 280 | } |
printRegWithShiftExtend_0_64_x_s Line | Count | Source | 1215 | 20 | { \ | 1216 | 20 | add_cs_detail( \ | 1217 | 20 | MI, \ | 1218 | 20 | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 20 | SignExtend), \ | 1220 | 20 | ExtWidth), \ | 1221 | 20 | SrcRegKind), \ | 1222 | 20 | Suffix), \ | 1223 | 20 | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 20 | CHAR(Suffix)); \ | 1225 | 20 | printOperand(MI, OpNum, O); \ | 1226 | 20 | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 20 | SStream_concat1(O, '.'); \ | 1228 | 20 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 20 | SStream_concat1(O, '\0'); \ | 1230 | 20 | } else \ | 1231 | 20 | assert((CHAR(Suffix) == '0') && \ | 1232 | 20 | "Unsupported suffix size"); \ | 1233 | 20 | bool DoShift = ExtWidth != 8; \ | 1234 | 20 | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 20 | SStream_concat0(O, ", "); \ | 1236 | 20 | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 20 | CHAR(SrcRegKind), O, \ | 1238 | 20 | getUseMarkup()); \ | 1239 | 20 | } \ | 1240 | 20 | } |
printRegWithShiftExtend_0_128_x_0 Line | Count | Source | 1215 | 1.09k | { \ | 1216 | 1.09k | add_cs_detail( \ | 1217 | 1.09k | MI, \ | 1218 | 1.09k | CONCAT(CONCAT(CONCAT(CONCAT(AArch64_OP_GROUP_RegWithShiftExtend, \ | 1219 | 1.09k | SignExtend), \ | 1220 | 1.09k | ExtWidth), \ | 1221 | 1.09k | SrcRegKind), \ | 1222 | 1.09k | Suffix), \ | 1223 | 1.09k | OpNum, SignExtend, ExtWidth, CHAR(SrcRegKind), \ | 1224 | 1.09k | CHAR(Suffix)); \ | 1225 | 1.09k | printOperand(MI, OpNum, O); \ | 1226 | 1.09k | if (CHAR(Suffix) == 's' || CHAR(Suffix) == 'd') { \ | 1227 | 0 | SStream_concat1(O, '.'); \ | 1228 | 0 | SStream_concat1(O, CHAR(Suffix)); \ | 1229 | 0 | SStream_concat1(O, '\0'); \ | 1230 | 0 | } else \ | 1231 | 1.09k | assert((CHAR(Suffix) == '0') && \ | 1232 | 1.09k | "Unsupported suffix size"); \ | 1233 | 1.09k | bool DoShift = ExtWidth != 8; \ | 1234 | 1.09k | if (SignExtend || DoShift || CHAR(SrcRegKind) == 'w') { \ | 1235 | 1.09k | SStream_concat0(O, ", "); \ | 1236 | 1.09k | printMemExtendImpl(SignExtend, DoShift, ExtWidth, \ | 1237 | 1.09k | CHAR(SrcRegKind), O, \ | 1238 | 1.09k | getUseMarkup()); \ | 1239 | 1.09k | } \ | 1240 | 1.09k | } |
|
1241 | | DEFINE_printRegWithShiftExtend(false, 8, x, d); |
1242 | | DEFINE_printRegWithShiftExtend(true, 8, w, d); |
1243 | | DEFINE_printRegWithShiftExtend(false, 8, w, d); |
1244 | | DEFINE_printRegWithShiftExtend(false, 8, x, 0); |
1245 | | DEFINE_printRegWithShiftExtend(true, 8, w, s); |
1246 | | DEFINE_printRegWithShiftExtend(false, 8, w, s); |
1247 | | DEFINE_printRegWithShiftExtend(false, 64, x, d); |
1248 | | DEFINE_printRegWithShiftExtend(true, 64, w, d); |
1249 | | DEFINE_printRegWithShiftExtend(false, 64, w, d); |
1250 | | DEFINE_printRegWithShiftExtend(false, 64, x, 0); |
1251 | | DEFINE_printRegWithShiftExtend(true, 64, w, s); |
1252 | | DEFINE_printRegWithShiftExtend(false, 64, w, s); |
1253 | | DEFINE_printRegWithShiftExtend(false, 16, x, d); |
1254 | | DEFINE_printRegWithShiftExtend(true, 16, w, d); |
1255 | | DEFINE_printRegWithShiftExtend(false, 16, w, d); |
1256 | | DEFINE_printRegWithShiftExtend(false, 16, x, 0); |
1257 | | DEFINE_printRegWithShiftExtend(true, 16, w, s); |
1258 | | DEFINE_printRegWithShiftExtend(false, 16, w, s); |
1259 | | DEFINE_printRegWithShiftExtend(false, 32, x, d); |
1260 | | DEFINE_printRegWithShiftExtend(true, 32, w, d); |
1261 | | DEFINE_printRegWithShiftExtend(false, 32, w, d); |
1262 | | DEFINE_printRegWithShiftExtend(false, 32, x, 0); |
1263 | | DEFINE_printRegWithShiftExtend(true, 32, w, s); |
1264 | | DEFINE_printRegWithShiftExtend(false, 32, w, s); |
1265 | | DEFINE_printRegWithShiftExtend(false, 8, x, s); |
1266 | | DEFINE_printRegWithShiftExtend(false, 16, x, s); |
1267 | | DEFINE_printRegWithShiftExtend(false, 32, x, s); |
1268 | | DEFINE_printRegWithShiftExtend(false, 64, x, s); |
1269 | | DEFINE_printRegWithShiftExtend(false, 128, x, 0); |
1270 | | |
1271 | | #define DEFINE_printPredicateAsCounter(EltSize) \ |
1272 | | void CONCAT(printPredicateAsCounter, \ |
1273 | | EltSize)(MCInst * MI, unsigned OpNum, SStream *O) \ |
1274 | 10.6k | { \ |
1275 | 10.6k | add_cs_detail(MI, \ |
1276 | 10.6k | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ |
1277 | 10.6k | EltSize), \ |
1278 | 10.6k | OpNum, EltSize); \ |
1279 | 10.6k | unsigned Reg = \ |
1280 | 10.6k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ |
1281 | 10.6k | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ |
1282 | 10.6k | assert(0 && \ |
1283 | 10.6k | "Unsupported predicate-as-counter register"); \ |
1284 | 10.6k | SStream_concat(O, "%s", "pn"); \ |
1285 | 10.6k | printUInt32(O, (Reg - AArch64_P0)); \ |
1286 | 10.6k | switch (EltSize) { \ |
1287 | 9.13k | case 0: \ |
1288 | 9.13k | break; \ |
1289 | 66 | case 8: \ |
1290 | 66 | SStream_concat0(O, ".b"); \ |
1291 | 66 | break; \ |
1292 | 719 | case 16: \ |
1293 | 719 | SStream_concat0(O, ".h"); \ |
1294 | 719 | break; \ |
1295 | 210 | case 32: \ |
1296 | 210 | SStream_concat0(O, ".s"); \ |
1297 | 210 | break; \ |
1298 | 516 | case 64: \ |
1299 | 516 | SStream_concat0(O, ".d"); \ |
1300 | 516 | break; \ |
1301 | 0 | default: \ |
1302 | 0 | assert(0 && "Unsupported element size"); \ |
1303 | 10.6k | } \ |
1304 | 10.6k | } printPredicateAsCounter_8 Line | Count | Source | 1274 | 66 | { \ | 1275 | 66 | add_cs_detail(MI, \ | 1276 | 66 | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ | 1277 | 66 | EltSize), \ | 1278 | 66 | OpNum, EltSize); \ | 1279 | 66 | unsigned Reg = \ | 1280 | 66 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1281 | 66 | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ | 1282 | 66 | assert(0 && \ | 1283 | 66 | "Unsupported predicate-as-counter register"); \ | 1284 | 66 | SStream_concat(O, "%s", "pn"); \ | 1285 | 66 | printUInt32(O, (Reg - AArch64_P0)); \ | 1286 | 66 | switch (EltSize) { \ | 1287 | 0 | case 0: \ | 1288 | 0 | break; \ | 1289 | 66 | case 8: \ | 1290 | 66 | SStream_concat0(O, ".b"); \ | 1291 | 66 | break; \ | 1292 | 0 | case 16: \ | 1293 | 0 | SStream_concat0(O, ".h"); \ | 1294 | 0 | break; \ | 1295 | 0 | case 32: \ | 1296 | 0 | SStream_concat0(O, ".s"); \ | 1297 | 0 | break; \ | 1298 | 0 | case 64: \ | 1299 | 0 | SStream_concat0(O, ".d"); \ | 1300 | 0 | break; \ | 1301 | 0 | default: \ | 1302 | 0 | assert(0 && "Unsupported element size"); \ | 1303 | 66 | } \ | 1304 | 66 | } |
printPredicateAsCounter_64 Line | Count | Source | 1274 | 516 | { \ | 1275 | 516 | add_cs_detail(MI, \ | 1276 | 516 | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ | 1277 | 516 | EltSize), \ | 1278 | 516 | OpNum, EltSize); \ | 1279 | 516 | unsigned Reg = \ | 1280 | 516 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1281 | 516 | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ | 1282 | 516 | assert(0 && \ | 1283 | 516 | "Unsupported predicate-as-counter register"); \ | 1284 | 516 | SStream_concat(O, "%s", "pn"); \ | 1285 | 516 | printUInt32(O, (Reg - AArch64_P0)); \ | 1286 | 516 | switch (EltSize) { \ | 1287 | 0 | case 0: \ | 1288 | 0 | break; \ | 1289 | 0 | case 8: \ | 1290 | 0 | SStream_concat0(O, ".b"); \ | 1291 | 0 | break; \ | 1292 | 0 | case 16: \ | 1293 | 0 | SStream_concat0(O, ".h"); \ | 1294 | 0 | break; \ | 1295 | 0 | case 32: \ | 1296 | 0 | SStream_concat0(O, ".s"); \ | 1297 | 0 | break; \ | 1298 | 516 | case 64: \ | 1299 | 516 | SStream_concat0(O, ".d"); \ | 1300 | 516 | break; \ | 1301 | 0 | default: \ | 1302 | 0 | assert(0 && "Unsupported element size"); \ | 1303 | 516 | } \ | 1304 | 516 | } |
printPredicateAsCounter_16 Line | Count | Source | 1274 | 719 | { \ | 1275 | 719 | add_cs_detail(MI, \ | 1276 | 719 | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ | 1277 | 719 | EltSize), \ | 1278 | 719 | OpNum, EltSize); \ | 1279 | 719 | unsigned Reg = \ | 1280 | 719 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1281 | 719 | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ | 1282 | 719 | assert(0 && \ | 1283 | 719 | "Unsupported predicate-as-counter register"); \ | 1284 | 719 | SStream_concat(O, "%s", "pn"); \ | 1285 | 719 | printUInt32(O, (Reg - AArch64_P0)); \ | 1286 | 719 | switch (EltSize) { \ | 1287 | 0 | case 0: \ | 1288 | 0 | break; \ | 1289 | 0 | case 8: \ | 1290 | 0 | SStream_concat0(O, ".b"); \ | 1291 | 0 | break; \ | 1292 | 719 | case 16: \ | 1293 | 719 | SStream_concat0(O, ".h"); \ | 1294 | 719 | break; \ | 1295 | 0 | case 32: \ | 1296 | 0 | SStream_concat0(O, ".s"); \ | 1297 | 0 | break; \ | 1298 | 0 | case 64: \ | 1299 | 0 | SStream_concat0(O, ".d"); \ | 1300 | 0 | break; \ | 1301 | 0 | default: \ | 1302 | 0 | assert(0 && "Unsupported element size"); \ | 1303 | 719 | } \ | 1304 | 719 | } |
printPredicateAsCounter_32 Line | Count | Source | 1274 | 210 | { \ | 1275 | 210 | add_cs_detail(MI, \ | 1276 | 210 | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ | 1277 | 210 | EltSize), \ | 1278 | 210 | OpNum, EltSize); \ | 1279 | 210 | unsigned Reg = \ | 1280 | 210 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1281 | 210 | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ | 1282 | 210 | assert(0 && \ | 1283 | 210 | "Unsupported predicate-as-counter register"); \ | 1284 | 210 | SStream_concat(O, "%s", "pn"); \ | 1285 | 210 | printUInt32(O, (Reg - AArch64_P0)); \ | 1286 | 210 | switch (EltSize) { \ | 1287 | 0 | case 0: \ | 1288 | 0 | break; \ | 1289 | 0 | case 8: \ | 1290 | 0 | SStream_concat0(O, ".b"); \ | 1291 | 0 | break; \ | 1292 | 0 | case 16: \ | 1293 | 0 | SStream_concat0(O, ".h"); \ | 1294 | 0 | break; \ | 1295 | 210 | case 32: \ | 1296 | 210 | SStream_concat0(O, ".s"); \ | 1297 | 210 | break; \ | 1298 | 0 | case 64: \ | 1299 | 0 | SStream_concat0(O, ".d"); \ | 1300 | 0 | break; \ | 1301 | 0 | default: \ | 1302 | 0 | assert(0 && "Unsupported element size"); \ | 1303 | 210 | } \ | 1304 | 210 | } |
printPredicateAsCounter_0 Line | Count | Source | 1274 | 9.13k | { \ | 1275 | 9.13k | add_cs_detail(MI, \ | 1276 | 9.13k | CONCAT(AArch64_OP_GROUP_PredicateAsCounter, \ | 1277 | 9.13k | EltSize), \ | 1278 | 9.13k | OpNum, EltSize); \ | 1279 | 9.13k | unsigned Reg = \ | 1280 | 9.13k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1281 | 9.13k | if (Reg < AArch64_PN0 || Reg > AArch64_PN15) \ | 1282 | 9.13k | assert(0 && \ | 1283 | 9.13k | "Unsupported predicate-as-counter register"); \ | 1284 | 9.13k | SStream_concat(O, "%s", "pn"); \ | 1285 | 9.13k | printUInt32(O, (Reg - AArch64_P0)); \ | 1286 | 9.13k | switch (EltSize) { \ | 1287 | 9.13k | case 0: \ | 1288 | 9.13k | break; \ | 1289 | 0 | case 8: \ | 1290 | 0 | SStream_concat0(O, ".b"); \ | 1291 | 0 | break; \ | 1292 | 0 | case 16: \ | 1293 | 0 | SStream_concat0(O, ".h"); \ | 1294 | 0 | break; \ | 1295 | 0 | case 32: \ | 1296 | 0 | SStream_concat0(O, ".s"); \ | 1297 | 0 | break; \ | 1298 | 0 | case 64: \ | 1299 | 0 | SStream_concat0(O, ".d"); \ | 1300 | 0 | break; \ | 1301 | 0 | default: \ | 1302 | 0 | assert(0 && "Unsupported element size"); \ | 1303 | 9.13k | } \ | 1304 | 9.13k | } |
|
1305 | | DEFINE_printPredicateAsCounter(8); |
1306 | | DEFINE_printPredicateAsCounter(64); |
1307 | | DEFINE_printPredicateAsCounter(16); |
1308 | | DEFINE_printPredicateAsCounter(32); |
1309 | | DEFINE_printPredicateAsCounter(0); |
1310 | | |
1311 | | void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) |
1312 | 2.11k | { |
1313 | 2.11k | add_cs_detail(MI, AArch64_OP_GROUP_CondCode, OpNum); |
1314 | 2.11k | AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm( |
1315 | 2.11k | MCInst_getOperand(MI, (OpNum))); |
1316 | 2.11k | SStream_concat0(O, AArch64CC_getCondCodeName(CC)); |
1317 | 2.11k | } |
1318 | | |
1319 | | void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) |
1320 | 217 | { |
1321 | 217 | add_cs_detail(MI, AArch64_OP_GROUP_InverseCondCode, OpNum); |
1322 | 217 | AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm( |
1323 | 217 | MCInst_getOperand(MI, (OpNum))); |
1324 | 217 | SStream_concat0(O, AArch64CC_getCondCodeName( |
1325 | 217 | AArch64CC_getInvertedCondCode(CC))); |
1326 | 217 | } |
1327 | | |
1328 | | void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O) |
1329 | 0 | { |
1330 | 0 | add_cs_detail(MI, AArch64_OP_GROUP_AMNoIndex, OpNum); |
1331 | 0 | SStream_concat0(O, "["); |
1332 | |
|
1333 | 0 | printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); |
1334 | 0 | SStream_concat0(O, "]"); |
1335 | 0 | } |
1336 | | |
1337 | | #define DEFINE_printImmScale(Scale) \ |
1338 | | void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \ |
1339 | | SStream *O) \ |
1340 | 28.6k | { \ |
1341 | 28.6k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ |
1342 | 28.6k | OpNum, Scale); \ |
1343 | 28.6k | SStream_concat(O, "%s", markup("<imm:")); \ |
1344 | 28.6k | printInt32Bang(O, Scale *MCOperand_getImm( \ |
1345 | 28.6k | MCInst_getOperand(MI, (OpNum)))); \ |
1346 | 28.6k | SStream_concat0(O, markup(">")); \ |
1347 | 28.6k | } Line | Count | Source | 1340 | 8.75k | { \ | 1341 | 8.75k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 8.75k | OpNum, Scale); \ | 1343 | 8.75k | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 8.75k | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 8.75k | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 8.75k | SStream_concat0(O, markup(">")); \ | 1347 | 8.75k | } |
Line | Count | Source | 1340 | 2.25k | { \ | 1341 | 2.25k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 2.25k | OpNum, Scale); \ | 1343 | 2.25k | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 2.25k | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 2.25k | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 2.25k | SStream_concat0(O, markup(">")); \ | 1347 | 2.25k | } |
Line | Count | Source | 1340 | 11.9k | { \ | 1341 | 11.9k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 11.9k | OpNum, Scale); \ | 1343 | 11.9k | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 11.9k | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 11.9k | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 11.9k | SStream_concat0(O, markup(">")); \ | 1347 | 11.9k | } |
Line | Count | Source | 1340 | 5.35k | { \ | 1341 | 5.35k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 5.35k | OpNum, Scale); \ | 1343 | 5.35k | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 5.35k | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 5.35k | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 5.35k | SStream_concat0(O, markup(">")); \ | 1347 | 5.35k | } |
Line | Count | Source | 1340 | 121 | { \ | 1341 | 121 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 121 | OpNum, Scale); \ | 1343 | 121 | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 121 | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 121 | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 121 | SStream_concat0(O, markup(">")); \ | 1347 | 121 | } |
Line | Count | Source | 1340 | 207 | { \ | 1341 | 207 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ImmScale, Scale), \ | 1342 | 207 | OpNum, Scale); \ | 1343 | 207 | SStream_concat(O, "%s", markup("<imm:")); \ | 1344 | 207 | printInt32Bang(O, Scale *MCOperand_getImm( \ | 1345 | 207 | MCInst_getOperand(MI, (OpNum)))); \ | 1346 | 207 | SStream_concat0(O, markup(">")); \ | 1347 | 207 | } |
|
1348 | | DEFINE_printImmScale(8); |
1349 | | DEFINE_printImmScale(2); |
1350 | | DEFINE_printImmScale(4); |
1351 | | DEFINE_printImmScale(16); |
1352 | | DEFINE_printImmScale(32); |
1353 | | DEFINE_printImmScale(3); |
1354 | | |
1355 | | #define DEFINE_printImmRangeScale(Scale, Offset) \ |
1356 | | void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \ |
1357 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
1358 | 8.48k | { \ |
1359 | 8.48k | add_cs_detail( \ |
1360 | 8.48k | MI, \ |
1361 | 8.48k | CONCAT(CONCAT(AArch64_OP_GROUP_ImmRangeScale, Scale), \ |
1362 | 8.48k | Offset), \ |
1363 | 8.48k | OpNum, Scale, Offset); \ |
1364 | 8.48k | unsigned FirstImm = \ |
1365 | 8.48k | Scale * \ |
1366 | 8.48k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
1367 | 8.48k | printUInt32(O, (FirstImm)); \ |
1368 | 8.48k | SStream_concat(O, "%s", ":"); \ |
1369 | 8.48k | printUInt32(O, (FirstImm + Offset)); \ |
1370 | 8.48k | SStream_concat1(O, '\0'); \ |
1371 | 8.48k | } Line | Count | Source | 1358 | 4.04k | { \ | 1359 | 4.04k | add_cs_detail( \ | 1360 | 4.04k | MI, \ | 1361 | 4.04k | CONCAT(CONCAT(AArch64_OP_GROUP_ImmRangeScale, Scale), \ | 1362 | 4.04k | Offset), \ | 1363 | 4.04k | OpNum, Scale, Offset); \ | 1364 | 4.04k | unsigned FirstImm = \ | 1365 | 4.04k | Scale * \ | 1366 | 4.04k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1367 | 4.04k | printUInt32(O, (FirstImm)); \ | 1368 | 4.04k | SStream_concat(O, "%s", ":"); \ | 1369 | 4.04k | printUInt32(O, (FirstImm + Offset)); \ | 1370 | 4.04k | SStream_concat1(O, '\0'); \ | 1371 | 4.04k | } |
Line | Count | Source | 1358 | 4.44k | { \ | 1359 | 4.44k | add_cs_detail( \ | 1360 | 4.44k | MI, \ | 1361 | 4.44k | CONCAT(CONCAT(AArch64_OP_GROUP_ImmRangeScale, Scale), \ | 1362 | 4.44k | Offset), \ | 1363 | 4.44k | OpNum, Scale, Offset); \ | 1364 | 4.44k | unsigned FirstImm = \ | 1365 | 4.44k | Scale * \ | 1366 | 4.44k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1367 | 4.44k | printUInt32(O, (FirstImm)); \ | 1368 | 4.44k | SStream_concat(O, "%s", ":"); \ | 1369 | 4.44k | printUInt32(O, (FirstImm + Offset)); \ | 1370 | 4.44k | SStream_concat1(O, '\0'); \ | 1371 | 4.44k | } |
|
1372 | | DEFINE_printImmRangeScale(2, 1); |
1373 | | DEFINE_printImmRangeScale(4, 3); |
1374 | | |
1375 | | void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) |
1376 | 6.91k | { |
1377 | 6.91k | MCOperand *MO = MCInst_getOperand(MI, (OpNum)); |
1378 | 6.91k | if (MCOperand_isImm(MO)) { |
1379 | 6.91k | SStream_concat(O, "%s", markup("<imm:")); |
1380 | 6.91k | printUInt32Bang(O, (MCOperand_getImm(MO) * Scale)); |
1381 | 6.91k | SStream_concat0(O, markup(">")); |
1382 | 6.91k | } else { |
1383 | 0 | SStream_concat0(O, "<llvm-expr>"); |
1384 | 0 | } |
1385 | 6.91k | } |
1386 | | |
1387 | | void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) |
1388 | 0 | { |
1389 | 0 | MCOperand *MO1 = MCInst_getOperand(MI, (OpNum + 1)); |
1390 | 0 | SStream_concat0(O, "["); |
1391 | |
|
1392 | 0 | printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); |
1393 | 0 | if (MCOperand_isImm(MO1)) { |
1394 | 0 | SStream_concat(O, "%s%s", ", ", markup("<imm:")); |
1395 | 0 | printUInt32Bang(O, MCOperand_getImm(MO1) * Scale); |
1396 | 0 | SStream_concat0(O, markup(">")); |
1397 | 0 | } else { |
1398 | 0 | SStream_concat0(O, "<llvm-expr>"); |
1399 | 0 | } |
1400 | 0 | SStream_concat0(O, "]"); |
1401 | 0 | } |
1402 | | |
1403 | | void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O) |
1404 | 126 | { |
1405 | 126 | add_cs_detail(MI, AArch64_OP_GROUP_RPRFMOperand, OpNum); |
1406 | 126 | unsigned prfop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1407 | 126 | const AArch64PRFM_PRFM *PRFM = |
1408 | 126 | AArch64RPRFM_lookupRPRFMByEncoding(prfop); |
1409 | 126 | if (PRFM) { |
1410 | 76 | SStream_concat0(O, PRFM->Name); |
1411 | 76 | return; |
1412 | 76 | } |
1413 | | |
1414 | 50 | printUInt32Bang(O, (prfop)); |
1415 | 50 | SStream_concat1(O, '\0'); |
1416 | 50 | } |
1417 | | |
1418 | | #define DEFINE_printPrefetchOp(IsSVEPrefetch) \ |
1419 | | void CONCAT(printPrefetchOp, \ |
1420 | | IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O) \ |
1421 | 8.08k | { \ |
1422 | 8.08k | add_cs_detail(MI, \ |
1423 | 8.08k | CONCAT(AArch64_OP_GROUP_PrefetchOp, \ |
1424 | 8.08k | IsSVEPrefetch), \ |
1425 | 8.08k | OpNum, IsSVEPrefetch); \ |
1426 | 8.08k | unsigned prfop = \ |
1427 | 8.08k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
1428 | 8.08k | if (IsSVEPrefetch) { \ |
1429 | 4.49k | const AArch64SVEPRFM_SVEPRFM *PRFM = \ |
1430 | 4.49k | AArch64SVEPRFM_lookupSVEPRFMByEncoding(prfop); \ |
1431 | 4.49k | if (PRFM) { \ |
1432 | 3.28k | SStream_concat0(O, PRFM->Name); \ |
1433 | 3.28k | return; \ |
1434 | 3.28k | } \ |
1435 | 4.49k | } else { \ |
1436 | 3.58k | const AArch64PRFM_PRFM *PRFM = \ |
1437 | 3.58k | AArch64PRFM_lookupPRFMByEncoding(prfop); \ |
1438 | 3.58k | if (PRFM && \ |
1439 | 3.58k | AArch64_testFeatureList(MI->csh->mode, \ |
1440 | 2.68k | PRFM->FeaturesRequired)) { \ |
1441 | 2.68k | SStream_concat0(O, PRFM->Name); \ |
1442 | 2.68k | return; \ |
1443 | 2.68k | } \ |
1444 | 3.58k | } \ |
1445 | 8.08k | \ |
1446 | 8.08k | SStream_concat(O, "%s", markup("<imm:")); \ |
1447 | 2.11k | printUInt32Bang(O, (prfop)); \ |
1448 | 2.11k | SStream_concat0(O, markup(">")); \ |
1449 | 2.11k | } Line | Count | Source | 1421 | 3.58k | { \ | 1422 | 3.58k | add_cs_detail(MI, \ | 1423 | 3.58k | CONCAT(AArch64_OP_GROUP_PrefetchOp, \ | 1424 | 3.58k | IsSVEPrefetch), \ | 1425 | 3.58k | OpNum, IsSVEPrefetch); \ | 1426 | 3.58k | unsigned prfop = \ | 1427 | 3.58k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1428 | 3.58k | if (IsSVEPrefetch) { \ | 1429 | 0 | const AArch64SVEPRFM_SVEPRFM *PRFM = \ | 1430 | 0 | AArch64SVEPRFM_lookupSVEPRFMByEncoding(prfop); \ | 1431 | 0 | if (PRFM) { \ | 1432 | 0 | SStream_concat0(O, PRFM->Name); \ | 1433 | 0 | return; \ | 1434 | 0 | } \ | 1435 | 3.58k | } else { \ | 1436 | 3.58k | const AArch64PRFM_PRFM *PRFM = \ | 1437 | 3.58k | AArch64PRFM_lookupPRFMByEncoding(prfop); \ | 1438 | 3.58k | if (PRFM && \ | 1439 | 3.58k | AArch64_testFeatureList(MI->csh->mode, \ | 1440 | 2.68k | PRFM->FeaturesRequired)) { \ | 1441 | 2.68k | SStream_concat0(O, PRFM->Name); \ | 1442 | 2.68k | return; \ | 1443 | 2.68k | } \ | 1444 | 3.58k | } \ | 1445 | 3.58k | \ | 1446 | 3.58k | SStream_concat(O, "%s", markup("<imm:")); \ | 1447 | 901 | printUInt32Bang(O, (prfop)); \ | 1448 | 901 | SStream_concat0(O, markup(">")); \ | 1449 | 901 | } |
Line | Count | Source | 1421 | 4.49k | { \ | 1422 | 4.49k | add_cs_detail(MI, \ | 1423 | 4.49k | CONCAT(AArch64_OP_GROUP_PrefetchOp, \ | 1424 | 4.49k | IsSVEPrefetch), \ | 1425 | 4.49k | OpNum, IsSVEPrefetch); \ | 1426 | 4.49k | unsigned prfop = \ | 1427 | 4.49k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 1428 | 4.49k | if (IsSVEPrefetch) { \ | 1429 | 4.49k | const AArch64SVEPRFM_SVEPRFM *PRFM = \ | 1430 | 4.49k | AArch64SVEPRFM_lookupSVEPRFMByEncoding(prfop); \ | 1431 | 4.49k | if (PRFM) { \ | 1432 | 3.28k | SStream_concat0(O, PRFM->Name); \ | 1433 | 3.28k | return; \ | 1434 | 3.28k | } \ | 1435 | 4.49k | } else { \ | 1436 | 0 | const AArch64PRFM_PRFM *PRFM = \ | 1437 | 0 | AArch64PRFM_lookupPRFMByEncoding(prfop); \ | 1438 | 0 | if (PRFM && \ | 1439 | 0 | AArch64_testFeatureList(MI->csh->mode, \ | 1440 | 0 | PRFM->FeaturesRequired)) { \ | 1441 | 0 | SStream_concat0(O, PRFM->Name); \ | 1442 | 0 | return; \ | 1443 | 0 | } \ | 1444 | 0 | } \ | 1445 | 4.49k | \ | 1446 | 4.49k | SStream_concat(O, "%s", markup("<imm:")); \ | 1447 | 1.21k | printUInt32Bang(O, (prfop)); \ | 1448 | 1.21k | SStream_concat0(O, markup(">")); \ | 1449 | 1.21k | } |
|
1450 | | DEFINE_printPrefetchOp(false); |
1451 | | DEFINE_printPrefetchOp(true); |
1452 | | |
1453 | | void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) |
1454 | 282 | { |
1455 | 282 | add_cs_detail(MI, AArch64_OP_GROUP_PSBHintOp, OpNum); |
1456 | 282 | unsigned psbhintop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1457 | 282 | const AArch64PSBHint_PSB *PSB = |
1458 | 282 | AArch64PSBHint_lookupPSBByEncoding(psbhintop); |
1459 | 282 | if (PSB) |
1460 | 282 | SStream_concat0(O, PSB->Name); |
1461 | 0 | else { |
1462 | 0 | SStream_concat(O, "%s", markup("<imm:")); |
1463 | 0 | SStream_concat1(O, '#'); |
1464 | 0 | printUInt32Bang(O, (psbhintop)); |
1465 | 0 | SStream_concat0(O, markup(">")); |
1466 | 0 | } |
1467 | 282 | } |
1468 | | |
1469 | | void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) |
1470 | 142 | { |
1471 | 142 | add_cs_detail(MI, AArch64_OP_GROUP_BTIHintOp, OpNum); |
1472 | 142 | unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) ^ |
1473 | 142 | 32; |
1474 | 142 | const AArch64BTIHint_BTI *BTI = |
1475 | 142 | AArch64BTIHint_lookupBTIByEncoding(btihintop); |
1476 | 142 | if (BTI) |
1477 | 142 | SStream_concat0(O, BTI->Name); |
1478 | 0 | else { |
1479 | 0 | SStream_concat(O, "%s", markup("<imm:")); |
1480 | 0 | printUInt32Bang(O, (btihintop)); |
1481 | 0 | SStream_concat0(O, markup(">")); |
1482 | 0 | } |
1483 | 142 | } |
1484 | | |
1485 | | static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
1486 | 957 | { |
1487 | 957 | add_cs_detail(MI, AArch64_OP_GROUP_FPImmOperand, OpNum); |
1488 | 957 | MCOperand *MO = MCInst_getOperand(MI, (OpNum)); |
1489 | 957 | float FPImm = MCOperand_isDFPImm(MO) ? |
1490 | 0 | BitsToDouble(MCOperand_getImm(MO)) : |
1491 | 957 | AArch64_AM_getFPImmFloat(MCOperand_getImm(MO)); |
1492 | | |
1493 | | // 8 decimal places are enough to perfectly represent permitted floats. |
1494 | 957 | SStream_concat(O, "%s", markup("<imm:")); |
1495 | 957 | SStream_concat(O, "#%.8f", FPImm); |
1496 | 957 | SStream_concat0(O, markup(">")); |
1497 | 957 | } |
1498 | | |
1499 | | static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride /* = 1 */) |
1500 | 134k | { |
1501 | 337k | while (Stride--) { |
1502 | 202k | switch (Reg) { |
1503 | 0 | default: |
1504 | 0 | assert(0 && "Vector register expected!"); |
1505 | 3.71k | case AArch64_Q0: |
1506 | 3.71k | Reg = AArch64_Q1; |
1507 | 3.71k | break; |
1508 | 3.27k | case AArch64_Q1: |
1509 | 3.27k | Reg = AArch64_Q2; |
1510 | 3.27k | break; |
1511 | 954 | case AArch64_Q2: |
1512 | 954 | Reg = AArch64_Q3; |
1513 | 954 | break; |
1514 | 891 | case AArch64_Q3: |
1515 | 891 | Reg = AArch64_Q4; |
1516 | 891 | break; |
1517 | 793 | case AArch64_Q4: |
1518 | 793 | Reg = AArch64_Q5; |
1519 | 793 | break; |
1520 | 675 | case AArch64_Q5: |
1521 | 675 | Reg = AArch64_Q6; |
1522 | 675 | break; |
1523 | 1.53k | case AArch64_Q6: |
1524 | 1.53k | Reg = AArch64_Q7; |
1525 | 1.53k | break; |
1526 | 2.49k | case AArch64_Q7: |
1527 | 2.49k | Reg = AArch64_Q8; |
1528 | 2.49k | break; |
1529 | 2.38k | case AArch64_Q8: |
1530 | 2.38k | Reg = AArch64_Q9; |
1531 | 2.38k | break; |
1532 | 3.02k | case AArch64_Q9: |
1533 | 3.02k | Reg = AArch64_Q10; |
1534 | 3.02k | break; |
1535 | 2.59k | case AArch64_Q10: |
1536 | 2.59k | Reg = AArch64_Q11; |
1537 | 2.59k | break; |
1538 | 1.26k | case AArch64_Q11: |
1539 | 1.26k | Reg = AArch64_Q12; |
1540 | 1.26k | break; |
1541 | 666 | case AArch64_Q12: |
1542 | 666 | Reg = AArch64_Q13; |
1543 | 666 | break; |
1544 | 532 | case AArch64_Q13: |
1545 | 532 | Reg = AArch64_Q14; |
1546 | 532 | break; |
1547 | 1.65k | case AArch64_Q14: |
1548 | 1.65k | Reg = AArch64_Q15; |
1549 | 1.65k | break; |
1550 | 1.64k | case AArch64_Q15: |
1551 | 1.64k | Reg = AArch64_Q16; |
1552 | 1.64k | break; |
1553 | 1.63k | case AArch64_Q16: |
1554 | 1.63k | Reg = AArch64_Q17; |
1555 | 1.63k | break; |
1556 | 1.50k | case AArch64_Q17: |
1557 | 1.50k | Reg = AArch64_Q18; |
1558 | 1.50k | break; |
1559 | 566 | case AArch64_Q18: |
1560 | 566 | Reg = AArch64_Q19; |
1561 | 566 | break; |
1562 | 565 | case AArch64_Q19: |
1563 | 565 | Reg = AArch64_Q20; |
1564 | 565 | break; |
1565 | 4.97k | case AArch64_Q20: |
1566 | 4.97k | Reg = AArch64_Q21; |
1567 | 4.97k | break; |
1568 | 3.14k | case AArch64_Q21: |
1569 | 3.14k | Reg = AArch64_Q22; |
1570 | 3.14k | break; |
1571 | 4.22k | case AArch64_Q22: |
1572 | 4.22k | Reg = AArch64_Q23; |
1573 | 4.22k | break; |
1574 | 2.35k | case AArch64_Q23: |
1575 | 2.35k | Reg = AArch64_Q24; |
1576 | 2.35k | break; |
1577 | 1.53k | case AArch64_Q24: |
1578 | 1.53k | Reg = AArch64_Q25; |
1579 | 1.53k | break; |
1580 | 1.37k | case AArch64_Q25: |
1581 | 1.37k | Reg = AArch64_Q26; |
1582 | 1.37k | break; |
1583 | 488 | case AArch64_Q26: |
1584 | 488 | Reg = AArch64_Q27; |
1585 | 488 | break; |
1586 | 3.93k | case AArch64_Q27: |
1587 | 3.93k | Reg = AArch64_Q28; |
1588 | 3.93k | break; |
1589 | 3.16k | case AArch64_Q28: |
1590 | 3.16k | Reg = AArch64_Q29; |
1591 | 3.16k | break; |
1592 | 1.62k | case AArch64_Q29: |
1593 | 1.62k | Reg = AArch64_Q30; |
1594 | 1.62k | break; |
1595 | 1.45k | case AArch64_Q30: |
1596 | 1.45k | Reg = AArch64_Q31; |
1597 | 1.45k | break; |
1598 | | // Vector lists can wrap around. |
1599 | 910 | case AArch64_Q31: |
1600 | 910 | Reg = AArch64_Q0; |
1601 | 910 | break; |
1602 | 11.9k | case AArch64_Z0: |
1603 | 11.9k | Reg = AArch64_Z1; |
1604 | 11.9k | break; |
1605 | 5.24k | case AArch64_Z1: |
1606 | 5.24k | Reg = AArch64_Z2; |
1607 | 5.24k | break; |
1608 | 5.29k | case AArch64_Z2: |
1609 | 5.29k | Reg = AArch64_Z3; |
1610 | 5.29k | break; |
1611 | 1.77k | case AArch64_Z3: |
1612 | 1.77k | Reg = AArch64_Z4; |
1613 | 1.77k | break; |
1614 | 9.72k | case AArch64_Z4: |
1615 | 9.72k | Reg = AArch64_Z5; |
1616 | 9.72k | break; |
1617 | 6.38k | case AArch64_Z5: |
1618 | 6.38k | Reg = AArch64_Z6; |
1619 | 6.38k | break; |
1620 | 10.6k | case AArch64_Z6: |
1621 | 10.6k | Reg = AArch64_Z7; |
1622 | 10.6k | break; |
1623 | 2.46k | case AArch64_Z7: |
1624 | 2.46k | Reg = AArch64_Z8; |
1625 | 2.46k | break; |
1626 | 7.32k | case AArch64_Z8: |
1627 | 7.32k | Reg = AArch64_Z9; |
1628 | 7.32k | break; |
1629 | 8.74k | case AArch64_Z9: |
1630 | 8.74k | Reg = AArch64_Z10; |
1631 | 8.74k | break; |
1632 | 7.32k | case AArch64_Z10: |
1633 | 7.32k | Reg = AArch64_Z11; |
1634 | 7.32k | break; |
1635 | 4.37k | case AArch64_Z11: |
1636 | 4.37k | Reg = AArch64_Z12; |
1637 | 4.37k | break; |
1638 | 3.33k | case AArch64_Z12: |
1639 | 3.33k | Reg = AArch64_Z13; |
1640 | 3.33k | break; |
1641 | 2.95k | case AArch64_Z13: |
1642 | 2.95k | Reg = AArch64_Z14; |
1643 | 2.95k | break; |
1644 | 7.45k | case AArch64_Z14: |
1645 | 7.45k | Reg = AArch64_Z15; |
1646 | 7.45k | break; |
1647 | 2.59k | case AArch64_Z15: |
1648 | 2.59k | Reg = AArch64_Z16; |
1649 | 2.59k | break; |
1650 | 4.74k | case AArch64_Z16: |
1651 | 4.74k | Reg = AArch64_Z17; |
1652 | 4.74k | break; |
1653 | 2.40k | case AArch64_Z17: |
1654 | 2.40k | Reg = AArch64_Z18; |
1655 | 2.40k | break; |
1656 | 2.77k | case AArch64_Z18: |
1657 | 2.77k | Reg = AArch64_Z19; |
1658 | 2.77k | break; |
1659 | 2.03k | case AArch64_Z19: |
1660 | 2.03k | Reg = AArch64_Z20; |
1661 | 2.03k | break; |
1662 | 3.60k | case AArch64_Z20: |
1663 | 3.60k | Reg = AArch64_Z21; |
1664 | 3.60k | break; |
1665 | 1.40k | case AArch64_Z21: |
1666 | 1.40k | Reg = AArch64_Z22; |
1667 | 1.40k | break; |
1668 | 1.38k | case AArch64_Z22: |
1669 | 1.38k | Reg = AArch64_Z23; |
1670 | 1.38k | break; |
1671 | 979 | case AArch64_Z23: |
1672 | 979 | Reg = AArch64_Z24; |
1673 | 979 | break; |
1674 | 2.30k | case AArch64_Z24: |
1675 | 2.30k | Reg = AArch64_Z25; |
1676 | 2.30k | break; |
1677 | 2.73k | case AArch64_Z25: |
1678 | 2.73k | Reg = AArch64_Z26; |
1679 | 2.73k | break; |
1680 | 2.58k | case AArch64_Z26: |
1681 | 2.58k | Reg = AArch64_Z27; |
1682 | 2.58k | break; |
1683 | 936 | case AArch64_Z27: |
1684 | 936 | Reg = AArch64_Z28; |
1685 | 936 | break; |
1686 | 1.16k | case AArch64_Z28: |
1687 | 1.16k | Reg = AArch64_Z29; |
1688 | 1.16k | break; |
1689 | 1.83k | case AArch64_Z29: |
1690 | 1.83k | Reg = AArch64_Z30; |
1691 | 1.83k | break; |
1692 | 2.82k | case AArch64_Z30: |
1693 | 2.82k | Reg = AArch64_Z31; |
1694 | 2.82k | break; |
1695 | | // Vector lists can wrap around. |
1696 | 1.78k | case AArch64_Z31: |
1697 | 1.78k | Reg = AArch64_Z0; |
1698 | 1.78k | break; |
1699 | 168 | case AArch64_P0: |
1700 | 168 | Reg = AArch64_P1; |
1701 | 168 | break; |
1702 | 2.52k | case AArch64_P1: |
1703 | 2.52k | Reg = AArch64_P2; |
1704 | 2.52k | break; |
1705 | 1.17k | case AArch64_P2: |
1706 | 1.17k | Reg = AArch64_P3; |
1707 | 1.17k | break; |
1708 | 20 | case AArch64_P3: |
1709 | 20 | Reg = AArch64_P4; |
1710 | 20 | break; |
1711 | 924 | case AArch64_P4: |
1712 | 924 | Reg = AArch64_P5; |
1713 | 924 | break; |
1714 | 24 | case AArch64_P5: |
1715 | 24 | Reg = AArch64_P6; |
1716 | 24 | break; |
1717 | 538 | case AArch64_P6: |
1718 | 538 | Reg = AArch64_P7; |
1719 | 538 | break; |
1720 | 22 | case AArch64_P7: |
1721 | 22 | Reg = AArch64_P8; |
1722 | 22 | break; |
1723 | 30 | case AArch64_P8: |
1724 | 30 | Reg = AArch64_P9; |
1725 | 30 | break; |
1726 | 72 | case AArch64_P9: |
1727 | 72 | Reg = AArch64_P10; |
1728 | 72 | break; |
1729 | 8 | case AArch64_P10: |
1730 | 8 | Reg = AArch64_P11; |
1731 | 8 | break; |
1732 | 22 | case AArch64_P11: |
1733 | 22 | Reg = AArch64_P12; |
1734 | 22 | break; |
1735 | 266 | case AArch64_P12: |
1736 | 266 | Reg = AArch64_P13; |
1737 | 266 | break; |
1738 | 78 | case AArch64_P13: |
1739 | 78 | Reg = AArch64_P14; |
1740 | 78 | break; |
1741 | 2.40k | case AArch64_P14: |
1742 | 2.40k | Reg = AArch64_P15; |
1743 | 2.40k | break; |
1744 | | // Vector lists can wrap around. |
1745 | 24 | case AArch64_P15: |
1746 | 24 | Reg = AArch64_P0; |
1747 | 24 | break; |
1748 | 202k | } |
1749 | 202k | } |
1750 | 134k | return Reg; |
1751 | 134k | } |
1752 | | |
1753 | | #define DEFINE_printGPRSeqPairsClassOperand(size) \ |
1754 | | void CONCAT(printGPRSeqPairsClassOperand, \ |
1755 | | size)(MCInst * MI, unsigned OpNum, SStream *O) \ |
1756 | 1.52k | { \ |
1757 | 1.52k | add_cs_detail(MI, \ |
1758 | 1.52k | CONCAT(AArch64_OP_GROUP_GPRSeqPairsClassOperand, \ |
1759 | 1.52k | size), \ |
1760 | 1.52k | OpNum, size); \ |
1761 | 1.52k | assert((size == 64 || size == 32) && \ |
1762 | 1.52k | "Template parameter must be either 32 or 64"); \ |
1763 | 1.52k | unsigned Reg = \ |
1764 | 1.52k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ |
1765 | 1.52k | \ |
1766 | 1.52k | unsigned Sube = (size == 32) ? AArch64_sube32 : \ |
1767 | 1.52k | AArch64_sube64; \ |
1768 | 1.52k | unsigned Subo = (size == 32) ? AArch64_subo32 : \ |
1769 | 1.52k | AArch64_subo64; \ |
1770 | 1.52k | \ |
1771 | 1.52k | unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); \ |
1772 | 1.52k | unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); \ |
1773 | 1.52k | printRegName(O, Even); \ |
1774 | 1.52k | SStream_concat0(O, ", "); \ |
1775 | 1.52k | printRegName(O, Odd); \ |
1776 | 1.52k | } printGPRSeqPairsClassOperand_32 Line | Count | Source | 1756 | 156 | { \ | 1757 | 156 | add_cs_detail(MI, \ | 1758 | 156 | CONCAT(AArch64_OP_GROUP_GPRSeqPairsClassOperand, \ | 1759 | 156 | size), \ | 1760 | 156 | OpNum, size); \ | 1761 | 156 | assert((size == 64 || size == 32) && \ | 1762 | 156 | "Template parameter must be either 32 or 64"); \ | 1763 | 156 | unsigned Reg = \ | 1764 | 156 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1765 | 156 | \ | 1766 | 156 | unsigned Sube = (size == 32) ? AArch64_sube32 : \ | 1767 | 156 | AArch64_sube64; \ | 1768 | 156 | unsigned Subo = (size == 32) ? AArch64_subo32 : \ | 1769 | 156 | AArch64_subo64; \ | 1770 | 156 | \ | 1771 | 156 | unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); \ | 1772 | 156 | unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); \ | 1773 | 156 | printRegName(O, Even); \ | 1774 | 156 | SStream_concat0(O, ", "); \ | 1775 | 156 | printRegName(O, Odd); \ | 1776 | 156 | } |
printGPRSeqPairsClassOperand_64 Line | Count | Source | 1756 | 1.37k | { \ | 1757 | 1.37k | add_cs_detail(MI, \ | 1758 | 1.37k | CONCAT(AArch64_OP_GROUP_GPRSeqPairsClassOperand, \ | 1759 | 1.37k | size), \ | 1760 | 1.37k | OpNum, size); \ | 1761 | 1.37k | assert((size == 64 || size == 32) && \ | 1762 | 1.37k | "Template parameter must be either 32 or 64"); \ | 1763 | 1.37k | unsigned Reg = \ | 1764 | 1.37k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 1765 | 1.37k | \ | 1766 | 1.37k | unsigned Sube = (size == 32) ? AArch64_sube32 : \ | 1767 | 1.37k | AArch64_sube64; \ | 1768 | 1.37k | unsigned Subo = (size == 32) ? AArch64_subo32 : \ | 1769 | 1.37k | AArch64_subo64; \ | 1770 | 1.37k | \ | 1771 | 1.37k | unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); \ | 1772 | 1.37k | unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); \ | 1773 | 1.37k | printRegName(O, Even); \ | 1774 | 1.37k | SStream_concat0(O, ", "); \ | 1775 | 1.37k | printRegName(O, Odd); \ | 1776 | 1.37k | } |
|
1777 | | DEFINE_printGPRSeqPairsClassOperand(32); |
1778 | | DEFINE_printGPRSeqPairsClassOperand(64); |
1779 | | |
1780 | | #define DEFINE_printMatrixIndex(Scale) \ |
1781 | | void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \ |
1782 | | SStream *O) \ |
1783 | 9.96k | { \ |
1784 | 9.96k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_MatrixIndex, Scale), \ |
1785 | 9.96k | OpNum, Scale); \ |
1786 | 9.96k | printInt64(O, Scale *MCOperand_getImm( \ |
1787 | 9.96k | MCInst_getOperand(MI, (OpNum)))); \ |
1788 | 9.96k | } Line | Count | Source | 1783 | 536 | { \ | 1784 | 536 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_MatrixIndex, Scale), \ | 1785 | 536 | OpNum, Scale); \ | 1786 | 536 | printInt64(O, Scale *MCOperand_getImm( \ | 1787 | 536 | MCInst_getOperand(MI, (OpNum)))); \ | 1788 | 536 | } |
Unexecuted instantiation: printMatrixIndex_0 Line | Count | Source | 1783 | 9.43k | { \ | 1784 | 9.43k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_MatrixIndex, Scale), \ | 1785 | 9.43k | OpNum, Scale); \ | 1786 | 9.43k | printInt64(O, Scale *MCOperand_getImm( \ | 1787 | 9.43k | MCInst_getOperand(MI, (OpNum)))); \ | 1788 | 9.43k | } |
|
1789 | | DEFINE_printMatrixIndex(8); |
1790 | | DEFINE_printMatrixIndex(0); |
1791 | | DEFINE_printMatrixIndex(1); |
1792 | | |
1793 | | void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O) |
1794 | 409 | { |
1795 | 409 | add_cs_detail(MI, AArch64_OP_GROUP_MatrixTileList, OpNum); |
1796 | 409 | unsigned MaxRegs = 8; |
1797 | 409 | unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
1798 | | |
1799 | 409 | unsigned NumRegs = 0; |
1800 | 3.68k | for (unsigned I = 0; I < MaxRegs; ++I) |
1801 | 3.27k | if ((RegMask & (1 << I)) != 0) |
1802 | 1.37k | ++NumRegs; |
1803 | | |
1804 | 409 | SStream_concat0(O, "{"); |
1805 | 409 | unsigned Printed = 0; |
1806 | 3.68k | for (unsigned I = 0; I < MaxRegs; ++I) { |
1807 | 3.27k | unsigned Reg = RegMask & (1 << I); |
1808 | 3.27k | if (Reg == 0) |
1809 | 1.90k | continue; |
1810 | 1.37k | printRegName(O, AArch64_ZAD0 + I); |
1811 | 1.37k | if (Printed + 1 != NumRegs) |
1812 | 965 | SStream_concat0(O, ", "); |
1813 | 1.37k | ++Printed; |
1814 | 1.37k | } |
1815 | 409 | SStream_concat0(O, "}"); |
1816 | 409 | } |
1817 | | |
1818 | | void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, |
1819 | | const char *LayoutSuffix) |
1820 | 63.2k | { |
1821 | 63.2k | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); |
1822 | | |
1823 | 63.2k | SStream_concat0(O, "{ "); |
1824 | | |
1825 | | // Work out how many registers there are in the list (if there is an actual |
1826 | | // list). |
1827 | 63.2k | unsigned NumRegs = 1; |
1828 | 63.2k | if (MCRegisterClass_contains( |
1829 | 63.2k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_DDRegClassID), |
1830 | 63.2k | Reg) || |
1831 | 63.2k | MCRegisterClass_contains( |
1832 | 62.3k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR2RegClassID), |
1833 | 62.3k | Reg) || |
1834 | 63.2k | MCRegisterClass_contains( |
1835 | 46.9k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_QQRegClassID), |
1836 | 46.9k | Reg) || |
1837 | 63.2k | MCRegisterClass_contains( |
1838 | 41.5k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_PPR2RegClassID), |
1839 | 41.5k | Reg) || |
1840 | 63.2k | MCRegisterClass_contains( |
1841 | 37.3k | MCRegisterInfo_getRegClass(MI->MRI, |
1842 | 37.3k | AArch64_ZPR2StridedRegClassID), |
1843 | 37.3k | Reg)) |
1844 | 28.0k | NumRegs = 2; |
1845 | 35.1k | else if (MCRegisterClass_contains( |
1846 | 35.1k | MCRegisterInfo_getRegClass(MI->MRI, |
1847 | 35.1k | AArch64_DDDRegClassID), |
1848 | 35.1k | Reg) || |
1849 | 35.1k | MCRegisterClass_contains( |
1850 | 34.7k | MCRegisterInfo_getRegClass(MI->MRI, |
1851 | 34.7k | AArch64_ZPR3RegClassID), |
1852 | 34.7k | Reg) || |
1853 | 35.1k | MCRegisterClass_contains( |
1854 | 33.8k | MCRegisterInfo_getRegClass(MI->MRI, |
1855 | 33.8k | AArch64_QQQRegClassID), |
1856 | 33.8k | Reg)) |
1857 | 5.50k | NumRegs = 3; |
1858 | 29.6k | else if (MCRegisterClass_contains( |
1859 | 29.6k | MCRegisterInfo_getRegClass(MI->MRI, |
1860 | 29.6k | AArch64_DDDDRegClassID), |
1861 | 29.6k | Reg) || |
1862 | 29.6k | MCRegisterClass_contains( |
1863 | 28.8k | MCRegisterInfo_getRegClass(MI->MRI, |
1864 | 28.8k | AArch64_ZPR4RegClassID), |
1865 | 28.8k | Reg) || |
1866 | 29.6k | MCRegisterClass_contains( |
1867 | 21.4k | MCRegisterInfo_getRegClass(MI->MRI, |
1868 | 21.4k | AArch64_QQQQRegClassID), |
1869 | 21.4k | Reg) || |
1870 | 29.6k | MCRegisterClass_contains( |
1871 | 14.6k | MCRegisterInfo_getRegClass( |
1872 | 14.6k | MI->MRI, AArch64_ZPR4StridedRegClassID), |
1873 | 14.6k | Reg)) |
1874 | 15.5k | NumRegs = 4; |
1875 | | |
1876 | 63.2k | unsigned Stride = 1; |
1877 | 63.2k | if (MCRegisterClass_contains( |
1878 | 63.2k | MCRegisterInfo_getRegClass(MI->MRI, |
1879 | 63.2k | AArch64_ZPR2StridedRegClassID), |
1880 | 63.2k | Reg)) |
1881 | 2.22k | Stride = 8; |
1882 | 60.9k | else if (MCRegisterClass_contains( |
1883 | 60.9k | MCRegisterInfo_getRegClass( |
1884 | 60.9k | MI->MRI, AArch64_ZPR4StridedRegClassID), |
1885 | 60.9k | Reg)) |
1886 | 555 | Stride = 4; |
1887 | | |
1888 | | // Now forget about the list and find out what the first register is. |
1889 | 63.2k | if (MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_dsub0)) |
1890 | 2.02k | Reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_dsub0); |
1891 | 61.1k | else if (MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_qsub0)) |
1892 | 16.4k | Reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_qsub0); |
1893 | 44.7k | else if (MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_zsub0)) |
1894 | 26.5k | Reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_zsub0); |
1895 | 18.2k | else if (MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_psub0)) |
1896 | 4.13k | Reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_psub0); |
1897 | | |
1898 | | // If it's a D-reg, we need to promote it to the equivalent Q-reg before |
1899 | | // printing (otherwise getRegisterName fails). |
1900 | 63.2k | if (MCRegisterClass_contains(MCRegisterInfo_getRegClass( |
1901 | 63.2k | MI->MRI, AArch64_FPR64RegClassID), |
1902 | 63.2k | Reg)) { |
1903 | 2.15k | const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass( |
1904 | 2.15k | MI->MRI, AArch64_FPR128RegClassID); |
1905 | 2.15k | Reg = MCRegisterInfo_getMatchingSuperReg( |
1906 | 2.15k | MI->MRI, Reg, AArch64_dsub, FPR128RC); |
1907 | 2.15k | } |
1908 | | |
1909 | 63.2k | if ((MCRegisterClass_contains( |
1910 | 63.2k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPRRegClassID), |
1911 | 63.2k | Reg) || |
1912 | 63.2k | MCRegisterClass_contains( |
1913 | 27.5k | MCRegisterInfo_getRegClass(MI->MRI, AArch64_PPRRegClassID), |
1914 | 27.5k | Reg)) && |
1915 | 63.2k | NumRegs > 1 && Stride == 1 && |
1916 | | // Do not print the range when the last register is lower than the |
1917 | | // first. Because it is a wrap-around register. |
1918 | 63.2k | Reg < getNextVectorRegister(Reg, NumRegs - 1)) { |
1919 | 27.4k | printRegName(O, Reg); |
1920 | 27.4k | SStream_concat0(O, LayoutSuffix); |
1921 | 27.4k | if (NumRegs > 1) { |
1922 | | // Set of two sve registers should be separated by ',' |
1923 | 27.4k | const char *split_char = NumRegs == 2 ? ", " : " - "; |
1924 | 27.4k | SStream_concat0(O, split_char); |
1925 | 27.4k | printRegName(O, |
1926 | 27.4k | (getNextVectorRegister(Reg, NumRegs - 1))); |
1927 | 27.4k | SStream_concat0(O, LayoutSuffix); |
1928 | 27.4k | } |
1929 | 35.7k | } else { |
1930 | 114k | for (unsigned i = 0; i < NumRegs; |
1931 | 78.8k | ++i, Reg = getNextVectorRegister(Reg, Stride)) { |
1932 | | // wrap-around sve register |
1933 | 78.8k | if (MCRegisterClass_contains( |
1934 | 78.8k | MCRegisterInfo_getRegClass( |
1935 | 78.8k | MI->MRI, AArch64_ZPRRegClassID), |
1936 | 78.8k | Reg) || |
1937 | 78.8k | MCRegisterClass_contains( |
1938 | 61.5k | MCRegisterInfo_getRegClass( |
1939 | 61.5k | MI->MRI, AArch64_PPRRegClassID), |
1940 | 61.5k | Reg)) |
1941 | 17.2k | printRegName(O, Reg); |
1942 | 61.5k | else |
1943 | 61.5k | printRegNameAlt(O, Reg, AArch64_vreg); |
1944 | 78.8k | SStream_concat0(O, LayoutSuffix); |
1945 | 78.8k | if (i + 1 != NumRegs) |
1946 | 43.1k | SStream_concat0(O, ", "); |
1947 | 78.8k | } |
1948 | 35.7k | } |
1949 | 63.2k | SStream_concat0(O, " }"); |
1950 | 63.2k | } |
1951 | | |
1952 | | void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O) |
1953 | 0 | { |
1954 | 0 | add_cs_detail(MI, AArch64_OP_GROUP_ImplicitlyTypedVectorList, OpNum); |
1955 | 0 | printVectorList(MI, OpNum, O, ""); |
1956 | 0 | } |
1957 | | |
1958 | | #define DEFINE_printTypedVectorList(NumLanes, LaneKind) \ |
1959 | | void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \ |
1960 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
1961 | 63.2k | { \ |
1962 | 63.2k | add_cs_detail(MI, \ |
1963 | 63.2k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ |
1964 | 63.2k | NumLanes), \ |
1965 | 63.2k | LaneKind), \ |
1966 | 63.2k | OpNum, NumLanes, CHAR(LaneKind)); \ |
1967 | 63.2k | if (CHAR(LaneKind) == 0) { \ |
1968 | 0 | printVectorList(MI, OpNum, O, ""); \ |
1969 | 0 | return; \ |
1970 | 0 | } \ |
1971 | 63.2k | char Suffix[32]; \ |
1972 | 63.2k | if (NumLanes) \ |
1973 | 63.2k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ |
1974 | 5.08k | CHAR(LaneKind)); \ |
1975 | 63.2k | else \ |
1976 | 63.2k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ |
1977 | 58.1k | CHAR(LaneKind)); \ |
1978 | 63.2k | \ |
1979 | 63.2k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ |
1980 | 63.2k | } Line | Count | Source | 1961 | 9.80k | { \ | 1962 | 9.80k | add_cs_detail(MI, \ | 1963 | 9.80k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 9.80k | NumLanes), \ | 1965 | 9.80k | LaneKind), \ | 1966 | 9.80k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 9.80k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 9.80k | char Suffix[32]; \ | 1972 | 9.80k | if (NumLanes) \ | 1973 | 9.80k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 9.80k | else \ | 1976 | 9.80k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 9.80k | CHAR(LaneKind)); \ | 1978 | 9.80k | \ | 1979 | 9.80k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 9.80k | } |
Line | Count | Source | 1961 | 17.6k | { \ | 1962 | 17.6k | add_cs_detail(MI, \ | 1963 | 17.6k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 17.6k | NumLanes), \ | 1965 | 17.6k | LaneKind), \ | 1966 | 17.6k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 17.6k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 17.6k | char Suffix[32]; \ | 1972 | 17.6k | if (NumLanes) \ | 1973 | 17.6k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 17.6k | else \ | 1976 | 17.6k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 17.6k | CHAR(LaneKind)); \ | 1978 | 17.6k | \ | 1979 | 17.6k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 17.6k | } |
Line | Count | Source | 1961 | 14.0k | { \ | 1962 | 14.0k | add_cs_detail(MI, \ | 1963 | 14.0k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 14.0k | NumLanes), \ | 1965 | 14.0k | LaneKind), \ | 1966 | 14.0k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 14.0k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 14.0k | char Suffix[32]; \ | 1972 | 14.0k | if (NumLanes) \ | 1973 | 14.0k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 14.0k | else \ | 1976 | 14.0k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 14.0k | CHAR(LaneKind)); \ | 1978 | 14.0k | \ | 1979 | 14.0k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 14.0k | } |
Line | Count | Source | 1961 | 14.5k | { \ | 1962 | 14.5k | add_cs_detail(MI, \ | 1963 | 14.5k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 14.5k | NumLanes), \ | 1965 | 14.5k | LaneKind), \ | 1966 | 14.5k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 14.5k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 14.5k | char Suffix[32]; \ | 1972 | 14.5k | if (NumLanes) \ | 1973 | 14.5k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 14.5k | else \ | 1976 | 14.5k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 14.5k | CHAR(LaneKind)); \ | 1978 | 14.5k | \ | 1979 | 14.5k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 14.5k | } |
Line | Count | Source | 1961 | 1.97k | { \ | 1962 | 1.97k | add_cs_detail(MI, \ | 1963 | 1.97k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 1.97k | NumLanes), \ | 1965 | 1.97k | LaneKind), \ | 1966 | 1.97k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 1.97k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 1.97k | char Suffix[32]; \ | 1972 | 1.97k | if (NumLanes) \ | 1973 | 1.97k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 1.97k | else \ | 1976 | 1.97k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 1.97k | CHAR(LaneKind)); \ | 1978 | 1.97k | \ | 1979 | 1.97k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 1.97k | } |
printTypedVectorList_16_b Line | Count | Source | 1961 | 1.35k | { \ | 1962 | 1.35k | add_cs_detail(MI, \ | 1963 | 1.35k | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 1.35k | NumLanes), \ | 1965 | 1.35k | LaneKind), \ | 1966 | 1.35k | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 1.35k | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 1.35k | char Suffix[32]; \ | 1972 | 1.35k | if (NumLanes) \ | 1973 | 1.35k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 1.35k | CHAR(LaneKind)); \ | 1975 | 1.35k | else \ | 1976 | 1.35k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 1.35k | \ | 1979 | 1.35k | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 1.35k | } |
Line | Count | Source | 1961 | 126 | { \ | 1962 | 126 | add_cs_detail(MI, \ | 1963 | 126 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 126 | NumLanes), \ | 1965 | 126 | LaneKind), \ | 1966 | 126 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 126 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 126 | char Suffix[32]; \ | 1972 | 126 | if (NumLanes) \ | 1973 | 126 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 126 | CHAR(LaneKind)); \ | 1975 | 126 | else \ | 1976 | 126 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 126 | \ | 1979 | 126 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 126 | } |
Line | Count | Source | 1961 | 555 | { \ | 1962 | 555 | add_cs_detail(MI, \ | 1963 | 555 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 555 | NumLanes), \ | 1965 | 555 | LaneKind), \ | 1966 | 555 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 555 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 555 | char Suffix[32]; \ | 1972 | 555 | if (NumLanes) \ | 1973 | 555 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 555 | CHAR(LaneKind)); \ | 1975 | 555 | else \ | 1976 | 555 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 555 | \ | 1979 | 555 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 555 | } |
Line | Count | Source | 1961 | 673 | { \ | 1962 | 673 | add_cs_detail(MI, \ | 1963 | 673 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 673 | NumLanes), \ | 1965 | 673 | LaneKind), \ | 1966 | 673 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 673 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 673 | char Suffix[32]; \ | 1972 | 673 | if (NumLanes) \ | 1973 | 673 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 673 | CHAR(LaneKind)); \ | 1975 | 673 | else \ | 1976 | 673 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 673 | \ | 1979 | 673 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 673 | } |
Line | Count | Source | 1961 | 392 | { \ | 1962 | 392 | add_cs_detail(MI, \ | 1963 | 392 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 392 | NumLanes), \ | 1965 | 392 | LaneKind), \ | 1966 | 392 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 392 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 392 | char Suffix[32]; \ | 1972 | 392 | if (NumLanes) \ | 1973 | 392 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 392 | CHAR(LaneKind)); \ | 1975 | 392 | else \ | 1976 | 392 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 392 | \ | 1979 | 392 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 392 | } |
Line | Count | Source | 1961 | 277 | { \ | 1962 | 277 | add_cs_detail(MI, \ | 1963 | 277 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 277 | NumLanes), \ | 1965 | 277 | LaneKind), \ | 1966 | 277 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 277 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 277 | char Suffix[32]; \ | 1972 | 277 | if (NumLanes) \ | 1973 | 277 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 277 | CHAR(LaneKind)); \ | 1975 | 277 | else \ | 1976 | 277 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 277 | \ | 1979 | 277 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 277 | } |
Line | Count | Source | 1961 | 964 | { \ | 1962 | 964 | add_cs_detail(MI, \ | 1963 | 964 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 964 | NumLanes), \ | 1965 | 964 | LaneKind), \ | 1966 | 964 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 964 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 964 | char Suffix[32]; \ | 1972 | 964 | if (NumLanes) \ | 1973 | 964 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 964 | CHAR(LaneKind)); \ | 1975 | 964 | else \ | 1976 | 964 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 964 | \ | 1979 | 964 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 964 | } |
Line | Count | Source | 1961 | 745 | { \ | 1962 | 745 | add_cs_detail(MI, \ | 1963 | 745 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 745 | NumLanes), \ | 1965 | 745 | LaneKind), \ | 1966 | 745 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 745 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 745 | char Suffix[32]; \ | 1972 | 745 | if (NumLanes) \ | 1973 | 745 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 745 | CHAR(LaneKind)); \ | 1975 | 745 | else \ | 1976 | 745 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 0 | CHAR(LaneKind)); \ | 1978 | 745 | \ | 1979 | 745 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 745 | } |
Line | Count | Source | 1961 | 122 | { \ | 1962 | 122 | add_cs_detail(MI, \ | 1963 | 122 | CONCAT(CONCAT(AArch64_OP_GROUP_TypedVectorList, \ | 1964 | 122 | NumLanes), \ | 1965 | 122 | LaneKind), \ | 1966 | 122 | OpNum, NumLanes, CHAR(LaneKind)); \ | 1967 | 122 | if (CHAR(LaneKind) == 0) { \ | 1968 | 0 | printVectorList(MI, OpNum, O, ""); \ | 1969 | 0 | return; \ | 1970 | 0 | } \ | 1971 | 122 | char Suffix[32]; \ | 1972 | 122 | if (NumLanes) \ | 1973 | 122 | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, \ | 1974 | 0 | CHAR(LaneKind)); \ | 1975 | 122 | else \ | 1976 | 122 | cs_snprintf(Suffix, sizeof(Suffix), ".%c", \ | 1977 | 122 | CHAR(LaneKind)); \ | 1978 | 122 | \ | 1979 | 122 | printVectorList(MI, OpNum, O, ((const char *)&Suffix)); \ | 1980 | 122 | } |
|
1981 | | DEFINE_printTypedVectorList(0, b); |
1982 | | DEFINE_printTypedVectorList(0, d); |
1983 | | DEFINE_printTypedVectorList(0, h); |
1984 | | DEFINE_printTypedVectorList(0, s); |
1985 | | DEFINE_printTypedVectorList(0, q); |
1986 | | DEFINE_printTypedVectorList(16, b); |
1987 | | DEFINE_printTypedVectorList(1, d); |
1988 | | DEFINE_printTypedVectorList(2, d); |
1989 | | DEFINE_printTypedVectorList(2, s); |
1990 | | DEFINE_printTypedVectorList(4, h); |
1991 | | DEFINE_printTypedVectorList(4, s); |
1992 | | DEFINE_printTypedVectorList(8, b); |
1993 | | DEFINE_printTypedVectorList(8, h); |
1994 | | DEFINE_printTypedVectorList(0, 0); |
1995 | | |
1996 | | #define DEFINE_printVectorIndex(Scale) \ |
1997 | | void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \ |
1998 | | SStream *O) \ |
1999 | 39.0k | { \ |
2000 | 39.0k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_VectorIndex, Scale), \ |
2001 | 39.0k | OpNum, Scale); \ |
2002 | 39.0k | SStream_concat(O, "%s", "["); \ |
2003 | 39.0k | printUInt64(O, Scale *MCOperand_getImm( \ |
2004 | 39.0k | MCInst_getOperand(MI, (OpNum)))); \ |
2005 | 39.0k | SStream_concat0(O, "]"); \ |
2006 | 39.0k | } Line | Count | Source | 1999 | 39.0k | { \ | 2000 | 39.0k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_VectorIndex, Scale), \ | 2001 | 39.0k | OpNum, Scale); \ | 2002 | 39.0k | SStream_concat(O, "%s", "["); \ | 2003 | 39.0k | printUInt64(O, Scale *MCOperand_getImm( \ | 2004 | 39.0k | MCInst_getOperand(MI, (OpNum)))); \ | 2005 | 39.0k | SStream_concat0(O, "]"); \ | 2006 | 39.0k | } |
Unexecuted instantiation: printVectorIndex_8 |
2007 | | DEFINE_printVectorIndex(1); |
2008 | | DEFINE_printVectorIndex(8); |
2009 | | |
2010 | | void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) |
2011 | 17.3k | { |
2012 | 17.3k | add_cs_detail(MI, AArch64_OP_GROUP_AlignedLabel, OpNum); |
2013 | 17.3k | MCOperand *Op = MCInst_getOperand(MI, (OpNum)); |
2014 | | |
2015 | | // If the label has already been resolved to an immediate offset (say, when |
2016 | | // we're running the disassembler), just print the immediate. |
2017 | 17.3k | if (MCOperand_isImm(Op)) { |
2018 | 17.3k | SStream_concat0(O, markup("<imm:")); |
2019 | 17.3k | int64_t Offset = MCOperand_getImm(Op) * 4; |
2020 | 17.3k | if (!MI->csh->PrintBranchImmNotAsAddress) |
2021 | 17.3k | printUInt64(O, (Address + Offset)); |
2022 | 0 | else { |
2023 | 0 | printUInt64Bang(O, (Offset)); |
2024 | 0 | } |
2025 | 17.3k | SStream_concat0(O, markup(">")); |
2026 | 17.3k | return; |
2027 | 17.3k | } |
2028 | | |
2029 | 31 | SStream_concat0(O, "<llvm-expr>"); |
2030 | 31 | } |
2031 | | |
2032 | | void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) |
2033 | 0 | { |
2034 | 0 | add_cs_detail(MI, AArch64_OP_GROUP_AdrLabel, OpNum); |
2035 | 0 | MCOperand *Op = MCInst_getOperand(MI, (OpNum)); |
2036 | | |
2037 | | // If the label has already been resolved to an immediate offset (say, when |
2038 | | // we're running the disassembler), just print the immediate. |
2039 | 0 | if (MCOperand_isImm(Op)) { |
2040 | 0 | const int64_t Offset = MCOperand_getImm(Op); |
2041 | 0 | SStream_concat0(O, markup("<imm:")); |
2042 | 0 | if (!MI->csh->PrintBranchImmNotAsAddress) |
2043 | 0 | printUInt64(O, ((Address & -4) + Offset)); |
2044 | 0 | else { |
2045 | 0 | printUInt64Bang(O, Offset); |
2046 | 0 | } |
2047 | 0 | SStream_concat0(O, markup(">")); |
2048 | 0 | return; |
2049 | 0 | } |
2050 | | |
2051 | 0 | SStream_concat0(O, "<llvm-expr>"); |
2052 | 0 | } |
2053 | | |
2054 | | void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) |
2055 | 0 | { |
2056 | 0 | add_cs_detail(MI, AArch64_OP_GROUP_AdrpLabel, OpNum); |
2057 | 0 | MCOperand *Op = MCInst_getOperand(MI, (OpNum)); |
2058 | | |
2059 | | // If the label has already been resolved to an immediate offset (say, when |
2060 | | // we're running the disassembler), just print the immediate. |
2061 | 0 | if (MCOperand_isImm(Op)) { |
2062 | 0 | const int64_t Offset = MCOperand_getImm(Op) * 4096; |
2063 | 0 | SStream_concat0(O, markup("<imm:")); |
2064 | 0 | if (!MI->csh->PrintBranchImmNotAsAddress) |
2065 | 0 | printUInt64(O, ((Address & -4096) + Offset)); |
2066 | 0 | else { |
2067 | 0 | printUInt64Bang(O, Offset); |
2068 | 0 | } |
2069 | 0 | SStream_concat0(O, markup(">")); |
2070 | 0 | return; |
2071 | 0 | } |
2072 | | |
2073 | 0 | SStream_concat0(O, "<llvm-expr>"); |
2074 | 0 | } |
2075 | | |
2076 | 7.58k | void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) { |
2077 | 7.58k | add_cs_detail(MI, AArch64_OP_GROUP_AdrAdrpLabel, OpNum); |
2078 | 7.58k | MCOperand *Op = MCInst_getOperand(MI, (OpNum)); |
2079 | | |
2080 | | // If the label has already been resolved to an immediate offset (say, when |
2081 | | // we're running the disassembler), just print the immediate. |
2082 | 7.58k | if (MCOperand_isImm(Op)) { |
2083 | 7.58k | int64_t Offset = MCOperand_getImm(Op); |
2084 | 7.58k | if (MCInst_getOpcode(MI) == AArch64_ADRP) { |
2085 | 2.84k | Offset = Offset * 4096; |
2086 | 2.84k | Address = Address & -4096; |
2087 | 2.84k | } |
2088 | 7.58k | SStream_concat0(O, markup(">")); |
2089 | 7.58k | if (!MI->csh->PrintBranchImmNotAsAddress) |
2090 | 7.58k | printUInt64(O, (Address + Offset)); |
2091 | 0 | else { |
2092 | 0 | printUInt64Bang(O, Offset); |
2093 | 0 | } |
2094 | 7.58k | SStream_concat0(O, markup(">")); |
2095 | 7.58k | return; |
2096 | 7.58k | } |
2097 | | |
2098 | 0 | SStream_concat0(O, "<llvm-expr>"); |
2099 | 0 | } |
2100 | | |
2101 | | void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O) |
2102 | 63 | { |
2103 | 63 | add_cs_detail(MI, AArch64_OP_GROUP_BarrierOption, OpNo); |
2104 | 63 | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2105 | 63 | unsigned Opcode = MCInst_getOpcode(MI); |
2106 | | |
2107 | 63 | const char *Name; |
2108 | 63 | if (Opcode == AArch64_ISB) { |
2109 | 30 | const AArch64ISB_ISB *ISB = AArch64ISB_lookupISBByEncoding(Val); |
2110 | 30 | Name = ISB ? ISB->Name : ""; |
2111 | 33 | } else if (Opcode == AArch64_TSB) { |
2112 | 10 | const AArch64TSB_TSB *TSB = AArch64TSB_lookupTSBByEncoding(Val); |
2113 | 10 | Name = TSB ? TSB->Name : ""; |
2114 | 23 | } else { |
2115 | 23 | const AArch64DB_DB *DB = AArch64DB_lookupDBByEncoding(Val); |
2116 | 23 | Name = DB ? DB->Name : ""; |
2117 | 23 | } |
2118 | 63 | if (Name[0] != '\0') |
2119 | 23 | SStream_concat0(O, Name); |
2120 | 40 | else { |
2121 | 40 | SStream_concat(O, "%s", markup("<imm:")); |
2122 | 40 | printUInt32Bang(O, Val); |
2123 | 40 | SStream_concat0(O, markup(">")); |
2124 | 40 | } |
2125 | 63 | } |
2126 | | |
2127 | | void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) |
2128 | 1.16k | { |
2129 | 1.16k | add_cs_detail(MI, AArch64_OP_GROUP_BarriernXSOption, OpNo); |
2130 | 1.16k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2131 | | |
2132 | 1.16k | const char *Name; |
2133 | 1.16k | const AArch64DBnXS_DBnXS *DB = AArch64DBnXS_lookupDBnXSByEncoding(Val); |
2134 | 1.16k | Name = DB ? DB->Name : ""; |
2135 | | |
2136 | 1.16k | if (Name[0] != '\0') |
2137 | 1.16k | SStream_concat0(O, Name); |
2138 | 0 | else { |
2139 | 0 | SStream_concat(O, "%s%s%s", markup("<imm:"), "#", Val); |
2140 | 0 | SStream_concat0(O, markup(">")); |
2141 | 0 | } |
2142 | 1.16k | } |
2143 | | |
2144 | | static bool isValidSysReg(const AArch64SysReg_SysReg *Reg, bool Read, |
2145 | | unsigned mode) |
2146 | 4.54k | { |
2147 | 4.54k | return (Reg && (Read ? Reg->Readable : Reg->Writeable) && |
2148 | 4.54k | AArch64_testFeatureList(mode, Reg->FeaturesRequired)); |
2149 | 4.54k | } |
2150 | | |
2151 | | // Looks up a system register either by encoding or by name. Some system |
2152 | | // registers share the same encoding between different architectures, |
2153 | | // therefore a tablegen lookup by encoding will return an entry regardless |
2154 | | // of the register's predication on a specific subtarget feature. To work |
2155 | | // around this problem we keep an alternative name for such registers and |
2156 | | // look them up by that name if the first lookup was unsuccessful. |
2157 | | static const AArch64SysReg_SysReg *lookupSysReg(unsigned Val, bool Read, |
2158 | | unsigned mode) |
2159 | 4.29k | { |
2160 | 4.29k | const AArch64SysReg_SysReg *Reg = |
2161 | 4.29k | AArch64SysReg_lookupSysRegByEncoding(Val); |
2162 | | |
2163 | 4.29k | if (Reg && !isValidSysReg(Reg, Read, mode)) |
2164 | 150 | Reg = AArch64SysReg_lookupSysRegByName(Reg->AltName); |
2165 | | |
2166 | 4.29k | return Reg; |
2167 | 4.29k | } |
2168 | | |
2169 | | void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) |
2170 | 726 | { |
2171 | 726 | add_cs_detail(MI, AArch64_OP_GROUP_MRSSystemRegister, OpNo); |
2172 | 726 | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2173 | | |
2174 | | // Horrible hack for the one register that has identical encodings but |
2175 | | // different names in MSR and MRS. Because of this, one of MRS and MSR is |
2176 | | // going to get the wrong entry |
2177 | 726 | if (Val == AARCH64_SYSREG_DBGDTRRX_EL0) { |
2178 | 10 | SStream_concat0(O, "DBGDTRRX_EL0"); |
2179 | 10 | return; |
2180 | 10 | } |
2181 | | |
2182 | | // Horrible hack for two different registers having the same encoding. |
2183 | 716 | if (Val == AARCH64_SYSREG_TRCEXTINSELR) { |
2184 | 12 | SStream_concat0(O, "TRCEXTINSELR"); |
2185 | 12 | return; |
2186 | 12 | } |
2187 | | |
2188 | 704 | const AArch64SysReg_SysReg *Reg = |
2189 | 704 | lookupSysReg(Val, true /*Read*/, MI->csh->mode); |
2190 | | |
2191 | 704 | if (isValidSysReg(Reg, true /*Read*/, MI->csh->mode)) |
2192 | 17 | SStream_concat0(O, Reg->Name); |
2193 | 687 | else { |
2194 | 687 | char result[AARCH64_GRS_LEN + 1] = { 0 }; |
2195 | 687 | AArch64SysReg_genericRegisterString(Val, result); |
2196 | 687 | SStream_concat0(O, result); |
2197 | 687 | } |
2198 | 704 | } |
2199 | | |
2200 | | void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) |
2201 | 3.86k | { |
2202 | 3.86k | add_cs_detail(MI, AArch64_OP_GROUP_MSRSystemRegister, OpNo); |
2203 | 3.86k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2204 | | |
2205 | | // Horrible hack for the one register that has identical encodings but |
2206 | | // different names in MSR and MRS. Because of this, one of MRS and MSR is |
2207 | | // going to get the wrong entry |
2208 | 3.86k | if (Val == AARCH64_SYSREG_DBGDTRTX_EL0) { |
2209 | 78 | SStream_concat0(O, "DBGDTRTX_EL0"); |
2210 | 78 | return; |
2211 | 78 | } |
2212 | | |
2213 | | // Horrible hack for two different registers having the same encoding. |
2214 | 3.78k | if (Val == AARCH64_SYSREG_TRCEXTINSELR) { |
2215 | 196 | SStream_concat0(O, "TRCEXTINSELR"); |
2216 | 196 | return; |
2217 | 196 | } |
2218 | | |
2219 | 3.58k | const AArch64SysReg_SysReg *Reg = |
2220 | 3.58k | lookupSysReg(Val, false /*Read*/, MI->csh->mode); |
2221 | | |
2222 | 3.58k | if (isValidSysReg(Reg, false /*Read*/, MI->csh->mode)) |
2223 | 88 | SStream_concat0(O, Reg->Name); |
2224 | 3.50k | else { |
2225 | 3.50k | char result[AARCH64_GRS_LEN + 1] = { 0 }; |
2226 | 3.50k | AArch64SysReg_genericRegisterString(Val, result); |
2227 | 3.50k | SStream_concat0(O, result); |
2228 | 3.50k | } |
2229 | 3.58k | } |
2230 | | |
2231 | | void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O) |
2232 | 1.05k | { |
2233 | 1.05k | add_cs_detail(MI, AArch64_OP_GROUP_SystemPStateField, OpNo); |
2234 | 1.05k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2235 | | |
2236 | 1.05k | const AArch64PState_PStateImm0_15 *PStateImm15 = |
2237 | 1.05k | AArch64PState_lookupPStateImm0_15ByEncoding(Val); |
2238 | 1.05k | const AArch64PState_PStateImm0_1 *PStateImm1 = |
2239 | 1.05k | AArch64PState_lookupPStateImm0_1ByEncoding(Val); |
2240 | 1.05k | if (PStateImm15 && |
2241 | 1.05k | AArch64_testFeatureList(MI->csh->mode, |
2242 | 811 | PStateImm15->FeaturesRequired)) |
2243 | 811 | SStream_concat0(O, PStateImm15->Name); |
2244 | 247 | else if (PStateImm1 && |
2245 | 247 | AArch64_testFeatureList(MI->csh->mode, |
2246 | 247 | PStateImm1->FeaturesRequired)) |
2247 | 247 | SStream_concat0(O, PStateImm1->Name); |
2248 | 0 | else { |
2249 | 0 | printUInt32Bang(O, (Val)); |
2250 | 0 | SStream_concat1(O, '\0'); |
2251 | 0 | } |
2252 | 1.05k | } |
2253 | | |
2254 | | void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O) |
2255 | 252 | { |
2256 | 252 | add_cs_detail(MI, AArch64_OP_GROUP_SIMDType10Operand, OpNo); |
2257 | 252 | unsigned RawVal = MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); |
2258 | 252 | uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); |
2259 | 252 | SStream_concat(O, "%s#%#016llx", markup("<imm:"), Val); |
2260 | 252 | SStream_concat0(O, markup(">")); |
2261 | 252 | } |
2262 | | |
2263 | | #define DEFINE_printComplexRotationOp(Angle, Remainder) \ |
2264 | | static void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \ |
2265 | | MCInst * MI, unsigned OpNo, SStream *O) \ |
2266 | 2.31k | { \ |
2267 | 2.31k | add_cs_detail( \ |
2268 | 2.31k | MI, \ |
2269 | 2.31k | CONCAT(CONCAT(AArch64_OP_GROUP_ComplexRotationOp, \ |
2270 | 2.31k | Angle), \ |
2271 | 2.31k | Remainder), \ |
2272 | 2.31k | OpNo, Angle, Remainder); \ |
2273 | 2.31k | unsigned Val = \ |
2274 | 2.31k | MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ |
2275 | 2.31k | SStream_concat(O, "%s", markup("<imm:")); \ |
2276 | 2.31k | SStream_concat(O, "#%d", (Val * Angle) + Remainder); \ |
2277 | 2.31k | SStream_concat0(O, markup(">")); \ |
2278 | 2.31k | } AArch64InstPrinter.c:printComplexRotationOp_180_90 Line | Count | Source | 2266 | 302 | { \ | 2267 | 302 | add_cs_detail( \ | 2268 | 302 | MI, \ | 2269 | 302 | CONCAT(CONCAT(AArch64_OP_GROUP_ComplexRotationOp, \ | 2270 | 302 | Angle), \ | 2271 | 302 | Remainder), \ | 2272 | 302 | OpNo, Angle, Remainder); \ | 2273 | 302 | unsigned Val = \ | 2274 | 302 | MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ | 2275 | 302 | SStream_concat(O, "%s", markup("<imm:")); \ | 2276 | 302 | SStream_concat(O, "#%d", (Val * Angle) + Remainder); \ | 2277 | 302 | SStream_concat0(O, markup(">")); \ | 2278 | 302 | } |
AArch64InstPrinter.c:printComplexRotationOp_90_0 Line | Count | Source | 2266 | 2.00k | { \ | 2267 | 2.00k | add_cs_detail( \ | 2268 | 2.00k | MI, \ | 2269 | 2.00k | CONCAT(CONCAT(AArch64_OP_GROUP_ComplexRotationOp, \ | 2270 | 2.00k | Angle), \ | 2271 | 2.00k | Remainder), \ | 2272 | 2.00k | OpNo, Angle, Remainder); \ | 2273 | 2.00k | unsigned Val = \ | 2274 | 2.00k | MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ | 2275 | 2.00k | SStream_concat(O, "%s", markup("<imm:")); \ | 2276 | 2.00k | SStream_concat(O, "#%d", (Val * Angle) + Remainder); \ | 2277 | 2.00k | SStream_concat0(O, markup(">")); \ | 2278 | 2.00k | } |
|
2279 | | DEFINE_printComplexRotationOp(180, 90); |
2280 | | DEFINE_printComplexRotationOp(90, 0); |
2281 | | |
2282 | | void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) |
2283 | 6.68k | { |
2284 | 6.68k | add_cs_detail(MI, AArch64_OP_GROUP_SVEPattern, OpNum); |
2285 | 6.68k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
2286 | 6.68k | const AArch64SVEPredPattern_SVEPREDPAT *Pat = |
2287 | 6.68k | AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val); |
2288 | 6.68k | if (Pat) |
2289 | 4.15k | SStream_concat0(O, Pat->Name); |
2290 | 6.68k | } |
2291 | | |
2292 | | void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O) |
2293 | 1.49k | { |
2294 | 1.49k | add_cs_detail(MI, AArch64_OP_GROUP_SVEVecLenSpecifier, OpNum); |
2295 | 1.49k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); |
2296 | | // Pattern has only 1 bit |
2297 | 1.49k | if (Val > 1) |
2298 | 0 | assert(0 && "Invalid vector length specifier"); |
2299 | 1.49k | const AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER *Pat = |
2300 | 1.49k | AArch64SVEVecLenSpecifier_lookupSVEVECLENSPECIFIERByEncoding( |
2301 | 1.49k | Val); |
2302 | 1.49k | if (Pat) |
2303 | 1.49k | SStream_concat0(O, Pat->Name); |
2304 | 1.49k | } |
2305 | | |
2306 | | #define DEFINE_printSVERegOp(suffix) \ |
2307 | | void CONCAT(printSVERegOp, suffix)(MCInst * MI, unsigned OpNum, \ |
2308 | | SStream *O) \ |
2309 | 282k | { \ |
2310 | 282k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ |
2311 | 282k | OpNum, CHAR(suffix)); \ |
2312 | 282k | switch (CHAR(suffix)) { \ |
2313 | 78.7k | case '0': \ |
2314 | 109k | case 'b': \ |
2315 | 142k | case 'h': \ |
2316 | 215k | case 's': \ |
2317 | 281k | case 'd': \ |
2318 | 282k | case 'q': \ |
2319 | 282k | break; \ |
2320 | 281k | default: \ |
2321 | 0 | assert(0 && "Invalid kind specifier."); \ |
2322 | 282k | } \ |
2323 | 282k | \ |
2324 | 282k | unsigned Reg = \ |
2325 | 282k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ |
2326 | 282k | printRegName(O, Reg); \ |
2327 | 282k | if (CHAR(suffix) != '0') { \ |
2328 | 203k | SStream_concat1(O, '.'); \ |
2329 | 203k | SStream_concat1(O, CHAR(suffix)); \ |
2330 | 203k | } \ |
2331 | 282k | } Line | Count | Source | 2309 | 30.4k | { \ | 2310 | 30.4k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 30.4k | OpNum, CHAR(suffix)); \ | 2312 | 30.4k | switch (CHAR(suffix)) { \ | 2313 | 0 | case '0': \ | 2314 | 30.4k | case 'b': \ | 2315 | 30.4k | case 'h': \ | 2316 | 30.4k | case 's': \ | 2317 | 30.4k | case 'd': \ | 2318 | 30.4k | case 'q': \ | 2319 | 30.4k | break; \ | 2320 | 30.4k | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 30.4k | } \ | 2323 | 30.4k | \ | 2324 | 30.4k | unsigned Reg = \ | 2325 | 30.4k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 30.4k | printRegName(O, Reg); \ | 2327 | 30.4k | if (CHAR(suffix) != '0') { \ | 2328 | 30.4k | SStream_concat1(O, '.'); \ | 2329 | 30.4k | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 30.4k | } \ | 2331 | 30.4k | } |
Line | Count | Source | 2309 | 65.5k | { \ | 2310 | 65.5k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 65.5k | OpNum, CHAR(suffix)); \ | 2312 | 65.5k | switch (CHAR(suffix)) { \ | 2313 | 0 | case '0': \ | 2314 | 0 | case 'b': \ | 2315 | 0 | case 'h': \ | 2316 | 0 | case 's': \ | 2317 | 65.5k | case 'd': \ | 2318 | 65.5k | case 'q': \ | 2319 | 65.5k | break; \ | 2320 | 65.5k | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 65.5k | } \ | 2323 | 65.5k | \ | 2324 | 65.5k | unsigned Reg = \ | 2325 | 65.5k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 65.5k | printRegName(O, Reg); \ | 2327 | 65.5k | if (CHAR(suffix) != '0') { \ | 2328 | 65.5k | SStream_concat1(O, '.'); \ | 2329 | 65.5k | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 65.5k | } \ | 2331 | 65.5k | } |
Line | Count | Source | 2309 | 33.4k | { \ | 2310 | 33.4k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 33.4k | OpNum, CHAR(suffix)); \ | 2312 | 33.4k | switch (CHAR(suffix)) { \ | 2313 | 0 | case '0': \ | 2314 | 0 | case 'b': \ | 2315 | 33.4k | case 'h': \ | 2316 | 33.4k | case 's': \ | 2317 | 33.4k | case 'd': \ | 2318 | 33.4k | case 'q': \ | 2319 | 33.4k | break; \ | 2320 | 33.4k | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 33.4k | } \ | 2323 | 33.4k | \ | 2324 | 33.4k | unsigned Reg = \ | 2325 | 33.4k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 33.4k | printRegName(O, Reg); \ | 2327 | 33.4k | if (CHAR(suffix) != '0') { \ | 2328 | 33.4k | SStream_concat1(O, '.'); \ | 2329 | 33.4k | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 33.4k | } \ | 2331 | 33.4k | } |
Line | Count | Source | 2309 | 73.0k | { \ | 2310 | 73.0k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 73.0k | OpNum, CHAR(suffix)); \ | 2312 | 73.0k | switch (CHAR(suffix)) { \ | 2313 | 0 | case '0': \ | 2314 | 0 | case 'b': \ | 2315 | 0 | case 'h': \ | 2316 | 73.0k | case 's': \ | 2317 | 73.0k | case 'd': \ | 2318 | 73.0k | case 'q': \ | 2319 | 73.0k | break; \ | 2320 | 73.0k | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 73.0k | } \ | 2323 | 73.0k | \ | 2324 | 73.0k | unsigned Reg = \ | 2325 | 73.0k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 73.0k | printRegName(O, Reg); \ | 2327 | 73.0k | if (CHAR(suffix) != '0') { \ | 2328 | 73.0k | SStream_concat1(O, '.'); \ | 2329 | 73.0k | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 73.0k | } \ | 2331 | 73.0k | } |
Line | Count | Source | 2309 | 78.7k | { \ | 2310 | 78.7k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 78.7k | OpNum, CHAR(suffix)); \ | 2312 | 78.7k | switch (CHAR(suffix)) { \ | 2313 | 78.7k | case '0': \ | 2314 | 78.7k | case 'b': \ | 2315 | 78.7k | case 'h': \ | 2316 | 78.7k | case 's': \ | 2317 | 78.7k | case 'd': \ | 2318 | 78.7k | case 'q': \ | 2319 | 78.7k | break; \ | 2320 | 78.7k | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 78.7k | } \ | 2323 | 78.7k | \ | 2324 | 78.7k | unsigned Reg = \ | 2325 | 78.7k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 78.7k | printRegName(O, Reg); \ | 2327 | 78.7k | if (CHAR(suffix) != '0') { \ | 2328 | 0 | SStream_concat1(O, '.'); \ | 2329 | 0 | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 0 | } \ | 2331 | 78.7k | } |
Line | Count | Source | 2309 | 1.28k | { \ | 2310 | 1.28k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVERegOp, suffix), \ | 2311 | 1.28k | OpNum, CHAR(suffix)); \ | 2312 | 1.28k | switch (CHAR(suffix)) { \ | 2313 | 0 | case '0': \ | 2314 | 0 | case 'b': \ | 2315 | 0 | case 'h': \ | 2316 | 0 | case 's': \ | 2317 | 0 | case 'd': \ | 2318 | 1.28k | case 'q': \ | 2319 | 1.28k | break; \ | 2320 | 0 | default: \ | 2321 | 0 | assert(0 && "Invalid kind specifier."); \ | 2322 | 1.28k | } \ | 2323 | 1.28k | \ | 2324 | 1.28k | unsigned Reg = \ | 2325 | 1.28k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2326 | 1.28k | printRegName(O, Reg); \ | 2327 | 1.28k | if (CHAR(suffix) != '0') { \ | 2328 | 1.28k | SStream_concat1(O, '.'); \ | 2329 | 1.28k | SStream_concat1(O, CHAR(suffix)); \ | 2330 | 1.28k | } \ | 2331 | 1.28k | } |
|
2332 | | DEFINE_printSVERegOp(b); |
2333 | | DEFINE_printSVERegOp(d); |
2334 | | DEFINE_printSVERegOp(h); |
2335 | | DEFINE_printSVERegOp(s); |
2336 | | DEFINE_printSVERegOp(0); |
2337 | | DEFINE_printSVERegOp(q); |
2338 | | |
2339 | | #define DECLARE_printImmSVE_S32(T) \ |
2340 | | void CONCAT(printImmSVE, T)(T Val, SStream * O) \ |
2341 | 1.89k | { \ |
2342 | 1.89k | printInt32Bang(O, Val); \ |
2343 | 1.89k | } Line | Count | Source | 2341 | 1.25k | { \ | 2342 | 1.25k | printInt32Bang(O, Val); \ | 2343 | 1.25k | } |
Line | Count | Source | 2341 | 323 | { \ | 2342 | 323 | printInt32Bang(O, Val); \ | 2343 | 323 | } |
Line | Count | Source | 2341 | 319 | { \ | 2342 | 319 | printInt32Bang(O, Val); \ | 2343 | 319 | } |
|
2344 | | DECLARE_printImmSVE_S32(int16_t); |
2345 | | DECLARE_printImmSVE_S32(int8_t); |
2346 | | DECLARE_printImmSVE_S32(int32_t); |
2347 | | |
2348 | | #define DECLARE_printImmSVE_U32(T) \ |
2349 | | void CONCAT(printImmSVE, T)(T Val, SStream * O) \ |
2350 | 819 | { \ |
2351 | 819 | printUInt32Bang(O, Val); \ |
2352 | 819 | } Line | Count | Source | 2350 | 365 | { \ | 2351 | 365 | printUInt32Bang(O, Val); \ | 2352 | 365 | } |
Line | Count | Source | 2350 | 56 | { \ | 2351 | 56 | printUInt32Bang(O, Val); \ | 2352 | 56 | } |
Line | Count | Source | 2350 | 398 | { \ | 2351 | 398 | printUInt32Bang(O, Val); \ | 2352 | 398 | } |
|
2353 | | DECLARE_printImmSVE_U32(uint16_t); |
2354 | | DECLARE_printImmSVE_U32(uint8_t); |
2355 | | DECLARE_printImmSVE_U32(uint32_t); |
2356 | | |
2357 | | #define DECLARE_printImmSVE_S64(T) \ |
2358 | | void CONCAT(printImmSVE, T)(T Val, SStream * O) \ |
2359 | 618 | { \ |
2360 | 618 | printInt64Bang(O, Val); \ |
2361 | 618 | } |
2362 | | DECLARE_printImmSVE_S64(int64_t); |
2363 | | |
2364 | | #define DECLARE_printImmSVE_U64(T) \ |
2365 | | void CONCAT(printImmSVE, T)(T Val, SStream * O) \ |
2366 | 306 | { \ |
2367 | 306 | printUInt64Bang(O, Val); \ |
2368 | 306 | } |
2369 | | DECLARE_printImmSVE_U64(uint64_t); |
2370 | | |
2371 | | #define DEFINE_isSignedType(T) \ |
2372 | | static inline bool CONCAT(isSignedType, T)() \ |
2373 | 2.06k | { \ |
2374 | 2.06k | return CHAR(t) == 'i'; \ |
2375 | 2.06k | } AArch64InstPrinter.c:isSignedType_int16_t Line | Count | Source | 2373 | 260 | { \ | 2374 | 260 | return CHAR(t) == 'i'; \ | 2375 | 260 | } |
AArch64InstPrinter.c:isSignedType_int8_t Line | Count | Source | 2373 | 323 | { \ | 2374 | 323 | return CHAR(t) == 'i'; \ | 2375 | 323 | } |
AArch64InstPrinter.c:isSignedType_int64_t Line | Count | Source | 2373 | 204 | { \ | 2374 | 204 | return CHAR(t) == 'i'; \ | 2375 | 204 | } |
AArch64InstPrinter.c:isSignedType_int32_t Line | Count | Source | 2373 | 154 | { \ | 2374 | 154 | return CHAR(t) == 'i'; \ | 2375 | 154 | } |
AArch64InstPrinter.c:isSignedType_uint16_t Line | Count | Source | 2373 | 365 | { \ | 2374 | 365 | return CHAR(t) == 'i'; \ | 2375 | 365 | } |
AArch64InstPrinter.c:isSignedType_uint8_t Line | Count | Source | 2373 | 56 | { \ | 2374 | 56 | return CHAR(t) == 'i'; \ | 2375 | 56 | } |
AArch64InstPrinter.c:isSignedType_uint64_t Line | Count | Source | 2373 | 306 | { \ | 2374 | 306 | return CHAR(t) == 'i'; \ | 2375 | 306 | } |
AArch64InstPrinter.c:isSignedType_uint32_t Line | Count | Source | 2373 | 398 | { \ | 2374 | 398 | return CHAR(t) == 'i'; \ | 2375 | 398 | } |
|
2376 | | DEFINE_isSignedType(int8_t); |
2377 | | DEFINE_isSignedType(int16_t); |
2378 | | DEFINE_isSignedType(int32_t); |
2379 | | DEFINE_isSignedType(int64_t); |
2380 | | DEFINE_isSignedType(uint8_t); |
2381 | | DEFINE_isSignedType(uint16_t); |
2382 | | DEFINE_isSignedType(uint32_t); |
2383 | | DEFINE_isSignedType(uint64_t); |
2384 | | |
2385 | | #define DEFINE_printImm8OptLsl(T) \ |
2386 | | void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \ |
2387 | | SStream *O) \ |
2388 | 2.54k | { \ |
2389 | 2.54k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ |
2390 | 2.54k | OpNum, sizeof(T)); \ |
2391 | 2.54k | unsigned UnscaledVal = \ |
2392 | 2.54k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
2393 | 2.54k | unsigned Shift = \ |
2394 | 2.54k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ |
2395 | 2.54k | \ |
2396 | 2.54k | if ((UnscaledVal == 0) && \ |
2397 | 2.54k | (AArch64_AM_getShiftValue(Shift) != 0)) { \ |
2398 | 481 | SStream_concat(O, "%s", markup("<imm:")); \ |
2399 | 481 | SStream_concat1(O, '#'); \ |
2400 | 481 | printUInt64(O, (UnscaledVal)); \ |
2401 | 481 | SStream_concat0(O, markup(">")); \ |
2402 | 481 | printShifter(MI, OpNum + 1, O); \ |
2403 | 481 | return; \ |
2404 | 481 | } \ |
2405 | 2.54k | \ |
2406 | 2.54k | T Val; \ |
2407 | 2.06k | if (CONCAT(isSignedType, T)()) \ |
2408 | 2.06k | Val = (int8_t)UnscaledVal * \ |
2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ |
2410 | 2.06k | else \ |
2411 | 2.06k | Val = (uint8_t)UnscaledVal * \ |
2412 | 2.06k | (1 << AArch64_AM_getShiftValue(Shift)); \ |
2413 | 2.06k | \ |
2414 | 2.06k | CONCAT(printImmSVE, T)(Val, O); \ |
2415 | 2.06k | } Line | Count | Source | 2388 | 270 | { \ | 2389 | 270 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 270 | OpNum, sizeof(T)); \ | 2391 | 270 | unsigned UnscaledVal = \ | 2392 | 270 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 270 | unsigned Shift = \ | 2394 | 270 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 270 | \ | 2396 | 270 | if ((UnscaledVal == 0) && \ | 2397 | 270 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 10 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 10 | SStream_concat1(O, '#'); \ | 2400 | 10 | printUInt64(O, (UnscaledVal)); \ | 2401 | 10 | SStream_concat0(O, markup(">")); \ | 2402 | 10 | printShifter(MI, OpNum + 1, O); \ | 2403 | 10 | return; \ | 2404 | 10 | } \ | 2405 | 270 | \ | 2406 | 270 | T Val; \ | 2407 | 260 | if (CONCAT(isSignedType, T)()) \ | 2408 | 260 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 260 | else \ | 2411 | 260 | Val = (uint8_t)UnscaledVal * \ | 2412 | 260 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 260 | \ | 2414 | 260 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 260 | } |
Line | Count | Source | 2388 | 323 | { \ | 2389 | 323 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 323 | OpNum, sizeof(T)); \ | 2391 | 323 | unsigned UnscaledVal = \ | 2392 | 323 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 323 | unsigned Shift = \ | 2394 | 323 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 323 | \ | 2396 | 323 | if ((UnscaledVal == 0) && \ | 2397 | 323 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 0 | SStream_concat1(O, '#'); \ | 2400 | 0 | printUInt64(O, (UnscaledVal)); \ | 2401 | 0 | SStream_concat0(O, markup(">")); \ | 2402 | 0 | printShifter(MI, OpNum + 1, O); \ | 2403 | 0 | return; \ | 2404 | 0 | } \ | 2405 | 323 | \ | 2406 | 323 | T Val; \ | 2407 | 323 | if (CONCAT(isSignedType, T)()) \ | 2408 | 323 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 323 | else \ | 2411 | 323 | Val = (uint8_t)UnscaledVal * \ | 2412 | 323 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 323 | \ | 2414 | 323 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 323 | } |
Line | Count | Source | 2388 | 233 | { \ | 2389 | 233 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 233 | OpNum, sizeof(T)); \ | 2391 | 233 | unsigned UnscaledVal = \ | 2392 | 233 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 233 | unsigned Shift = \ | 2394 | 233 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 233 | \ | 2396 | 233 | if ((UnscaledVal == 0) && \ | 2397 | 233 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 29 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 29 | SStream_concat1(O, '#'); \ | 2400 | 29 | printUInt64(O, (UnscaledVal)); \ | 2401 | 29 | SStream_concat0(O, markup(">")); \ | 2402 | 29 | printShifter(MI, OpNum + 1, O); \ | 2403 | 29 | return; \ | 2404 | 29 | } \ | 2405 | 233 | \ | 2406 | 233 | T Val; \ | 2407 | 204 | if (CONCAT(isSignedType, T)()) \ | 2408 | 204 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 204 | else \ | 2411 | 204 | Val = (uint8_t)UnscaledVal * \ | 2412 | 204 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 204 | \ | 2414 | 204 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 204 | } |
Line | Count | Source | 2388 | 262 | { \ | 2389 | 262 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 262 | OpNum, sizeof(T)); \ | 2391 | 262 | unsigned UnscaledVal = \ | 2392 | 262 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 262 | unsigned Shift = \ | 2394 | 262 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 262 | \ | 2396 | 262 | if ((UnscaledVal == 0) && \ | 2397 | 262 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 108 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 108 | SStream_concat1(O, '#'); \ | 2400 | 108 | printUInt64(O, (UnscaledVal)); \ | 2401 | 108 | SStream_concat0(O, markup(">")); \ | 2402 | 108 | printShifter(MI, OpNum + 1, O); \ | 2403 | 108 | return; \ | 2404 | 108 | } \ | 2405 | 262 | \ | 2406 | 262 | T Val; \ | 2407 | 154 | if (CONCAT(isSignedType, T)()) \ | 2408 | 154 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 154 | else \ | 2411 | 154 | Val = (uint8_t)UnscaledVal * \ | 2412 | 154 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 154 | \ | 2414 | 154 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 154 | } |
Line | Count | Source | 2388 | 645 | { \ | 2389 | 645 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 645 | OpNum, sizeof(T)); \ | 2391 | 645 | unsigned UnscaledVal = \ | 2392 | 645 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 645 | unsigned Shift = \ | 2394 | 645 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 645 | \ | 2396 | 645 | if ((UnscaledVal == 0) && \ | 2397 | 645 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 280 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 280 | SStream_concat1(O, '#'); \ | 2400 | 280 | printUInt64(O, (UnscaledVal)); \ | 2401 | 280 | SStream_concat0(O, markup(">")); \ | 2402 | 280 | printShifter(MI, OpNum + 1, O); \ | 2403 | 280 | return; \ | 2404 | 280 | } \ | 2405 | 645 | \ | 2406 | 645 | T Val; \ | 2407 | 365 | if (CONCAT(isSignedType, T)()) \ | 2408 | 365 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 365 | else \ | 2411 | 365 | Val = (uint8_t)UnscaledVal * \ | 2412 | 365 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 365 | \ | 2414 | 365 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 365 | } |
Line | Count | Source | 2388 | 56 | { \ | 2389 | 56 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 56 | OpNum, sizeof(T)); \ | 2391 | 56 | unsigned UnscaledVal = \ | 2392 | 56 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 56 | unsigned Shift = \ | 2394 | 56 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 56 | \ | 2396 | 56 | if ((UnscaledVal == 0) && \ | 2397 | 56 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 0 | SStream_concat1(O, '#'); \ | 2400 | 0 | printUInt64(O, (UnscaledVal)); \ | 2401 | 0 | SStream_concat0(O, markup(">")); \ | 2402 | 0 | printShifter(MI, OpNum + 1, O); \ | 2403 | 0 | return; \ | 2404 | 0 | } \ | 2405 | 56 | \ | 2406 | 56 | T Val; \ | 2407 | 56 | if (CONCAT(isSignedType, T)()) \ | 2408 | 56 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 56 | else \ | 2411 | 56 | Val = (uint8_t)UnscaledVal * \ | 2412 | 56 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 56 | \ | 2414 | 56 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 56 | } |
Line | Count | Source | 2388 | 350 | { \ | 2389 | 350 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 350 | OpNum, sizeof(T)); \ | 2391 | 350 | unsigned UnscaledVal = \ | 2392 | 350 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 350 | unsigned Shift = \ | 2394 | 350 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 350 | \ | 2396 | 350 | if ((UnscaledVal == 0) && \ | 2397 | 350 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 44 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 44 | SStream_concat1(O, '#'); \ | 2400 | 44 | printUInt64(O, (UnscaledVal)); \ | 2401 | 44 | SStream_concat0(O, markup(">")); \ | 2402 | 44 | printShifter(MI, OpNum + 1, O); \ | 2403 | 44 | return; \ | 2404 | 44 | } \ | 2405 | 350 | \ | 2406 | 350 | T Val; \ | 2407 | 306 | if (CONCAT(isSignedType, T)()) \ | 2408 | 306 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 306 | else \ | 2411 | 306 | Val = (uint8_t)UnscaledVal * \ | 2412 | 306 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 306 | \ | 2414 | 306 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 306 | } |
Line | Count | Source | 2388 | 408 | { \ | 2389 | 408 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_Imm8OptLsl, T), \ | 2390 | 408 | OpNum, sizeof(T)); \ | 2391 | 408 | unsigned UnscaledVal = \ | 2392 | 408 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2393 | 408 | unsigned Shift = \ | 2394 | 408 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 1))); \ | 2395 | 408 | \ | 2396 | 408 | if ((UnscaledVal == 0) && \ | 2397 | 408 | (AArch64_AM_getShiftValue(Shift) != 0)) { \ | 2398 | 10 | SStream_concat(O, "%s", markup("<imm:")); \ | 2399 | 10 | SStream_concat1(O, '#'); \ | 2400 | 10 | printUInt64(O, (UnscaledVal)); \ | 2401 | 10 | SStream_concat0(O, markup(">")); \ | 2402 | 10 | printShifter(MI, OpNum + 1, O); \ | 2403 | 10 | return; \ | 2404 | 10 | } \ | 2405 | 408 | \ | 2406 | 408 | T Val; \ | 2407 | 398 | if (CONCAT(isSignedType, T)()) \ | 2408 | 398 | Val = (int8_t)UnscaledVal * \ | 2409 | 0 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2410 | 398 | else \ | 2411 | 398 | Val = (uint8_t)UnscaledVal * \ | 2412 | 398 | (1 << AArch64_AM_getShiftValue(Shift)); \ | 2413 | 398 | \ | 2414 | 398 | CONCAT(printImmSVE, T)(Val, O); \ | 2415 | 398 | } |
|
2416 | | DEFINE_printImm8OptLsl(int16_t); |
2417 | | DEFINE_printImm8OptLsl(int8_t); |
2418 | | DEFINE_printImm8OptLsl(int64_t); |
2419 | | DEFINE_printImm8OptLsl(int32_t); |
2420 | | DEFINE_printImm8OptLsl(uint16_t); |
2421 | | DEFINE_printImm8OptLsl(uint8_t); |
2422 | | DEFINE_printImm8OptLsl(uint64_t); |
2423 | | DEFINE_printImm8OptLsl(uint32_t); |
2424 | | |
2425 | | #define DEFINE_printSVELogicalImm(T) \ |
2426 | | void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \ |
2427 | | SStream *O) \ |
2428 | 2.81k | { \ |
2429 | 2.81k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), \ |
2430 | 2.81k | OpNum, sizeof(T)); \ |
2431 | 2.81k | typedef T SignedT; \ |
2432 | 2.81k | typedef CONCATS(u, T) UnsignedT; \ |
2433 | 2.81k | \ |
2434 | 2.81k | uint64_t Val = \ |
2435 | 2.81k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
2436 | 2.81k | UnsignedT PrintVal = \ |
2437 | 2.81k | AArch64_AM_decodeLogicalImmediate(Val, 64); \ |
2438 | 2.81k | \ |
2439 | 2.81k | if ((int16_t)PrintVal == (SignedT)PrintVal) \ |
2440 | 2.81k | CONCAT(printImmSVE, T)((T)PrintVal, O); \ |
2441 | 2.81k | else if ((uint16_t)PrintVal == PrintVal) \ |
2442 | 1.64k | CONCAT(printImmSVE, T)(PrintVal, O); \ |
2443 | 1.64k | else { \ |
2444 | 1.24k | SStream_concat(O, "%s", markup("<imm:")); \ |
2445 | 1.24k | printUInt64Bang(O, ((uint64_t)PrintVal)); \ |
2446 | 1.24k | SStream_concat0(O, markup(">")); \ |
2447 | 1.24k | } \ |
2448 | 2.81k | } printSVELogicalImm_int16_t Line | Count | Source | 2428 | 991 | { \ | 2429 | 991 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), \ | 2430 | 991 | OpNum, sizeof(T)); \ | 2431 | 991 | typedef T SignedT; \ | 2432 | 991 | typedef CONCATS(u, T) UnsignedT; \ | 2433 | 991 | \ | 2434 | 991 | uint64_t Val = \ | 2435 | 991 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2436 | 991 | UnsignedT PrintVal = \ | 2437 | 991 | AArch64_AM_decodeLogicalImmediate(Val, 64); \ | 2438 | 991 | \ | 2439 | 991 | if ((int16_t)PrintVal == (SignedT)PrintVal) \ | 2440 | 991 | CONCAT(printImmSVE, T)((T)PrintVal, O); \ | 2441 | 991 | else if ((uint16_t)PrintVal == PrintVal) \ | 2442 | 0 | CONCAT(printImmSVE, T)(PrintVal, O); \ | 2443 | 0 | else { \ | 2444 | 0 | SStream_concat(O, "%s", markup("<imm:")); \ | 2445 | 0 | printUInt64Bang(O, ((uint64_t)PrintVal)); \ | 2446 | 0 | SStream_concat0(O, markup(">")); \ | 2447 | 0 | } \ | 2448 | 991 | } |
printSVELogicalImm_int32_t Line | Count | Source | 2428 | 765 | { \ | 2429 | 765 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), \ | 2430 | 765 | OpNum, sizeof(T)); \ | 2431 | 765 | typedef T SignedT; \ | 2432 | 765 | typedef CONCATS(u, T) UnsignedT; \ | 2433 | 765 | \ | 2434 | 765 | uint64_t Val = \ | 2435 | 765 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2436 | 765 | UnsignedT PrintVal = \ | 2437 | 765 | AArch64_AM_decodeLogicalImmediate(Val, 64); \ | 2438 | 765 | \ | 2439 | 765 | if ((int16_t)PrintVal == (SignedT)PrintVal) \ | 2440 | 765 | CONCAT(printImmSVE, T)((T)PrintVal, O); \ | 2441 | 765 | else if ((uint16_t)PrintVal == PrintVal) \ | 2442 | 623 | CONCAT(printImmSVE, T)(PrintVal, O); \ | 2443 | 623 | else { \ | 2444 | 600 | SStream_concat(O, "%s", markup("<imm:")); \ | 2445 | 600 | printUInt64Bang(O, ((uint64_t)PrintVal)); \ | 2446 | 600 | SStream_concat0(O, markup(">")); \ | 2447 | 600 | } \ | 2448 | 765 | } |
printSVELogicalImm_int64_t Line | Count | Source | 2428 | 1.05k | { \ | 2429 | 1.05k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_SVELogicalImm, T), \ | 2430 | 1.05k | OpNum, sizeof(T)); \ | 2431 | 1.05k | typedef T SignedT; \ | 2432 | 1.05k | typedef CONCATS(u, T) UnsignedT; \ | 2433 | 1.05k | \ | 2434 | 1.05k | uint64_t Val = \ | 2435 | 1.05k | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2436 | 1.05k | UnsignedT PrintVal = \ | 2437 | 1.05k | AArch64_AM_decodeLogicalImmediate(Val, 64); \ | 2438 | 1.05k | \ | 2439 | 1.05k | if ((int16_t)PrintVal == (SignedT)PrintVal) \ | 2440 | 1.05k | CONCAT(printImmSVE, T)((T)PrintVal, O); \ | 2441 | 1.05k | else if ((uint16_t)PrintVal == PrintVal) \ | 2442 | 1.02k | CONCAT(printImmSVE, T)(PrintVal, O); \ | 2443 | 1.02k | else { \ | 2444 | 642 | SStream_concat(O, "%s", markup("<imm:")); \ | 2445 | 642 | printUInt64Bang(O, ((uint64_t)PrintVal)); \ | 2446 | 642 | SStream_concat0(O, markup(">")); \ | 2447 | 642 | } \ | 2448 | 1.05k | } |
|
2449 | | DEFINE_printSVELogicalImm(int16_t); |
2450 | | DEFINE_printSVELogicalImm(int32_t); |
2451 | | DEFINE_printSVELogicalImm(int64_t); |
2452 | | |
2453 | | #define DEFINE_printZPRasFPR(Width) \ |
2454 | | void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \ |
2455 | | SStream *O) \ |
2456 | 1.46k | { \ |
2457 | 1.46k | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ |
2458 | 1.46k | OpNum, Width); \ |
2459 | 1.46k | unsigned Base; \ |
2460 | 1.46k | switch (Width) { \ |
2461 | 456 | case 8: \ |
2462 | 456 | Base = AArch64_B0; \ |
2463 | 456 | break; \ |
2464 | 96 | case 16: \ |
2465 | 96 | Base = AArch64_H0; \ |
2466 | 96 | break; \ |
2467 | 580 | case 32: \ |
2468 | 580 | Base = AArch64_S0; \ |
2469 | 580 | break; \ |
2470 | 316 | case 64: \ |
2471 | 316 | Base = AArch64_D0; \ |
2472 | 316 | break; \ |
2473 | 16 | case 128: \ |
2474 | 16 | Base = AArch64_Q0; \ |
2475 | 16 | break; \ |
2476 | 0 | default: \ |
2477 | 0 | assert(0 && "Unsupported width"); \ |
2478 | 1.46k | } \ |
2479 | 1.46k | unsigned Reg = \ |
2480 | 1.46k | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ |
2481 | 1.46k | printRegName(O, Reg - AArch64_Z0 + Base); \ |
2482 | 1.46k | } Line | Count | Source | 2456 | 456 | { \ | 2457 | 456 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ | 2458 | 456 | OpNum, Width); \ | 2459 | 456 | unsigned Base; \ | 2460 | 456 | switch (Width) { \ | 2461 | 456 | case 8: \ | 2462 | 456 | Base = AArch64_B0; \ | 2463 | 456 | break; \ | 2464 | 0 | case 16: \ | 2465 | 0 | Base = AArch64_H0; \ | 2466 | 0 | break; \ | 2467 | 0 | case 32: \ | 2468 | 0 | Base = AArch64_S0; \ | 2469 | 0 | break; \ | 2470 | 0 | case 64: \ | 2471 | 0 | Base = AArch64_D0; \ | 2472 | 0 | break; \ | 2473 | 0 | case 128: \ | 2474 | 0 | Base = AArch64_Q0; \ | 2475 | 0 | break; \ | 2476 | 0 | default: \ | 2477 | 0 | assert(0 && "Unsupported width"); \ | 2478 | 456 | } \ | 2479 | 456 | unsigned Reg = \ | 2480 | 456 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2481 | 456 | printRegName(O, Reg - AArch64_Z0 + Base); \ | 2482 | 456 | } |
Line | Count | Source | 2456 | 316 | { \ | 2457 | 316 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ | 2458 | 316 | OpNum, Width); \ | 2459 | 316 | unsigned Base; \ | 2460 | 316 | switch (Width) { \ | 2461 | 0 | case 8: \ | 2462 | 0 | Base = AArch64_B0; \ | 2463 | 0 | break; \ | 2464 | 0 | case 16: \ | 2465 | 0 | Base = AArch64_H0; \ | 2466 | 0 | break; \ | 2467 | 0 | case 32: \ | 2468 | 0 | Base = AArch64_S0; \ | 2469 | 0 | break; \ | 2470 | 316 | case 64: \ | 2471 | 316 | Base = AArch64_D0; \ | 2472 | 316 | break; \ | 2473 | 0 | case 128: \ | 2474 | 0 | Base = AArch64_Q0; \ | 2475 | 0 | break; \ | 2476 | 0 | default: \ | 2477 | 0 | assert(0 && "Unsupported width"); \ | 2478 | 316 | } \ | 2479 | 316 | unsigned Reg = \ | 2480 | 316 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2481 | 316 | printRegName(O, Reg - AArch64_Z0 + Base); \ | 2482 | 316 | } |
Line | Count | Source | 2456 | 96 | { \ | 2457 | 96 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ | 2458 | 96 | OpNum, Width); \ | 2459 | 96 | unsigned Base; \ | 2460 | 96 | switch (Width) { \ | 2461 | 0 | case 8: \ | 2462 | 0 | Base = AArch64_B0; \ | 2463 | 0 | break; \ | 2464 | 96 | case 16: \ | 2465 | 96 | Base = AArch64_H0; \ | 2466 | 96 | break; \ | 2467 | 0 | case 32: \ | 2468 | 0 | Base = AArch64_S0; \ | 2469 | 0 | break; \ | 2470 | 0 | case 64: \ | 2471 | 0 | Base = AArch64_D0; \ | 2472 | 0 | break; \ | 2473 | 0 | case 128: \ | 2474 | 0 | Base = AArch64_Q0; \ | 2475 | 0 | break; \ | 2476 | 0 | default: \ | 2477 | 0 | assert(0 && "Unsupported width"); \ | 2478 | 96 | } \ | 2479 | 96 | unsigned Reg = \ | 2480 | 96 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2481 | 96 | printRegName(O, Reg - AArch64_Z0 + Base); \ | 2482 | 96 | } |
Line | Count | Source | 2456 | 580 | { \ | 2457 | 580 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ | 2458 | 580 | OpNum, Width); \ | 2459 | 580 | unsigned Base; \ | 2460 | 580 | switch (Width) { \ | 2461 | 0 | case 8: \ | 2462 | 0 | Base = AArch64_B0; \ | 2463 | 0 | break; \ | 2464 | 0 | case 16: \ | 2465 | 0 | Base = AArch64_H0; \ | 2466 | 0 | break; \ | 2467 | 580 | case 32: \ | 2468 | 580 | Base = AArch64_S0; \ | 2469 | 580 | break; \ | 2470 | 0 | case 64: \ | 2471 | 0 | Base = AArch64_D0; \ | 2472 | 0 | break; \ | 2473 | 0 | case 128: \ | 2474 | 0 | Base = AArch64_Q0; \ | 2475 | 0 | break; \ | 2476 | 0 | default: \ | 2477 | 0 | assert(0 && "Unsupported width"); \ | 2478 | 580 | } \ | 2479 | 580 | unsigned Reg = \ | 2480 | 580 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2481 | 580 | printRegName(O, Reg - AArch64_Z0 + Base); \ | 2482 | 580 | } |
Line | Count | Source | 2456 | 16 | { \ | 2457 | 16 | add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_ZPRasFPR, Width), \ | 2458 | 16 | OpNum, Width); \ | 2459 | 16 | unsigned Base; \ | 2460 | 16 | switch (Width) { \ | 2461 | 0 | case 8: \ | 2462 | 0 | Base = AArch64_B0; \ | 2463 | 0 | break; \ | 2464 | 0 | case 16: \ | 2465 | 0 | Base = AArch64_H0; \ | 2466 | 0 | break; \ | 2467 | 0 | case 32: \ | 2468 | 0 | Base = AArch64_S0; \ | 2469 | 0 | break; \ | 2470 | 0 | case 64: \ | 2471 | 0 | Base = AArch64_D0; \ | 2472 | 0 | break; \ | 2473 | 16 | case 128: \ | 2474 | 16 | Base = AArch64_Q0; \ | 2475 | 16 | break; \ | 2476 | 0 | default: \ | 2477 | 0 | assert(0 && "Unsupported width"); \ | 2478 | 16 | } \ | 2479 | 16 | unsigned Reg = \ | 2480 | 16 | MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ | 2481 | 16 | printRegName(O, Reg - AArch64_Z0 + Base); \ | 2482 | 16 | } |
|
2483 | | DEFINE_printZPRasFPR(8); |
2484 | | DEFINE_printZPRasFPR(64); |
2485 | | DEFINE_printZPRasFPR(16); |
2486 | | DEFINE_printZPRasFPR(32); |
2487 | | DEFINE_printZPRasFPR(128); |
2488 | | |
2489 | | #define DEFINE_printExactFPImm(ImmIs0, ImmIs1) \ |
2490 | | void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \ |
2491 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
2492 | 788 | { \ |
2493 | 788 | add_cs_detail( \ |
2494 | 788 | MI, \ |
2495 | 788 | CONCAT(CONCAT(AArch64_OP_GROUP_ExactFPImm, ImmIs0), \ |
2496 | 788 | ImmIs1), \ |
2497 | 788 | OpNum, ImmIs0, ImmIs1); \ |
2498 | 788 | const AArch64ExactFPImm_ExactFPImm *Imm0Desc = \ |
2499 | 788 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs0); \ |
2500 | 788 | const AArch64ExactFPImm_ExactFPImm *Imm1Desc = \ |
2501 | 788 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs1); \ |
2502 | 788 | unsigned Val = \ |
2503 | 788 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ |
2504 | 788 | SStream_concat(O, "%s%s%s", markup("<imm:"), "#", \ |
2505 | 788 | (Val ? Imm1Desc->Repr : Imm0Desc->Repr)); \ |
2506 | 788 | SStream_concat0(O, markup(">")); \ |
2507 | 788 | } printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one Line | Count | Source | 2492 | 66 | { \ | 2493 | 66 | add_cs_detail( \ | 2494 | 66 | MI, \ | 2495 | 66 | CONCAT(CONCAT(AArch64_OP_GROUP_ExactFPImm, ImmIs0), \ | 2496 | 66 | ImmIs1), \ | 2497 | 66 | OpNum, ImmIs0, ImmIs1); \ | 2498 | 66 | const AArch64ExactFPImm_ExactFPImm *Imm0Desc = \ | 2499 | 66 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs0); \ | 2500 | 66 | const AArch64ExactFPImm_ExactFPImm *Imm1Desc = \ | 2501 | 66 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs1); \ | 2502 | 66 | unsigned Val = \ | 2503 | 66 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2504 | 66 | SStream_concat(O, "%s%s%s", markup("<imm:"), "#", \ | 2505 | 66 | (Val ? Imm1Desc->Repr : Imm0Desc->Repr)); \ | 2506 | 66 | SStream_concat0(O, markup(">")); \ | 2507 | 66 | } |
printExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one Line | Count | Source | 2492 | 670 | { \ | 2493 | 670 | add_cs_detail( \ | 2494 | 670 | MI, \ | 2495 | 670 | CONCAT(CONCAT(AArch64_OP_GROUP_ExactFPImm, ImmIs0), \ | 2496 | 670 | ImmIs1), \ | 2497 | 670 | OpNum, ImmIs0, ImmIs1); \ | 2498 | 670 | const AArch64ExactFPImm_ExactFPImm *Imm0Desc = \ | 2499 | 670 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs0); \ | 2500 | 670 | const AArch64ExactFPImm_ExactFPImm *Imm1Desc = \ | 2501 | 670 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs1); \ | 2502 | 670 | unsigned Val = \ | 2503 | 670 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2504 | 670 | SStream_concat(O, "%s%s%s", markup("<imm:"), "#", \ | 2505 | 670 | (Val ? Imm1Desc->Repr : Imm0Desc->Repr)); \ | 2506 | 670 | SStream_concat0(O, markup(">")); \ | 2507 | 670 | } |
printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two Line | Count | Source | 2492 | 52 | { \ | 2493 | 52 | add_cs_detail( \ | 2494 | 52 | MI, \ | 2495 | 52 | CONCAT(CONCAT(AArch64_OP_GROUP_ExactFPImm, ImmIs0), \ | 2496 | 52 | ImmIs1), \ | 2497 | 52 | OpNum, ImmIs0, ImmIs1); \ | 2498 | 52 | const AArch64ExactFPImm_ExactFPImm *Imm0Desc = \ | 2499 | 52 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs0); \ | 2500 | 52 | const AArch64ExactFPImm_ExactFPImm *Imm1Desc = \ | 2501 | 52 | AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs1); \ | 2502 | 52 | unsigned Val = \ | 2503 | 52 | MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ | 2504 | 52 | SStream_concat(O, "%s%s%s", markup("<imm:"), "#", \ | 2505 | 52 | (Val ? Imm1Desc->Repr : Imm0Desc->Repr)); \ | 2506 | 52 | SStream_concat0(O, markup(">")); \ | 2507 | 52 | } |
|
2508 | | DEFINE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one); |
2509 | | DEFINE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one); |
2510 | | DEFINE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two); |
2511 | | |
2512 | | void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) |
2513 | 6.51k | { |
2514 | 6.51k | add_cs_detail(MI, AArch64_OP_GROUP_GPR64as32, OpNum); |
2515 | 6.51k | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); |
2516 | 6.51k | printRegName(O, getWRegFromXReg(Reg)); |
2517 | 6.51k | } |
2518 | | |
2519 | | void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) |
2520 | 39 | { |
2521 | 39 | add_cs_detail(MI, AArch64_OP_GROUP_GPR64x8, OpNum); |
2522 | 39 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); |
2523 | 39 | printRegName(O, |
2524 | 39 | MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0)); |
2525 | 39 | } |
2526 | | |
2527 | | void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O) |
2528 | 451 | { |
2529 | 451 | add_cs_detail(MI, AArch64_OP_GROUP_SyspXzrPair, OpNum); |
2530 | 451 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); |
2531 | | |
2532 | 451 | SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), |
2533 | 451 | ", "); |
2534 | 451 | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
2535 | 451 | } |
2536 | | |
2537 | | const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx) |
2538 | 186k | { |
2539 | 186k | return getRegisterName(RegNo, AltIdx); |
2540 | 186k | } |
2541 | | |
2542 | | void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O, |
2543 | | void * /* MCRegisterInfo* */ info) |
2544 | 337k | { |
2545 | 337k | printInst(MI, MI->address, "", O); |
2546 | 337k | } |