/src/capstonenext/arch/AArch64/AArch64InstPrinter.h
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1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This class prints an AArch64 MCInst to a .s file. |
24 | | // |
25 | | //===----------------------------------------------------------------------===// |
26 | | |
27 | | #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H |
28 | | #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H |
29 | | |
30 | | #include <stdio.h> |
31 | | #include <string.h> |
32 | | #include <stdlib.h> |
33 | | #include <capstone/platform.h> |
34 | | |
35 | | #include "AArch64Mapping.h" |
36 | | |
37 | | #include "../../MCInst.h" |
38 | | #include "../../MCRegisterInfo.h" |
39 | | #include "../../MCInstPrinter.h" |
40 | | #include "../../SStream.h" |
41 | | #include "../../utils.h" |
42 | | |
43 | 18.2k | #define CONCAT(a, b) CONCAT_(a, b) |
44 | 18.2k | #define CONCAT_(a, b) a##_##b |
45 | 1.34M | #define CHAR(c) #c[0] |
46 | | |
47 | | void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O); |
48 | | void printRegName(SStream *OS, unsigned Reg); |
49 | | void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx); |
50 | | // Autogenerated by tblgen. |
51 | | const char *getRegName(unsigned Reg); |
52 | | bool printSysAlias(MCInst *MI, SStream *O); |
53 | | bool printSyspAlias(MCInst *MI, SStream *O); |
54 | | bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot); |
55 | | // Operand printers |
56 | | void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
57 | | void printImm(MCInst *MI, unsigned OpNo, SStream *O); |
58 | | void printImmHex(MCInst *MI, unsigned OpNo, SStream *O); |
59 | | #define DECLARE_printSImm(Size) \ |
60 | | void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O); |
61 | | DECLARE_printSImm(16); |
62 | | DECLARE_printSImm(8); |
63 | | |
64 | | #define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O); |
65 | | DECLARE_printImmSVE(int16_t); |
66 | | DECLARE_printImmSVE(int8_t); |
67 | | DECLARE_printImmSVE(int64_t); |
68 | | DECLARE_printImmSVE(int32_t); |
69 | | DECLARE_printImmSVE(uint16_t); |
70 | | DECLARE_printImmSVE(uint8_t); |
71 | | DECLARE_printImmSVE(uint64_t); |
72 | | DECLARE_printImmSVE(uint32_t); |
73 | | |
74 | | void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O); |
75 | | #define DEFINE_printPostIncOperand(Amount) \ |
76 | | static inline void CONCAT(printPostIncOperand, Amount)( \ |
77 | | MCInst * MI, unsigned OpNo, SStream *O) \ |
78 | 9.29k | { \ |
79 | 9.29k | add_cs_detail(MI, \ |
80 | 9.29k | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ |
81 | 9.29k | OpNo, Amount); \ |
82 | 9.29k | printPostIncOperand(MI, OpNo, Amount, O); \ |
83 | 9.29k | } Unexecuted instantiation: AArch64Module.c:printPostIncOperand_64 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_32 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_16 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_8 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_1 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_4 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_2 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_48 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_24 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_3 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_12 Unexecuted instantiation: AArch64Module.c:printPostIncOperand_6 AArch64InstPrinter.c:printPostIncOperand_64 Line | Count | Source | 78 | 164 | { \ | 79 | 164 | add_cs_detail(MI, \ | 80 | 164 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 164 | OpNo, Amount); \ | 82 | 164 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 164 | } |
AArch64InstPrinter.c:printPostIncOperand_32 Line | Count | Source | 78 | 1.61k | { \ | 79 | 1.61k | add_cs_detail(MI, \ | 80 | 1.61k | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 1.61k | OpNo, Amount); \ | 82 | 1.61k | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 1.61k | } |
AArch64InstPrinter.c:printPostIncOperand_16 Line | Count | Source | 78 | 1.63k | { \ | 79 | 1.63k | add_cs_detail(MI, \ | 80 | 1.63k | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 1.63k | OpNo, Amount); \ | 82 | 1.63k | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 1.63k | } |
AArch64InstPrinter.c:printPostIncOperand_8 Line | Count | Source | 78 | 1.80k | { \ | 79 | 1.80k | add_cs_detail(MI, \ | 80 | 1.80k | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 1.80k | OpNo, Amount); \ | 82 | 1.80k | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 1.80k | } |
AArch64InstPrinter.c:printPostIncOperand_1 Line | Count | Source | 78 | 895 | { \ | 79 | 895 | add_cs_detail(MI, \ | 80 | 895 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 895 | OpNo, Amount); \ | 82 | 895 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 895 | } |
AArch64InstPrinter.c:printPostIncOperand_4 Line | Count | Source | 78 | 722 | { \ | 79 | 722 | add_cs_detail(MI, \ | 80 | 722 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 722 | OpNo, Amount); \ | 82 | 722 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 722 | } |
AArch64InstPrinter.c:printPostIncOperand_2 Line | Count | Source | 78 | 633 | { \ | 79 | 633 | add_cs_detail(MI, \ | 80 | 633 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 633 | OpNo, Amount); \ | 82 | 633 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 633 | } |
AArch64InstPrinter.c:printPostIncOperand_48 Line | Count | Source | 78 | 29 | { \ | 79 | 29 | add_cs_detail(MI, \ | 80 | 29 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 29 | OpNo, Amount); \ | 82 | 29 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 29 | } |
AArch64InstPrinter.c:printPostIncOperand_24 Line | Count | Source | 78 | 1.36k | { \ | 79 | 1.36k | add_cs_detail(MI, \ | 80 | 1.36k | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 1.36k | OpNo, Amount); \ | 82 | 1.36k | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 1.36k | } |
AArch64InstPrinter.c:printPostIncOperand_3 Line | Count | Source | 78 | 139 | { \ | 79 | 139 | add_cs_detail(MI, \ | 80 | 139 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 139 | OpNo, Amount); \ | 82 | 139 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 139 | } |
AArch64InstPrinter.c:printPostIncOperand_12 Line | Count | Source | 78 | 94 | { \ | 79 | 94 | add_cs_detail(MI, \ | 80 | 94 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 94 | OpNo, Amount); \ | 82 | 94 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 94 | } |
AArch64InstPrinter.c:printPostIncOperand_6 Line | Count | Source | 78 | 205 | { \ | 79 | 205 | add_cs_detail(MI, \ | 80 | 205 | CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \ | 81 | 205 | OpNo, Amount); \ | 82 | 205 | printPostIncOperand(MI, OpNo, Amount, O); \ | 83 | 205 | } |
|
84 | | DEFINE_printPostIncOperand(64); |
85 | | DEFINE_printPostIncOperand(32); |
86 | | DEFINE_printPostIncOperand(16); |
87 | | DEFINE_printPostIncOperand(8); |
88 | | DEFINE_printPostIncOperand(1); |
89 | | DEFINE_printPostIncOperand(4); |
90 | | DEFINE_printPostIncOperand(2); |
91 | | DEFINE_printPostIncOperand(48); |
92 | | DEFINE_printPostIncOperand(24); |
93 | | DEFINE_printPostIncOperand(3); |
94 | | DEFINE_printPostIncOperand(12); |
95 | | DEFINE_printPostIncOperand(6); |
96 | | |
97 | | void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O); |
98 | | void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O); |
99 | | void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O); |
100 | | #define DECLARE_printLogicalImm(T) \ |
101 | | void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \ |
102 | | SStream *O); |
103 | | DECLARE_printLogicalImm(int64_t); |
104 | | DECLARE_printLogicalImm(int32_t); |
105 | | DECLARE_printLogicalImm(int8_t); |
106 | | DECLARE_printLogicalImm(int16_t); |
107 | | |
108 | | void printShifter(MCInst *MI, unsigned OpNum, SStream *O); |
109 | | void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O); |
110 | | void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O); |
111 | | void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O); |
112 | | |
113 | | void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, |
114 | | unsigned Width); |
115 | | void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, |
116 | | unsigned Width); |
117 | | #define DEFINE_printMemExtend(SrcRegKind, Width) \ |
118 | | static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \ |
119 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
120 | 2.08k | { \ |
121 | 2.08k | add_cs_detail( \ |
122 | 2.08k | MI, \ |
123 | 2.08k | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ |
124 | 2.08k | Width), \ |
125 | 2.08k | OpNum, CHAR(SrcRegKind), Width); \ |
126 | 2.08k | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ |
127 | 2.08k | } Unexecuted instantiation: AArch64Module.c:printMemExtend_w_8 Unexecuted instantiation: AArch64Module.c:printMemExtend_x_8 Unexecuted instantiation: AArch64Module.c:printMemExtend_w_64 Unexecuted instantiation: AArch64Module.c:printMemExtend_x_64 Unexecuted instantiation: AArch64Module.c:printMemExtend_w_16 Unexecuted instantiation: AArch64Module.c:printMemExtend_x_16 Unexecuted instantiation: AArch64Module.c:printMemExtend_w_128 Unexecuted instantiation: AArch64Module.c:printMemExtend_x_128 Unexecuted instantiation: AArch64Module.c:printMemExtend_w_32 Unexecuted instantiation: AArch64Module.c:printMemExtend_x_32 AArch64InstPrinter.c:printMemExtend_w_8 Line | Count | Source | 120 | 60 | { \ | 121 | 60 | add_cs_detail( \ | 122 | 60 | MI, \ | 123 | 60 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 60 | Width), \ | 125 | 60 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 60 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 60 | } |
AArch64InstPrinter.c:printMemExtend_x_8 Line | Count | Source | 120 | 111 | { \ | 121 | 111 | add_cs_detail( \ | 122 | 111 | MI, \ | 123 | 111 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 111 | Width), \ | 125 | 111 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 111 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 111 | } |
AArch64InstPrinter.c:printMemExtend_w_64 Line | Count | Source | 120 | 220 | { \ | 121 | 220 | add_cs_detail( \ | 122 | 220 | MI, \ | 123 | 220 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 220 | Width), \ | 125 | 220 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 220 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 220 | } |
AArch64InstPrinter.c:printMemExtend_x_64 Line | Count | Source | 120 | 647 | { \ | 121 | 647 | add_cs_detail( \ | 122 | 647 | MI, \ | 123 | 647 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 647 | Width), \ | 125 | 647 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 647 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 647 | } |
AArch64InstPrinter.c:printMemExtend_w_16 Line | Count | Source | 120 | 257 | { \ | 121 | 257 | add_cs_detail( \ | 122 | 257 | MI, \ | 123 | 257 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 257 | Width), \ | 125 | 257 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 257 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 257 | } |
AArch64InstPrinter.c:printMemExtend_x_16 Line | Count | Source | 120 | 663 | { \ | 121 | 663 | add_cs_detail( \ | 122 | 663 | MI, \ | 123 | 663 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 663 | Width), \ | 125 | 663 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 663 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 663 | } |
AArch64InstPrinter.c:printMemExtend_w_128 Line | Count | Source | 120 | 11 | { \ | 121 | 11 | add_cs_detail( \ | 122 | 11 | MI, \ | 123 | 11 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 11 | Width), \ | 125 | 11 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 11 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 11 | } |
AArch64InstPrinter.c:printMemExtend_x_128 Line | Count | Source | 120 | 12 | { \ | 121 | 12 | add_cs_detail( \ | 122 | 12 | MI, \ | 123 | 12 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 12 | Width), \ | 125 | 12 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 12 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 12 | } |
AArch64InstPrinter.c:printMemExtend_w_32 Line | Count | Source | 120 | 76 | { \ | 121 | 76 | add_cs_detail( \ | 122 | 76 | MI, \ | 123 | 76 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 76 | Width), \ | 125 | 76 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 76 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 76 | } |
AArch64InstPrinter.c:printMemExtend_x_32 Line | Count | Source | 120 | 23 | { \ | 121 | 23 | add_cs_detail( \ | 122 | 23 | MI, \ | 123 | 23 | CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \ | 124 | 23 | Width), \ | 125 | 23 | OpNum, CHAR(SrcRegKind), Width); \ | 126 | 23 | printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \ | 127 | 23 | } |
|
128 | | DEFINE_printMemExtend(w, 8); |
129 | | DEFINE_printMemExtend(x, 8); |
130 | | DEFINE_printMemExtend(w, 64); |
131 | | DEFINE_printMemExtend(x, 64); |
132 | | DEFINE_printMemExtend(w, 16); |
133 | | DEFINE_printMemExtend(x, 16); |
134 | | DEFINE_printMemExtend(w, 128); |
135 | | DEFINE_printMemExtend(x, 128); |
136 | | DEFINE_printMemExtend(w, 32); |
137 | | DEFINE_printMemExtend(x, 32); |
138 | | |
139 | | #define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \ |
140 | | Suffix) \ |
141 | | void CONCAT(printRegWithShiftExtend, \ |
142 | | CONCAT(SignedExtend, \ |
143 | | CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \ |
144 | | MCInst * MI, unsigned OpNum, SStream *O); |
145 | | DECLARE_printRegWithShiftExtend(false, 8, x, d); |
146 | | DECLARE_printRegWithShiftExtend(true, 8, w, d); |
147 | | DECLARE_printRegWithShiftExtend(false, 8, w, d); |
148 | | DECLARE_printRegWithShiftExtend(false, 8, x, 0); |
149 | | DECLARE_printRegWithShiftExtend(true, 8, w, s); |
150 | | DECLARE_printRegWithShiftExtend(false, 8, w, s); |
151 | | DECLARE_printRegWithShiftExtend(false, 64, x, d); |
152 | | DECLARE_printRegWithShiftExtend(true, 64, w, d); |
153 | | DECLARE_printRegWithShiftExtend(false, 64, w, d); |
154 | | DECLARE_printRegWithShiftExtend(false, 64, x, 0); |
155 | | DECLARE_printRegWithShiftExtend(true, 64, w, s); |
156 | | DECLARE_printRegWithShiftExtend(false, 64, w, s); |
157 | | DECLARE_printRegWithShiftExtend(false, 16, x, d); |
158 | | DECLARE_printRegWithShiftExtend(true, 16, w, d); |
159 | | DECLARE_printRegWithShiftExtend(false, 16, w, d); |
160 | | DECLARE_printRegWithShiftExtend(false, 16, x, 0); |
161 | | DECLARE_printRegWithShiftExtend(true, 16, w, s); |
162 | | DECLARE_printRegWithShiftExtend(false, 16, w, s); |
163 | | DECLARE_printRegWithShiftExtend(false, 32, x, d); |
164 | | DECLARE_printRegWithShiftExtend(true, 32, w, d); |
165 | | DECLARE_printRegWithShiftExtend(false, 32, w, d); |
166 | | DECLARE_printRegWithShiftExtend(false, 32, x, 0); |
167 | | DECLARE_printRegWithShiftExtend(true, 32, w, s); |
168 | | DECLARE_printRegWithShiftExtend(false, 32, w, s); |
169 | | DECLARE_printRegWithShiftExtend(false, 8, x, s); |
170 | | DECLARE_printRegWithShiftExtend(false, 16, x, s); |
171 | | DECLARE_printRegWithShiftExtend(false, 32, x, s); |
172 | | DECLARE_printRegWithShiftExtend(false, 64, x, s); |
173 | | DECLARE_printRegWithShiftExtend(false, 128, x, 0); |
174 | | |
175 | | void printCondCode(MCInst *MI, unsigned OpNum, SStream *O); |
176 | | void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O); |
177 | | void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, |
178 | | SStream *O); |
179 | | void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O); |
180 | | void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O); |
181 | | #define DEFINE_printUImm12Offset(Scale) \ |
182 | | static inline void CONCAT(printUImm12Offset, Scale)( \ |
183 | | MCInst * MI, unsigned OpNum, SStream *O) \ |
184 | 6.91k | { \ |
185 | 6.91k | add_cs_detail(MI, \ |
186 | 6.91k | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ |
187 | 6.91k | OpNum, Scale); \ |
188 | 6.91k | printUImm12Offset(MI, OpNum, Scale, O); \ |
189 | 6.91k | } Unexecuted instantiation: AArch64Module.c:printUImm12Offset_1 Unexecuted instantiation: AArch64Module.c:printUImm12Offset_8 Unexecuted instantiation: AArch64Module.c:printUImm12Offset_2 Unexecuted instantiation: AArch64Module.c:printUImm12Offset_16 Unexecuted instantiation: AArch64Module.c:printUImm12Offset_4 AArch64InstPrinter.c:printUImm12Offset_1 Line | Count | Source | 184 | 1.42k | { \ | 185 | 1.42k | add_cs_detail(MI, \ | 186 | 1.42k | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ | 187 | 1.42k | OpNum, Scale); \ | 188 | 1.42k | printUImm12Offset(MI, OpNum, Scale, O); \ | 189 | 1.42k | } |
AArch64InstPrinter.c:printUImm12Offset_8 Line | Count | Source | 184 | 1.98k | { \ | 185 | 1.98k | add_cs_detail(MI, \ | 186 | 1.98k | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ | 187 | 1.98k | OpNum, Scale); \ | 188 | 1.98k | printUImm12Offset(MI, OpNum, Scale, O); \ | 189 | 1.98k | } |
AArch64InstPrinter.c:printUImm12Offset_2 Line | Count | Source | 184 | 1.59k | { \ | 185 | 1.59k | add_cs_detail(MI, \ | 186 | 1.59k | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ | 187 | 1.59k | OpNum, Scale); \ | 188 | 1.59k | printUImm12Offset(MI, OpNum, Scale, O); \ | 189 | 1.59k | } |
AArch64InstPrinter.c:printUImm12Offset_16 Line | Count | Source | 184 | 382 | { \ | 185 | 382 | add_cs_detail(MI, \ | 186 | 382 | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ | 187 | 382 | OpNum, Scale); \ | 188 | 382 | printUImm12Offset(MI, OpNum, Scale, O); \ | 189 | 382 | } |
AArch64InstPrinter.c:printUImm12Offset_4 Line | Count | Source | 184 | 1.52k | { \ | 185 | 1.52k | add_cs_detail(MI, \ | 186 | 1.52k | CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \ | 187 | 1.52k | OpNum, Scale); \ | 188 | 1.52k | printUImm12Offset(MI, OpNum, Scale, O); \ | 189 | 1.52k | } |
|
190 | | DEFINE_printUImm12Offset(1); |
191 | | DEFINE_printUImm12Offset(8); |
192 | | DEFINE_printUImm12Offset(2); |
193 | | DEFINE_printUImm12Offset(16); |
194 | | DEFINE_printUImm12Offset(4); |
195 | | |
196 | | void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O); |
197 | | #define DECLARE_printImmScale(Scale) \ |
198 | | void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \ |
199 | | SStream *O); |
200 | | DECLARE_printImmScale(8); |
201 | | DECLARE_printImmScale(2); |
202 | | DECLARE_printImmScale(4); |
203 | | DECLARE_printImmScale(16); |
204 | | DECLARE_printImmScale(32); |
205 | | DECLARE_printImmScale(3); |
206 | | |
207 | | #define DECLARE_printImmRangeScale(Scale, Offset) \ |
208 | | void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \ |
209 | | MCInst * MI, unsigned OpNum, SStream *O); |
210 | | DECLARE_printImmRangeScale(2, 1); |
211 | | DECLARE_printImmRangeScale(4, 3); |
212 | | |
213 | | #define DECLARE_printPrefetchOp(IsSVEPrefetch) \ |
214 | | void CONCAT(printPrefetchOp, \ |
215 | | IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O); |
216 | | DECLARE_printPrefetchOp(true); |
217 | | DECLARE_printPrefetchOp(false); |
218 | | |
219 | | void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O); |
220 | | void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O); |
221 | | void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O); |
222 | | void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, |
223 | | const char *LayoutSuffix); |
224 | | void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O); |
225 | | /// (i.e. attached to the instruction rather than the registers). |
226 | | /// Print a list of vector registers where the type suffix is implicit |
227 | | void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O); |
228 | | #define DECLARE_printTypedVectorList(NumLanes, LaneKind) \ |
229 | | void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \ |
230 | | MCInst * MI, unsigned OpNum, SStream *O); |
231 | | DECLARE_printTypedVectorList(0, b); |
232 | | DECLARE_printTypedVectorList(0, d); |
233 | | DECLARE_printTypedVectorList(0, h); |
234 | | DECLARE_printTypedVectorList(0, s); |
235 | | DECLARE_printTypedVectorList(0, q); |
236 | | DECLARE_printTypedVectorList(16, b); |
237 | | DECLARE_printTypedVectorList(1, d); |
238 | | DECLARE_printTypedVectorList(2, d); |
239 | | DECLARE_printTypedVectorList(2, s); |
240 | | DECLARE_printTypedVectorList(4, h); |
241 | | DECLARE_printTypedVectorList(4, s); |
242 | | DECLARE_printTypedVectorList(8, b); |
243 | | DECLARE_printTypedVectorList(8, h); |
244 | | DECLARE_printTypedVectorList(0, 0); |
245 | | |
246 | | #define DECLARE_printVectorIndex(Scale) \ |
247 | | void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \ |
248 | | SStream *O); |
249 | | DECLARE_printVectorIndex(1); |
250 | | DECLARE_printVectorIndex(8); |
251 | | |
252 | | void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, |
253 | | SStream *O); |
254 | | void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O); |
255 | | void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O); |
256 | | void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O); |
257 | | void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O); |
258 | | void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O); |
259 | | void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O); |
260 | | #define DECLARE_printPredicateAsCounter(EltSize) \ |
261 | | void CONCAT(printPredicateAsCounter, \ |
262 | | EltSize)(MCInst * MI, unsigned OpNum, SStream *O); |
263 | | DECLARE_printPredicateAsCounter(8); |
264 | | DECLARE_printPredicateAsCounter(64); |
265 | | DECLARE_printPredicateAsCounter(16); |
266 | | DECLARE_printPredicateAsCounter(32); |
267 | | DECLARE_printPredicateAsCounter(0); |
268 | | |
269 | | #define DECLARE_printGPRSeqPairsClassOperand(size) \ |
270 | | void CONCAT(printGPRSeqPairsClassOperand, \ |
271 | | size)(MCInst * MI, unsigned OpNum, SStream *O); |
272 | | DECLARE_printGPRSeqPairsClassOperand(32); |
273 | | DECLARE_printGPRSeqPairsClassOperand(64); |
274 | | |
275 | | #define DECLARE_printImm8OptLsl(T) \ |
276 | | void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \ |
277 | | SStream *O); |
278 | | DECLARE_printImm8OptLsl(int16_t); |
279 | | DECLARE_printImm8OptLsl(int8_t); |
280 | | DECLARE_printImm8OptLsl(int64_t); |
281 | | DECLARE_printImm8OptLsl(int32_t); |
282 | | DECLARE_printImm8OptLsl(uint16_t); |
283 | | DECLARE_printImm8OptLsl(uint8_t); |
284 | | DECLARE_printImm8OptLsl(uint64_t); |
285 | | DECLARE_printImm8OptLsl(uint32_t); |
286 | | |
287 | | #define DECLARE_printSVELogicalImm(T) \ |
288 | | void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \ |
289 | | SStream *O); |
290 | | DECLARE_printSVELogicalImm(int16_t); |
291 | | DECLARE_printSVELogicalImm(int32_t); |
292 | | DECLARE_printSVELogicalImm(int64_t); |
293 | | |
294 | | void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O); |
295 | | void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O); |
296 | | #define DECLARE_printMatrixTileVector(IsVertical) \ |
297 | | void CONCAT(printMatrixTileVector, \ |
298 | | IsVertical)(MCInst * MI, unsigned OpNum, SStream *O); |
299 | | DECLARE_printMatrixTileVector(0); |
300 | | DECLARE_printMatrixTileVector(1); |
301 | | |
302 | | void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O); |
303 | | #define DECLARE_printMatrix(EltSize) \ |
304 | | void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \ |
305 | | SStream *O); |
306 | | DECLARE_printMatrix(64); |
307 | | DECLARE_printMatrix(32); |
308 | | DECLARE_printMatrix(16); |
309 | | DECLARE_printMatrix(0); |
310 | | |
311 | | void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O); |
312 | | #define DECLARE_printSVERegOp(char) \ |
313 | | void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \ |
314 | | SStream *O); |
315 | | DECLARE_printSVERegOp(b); |
316 | | DECLARE_printSVERegOp(d); |
317 | | DECLARE_printSVERegOp(h); |
318 | | DECLARE_printSVERegOp(s); |
319 | | DECLARE_printSVERegOp(0); |
320 | | DECLARE_printSVERegOp(q); |
321 | | |
322 | | void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O); |
323 | | void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O); |
324 | | void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O); |
325 | | #define DECLARE_printZPRasFPR(Width) \ |
326 | | void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \ |
327 | | SStream *O); |
328 | | DECLARE_printZPRasFPR(8); |
329 | | DECLARE_printZPRasFPR(64); |
330 | | DECLARE_printZPRasFPR(16); |
331 | | DECLARE_printZPRasFPR(32); |
332 | | DECLARE_printZPRasFPR(128); |
333 | | |
334 | | #define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \ |
335 | | void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \ |
336 | | MCInst * MI, unsigned OpNum, SStream *O); |
337 | | DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one); |
338 | | DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one); |
339 | | DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two); |
340 | | |
341 | | #define DECLARE_printMatrixIndex(Scale) \ |
342 | | void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \ |
343 | | SStream *O); |
344 | | DECLARE_printMatrixIndex(8); |
345 | | DECLARE_printMatrixIndex(0); |
346 | | DECLARE_printMatrixIndex(1); |
347 | | |
348 | | // end namespace llvm |
349 | | |
350 | | #endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H |