/src/capstonenext/arch/ARM/ARMGenAsmWriter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ |
5 | | |
6 | | /* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ |
7 | | /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ |
8 | | |
9 | | /* Do not edit. */ |
10 | | |
11 | | /* Capstone's LLVM TableGen Backends: */ |
12 | | /* https://github.com/capstone-engine/llvm-capstone */ |
13 | | |
14 | | #include <capstone/platform.h> |
15 | | #include <assert.h> |
16 | | |
17 | | /// getMnemonic - This method is automatically generated by tablegen |
18 | | /// from the instruction set description. |
19 | | static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) |
20 | 1.45M | { |
21 | 1.45M | #ifndef CAPSTONE_DIET |
22 | 1.45M | static const char AsmStrs[] = { |
23 | 1.45M | /* 0 */ "vcx1\t\0" |
24 | 1.45M | /* 6 */ "vld20.32\t\0" |
25 | 1.45M | /* 16 */ "vst20.32\t\0" |
26 | 1.45M | /* 26 */ "vld40.32\t\0" |
27 | 1.45M | /* 36 */ "vst40.32\t\0" |
28 | 1.45M | /* 46 */ "sha1su0.32\t\0" |
29 | 1.45M | /* 58 */ "sha256su0.32\t\0" |
30 | 1.45M | /* 72 */ "vld21.32\t\0" |
31 | 1.45M | /* 82 */ "vst21.32\t\0" |
32 | 1.45M | /* 92 */ "vld41.32\t\0" |
33 | 1.45M | /* 102 */ "vst41.32\t\0" |
34 | 1.45M | /* 112 */ "sha1su1.32\t\0" |
35 | 1.45M | /* 124 */ "sha256su1.32\t\0" |
36 | 1.45M | /* 138 */ "vld42.32\t\0" |
37 | 1.45M | /* 148 */ "vst42.32\t\0" |
38 | 1.45M | /* 158 */ "sha256h2.32\t\0" |
39 | 1.45M | /* 171 */ "vld43.32\t\0" |
40 | 1.45M | /* 181 */ "vst43.32\t\0" |
41 | 1.45M | /* 191 */ "sha1c.32\t\0" |
42 | 1.45M | /* 201 */ "sha1h.32\t\0" |
43 | 1.45M | /* 211 */ "sha256h.32\t\0" |
44 | 1.45M | /* 223 */ "sha1m.32\t\0" |
45 | 1.45M | /* 233 */ "sha1p.32\t\0" |
46 | 1.45M | /* 243 */ "dlstp.32\t\0" |
47 | 1.45M | /* 253 */ "wlstp.32\t\0" |
48 | 1.45M | /* 263 */ "vcvta.s32.f32\t\0" |
49 | 1.45M | /* 278 */ "vcvtm.s32.f32\t\0" |
50 | 1.45M | /* 293 */ "vcvtn.s32.f32\t\0" |
51 | 1.45M | /* 308 */ "vcvtp.s32.f32\t\0" |
52 | 1.45M | /* 323 */ "vcvta.u32.f32\t\0" |
53 | 1.45M | /* 338 */ "vcvtm.u32.f32\t\0" |
54 | 1.45M | /* 353 */ "vcvtn.u32.f32\t\0" |
55 | 1.45M | /* 368 */ "vcvtp.u32.f32\t\0" |
56 | 1.45M | /* 383 */ "vcmla.f32\t\0" |
57 | 1.45M | /* 394 */ "vrinta.f32\t\0" |
58 | 1.45M | /* 406 */ "vcadd.f32\t\0" |
59 | 1.45M | /* 417 */ "vselge.f32\t\0" |
60 | 1.45M | /* 429 */ "vminnm.f32\t\0" |
61 | 1.45M | /* 441 */ "vmaxnm.f32\t\0" |
62 | 1.45M | /* 453 */ "vrintm.f32\t\0" |
63 | 1.45M | /* 465 */ "vrintn.f32\t\0" |
64 | 1.45M | /* 477 */ "vrintp.f32\t\0" |
65 | 1.45M | /* 489 */ "vseleq.f32\t\0" |
66 | 1.45M | /* 501 */ "vselvs.f32\t\0" |
67 | 1.45M | /* 513 */ "vselgt.f32\t\0" |
68 | 1.45M | /* 525 */ "vrintx.f32\t\0" |
69 | 1.45M | /* 537 */ "vrintz.f32\t\0" |
70 | 1.45M | /* 549 */ "ldc2\t\0" |
71 | 1.45M | /* 555 */ "mrc2\t\0" |
72 | 1.45M | /* 561 */ "mrrc2\t\0" |
73 | 1.45M | /* 568 */ "stc2\t\0" |
74 | 1.45M | /* 574 */ "cdp2\t\0" |
75 | 1.45M | /* 580 */ "mcr2\t\0" |
76 | 1.45M | /* 586 */ "mcrr2\t\0" |
77 | 1.45M | /* 593 */ "vcx2\t\0" |
78 | 1.45M | /* 599 */ "vcx3\t\0" |
79 | 1.45M | /* 605 */ "dlstp.64\t\0" |
80 | 1.45M | /* 615 */ "wlstp.64\t\0" |
81 | 1.45M | /* 625 */ "vcvta.s32.f64\t\0" |
82 | 1.45M | /* 640 */ "vcvtm.s32.f64\t\0" |
83 | 1.45M | /* 655 */ "vcvtn.s32.f64\t\0" |
84 | 1.45M | /* 670 */ "vcvtp.s32.f64\t\0" |
85 | 1.45M | /* 685 */ "vcvta.u32.f64\t\0" |
86 | 1.45M | /* 700 */ "vcvtm.u32.f64\t\0" |
87 | 1.45M | /* 715 */ "vcvtn.u32.f64\t\0" |
88 | 1.45M | /* 730 */ "vcvtp.u32.f64\t\0" |
89 | 1.45M | /* 745 */ "vrinta.f64\t\0" |
90 | 1.45M | /* 757 */ "vselge.f64\t\0" |
91 | 1.45M | /* 769 */ "vminnm.f64\t\0" |
92 | 1.45M | /* 781 */ "vmaxnm.f64\t\0" |
93 | 1.45M | /* 793 */ "vrintm.f64\t\0" |
94 | 1.45M | /* 805 */ "vrintn.f64\t\0" |
95 | 1.45M | /* 817 */ "vrintp.f64\t\0" |
96 | 1.45M | /* 829 */ "vseleq.f64\t\0" |
97 | 1.45M | /* 841 */ "vselvs.f64\t\0" |
98 | 1.45M | /* 853 */ "vselgt.f64\t\0" |
99 | 1.45M | /* 865 */ "vmull.p64\t\0" |
100 | 1.45M | /* 876 */ "vld20.16\t\0" |
101 | 1.45M | /* 886 */ "vst20.16\t\0" |
102 | 1.45M | /* 896 */ "vld40.16\t\0" |
103 | 1.45M | /* 906 */ "vst40.16\t\0" |
104 | 1.45M | /* 916 */ "vld21.16\t\0" |
105 | 1.45M | /* 926 */ "vst21.16\t\0" |
106 | 1.45M | /* 936 */ "vld41.16\t\0" |
107 | 1.45M | /* 946 */ "vst41.16\t\0" |
108 | 1.45M | /* 956 */ "vld42.16\t\0" |
109 | 1.45M | /* 966 */ "vst42.16\t\0" |
110 | 1.45M | /* 976 */ "vld43.16\t\0" |
111 | 1.45M | /* 986 */ "vst43.16\t\0" |
112 | 1.45M | /* 996 */ "dlstp.16\t\0" |
113 | 1.45M | /* 1006 */ "wlstp.16\t\0" |
114 | 1.45M | /* 1016 */ "vcvta.s32.f16\t\0" |
115 | 1.45M | /* 1031 */ "vcvtm.s32.f16\t\0" |
116 | 1.45M | /* 1046 */ "vcvtn.s32.f16\t\0" |
117 | 1.45M | /* 1061 */ "vcvtp.s32.f16\t\0" |
118 | 1.45M | /* 1076 */ "vcvta.u32.f16\t\0" |
119 | 1.45M | /* 1091 */ "vcvtm.u32.f16\t\0" |
120 | 1.45M | /* 1106 */ "vcvtn.u32.f16\t\0" |
121 | 1.45M | /* 1121 */ "vcvtp.u32.f16\t\0" |
122 | 1.45M | /* 1136 */ "vcvta.s16.f16\t\0" |
123 | 1.45M | /* 1151 */ "vcvtm.s16.f16\t\0" |
124 | 1.45M | /* 1166 */ "vcvtn.s16.f16\t\0" |
125 | 1.45M | /* 1181 */ "vcvtp.s16.f16\t\0" |
126 | 1.45M | /* 1196 */ "vcvta.u16.f16\t\0" |
127 | 1.45M | /* 1211 */ "vcvtm.u16.f16\t\0" |
128 | 1.45M | /* 1226 */ "vcvtn.u16.f16\t\0" |
129 | 1.45M | /* 1241 */ "vcvtp.u16.f16\t\0" |
130 | 1.45M | /* 1256 */ "vcmla.f16\t\0" |
131 | 1.45M | /* 1267 */ "vrinta.f16\t\0" |
132 | 1.45M | /* 1279 */ "vcadd.f16\t\0" |
133 | 1.45M | /* 1290 */ "vselge.f16\t\0" |
134 | 1.45M | /* 1302 */ "vfmal.f16\t\0" |
135 | 1.45M | /* 1313 */ "vfmsl.f16\t\0" |
136 | 1.45M | /* 1324 */ "vminnm.f16\t\0" |
137 | 1.45M | /* 1336 */ "vmaxnm.f16\t\0" |
138 | 1.45M | /* 1348 */ "vrintm.f16\t\0" |
139 | 1.45M | /* 1360 */ "vrintn.f16\t\0" |
140 | 1.45M | /* 1372 */ "vrintp.f16\t\0" |
141 | 1.45M | /* 1384 */ "vseleq.f16\t\0" |
142 | 1.45M | /* 1396 */ "vins.f16\t\0" |
143 | 1.45M | /* 1406 */ "vselvs.f16\t\0" |
144 | 1.45M | /* 1418 */ "vselgt.f16\t\0" |
145 | 1.45M | /* 1430 */ "vrintx.f16\t\0" |
146 | 1.45M | /* 1442 */ "vmovx.f16\t\0" |
147 | 1.45M | /* 1453 */ "vrintz.f16\t\0" |
148 | 1.45M | /* 1465 */ "vmmla.bf16\t\0" |
149 | 1.45M | /* 1477 */ "vfmab.bf16\t\0" |
150 | 1.45M | /* 1489 */ "vfmat.bf16\t\0" |
151 | 1.45M | /* 1501 */ "vdot.bf16\t\0" |
152 | 1.45M | /* 1512 */ "vld20.8\t\0" |
153 | 1.45M | /* 1521 */ "vst20.8\t\0" |
154 | 1.45M | /* 1530 */ "vld40.8\t\0" |
155 | 1.45M | /* 1539 */ "vst40.8\t\0" |
156 | 1.45M | /* 1548 */ "vld21.8\t\0" |
157 | 1.45M | /* 1557 */ "vst21.8\t\0" |
158 | 1.45M | /* 1566 */ "vld41.8\t\0" |
159 | 1.45M | /* 1575 */ "vst41.8\t\0" |
160 | 1.45M | /* 1584 */ "vld42.8\t\0" |
161 | 1.45M | /* 1593 */ "vst42.8\t\0" |
162 | 1.45M | /* 1602 */ "vld43.8\t\0" |
163 | 1.45M | /* 1611 */ "vst43.8\t\0" |
164 | 1.45M | /* 1620 */ "aesimc.8\t\0" |
165 | 1.45M | /* 1630 */ "aesmc.8\t\0" |
166 | 1.45M | /* 1639 */ "aesd.8\t\0" |
167 | 1.45M | /* 1647 */ "aese.8\t\0" |
168 | 1.45M | /* 1655 */ "dlstp.8\t\0" |
169 | 1.45M | /* 1664 */ "wlstp.8\t\0" |
170 | 1.45M | /* 1673 */ "vusmmla.s8\t\0" |
171 | 1.45M | /* 1685 */ "vsmmla.s8\t\0" |
172 | 1.45M | /* 1696 */ "vusdot.s8\t\0" |
173 | 1.45M | /* 1707 */ "vsdot.s8\t\0" |
174 | 1.45M | /* 1717 */ "vummla.u8\t\0" |
175 | 1.45M | /* 1728 */ "vsudot.u8\t\0" |
176 | 1.45M | /* 1739 */ "vudot.u8\t\0" |
177 | 1.45M | /* 1749 */ "vcx1a\t\0" |
178 | 1.45M | /* 1756 */ "vcx2a\t\0" |
179 | 1.45M | /* 1763 */ "vcx3a\t\0" |
180 | 1.45M | /* 1770 */ "rfeda\t\0" |
181 | 1.45M | /* 1777 */ "rfeia\t\0" |
182 | 1.45M | /* 1784 */ "crc32b\t\0" |
183 | 1.45M | /* 1792 */ "crc32cb\t\0" |
184 | 1.45M | /* 1801 */ "rfedb\t\0" |
185 | 1.45M | /* 1808 */ "rfeib\t\0" |
186 | 1.45M | /* 1815 */ "dmb\t\0" |
187 | 1.45M | /* 1820 */ "dsb\t\0" |
188 | 1.45M | /* 1825 */ "isb\t\0" |
189 | 1.45M | /* 1830 */ "tsb\t\0" |
190 | 1.45M | /* 1835 */ "csinc\t\0" |
191 | 1.45M | /* 1842 */ "hvc\t\0" |
192 | 1.45M | /* 1847 */ "cx1d\t\0" |
193 | 1.45M | /* 1853 */ "cx2d\t\0" |
194 | 1.45M | /* 1859 */ "cx3d\t\0" |
195 | 1.45M | /* 1865 */ "pld\t\0" |
196 | 1.45M | /* 1870 */ "setend\t\0" |
197 | 1.45M | /* 1878 */ "le\t\0" |
198 | 1.45M | /* 1882 */ "udf\t\0" |
199 | 1.45M | /* 1887 */ "csneg\t\0" |
200 | 1.45M | /* 1894 */ "crc32h\t\0" |
201 | 1.45M | /* 1902 */ "crc32ch\t\0" |
202 | 1.45M | /* 1911 */ "pli\t\0" |
203 | 1.45M | /* 1916 */ "bti\t\0" |
204 | 1.45M | /* 1921 */ "ldc2l\t\0" |
205 | 1.45M | /* 1928 */ "stc2l\t\0" |
206 | 1.45M | /* 1935 */ "bl\t\0" |
207 | 1.45M | /* 1939 */ "bfcsel\t\0" |
208 | 1.45M | /* 1947 */ "setpan\t\0" |
209 | 1.45M | /* 1955 */ "letp\t\0" |
210 | 1.45M | /* 1961 */ "dls\t\0" |
211 | 1.45M | /* 1966 */ "wls\t\0" |
212 | 1.45M | /* 1971 */ "cps\t\0" |
213 | 1.45M | /* 1976 */ "movs\t\0" |
214 | 1.45M | /* 1982 */ "hlt\t\0" |
215 | 1.45M | /* 1987 */ "bkpt\t\0" |
216 | 1.45M | /* 1993 */ "csinv\t\0" |
217 | 1.45M | /* 2000 */ "hvc.w\t\0" |
218 | 1.45M | /* 2007 */ "udf.w\t\0" |
219 | 1.45M | /* 2014 */ "crc32w\t\0" |
220 | 1.45M | /* 2022 */ "crc32cw\t\0" |
221 | 1.45M | /* 2031 */ "pldw\t\0" |
222 | 1.45M | /* 2037 */ "bx\t\0" |
223 | 1.45M | /* 2041 */ "blx\t\0" |
224 | 1.45M | /* 2046 */ "cbz\t\0" |
225 | 1.45M | /* 2051 */ "cbnz\t\0" |
226 | 1.45M | /* 2057 */ "srsda\tsp!, \0" |
227 | 1.45M | /* 2069 */ "srsia\tsp!, \0" |
228 | 1.45M | /* 2081 */ "srsdb\tsp!, \0" |
229 | 1.45M | /* 2093 */ "srsib\tsp!, \0" |
230 | 1.45M | /* 2105 */ "srsda\tsp, \0" |
231 | 1.45M | /* 2116 */ "srsia\tsp, \0" |
232 | 1.45M | /* 2127 */ "srsdb\tsp, \0" |
233 | 1.45M | /* 2138 */ "srsib\tsp, \0" |
234 | 1.45M | /* 2149 */ "# XRay Function Patchable RET.\0" |
235 | 1.45M | /* 2180 */ "# XRay Typed Event Log.\0" |
236 | 1.45M | /* 2204 */ "# XRay Custom Event Log.\0" |
237 | 1.45M | /* 2229 */ "# XRay Function Enter.\0" |
238 | 1.45M | /* 2252 */ "# XRay Tail Call Exit.\0" |
239 | 1.45M | /* 2275 */ "# XRay Function Exit.\0" |
240 | 1.45M | /* 2297 */ "__brkdiv0\0" |
241 | 1.45M | /* 2307 */ "vld1\0" |
242 | 1.45M | /* 2312 */ "dcps1\0" |
243 | 1.45M | /* 2318 */ "vst1\0" |
244 | 1.45M | /* 2323 */ "vcx1\0" |
245 | 1.45M | /* 2328 */ "vrev32\0" |
246 | 1.45M | /* 2335 */ "ldc2\0" |
247 | 1.45M | /* 2340 */ "mrc2\0" |
248 | 1.45M | /* 2345 */ "mrrc2\0" |
249 | 1.45M | /* 2351 */ "stc2\0" |
250 | 1.45M | /* 2356 */ "vld2\0" |
251 | 1.45M | /* 2361 */ "cdp2\0" |
252 | 1.45M | /* 2366 */ "mcr2\0" |
253 | 1.45M | /* 2371 */ "mcrr2\0" |
254 | 1.45M | /* 2377 */ "dcps2\0" |
255 | 1.45M | /* 2383 */ "vst2\0" |
256 | 1.45M | /* 2388 */ "vcx2\0" |
257 | 1.45M | /* 2393 */ "vld3\0" |
258 | 1.45M | /* 2398 */ "dcps3\0" |
259 | 1.45M | /* 2404 */ "vst3\0" |
260 | 1.45M | /* 2409 */ "vcx3\0" |
261 | 1.45M | /* 2414 */ "vrev64\0" |
262 | 1.45M | /* 2421 */ "vld4\0" |
263 | 1.45M | /* 2426 */ "vst4\0" |
264 | 1.45M | /* 2431 */ "sxtab16\0" |
265 | 1.45M | /* 2439 */ "uxtab16\0" |
266 | 1.45M | /* 2447 */ "sxtb16\0" |
267 | 1.45M | /* 2454 */ "uxtb16\0" |
268 | 1.45M | /* 2461 */ "shsub16\0" |
269 | 1.45M | /* 2469 */ "uhsub16\0" |
270 | 1.45M | /* 2477 */ "uqsub16\0" |
271 | 1.45M | /* 2485 */ "ssub16\0" |
272 | 1.45M | /* 2492 */ "usub16\0" |
273 | 1.45M | /* 2499 */ "shadd16\0" |
274 | 1.45M | /* 2507 */ "uhadd16\0" |
275 | 1.45M | /* 2515 */ "uqadd16\0" |
276 | 1.45M | /* 2523 */ "sadd16\0" |
277 | 1.45M | /* 2530 */ "uadd16\0" |
278 | 1.45M | /* 2537 */ "ssat16\0" |
279 | 1.45M | /* 2544 */ "usat16\0" |
280 | 1.45M | /* 2551 */ "vrev16\0" |
281 | 1.45M | /* 2558 */ "usada8\0" |
282 | 1.45M | /* 2565 */ "shsub8\0" |
283 | 1.45M | /* 2572 */ "uhsub8\0" |
284 | 1.45M | /* 2579 */ "uqsub8\0" |
285 | 1.45M | /* 2586 */ "ssub8\0" |
286 | 1.45M | /* 2592 */ "usub8\0" |
287 | 1.45M | /* 2598 */ "usad8\0" |
288 | 1.45M | /* 2604 */ "shadd8\0" |
289 | 1.45M | /* 2611 */ "uhadd8\0" |
290 | 1.45M | /* 2618 */ "uqadd8\0" |
291 | 1.45M | /* 2625 */ "sadd8\0" |
292 | 1.45M | /* 2631 */ "uadd8\0" |
293 | 1.45M | /* 2637 */ "LIFETIME_END\0" |
294 | 1.45M | /* 2650 */ "PSEUDO_PROBE\0" |
295 | 1.45M | /* 2663 */ "BUNDLE\0" |
296 | 1.45M | /* 2670 */ "DBG_VALUE\0" |
297 | 1.45M | /* 2680 */ "DBG_INSTR_REF\0" |
298 | 1.45M | /* 2694 */ "DBG_PHI\0" |
299 | 1.45M | /* 2702 */ "DBG_LABEL\0" |
300 | 1.45M | /* 2712 */ "LIFETIME_START\0" |
301 | 1.45M | /* 2727 */ "DBG_VALUE_LIST\0" |
302 | 1.45M | /* 2742 */ "vcx1a\0" |
303 | 1.45M | /* 2748 */ "vcx2a\0" |
304 | 1.45M | /* 2754 */ "vcx3a\0" |
305 | 1.45M | /* 2760 */ "vaba\0" |
306 | 1.45M | /* 2765 */ "cx1da\0" |
307 | 1.45M | /* 2771 */ "cx2da\0" |
308 | 1.45M | /* 2777 */ "cx3da\0" |
309 | 1.45M | /* 2783 */ "lda\0" |
310 | 1.45M | /* 2787 */ "ldmda\0" |
311 | 1.45M | /* 2793 */ "stmda\0" |
312 | 1.45M | /* 2799 */ "vrmlaldavha\0" |
313 | 1.45M | /* 2811 */ "vrmlsldavha\0" |
314 | 1.45M | /* 2823 */ "rfeia\0" |
315 | 1.45M | /* 2829 */ "vldmia\0" |
316 | 1.45M | /* 2836 */ "vstmia\0" |
317 | 1.45M | /* 2843 */ "srsia\0" |
318 | 1.45M | /* 2849 */ "vcmla\0" |
319 | 1.45M | /* 2855 */ "smmla\0" |
320 | 1.45M | /* 2861 */ "vnmla\0" |
321 | 1.45M | /* 2867 */ "vmla\0" |
322 | 1.45M | /* 2872 */ "vfma\0" |
323 | 1.45M | /* 2877 */ "vfnma\0" |
324 | 1.45M | /* 2883 */ "vminnma\0" |
325 | 1.45M | /* 2891 */ "vmaxnma\0" |
326 | 1.45M | /* 2899 */ "vmina\0" |
327 | 1.45M | /* 2905 */ "vrsra\0" |
328 | 1.45M | /* 2911 */ "vsra\0" |
329 | 1.45M | /* 2916 */ "vrinta\0" |
330 | 1.45M | /* 2923 */ "tta\0" |
331 | 1.45M | /* 2927 */ "vcvta\0" |
332 | 1.45M | /* 2933 */ "vmladava\0" |
333 | 1.45M | /* 2942 */ "vmlaldava\0" |
334 | 1.45M | /* 2952 */ "vmlsldava\0" |
335 | 1.45M | /* 2962 */ "vmlsdava\0" |
336 | 1.45M | /* 2971 */ "vaddva\0" |
337 | 1.45M | /* 2978 */ "vaddlva\0" |
338 | 1.45M | /* 2986 */ "vmaxa\0" |
339 | 1.45M | /* 2992 */ "ldab\0" |
340 | 1.45M | /* 2997 */ "sxtab\0" |
341 | 1.45M | /* 3003 */ "uxtab\0" |
342 | 1.45M | /* 3009 */ "smlabb\0" |
343 | 1.45M | /* 3016 */ "smlalbb\0" |
344 | 1.45M | /* 3024 */ "smulbb\0" |
345 | 1.45M | /* 3031 */ "tbb\0" |
346 | 1.45M | /* 3035 */ "rfedb\0" |
347 | 1.45M | /* 3041 */ "vldmdb\0" |
348 | 1.45M | /* 3048 */ "vstmdb\0" |
349 | 1.45M | /* 3055 */ "srsdb\0" |
350 | 1.45M | /* 3061 */ "ldmib\0" |
351 | 1.45M | /* 3067 */ "stmib\0" |
352 | 1.45M | /* 3073 */ "vshllb\0" |
353 | 1.45M | /* 3080 */ "vqdmullb\0" |
354 | 1.45M | /* 3089 */ "vmullb\0" |
355 | 1.45M | /* 3096 */ "stlb\0" |
356 | 1.45M | /* 3101 */ "vmovlb\0" |
357 | 1.45M | /* 3108 */ "dmb\0" |
358 | 1.45M | /* 3112 */ "vqshrnb\0" |
359 | 1.45M | /* 3120 */ "vqrshrnb\0" |
360 | 1.45M | /* 3129 */ "vrshrnb\0" |
361 | 1.45M | /* 3137 */ "vshrnb\0" |
362 | 1.45M | /* 3144 */ "vqshrunb\0" |
363 | 1.45M | /* 3153 */ "vqrshrunb\0" |
364 | 1.45M | /* 3163 */ "vqmovunb\0" |
365 | 1.45M | /* 3172 */ "vqmovnb\0" |
366 | 1.45M | /* 3180 */ "vmovnb\0" |
367 | 1.45M | /* 3187 */ "swpb\0" |
368 | 1.45M | /* 3192 */ "vldrb\0" |
369 | 1.45M | /* 3198 */ "vstrb\0" |
370 | 1.45M | /* 3204 */ "dsb\0" |
371 | 1.45M | /* 3208 */ "isb\0" |
372 | 1.45M | /* 3212 */ "ldrsb\0" |
373 | 1.45M | /* 3218 */ "tsb\0" |
374 | 1.45M | /* 3222 */ "smlatb\0" |
375 | 1.45M | /* 3229 */ "pkhtb\0" |
376 | 1.45M | /* 3235 */ "smlaltb\0" |
377 | 1.45M | /* 3243 */ "smultb\0" |
378 | 1.45M | /* 3250 */ "vcvtb\0" |
379 | 1.45M | /* 3256 */ "sxtb\0" |
380 | 1.45M | /* 3261 */ "uxtb\0" |
381 | 1.45M | /* 3266 */ "qdsub\0" |
382 | 1.45M | /* 3272 */ "vhsub\0" |
383 | 1.45M | /* 3278 */ "vqsub\0" |
384 | 1.45M | /* 3284 */ "vsub\0" |
385 | 1.45M | /* 3289 */ "smlawb\0" |
386 | 1.45M | /* 3296 */ "smulwb\0" |
387 | 1.45M | /* 3303 */ "ldaexb\0" |
388 | 1.45M | /* 3310 */ "stlexb\0" |
389 | 1.45M | /* 3317 */ "ldrexb\0" |
390 | 1.45M | /* 3324 */ "strexb\0" |
391 | 1.45M | /* 3331 */ "vsbc\0" |
392 | 1.45M | /* 3336 */ "vadc\0" |
393 | 1.45M | /* 3341 */ "ldc\0" |
394 | 1.45M | /* 3345 */ "bfc\0" |
395 | 1.45M | /* 3349 */ "vbic\0" |
396 | 1.45M | /* 3354 */ "vshlc\0" |
397 | 1.45M | /* 3360 */ "smc\0" |
398 | 1.45M | /* 3364 */ "mrc\0" |
399 | 1.45M | /* 3368 */ "mrrc\0" |
400 | 1.45M | /* 3373 */ "rsc\0" |
401 | 1.45M | /* 3377 */ "stc\0" |
402 | 1.45M | /* 3381 */ "svc\0" |
403 | 1.45M | /* 3385 */ "smlad\0" |
404 | 1.45M | /* 3391 */ "smuad\0" |
405 | 1.45M | /* 3397 */ "vabd\0" |
406 | 1.45M | /* 3402 */ "vhcadd\0" |
407 | 1.45M | /* 3409 */ "vcadd\0" |
408 | 1.45M | /* 3415 */ "qdadd\0" |
409 | 1.45M | /* 3421 */ "vrhadd\0" |
410 | 1.45M | /* 3428 */ "vhadd\0" |
411 | 1.45M | /* 3434 */ "vpadd\0" |
412 | 1.45M | /* 3440 */ "vqadd\0" |
413 | 1.45M | /* 3446 */ "vadd\0" |
414 | 1.45M | /* 3451 */ "smlald\0" |
415 | 1.45M | /* 3458 */ "pld\0" |
416 | 1.45M | /* 3462 */ "smlsld\0" |
417 | 1.45M | /* 3469 */ "vand\0" |
418 | 1.45M | /* 3474 */ "vldrd\0" |
419 | 1.45M | /* 3480 */ "vstrd\0" |
420 | 1.45M | /* 3486 */ "smlsd\0" |
421 | 1.45M | /* 3492 */ "smusd\0" |
422 | 1.45M | /* 3498 */ "ldaexd\0" |
423 | 1.45M | /* 3505 */ "stlexd\0" |
424 | 1.45M | /* 3512 */ "ldrexd\0" |
425 | 1.45M | /* 3519 */ "strexd\0" |
426 | 1.45M | /* 3526 */ "vacge\0" |
427 | 1.45M | /* 3532 */ "vcge\0" |
428 | 1.45M | /* 3537 */ "vcle\0" |
429 | 1.45M | /* 3542 */ "vrecpe\0" |
430 | 1.45M | /* 3549 */ "vcmpe\0" |
431 | 1.45M | /* 3555 */ "vrsqrte\0" |
432 | 1.45M | /* 3563 */ "bf\0" |
433 | 1.45M | /* 3566 */ "vbif\0" |
434 | 1.45M | /* 3571 */ "dbg\0" |
435 | 1.45M | /* 3575 */ "pacg\0" |
436 | 1.45M | /* 3580 */ "vqneg\0" |
437 | 1.45M | /* 3586 */ "vneg\0" |
438 | 1.45M | /* 3591 */ "sg\0" |
439 | 1.45M | /* 3594 */ "autg\0" |
440 | 1.45M | /* 3599 */ "ldah\0" |
441 | 1.45M | /* 3604 */ "vqdmlah\0" |
442 | 1.45M | /* 3612 */ "vqrdmlah\0" |
443 | 1.45M | /* 3621 */ "sxtah\0" |
444 | 1.45M | /* 3627 */ "uxtah\0" |
445 | 1.45M | /* 3633 */ "tbh\0" |
446 | 1.45M | /* 3637 */ "vqdmladh\0" |
447 | 1.45M | /* 3646 */ "vqrdmladh\0" |
448 | 1.45M | /* 3656 */ "vqdmlsdh\0" |
449 | 1.45M | /* 3665 */ "vqrdmlsdh\0" |
450 | 1.45M | /* 3675 */ "stlh\0" |
451 | 1.45M | /* 3680 */ "vqdmulh\0" |
452 | 1.45M | /* 3688 */ "vqrdmulh\0" |
453 | 1.45M | /* 3697 */ "vrmulh\0" |
454 | 1.45M | /* 3704 */ "vmulh\0" |
455 | 1.45M | /* 3710 */ "vldrh\0" |
456 | 1.45M | /* 3716 */ "vstrh\0" |
457 | 1.45M | /* 3722 */ "vqdmlash\0" |
458 | 1.45M | /* 3731 */ "vqrdmlash\0" |
459 | 1.45M | /* 3741 */ "vqrdmlsh\0" |
460 | 1.45M | /* 3750 */ "ldrsh\0" |
461 | 1.45M | /* 3756 */ "push\0" |
462 | 1.45M | /* 3761 */ "revsh\0" |
463 | 1.45M | /* 3767 */ "sxth\0" |
464 | 1.45M | /* 3772 */ "uxth\0" |
465 | 1.45M | /* 3777 */ "vrmlaldavh\0" |
466 | 1.45M | /* 3788 */ "vrmlsldavh\0" |
467 | 1.45M | /* 3799 */ "ldaexh\0" |
468 | 1.45M | /* 3806 */ "stlexh\0" |
469 | 1.45M | /* 3813 */ "ldrexh\0" |
470 | 1.45M | /* 3820 */ "strexh\0" |
471 | 1.45M | /* 3827 */ "vsbci\0" |
472 | 1.45M | /* 3833 */ "vadci\0" |
473 | 1.45M | /* 3839 */ "bfi\0" |
474 | 1.45M | /* 3843 */ "pli\0" |
475 | 1.45M | /* 3847 */ "vsli\0" |
476 | 1.45M | /* 3852 */ "vsri\0" |
477 | 1.45M | /* 3857 */ "bxj\0" |
478 | 1.45M | /* 3861 */ "ldc2l\0" |
479 | 1.45M | /* 3867 */ "stc2l\0" |
480 | 1.45M | /* 3873 */ "umaal\0" |
481 | 1.45M | /* 3879 */ "vabal\0" |
482 | 1.45M | /* 3885 */ "vpadal\0" |
483 | 1.45M | /* 3892 */ "vqdmlal\0" |
484 | 1.45M | /* 3900 */ "smlal\0" |
485 | 1.45M | /* 3906 */ "umlal\0" |
486 | 1.45M | /* 3912 */ "vmlal\0" |
487 | 1.45M | /* 3918 */ "vtbl\0" |
488 | 1.45M | /* 3923 */ "vsubl\0" |
489 | 1.45M | /* 3929 */ "ldcl\0" |
490 | 1.45M | /* 3934 */ "stcl\0" |
491 | 1.45M | /* 3939 */ "vabdl\0" |
492 | 1.45M | /* 3945 */ "vpaddl\0" |
493 | 1.45M | /* 3952 */ "vaddl\0" |
494 | 1.45M | /* 3958 */ "vpsel\0" |
495 | 1.45M | /* 3964 */ "bfl\0" |
496 | 1.45M | /* 3968 */ "sqshl\0" |
497 | 1.45M | /* 3974 */ "uqshl\0" |
498 | 1.45M | /* 3980 */ "vqshl\0" |
499 | 1.45M | /* 3986 */ "uqrshl\0" |
500 | 1.45M | /* 3993 */ "vqrshl\0" |
501 | 1.45M | /* 4000 */ "vrshl\0" |
502 | 1.45M | /* 4006 */ "vshl\0" |
503 | 1.45M | /* 4011 */ "# FEntry call\0" |
504 | 1.45M | /* 4025 */ "sqshll\0" |
505 | 1.45M | /* 4032 */ "uqshll\0" |
506 | 1.45M | /* 4039 */ "uqrshll\0" |
507 | 1.45M | /* 4047 */ "vshll\0" |
508 | 1.45M | /* 4053 */ "lsll\0" |
509 | 1.45M | /* 4058 */ "vqdmull\0" |
510 | 1.45M | /* 4066 */ "smull\0" |
511 | 1.45M | /* 4072 */ "umull\0" |
512 | 1.45M | /* 4078 */ "vmull\0" |
513 | 1.45M | /* 4084 */ "sqrshrl\0" |
514 | 1.45M | /* 4092 */ "srshrl\0" |
515 | 1.45M | /* 4099 */ "urshrl\0" |
516 | 1.45M | /* 4106 */ "asrl\0" |
517 | 1.45M | /* 4111 */ "lsrl\0" |
518 | 1.45M | /* 4116 */ "vbsl\0" |
519 | 1.45M | /* 4121 */ "vqdmlsl\0" |
520 | 1.45M | /* 4129 */ "vmlsl\0" |
521 | 1.45M | /* 4135 */ "stl\0" |
522 | 1.45M | /* 4139 */ "vcmul\0" |
523 | 1.45M | /* 4145 */ "smmul\0" |
524 | 1.45M | /* 4151 */ "vnmul\0" |
525 | 1.45M | /* 4157 */ "vmul\0" |
526 | 1.45M | /* 4162 */ "vmovl\0" |
527 | 1.45M | /* 4168 */ "vlldm\0" |
528 | 1.45M | /* 4174 */ "vminnm\0" |
529 | 1.45M | /* 4181 */ "vmaxnm\0" |
530 | 1.45M | /* 4188 */ "vscclrm\0" |
531 | 1.45M | /* 4196 */ "vrintm\0" |
532 | 1.45M | /* 4203 */ "vlstm\0" |
533 | 1.45M | /* 4209 */ "vcvtm\0" |
534 | 1.45M | /* 4215 */ "vrsubhn\0" |
535 | 1.45M | /* 4223 */ "vsubhn\0" |
536 | 1.45M | /* 4230 */ "vraddhn\0" |
537 | 1.45M | /* 4238 */ "vaddhn\0" |
538 | 1.45M | /* 4245 */ "vpmin\0" |
539 | 1.45M | /* 4251 */ "vmin\0" |
540 | 1.45M | /* 4256 */ "cmn\0" |
541 | 1.45M | /* 4260 */ "vqshrn\0" |
542 | 1.45M | /* 4267 */ "vqrshrn\0" |
543 | 1.45M | /* 4275 */ "vrshrn\0" |
544 | 1.45M | /* 4282 */ "vshrn\0" |
545 | 1.45M | /* 4288 */ "vorn\0" |
546 | 1.45M | /* 4293 */ "vtrn\0" |
547 | 1.45M | /* 4298 */ "vrintn\0" |
548 | 1.45M | /* 4305 */ "vcvtn\0" |
549 | 1.45M | /* 4311 */ "vqshrun\0" |
550 | 1.45M | /* 4319 */ "vqrshrun\0" |
551 | 1.45M | /* 4328 */ "vqmovun\0" |
552 | 1.45M | /* 4336 */ "vmvn\0" |
553 | 1.45M | /* 4341 */ "vqmovn\0" |
554 | 1.45M | /* 4348 */ "vmovn\0" |
555 | 1.45M | /* 4354 */ "trap\0" |
556 | 1.45M | /* 4359 */ "cdp\0" |
557 | 1.45M | /* 4363 */ "vzip\0" |
558 | 1.45M | /* 4368 */ "vcmp\0" |
559 | 1.45M | /* 4373 */ "pop\0" |
560 | 1.45M | /* 4377 */ "pac\tr12, lr, sp\0" |
561 | 1.45M | /* 4393 */ "pacbti\tr12, lr, sp\0" |
562 | 1.45M | /* 4412 */ "aut\tr12, lr, sp\0" |
563 | 1.45M | /* 4428 */ "lctp\0" |
564 | 1.45M | /* 4433 */ "vctp\0" |
565 | 1.45M | /* 4438 */ "vrintp\0" |
566 | 1.45M | /* 4445 */ "vcvtp\0" |
567 | 1.45M | /* 4451 */ "vddup\0" |
568 | 1.45M | /* 4457 */ "vidup\0" |
569 | 1.45M | /* 4463 */ "vdup\0" |
570 | 1.45M | /* 4468 */ "vdwdup\0" |
571 | 1.45M | /* 4475 */ "viwdup\0" |
572 | 1.45M | /* 4482 */ "vswp\0" |
573 | 1.45M | /* 4487 */ "vuzp\0" |
574 | 1.45M | /* 4492 */ "vceq\0" |
575 | 1.45M | /* 4497 */ "teq\0" |
576 | 1.45M | /* 4501 */ "smmlar\0" |
577 | 1.45M | /* 4508 */ "mcr\0" |
578 | 1.45M | /* 4512 */ "adr\0" |
579 | 1.45M | /* 4516 */ "vldr\0" |
580 | 1.45M | /* 4521 */ "sqrshr\0" |
581 | 1.45M | /* 4528 */ "srshr\0" |
582 | 1.45M | /* 4534 */ "urshr\0" |
583 | 1.45M | /* 4540 */ "vrshr\0" |
584 | 1.45M | /* 4546 */ "vshr\0" |
585 | 1.45M | /* 4551 */ "smmulr\0" |
586 | 1.45M | /* 4558 */ "veor\0" |
587 | 1.45M | /* 4563 */ "ror\0" |
588 | 1.45M | /* 4567 */ "mcrr\0" |
589 | 1.45M | /* 4572 */ "vorr\0" |
590 | 1.45M | /* 4577 */ "asr\0" |
591 | 1.45M | /* 4581 */ "smmlsr\0" |
592 | 1.45M | /* 4588 */ "vmsr\0" |
593 | 1.45M | /* 4593 */ "vbrsr\0" |
594 | 1.45M | /* 4599 */ "vrintr\0" |
595 | 1.45M | /* 4606 */ "vstr\0" |
596 | 1.45M | /* 4611 */ "vcvtr\0" |
597 | 1.45M | /* 4617 */ "vmlas\0" |
598 | 1.45M | /* 4623 */ "vfmas\0" |
599 | 1.45M | /* 4629 */ "vqabs\0" |
600 | 1.45M | /* 4635 */ "vabs\0" |
601 | 1.45M | /* 4640 */ "subs\0" |
602 | 1.45M | /* 4645 */ "vcls\0" |
603 | 1.45M | /* 4650 */ "smmls\0" |
604 | 1.45M | /* 4656 */ "vnmls\0" |
605 | 1.45M | /* 4662 */ "vmls\0" |
606 | 1.45M | /* 4667 */ "vfms\0" |
607 | 1.45M | /* 4672 */ "vfnms\0" |
608 | 1.45M | /* 4678 */ "bxns\0" |
609 | 1.45M | /* 4683 */ "blxns\0" |
610 | 1.45M | /* 4689 */ "vrecps\0" |
611 | 1.45M | /* 4696 */ "vmrs\0" |
612 | 1.45M | /* 4701 */ "asrs\0" |
613 | 1.45M | /* 4706 */ "lsrs\0" |
614 | 1.45M | /* 4711 */ "vrsqrts\0" |
615 | 1.45M | /* 4719 */ "movs\0" |
616 | 1.45M | /* 4724 */ "ssat\0" |
617 | 1.45M | /* 4729 */ "usat\0" |
618 | 1.45M | /* 4734 */ "ttat\0" |
619 | 1.45M | /* 4739 */ "smlabt\0" |
620 | 1.45M | /* 4746 */ "pkhbt\0" |
621 | 1.45M | /* 4752 */ "smlalbt\0" |
622 | 1.45M | /* 4760 */ "smulbt\0" |
623 | 1.45M | /* 4767 */ "ldrbt\0" |
624 | 1.45M | /* 4773 */ "strbt\0" |
625 | 1.45M | /* 4779 */ "ldrsbt\0" |
626 | 1.45M | /* 4786 */ "eret\0" |
627 | 1.45M | /* 4791 */ "vacgt\0" |
628 | 1.45M | /* 4797 */ "vcgt\0" |
629 | 1.45M | /* 4802 */ "ldrht\0" |
630 | 1.45M | /* 4808 */ "strht\0" |
631 | 1.45M | /* 4814 */ "ldrsht\0" |
632 | 1.45M | /* 4821 */ "rbit\0" |
633 | 1.45M | /* 4826 */ "vbit\0" |
634 | 1.45M | /* 4831 */ "vclt\0" |
635 | 1.45M | /* 4836 */ "vshllt\0" |
636 | 1.45M | /* 4843 */ "vqdmullt\0" |
637 | 1.45M | /* 4852 */ "vmullt\0" |
638 | 1.45M | /* 4859 */ "vmovlt\0" |
639 | 1.45M | /* 4866 */ "vcnt\0" |
640 | 1.45M | /* 4871 */ "hint\0" |
641 | 1.45M | /* 4876 */ "vqshrnt\0" |
642 | 1.45M | /* 4884 */ "vqrshrnt\0" |
643 | 1.45M | /* 4893 */ "vrshrnt\0" |
644 | 1.45M | /* 4901 */ "vshrnt\0" |
645 | 1.45M | /* 4908 */ "vqshrunt\0" |
646 | 1.45M | /* 4917 */ "vqrshrunt\0" |
647 | 1.45M | /* 4927 */ "vqmovunt\0" |
648 | 1.45M | /* 4936 */ "vqmovnt\0" |
649 | 1.45M | /* 4944 */ "vmovnt\0" |
650 | 1.45M | /* 4951 */ "vpnot\0" |
651 | 1.45M | /* 4957 */ "vpt\0" |
652 | 1.45M | /* 4961 */ "ldrt\0" |
653 | 1.45M | /* 4966 */ "vsqrt\0" |
654 | 1.45M | /* 4972 */ "strt\0" |
655 | 1.45M | /* 4977 */ "vpst\0" |
656 | 1.45M | /* 4982 */ "vtst\0" |
657 | 1.45M | /* 4987 */ "smlatt\0" |
658 | 1.45M | /* 4994 */ "smlaltt\0" |
659 | 1.45M | /* 5002 */ "smultt\0" |
660 | 1.45M | /* 5009 */ "ttt\0" |
661 | 1.45M | /* 5013 */ "vcvtt\0" |
662 | 1.45M | /* 5019 */ "bxaut\0" |
663 | 1.45M | /* 5025 */ "vjcvt\0" |
664 | 1.45M | /* 5031 */ "vcvt\0" |
665 | 1.45M | /* 5036 */ "movt\0" |
666 | 1.45M | /* 5041 */ "smlawt\0" |
667 | 1.45M | /* 5048 */ "smulwt\0" |
668 | 1.45M | /* 5055 */ "vext\0" |
669 | 1.45M | /* 5060 */ "vqshlu\0" |
670 | 1.45M | /* 5067 */ "vabav\0" |
671 | 1.45M | /* 5073 */ "vmladav\0" |
672 | 1.45M | /* 5081 */ "vmlaldav\0" |
673 | 1.45M | /* 5090 */ "vmlsldav\0" |
674 | 1.45M | /* 5099 */ "vmlsdav\0" |
675 | 1.45M | /* 5107 */ "vminnmav\0" |
676 | 1.45M | /* 5116 */ "vmaxnmav\0" |
677 | 1.45M | /* 5125 */ "vminav\0" |
678 | 1.45M | /* 5132 */ "vmaxav\0" |
679 | 1.45M | /* 5139 */ "vaddv\0" |
680 | 1.45M | /* 5145 */ "rev\0" |
681 | 1.45M | /* 5149 */ "sdiv\0" |
682 | 1.45M | /* 5154 */ "udiv\0" |
683 | 1.45M | /* 5159 */ "vdiv\0" |
684 | 1.45M | /* 5164 */ "vaddlv\0" |
685 | 1.45M | /* 5171 */ "vminnmv\0" |
686 | 1.45M | /* 5179 */ "vmaxnmv\0" |
687 | 1.45M | /* 5187 */ "vminv\0" |
688 | 1.45M | /* 5193 */ "vmov\0" |
689 | 1.45M | /* 5198 */ "vmaxv\0" |
690 | 1.45M | /* 5204 */ "vsubw\0" |
691 | 1.45M | /* 5210 */ "vaddw\0" |
692 | 1.45M | /* 5216 */ "pldw\0" |
693 | 1.45M | /* 5221 */ "vldrw\0" |
694 | 1.45M | /* 5227 */ "vstrw\0" |
695 | 1.45M | /* 5233 */ "movw\0" |
696 | 1.45M | /* 5238 */ "vrmlaldavhax\0" |
697 | 1.45M | /* 5251 */ "vrmlsldavhax\0" |
698 | 1.45M | /* 5264 */ "fldmiax\0" |
699 | 1.45M | /* 5272 */ "fstmiax\0" |
700 | 1.45M | /* 5280 */ "vpmax\0" |
701 | 1.45M | /* 5286 */ "vmax\0" |
702 | 1.45M | /* 5291 */ "shsax\0" |
703 | 1.45M | /* 5297 */ "uhsax\0" |
704 | 1.45M | /* 5303 */ "uqsax\0" |
705 | 1.45M | /* 5309 */ "ssax\0" |
706 | 1.45M | /* 5314 */ "usax\0" |
707 | 1.45M | /* 5319 */ "vmladavax\0" |
708 | 1.45M | /* 5329 */ "vmlaldavax\0" |
709 | 1.45M | /* 5340 */ "vmlsldavax\0" |
710 | 1.45M | /* 5351 */ "vmlsdavax\0" |
711 | 1.45M | /* 5361 */ "fldmdbx\0" |
712 | 1.45M | /* 5369 */ "fstmdbx\0" |
713 | 1.45M | /* 5377 */ "vtbx\0" |
714 | 1.45M | /* 5382 */ "smladx\0" |
715 | 1.45M | /* 5389 */ "smuadx\0" |
716 | 1.45M | /* 5396 */ "smlaldx\0" |
717 | 1.45M | /* 5404 */ "smlsldx\0" |
718 | 1.45M | /* 5412 */ "smlsdx\0" |
719 | 1.45M | /* 5419 */ "smusdx\0" |
720 | 1.45M | /* 5426 */ "ldaex\0" |
721 | 1.45M | /* 5432 */ "stlex\0" |
722 | 1.45M | /* 5438 */ "ldrex\0" |
723 | 1.45M | /* 5444 */ "clrex\0" |
724 | 1.45M | /* 5450 */ "strex\0" |
725 | 1.45M | /* 5456 */ "sbfx\0" |
726 | 1.45M | /* 5461 */ "ubfx\0" |
727 | 1.45M | /* 5466 */ "vqdmladhx\0" |
728 | 1.45M | /* 5476 */ "vqrdmladhx\0" |
729 | 1.45M | /* 5487 */ "vqdmlsdhx\0" |
730 | 1.45M | /* 5497 */ "vqrdmlsdhx\0" |
731 | 1.45M | /* 5508 */ "vrmlaldavhx\0" |
732 | 1.45M | /* 5520 */ "vrmlsldavhx\0" |
733 | 1.45M | /* 5532 */ "blx\0" |
734 | 1.45M | /* 5536 */ "bflx\0" |
735 | 1.45M | /* 5541 */ "rrx\0" |
736 | 1.45M | /* 5545 */ "shasx\0" |
737 | 1.45M | /* 5551 */ "uhasx\0" |
738 | 1.45M | /* 5557 */ "uqasx\0" |
739 | 1.45M | /* 5563 */ "sasx\0" |
740 | 1.45M | /* 5568 */ "uasx\0" |
741 | 1.45M | /* 5573 */ "vrintx\0" |
742 | 1.45M | /* 5580 */ "vmladavx\0" |
743 | 1.45M | /* 5589 */ "vmlaldavx\0" |
744 | 1.45M | /* 5599 */ "vmlsldavx\0" |
745 | 1.45M | /* 5609 */ "vmlsdavx\0" |
746 | 1.45M | /* 5618 */ "vclz\0" |
747 | 1.45M | /* 5623 */ "vrintz\0" |
748 | 1.45M | }; |
749 | 1.45M | #endif // CAPSTONE_DIET |
750 | | |
751 | 1.45M | static const uint32_t OpInfo0[] = { |
752 | 1.45M | 0U, // PHI |
753 | 1.45M | 0U, // INLINEASM |
754 | 1.45M | 0U, // INLINEASM_BR |
755 | 1.45M | 0U, // CFI_INSTRUCTION |
756 | 1.45M | 0U, // EH_LABEL |
757 | 1.45M | 0U, // GC_LABEL |
758 | 1.45M | 0U, // ANNOTATION_LABEL |
759 | 1.45M | 0U, // KILL |
760 | 1.45M | 0U, // EXTRACT_SUBREG |
761 | 1.45M | 0U, // INSERT_SUBREG |
762 | 1.45M | 0U, // IMPLICIT_DEF |
763 | 1.45M | 0U, // SUBREG_TO_REG |
764 | 1.45M | 0U, // COPY_TO_REGCLASS |
765 | 1.45M | 2671U, // DBG_VALUE |
766 | 1.45M | 2728U, // DBG_VALUE_LIST |
767 | 1.45M | 2681U, // DBG_INSTR_REF |
768 | 1.45M | 2695U, // DBG_PHI |
769 | 1.45M | 2703U, // DBG_LABEL |
770 | 1.45M | 0U, // REG_SEQUENCE |
771 | 1.45M | 0U, // COPY |
772 | 1.45M | 2664U, // BUNDLE |
773 | 1.45M | 2713U, // LIFETIME_START |
774 | 1.45M | 2638U, // LIFETIME_END |
775 | 1.45M | 2651U, // PSEUDO_PROBE |
776 | 1.45M | 0U, // ARITH_FENCE |
777 | 1.45M | 0U, // STACKMAP |
778 | 1.45M | 4012U, // FENTRY_CALL |
779 | 1.45M | 0U, // PATCHPOINT |
780 | 1.45M | 0U, // LOAD_STACK_GUARD |
781 | 1.45M | 0U, // PREALLOCATED_SETUP |
782 | 1.45M | 0U, // PREALLOCATED_ARG |
783 | 1.45M | 0U, // STATEPOINT |
784 | 1.45M | 0U, // LOCAL_ESCAPE |
785 | 1.45M | 0U, // FAULTING_OP |
786 | 1.45M | 0U, // PATCHABLE_OP |
787 | 1.45M | 2230U, // PATCHABLE_FUNCTION_ENTER |
788 | 1.45M | 2150U, // PATCHABLE_RET |
789 | 1.45M | 2276U, // PATCHABLE_FUNCTION_EXIT |
790 | 1.45M | 2253U, // PATCHABLE_TAIL_CALL |
791 | 1.45M | 2205U, // PATCHABLE_EVENT_CALL |
792 | 1.45M | 2181U, // PATCHABLE_TYPED_EVENT_CALL |
793 | 1.45M | 0U, // ICALL_BRANCH_FUNNEL |
794 | 1.45M | 0U, // MEMBARRIER |
795 | 1.45M | 0U, // G_ASSERT_SEXT |
796 | 1.45M | 0U, // G_ASSERT_ZEXT |
797 | 1.45M | 0U, // G_ASSERT_ALIGN |
798 | 1.45M | 0U, // G_ADD |
799 | 1.45M | 0U, // G_SUB |
800 | 1.45M | 0U, // G_MUL |
801 | 1.45M | 0U, // G_SDIV |
802 | 1.45M | 0U, // G_UDIV |
803 | 1.45M | 0U, // G_SREM |
804 | 1.45M | 0U, // G_UREM |
805 | 1.45M | 0U, // G_SDIVREM |
806 | 1.45M | 0U, // G_UDIVREM |
807 | 1.45M | 0U, // G_AND |
808 | 1.45M | 0U, // G_OR |
809 | 1.45M | 0U, // G_XOR |
810 | 1.45M | 0U, // G_IMPLICIT_DEF |
811 | 1.45M | 0U, // G_PHI |
812 | 1.45M | 0U, // G_FRAME_INDEX |
813 | 1.45M | 0U, // G_GLOBAL_VALUE |
814 | 1.45M | 0U, // G_EXTRACT |
815 | 1.45M | 0U, // G_UNMERGE_VALUES |
816 | 1.45M | 0U, // G_INSERT |
817 | 1.45M | 0U, // G_MERGE_VALUES |
818 | 1.45M | 0U, // G_BUILD_VECTOR |
819 | 1.45M | 0U, // G_BUILD_VECTOR_TRUNC |
820 | 1.45M | 0U, // G_CONCAT_VECTORS |
821 | 1.45M | 0U, // G_PTRTOINT |
822 | 1.45M | 0U, // G_INTTOPTR |
823 | 1.45M | 0U, // G_BITCAST |
824 | 1.45M | 0U, // G_FREEZE |
825 | 1.45M | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
826 | 1.45M | 0U, // G_INTRINSIC_TRUNC |
827 | 1.45M | 0U, // G_INTRINSIC_ROUND |
828 | 1.45M | 0U, // G_INTRINSIC_LRINT |
829 | 1.45M | 0U, // G_INTRINSIC_ROUNDEVEN |
830 | 1.45M | 0U, // G_READCYCLECOUNTER |
831 | 1.45M | 0U, // G_LOAD |
832 | 1.45M | 0U, // G_SEXTLOAD |
833 | 1.45M | 0U, // G_ZEXTLOAD |
834 | 1.45M | 0U, // G_INDEXED_LOAD |
835 | 1.45M | 0U, // G_INDEXED_SEXTLOAD |
836 | 1.45M | 0U, // G_INDEXED_ZEXTLOAD |
837 | 1.45M | 0U, // G_STORE |
838 | 1.45M | 0U, // G_INDEXED_STORE |
839 | 1.45M | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
840 | 1.45M | 0U, // G_ATOMIC_CMPXCHG |
841 | 1.45M | 0U, // G_ATOMICRMW_XCHG |
842 | 1.45M | 0U, // G_ATOMICRMW_ADD |
843 | 1.45M | 0U, // G_ATOMICRMW_SUB |
844 | 1.45M | 0U, // G_ATOMICRMW_AND |
845 | 1.45M | 0U, // G_ATOMICRMW_NAND |
846 | 1.45M | 0U, // G_ATOMICRMW_OR |
847 | 1.45M | 0U, // G_ATOMICRMW_XOR |
848 | 1.45M | 0U, // G_ATOMICRMW_MAX |
849 | 1.45M | 0U, // G_ATOMICRMW_MIN |
850 | 1.45M | 0U, // G_ATOMICRMW_UMAX |
851 | 1.45M | 0U, // G_ATOMICRMW_UMIN |
852 | 1.45M | 0U, // G_ATOMICRMW_FADD |
853 | 1.45M | 0U, // G_ATOMICRMW_FSUB |
854 | 1.45M | 0U, // G_ATOMICRMW_FMAX |
855 | 1.45M | 0U, // G_ATOMICRMW_FMIN |
856 | 1.45M | 0U, // G_ATOMICRMW_UINC_WRAP |
857 | 1.45M | 0U, // G_ATOMICRMW_UDEC_WRAP |
858 | 1.45M | 0U, // G_FENCE |
859 | 1.45M | 0U, // G_BRCOND |
860 | 1.45M | 0U, // G_BRINDIRECT |
861 | 1.45M | 0U, // G_INVOKE_REGION_START |
862 | 1.45M | 0U, // G_INTRINSIC |
863 | 1.45M | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
864 | 1.45M | 0U, // G_ANYEXT |
865 | 1.45M | 0U, // G_TRUNC |
866 | 1.45M | 0U, // G_CONSTANT |
867 | 1.45M | 0U, // G_FCONSTANT |
868 | 1.45M | 0U, // G_VASTART |
869 | 1.45M | 0U, // G_VAARG |
870 | 1.45M | 0U, // G_SEXT |
871 | 1.45M | 0U, // G_SEXT_INREG |
872 | 1.45M | 0U, // G_ZEXT |
873 | 1.45M | 0U, // G_SHL |
874 | 1.45M | 0U, // G_LSHR |
875 | 1.45M | 0U, // G_ASHR |
876 | 1.45M | 0U, // G_FSHL |
877 | 1.45M | 0U, // G_FSHR |
878 | 1.45M | 0U, // G_ROTR |
879 | 1.45M | 0U, // G_ROTL |
880 | 1.45M | 0U, // G_ICMP |
881 | 1.45M | 0U, // G_FCMP |
882 | 1.45M | 0U, // G_SELECT |
883 | 1.45M | 0U, // G_UADDO |
884 | 1.45M | 0U, // G_UADDE |
885 | 1.45M | 0U, // G_USUBO |
886 | 1.45M | 0U, // G_USUBE |
887 | 1.45M | 0U, // G_SADDO |
888 | 1.45M | 0U, // G_SADDE |
889 | 1.45M | 0U, // G_SSUBO |
890 | 1.45M | 0U, // G_SSUBE |
891 | 1.45M | 0U, // G_UMULO |
892 | 1.45M | 0U, // G_SMULO |
893 | 1.45M | 0U, // G_UMULH |
894 | 1.45M | 0U, // G_SMULH |
895 | 1.45M | 0U, // G_UADDSAT |
896 | 1.45M | 0U, // G_SADDSAT |
897 | 1.45M | 0U, // G_USUBSAT |
898 | 1.45M | 0U, // G_SSUBSAT |
899 | 1.45M | 0U, // G_USHLSAT |
900 | 1.45M | 0U, // G_SSHLSAT |
901 | 1.45M | 0U, // G_SMULFIX |
902 | 1.45M | 0U, // G_UMULFIX |
903 | 1.45M | 0U, // G_SMULFIXSAT |
904 | 1.45M | 0U, // G_UMULFIXSAT |
905 | 1.45M | 0U, // G_SDIVFIX |
906 | 1.45M | 0U, // G_UDIVFIX |
907 | 1.45M | 0U, // G_SDIVFIXSAT |
908 | 1.45M | 0U, // G_UDIVFIXSAT |
909 | 1.45M | 0U, // G_FADD |
910 | 1.45M | 0U, // G_FSUB |
911 | 1.45M | 0U, // G_FMUL |
912 | 1.45M | 0U, // G_FMA |
913 | 1.45M | 0U, // G_FMAD |
914 | 1.45M | 0U, // G_FDIV |
915 | 1.45M | 0U, // G_FREM |
916 | 1.45M | 0U, // G_FPOW |
917 | 1.45M | 0U, // G_FPOWI |
918 | 1.45M | 0U, // G_FEXP |
919 | 1.45M | 0U, // G_FEXP2 |
920 | 1.45M | 0U, // G_FLOG |
921 | 1.45M | 0U, // G_FLOG2 |
922 | 1.45M | 0U, // G_FLOG10 |
923 | 1.45M | 0U, // G_FNEG |
924 | 1.45M | 0U, // G_FPEXT |
925 | 1.45M | 0U, // G_FPTRUNC |
926 | 1.45M | 0U, // G_FPTOSI |
927 | 1.45M | 0U, // G_FPTOUI |
928 | 1.45M | 0U, // G_SITOFP |
929 | 1.45M | 0U, // G_UITOFP |
930 | 1.45M | 0U, // G_FABS |
931 | 1.45M | 0U, // G_FCOPYSIGN |
932 | 1.45M | 0U, // G_IS_FPCLASS |
933 | 1.45M | 0U, // G_FCANONICALIZE |
934 | 1.45M | 0U, // G_FMINNUM |
935 | 1.45M | 0U, // G_FMAXNUM |
936 | 1.45M | 0U, // G_FMINNUM_IEEE |
937 | 1.45M | 0U, // G_FMAXNUM_IEEE |
938 | 1.45M | 0U, // G_FMINIMUM |
939 | 1.45M | 0U, // G_FMAXIMUM |
940 | 1.45M | 0U, // G_PTR_ADD |
941 | 1.45M | 0U, // G_PTRMASK |
942 | 1.45M | 0U, // G_SMIN |
943 | 1.45M | 0U, // G_SMAX |
944 | 1.45M | 0U, // G_UMIN |
945 | 1.45M | 0U, // G_UMAX |
946 | 1.45M | 0U, // G_ABS |
947 | 1.45M | 0U, // G_LROUND |
948 | 1.45M | 0U, // G_LLROUND |
949 | 1.45M | 0U, // G_BR |
950 | 1.45M | 0U, // G_BRJT |
951 | 1.45M | 0U, // G_INSERT_VECTOR_ELT |
952 | 1.45M | 0U, // G_EXTRACT_VECTOR_ELT |
953 | 1.45M | 0U, // G_SHUFFLE_VECTOR |
954 | 1.45M | 0U, // G_CTTZ |
955 | 1.45M | 0U, // G_CTTZ_ZERO_UNDEF |
956 | 1.45M | 0U, // G_CTLZ |
957 | 1.45M | 0U, // G_CTLZ_ZERO_UNDEF |
958 | 1.45M | 0U, // G_CTPOP |
959 | 1.45M | 0U, // G_BSWAP |
960 | 1.45M | 0U, // G_BITREVERSE |
961 | 1.45M | 0U, // G_FCEIL |
962 | 1.45M | 0U, // G_FCOS |
963 | 1.45M | 0U, // G_FSIN |
964 | 1.45M | 0U, // G_FSQRT |
965 | 1.45M | 0U, // G_FFLOOR |
966 | 1.45M | 0U, // G_FRINT |
967 | 1.45M | 0U, // G_FNEARBYINT |
968 | 1.45M | 0U, // G_ADDRSPACE_CAST |
969 | 1.45M | 0U, // G_BLOCK_ADDR |
970 | 1.45M | 0U, // G_JUMP_TABLE |
971 | 1.45M | 0U, // G_DYN_STACKALLOC |
972 | 1.45M | 0U, // G_STRICT_FADD |
973 | 1.45M | 0U, // G_STRICT_FSUB |
974 | 1.45M | 0U, // G_STRICT_FMUL |
975 | 1.45M | 0U, // G_STRICT_FDIV |
976 | 1.45M | 0U, // G_STRICT_FREM |
977 | 1.45M | 0U, // G_STRICT_FMA |
978 | 1.45M | 0U, // G_STRICT_FSQRT |
979 | 1.45M | 0U, // G_READ_REGISTER |
980 | 1.45M | 0U, // G_WRITE_REGISTER |
981 | 1.45M | 0U, // G_MEMCPY |
982 | 1.45M | 0U, // G_MEMCPY_INLINE |
983 | 1.45M | 0U, // G_MEMMOVE |
984 | 1.45M | 0U, // G_MEMSET |
985 | 1.45M | 0U, // G_BZERO |
986 | 1.45M | 0U, // G_VECREDUCE_SEQ_FADD |
987 | 1.45M | 0U, // G_VECREDUCE_SEQ_FMUL |
988 | 1.45M | 0U, // G_VECREDUCE_FADD |
989 | 1.45M | 0U, // G_VECREDUCE_FMUL |
990 | 1.45M | 0U, // G_VECREDUCE_FMAX |
991 | 1.45M | 0U, // G_VECREDUCE_FMIN |
992 | 1.45M | 0U, // G_VECREDUCE_ADD |
993 | 1.45M | 0U, // G_VECREDUCE_MUL |
994 | 1.45M | 0U, // G_VECREDUCE_AND |
995 | 1.45M | 0U, // G_VECREDUCE_OR |
996 | 1.45M | 0U, // G_VECREDUCE_XOR |
997 | 1.45M | 0U, // G_VECREDUCE_SMAX |
998 | 1.45M | 0U, // G_VECREDUCE_SMIN |
999 | 1.45M | 0U, // G_VECREDUCE_UMAX |
1000 | 1.45M | 0U, // G_VECREDUCE_UMIN |
1001 | 1.45M | 0U, // G_SBFX |
1002 | 1.45M | 0U, // G_UBFX |
1003 | 1.45M | 0U, // ABS |
1004 | 1.45M | 0U, // ADDSri |
1005 | 1.45M | 0U, // ADDSrr |
1006 | 1.45M | 0U, // ADDSrsi |
1007 | 1.45M | 0U, // ADDSrsr |
1008 | 1.45M | 0U, // ADJCALLSTACKDOWN |
1009 | 1.45M | 0U, // ADJCALLSTACKUP |
1010 | 1.45M | 12770U, // ASRi |
1011 | 1.45M | 12770U, // ASRr |
1012 | 1.45M | 0U, // B |
1013 | 1.45M | 0U, // BCCZi64 |
1014 | 1.45M | 0U, // BCCi64 |
1015 | 1.45M | 0U, // BLX_noip |
1016 | 1.45M | 0U, // BLX_pred_noip |
1017 | 1.45M | 0U, // BL_PUSHLR |
1018 | 1.45M | 0U, // BMOVPCB_CALL |
1019 | 1.45M | 0U, // BMOVPCRX_CALL |
1020 | 1.45M | 0U, // BR_JTadd |
1021 | 1.45M | 0U, // BR_JTm_i12 |
1022 | 1.45M | 0U, // BR_JTm_rs |
1023 | 1.45M | 0U, // BR_JTr |
1024 | 1.45M | 0U, // BX_CALL |
1025 | 1.45M | 0U, // CMP_SWAP_16 |
1026 | 1.45M | 0U, // CMP_SWAP_32 |
1027 | 1.45M | 0U, // CMP_SWAP_64 |
1028 | 1.45M | 0U, // CMP_SWAP_8 |
1029 | 1.45M | 0U, // CONSTPOOL_ENTRY |
1030 | 1.45M | 0U, // COPY_STRUCT_BYVAL_I32 |
1031 | 1.45M | 67130072U, // ITasm |
1032 | 1.45M | 0U, // Int_eh_sjlj_dispatchsetup |
1033 | 1.45M | 0U, // Int_eh_sjlj_longjmp |
1034 | 1.45M | 0U, // Int_eh_sjlj_setjmp |
1035 | 1.45M | 0U, // Int_eh_sjlj_setjmp_nofp |
1036 | 1.45M | 0U, // Int_eh_sjlj_setup_dispatch |
1037 | 1.45M | 0U, // JUMPTABLE_ADDRS |
1038 | 1.45M | 0U, // JUMPTABLE_INSTS |
1039 | 1.45M | 0U, // JUMPTABLE_TBB |
1040 | 1.45M | 0U, // JUMPTABLE_TBH |
1041 | 1.45M | 0U, // LDMIA_RET |
1042 | 1.45M | 29344U, // LDRBT_POST |
1043 | 1.45M | 29094U, // LDRConstPool |
1044 | 1.45M | 29379U, // LDRHTii |
1045 | 1.45M | 0U, // LDRLIT_ga_abs |
1046 | 1.45M | 0U, // LDRLIT_ga_pcrel |
1047 | 1.45M | 0U, // LDRLIT_ga_pcrel_ldr |
1048 | 1.45M | 29356U, // LDRSBTii |
1049 | 1.45M | 29391U, // LDRSHTii |
1050 | 1.45M | 29538U, // LDRT_POST |
1051 | 1.45M | 0U, // LEApcrel |
1052 | 1.45M | 0U, // LEApcrelJT |
1053 | 1.45M | 0U, // LOADDUAL |
1054 | 1.45M | 12318U, // LSLi |
1055 | 1.45M | 12318U, // LSLr |
1056 | 1.45M | 12777U, // LSRi |
1057 | 1.45M | 12777U, // LSRr |
1058 | 1.45M | 0U, // MEMCPY |
1059 | 1.45M | 0U, // MLAv5 |
1060 | 1.45M | 0U, // MOVCCi |
1061 | 1.45M | 0U, // MOVCCi16 |
1062 | 1.45M | 0U, // MOVCCi32imm |
1063 | 1.45M | 0U, // MOVCCr |
1064 | 1.45M | 0U, // MOVCCsi |
1065 | 1.45M | 0U, // MOVCCsr |
1066 | 1.45M | 0U, // MOVPCRX |
1067 | 1.45M | 0U, // MOVTi16_ga_pcrel |
1068 | 1.45M | 0U, // MOV_ga_pcrel |
1069 | 1.45M | 0U, // MOV_ga_pcrel_ldr |
1070 | 1.45M | 0U, // MOVi16_ga_pcrel |
1071 | 1.45M | 0U, // MOVi32imm |
1072 | 1.45M | 0U, // MOVsra_flag |
1073 | 1.45M | 0U, // MOVsrl_flag |
1074 | 1.45M | 0U, // MQPRCopy |
1075 | 1.45M | 0U, // MQQPRLoad |
1076 | 1.45M | 0U, // MQQPRStore |
1077 | 1.45M | 0U, // MQQQQPRLoad |
1078 | 1.45M | 0U, // MQQQQPRStore |
1079 | 1.45M | 0U, // MULv5 |
1080 | 1.45M | 0U, // MVE_MEMCPYLOOPINST |
1081 | 1.45M | 0U, // MVE_MEMSETLOOPINST |
1082 | 1.45M | 0U, // MVNCCi |
1083 | 1.45M | 0U, // PICADD |
1084 | 1.45M | 0U, // PICLDR |
1085 | 1.45M | 0U, // PICLDRB |
1086 | 1.45M | 0U, // PICLDRH |
1087 | 1.45M | 0U, // PICLDRSB |
1088 | 1.45M | 0U, // PICLDRSH |
1089 | 1.45M | 0U, // PICSTR |
1090 | 1.45M | 0U, // PICSTRB |
1091 | 1.45M | 0U, // PICSTRH |
1092 | 1.45M | 12756U, // RORi |
1093 | 1.45M | 12756U, // RORr |
1094 | 1.45M | 0U, // RRX |
1095 | 1.45M | 38310U, // RRXi |
1096 | 1.45M | 0U, // RSBSri |
1097 | 1.45M | 0U, // RSBSrsi |
1098 | 1.45M | 0U, // RSBSrsr |
1099 | 1.45M | 0U, // SEH_EpilogEnd |
1100 | 1.45M | 0U, // SEH_EpilogStart |
1101 | 1.45M | 0U, // SEH_Nop |
1102 | 1.45M | 0U, // SEH_Nop_Ret |
1103 | 1.45M | 0U, // SEH_PrologEnd |
1104 | 1.45M | 0U, // SEH_SaveFRegs |
1105 | 1.45M | 0U, // SEH_SaveLR |
1106 | 1.45M | 0U, // SEH_SaveRegs |
1107 | 1.45M | 0U, // SEH_SaveRegs_Ret |
1108 | 1.45M | 0U, // SEH_SaveSP |
1109 | 1.45M | 0U, // SEH_StackAlloc |
1110 | 1.45M | 0U, // SMLALv5 |
1111 | 1.45M | 0U, // SMULLv5 |
1112 | 1.45M | 0U, // SPACE |
1113 | 1.45M | 0U, // STOREDUAL |
1114 | 1.45M | 29350U, // STRBT_POST |
1115 | 1.45M | 0U, // STRBi_preidx |
1116 | 1.45M | 0U, // STRBr_preidx |
1117 | 1.45M | 0U, // STRH_preidx |
1118 | 1.45M | 29549U, // STRT_POST |
1119 | 1.45M | 0U, // STRi_preidx |
1120 | 1.45M | 0U, // STRr_preidx |
1121 | 1.45M | 0U, // SUBS_PC_LR |
1122 | 1.45M | 0U, // SUBSri |
1123 | 1.45M | 0U, // SUBSrr |
1124 | 1.45M | 0U, // SUBSrsi |
1125 | 1.45M | 0U, // SUBSrsr |
1126 | 1.45M | 0U, // SpeculationBarrierISBDSBEndBB |
1127 | 1.45M | 0U, // SpeculationBarrierSBEndBB |
1128 | 1.45M | 0U, // TAILJMPd |
1129 | 1.45M | 0U, // TAILJMPr |
1130 | 1.45M | 0U, // TAILJMPr4 |
1131 | 1.45M | 0U, // TCRETURNdi |
1132 | 1.45M | 0U, // TCRETURNri |
1133 | 1.45M | 0U, // TPsoft |
1134 | 1.45M | 0U, // UMLALv5 |
1135 | 1.45M | 0U, // UMULLv5 |
1136 | 1.45M | 567556U, // VLD1LNdAsm_16 |
1137 | 1.45M | 1091844U, // VLD1LNdAsm_32 |
1138 | 1.45M | 1616132U, // VLD1LNdAsm_8 |
1139 | 1.45M | 567556U, // VLD1LNdWB_fixed_Asm_16 |
1140 | 1.45M | 1091844U, // VLD1LNdWB_fixed_Asm_32 |
1141 | 1.45M | 1616132U, // VLD1LNdWB_fixed_Asm_8 |
1142 | 1.45M | 575748U, // VLD1LNdWB_register_Asm_16 |
1143 | 1.45M | 1100036U, // VLD1LNdWB_register_Asm_32 |
1144 | 1.45M | 1624324U, // VLD1LNdWB_register_Asm_8 |
1145 | 1.45M | 567605U, // VLD2LNdAsm_16 |
1146 | 1.45M | 1091893U, // VLD2LNdAsm_32 |
1147 | 1.45M | 1616181U, // VLD2LNdAsm_8 |
1148 | 1.45M | 567605U, // VLD2LNdWB_fixed_Asm_16 |
1149 | 1.45M | 1091893U, // VLD2LNdWB_fixed_Asm_32 |
1150 | 1.45M | 1616181U, // VLD2LNdWB_fixed_Asm_8 |
1151 | 1.45M | 575797U, // VLD2LNdWB_register_Asm_16 |
1152 | 1.45M | 1100085U, // VLD2LNdWB_register_Asm_32 |
1153 | 1.45M | 1624373U, // VLD2LNdWB_register_Asm_8 |
1154 | 1.45M | 567605U, // VLD2LNqAsm_16 |
1155 | 1.45M | 1091893U, // VLD2LNqAsm_32 |
1156 | 1.45M | 567605U, // VLD2LNqWB_fixed_Asm_16 |
1157 | 1.45M | 1091893U, // VLD2LNqWB_fixed_Asm_32 |
1158 | 1.45M | 575797U, // VLD2LNqWB_register_Asm_16 |
1159 | 1.45M | 1100085U, // VLD2LNqWB_register_Asm_32 |
1160 | 1.45M | 134801754U, // VLD3DUPdAsm_16 |
1161 | 1.45M | 135326042U, // VLD3DUPdAsm_32 |
1162 | 1.45M | 135850330U, // VLD3DUPdAsm_8 |
1163 | 1.45M | 134801754U, // VLD3DUPdWB_fixed_Asm_16 |
1164 | 1.45M | 135326042U, // VLD3DUPdWB_fixed_Asm_32 |
1165 | 1.45M | 135850330U, // VLD3DUPdWB_fixed_Asm_8 |
1166 | 1.45M | 134785370U, // VLD3DUPdWB_register_Asm_16 |
1167 | 1.45M | 135309658U, // VLD3DUPdWB_register_Asm_32 |
1168 | 1.45M | 135833946U, // VLD3DUPdWB_register_Asm_8 |
1169 | 1.45M | 201910618U, // VLD3DUPqAsm_16 |
1170 | 1.45M | 202434906U, // VLD3DUPqAsm_32 |
1171 | 1.45M | 202959194U, // VLD3DUPqAsm_8 |
1172 | 1.45M | 201910618U, // VLD3DUPqWB_fixed_Asm_16 |
1173 | 1.45M | 202434906U, // VLD3DUPqWB_fixed_Asm_32 |
1174 | 1.45M | 202959194U, // VLD3DUPqWB_fixed_Asm_8 |
1175 | 1.45M | 201894234U, // VLD3DUPqWB_register_Asm_16 |
1176 | 1.45M | 202418522U, // VLD3DUPqWB_register_Asm_32 |
1177 | 1.45M | 202942810U, // VLD3DUPqWB_register_Asm_8 |
1178 | 1.45M | 567642U, // VLD3LNdAsm_16 |
1179 | 1.45M | 1091930U, // VLD3LNdAsm_32 |
1180 | 1.45M | 1616218U, // VLD3LNdAsm_8 |
1181 | 1.45M | 567642U, // VLD3LNdWB_fixed_Asm_16 |
1182 | 1.45M | 1091930U, // VLD3LNdWB_fixed_Asm_32 |
1183 | 1.45M | 1616218U, // VLD3LNdWB_fixed_Asm_8 |
1184 | 1.45M | 575834U, // VLD3LNdWB_register_Asm_16 |
1185 | 1.45M | 1100122U, // VLD3LNdWB_register_Asm_32 |
1186 | 1.45M | 1624410U, // VLD3LNdWB_register_Asm_8 |
1187 | 1.45M | 567642U, // VLD3LNqAsm_16 |
1188 | 1.45M | 1091930U, // VLD3LNqAsm_32 |
1189 | 1.45M | 567642U, // VLD3LNqWB_fixed_Asm_16 |
1190 | 1.45M | 1091930U, // VLD3LNqWB_fixed_Asm_32 |
1191 | 1.45M | 575834U, // VLD3LNqWB_register_Asm_16 |
1192 | 1.45M | 1100122U, // VLD3LNqWB_register_Asm_32 |
1193 | 1.45M | 269019482U, // VLD3dAsm_16 |
1194 | 1.45M | 269543770U, // VLD3dAsm_32 |
1195 | 1.45M | 270068058U, // VLD3dAsm_8 |
1196 | 1.45M | 269019482U, // VLD3dWB_fixed_Asm_16 |
1197 | 1.45M | 269543770U, // VLD3dWB_fixed_Asm_32 |
1198 | 1.45M | 270068058U, // VLD3dWB_fixed_Asm_8 |
1199 | 1.45M | 269003098U, // VLD3dWB_register_Asm_16 |
1200 | 1.45M | 269527386U, // VLD3dWB_register_Asm_32 |
1201 | 1.45M | 270051674U, // VLD3dWB_register_Asm_8 |
1202 | 1.45M | 336128346U, // VLD3qAsm_16 |
1203 | 1.45M | 336652634U, // VLD3qAsm_32 |
1204 | 1.45M | 337176922U, // VLD3qAsm_8 |
1205 | 1.45M | 336128346U, // VLD3qWB_fixed_Asm_16 |
1206 | 1.45M | 336652634U, // VLD3qWB_fixed_Asm_32 |
1207 | 1.45M | 337176922U, // VLD3qWB_fixed_Asm_8 |
1208 | 1.45M | 336111962U, // VLD3qWB_register_Asm_16 |
1209 | 1.45M | 336636250U, // VLD3qWB_register_Asm_32 |
1210 | 1.45M | 337160538U, // VLD3qWB_register_Asm_8 |
1211 | 1.45M | 403237238U, // VLD4DUPdAsm_16 |
1212 | 1.45M | 403761526U, // VLD4DUPdAsm_32 |
1213 | 1.45M | 404285814U, // VLD4DUPdAsm_8 |
1214 | 1.45M | 403237238U, // VLD4DUPdWB_fixed_Asm_16 |
1215 | 1.45M | 403761526U, // VLD4DUPdWB_fixed_Asm_32 |
1216 | 1.45M | 404285814U, // VLD4DUPdWB_fixed_Asm_8 |
1217 | 1.45M | 403220854U, // VLD4DUPdWB_register_Asm_16 |
1218 | 1.45M | 403745142U, // VLD4DUPdWB_register_Asm_32 |
1219 | 1.45M | 404269430U, // VLD4DUPdWB_register_Asm_8 |
1220 | 1.45M | 470346102U, // VLD4DUPqAsm_16 |
1221 | 1.45M | 470870390U, // VLD4DUPqAsm_32 |
1222 | 1.45M | 471394678U, // VLD4DUPqAsm_8 |
1223 | 1.45M | 470346102U, // VLD4DUPqWB_fixed_Asm_16 |
1224 | 1.45M | 470870390U, // VLD4DUPqWB_fixed_Asm_32 |
1225 | 1.45M | 471394678U, // VLD4DUPqWB_fixed_Asm_8 |
1226 | 1.45M | 470329718U, // VLD4DUPqWB_register_Asm_16 |
1227 | 1.45M | 470854006U, // VLD4DUPqWB_register_Asm_32 |
1228 | 1.45M | 471378294U, // VLD4DUPqWB_register_Asm_8 |
1229 | 1.45M | 567670U, // VLD4LNdAsm_16 |
1230 | 1.45M | 1091958U, // VLD4LNdAsm_32 |
1231 | 1.45M | 1616246U, // VLD4LNdAsm_8 |
1232 | 1.45M | 567670U, // VLD4LNdWB_fixed_Asm_16 |
1233 | 1.45M | 1091958U, // VLD4LNdWB_fixed_Asm_32 |
1234 | 1.45M | 1616246U, // VLD4LNdWB_fixed_Asm_8 |
1235 | 1.45M | 575862U, // VLD4LNdWB_register_Asm_16 |
1236 | 1.45M | 1100150U, // VLD4LNdWB_register_Asm_32 |
1237 | 1.45M | 1624438U, // VLD4LNdWB_register_Asm_8 |
1238 | 1.45M | 567670U, // VLD4LNqAsm_16 |
1239 | 1.45M | 1091958U, // VLD4LNqAsm_32 |
1240 | 1.45M | 567670U, // VLD4LNqWB_fixed_Asm_16 |
1241 | 1.45M | 1091958U, // VLD4LNqWB_fixed_Asm_32 |
1242 | 1.45M | 575862U, // VLD4LNqWB_register_Asm_16 |
1243 | 1.45M | 1100150U, // VLD4LNqWB_register_Asm_32 |
1244 | 1.45M | 537454966U, // VLD4dAsm_16 |
1245 | 1.45M | 537979254U, // VLD4dAsm_32 |
1246 | 1.45M | 538503542U, // VLD4dAsm_8 |
1247 | 1.45M | 537454966U, // VLD4dWB_fixed_Asm_16 |
1248 | 1.45M | 537979254U, // VLD4dWB_fixed_Asm_32 |
1249 | 1.45M | 538503542U, // VLD4dWB_fixed_Asm_8 |
1250 | 1.45M | 537438582U, // VLD4dWB_register_Asm_16 |
1251 | 1.45M | 537962870U, // VLD4dWB_register_Asm_32 |
1252 | 1.45M | 538487158U, // VLD4dWB_register_Asm_8 |
1253 | 1.45M | 604563830U, // VLD4qAsm_16 |
1254 | 1.45M | 605088118U, // VLD4qAsm_32 |
1255 | 1.45M | 605612406U, // VLD4qAsm_8 |
1256 | 1.45M | 604563830U, // VLD4qWB_fixed_Asm_16 |
1257 | 1.45M | 605088118U, // VLD4qWB_fixed_Asm_32 |
1258 | 1.45M | 605612406U, // VLD4qWB_fixed_Asm_8 |
1259 | 1.45M | 604547446U, // VLD4qWB_register_Asm_16 |
1260 | 1.45M | 605071734U, // VLD4qWB_register_Asm_32 |
1261 | 1.45M | 605596022U, // VLD4qWB_register_Asm_8 |
1262 | 1.45M | 0U, // VMOVD0 |
1263 | 1.45M | 0U, // VMOVDcc |
1264 | 1.45M | 0U, // VMOVHcc |
1265 | 1.45M | 0U, // VMOVQ0 |
1266 | 1.45M | 0U, // VMOVScc |
1267 | 1.45M | 567567U, // VST1LNdAsm_16 |
1268 | 1.45M | 1091855U, // VST1LNdAsm_32 |
1269 | 1.45M | 1616143U, // VST1LNdAsm_8 |
1270 | 1.45M | 567567U, // VST1LNdWB_fixed_Asm_16 |
1271 | 1.45M | 1091855U, // VST1LNdWB_fixed_Asm_32 |
1272 | 1.45M | 1616143U, // VST1LNdWB_fixed_Asm_8 |
1273 | 1.45M | 575759U, // VST1LNdWB_register_Asm_16 |
1274 | 1.45M | 1100047U, // VST1LNdWB_register_Asm_32 |
1275 | 1.45M | 1624335U, // VST1LNdWB_register_Asm_8 |
1276 | 1.45M | 567632U, // VST2LNdAsm_16 |
1277 | 1.45M | 1091920U, // VST2LNdAsm_32 |
1278 | 1.45M | 1616208U, // VST2LNdAsm_8 |
1279 | 1.45M | 567632U, // VST2LNdWB_fixed_Asm_16 |
1280 | 1.45M | 1091920U, // VST2LNdWB_fixed_Asm_32 |
1281 | 1.45M | 1616208U, // VST2LNdWB_fixed_Asm_8 |
1282 | 1.45M | 575824U, // VST2LNdWB_register_Asm_16 |
1283 | 1.45M | 1100112U, // VST2LNdWB_register_Asm_32 |
1284 | 1.45M | 1624400U, // VST2LNdWB_register_Asm_8 |
1285 | 1.45M | 567632U, // VST2LNqAsm_16 |
1286 | 1.45M | 1091920U, // VST2LNqAsm_32 |
1287 | 1.45M | 567632U, // VST2LNqWB_fixed_Asm_16 |
1288 | 1.45M | 1091920U, // VST2LNqWB_fixed_Asm_32 |
1289 | 1.45M | 575824U, // VST2LNqWB_register_Asm_16 |
1290 | 1.45M | 1100112U, // VST2LNqWB_register_Asm_32 |
1291 | 1.45M | 567653U, // VST3LNdAsm_16 |
1292 | 1.45M | 1091941U, // VST3LNdAsm_32 |
1293 | 1.45M | 1616229U, // VST3LNdAsm_8 |
1294 | 1.45M | 567653U, // VST3LNdWB_fixed_Asm_16 |
1295 | 1.45M | 1091941U, // VST3LNdWB_fixed_Asm_32 |
1296 | 1.45M | 1616229U, // VST3LNdWB_fixed_Asm_8 |
1297 | 1.45M | 575845U, // VST3LNdWB_register_Asm_16 |
1298 | 1.45M | 1100133U, // VST3LNdWB_register_Asm_32 |
1299 | 1.45M | 1624421U, // VST3LNdWB_register_Asm_8 |
1300 | 1.45M | 567653U, // VST3LNqAsm_16 |
1301 | 1.45M | 1091941U, // VST3LNqAsm_32 |
1302 | 1.45M | 567653U, // VST3LNqWB_fixed_Asm_16 |
1303 | 1.45M | 1091941U, // VST3LNqWB_fixed_Asm_32 |
1304 | 1.45M | 575845U, // VST3LNqWB_register_Asm_16 |
1305 | 1.45M | 1100133U, // VST3LNqWB_register_Asm_32 |
1306 | 1.45M | 269019493U, // VST3dAsm_16 |
1307 | 1.45M | 269543781U, // VST3dAsm_32 |
1308 | 1.45M | 270068069U, // VST3dAsm_8 |
1309 | 1.45M | 269019493U, // VST3dWB_fixed_Asm_16 |
1310 | 1.45M | 269543781U, // VST3dWB_fixed_Asm_32 |
1311 | 1.45M | 270068069U, // VST3dWB_fixed_Asm_8 |
1312 | 1.45M | 269003109U, // VST3dWB_register_Asm_16 |
1313 | 1.45M | 269527397U, // VST3dWB_register_Asm_32 |
1314 | 1.45M | 270051685U, // VST3dWB_register_Asm_8 |
1315 | 1.45M | 336128357U, // VST3qAsm_16 |
1316 | 1.45M | 336652645U, // VST3qAsm_32 |
1317 | 1.45M | 337176933U, // VST3qAsm_8 |
1318 | 1.45M | 336128357U, // VST3qWB_fixed_Asm_16 |
1319 | 1.45M | 336652645U, // VST3qWB_fixed_Asm_32 |
1320 | 1.45M | 337176933U, // VST3qWB_fixed_Asm_8 |
1321 | 1.45M | 336111973U, // VST3qWB_register_Asm_16 |
1322 | 1.45M | 336636261U, // VST3qWB_register_Asm_32 |
1323 | 1.45M | 337160549U, // VST3qWB_register_Asm_8 |
1324 | 1.45M | 567675U, // VST4LNdAsm_16 |
1325 | 1.45M | 1091963U, // VST4LNdAsm_32 |
1326 | 1.45M | 1616251U, // VST4LNdAsm_8 |
1327 | 1.45M | 567675U, // VST4LNdWB_fixed_Asm_16 |
1328 | 1.45M | 1091963U, // VST4LNdWB_fixed_Asm_32 |
1329 | 1.45M | 1616251U, // VST4LNdWB_fixed_Asm_8 |
1330 | 1.45M | 575867U, // VST4LNdWB_register_Asm_16 |
1331 | 1.45M | 1100155U, // VST4LNdWB_register_Asm_32 |
1332 | 1.45M | 1624443U, // VST4LNdWB_register_Asm_8 |
1333 | 1.45M | 567675U, // VST4LNqAsm_16 |
1334 | 1.45M | 1091963U, // VST4LNqAsm_32 |
1335 | 1.45M | 567675U, // VST4LNqWB_fixed_Asm_16 |
1336 | 1.45M | 1091963U, // VST4LNqWB_fixed_Asm_32 |
1337 | 1.45M | 575867U, // VST4LNqWB_register_Asm_16 |
1338 | 1.45M | 1100155U, // VST4LNqWB_register_Asm_32 |
1339 | 1.45M | 537454971U, // VST4dAsm_16 |
1340 | 1.45M | 537979259U, // VST4dAsm_32 |
1341 | 1.45M | 538503547U, // VST4dAsm_8 |
1342 | 1.45M | 537454971U, // VST4dWB_fixed_Asm_16 |
1343 | 1.45M | 537979259U, // VST4dWB_fixed_Asm_32 |
1344 | 1.45M | 538503547U, // VST4dWB_fixed_Asm_8 |
1345 | 1.45M | 537438587U, // VST4dWB_register_Asm_16 |
1346 | 1.45M | 537962875U, // VST4dWB_register_Asm_32 |
1347 | 1.45M | 538487163U, // VST4dWB_register_Asm_8 |
1348 | 1.45M | 604563835U, // VST4qAsm_16 |
1349 | 1.45M | 605088123U, // VST4qAsm_32 |
1350 | 1.45M | 605612411U, // VST4qAsm_8 |
1351 | 1.45M | 604563835U, // VST4qWB_fixed_Asm_16 |
1352 | 1.45M | 605088123U, // VST4qWB_fixed_Asm_32 |
1353 | 1.45M | 605612411U, // VST4qWB_fixed_Asm_8 |
1354 | 1.45M | 604547451U, // VST4qWB_register_Asm_16 |
1355 | 1.45M | 605071739U, // VST4qWB_register_Asm_32 |
1356 | 1.45M | 605596027U, // VST4qWB_register_Asm_8 |
1357 | 1.45M | 0U, // WIN__CHKSTK |
1358 | 1.45M | 0U, // WIN__DBZCHK |
1359 | 1.45M | 0U, // t2ABS |
1360 | 1.45M | 0U, // t2ADDSri |
1361 | 1.45M | 0U, // t2ADDSrr |
1362 | 1.45M | 0U, // t2ADDSrs |
1363 | 1.45M | 0U, // t2BF_LabelPseudo |
1364 | 1.45M | 0U, // t2BR_JT |
1365 | 1.45M | 0U, // t2CALL_BTI |
1366 | 1.45M | 0U, // t2DoLoopStart |
1367 | 1.45M | 0U, // t2DoLoopStartTP |
1368 | 1.45M | 0U, // t2LDMIA_RET |
1369 | 1.45M | 27770U, // t2LDRBpcrel |
1370 | 1.45M | 29094U, // t2LDRConstPool |
1371 | 1.45M | 28288U, // t2LDRHpcrel |
1372 | 1.45M | 0U, // t2LDRLIT_ga_pcrel |
1373 | 1.45M | 27789U, // t2LDRSBpcrel |
1374 | 1.45M | 28327U, // t2LDRSHpcrel |
1375 | 1.45M | 673247654U, // t2LDR_POST_imm |
1376 | 1.45M | 740356518U, // t2LDR_PRE_imm |
1377 | 1.45M | 0U, // t2LDRpci_pic |
1378 | 1.45M | 29094U, // t2LDRpcrel |
1379 | 1.45M | 0U, // t2LEApcrel |
1380 | 1.45M | 0U, // t2LEApcrelJT |
1381 | 1.45M | 0U, // t2LoopDec |
1382 | 1.45M | 0U, // t2LoopEnd |
1383 | 1.45M | 0U, // t2LoopEndDec |
1384 | 1.45M | 0U, // t2MOVCCasr |
1385 | 1.45M | 0U, // t2MOVCCi |
1386 | 1.45M | 0U, // t2MOVCCi16 |
1387 | 1.45M | 0U, // t2MOVCCi32imm |
1388 | 1.45M | 0U, // t2MOVCClsl |
1389 | 1.45M | 0U, // t2MOVCClsr |
1390 | 1.45M | 0U, // t2MOVCCr |
1391 | 1.45M | 0U, // t2MOVCCror |
1392 | 1.45M | 62064U, // t2MOVSsi |
1393 | 1.45M | 45680U, // t2MOVSsr |
1394 | 1.45M | 0U, // t2MOVTi16_ga_pcrel |
1395 | 1.45M | 0U, // t2MOV_ga_pcrel |
1396 | 1.45M | 0U, // t2MOVi16_ga_pcrel |
1397 | 1.45M | 0U, // t2MOVi32imm |
1398 | 1.45M | 62539U, // t2MOVsi |
1399 | 1.45M | 46155U, // t2MOVsr |
1400 | 1.45M | 0U, // t2MVNCCi |
1401 | 1.45M | 0U, // t2RSBSri |
1402 | 1.45M | 0U, // t2RSBSrs |
1403 | 1.45M | 0U, // t2STRB_preidx |
1404 | 1.45M | 0U, // t2STRH_preidx |
1405 | 1.45M | 673247744U, // t2STR_POST_imm |
1406 | 1.45M | 740356608U, // t2STR_PRE_imm |
1407 | 1.45M | 0U, // t2STR_preidx |
1408 | 1.45M | 0U, // t2SUBSri |
1409 | 1.45M | 0U, // t2SUBSrr |
1410 | 1.45M | 0U, // t2SUBSrs |
1411 | 1.45M | 0U, // t2SpeculationBarrierISBDSBEndBB |
1412 | 1.45M | 0U, // t2SpeculationBarrierSBEndBB |
1413 | 1.45M | 0U, // t2TBB_JT |
1414 | 1.45M | 0U, // t2TBH_JT |
1415 | 1.45M | 0U, // t2WhileLoopSetup |
1416 | 1.45M | 0U, // t2WhileLoopStart |
1417 | 1.45M | 0U, // t2WhileLoopStartLR |
1418 | 1.45M | 0U, // t2WhileLoopStartTP |
1419 | 1.45M | 0U, // tADCS |
1420 | 1.45M | 0U, // tADDSi3 |
1421 | 1.45M | 0U, // tADDSi8 |
1422 | 1.45M | 0U, // tADDSrr |
1423 | 1.45M | 0U, // tADDframe |
1424 | 1.45M | 0U, // tADJCALLSTACKDOWN |
1425 | 1.45M | 0U, // tADJCALLSTACKUP |
1426 | 1.45M | 0U, // tBLXNS_CALL |
1427 | 1.45M | 0U, // tBLXr_noip |
1428 | 1.45M | 0U, // tBL_PUSHLR |
1429 | 1.45M | 0U, // tBRIND |
1430 | 1.45M | 0U, // tBR_JTr |
1431 | 1.45M | 0U, // tBXNS_RET |
1432 | 1.45M | 0U, // tBX_CALL |
1433 | 1.45M | 0U, // tBX_RET |
1434 | 1.45M | 0U, // tBX_RET_vararg |
1435 | 1.45M | 0U, // tBfar |
1436 | 1.45M | 0U, // tCMP_SWAP_16 |
1437 | 1.45M | 0U, // tCMP_SWAP_32 |
1438 | 1.45M | 0U, // tCMP_SWAP_8 |
1439 | 1.45M | 0U, // tLDMIA_UPD |
1440 | 1.45M | 29094U, // tLDRConstPool |
1441 | 1.45M | 0U, // tLDRLIT_ga_abs |
1442 | 1.45M | 0U, // tLDRLIT_ga_pcrel |
1443 | 1.45M | 0U, // tLDR_postidx |
1444 | 1.45M | 0U, // tLDRpci_pic |
1445 | 1.45M | 0U, // tLEApcrel |
1446 | 1.45M | 0U, // tLEApcrelJT |
1447 | 1.45M | 0U, // tLSLSri |
1448 | 1.45M | 0U, // tMOVCCr_pseudo |
1449 | 1.45M | 0U, // tPOP_RET |
1450 | 1.45M | 0U, // tRSBS |
1451 | 1.45M | 0U, // tSBCS |
1452 | 1.45M | 0U, // tSUBSi3 |
1453 | 1.45M | 0U, // tSUBSi8 |
1454 | 1.45M | 0U, // tSUBSrr |
1455 | 1.45M | 0U, // tTAILJMPd |
1456 | 1.45M | 0U, // tTAILJMPdND |
1457 | 1.45M | 0U, // tTAILJMPr |
1458 | 1.45M | 0U, // tTBB_JT |
1459 | 1.45M | 0U, // tTBH_JT |
1460 | 1.45M | 0U, // tTPsoft |
1461 | 1.45M | 2632970U, // ADCri |
1462 | 1.45M | 2632970U, // ADCrr |
1463 | 1.45M | 2690314U, // ADCrsi |
1464 | 1.45M | 77066U, // ADCrsr |
1465 | 1.45M | 2633038U, // ADDri |
1466 | 1.45M | 2633038U, // ADDrr |
1467 | 1.45M | 2690382U, // ADDrsi |
1468 | 1.45M | 77134U, // ADDrsr |
1469 | 1.45M | 2650529U, // ADR |
1470 | 1.45M | 808535656U, // AESD |
1471 | 1.45M | 808535664U, // AESE |
1472 | 1.45M | 875644501U, // AESIMC |
1473 | 1.45M | 875644511U, // AESMC |
1474 | 1.45M | 2633103U, // ANDri |
1475 | 1.45M | 2633103U, // ANDrr |
1476 | 1.45M | 2690447U, // ANDrsi |
1477 | 1.45M | 77199U, // ANDrsr |
1478 | 1.45M | 808543710U, // BF16VDOTI_VDOTD |
1479 | 1.45M | 808543710U, // BF16VDOTI_VDOTQ |
1480 | 1.45M | 808543710U, // BF16VDOTS_VDOTD |
1481 | 1.45M | 808543710U, // BF16VDOTS_VDOTQ |
1482 | 1.45M | 876114856U, // BF16_VCVT |
1483 | 1.45M | 809036979U, // BF16_VCVTB |
1484 | 1.45M | 809038742U, // BF16_VCVTT |
1485 | 1.45M | 2682130U, // BFC |
1486 | 1.45M | 2666240U, // BFI |
1487 | 1.45M | 2632983U, // BICri |
1488 | 1.45M | 2632983U, // BICrr |
1489 | 1.45M | 2690327U, // BICrsi |
1490 | 1.45M | 77079U, // BICrsr |
1491 | 1.45M | 4278212U, // BKPT |
1492 | 1.45M | 4294544U, // BL |
1493 | 1.45M | 4278266U, // BLX |
1494 | 1.45M | 2733469U, // BLX_pred |
1495 | 1.45M | 4294650U, // BLXi |
1496 | 1.45M | 942255953U, // BL_pred |
1497 | 1.45M | 4278262U, // BX |
1498 | 1.45M | 2731794U, // BXJ |
1499 | 1.45M | 4838647U, // BX_RET |
1500 | 1.45M | 2733303U, // BX_pred |
1501 | 1.45M | 942255028U, // Bcc |
1502 | 1.45M | 810672130U, // CDE_CX1 |
1503 | 1.45M | 1009298104U, // CDE_CX1A |
1504 | 1.45M | 1079633720U, // CDE_CX1D |
1505 | 1.45M | 1009298126U, // CDE_CX1DA |
1506 | 1.45M | 810672723U, // CDE_CX2 |
1507 | 1.45M | 1009306302U, // CDE_CX2A |
1508 | 1.45M | 1146742590U, // CDE_CX2D |
1509 | 1.45M | 1009306324U, // CDE_CX2DA |
1510 | 1.45M | 810672729U, // CDE_CX3 |
1511 | 1.45M | 1009388228U, // CDE_CX3A |
1512 | 1.45M | 1146742596U, // CDE_CX3D |
1513 | 1.45M | 1009388250U, // CDE_CX3DA |
1514 | 1.45M | 1213327062U, // CDE_VCX1A_fpdp |
1515 | 1.45M | 1213327062U, // CDE_VCX1A_fpsp |
1516 | 1.45M | 1009396407U, // CDE_VCX1A_vec |
1517 | 1.45M | 810672129U, // CDE_VCX1_fpdp |
1518 | 1.45M | 810672129U, // CDE_VCX1_fpsp |
1519 | 1.45M | 1009404180U, // CDE_VCX1_vec |
1520 | 1.45M | 1213327069U, // CDE_VCX2A_fpdp |
1521 | 1.45M | 1213327069U, // CDE_VCX2A_fpsp |
1522 | 1.45M | 1009412797U, // CDE_VCX2A_vec |
1523 | 1.45M | 810672722U, // CDE_VCX2_fpdp |
1524 | 1.45M | 810672722U, // CDE_VCX2_fpsp |
1525 | 1.45M | 1009396053U, // CDE_VCX2_vec |
1526 | 1.45M | 1213327076U, // CDE_VCX3A_fpdp |
1527 | 1.45M | 1213327076U, // CDE_VCX3A_fpsp |
1528 | 1.45M | 1009420995U, // CDE_VCX3A_vec |
1529 | 1.45M | 810672728U, // CDE_VCX3_fpdp |
1530 | 1.45M | 810672728U, // CDE_VCX3_fpsp |
1531 | 1.45M | 1009412458U, // CDE_VCX3_vec |
1532 | 1.45M | 1277825288U, // CDP |
1533 | 1.45M | 1348641343U, // CDP2 |
1534 | 1.45M | 5445U, // CLREX |
1535 | 1.45M | 2651636U, // CLZ |
1536 | 1.45M | 2650273U, // CMNri |
1537 | 1.45M | 2650273U, // CMNzrr |
1538 | 1.45M | 2683041U, // CMNzrsi |
1539 | 1.45M | 2666657U, // CMNzrsr |
1540 | 1.45M | 2650386U, // CMPri |
1541 | 1.45M | 2650386U, // CMPrr |
1542 | 1.45M | 2683154U, // CMPrsi |
1543 | 1.45M | 2666770U, // CMPrsr |
1544 | 1.45M | 4278196U, // CPS1p |
1545 | 1.45M | 1412092501U, // CPS2p |
1546 | 1.45M | 1412092501U, // CPS3p |
1547 | 1.45M | 875644665U, // CRC32B |
1548 | 1.45M | 875644673U, // CRC32CB |
1549 | 1.45M | 875644783U, // CRC32CH |
1550 | 1.45M | 875644903U, // CRC32CW |
1551 | 1.45M | 875644775U, // CRC32H |
1552 | 1.45M | 875644895U, // CRC32W |
1553 | 1.45M | 2731508U, // DBG |
1554 | 1.45M | 190232U, // DMB |
1555 | 1.45M | 190237U, // DSB |
1556 | 1.45M | 2634192U, // EORri |
1557 | 1.45M | 2634192U, // EORrr |
1558 | 1.45M | 2691536U, // EORrsi |
1559 | 1.45M | 78288U, // EORrsr |
1560 | 1.45M | 4313779U, // ERET |
1561 | 1.45M | 1147696202U, // FCONSTD |
1562 | 1.45M | 7369802U, // FCONSTH |
1563 | 1.45M | 7894090U, // FCONSTS |
1564 | 1.45M | 875066610U, // FLDMXDB_UPD |
1565 | 1.45M | 2733201U, // FLDMXIA |
1566 | 1.45M | 875066513U, // FLDMXIA_UPD |
1567 | 1.45M | 8507993U, // FMSTAT |
1568 | 1.45M | 875066618U, // FSTMXDB_UPD |
1569 | 1.45M | 2733209U, // FSTMXIA |
1570 | 1.45M | 875066521U, // FSTMXIA_UPD |
1571 | 1.45M | 2732808U, // HINT |
1572 | 1.45M | 4278207U, // HLT |
1573 | 1.45M | 4278067U, // HVC |
1574 | 1.45M | 198434U, // ISB |
1575 | 1.45M | 2648800U, // LDA |
1576 | 1.45M | 2649009U, // LDAB |
1577 | 1.45M | 2651443U, // LDAEX |
1578 | 1.45M | 2649320U, // LDAEXB |
1579 | 1.45M | 1479044523U, // LDAEXD |
1580 | 1.45M | 2649816U, // LDAEXH |
1581 | 1.45M | 2649616U, // LDAH |
1582 | 1.45M | 1552590722U, // LDC2L_OFFSET |
1583 | 1.45M | 1619699586U, // LDC2L_OPTION |
1584 | 1.45M | 1619699586U, // LDC2L_POST |
1585 | 1.45M | 9561986U, // LDC2L_PRE |
1586 | 1.45M | 1552589350U, // LDC2_OFFSET |
1587 | 1.45M | 1619698214U, // LDC2_OPTION |
1588 | 1.45M | 1619698214U, // LDC2_POST |
1589 | 1.45M | 9560614U, // LDC2_PRE |
1590 | 1.45M | 1277734746U, // LDCL_OFFSET |
1591 | 1.45M | 1277734746U, // LDCL_OPTION |
1592 | 1.45M | 1277734746U, // LDCL_POST |
1593 | 1.45M | 1009307482U, // LDCL_PRE |
1594 | 1.45M | 1277734158U, // LDC_OFFSET |
1595 | 1.45M | 1277734158U, // LDC_OPTION |
1596 | 1.45M | 1277734158U, // LDC_POST |
1597 | 1.45M | 1009306894U, // LDC_PRE |
1598 | 1.45M | 2730724U, // LDMDA |
1599 | 1.45M | 875064036U, // LDMDA_UPD |
1600 | 1.45M | 2730979U, // LDMDB |
1601 | 1.45M | 875064291U, // LDMDB_UPD |
1602 | 1.45M | 2732107U, // LDMIA |
1603 | 1.45M | 875065419U, // LDMIA_UPD |
1604 | 1.45M | 2730998U, // LDMIB |
1605 | 1.45M | 875064310U, // LDMIB_UPD |
1606 | 1.45M | 2675360U, // LDRBT_POST_IMM |
1607 | 1.45M | 2675360U, // LDRBT_POST_REG |
1608 | 1.45M | 2673786U, // LDRB_POST_IMM |
1609 | 1.45M | 2673786U, // LDRB_POST_REG |
1610 | 1.45M | 2665594U, // LDRB_PRE_IMM |
1611 | 1.45M | 2673786U, // LDRB_PRE_REG |
1612 | 1.45M | 2681978U, // LDRBi12 |
1613 | 1.45M | 2665594U, // LDRBrs |
1614 | 1.45M | 2674068U, // LDRD |
1615 | 1.45M | 2755988U, // LDRD_POST |
1616 | 1.45M | 2755988U, // LDRD_PRE |
1617 | 1.45M | 2651455U, // LDREX |
1618 | 1.45M | 2649334U, // LDREXB |
1619 | 1.45M | 1479044537U, // LDREXD |
1620 | 1.45M | 2649830U, // LDREXH |
1621 | 1.45M | 2666112U, // LDRH |
1622 | 1.45M | 2667203U, // LDRHTi |
1623 | 1.45M | 2675395U, // LDRHTr |
1624 | 1.45M | 2674304U, // LDRH_POST |
1625 | 1.45M | 2674304U, // LDRH_PRE |
1626 | 1.45M | 2665613U, // LDRSB |
1627 | 1.45M | 2667180U, // LDRSBTi |
1628 | 1.45M | 2675372U, // LDRSBTr |
1629 | 1.45M | 2673805U, // LDRSB_POST |
1630 | 1.45M | 2673805U, // LDRSB_PRE |
1631 | 1.45M | 2666151U, // LDRSH |
1632 | 1.45M | 2667215U, // LDRSHTi |
1633 | 1.45M | 2675407U, // LDRSHTr |
1634 | 1.45M | 2674343U, // LDRSH_POST |
1635 | 1.45M | 2674343U, // LDRSH_PRE |
1636 | 1.45M | 2675554U, // LDRT_POST_IMM |
1637 | 1.45M | 2675554U, // LDRT_POST_REG |
1638 | 1.45M | 2675110U, // LDR_POST_IMM |
1639 | 1.45M | 2675110U, // LDR_POST_REG |
1640 | 1.45M | 2666918U, // LDR_PRE_IMM |
1641 | 1.45M | 2675110U, // LDR_PRE_REG |
1642 | 1.45M | 2683302U, // LDRcp |
1643 | 1.45M | 2683302U, // LDRi12 |
1644 | 1.45M | 2666918U, // LDRrs |
1645 | 1.45M | 1277825437U, // MCR |
1646 | 1.45M | 811770437U, // MCR2 |
1647 | 1.45M | 1277743576U, // MCRR |
1648 | 1.45M | 811770443U, // MCRR2 |
1649 | 1.45M | 2689828U, // MLA |
1650 | 1.45M | 2667053U, // MLS |
1651 | 1.45M | 10081355U, // MOVPCLR |
1652 | 1.45M | 2683821U, // MOVTi16 |
1653 | 1.45M | 2659403U, // MOVi |
1654 | 1.45M | 2651250U, // MOVi16 |
1655 | 1.45M | 2659403U, // MOVr |
1656 | 1.45M | 2659403U, // MOVr_TC |
1657 | 1.45M | 2634827U, // MOVsi |
1658 | 1.45M | 2692171U, // MOVsr |
1659 | 1.45M | 1009388837U, // MRC |
1660 | 1.45M | 10609196U, // MRC2 |
1661 | 1.45M | 1680395561U, // MRRC |
1662 | 1.45M | 205362U, // MRRC2 |
1663 | 1.45M | 2732634U, // MRS |
1664 | 1.45M | 2650714U, // MRSbanked |
1665 | 1.45M | 2732634U, // MRSsys |
1666 | 1.45M | 1747481070U, // MSR |
1667 | 1.45M | 1814589934U, // MSRbanked |
1668 | 1.45M | 1747481070U, // MSRi |
1669 | 1.45M | 2633774U, // MUL |
1670 | 1.45M | 2674699U, // MVE_ASRLi |
1671 | 1.45M | 2674699U, // MVE_ASRLr |
1672 | 1.45M | 875643877U, // MVE_DLSTP_16 |
1673 | 1.45M | 875643124U, // MVE_DLSTP_32 |
1674 | 1.45M | 875643486U, // MVE_DLSTP_64 |
1675 | 1.45M | 875644536U, // MVE_DLSTP_8 |
1676 | 1.45M | 1076482381U, // MVE_LCTP |
1677 | 1.45M | 1882285988U, // MVE_LETP |
1678 | 1.45M | 2674646U, // MVE_LSLLi |
1679 | 1.45M | 2674646U, // MVE_LSLLr |
1680 | 1.45M | 2674704U, // MVE_LSRL |
1681 | 1.45M | 875098538U, // MVE_SQRSHR |
1682 | 1.45M | 2756597U, // MVE_SQRSHRL |
1683 | 1.45M | 875097985U, // MVE_SQSHL |
1684 | 1.45M | 2674618U, // MVE_SQSHLL |
1685 | 1.45M | 875098545U, // MVE_SRSHR |
1686 | 1.45M | 2674685U, // MVE_SRSHRL |
1687 | 1.45M | 875098003U, // MVE_UQRSHL |
1688 | 1.45M | 2756552U, // MVE_UQRSHLL |
1689 | 1.45M | 875097991U, // MVE_UQSHL |
1690 | 1.45M | 2674625U, // MVE_UQSHLL |
1691 | 1.45M | 875098551U, // MVE_URSHR |
1692 | 1.45M | 2674692U, // MVE_URSHRL |
1693 | 1.45M | 11154380U, // MVE_VABAVs16 |
1694 | 1.45M | 11678668U, // MVE_VABAVs32 |
1695 | 1.45M | 12202956U, // MVE_VABAVs8 |
1696 | 1.45M | 12727244U, // MVE_VABAVu16 |
1697 | 1.45M | 13251532U, // MVE_VABAVu32 |
1698 | 1.45M | 13775820U, // MVE_VABAVu8 |
1699 | 1.45M | 7490886U, // MVE_VABDf16 |
1700 | 1.45M | 8015174U, // MVE_VABDf32 |
1701 | 1.45M | 11160902U, // MVE_VABDs16 |
1702 | 1.45M | 11685190U, // MVE_VABDs32 |
1703 | 1.45M | 12209478U, // MVE_VABDs8 |
1704 | 1.45M | 12733766U, // MVE_VABDu16 |
1705 | 1.45M | 13258054U, // MVE_VABDu32 |
1706 | 1.45M | 13782342U, // MVE_VABDu8 |
1707 | 1.45M | 7557660U, // MVE_VABSf16 |
1708 | 1.45M | 8081948U, // MVE_VABSf32 |
1709 | 1.45M | 11227676U, // MVE_VABSs16 |
1710 | 1.45M | 11751964U, // MVE_VABSs32 |
1711 | 1.45M | 12276252U, // MVE_VABSs8 |
1712 | 1.45M | 14314761U, // MVE_VADC |
1713 | 1.45M | 14298874U, // MVE_VADCI |
1714 | 1.45M | 11692963U, // MVE_VADDLVs32acc |
1715 | 1.45M | 11686957U, // MVE_VADDLVs32no_acc |
1716 | 1.45M | 13265827U, // MVE_VADDLVu32acc |
1717 | 1.45M | 13259821U, // MVE_VADDLVu32no_acc |
1718 | 1.45M | 11160476U, // MVE_VADDVs16acc |
1719 | 1.45M | 11228180U, // MVE_VADDVs16no_acc |
1720 | 1.45M | 11684764U, // MVE_VADDVs32acc |
1721 | 1.45M | 11752468U, // MVE_VADDVs32no_acc |
1722 | 1.45M | 12209052U, // MVE_VADDVs8acc |
1723 | 1.45M | 12276756U, // MVE_VADDVs8no_acc |
1724 | 1.45M | 12733340U, // MVE_VADDVu16acc |
1725 | 1.45M | 12801044U, // MVE_VADDVu16no_acc |
1726 | 1.45M | 13257628U, // MVE_VADDVu32acc |
1727 | 1.45M | 13325332U, // MVE_VADDVu32no_acc |
1728 | 1.45M | 13781916U, // MVE_VADDVu8acc |
1729 | 1.45M | 13849620U, // MVE_VADDVu8no_acc |
1730 | 1.45M | 7490935U, // MVE_VADD_qr_f16 |
1731 | 1.45M | 8015223U, // MVE_VADD_qr_f32 |
1732 | 1.45M | 14830967U, // MVE_VADD_qr_i16 |
1733 | 1.45M | 14306679U, // MVE_VADD_qr_i32 |
1734 | 1.45M | 15355255U, // MVE_VADD_qr_i8 |
1735 | 1.45M | 7490935U, // MVE_VADDf16 |
1736 | 1.45M | 8015223U, // MVE_VADDf32 |
1737 | 1.45M | 14830967U, // MVE_VADDi16 |
1738 | 1.45M | 14306679U, // MVE_VADDi32 |
1739 | 1.45M | 15355255U, // MVE_VADDi8 |
1740 | 1.45M | 2772366U, // MVE_VAND |
1741 | 1.45M | 2772246U, // MVE_VBIC |
1742 | 1.45M | 14830870U, // MVE_VBICimmi16 |
1743 | 1.45M | 14306582U, // MVE_VBICimmi32 |
1744 | 1.45M | 676338U, // MVE_VBRSR16 |
1745 | 1.45M | 1200626U, // MVE_VBRSR32 |
1746 | 1.45M | 1724914U, // MVE_VBRSR8 |
1747 | 1.45M | 7482706U, // MVE_VCADDf16 |
1748 | 1.45M | 8006994U, // MVE_VCADDf32 |
1749 | 1.45M | 14822738U, // MVE_VCADDi16 |
1750 | 1.45M | 14298450U, // MVE_VCADDi32 |
1751 | 1.45M | 15347026U, // MVE_VCADDi8 |
1752 | 1.45M | 11227686U, // MVE_VCLSs16 |
1753 | 1.45M | 11751974U, // MVE_VCLSs32 |
1754 | 1.45M | 12276262U, // MVE_VCLSs8 |
1755 | 1.45M | 14898675U, // MVE_VCLZs16 |
1756 | 1.45M | 14374387U, // MVE_VCLZs32 |
1757 | 1.45M | 15422963U, // MVE_VCLZs8 |
1758 | 1.45M | 7498530U, // MVE_VCMLAf16 |
1759 | 1.45M | 8022818U, // MVE_VCMLAf32 |
1760 | 1.45M | 1953640721U, // MVE_VCMPf16 |
1761 | 1.45M | 1953640721U, // MVE_VCMPf16r |
1762 | 1.45M | 1954165009U, // MVE_VCMPf32 |
1763 | 1.45M | 1954165009U, // MVE_VCMPf32r |
1764 | 1.45M | 1960980753U, // MVE_VCMPi16 |
1765 | 1.45M | 1960980753U, // MVE_VCMPi16r |
1766 | 1.45M | 1960456465U, // MVE_VCMPi32 |
1767 | 1.45M | 1960456465U, // MVE_VCMPi32r |
1768 | 1.45M | 1961505041U, // MVE_VCMPi8 |
1769 | 1.45M | 1961505041U, // MVE_VCMPi8r |
1770 | 1.45M | 1957310737U, // MVE_VCMPs16 |
1771 | 1.45M | 1957310737U, // MVE_VCMPs16r |
1772 | 1.45M | 1957835025U, // MVE_VCMPs32 |
1773 | 1.45M | 1957835025U, // MVE_VCMPs32r |
1774 | 1.45M | 1958359313U, // MVE_VCMPs8 |
1775 | 1.45M | 1958359313U, // MVE_VCMPs8r |
1776 | 1.45M | 1958883601U, // MVE_VCMPu16 |
1777 | 1.45M | 1958883601U, // MVE_VCMPu16r |
1778 | 1.45M | 1959407889U, // MVE_VCMPu32 |
1779 | 1.45M | 1959407889U, // MVE_VCMPu32r |
1780 | 1.45M | 1959932177U, // MVE_VCMPu8 |
1781 | 1.45M | 1959932177U, // MVE_VCMPu8r |
1782 | 1.45M | 7483436U, // MVE_VCMULf16 |
1783 | 1.45M | 8007724U, // MVE_VCMULf32 |
1784 | 1.45M | 873156946U, // MVE_VCTP16 |
1785 | 1.45M | 873681234U, // MVE_VCTP32 |
1786 | 1.45M | 888361298U, // MVE_VCTP64 |
1787 | 1.45M | 874205522U, // MVE_VCTP8 |
1788 | 1.45M | 821710003U, // MVE_VCVTf16f32bh |
1789 | 1.45M | 821711766U, // MVE_VCVTf16f32th |
1790 | 1.45M | 1157780392U, // MVE_VCVTf16s16_fix |
1791 | 1.45M | 1090737064U, // MVE_VCVTf16s16n |
1792 | 1.45M | 1158304680U, // MVE_VCVTf16u16_fix |
1793 | 1.45M | 1091261352U, // MVE_VCVTf16u16n |
1794 | 1.45M | 18042035U, // MVE_VCVTf32f16bh |
1795 | 1.45M | 18043798U, // MVE_VCVTf32f16th |
1796 | 1.45M | 1159353256U, // MVE_VCVTf32s32_fix |
1797 | 1.45M | 1092309928U, // MVE_VCVTf32s32n |
1798 | 1.45M | 1159877544U, // MVE_VCVTf32u32_fix |
1799 | 1.45M | 1092834216U, // MVE_VCVTf32u32n |
1800 | 1.45M | 1160401832U, // MVE_VCVTs16f16_fix |
1801 | 1.45M | 1093356400U, // MVE_VCVTs16f16a |
1802 | 1.45M | 1093357682U, // MVE_VCVTs16f16m |
1803 | 1.45M | 1093357778U, // MVE_VCVTs16f16n |
1804 | 1.45M | 1093357918U, // MVE_VCVTs16f16p |
1805 | 1.45M | 1093358504U, // MVE_VCVTs16f16z |
1806 | 1.45M | 1160926120U, // MVE_VCVTs32f32_fix |
1807 | 1.45M | 1093880688U, // MVE_VCVTs32f32a |
1808 | 1.45M | 1093881970U, // MVE_VCVTs32f32m |
1809 | 1.45M | 1093882066U, // MVE_VCVTs32f32n |
1810 | 1.45M | 1093882206U, // MVE_VCVTs32f32p |
1811 | 1.45M | 1093882792U, // MVE_VCVTs32f32z |
1812 | 1.45M | 1161450408U, // MVE_VCVTu16f16_fix |
1813 | 1.45M | 1094404976U, // MVE_VCVTu16f16a |
1814 | 1.45M | 1094406258U, // MVE_VCVTu16f16m |
1815 | 1.45M | 1094406354U, // MVE_VCVTu16f16n |
1816 | 1.45M | 1094406494U, // MVE_VCVTu16f16p |
1817 | 1.45M | 1094407080U, // MVE_VCVTu16f16z |
1818 | 1.45M | 1161974696U, // MVE_VCVTu32f32_fix |
1819 | 1.45M | 1094929264U, // MVE_VCVTu32f32a |
1820 | 1.45M | 1094930546U, // MVE_VCVTu32f32m |
1821 | 1.45M | 1094930642U, // MVE_VCVTu32f32n |
1822 | 1.45M | 1094930782U, // MVE_VCVTu32f32p |
1823 | 1.45M | 1094931368U, // MVE_VCVTu32f32z |
1824 | 1.45M | 12726628U, // MVE_VDDUPu16 |
1825 | 1.45M | 13250916U, // MVE_VDDUPu32 |
1826 | 1.45M | 13775204U, // MVE_VDDUPu8 |
1827 | 1.45M | 741744U, // MVE_VDUP16 |
1828 | 1.45M | 1266032U, // MVE_VDUP32 |
1829 | 1.45M | 1790320U, // MVE_VDUP8 |
1830 | 1.45M | 12743029U, // MVE_VDWDUPu16 |
1831 | 1.45M | 13267317U, // MVE_VDWDUPu32 |
1832 | 1.45M | 13791605U, // MVE_VDWDUPu8 |
1833 | 1.45M | 2773455U, // MVE_VEOR |
1834 | 1.45M | 7483920U, // MVE_VFMA_qr_Sf16 |
1835 | 1.45M | 8008208U, // MVE_VFMA_qr_Sf32 |
1836 | 1.45M | 7482169U, // MVE_VFMA_qr_f16 |
1837 | 1.45M | 8006457U, // MVE_VFMA_qr_f32 |
1838 | 1.45M | 7482169U, // MVE_VFMAf16 |
1839 | 1.45M | 8006457U, // MVE_VFMAf32 |
1840 | 1.45M | 7483964U, // MVE_VFMSf16 |
1841 | 1.45M | 8008252U, // MVE_VFMSf32 |
1842 | 1.45M | 11160933U, // MVE_VHADD_qr_s16 |
1843 | 1.45M | 11685221U, // MVE_VHADD_qr_s32 |
1844 | 1.45M | 12209509U, // MVE_VHADD_qr_s8 |
1845 | 1.45M | 12733797U, // MVE_VHADD_qr_u16 |
1846 | 1.45M | 13258085U, // MVE_VHADD_qr_u32 |
1847 | 1.45M | 13782373U, // MVE_VHADD_qr_u8 |
1848 | 1.45M | 11160933U, // MVE_VHADDs16 |
1849 | 1.45M | 11685221U, // MVE_VHADDs32 |
1850 | 1.45M | 12209509U, // MVE_VHADDs8 |
1851 | 1.45M | 12733797U, // MVE_VHADDu16 |
1852 | 1.45M | 13258085U, // MVE_VHADDu32 |
1853 | 1.45M | 13782373U, // MVE_VHADDu8 |
1854 | 1.45M | 11152715U, // MVE_VHCADDs16 |
1855 | 1.45M | 11677003U, // MVE_VHCADDs32 |
1856 | 1.45M | 12201291U, // MVE_VHCADDs8 |
1857 | 1.45M | 11160777U, // MVE_VHSUB_qr_s16 |
1858 | 1.45M | 11685065U, // MVE_VHSUB_qr_s32 |
1859 | 1.45M | 12209353U, // MVE_VHSUB_qr_s8 |
1860 | 1.45M | 12733641U, // MVE_VHSUB_qr_u16 |
1861 | 1.45M | 13257929U, // MVE_VHSUB_qr_u32 |
1862 | 1.45M | 13782217U, // MVE_VHSUB_qr_u8 |
1863 | 1.45M | 11160777U, // MVE_VHSUBs16 |
1864 | 1.45M | 11685065U, // MVE_VHSUBs32 |
1865 | 1.45M | 12209353U, // MVE_VHSUBs8 |
1866 | 1.45M | 12733641U, // MVE_VHSUBu16 |
1867 | 1.45M | 13257929U, // MVE_VHSUBu32 |
1868 | 1.45M | 13782217U, // MVE_VHSUBu8 |
1869 | 1.45M | 12726634U, // MVE_VIDUPu16 |
1870 | 1.45M | 13250922U, // MVE_VIDUPu32 |
1871 | 1.45M | 13775210U, // MVE_VIDUPu8 |
1872 | 1.45M | 12743036U, // MVE_VIWDUPu16 |
1873 | 1.45M | 13267324U, // MVE_VIWDUPu32 |
1874 | 1.45M | 13791612U, // MVE_VIWDUPu8 |
1875 | 1.45M | 21717869U, // MVE_VLD20_16 |
1876 | 1.45M | 22242157U, // MVE_VLD20_16_wb |
1877 | 1.45M | 21716999U, // MVE_VLD20_32 |
1878 | 1.45M | 22241287U, // MVE_VLD20_32_wb |
1879 | 1.45M | 21718505U, // MVE_VLD20_8 |
1880 | 1.45M | 22242793U, // MVE_VLD20_8_wb |
1881 | 1.45M | 21717909U, // MVE_VLD21_16 |
1882 | 1.45M | 22242197U, // MVE_VLD21_16_wb |
1883 | 1.45M | 21717065U, // MVE_VLD21_32 |
1884 | 1.45M | 22241353U, // MVE_VLD21_32_wb |
1885 | 1.45M | 21718541U, // MVE_VLD21_8 |
1886 | 1.45M | 22242829U, // MVE_VLD21_8_wb |
1887 | 1.45M | 21726081U, // MVE_VLD40_16 |
1888 | 1.45M | 22250369U, // MVE_VLD40_16_wb |
1889 | 1.45M | 21725211U, // MVE_VLD40_32 |
1890 | 1.45M | 22249499U, // MVE_VLD40_32_wb |
1891 | 1.45M | 21726715U, // MVE_VLD40_8 |
1892 | 1.45M | 22251003U, // MVE_VLD40_8_wb |
1893 | 1.45M | 21726121U, // MVE_VLD41_16 |
1894 | 1.45M | 22250409U, // MVE_VLD41_16_wb |
1895 | 1.45M | 21725277U, // MVE_VLD41_32 |
1896 | 1.45M | 22249565U, // MVE_VLD41_32_wb |
1897 | 1.45M | 21726751U, // MVE_VLD41_8 |
1898 | 1.45M | 22251039U, // MVE_VLD41_8_wb |
1899 | 1.45M | 21726141U, // MVE_VLD42_16 |
1900 | 1.45M | 22250429U, // MVE_VLD42_16_wb |
1901 | 1.45M | 21725323U, // MVE_VLD42_32 |
1902 | 1.45M | 22249611U, // MVE_VLD42_32_wb |
1903 | 1.45M | 21726769U, // MVE_VLD42_8 |
1904 | 1.45M | 22251057U, // MVE_VLD42_8_wb |
1905 | 1.45M | 21726161U, // MVE_VLD43_16 |
1906 | 1.45M | 22250449U, // MVE_VLD43_16_wb |
1907 | 1.45M | 21725356U, // MVE_VLD43_32 |
1908 | 1.45M | 22249644U, // MVE_VLD43_32_wb |
1909 | 1.45M | 21726787U, // MVE_VLD43_8 |
1910 | 1.45M | 22251075U, // MVE_VLD43_8_wb |
1911 | 1.45M | 11160697U, // MVE_VLDRBS16 |
1912 | 1.45M | 883567737U, // MVE_VLDRBS16_post |
1913 | 1.45M | 883567737U, // MVE_VLDRBS16_pre |
1914 | 1.45M | 11160697U, // MVE_VLDRBS16_rq |
1915 | 1.45M | 11684985U, // MVE_VLDRBS32 |
1916 | 1.45M | 884092025U, // MVE_VLDRBS32_post |
1917 | 1.45M | 884092025U, // MVE_VLDRBS32_pre |
1918 | 1.45M | 11684985U, // MVE_VLDRBS32_rq |
1919 | 1.45M | 12733561U, // MVE_VLDRBU16 |
1920 | 1.45M | 885140601U, // MVE_VLDRBU16_post |
1921 | 1.45M | 885140601U, // MVE_VLDRBU16_pre |
1922 | 1.45M | 12733561U, // MVE_VLDRBU16_rq |
1923 | 1.45M | 13257849U, // MVE_VLDRBU32 |
1924 | 1.45M | 885664889U, // MVE_VLDRBU32_post |
1925 | 1.45M | 885664889U, // MVE_VLDRBU32_pre |
1926 | 1.45M | 13257849U, // MVE_VLDRBU32_rq |
1927 | 1.45M | 13782137U, // MVE_VLDRBU8 |
1928 | 1.45M | 886189177U, // MVE_VLDRBU8_post |
1929 | 1.45M | 886189177U, // MVE_VLDRBU8_pre |
1930 | 1.45M | 13782137U, // MVE_VLDRBU8_rq |
1931 | 1.45M | 22695315U, // MVE_VLDRDU64_qi |
1932 | 1.45M | 895102355U, // MVE_VLDRDU64_qi_pre |
1933 | 1.45M | 22695315U, // MVE_VLDRDU64_rq |
1934 | 1.45M | 22695315U, // MVE_VLDRDU64_rq_u |
1935 | 1.45M | 11685503U, // MVE_VLDRHS32 |
1936 | 1.45M | 884092543U, // MVE_VLDRHS32_post |
1937 | 1.45M | 884092543U, // MVE_VLDRHS32_pre |
1938 | 1.45M | 11685503U, // MVE_VLDRHS32_rq |
1939 | 1.45M | 11685503U, // MVE_VLDRHS32_rq_u |
1940 | 1.45M | 12734079U, // MVE_VLDRHU16 |
1941 | 1.45M | 885141119U, // MVE_VLDRHU16_post |
1942 | 1.45M | 885141119U, // MVE_VLDRHU16_pre |
1943 | 1.45M | 12734079U, // MVE_VLDRHU16_rq |
1944 | 1.45M | 12734079U, // MVE_VLDRHU16_rq_u |
1945 | 1.45M | 13258367U, // MVE_VLDRHU32 |
1946 | 1.45M | 885665407U, // MVE_VLDRHU32_post |
1947 | 1.45M | 885665407U, // MVE_VLDRHU32_pre |
1948 | 1.45M | 13258367U, // MVE_VLDRHU32_rq |
1949 | 1.45M | 13258367U, // MVE_VLDRHU32_rq_u |
1950 | 1.45M | 13259878U, // MVE_VLDRWU32 |
1951 | 1.45M | 885666918U, // MVE_VLDRWU32_post |
1952 | 1.45M | 885666918U, // MVE_VLDRWU32_pre |
1953 | 1.45M | 13259878U, // MVE_VLDRWU32_qi |
1954 | 1.45M | 885666918U, // MVE_VLDRWU32_qi_pre |
1955 | 1.45M | 13259878U, // MVE_VLDRWU32_rq |
1956 | 1.45M | 13259878U, // MVE_VLDRWU32_rq_u |
1957 | 1.45M | 883577869U, // MVE_VMAXAVs16 |
1958 | 1.45M | 884102157U, // MVE_VMAXAVs32 |
1959 | 1.45M | 884626445U, // MVE_VMAXAVs8 |
1960 | 1.45M | 11160491U, // MVE_VMAXAs16 |
1961 | 1.45M | 11684779U, // MVE_VMAXAs32 |
1962 | 1.45M | 12209067U, // MVE_VMAXAs8 |
1963 | 1.45M | 879907837U, // MVE_VMAXNMAVf16 |
1964 | 1.45M | 880432125U, // MVE_VMAXNMAVf32 |
1965 | 1.45M | 7490380U, // MVE_VMAXNMAf16 |
1966 | 1.45M | 8014668U, // MVE_VMAXNMAf32 |
1967 | 1.45M | 879907900U, // MVE_VMAXNMVf16 |
1968 | 1.45M | 880432188U, // MVE_VMAXNMVf32 |
1969 | 1.45M | 7491670U, // MVE_VMAXNMf16 |
1970 | 1.45M | 8015958U, // MVE_VMAXNMf32 |
1971 | 1.45M | 883577935U, // MVE_VMAXVs16 |
1972 | 1.45M | 884102223U, // MVE_VMAXVs32 |
1973 | 1.45M | 884626511U, // MVE_VMAXVs8 |
1974 | 1.45M | 885150799U, // MVE_VMAXVu16 |
1975 | 1.45M | 885675087U, // MVE_VMAXVu32 |
1976 | 1.45M | 886199375U, // MVE_VMAXVu8 |
1977 | 1.45M | 11162791U, // MVE_VMAXs16 |
1978 | 1.45M | 11687079U, // MVE_VMAXs32 |
1979 | 1.45M | 12211367U, // MVE_VMAXs8 |
1980 | 1.45M | 12735655U, // MVE_VMAXu16 |
1981 | 1.45M | 13259943U, // MVE_VMAXu32 |
1982 | 1.45M | 13784231U, // MVE_VMAXu8 |
1983 | 1.45M | 883577862U, // MVE_VMINAVs16 |
1984 | 1.45M | 884102150U, // MVE_VMINAVs32 |
1985 | 1.45M | 884626438U, // MVE_VMINAVs8 |
1986 | 1.45M | 11160404U, // MVE_VMINAs16 |
1987 | 1.45M | 11684692U, // MVE_VMINAs32 |
1988 | 1.45M | 12208980U, // MVE_VMINAs8 |
1989 | 1.45M | 879907828U, // MVE_VMINNMAVf16 |
1990 | 1.45M | 880432116U, // MVE_VMINNMAVf32 |
1991 | 1.45M | 7490372U, // MVE_VMINNMAf16 |
1992 | 1.45M | 8014660U, // MVE_VMINNMAf32 |
1993 | 1.45M | 879907892U, // MVE_VMINNMVf16 |
1994 | 1.45M | 880432180U, // MVE_VMINNMVf32 |
1995 | 1.45M | 7491663U, // MVE_VMINNMf16 |
1996 | 1.45M | 8015951U, // MVE_VMINNMf32 |
1997 | 1.45M | 883577924U, // MVE_VMINVs16 |
1998 | 1.45M | 884102212U, // MVE_VMINVs32 |
1999 | 1.45M | 884626500U, // MVE_VMINVs8 |
2000 | 1.45M | 885150788U, // MVE_VMINVu16 |
2001 | 1.45M | 885675076U, // MVE_VMINVu32 |
2002 | 1.45M | 886199364U, // MVE_VMINVu8 |
2003 | 1.45M | 11161756U, // MVE_VMINs16 |
2004 | 1.45M | 11686044U, // MVE_VMINs32 |
2005 | 1.45M | 12210332U, // MVE_VMINs8 |
2006 | 1.45M | 12734620U, // MVE_VMINu16 |
2007 | 1.45M | 13258908U, // MVE_VMINu32 |
2008 | 1.45M | 13783196U, // MVE_VMINu8 |
2009 | 1.45M | 11152246U, // MVE_VMLADAVas16 |
2010 | 1.45M | 11676534U, // MVE_VMLADAVas32 |
2011 | 1.45M | 12200822U, // MVE_VMLADAVas8 |
2012 | 1.45M | 12725110U, // MVE_VMLADAVau16 |
2013 | 1.45M | 13249398U, // MVE_VMLADAVau32 |
2014 | 1.45M | 13773686U, // MVE_VMLADAVau8 |
2015 | 1.45M | 11154632U, // MVE_VMLADAVaxs16 |
2016 | 1.45M | 11678920U, // MVE_VMLADAVaxs32 |
2017 | 1.45M | 12203208U, // MVE_VMLADAVaxs8 |
2018 | 1.45M | 11162578U, // MVE_VMLADAVs16 |
2019 | 1.45M | 11686866U, // MVE_VMLADAVs32 |
2020 | 1.45M | 12211154U, // MVE_VMLADAVs8 |
2021 | 1.45M | 12735442U, // MVE_VMLADAVu16 |
2022 | 1.45M | 13259730U, // MVE_VMLADAVu32 |
2023 | 1.45M | 13784018U, // MVE_VMLADAVu8 |
2024 | 1.45M | 11163085U, // MVE_VMLADAVxs16 |
2025 | 1.45M | 11687373U, // MVE_VMLADAVxs32 |
2026 | 1.45M | 12211661U, // MVE_VMLADAVxs8 |
2027 | 1.45M | 11176831U, // MVE_VMLALDAVas16 |
2028 | 1.45M | 11701119U, // MVE_VMLALDAVas32 |
2029 | 1.45M | 12749695U, // MVE_VMLALDAVau16 |
2030 | 1.45M | 13273983U, // MVE_VMLALDAVau32 |
2031 | 1.45M | 11179218U, // MVE_VMLALDAVaxs16 |
2032 | 1.45M | 11703506U, // MVE_VMLALDAVaxs32 |
2033 | 1.45M | 11154394U, // MVE_VMLALDAVs16 |
2034 | 1.45M | 11678682U, // MVE_VMLALDAVs32 |
2035 | 1.45M | 12727258U, // MVE_VMLALDAVu16 |
2036 | 1.45M | 13251546U, // MVE_VMLALDAVu32 |
2037 | 1.45M | 11154902U, // MVE_VMLALDAVxs16 |
2038 | 1.45M | 11679190U, // MVE_VMLALDAVxs32 |
2039 | 1.45M | 14823946U, // MVE_VMLAS_qr_i16 |
2040 | 1.45M | 14299658U, // MVE_VMLAS_qr_i32 |
2041 | 1.45M | 15348234U, // MVE_VMLAS_qr_i8 |
2042 | 1.45M | 14822196U, // MVE_VMLA_qr_i16 |
2043 | 1.45M | 14297908U, // MVE_VMLA_qr_i32 |
2044 | 1.45M | 15346484U, // MVE_VMLA_qr_i8 |
2045 | 1.45M | 11152275U, // MVE_VMLSDAVas16 |
2046 | 1.45M | 11676563U, // MVE_VMLSDAVas32 |
2047 | 1.45M | 12200851U, // MVE_VMLSDAVas8 |
2048 | 1.45M | 11154664U, // MVE_VMLSDAVaxs16 |
2049 | 1.45M | 11678952U, // MVE_VMLSDAVaxs32 |
2050 | 1.45M | 12203240U, // MVE_VMLSDAVaxs8 |
2051 | 1.45M | 11162604U, // MVE_VMLSDAVs16 |
2052 | 1.45M | 11686892U, // MVE_VMLSDAVs32 |
2053 | 1.45M | 12211180U, // MVE_VMLSDAVs8 |
2054 | 1.45M | 11163114U, // MVE_VMLSDAVxs16 |
2055 | 1.45M | 11687402U, // MVE_VMLSDAVxs32 |
2056 | 1.45M | 12211690U, // MVE_VMLSDAVxs8 |
2057 | 1.45M | 11176841U, // MVE_VMLSLDAVas16 |
2058 | 1.45M | 11701129U, // MVE_VMLSLDAVas32 |
2059 | 1.45M | 11179229U, // MVE_VMLSLDAVaxs16 |
2060 | 1.45M | 11703517U, // MVE_VMLSLDAVaxs32 |
2061 | 1.45M | 11154403U, // MVE_VMLSLDAVs16 |
2062 | 1.45M | 11678691U, // MVE_VMLSLDAVs32 |
2063 | 1.45M | 11154912U, // MVE_VMLSLDAVxs16 |
2064 | 1.45M | 11679200U, // MVE_VMLSLDAVxs32 |
2065 | 1.45M | 11226142U, // MVE_VMOVLs16bh |
2066 | 1.45M | 11227900U, // MVE_VMOVLs16th |
2067 | 1.45M | 12274718U, // MVE_VMOVLs8bh |
2068 | 1.45M | 12276476U, // MVE_VMOVLs8th |
2069 | 1.45M | 12799006U, // MVE_VMOVLu16bh |
2070 | 1.45M | 12800764U, // MVE_VMOVLu16th |
2071 | 1.45M | 13847582U, // MVE_VMOVLu8bh |
2072 | 1.45M | 13849340U, // MVE_VMOVLu8th |
2073 | 1.45M | 14830701U, // MVE_VMOVNi16bh |
2074 | 1.45M | 14832465U, // MVE_VMOVNi16th |
2075 | 1.45M | 14306413U, // MVE_VMOVNi32bh |
2076 | 1.45M | 14308177U, // MVE_VMOVNi32th |
2077 | 1.45M | 1111114U, // MVE_VMOV_from_lane_32 |
2078 | 1.45M | 11072586U, // MVE_VMOV_from_lane_s16 |
2079 | 1.45M | 12121162U, // MVE_VMOV_from_lane_s8 |
2080 | 1.45M | 12645450U, // MVE_VMOV_from_lane_u16 |
2081 | 1.45M | 13694026U, // MVE_VMOV_from_lane_u8 |
2082 | 1.45M | 2757706U, // MVE_VMOV_q_rr |
2083 | 1.45M | 2675786U, // MVE_VMOV_rr_q |
2084 | 1.45M | 570442U, // MVE_VMOV_to_lane_16 |
2085 | 1.45M | 1094730U, // MVE_VMOV_to_lane_32 |
2086 | 1.45M | 1619018U, // MVE_VMOV_to_lane_8 |
2087 | 1.45M | 8082506U, // MVE_VMOVimmf32 |
2088 | 1.45M | 14898250U, // MVE_VMOVimmi16 |
2089 | 1.45M | 14373962U, // MVE_VMOVimmi32 |
2090 | 1.45M | 2036552778U, // MVE_VMOVimmi64 |
2091 | 1.45M | 15422538U, // MVE_VMOVimmi8 |
2092 | 1.45M | 11161209U, // MVE_VMULHs16 |
2093 | 1.45M | 11685497U, // MVE_VMULHs32 |
2094 | 1.45M | 12209785U, // MVE_VMULHs8 |
2095 | 1.45M | 12734073U, // MVE_VMULHu16 |
2096 | 1.45M | 13258361U, // MVE_VMULHu32 |
2097 | 1.45M | 13782649U, // MVE_VMULHu8 |
2098 | 1.45M | 23743506U, // MVE_VMULLBp16 |
2099 | 1.45M | 24267794U, // MVE_VMULLBp8 |
2100 | 1.45M | 11160594U, // MVE_VMULLBs16 |
2101 | 1.45M | 11684882U, // MVE_VMULLBs32 |
2102 | 1.45M | 12209170U, // MVE_VMULLBs8 |
2103 | 1.45M | 12733458U, // MVE_VMULLBu16 |
2104 | 1.45M | 13257746U, // MVE_VMULLBu32 |
2105 | 1.45M | 13782034U, // MVE_VMULLBu8 |
2106 | 1.45M | 23745269U, // MVE_VMULLTp16 |
2107 | 1.45M | 24269557U, // MVE_VMULLTp8 |
2108 | 1.45M | 11162357U, // MVE_VMULLTs16 |
2109 | 1.45M | 11686645U, // MVE_VMULLTs32 |
2110 | 1.45M | 12210933U, // MVE_VMULLTs8 |
2111 | 1.45M | 12735221U, // MVE_VMULLTu16 |
2112 | 1.45M | 13259509U, // MVE_VMULLTu32 |
2113 | 1.45M | 13783797U, // MVE_VMULLTu8 |
2114 | 1.45M | 7491646U, // MVE_VMUL_qr_f16 |
2115 | 1.45M | 8015934U, // MVE_VMUL_qr_f32 |
2116 | 1.45M | 14831678U, // MVE_VMUL_qr_i16 |
2117 | 1.45M | 14307390U, // MVE_VMUL_qr_i32 |
2118 | 1.45M | 15355966U, // MVE_VMUL_qr_i8 |
2119 | 1.45M | 7491646U, // MVE_VMULf16 |
2120 | 1.45M | 8015934U, // MVE_VMULf32 |
2121 | 1.45M | 14831678U, // MVE_VMULi16 |
2122 | 1.45M | 14307390U, // MVE_VMULi32 |
2123 | 1.45M | 15355966U, // MVE_VMULi8 |
2124 | 1.45M | 2838769U, // MVE_VMVN |
2125 | 1.45M | 14897393U, // MVE_VMVNimmi16 |
2126 | 1.45M | 14373105U, // MVE_VMVNimmi32 |
2127 | 1.45M | 7556611U, // MVE_VNEGf16 |
2128 | 1.45M | 8080899U, // MVE_VNEGf32 |
2129 | 1.45M | 11226627U, // MVE_VNEGs16 |
2130 | 1.45M | 11750915U, // MVE_VNEGs32 |
2131 | 1.45M | 12275203U, // MVE_VNEGs8 |
2132 | 1.45M | 2773185U, // MVE_VORN |
2133 | 1.45M | 2773469U, // MVE_VORR |
2134 | 1.45M | 14832093U, // MVE_VORRimmi16 |
2135 | 1.45M | 14307805U, // MVE_VORRimmi32 |
2136 | 1.45M | 1076581208U, // MVE_VPNOT |
2137 | 1.45M | 2772855U, // MVE_VPSEL |
2138 | 1.45M | 1076605810U, // MVE_VPST |
2139 | 1.45M | 1961603934U, // MVE_VPTv16i8 |
2140 | 1.45M | 1961603934U, // MVE_VPTv16i8r |
2141 | 1.45M | 1958458206U, // MVE_VPTv16s8 |
2142 | 1.45M | 1958458206U, // MVE_VPTv16s8r |
2143 | 1.45M | 1960031070U, // MVE_VPTv16u8 |
2144 | 1.45M | 1960031070U, // MVE_VPTv16u8r |
2145 | 1.45M | 1954263902U, // MVE_VPTv4f32 |
2146 | 1.45M | 1954263902U, // MVE_VPTv4f32r |
2147 | 1.45M | 1960555358U, // MVE_VPTv4i32 |
2148 | 1.45M | 1960555358U, // MVE_VPTv4i32r |
2149 | 1.45M | 1957933918U, // MVE_VPTv4s32 |
2150 | 1.45M | 1957933918U, // MVE_VPTv4s32r |
2151 | 1.45M | 1959506782U, // MVE_VPTv4u32 |
2152 | 1.45M | 1959506782U, // MVE_VPTv4u32r |
2153 | 1.45M | 1953739614U, // MVE_VPTv8f16 |
2154 | 1.45M | 1953739614U, // MVE_VPTv8f16r |
2155 | 1.45M | 1961079646U, // MVE_VPTv8i16 |
2156 | 1.45M | 1961079646U, // MVE_VPTv8i16r |
2157 | 1.45M | 1957409630U, // MVE_VPTv8s16 |
2158 | 1.45M | 1957409630U, // MVE_VPTv8s16r |
2159 | 1.45M | 1958982494U, // MVE_VPTv8u16 |
2160 | 1.45M | 1958982494U, // MVE_VPTv8u16r |
2161 | 1.45M | 11227670U, // MVE_VQABSs16 |
2162 | 1.45M | 11751958U, // MVE_VQABSs32 |
2163 | 1.45M | 12276246U, // MVE_VQABSs8 |
2164 | 1.45M | 11160945U, // MVE_VQADD_qr_s16 |
2165 | 1.45M | 11685233U, // MVE_VQADD_qr_s32 |
2166 | 1.45M | 12209521U, // MVE_VQADD_qr_s8 |
2167 | 1.45M | 12733809U, // MVE_VQADD_qr_u16 |
2168 | 1.45M | 13258097U, // MVE_VQADD_qr_u32 |
2169 | 1.45M | 13782385U, // MVE_VQADD_qr_u8 |
2170 | 1.45M | 11160945U, // MVE_VQADDs16 |
2171 | 1.45M | 11685233U, // MVE_VQADDs32 |
2172 | 1.45M | 12209521U, // MVE_VQADDs8 |
2173 | 1.45M | 12733809U, // MVE_VQADDu16 |
2174 | 1.45M | 13258097U, // MVE_VQADDu32 |
2175 | 1.45M | 13782385U, // MVE_VQADDu8 |
2176 | 1.45M | 11154779U, // MVE_VQDMLADHXs16 |
2177 | 1.45M | 11679067U, // MVE_VQDMLADHXs32 |
2178 | 1.45M | 12203355U, // MVE_VQDMLADHXs8 |
2179 | 1.45M | 11152950U, // MVE_VQDMLADHs16 |
2180 | 1.45M | 11677238U, // MVE_VQDMLADHs32 |
2181 | 1.45M | 12201526U, // MVE_VQDMLADHs8 |
2182 | 1.45M | 11152917U, // MVE_VQDMLAH_qrs16 |
2183 | 1.45M | 11677205U, // MVE_VQDMLAH_qrs32 |
2184 | 1.45M | 12201493U, // MVE_VQDMLAH_qrs8 |
2185 | 1.45M | 11153035U, // MVE_VQDMLASH_qrs16 |
2186 | 1.45M | 11677323U, // MVE_VQDMLASH_qrs32 |
2187 | 1.45M | 12201611U, // MVE_VQDMLASH_qrs8 |
2188 | 1.45M | 11154800U, // MVE_VQDMLSDHXs16 |
2189 | 1.45M | 11679088U, // MVE_VQDMLSDHXs32 |
2190 | 1.45M | 12203376U, // MVE_VQDMLSDHXs8 |
2191 | 1.45M | 11152969U, // MVE_VQDMLSDHs16 |
2192 | 1.45M | 11677257U, // MVE_VQDMLSDHs32 |
2193 | 1.45M | 12201545U, // MVE_VQDMLSDHs8 |
2194 | 1.45M | 11161185U, // MVE_VQDMULH_qr_s16 |
2195 | 1.45M | 11685473U, // MVE_VQDMULH_qr_s32 |
2196 | 1.45M | 12209761U, // MVE_VQDMULH_qr_s8 |
2197 | 1.45M | 11161185U, // MVE_VQDMULHi16 |
2198 | 1.45M | 11685473U, // MVE_VQDMULHi32 |
2199 | 1.45M | 12209761U, // MVE_VQDMULHi8 |
2200 | 1.45M | 11160585U, // MVE_VQDMULL_qr_s16bh |
2201 | 1.45M | 11162348U, // MVE_VQDMULL_qr_s16th |
2202 | 1.45M | 11684873U, // MVE_VQDMULL_qr_s32bh |
2203 | 1.45M | 11686636U, // MVE_VQDMULL_qr_s32th |
2204 | 1.45M | 11160585U, // MVE_VQDMULLs16bh |
2205 | 1.45M | 11162348U, // MVE_VQDMULLs16th |
2206 | 1.45M | 11684873U, // MVE_VQDMULLs32bh |
2207 | 1.45M | 11686636U, // MVE_VQDMULLs32th |
2208 | 1.45M | 11160677U, // MVE_VQMOVNs16bh |
2209 | 1.45M | 11162441U, // MVE_VQMOVNs16th |
2210 | 1.45M | 11684965U, // MVE_VQMOVNs32bh |
2211 | 1.45M | 11686729U, // MVE_VQMOVNs32th |
2212 | 1.45M | 12733541U, // MVE_VQMOVNu16bh |
2213 | 1.45M | 12735305U, // MVE_VQMOVNu16th |
2214 | 1.45M | 13257829U, // MVE_VQMOVNu32bh |
2215 | 1.45M | 13259593U, // MVE_VQMOVNu32th |
2216 | 1.45M | 11160668U, // MVE_VQMOVUNs16bh |
2217 | 1.45M | 11162432U, // MVE_VQMOVUNs16th |
2218 | 1.45M | 11684956U, // MVE_VQMOVUNs32bh |
2219 | 1.45M | 11686720U, // MVE_VQMOVUNs32th |
2220 | 1.45M | 11226621U, // MVE_VQNEGs16 |
2221 | 1.45M | 11750909U, // MVE_VQNEGs32 |
2222 | 1.45M | 12275197U, // MVE_VQNEGs8 |
2223 | 1.45M | 11154789U, // MVE_VQRDMLADHXs16 |
2224 | 1.45M | 11679077U, // MVE_VQRDMLADHXs32 |
2225 | 1.45M | 12203365U, // MVE_VQRDMLADHXs8 |
2226 | 1.45M | 11152959U, // MVE_VQRDMLADHs16 |
2227 | 1.45M | 11677247U, // MVE_VQRDMLADHs32 |
2228 | 1.45M | 12201535U, // MVE_VQRDMLADHs8 |
2229 | 1.45M | 11152925U, // MVE_VQRDMLAH_qrs16 |
2230 | 1.45M | 11677213U, // MVE_VQRDMLAH_qrs32 |
2231 | 1.45M | 12201501U, // MVE_VQRDMLAH_qrs8 |
2232 | 1.45M | 11153044U, // MVE_VQRDMLASH_qrs16 |
2233 | 1.45M | 11677332U, // MVE_VQRDMLASH_qrs32 |
2234 | 1.45M | 12201620U, // MVE_VQRDMLASH_qrs8 |
2235 | 1.45M | 11154810U, // MVE_VQRDMLSDHXs16 |
2236 | 1.45M | 11679098U, // MVE_VQRDMLSDHXs32 |
2237 | 1.45M | 12203386U, // MVE_VQRDMLSDHXs8 |
2238 | 1.45M | 11152978U, // MVE_VQRDMLSDHs16 |
2239 | 1.45M | 11677266U, // MVE_VQRDMLSDHs32 |
2240 | 1.45M | 12201554U, // MVE_VQRDMLSDHs8 |
2241 | 1.45M | 11161193U, // MVE_VQRDMULH_qr_s16 |
2242 | 1.45M | 11685481U, // MVE_VQRDMULH_qr_s32 |
2243 | 1.45M | 12209769U, // MVE_VQRDMULH_qr_s8 |
2244 | 1.45M | 11161193U, // MVE_VQRDMULHi16 |
2245 | 1.45M | 11685481U, // MVE_VQRDMULHi32 |
2246 | 1.45M | 12209769U, // MVE_VQRDMULHi8 |
2247 | 1.45M | 11161498U, // MVE_VQRSHL_by_vecs16 |
2248 | 1.45M | 11685786U, // MVE_VQRSHL_by_vecs32 |
2249 | 1.45M | 12210074U, // MVE_VQRSHL_by_vecs8 |
2250 | 1.45M | 12734362U, // MVE_VQRSHL_by_vecu16 |
2251 | 1.45M | 13258650U, // MVE_VQRSHL_by_vecu32 |
2252 | 1.45M | 13782938U, // MVE_VQRSHL_by_vecu8 |
2253 | 1.45M | 11161498U, // MVE_VQRSHL_qrs16 |
2254 | 1.45M | 11685786U, // MVE_VQRSHL_qrs32 |
2255 | 1.45M | 12210074U, // MVE_VQRSHL_qrs8 |
2256 | 1.45M | 12734362U, // MVE_VQRSHL_qru16 |
2257 | 1.45M | 13258650U, // MVE_VQRSHL_qru32 |
2258 | 1.45M | 13782938U, // MVE_VQRSHL_qru8 |
2259 | 1.45M | 11152433U, // MVE_VQRSHRNbhs16 |
2260 | 1.45M | 11676721U, // MVE_VQRSHRNbhs32 |
2261 | 1.45M | 12725297U, // MVE_VQRSHRNbhu16 |
2262 | 1.45M | 13249585U, // MVE_VQRSHRNbhu32 |
2263 | 1.45M | 11154197U, // MVE_VQRSHRNths16 |
2264 | 1.45M | 11678485U, // MVE_VQRSHRNths32 |
2265 | 1.45M | 12727061U, // MVE_VQRSHRNthu16 |
2266 | 1.45M | 13251349U, // MVE_VQRSHRNthu32 |
2267 | 1.45M | 11152466U, // MVE_VQRSHRUNs16bh |
2268 | 1.45M | 11154230U, // MVE_VQRSHRUNs16th |
2269 | 1.45M | 11676754U, // MVE_VQRSHRUNs32bh |
2270 | 1.45M | 11678518U, // MVE_VQRSHRUNs32th |
2271 | 1.45M | 11162565U, // MVE_VQSHLU_imms16 |
2272 | 1.45M | 11686853U, // MVE_VQSHLU_imms32 |
2273 | 1.45M | 12211141U, // MVE_VQSHLU_imms8 |
2274 | 1.45M | 11161485U, // MVE_VQSHL_by_vecs16 |
2275 | 1.45M | 11685773U, // MVE_VQSHL_by_vecs32 |
2276 | 1.45M | 12210061U, // MVE_VQSHL_by_vecs8 |
2277 | 1.45M | 12734349U, // MVE_VQSHL_by_vecu16 |
2278 | 1.45M | 13258637U, // MVE_VQSHL_by_vecu32 |
2279 | 1.45M | 13782925U, // MVE_VQSHL_by_vecu8 |
2280 | 1.45M | 11161485U, // MVE_VQSHL_qrs16 |
2281 | 1.45M | 11685773U, // MVE_VQSHL_qrs32 |
2282 | 1.45M | 12210061U, // MVE_VQSHL_qrs8 |
2283 | 1.45M | 12734349U, // MVE_VQSHL_qru16 |
2284 | 1.45M | 13258637U, // MVE_VQSHL_qru32 |
2285 | 1.45M | 13782925U, // MVE_VQSHL_qru8 |
2286 | 1.45M | 11161485U, // MVE_VQSHLimms16 |
2287 | 1.45M | 11685773U, // MVE_VQSHLimms32 |
2288 | 1.45M | 12210061U, // MVE_VQSHLimms8 |
2289 | 1.45M | 12734349U, // MVE_VQSHLimmu16 |
2290 | 1.45M | 13258637U, // MVE_VQSHLimmu32 |
2291 | 1.45M | 13782925U, // MVE_VQSHLimmu8 |
2292 | 1.45M | 11152425U, // MVE_VQSHRNbhs16 |
2293 | 1.45M | 11676713U, // MVE_VQSHRNbhs32 |
2294 | 1.45M | 12725289U, // MVE_VQSHRNbhu16 |
2295 | 1.45M | 13249577U, // MVE_VQSHRNbhu32 |
2296 | 1.45M | 11154189U, // MVE_VQSHRNths16 |
2297 | 1.45M | 11678477U, // MVE_VQSHRNths32 |
2298 | 1.45M | 12727053U, // MVE_VQSHRNthu16 |
2299 | 1.45M | 13251341U, // MVE_VQSHRNthu32 |
2300 | 1.45M | 11152457U, // MVE_VQSHRUNs16bh |
2301 | 1.45M | 11154221U, // MVE_VQSHRUNs16th |
2302 | 1.45M | 11676745U, // MVE_VQSHRUNs32bh |
2303 | 1.45M | 11678509U, // MVE_VQSHRUNs32th |
2304 | 1.45M | 11160783U, // MVE_VQSUB_qr_s16 |
2305 | 1.45M | 11685071U, // MVE_VQSUB_qr_s32 |
2306 | 1.45M | 12209359U, // MVE_VQSUB_qr_s8 |
2307 | 1.45M | 12733647U, // MVE_VQSUB_qr_u16 |
2308 | 1.45M | 13257935U, // MVE_VQSUB_qr_u32 |
2309 | 1.45M | 13782223U, // MVE_VQSUB_qr_u8 |
2310 | 1.45M | 11160783U, // MVE_VQSUBs16 |
2311 | 1.45M | 11685071U, // MVE_VQSUBs32 |
2312 | 1.45M | 12209359U, // MVE_VQSUBs8 |
2313 | 1.45M | 12733647U, // MVE_VQSUBu16 |
2314 | 1.45M | 13257935U, // MVE_VQSUBu32 |
2315 | 1.45M | 13782223U, // MVE_VQSUBu8 |
2316 | 1.45M | 1788408U, // MVE_VREV16_8 |
2317 | 1.45M | 739609U, // MVE_VREV32_16 |
2318 | 1.45M | 1788185U, // MVE_VREV32_8 |
2319 | 1.45M | 739695U, // MVE_VREV64_16 |
2320 | 1.45M | 1263983U, // MVE_VREV64_32 |
2321 | 1.45M | 1788271U, // MVE_VREV64_8 |
2322 | 1.45M | 11160926U, // MVE_VRHADDs16 |
2323 | 1.45M | 11685214U, // MVE_VRHADDs32 |
2324 | 1.45M | 12209502U, // MVE_VRHADDs8 |
2325 | 1.45M | 12733790U, // MVE_VRHADDu16 |
2326 | 1.45M | 13258078U, // MVE_VRHADDu32 |
2327 | 1.45M | 13782366U, // MVE_VRHADDu8 |
2328 | 1.45M | 7555941U, // MVE_VRINTf16A |
2329 | 1.45M | 7557221U, // MVE_VRINTf16M |
2330 | 1.45M | 7557323U, // MVE_VRINTf16N |
2331 | 1.45M | 7557463U, // MVE_VRINTf16P |
2332 | 1.45M | 7558598U, // MVE_VRINTf16X |
2333 | 1.45M | 7558648U, // MVE_VRINTf16Z |
2334 | 1.45M | 8080229U, // MVE_VRINTf32A |
2335 | 1.45M | 8081509U, // MVE_VRINTf32M |
2336 | 1.45M | 8081611U, // MVE_VRINTf32N |
2337 | 1.45M | 8081751U, // MVE_VRINTf32P |
2338 | 1.45M | 8082886U, // MVE_VRINTf32X |
2339 | 1.45M | 8082936U, // MVE_VRINTf32Z |
2340 | 1.45M | 11700976U, // MVE_VRMLALDAVHas32 |
2341 | 1.45M | 13273840U, // MVE_VRMLALDAVHau32 |
2342 | 1.45M | 11703415U, // MVE_VRMLALDAVHaxs32 |
2343 | 1.45M | 11677378U, // MVE_VRMLALDAVHs32 |
2344 | 1.45M | 13250242U, // MVE_VRMLALDAVHu32 |
2345 | 1.45M | 11679109U, // MVE_VRMLALDAVHxs32 |
2346 | 1.45M | 11700988U, // MVE_VRMLSLDAVHas32 |
2347 | 1.45M | 11703428U, // MVE_VRMLSLDAVHaxs32 |
2348 | 1.45M | 11677389U, // MVE_VRMLSLDAVHs32 |
2349 | 1.45M | 11679121U, // MVE_VRMLSLDAVHxs32 |
2350 | 1.45M | 11161202U, // MVE_VRMULHs16 |
2351 | 1.45M | 11685490U, // MVE_VRMULHs32 |
2352 | 1.45M | 12209778U, // MVE_VRMULHs8 |
2353 | 1.45M | 12734066U, // MVE_VRMULHu16 |
2354 | 1.45M | 13258354U, // MVE_VRMULHu32 |
2355 | 1.45M | 13782642U, // MVE_VRMULHu8 |
2356 | 1.45M | 11161505U, // MVE_VRSHL_by_vecs16 |
2357 | 1.45M | 11685793U, // MVE_VRSHL_by_vecs32 |
2358 | 1.45M | 12210081U, // MVE_VRSHL_by_vecs8 |
2359 | 1.45M | 12734369U, // MVE_VRSHL_by_vecu16 |
2360 | 1.45M | 13258657U, // MVE_VRSHL_by_vecu32 |
2361 | 1.45M | 13782945U, // MVE_VRSHL_by_vecu8 |
2362 | 1.45M | 11161505U, // MVE_VRSHL_qrs16 |
2363 | 1.45M | 11685793U, // MVE_VRSHL_qrs32 |
2364 | 1.45M | 12210081U, // MVE_VRSHL_qrs8 |
2365 | 1.45M | 12734369U, // MVE_VRSHL_qru16 |
2366 | 1.45M | 13258657U, // MVE_VRSHL_qru32 |
2367 | 1.45M | 13782945U, // MVE_VRSHL_qru8 |
2368 | 1.45M | 14822458U, // MVE_VRSHRNi16bh |
2369 | 1.45M | 14824222U, // MVE_VRSHRNi16th |
2370 | 1.45M | 14298170U, // MVE_VRSHRNi32bh |
2371 | 1.45M | 14299934U, // MVE_VRSHRNi32th |
2372 | 1.45M | 11162045U, // MVE_VRSHR_imms16 |
2373 | 1.45M | 11686333U, // MVE_VRSHR_imms32 |
2374 | 1.45M | 12210621U, // MVE_VRSHR_imms8 |
2375 | 1.45M | 12734909U, // MVE_VRSHR_immu16 |
2376 | 1.45M | 13259197U, // MVE_VRSHR_immu32 |
2377 | 1.45M | 13783485U, // MVE_VRSHR_immu8 |
2378 | 1.45M | 14314756U, // MVE_VSBC |
2379 | 1.45M | 14298868U, // MVE_VSBCI |
2380 | 1.45M | 808086811U, // MVE_VSHLC |
2381 | 1.45M | 11160578U, // MVE_VSHLL_imms16bh |
2382 | 1.45M | 11162341U, // MVE_VSHLL_imms16th |
2383 | 1.45M | 12209154U, // MVE_VSHLL_imms8bh |
2384 | 1.45M | 12210917U, // MVE_VSHLL_imms8th |
2385 | 1.45M | 12733442U, // MVE_VSHLL_immu16bh |
2386 | 1.45M | 12735205U, // MVE_VSHLL_immu16th |
2387 | 1.45M | 13782018U, // MVE_VSHLL_immu8bh |
2388 | 1.45M | 13783781U, // MVE_VSHLL_immu8th |
2389 | 1.45M | 11226114U, // MVE_VSHLL_lws16bh |
2390 | 1.45M | 11227877U, // MVE_VSHLL_lws16th |
2391 | 1.45M | 12274690U, // MVE_VSHLL_lws8bh |
2392 | 1.45M | 12276453U, // MVE_VSHLL_lws8th |
2393 | 1.45M | 12798978U, // MVE_VSHLL_lwu16bh |
2394 | 1.45M | 12800741U, // MVE_VSHLL_lwu16th |
2395 | 1.45M | 13847554U, // MVE_VSHLL_lwu8bh |
2396 | 1.45M | 13849317U, // MVE_VSHLL_lwu8th |
2397 | 1.45M | 11161511U, // MVE_VSHL_by_vecs16 |
2398 | 1.45M | 11685799U, // MVE_VSHL_by_vecs32 |
2399 | 1.45M | 12210087U, // MVE_VSHL_by_vecs8 |
2400 | 1.45M | 12734375U, // MVE_VSHL_by_vecu16 |
2401 | 1.45M | 13258663U, // MVE_VSHL_by_vecu32 |
2402 | 1.45M | 13782951U, // MVE_VSHL_by_vecu8 |
2403 | 1.45M | 14831527U, // MVE_VSHL_immi16 |
2404 | 1.45M | 14307239U, // MVE_VSHL_immi32 |
2405 | 1.45M | 15355815U, // MVE_VSHL_immi8 |
2406 | 1.45M | 11161511U, // MVE_VSHL_qrs16 |
2407 | 1.45M | 11685799U, // MVE_VSHL_qrs32 |
2408 | 1.45M | 12210087U, // MVE_VSHL_qrs8 |
2409 | 1.45M | 12734375U, // MVE_VSHL_qru16 |
2410 | 1.45M | 13258663U, // MVE_VSHL_qru32 |
2411 | 1.45M | 13782951U, // MVE_VSHL_qru8 |
2412 | 1.45M | 14822466U, // MVE_VSHRNi16bh |
2413 | 1.45M | 14824230U, // MVE_VSHRNi16th |
2414 | 1.45M | 14298178U, // MVE_VSHRNi32bh |
2415 | 1.45M | 14299942U, // MVE_VSHRNi32th |
2416 | 1.45M | 11162051U, // MVE_VSHR_imms16 |
2417 | 1.45M | 11686339U, // MVE_VSHR_imms32 |
2418 | 1.45M | 12210627U, // MVE_VSHR_imms8 |
2419 | 1.45M | 12734915U, // MVE_VSHR_immu16 |
2420 | 1.45M | 13259203U, // MVE_VSHR_immu32 |
2421 | 1.45M | 13783491U, // MVE_VSHR_immu8 |
2422 | 1.45M | 667400U, // MVE_VSLIimm16 |
2423 | 1.45M | 1191688U, // MVE_VSLIimm32 |
2424 | 1.45M | 1715976U, // MVE_VSLIimm8 |
2425 | 1.45M | 667405U, // MVE_VSRIimm16 |
2426 | 1.45M | 1191693U, // MVE_VSRIimm32 |
2427 | 1.45M | 1715981U, // MVE_VSRIimm8 |
2428 | 1.45M | 24863607U, // MVE_VST20_16 |
2429 | 1.45M | 246647U, // MVE_VST20_16_wb |
2430 | 1.45M | 24862737U, // MVE_VST20_32 |
2431 | 1.45M | 245777U, // MVE_VST20_32_wb |
2432 | 1.45M | 24864242U, // MVE_VST20_8 |
2433 | 1.45M | 247282U, // MVE_VST20_8_wb |
2434 | 1.45M | 24863647U, // MVE_VST21_16 |
2435 | 1.45M | 246687U, // MVE_VST21_16_wb |
2436 | 1.45M | 24862803U, // MVE_VST21_32 |
2437 | 1.45M | 245843U, // MVE_VST21_32_wb |
2438 | 1.45M | 24864278U, // MVE_VST21_8 |
2439 | 1.45M | 247318U, // MVE_VST21_8_wb |
2440 | 1.45M | 24871819U, // MVE_VST40_16 |
2441 | 1.45M | 254859U, // MVE_VST40_16_wb |
2442 | 1.45M | 24870949U, // MVE_VST40_32 |
2443 | 1.45M | 253989U, // MVE_VST40_32_wb |
2444 | 1.45M | 24872452U, // MVE_VST40_8 |
2445 | 1.45M | 255492U, // MVE_VST40_8_wb |
2446 | 1.45M | 24871859U, // MVE_VST41_16 |
2447 | 1.45M | 254899U, // MVE_VST41_16_wb |
2448 | 1.45M | 24871015U, // MVE_VST41_32 |
2449 | 1.45M | 254055U, // MVE_VST41_32_wb |
2450 | 1.45M | 24872488U, // MVE_VST41_8 |
2451 | 1.45M | 255528U, // MVE_VST41_8_wb |
2452 | 1.45M | 24871879U, // MVE_VST42_16 |
2453 | 1.45M | 254919U, // MVE_VST42_16_wb |
2454 | 1.45M | 24871061U, // MVE_VST42_32 |
2455 | 1.45M | 254101U, // MVE_VST42_32_wb |
2456 | 1.45M | 24872506U, // MVE_VST42_8 |
2457 | 1.45M | 255546U, // MVE_VST42_8_wb |
2458 | 1.45M | 24871899U, // MVE_VST43_16 |
2459 | 1.45M | 254939U, // MVE_VST43_16_wb |
2460 | 1.45M | 24871094U, // MVE_VST43_32 |
2461 | 1.45M | 254134U, // MVE_VST43_32_wb |
2462 | 1.45M | 24872524U, // MVE_VST43_8 |
2463 | 1.45M | 255564U, // MVE_VST43_8_wb |
2464 | 1.45M | 674943U, // MVE_VSTRB16 |
2465 | 1.45M | 873081983U, // MVE_VSTRB16_post |
2466 | 1.45M | 873081983U, // MVE_VSTRB16_pre |
2467 | 1.45M | 674943U, // MVE_VSTRB16_rq |
2468 | 1.45M | 1199231U, // MVE_VSTRB32 |
2469 | 1.45M | 873606271U, // MVE_VSTRB32_post |
2470 | 1.45M | 873606271U, // MVE_VSTRB32_pre |
2471 | 1.45M | 1199231U, // MVE_VSTRB32_rq |
2472 | 1.45M | 1723519U, // MVE_VSTRB8_rq |
2473 | 1.45M | 1723519U, // MVE_VSTRBU8 |
2474 | 1.45M | 874130559U, // MVE_VSTRBU8_post |
2475 | 1.45M | 874130559U, // MVE_VSTRBU8_pre |
2476 | 1.45M | 15879577U, // MVE_VSTRD64_qi |
2477 | 1.45M | 888286617U, // MVE_VSTRD64_qi_pre |
2478 | 1.45M | 15879577U, // MVE_VSTRD64_rq |
2479 | 1.45M | 15879577U, // MVE_VSTRD64_rq_u |
2480 | 1.45M | 675461U, // MVE_VSTRH16_rq |
2481 | 1.45M | 675461U, // MVE_VSTRH16_rq_u |
2482 | 1.45M | 1199749U, // MVE_VSTRH32 |
2483 | 1.45M | 873606789U, // MVE_VSTRH32_post |
2484 | 1.45M | 873606789U, // MVE_VSTRH32_pre |
2485 | 1.45M | 1199749U, // MVE_VSTRH32_rq |
2486 | 1.45M | 1199749U, // MVE_VSTRH32_rq_u |
2487 | 1.45M | 675461U, // MVE_VSTRHU16 |
2488 | 1.45M | 873082501U, // MVE_VSTRHU16_post |
2489 | 1.45M | 873082501U, // MVE_VSTRHU16_pre |
2490 | 1.45M | 1201260U, // MVE_VSTRW32_qi |
2491 | 1.45M | 873608300U, // MVE_VSTRW32_qi_pre |
2492 | 1.45M | 1201260U, // MVE_VSTRW32_rq |
2493 | 1.45M | 1201260U, // MVE_VSTRW32_rq_u |
2494 | 1.45M | 1201260U, // MVE_VSTRWU32 |
2495 | 1.45M | 873608300U, // MVE_VSTRWU32_post |
2496 | 1.45M | 873608300U, // MVE_VSTRWU32_pre |
2497 | 1.45M | 7490773U, // MVE_VSUB_qr_f16 |
2498 | 1.45M | 8015061U, // MVE_VSUB_qr_f32 |
2499 | 1.45M | 14830805U, // MVE_VSUB_qr_i16 |
2500 | 1.45M | 14306517U, // MVE_VSUB_qr_i32 |
2501 | 1.45M | 15355093U, // MVE_VSUB_qr_i8 |
2502 | 1.45M | 7490773U, // MVE_VSUBf16 |
2503 | 1.45M | 8015061U, // MVE_VSUBf32 |
2504 | 1.45M | 14830805U, // MVE_VSUBi16 |
2505 | 1.45M | 14306517U, // MVE_VSUBi32 |
2506 | 1.45M | 15355093U, // MVE_VSUBi8 |
2507 | 1.45M | 875643887U, // MVE_WLSTP_16 |
2508 | 1.45M | 875643134U, // MVE_WLSTP_32 |
2509 | 1.45M | 875643496U, // MVE_WLSTP_64 |
2510 | 1.45M | 875644545U, // MVE_WLSTP_8 |
2511 | 1.45M | 2658546U, // MVNi |
2512 | 1.45M | 2658546U, // MVNr |
2513 | 1.45M | 2633970U, // MVNsi |
2514 | 1.45M | 2691314U, // MVNsr |
2515 | 1.45M | 875643322U, // NEON_VMAXNMNDf |
2516 | 1.45M | 875644217U, // NEON_VMAXNMNDh |
2517 | 1.45M | 875643322U, // NEON_VMAXNMNQf |
2518 | 1.45M | 875644217U, // NEON_VMAXNMNQh |
2519 | 1.45M | 875643310U, // NEON_VMINNMNDf |
2520 | 1.45M | 875644205U, // NEON_VMINNMNDh |
2521 | 1.45M | 875643310U, // NEON_VMINNMNQf |
2522 | 1.45M | 875644205U, // NEON_VMINNMNQh |
2523 | 1.45M | 2634206U, // ORRri |
2524 | 1.45M | 2634206U, // ORRrr |
2525 | 1.45M | 2691550U, // ORRrsi |
2526 | 1.45M | 78302U, // ORRrsr |
2527 | 1.45M | 2667147U, // PKHBT |
2528 | 1.45M | 2665630U, // PKHTB |
2529 | 1.45M | 264176U, // PLDWi12 |
2530 | 1.45M | 272368U, // PLDWrs |
2531 | 1.45M | 264010U, // PLDi12 |
2532 | 1.45M | 272202U, // PLDrs |
2533 | 1.45M | 264056U, // PLIi12 |
2534 | 1.45M | 272248U, // PLIrs |
2535 | 1.45M | 2682226U, // QADD |
2536 | 1.45M | 2681301U, // QADD16 |
2537 | 1.45M | 2681404U, // QADD8 |
2538 | 1.45M | 2684343U, // QASX |
2539 | 1.45M | 2682200U, // QDADD |
2540 | 1.45M | 2682051U, // QDSUB |
2541 | 1.45M | 2684089U, // QSAX |
2542 | 1.45M | 2682064U, // QSUB |
2543 | 1.45M | 2681263U, // QSUB16 |
2544 | 1.45M | 2681365U, // QSUB8 |
2545 | 1.45M | 2650838U, // RBIT |
2546 | 1.45M | 2651162U, // REV |
2547 | 1.45M | 2648569U, // REV16 |
2548 | 1.45M | 2649778U, // REVSH |
2549 | 1.45M | 4277995U, // RFEDA |
2550 | 1.45M | 25257707U, // RFEDA_UPD |
2551 | 1.45M | 4278026U, // RFEDB |
2552 | 1.45M | 25257738U, // RFEDB_UPD |
2553 | 1.45M | 4278002U, // RFEIA |
2554 | 1.45M | 25257714U, // RFEIA_UPD |
2555 | 1.45M | 4278033U, // RFEIB |
2556 | 1.45M | 25257745U, // RFEIB_UPD |
2557 | 1.45M | 2632847U, // RSBri |
2558 | 1.45M | 2632847U, // RSBrr |
2559 | 1.45M | 2690191U, // RSBrsi |
2560 | 1.45M | 76943U, // RSBrsr |
2561 | 1.45M | 2633006U, // RSCri |
2562 | 1.45M | 2633006U, // RSCrr |
2563 | 1.45M | 2690350U, // RSCrsi |
2564 | 1.45M | 77102U, // RSCrsr |
2565 | 1.45M | 2681308U, // SADD16 |
2566 | 1.45M | 2681410U, // SADD8 |
2567 | 1.45M | 2684348U, // SASX |
2568 | 1.45M | 3206U, // SB |
2569 | 1.45M | 2632965U, // SBCri |
2570 | 1.45M | 2632965U, // SBCrr |
2571 | 1.45M | 2690309U, // SBCrsi |
2572 | 1.45M | 77061U, // SBCrsr |
2573 | 1.45M | 2667857U, // SBFX |
2574 | 1.45M | 2683934U, // SDIV |
2575 | 1.45M | 2682745U, // SEL |
2576 | 1.45M | 280399U, // SETEND |
2577 | 1.45M | 4278172U, // SETPAN |
2578 | 1.45M | 808534208U, // SHA1C |
2579 | 1.45M | 875643082U, // SHA1H |
2580 | 1.45M | 808534240U, // SHA1M |
2581 | 1.45M | 808534250U, // SHA1P |
2582 | 1.45M | 808534063U, // SHA1SU0 |
2583 | 1.45M | 808534129U, // SHA1SU1 |
2584 | 1.45M | 808534228U, // SHA256H |
2585 | 1.45M | 808534175U, // SHA256H2 |
2586 | 1.45M | 808534075U, // SHA256SU0 |
2587 | 1.45M | 808534141U, // SHA256SU1 |
2588 | 1.45M | 2681284U, // SHADD16 |
2589 | 1.45M | 2681389U, // SHADD8 |
2590 | 1.45M | 2684330U, // SHASX |
2591 | 1.45M | 2684076U, // SHSAX |
2592 | 1.45M | 2681246U, // SHSUB16 |
2593 | 1.45M | 2681350U, // SHSUB8 |
2594 | 1.45M | 2731297U, // SMC |
2595 | 1.45M | 2665410U, // SMLABB |
2596 | 1.45M | 2667140U, // SMLABT |
2597 | 1.45M | 2665786U, // SMLAD |
2598 | 1.45M | 2667783U, // SMLADX |
2599 | 1.45M | 290621U, // SMLAL |
2600 | 1.45M | 2755529U, // SMLALBB |
2601 | 1.45M | 2757265U, // SMLALBT |
2602 | 1.45M | 2755964U, // SMLALD |
2603 | 1.45M | 2757909U, // SMLALDX |
2604 | 1.45M | 2755748U, // SMLALTB |
2605 | 1.45M | 2757507U, // SMLALTT |
2606 | 1.45M | 2665623U, // SMLATB |
2607 | 1.45M | 2667388U, // SMLATT |
2608 | 1.45M | 2665690U, // SMLAWB |
2609 | 1.45M | 2667442U, // SMLAWT |
2610 | 1.45M | 2665887U, // SMLSD |
2611 | 1.45M | 2667813U, // SMLSDX |
2612 | 1.45M | 2755975U, // SMLSLD |
2613 | 1.45M | 2757917U, // SMLSLDX |
2614 | 1.45M | 2665256U, // SMMLA |
2615 | 1.45M | 2666902U, // SMMLAR |
2616 | 1.45M | 2667051U, // SMMLS |
2617 | 1.45M | 2666982U, // SMMLSR |
2618 | 1.45M | 2682930U, // SMMUL |
2619 | 1.45M | 2683336U, // SMMULR |
2620 | 1.45M | 2682176U, // SMUAD |
2621 | 1.45M | 2684174U, // SMUADX |
2622 | 1.45M | 2681809U, // SMULBB |
2623 | 1.45M | 2683545U, // SMULBT |
2624 | 1.45M | 2691043U, // SMULL |
2625 | 1.45M | 2682028U, // SMULTB |
2626 | 1.45M | 2683787U, // SMULTT |
2627 | 1.45M | 2682081U, // SMULWB |
2628 | 1.45M | 2683833U, // SMULWT |
2629 | 1.45M | 2682277U, // SMUSD |
2630 | 1.45M | 2684204U, // SMUSDX |
2631 | 1.45M | 4278330U, // SRSDA |
2632 | 1.45M | 4278282U, // SRSDA_UPD |
2633 | 1.45M | 4278352U, // SRSDB |
2634 | 1.45M | 4278306U, // SRSDB_UPD |
2635 | 1.45M | 4278341U, // SRSIA |
2636 | 1.45M | 4278294U, // SRSIA_UPD |
2637 | 1.45M | 4278363U, // SRSIB |
2638 | 1.45M | 4278318U, // SRSIB_UPD |
2639 | 1.45M | 2667125U, // SSAT |
2640 | 1.45M | 2681322U, // SSAT16 |
2641 | 1.45M | 2684094U, // SSAX |
2642 | 1.45M | 2681270U, // SSUB16 |
2643 | 1.45M | 2681371U, // SSUB8 |
2644 | 1.45M | 1552590729U, // STC2L_OFFSET |
2645 | 1.45M | 1619699593U, // STC2L_OPTION |
2646 | 1.45M | 1619699593U, // STC2L_POST |
2647 | 1.45M | 9561993U, // STC2L_PRE |
2648 | 1.45M | 1552589369U, // STC2_OFFSET |
2649 | 1.45M | 1619698233U, // STC2_OPTION |
2650 | 1.45M | 1619698233U, // STC2_POST |
2651 | 1.45M | 9560633U, // STC2_PRE |
2652 | 1.45M | 1277734751U, // STCL_OFFSET |
2653 | 1.45M | 1277734751U, // STCL_OPTION |
2654 | 1.45M | 1277734751U, // STCL_POST |
2655 | 1.45M | 1009307487U, // STCL_PRE |
2656 | 1.45M | 1277734194U, // STC_OFFSET |
2657 | 1.45M | 1277734194U, // STC_OPTION |
2658 | 1.45M | 1277734194U, // STC_POST |
2659 | 1.45M | 1009306930U, // STC_PRE |
2660 | 1.45M | 2650152U, // STL |
2661 | 1.45M | 2649113U, // STLB |
2662 | 1.45M | 2684217U, // STLEX |
2663 | 1.45M | 2682095U, // STLEXB |
2664 | 1.45M | 2682290U, // STLEXD |
2665 | 1.45M | 2682591U, // STLEXH |
2666 | 1.45M | 2649692U, // STLH |
2667 | 1.45M | 2730730U, // STMDA |
2668 | 1.45M | 875064042U, // STMDA_UPD |
2669 | 1.45M | 2730986U, // STMDB |
2670 | 1.45M | 875064298U, // STMDB_UPD |
2671 | 1.45M | 2732142U, // STMIA |
2672 | 1.45M | 875065454U, // STMIA_UPD |
2673 | 1.45M | 2731004U, // STMIB |
2674 | 1.45M | 875064316U, // STMIB_UPD |
2675 | 1.45M | 875090598U, // STRBT_POST_IMM |
2676 | 1.45M | 875090598U, // STRBT_POST_REG |
2677 | 1.45M | 875089024U, // STRB_POST_IMM |
2678 | 1.45M | 875089024U, // STRB_POST_REG |
2679 | 1.45M | 875080832U, // STRB_PRE_IMM |
2680 | 1.45M | 875089024U, // STRB_PRE_REG |
2681 | 1.45M | 2681984U, // STRBi12 |
2682 | 1.45M | 2665600U, // STRBrs |
2683 | 1.45M | 2674074U, // STRD |
2684 | 1.45M | 875171226U, // STRD_POST |
2685 | 1.45M | 875171226U, // STRD_PRE |
2686 | 1.45M | 2684235U, // STREX |
2687 | 1.45M | 2682109U, // STREXB |
2688 | 1.45M | 2682304U, // STREXD |
2689 | 1.45M | 2682605U, // STREXH |
2690 | 1.45M | 2666118U, // STRH |
2691 | 1.45M | 875082441U, // STRHTi |
2692 | 1.45M | 875090633U, // STRHTr |
2693 | 1.45M | 875089542U, // STRH_POST |
2694 | 1.45M | 875089542U, // STRH_PRE |
2695 | 1.45M | 875090797U, // STRT_POST_IMM |
2696 | 1.45M | 875090797U, // STRT_POST_REG |
2697 | 1.45M | 875090432U, // STR_POST_IMM |
2698 | 1.45M | 875090432U, // STR_POST_REG |
2699 | 1.45M | 875082240U, // STR_PRE_IMM |
2700 | 1.45M | 875090432U, // STR_PRE_REG |
2701 | 1.45M | 2683392U, // STRi12 |
2702 | 1.45M | 2667008U, // STRrs |
2703 | 1.45M | 2632901U, // SUBri |
2704 | 1.45M | 2632901U, // SUBrr |
2705 | 1.45M | 2690245U, // SUBrsi |
2706 | 1.45M | 76997U, // SUBrsr |
2707 | 1.45M | 2731318U, // SVC |
2708 | 1.45M | 2683268U, // SWP |
2709 | 1.45M | 2681972U, // SWPB |
2710 | 1.45M | 2665398U, // SXTAB |
2711 | 1.45M | 2664832U, // SXTAB16 |
2712 | 1.45M | 2666022U, // SXTAH |
2713 | 1.45M | 2682041U, // SXTB |
2714 | 1.45M | 2681232U, // SXTB16 |
2715 | 1.45M | 2682552U, // SXTH |
2716 | 1.45M | 2650514U, // TEQri |
2717 | 1.45M | 2650514U, // TEQrr |
2718 | 1.45M | 2683282U, // TEQrsi |
2719 | 1.45M | 2666898U, // TEQrsr |
2720 | 1.45M | 4355U, // TRAP |
2721 | 1.45M | 4355U, // TRAPNaCl |
2722 | 1.45M | 296743U, // TSB |
2723 | 1.45M | 2651000U, // TSTri |
2724 | 1.45M | 2651000U, // TSTrr |
2725 | 1.45M | 2683768U, // TSTrsi |
2726 | 1.45M | 2667384U, // TSTrsr |
2727 | 1.45M | 2681315U, // UADD16 |
2728 | 1.45M | 2681416U, // UADD8 |
2729 | 1.45M | 2684353U, // UASX |
2730 | 1.45M | 2667862U, // UBFX |
2731 | 1.45M | 4278107U, // UDF |
2732 | 1.45M | 2683939U, // UDIV |
2733 | 1.45M | 2681292U, // UHADD16 |
2734 | 1.45M | 2681396U, // UHADD8 |
2735 | 1.45M | 2684336U, // UHASX |
2736 | 1.45M | 2684082U, // UHSAX |
2737 | 1.45M | 2681254U, // UHSUB16 |
2738 | 1.45M | 2681357U, // UHSUB8 |
2739 | 1.45M | 2756386U, // UMAAL |
2740 | 1.45M | 290627U, // UMLAL |
2741 | 1.45M | 2691049U, // UMULL |
2742 | 1.45M | 2681300U, // UQADD16 |
2743 | 1.45M | 2681403U, // UQADD8 |
2744 | 1.45M | 2684342U, // UQASX |
2745 | 1.45M | 2684088U, // UQSAX |
2746 | 1.45M | 2681262U, // UQSUB16 |
2747 | 1.45M | 2681364U, // UQSUB8 |
2748 | 1.45M | 2681383U, // USAD8 |
2749 | 1.45M | 2664959U, // USADA8 |
2750 | 1.45M | 2667130U, // USAT |
2751 | 1.45M | 2681329U, // USAT16 |
2752 | 1.45M | 2684099U, // USAX |
2753 | 1.45M | 2681277U, // USUB16 |
2754 | 1.45M | 2681377U, // USUB8 |
2755 | 1.45M | 2665404U, // UXTAB |
2756 | 1.45M | 2664840U, // UXTAB16 |
2757 | 1.45M | 2666028U, // UXTAH |
2758 | 1.45M | 2682046U, // UXTB |
2759 | 1.45M | 2681239U, // UXTB16 |
2760 | 1.45M | 2682557U, // UXTH |
2761 | 1.45M | 11579176U, // VABALsv2i64 |
2762 | 1.45M | 11054888U, // VABALsv4i32 |
2763 | 1.45M | 12103464U, // VABALsv8i16 |
2764 | 1.45M | 13152040U, // VABALuv2i64 |
2765 | 1.45M | 12627752U, // VABALuv4i32 |
2766 | 1.45M | 13676328U, // VABALuv8i16 |
2767 | 1.45M | 12102345U, // VABAsv16i8 |
2768 | 1.45M | 11578057U, // VABAsv2i32 |
2769 | 1.45M | 11053769U, // VABAsv4i16 |
2770 | 1.45M | 11578057U, // VABAsv4i32 |
2771 | 1.45M | 11053769U, // VABAsv8i16 |
2772 | 1.45M | 12102345U, // VABAsv8i8 |
2773 | 1.45M | 13675209U, // VABAuv16i8 |
2774 | 1.45M | 13150921U, // VABAuv2i32 |
2775 | 1.45M | 12626633U, // VABAuv4i16 |
2776 | 1.45M | 13150921U, // VABAuv4i32 |
2777 | 1.45M | 12626633U, // VABAuv8i16 |
2778 | 1.45M | 13675209U, // VABAuv8i8 |
2779 | 1.45M | 11595620U, // VABDLsv2i64 |
2780 | 1.45M | 11071332U, // VABDLsv4i32 |
2781 | 1.45M | 12119908U, // VABDLsv8i16 |
2782 | 1.45M | 13168484U, // VABDLuv2i64 |
2783 | 1.45M | 12644196U, // VABDLuv4i32 |
2784 | 1.45M | 13692772U, // VABDLuv8i16 |
2785 | 1.45M | 7925062U, // VABDfd |
2786 | 1.45M | 7925062U, // VABDfq |
2787 | 1.45M | 7400774U, // VABDhd |
2788 | 1.45M | 7400774U, // VABDhq |
2789 | 1.45M | 12119366U, // VABDsv16i8 |
2790 | 1.45M | 11595078U, // VABDsv2i32 |
2791 | 1.45M | 11070790U, // VABDsv4i16 |
2792 | 1.45M | 11595078U, // VABDsv4i32 |
2793 | 1.45M | 11070790U, // VABDsv8i16 |
2794 | 1.45M | 12119366U, // VABDsv8i8 |
2795 | 1.45M | 13692230U, // VABDuv16i8 |
2796 | 1.45M | 13167942U, // VABDuv2i32 |
2797 | 1.45M | 12643654U, // VABDuv4i16 |
2798 | 1.45M | 13167942U, // VABDuv4i32 |
2799 | 1.45M | 12643654U, // VABDuv8i16 |
2800 | 1.45M | 13692230U, // VABDuv8i8 |
2801 | 1.45M | 1147695644U, // VABSD |
2802 | 1.45M | 7369244U, // VABSH |
2803 | 1.45M | 7893532U, // VABSS |
2804 | 1.45M | 7893532U, // VABSfd |
2805 | 1.45M | 7893532U, // VABSfq |
2806 | 1.45M | 7369244U, // VABShd |
2807 | 1.45M | 7369244U, // VABShq |
2808 | 1.45M | 12087836U, // VABSv16i8 |
2809 | 1.45M | 11563548U, // VABSv2i32 |
2810 | 1.45M | 11039260U, // VABSv4i16 |
2811 | 1.45M | 11563548U, // VABSv4i32 |
2812 | 1.45M | 11039260U, // VABSv8i16 |
2813 | 1.45M | 12087836U, // VABSv8i8 |
2814 | 1.45M | 7925191U, // VACGEfd |
2815 | 1.45M | 7925191U, // VACGEfq |
2816 | 1.45M | 7400903U, // VACGEhd |
2817 | 1.45M | 7400903U, // VACGEhq |
2818 | 1.45M | 7926456U, // VACGTfd |
2819 | 1.45M | 7926456U, // VACGTfq |
2820 | 1.45M | 7402168U, // VACGThd |
2821 | 1.45M | 7402168U, // VACGThq |
2822 | 1.45M | 1147727223U, // VADDD |
2823 | 1.45M | 7400823U, // VADDH |
2824 | 1.45M | 895545487U, // VADDHNv2i32 |
2825 | 1.45M | 14217359U, // VADDHNv4i16 |
2826 | 1.45M | 14741647U, // VADDHNv8i8 |
2827 | 1.45M | 11595633U, // VADDLsv2i64 |
2828 | 1.45M | 11071345U, // VADDLsv4i32 |
2829 | 1.45M | 12119921U, // VADDLsv8i16 |
2830 | 1.45M | 13168497U, // VADDLuv2i64 |
2831 | 1.45M | 12644209U, // VADDLuv4i32 |
2832 | 1.45M | 13692785U, // VADDLuv8i16 |
2833 | 1.45M | 7925111U, // VADDS |
2834 | 1.45M | 11596891U, // VADDWsv2i64 |
2835 | 1.45M | 11072603U, // VADDWsv4i32 |
2836 | 1.45M | 12121179U, // VADDWsv8i16 |
2837 | 1.45M | 13169755U, // VADDWuv2i64 |
2838 | 1.45M | 12645467U, // VADDWuv4i32 |
2839 | 1.45M | 13694043U, // VADDWuv8i16 |
2840 | 1.45M | 7925111U, // VADDfd |
2841 | 1.45M | 7925111U, // VADDfq |
2842 | 1.45M | 7400823U, // VADDhd |
2843 | 1.45M | 7400823U, // VADDhq |
2844 | 1.45M | 15265143U, // VADDv16i8 |
2845 | 1.45M | 895544695U, // VADDv1i64 |
2846 | 1.45M | 14216567U, // VADDv2i32 |
2847 | 1.45M | 895544695U, // VADDv2i64 |
2848 | 1.45M | 14740855U, // VADDv4i16 |
2849 | 1.45M | 14216567U, // VADDv4i32 |
2850 | 1.45M | 14740855U, // VADDv8i16 |
2851 | 1.45M | 15265143U, // VADDv8i8 |
2852 | 1.45M | 2682254U, // VANDd |
2853 | 1.45M | 2682254U, // VANDq |
2854 | 1.45M | 808543686U, // VBF16MALBQ |
2855 | 1.45M | 808543686U, // VBF16MALBQI |
2856 | 1.45M | 808543698U, // VBF16MALTQ |
2857 | 1.45M | 808543698U, // VBF16MALTQI |
2858 | 1.45M | 2682134U, // VBICd |
2859 | 1.45M | 14216470U, // VBICiv2i32 |
2860 | 1.45M | 14740758U, // VBICiv4i16 |
2861 | 1.45M | 14216470U, // VBICiv4i32 |
2862 | 1.45M | 14740758U, // VBICiv8i16 |
2863 | 1.45M | 2682134U, // VBICq |
2864 | 1.45M | 2665967U, // VBIFd |
2865 | 1.45M | 2665967U, // VBIFq |
2866 | 1.45M | 2667227U, // VBITd |
2867 | 1.45M | 2667227U, // VBITq |
2868 | 1.45M | 2666517U, // VBSLd |
2869 | 1.45M | 2666517U, // VBSLq |
2870 | 1.45M | 0U, // VBSPd |
2871 | 1.45M | 0U, // VBSPq |
2872 | 1.45M | 875643287U, // VCADDv2f32 |
2873 | 1.45M | 875644160U, // VCADDv4f16 |
2874 | 1.45M | 875643287U, // VCADDv4f32 |
2875 | 1.45M | 875644160U, // VCADDv8f16 |
2876 | 1.45M | 7926157U, // VCEQfd |
2877 | 1.45M | 7926157U, // VCEQfq |
2878 | 1.45M | 7401869U, // VCEQhd |
2879 | 1.45M | 7401869U, // VCEQhq |
2880 | 1.45M | 15266189U, // VCEQv16i8 |
2881 | 1.45M | 14217613U, // VCEQv2i32 |
2882 | 1.45M | 14741901U, // VCEQv4i16 |
2883 | 1.45M | 14217613U, // VCEQv4i32 |
2884 | 1.45M | 14741901U, // VCEQv8i16 |
2885 | 1.45M | 15266189U, // VCEQv8i8 |
2886 | 1.45M | 15233421U, // VCEQzv16i8 |
2887 | 1.45M | 7893389U, // VCEQzv2f32 |
2888 | 1.45M | 14184845U, // VCEQzv2i32 |
2889 | 1.45M | 7369101U, // VCEQzv4f16 |
2890 | 1.45M | 7893389U, // VCEQzv4f32 |
2891 | 1.45M | 14709133U, // VCEQzv4i16 |
2892 | 1.45M | 14184845U, // VCEQzv4i32 |
2893 | 1.45M | 7369101U, // VCEQzv8f16 |
2894 | 1.45M | 14709133U, // VCEQzv8i16 |
2895 | 1.45M | 15233421U, // VCEQzv8i8 |
2896 | 1.45M | 7925197U, // VCGEfd |
2897 | 1.45M | 7925197U, // VCGEfq |
2898 | 1.45M | 7400909U, // VCGEhd |
2899 | 1.45M | 7400909U, // VCGEhq |
2900 | 1.45M | 12119501U, // VCGEsv16i8 |
2901 | 1.45M | 11595213U, // VCGEsv2i32 |
2902 | 1.45M | 11070925U, // VCGEsv4i16 |
2903 | 1.45M | 11595213U, // VCGEsv4i32 |
2904 | 1.45M | 11070925U, // VCGEsv8i16 |
2905 | 1.45M | 12119501U, // VCGEsv8i8 |
2906 | 1.45M | 13692365U, // VCGEuv16i8 |
2907 | 1.45M | 13168077U, // VCGEuv2i32 |
2908 | 1.45M | 12643789U, // VCGEuv4i16 |
2909 | 1.45M | 13168077U, // VCGEuv4i32 |
2910 | 1.45M | 12643789U, // VCGEuv8i16 |
2911 | 1.45M | 13692365U, // VCGEuv8i8 |
2912 | 1.45M | 12086733U, // VCGEzv16i8 |
2913 | 1.45M | 7892429U, // VCGEzv2f32 |
2914 | 1.45M | 11562445U, // VCGEzv2i32 |
2915 | 1.45M | 7368141U, // VCGEzv4f16 |
2916 | 1.45M | 7892429U, // VCGEzv4f32 |
2917 | 1.45M | 11038157U, // VCGEzv4i16 |
2918 | 1.45M | 11562445U, // VCGEzv4i32 |
2919 | 1.45M | 7368141U, // VCGEzv8f16 |
2920 | 1.45M | 11038157U, // VCGEzv8i16 |
2921 | 1.45M | 12086733U, // VCGEzv8i8 |
2922 | 1.45M | 7926462U, // VCGTfd |
2923 | 1.45M | 7926462U, // VCGTfq |
2924 | 1.45M | 7402174U, // VCGThd |
2925 | 1.45M | 7402174U, // VCGThq |
2926 | 1.45M | 12120766U, // VCGTsv16i8 |
2927 | 1.45M | 11596478U, // VCGTsv2i32 |
2928 | 1.45M | 11072190U, // VCGTsv4i16 |
2929 | 1.45M | 11596478U, // VCGTsv4i32 |
2930 | 1.45M | 11072190U, // VCGTsv8i16 |
2931 | 1.45M | 12120766U, // VCGTsv8i8 |
2932 | 1.45M | 13693630U, // VCGTuv16i8 |
2933 | 1.45M | 13169342U, // VCGTuv2i32 |
2934 | 1.45M | 12645054U, // VCGTuv4i16 |
2935 | 1.45M | 13169342U, // VCGTuv4i32 |
2936 | 1.45M | 12645054U, // VCGTuv8i16 |
2937 | 1.45M | 13693630U, // VCGTuv8i8 |
2938 | 1.45M | 12087998U, // VCGTzv16i8 |
2939 | 1.45M | 7893694U, // VCGTzv2f32 |
2940 | 1.45M | 11563710U, // VCGTzv2i32 |
2941 | 1.45M | 7369406U, // VCGTzv4f16 |
2942 | 1.45M | 7893694U, // VCGTzv4f32 |
2943 | 1.45M | 11039422U, // VCGTzv4i16 |
2944 | 1.45M | 11563710U, // VCGTzv4i32 |
2945 | 1.45M | 7369406U, // VCGTzv8f16 |
2946 | 1.45M | 11039422U, // VCGTzv8i16 |
2947 | 1.45M | 12087998U, // VCGTzv8i8 |
2948 | 1.45M | 12086738U, // VCLEzv16i8 |
2949 | 1.45M | 7892434U, // VCLEzv2f32 |
2950 | 1.45M | 11562450U, // VCLEzv2i32 |
2951 | 1.45M | 7368146U, // VCLEzv4f16 |
2952 | 1.45M | 7892434U, // VCLEzv4f32 |
2953 | 1.45M | 11038162U, // VCLEzv4i16 |
2954 | 1.45M | 11562450U, // VCLEzv4i32 |
2955 | 1.45M | 7368146U, // VCLEzv8f16 |
2956 | 1.45M | 11038162U, // VCLEzv8i16 |
2957 | 1.45M | 12086738U, // VCLEzv8i8 |
2958 | 1.45M | 12087846U, // VCLSv16i8 |
2959 | 1.45M | 11563558U, // VCLSv2i32 |
2960 | 1.45M | 11039270U, // VCLSv4i16 |
2961 | 1.45M | 11563558U, // VCLSv4i32 |
2962 | 1.45M | 11039270U, // VCLSv8i16 |
2963 | 1.45M | 12087846U, // VCLSv8i8 |
2964 | 1.45M | 12088032U, // VCLTzv16i8 |
2965 | 1.45M | 7893728U, // VCLTzv2f32 |
2966 | 1.45M | 11563744U, // VCLTzv2i32 |
2967 | 1.45M | 7369440U, // VCLTzv4f16 |
2968 | 1.45M | 7893728U, // VCLTzv4f32 |
2969 | 1.45M | 11039456U, // VCLTzv4i16 |
2970 | 1.45M | 11563744U, // VCLTzv4i32 |
2971 | 1.45M | 7369440U, // VCLTzv8f16 |
2972 | 1.45M | 11039456U, // VCLTzv8i16 |
2973 | 1.45M | 12088032U, // VCLTzv8i8 |
2974 | 1.45M | 15234547U, // VCLZv16i8 |
2975 | 1.45M | 14185971U, // VCLZv2i32 |
2976 | 1.45M | 14710259U, // VCLZv4i16 |
2977 | 1.45M | 14185971U, // VCLZv4i32 |
2978 | 1.45M | 14710259U, // VCLZv8i16 |
2979 | 1.45M | 15234547U, // VCLZv8i8 |
2980 | 1.45M | 808534400U, // VCMLAv2f32 |
2981 | 1.45M | 808534400U, // VCMLAv2f32_indexed |
2982 | 1.45M | 808535273U, // VCMLAv4f16 |
2983 | 1.45M | 808535273U, // VCMLAv4f16_indexed |
2984 | 1.45M | 808534400U, // VCMLAv4f32 |
2985 | 1.45M | 808534400U, // VCMLAv4f32_indexed |
2986 | 1.45M | 808535273U, // VCMLAv8f16 |
2987 | 1.45M | 808535273U, // VCMLAv8f16_indexed |
2988 | 1.45M | 1147695377U, // VCMPD |
2989 | 1.45M | 1147694558U, // VCMPED |
2990 | 1.45M | 7368158U, // VCMPEH |
2991 | 1.45M | 7892446U, // VCMPES |
2992 | 1.45M | 2087300574U, // VCMPEZD |
2993 | 1.45M | 7450078U, // VCMPEZH |
2994 | 1.45M | 7974366U, // VCMPEZS |
2995 | 1.45M | 7368977U, // VCMPH |
2996 | 1.45M | 7893265U, // VCMPS |
2997 | 1.45M | 2087301393U, // VCMPZD |
2998 | 1.45M | 7450897U, // VCMPZH |
2999 | 1.45M | 7975185U, // VCMPZS |
3000 | 1.45M | 1602307U, // VCNTd |
3001 | 1.45M | 1602307U, // VCNTq |
3002 | 1.45M | 875643144U, // VCVTANSDf |
3003 | 1.45M | 875644017U, // VCVTANSDh |
3004 | 1.45M | 875643144U, // VCVTANSQf |
3005 | 1.45M | 875644017U, // VCVTANSQh |
3006 | 1.45M | 875643204U, // VCVTANUDf |
3007 | 1.45M | 875644077U, // VCVTANUDh |
3008 | 1.45M | 875643204U, // VCVTANUQf |
3009 | 1.45M | 875644077U, // VCVTANUQh |
3010 | 1.45M | 875643506U, // VCVTASD |
3011 | 1.45M | 875643897U, // VCVTASH |
3012 | 1.45M | 875643144U, // VCVTASS |
3013 | 1.45M | 875643566U, // VCVTAUD |
3014 | 1.45M | 875643957U, // VCVTAUH |
3015 | 1.45M | 875643204U, // VCVTAUS |
3016 | 1.45M | 25750707U, // VCVTBDH |
3017 | 1.45M | 26242227U, // VCVTBHD |
3018 | 1.45M | 17853619U, // VCVTBHS |
3019 | 1.45M | 821619891U, // VCVTBSH |
3020 | 1.45M | 26768296U, // VCVTDS |
3021 | 1.45M | 875643159U, // VCVTMNSDf |
3022 | 1.45M | 875644032U, // VCVTMNSDh |
3023 | 1.45M | 875643159U, // VCVTMNSQf |
3024 | 1.45M | 875644032U, // VCVTMNSQh |
3025 | 1.45M | 875643219U, // VCVTMNUDf |
3026 | 1.45M | 875644092U, // VCVTMNUDh |
3027 | 1.45M | 875643219U, // VCVTMNUQf |
3028 | 1.45M | 875644092U, // VCVTMNUQh |
3029 | 1.45M | 875643521U, // VCVTMSD |
3030 | 1.45M | 875643912U, // VCVTMSH |
3031 | 1.45M | 875643159U, // VCVTMSS |
3032 | 1.45M | 875643581U, // VCVTMUD |
3033 | 1.45M | 875643972U, // VCVTMUH |
3034 | 1.45M | 875643219U, // VCVTMUS |
3035 | 1.45M | 875643174U, // VCVTNNSDf |
3036 | 1.45M | 875644047U, // VCVTNNSDh |
3037 | 1.45M | 875643174U, // VCVTNNSQf |
3038 | 1.45M | 875644047U, // VCVTNNSQh |
3039 | 1.45M | 875643234U, // VCVTNNUDf |
3040 | 1.45M | 875644107U, // VCVTNNUDh |
3041 | 1.45M | 875643234U, // VCVTNNUQf |
3042 | 1.45M | 875644107U, // VCVTNNUQh |
3043 | 1.45M | 875643536U, // VCVTNSD |
3044 | 1.45M | 875643927U, // VCVTNSH |
3045 | 1.45M | 875643174U, // VCVTNSS |
3046 | 1.45M | 875643596U, // VCVTNUD |
3047 | 1.45M | 875643987U, // VCVTNUH |
3048 | 1.45M | 875643234U, // VCVTNUS |
3049 | 1.45M | 875643189U, // VCVTPNSDf |
3050 | 1.45M | 875644062U, // VCVTPNSDh |
3051 | 1.45M | 875643189U, // VCVTPNSQf |
3052 | 1.45M | 875644062U, // VCVTPNSQh |
3053 | 1.45M | 875643249U, // VCVTPNUDf |
3054 | 1.45M | 875644122U, // VCVTPNUDh |
3055 | 1.45M | 875643249U, // VCVTPNUQf |
3056 | 1.45M | 875644122U, // VCVTPNUQh |
3057 | 1.45M | 875643551U, // VCVTPSD |
3058 | 1.45M | 875643942U, // VCVTPSH |
3059 | 1.45M | 875643189U, // VCVTPSS |
3060 | 1.45M | 875643611U, // VCVTPUD |
3061 | 1.45M | 875644002U, // VCVTPUH |
3062 | 1.45M | 875643249U, // VCVTPUS |
3063 | 1.45M | 27292584U, // VCVTSD |
3064 | 1.45M | 25752470U, // VCVTTDH |
3065 | 1.45M | 26243990U, // VCVTTHD |
3066 | 1.45M | 17855382U, // VCVTTHS |
3067 | 1.45M | 821621654U, // VCVTTSH |
3068 | 1.45M | 888697768U, // VCVTf2h |
3069 | 1.45M | 1093694376U, // VCVTf2sd |
3070 | 1.45M | 1093694376U, // VCVTf2sq |
3071 | 1.45M | 1094742952U, // VCVTf2ud |
3072 | 1.45M | 1094742952U, // VCVTf2uq |
3073 | 1.45M | 1160836008U, // VCVTf2xsd |
3074 | 1.45M | 1160836008U, // VCVTf2xsq |
3075 | 1.45M | 1161884584U, // VCVTf2xud |
3076 | 1.45M | 1161884584U, // VCVTf2xuq |
3077 | 1.45M | 17855400U, // VCVTh2f |
3078 | 1.45M | 1093170088U, // VCVTh2sd |
3079 | 1.45M | 1093170088U, // VCVTh2sq |
3080 | 1.45M | 1094218664U, // VCVTh2ud |
3081 | 1.45M | 1094218664U, // VCVTh2uq |
3082 | 1.45M | 1160311720U, // VCVTh2xsd |
3083 | 1.45M | 1160311720U, // VCVTh2xsq |
3084 | 1.45M | 1161360296U, // VCVTh2xud |
3085 | 1.45M | 1161360296U, // VCVTh2xuq |
3086 | 1.45M | 1092121512U, // VCVTs2fd |
3087 | 1.45M | 1092121512U, // VCVTs2fq |
3088 | 1.45M | 1090548648U, // VCVTs2hd |
3089 | 1.45M | 1090548648U, // VCVTs2hq |
3090 | 1.45M | 1092645800U, // VCVTu2fd |
3091 | 1.45M | 1092645800U, // VCVTu2fq |
3092 | 1.45M | 1091072936U, // VCVTu2hd |
3093 | 1.45M | 1091072936U, // VCVTu2hq |
3094 | 1.45M | 1159263144U, // VCVTxs2fd |
3095 | 1.45M | 1159263144U, // VCVTxs2fq |
3096 | 1.45M | 1157690280U, // VCVTxs2hd |
3097 | 1.45M | 1157690280U, // VCVTxs2hq |
3098 | 1.45M | 1159787432U, // VCVTxu2fd |
3099 | 1.45M | 1159787432U, // VCVTxu2fq |
3100 | 1.45M | 1158214568U, // VCVTxu2hd |
3101 | 1.45M | 1158214568U, // VCVTxu2hq |
3102 | 1.45M | 1147728936U, // VDIVD |
3103 | 1.45M | 7402536U, // VDIVH |
3104 | 1.45M | 7926824U, // VDIVS |
3105 | 1.45M | 553328U, // VDUP16d |
3106 | 1.45M | 553328U, // VDUP16q |
3107 | 1.45M | 1077616U, // VDUP32d |
3108 | 1.45M | 1077616U, // VDUP32q |
3109 | 1.45M | 1601904U, // VDUP8d |
3110 | 1.45M | 1601904U, // VDUP8q |
3111 | 1.45M | 586096U, // VDUPLN16d |
3112 | 1.45M | 586096U, // VDUPLN16q |
3113 | 1.45M | 1110384U, // VDUPLN32d |
3114 | 1.45M | 1110384U, // VDUPLN32q |
3115 | 1.45M | 1634672U, // VDUPLN8d |
3116 | 1.45M | 1634672U, // VDUPLN8q |
3117 | 1.45M | 2683343U, // VEORd |
3118 | 1.45M | 2683343U, // VEORq |
3119 | 1.45M | 570304U, // VEXTd16 |
3120 | 1.45M | 1094592U, // VEXTd32 |
3121 | 1.45M | 1618880U, // VEXTd8 |
3122 | 1.45M | 570304U, // VEXTq16 |
3123 | 1.45M | 1094592U, // VEXTq32 |
3124 | 1.45M | 15774656U, // VEXTq64 |
3125 | 1.45M | 1618880U, // VEXTq8 |
3126 | 1.45M | 1147710265U, // VFMAD |
3127 | 1.45M | 7383865U, // VFMAH |
3128 | 1.45M | 875644183U, // VFMALD |
3129 | 1.45M | 875644183U, // VFMALDI |
3130 | 1.45M | 875644183U, // VFMALQ |
3131 | 1.45M | 875644183U, // VFMALQI |
3132 | 1.45M | 7908153U, // VFMAS |
3133 | 1.45M | 7908153U, // VFMAfd |
3134 | 1.45M | 7908153U, // VFMAfq |
3135 | 1.45M | 7383865U, // VFMAhd |
3136 | 1.45M | 7383865U, // VFMAhq |
3137 | 1.45M | 1147712060U, // VFMSD |
3138 | 1.45M | 7385660U, // VFMSH |
3139 | 1.45M | 875644194U, // VFMSLD |
3140 | 1.45M | 875644194U, // VFMSLDI |
3141 | 1.45M | 875644194U, // VFMSLQ |
3142 | 1.45M | 875644194U, // VFMSLQI |
3143 | 1.45M | 7909948U, // VFMSS |
3144 | 1.45M | 7909948U, // VFMSfd |
3145 | 1.45M | 7909948U, // VFMSfq |
3146 | 1.45M | 7385660U, // VFMShd |
3147 | 1.45M | 7385660U, // VFMShq |
3148 | 1.45M | 1147710270U, // VFNMAD |
3149 | 1.45M | 7383870U, // VFNMAH |
3150 | 1.45M | 7908158U, // VFNMAS |
3151 | 1.45M | 1147712065U, // VFNMSD |
3152 | 1.45M | 7385665U, // VFNMSH |
3153 | 1.45M | 7909953U, // VFNMSS |
3154 | 1.45M | 875643662U, // VFP_VMAXNMD |
3155 | 1.45M | 875644217U, // VFP_VMAXNMH |
3156 | 1.45M | 875643322U, // VFP_VMAXNMS |
3157 | 1.45M | 875643650U, // VFP_VMINNMD |
3158 | 1.45M | 875644205U, // VFP_VMINNMH |
3159 | 1.45M | 875643310U, // VFP_VMINNMS |
3160 | 1.45M | 1111114U, // VGETLNi32 |
3161 | 1.45M | 11072586U, // VGETLNs16 |
3162 | 1.45M | 12121162U, // VGETLNs8 |
3163 | 1.45M | 12645450U, // VGETLNu16 |
3164 | 1.45M | 13694026U, // VGETLNu8 |
3165 | 1.45M | 12119397U, // VHADDsv16i8 |
3166 | 1.45M | 11595109U, // VHADDsv2i32 |
3167 | 1.45M | 11070821U, // VHADDsv4i16 |
3168 | 1.45M | 11595109U, // VHADDsv4i32 |
3169 | 1.45M | 11070821U, // VHADDsv8i16 |
3170 | 1.45M | 12119397U, // VHADDsv8i8 |
3171 | 1.45M | 13692261U, // VHADDuv16i8 |
3172 | 1.45M | 13167973U, // VHADDuv2i32 |
3173 | 1.45M | 12643685U, // VHADDuv4i16 |
3174 | 1.45M | 13167973U, // VHADDuv4i32 |
3175 | 1.45M | 12643685U, // VHADDuv8i16 |
3176 | 1.45M | 13692261U, // VHADDuv8i8 |
3177 | 1.45M | 12119241U, // VHSUBsv16i8 |
3178 | 1.45M | 11594953U, // VHSUBsv2i32 |
3179 | 1.45M | 11070665U, // VHSUBsv4i16 |
3180 | 1.45M | 11594953U, // VHSUBsv4i32 |
3181 | 1.45M | 11070665U, // VHSUBsv8i16 |
3182 | 1.45M | 12119241U, // VHSUBsv8i8 |
3183 | 1.45M | 13692105U, // VHSUBuv16i8 |
3184 | 1.45M | 13167817U, // VHSUBuv2i32 |
3185 | 1.45M | 12643529U, // VHSUBuv4i16 |
3186 | 1.45M | 13167817U, // VHSUBuv4i32 |
3187 | 1.45M | 12643529U, // VHSUBuv8i16 |
3188 | 1.45M | 13692105U, // VHSUBuv8i8 |
3189 | 1.45M | 808535413U, // VINSH |
3190 | 1.45M | 1101558690U, // VJCVT |
3191 | 1.45M | 2148067588U, // VLD1DUPd16 |
3192 | 1.45M | 2148051204U, // VLD1DUPd16wb_fixed |
3193 | 1.45M | 2148059396U, // VLD1DUPd16wb_register |
3194 | 1.45M | 2148591876U, // VLD1DUPd32 |
3195 | 1.45M | 2148575492U, // VLD1DUPd32wb_fixed |
3196 | 1.45M | 2148583684U, // VLD1DUPd32wb_register |
3197 | 1.45M | 2149116164U, // VLD1DUPd8 |
3198 | 1.45M | 2149099780U, // VLD1DUPd8wb_fixed |
3199 | 1.45M | 2149107972U, // VLD1DUPd8wb_register |
3200 | 1.45M | 2215176452U, // VLD1DUPq16 |
3201 | 1.45M | 2215160068U, // VLD1DUPq16wb_fixed |
3202 | 1.45M | 2215168260U, // VLD1DUPq16wb_register |
3203 | 1.45M | 2215700740U, // VLD1DUPq32 |
3204 | 1.45M | 2215684356U, // VLD1DUPq32wb_fixed |
3205 | 1.45M | 2215692548U, // VLD1DUPq32wb_register |
3206 | 1.45M | 2216225028U, // VLD1DUPq8 |
3207 | 1.45M | 2216208644U, // VLD1DUPq8wb_fixed |
3208 | 1.45M | 2216216836U, // VLD1DUPq8wb_register |
3209 | 1.45M | 28363012U, // VLD1LNd16 |
3210 | 1.45M | 28616964U, // VLD1LNd16_UPD |
3211 | 1.45M | 28887300U, // VLD1LNd32 |
3212 | 1.45M | 29141252U, // VLD1LNd32_UPD |
3213 | 1.45M | 29411588U, // VLD1LNd8 |
3214 | 1.45M | 29665540U, // VLD1LNd8_UPD |
3215 | 1.45M | 0U, // VLD1LNq16Pseudo |
3216 | 1.45M | 0U, // VLD1LNq16Pseudo_UPD |
3217 | 1.45M | 0U, // VLD1LNq32Pseudo |
3218 | 1.45M | 0U, // VLD1LNq32Pseudo_UPD |
3219 | 1.45M | 0U, // VLD1LNq8Pseudo |
3220 | 1.45M | 0U, // VLD1LNq8Pseudo_UPD |
3221 | 1.45M | 2282285316U, // VLD1d16 |
3222 | 1.45M | 537454852U, // VLD1d16Q |
3223 | 1.45M | 0U, // VLD1d16QPseudo |
3224 | 1.45M | 0U, // VLD1d16QPseudoWB_fixed |
3225 | 1.45M | 0U, // VLD1d16QPseudoWB_register |
3226 | 1.45M | 537438468U, // VLD1d16Qwb_fixed |
3227 | 1.45M | 537446660U, // VLD1d16Qwb_register |
3228 | 1.45M | 269019396U, // VLD1d16T |
3229 | 1.45M | 0U, // VLD1d16TPseudo |
3230 | 1.45M | 0U, // VLD1d16TPseudoWB_fixed |
3231 | 1.45M | 0U, // VLD1d16TPseudoWB_register |
3232 | 1.45M | 269003012U, // VLD1d16Twb_fixed |
3233 | 1.45M | 269011204U, // VLD1d16Twb_register |
3234 | 1.45M | 2282268932U, // VLD1d16wb_fixed |
3235 | 1.45M | 2282277124U, // VLD1d16wb_register |
3236 | 1.45M | 2282809604U, // VLD1d32 |
3237 | 1.45M | 537979140U, // VLD1d32Q |
3238 | 1.45M | 0U, // VLD1d32QPseudo |
3239 | 1.45M | 0U, // VLD1d32QPseudoWB_fixed |
3240 | 1.45M | 0U, // VLD1d32QPseudoWB_register |
3241 | 1.45M | 537962756U, // VLD1d32Qwb_fixed |
3242 | 1.45M | 537970948U, // VLD1d32Qwb_register |
3243 | 1.45M | 269543684U, // VLD1d32T |
3244 | 1.45M | 0U, // VLD1d32TPseudo |
3245 | 1.45M | 0U, // VLD1d32TPseudoWB_fixed |
3246 | 1.45M | 0U, // VLD1d32TPseudoWB_register |
3247 | 1.45M | 269527300U, // VLD1d32Twb_fixed |
3248 | 1.45M | 269535492U, // VLD1d32Twb_register |
3249 | 1.45M | 2282793220U, // VLD1d32wb_fixed |
3250 | 1.45M | 2282801412U, // VLD1d32wb_register |
3251 | 1.45M | 2297489668U, // VLD1d64 |
3252 | 1.45M | 552659204U, // VLD1d64Q |
3253 | 1.45M | 0U, // VLD1d64QPseudo |
3254 | 1.45M | 0U, // VLD1d64QPseudoWB_fixed |
3255 | 1.45M | 0U, // VLD1d64QPseudoWB_register |
3256 | 1.45M | 552642820U, // VLD1d64Qwb_fixed |
3257 | 1.45M | 552651012U, // VLD1d64Qwb_register |
3258 | 1.45M | 284223748U, // VLD1d64T |
3259 | 1.45M | 0U, // VLD1d64TPseudo |
3260 | 1.45M | 0U, // VLD1d64TPseudoWB_fixed |
3261 | 1.45M | 0U, // VLD1d64TPseudoWB_register |
3262 | 1.45M | 284207364U, // VLD1d64Twb_fixed |
3263 | 1.45M | 284215556U, // VLD1d64Twb_register |
3264 | 1.45M | 2297473284U, // VLD1d64wb_fixed |
3265 | 1.45M | 2297481476U, // VLD1d64wb_register |
3266 | 1.45M | 2283333892U, // VLD1d8 |
3267 | 1.45M | 538503428U, // VLD1d8Q |
3268 | 1.45M | 0U, // VLD1d8QPseudo |
3269 | 1.45M | 0U, // VLD1d8QPseudoWB_fixed |
3270 | 1.45M | 0U, // VLD1d8QPseudoWB_register |
3271 | 1.45M | 538487044U, // VLD1d8Qwb_fixed |
3272 | 1.45M | 538495236U, // VLD1d8Qwb_register |
3273 | 1.45M | 270067972U, // VLD1d8T |
3274 | 1.45M | 0U, // VLD1d8TPseudo |
3275 | 1.45M | 0U, // VLD1d8TPseudoWB_fixed |
3276 | 1.45M | 0U, // VLD1d8TPseudoWB_register |
3277 | 1.45M | 270051588U, // VLD1d8Twb_fixed |
3278 | 1.45M | 270059780U, // VLD1d8Twb_register |
3279 | 1.45M | 2283317508U, // VLD1d8wb_fixed |
3280 | 1.45M | 2283325700U, // VLD1d8wb_register |
3281 | 1.45M | 2349394180U, // VLD1q16 |
3282 | 1.45M | 0U, // VLD1q16HighQPseudo |
3283 | 1.45M | 0U, // VLD1q16HighQPseudo_UPD |
3284 | 1.45M | 0U, // VLD1q16HighTPseudo |
3285 | 1.45M | 0U, // VLD1q16HighTPseudo_UPD |
3286 | 1.45M | 0U, // VLD1q16LowQPseudo_UPD |
3287 | 1.45M | 0U, // VLD1q16LowTPseudo_UPD |
3288 | 1.45M | 2349377796U, // VLD1q16wb_fixed |
3289 | 1.45M | 2349385988U, // VLD1q16wb_register |
3290 | 1.45M | 2349918468U, // VLD1q32 |
3291 | 1.45M | 0U, // VLD1q32HighQPseudo |
3292 | 1.45M | 0U, // VLD1q32HighQPseudo_UPD |
3293 | 1.45M | 0U, // VLD1q32HighTPseudo |
3294 | 1.45M | 0U, // VLD1q32HighTPseudo_UPD |
3295 | 1.45M | 0U, // VLD1q32LowQPseudo_UPD |
3296 | 1.45M | 0U, // VLD1q32LowTPseudo_UPD |
3297 | 1.45M | 2349902084U, // VLD1q32wb_fixed |
3298 | 1.45M | 2349910276U, // VLD1q32wb_register |
3299 | 1.45M | 2364598532U, // VLD1q64 |
3300 | 1.45M | 0U, // VLD1q64HighQPseudo |
3301 | 1.45M | 0U, // VLD1q64HighQPseudo_UPD |
3302 | 1.45M | 0U, // VLD1q64HighTPseudo |
3303 | 1.45M | 0U, // VLD1q64HighTPseudo_UPD |
3304 | 1.45M | 0U, // VLD1q64LowQPseudo_UPD |
3305 | 1.45M | 0U, // VLD1q64LowTPseudo_UPD |
3306 | 1.45M | 2364582148U, // VLD1q64wb_fixed |
3307 | 1.45M | 2364590340U, // VLD1q64wb_register |
3308 | 1.45M | 2350442756U, // VLD1q8 |
3309 | 1.45M | 0U, // VLD1q8HighQPseudo |
3310 | 1.45M | 0U, // VLD1q8HighQPseudo_UPD |
3311 | 1.45M | 0U, // VLD1q8HighTPseudo |
3312 | 1.45M | 0U, // VLD1q8HighTPseudo_UPD |
3313 | 1.45M | 0U, // VLD1q8LowQPseudo_UPD |
3314 | 1.45M | 0U, // VLD1q8LowTPseudo_UPD |
3315 | 1.45M | 2350426372U, // VLD1q8wb_fixed |
3316 | 1.45M | 2350434564U, // VLD1q8wb_register |
3317 | 1.45M | 2215176501U, // VLD2DUPd16 |
3318 | 1.45M | 2215160117U, // VLD2DUPd16wb_fixed |
3319 | 1.45M | 2215168309U, // VLD2DUPd16wb_register |
3320 | 1.45M | 2416503093U, // VLD2DUPd16x2 |
3321 | 1.45M | 2416486709U, // VLD2DUPd16x2wb_fixed |
3322 | 1.45M | 2416494901U, // VLD2DUPd16x2wb_register |
3323 | 1.45M | 2215700789U, // VLD2DUPd32 |
3324 | 1.45M | 2215684405U, // VLD2DUPd32wb_fixed |
3325 | 1.45M | 2215692597U, // VLD2DUPd32wb_register |
3326 | 1.45M | 2417027381U, // VLD2DUPd32x2 |
3327 | 1.45M | 2417010997U, // VLD2DUPd32x2wb_fixed |
3328 | 1.45M | 2417019189U, // VLD2DUPd32x2wb_register |
3329 | 1.45M | 2216225077U, // VLD2DUPd8 |
3330 | 1.45M | 2216208693U, // VLD2DUPd8wb_fixed |
3331 | 1.45M | 2216216885U, // VLD2DUPd8wb_register |
3332 | 1.45M | 2417551669U, // VLD2DUPd8x2 |
3333 | 1.45M | 2417535285U, // VLD2DUPd8x2wb_fixed |
3334 | 1.45M | 2417543477U, // VLD2DUPd8x2wb_register |
3335 | 1.45M | 0U, // VLD2DUPq16EvenPseudo |
3336 | 1.45M | 0U, // VLD2DUPq16OddPseudo |
3337 | 1.45M | 0U, // VLD2DUPq16OddPseudoWB_fixed |
3338 | 1.45M | 0U, // VLD2DUPq16OddPseudoWB_register |
3339 | 1.45M | 0U, // VLD2DUPq32EvenPseudo |
3340 | 1.45M | 0U, // VLD2DUPq32OddPseudo |
3341 | 1.45M | 0U, // VLD2DUPq32OddPseudoWB_fixed |
3342 | 1.45M | 0U, // VLD2DUPq32OddPseudoWB_register |
3343 | 1.45M | 0U, // VLD2DUPq8EvenPseudo |
3344 | 1.45M | 0U, // VLD2DUPq8OddPseudo |
3345 | 1.45M | 0U, // VLD2DUPq8OddPseudoWB_fixed |
3346 | 1.45M | 0U, // VLD2DUPq8OddPseudoWB_register |
3347 | 1.45M | 28617013U, // VLD2LNd16 |
3348 | 1.45M | 0U, // VLD2LNd16Pseudo |
3349 | 1.45M | 0U, // VLD2LNd16Pseudo_UPD |
3350 | 1.45M | 28625205U, // VLD2LNd16_UPD |
3351 | 1.45M | 29141301U, // VLD2LNd32 |
3352 | 1.45M | 0U, // VLD2LNd32Pseudo |
3353 | 1.45M | 0U, // VLD2LNd32Pseudo_UPD |
3354 | 1.45M | 29149493U, // VLD2LNd32_UPD |
3355 | 1.45M | 29665589U, // VLD2LNd8 |
3356 | 1.45M | 0U, // VLD2LNd8Pseudo |
3357 | 1.45M | 0U, // VLD2LNd8Pseudo_UPD |
3358 | 1.45M | 29673781U, // VLD2LNd8_UPD |
3359 | 1.45M | 28617013U, // VLD2LNq16 |
3360 | 1.45M | 0U, // VLD2LNq16Pseudo |
3361 | 1.45M | 0U, // VLD2LNq16Pseudo_UPD |
3362 | 1.45M | 28625205U, // VLD2LNq16_UPD |
3363 | 1.45M | 29141301U, // VLD2LNq32 |
3364 | 1.45M | 0U, // VLD2LNq32Pseudo |
3365 | 1.45M | 0U, // VLD2LNq32Pseudo_UPD |
3366 | 1.45M | 29149493U, // VLD2LNq32_UPD |
3367 | 1.45M | 2483611957U, // VLD2b16 |
3368 | 1.45M | 2483595573U, // VLD2b16wb_fixed |
3369 | 1.45M | 2483603765U, // VLD2b16wb_register |
3370 | 1.45M | 2484136245U, // VLD2b32 |
3371 | 1.45M | 2484119861U, // VLD2b32wb_fixed |
3372 | 1.45M | 2484128053U, // VLD2b32wb_register |
3373 | 1.45M | 2484660533U, // VLD2b8 |
3374 | 1.45M | 2484644149U, // VLD2b8wb_fixed |
3375 | 1.45M | 2484652341U, // VLD2b8wb_register |
3376 | 1.45M | 2349394229U, // VLD2d16 |
3377 | 1.45M | 2349377845U, // VLD2d16wb_fixed |
3378 | 1.45M | 2349386037U, // VLD2d16wb_register |
3379 | 1.45M | 2349918517U, // VLD2d32 |
3380 | 1.45M | 2349902133U, // VLD2d32wb_fixed |
3381 | 1.45M | 2349910325U, // VLD2d32wb_register |
3382 | 1.45M | 2350442805U, // VLD2d8 |
3383 | 1.45M | 2350426421U, // VLD2d8wb_fixed |
3384 | 1.45M | 2350434613U, // VLD2d8wb_register |
3385 | 1.45M | 537454901U, // VLD2q16 |
3386 | 1.45M | 0U, // VLD2q16Pseudo |
3387 | 1.45M | 0U, // VLD2q16PseudoWB_fixed |
3388 | 1.45M | 0U, // VLD2q16PseudoWB_register |
3389 | 1.45M | 537438517U, // VLD2q16wb_fixed |
3390 | 1.45M | 537446709U, // VLD2q16wb_register |
3391 | 1.45M | 537979189U, // VLD2q32 |
3392 | 1.45M | 0U, // VLD2q32Pseudo |
3393 | 1.45M | 0U, // VLD2q32PseudoWB_fixed |
3394 | 1.45M | 0U, // VLD2q32PseudoWB_register |
3395 | 1.45M | 537962805U, // VLD2q32wb_fixed |
3396 | 1.45M | 537970997U, // VLD2q32wb_register |
3397 | 1.45M | 538503477U, // VLD2q8 |
3398 | 1.45M | 0U, // VLD2q8Pseudo |
3399 | 1.45M | 0U, // VLD2q8PseudoWB_fixed |
3400 | 1.45M | 0U, // VLD2q8PseudoWB_register |
3401 | 1.45M | 538487093U, // VLD2q8wb_fixed |
3402 | 1.45M | 538495285U, // VLD2q8wb_register |
3403 | 1.45M | 28363098U, // VLD3DUPd16 |
3404 | 1.45M | 0U, // VLD3DUPd16Pseudo |
3405 | 1.45M | 0U, // VLD3DUPd16Pseudo_UPD |
3406 | 1.45M | 28617050U, // VLD3DUPd16_UPD |
3407 | 1.45M | 28887386U, // VLD3DUPd32 |
3408 | 1.45M | 0U, // VLD3DUPd32Pseudo |
3409 | 1.45M | 0U, // VLD3DUPd32Pseudo_UPD |
3410 | 1.45M | 29141338U, // VLD3DUPd32_UPD |
3411 | 1.45M | 29411674U, // VLD3DUPd8 |
3412 | 1.45M | 0U, // VLD3DUPd8Pseudo |
3413 | 1.45M | 0U, // VLD3DUPd8Pseudo_UPD |
3414 | 1.45M | 29665626U, // VLD3DUPd8_UPD |
3415 | 1.45M | 28363098U, // VLD3DUPq16 |
3416 | 1.45M | 0U, // VLD3DUPq16EvenPseudo |
3417 | 1.45M | 0U, // VLD3DUPq16OddPseudo |
3418 | 1.45M | 0U, // VLD3DUPq16OddPseudo_UPD |
3419 | 1.45M | 28617050U, // VLD3DUPq16_UPD |
3420 | 1.45M | 28887386U, // VLD3DUPq32 |
3421 | 1.45M | 0U, // VLD3DUPq32EvenPseudo |
3422 | 1.45M | 0U, // VLD3DUPq32OddPseudo |
3423 | 1.45M | 0U, // VLD3DUPq32OddPseudo_UPD |
3424 | 1.45M | 29141338U, // VLD3DUPq32_UPD |
3425 | 1.45M | 29411674U, // VLD3DUPq8 |
3426 | 1.45M | 0U, // VLD3DUPq8EvenPseudo |
3427 | 1.45M | 0U, // VLD3DUPq8OddPseudo |
3428 | 1.45M | 0U, // VLD3DUPq8OddPseudo_UPD |
3429 | 1.45M | 29665626U, // VLD3DUPq8_UPD |
3430 | 1.45M | 28625242U, // VLD3LNd16 |
3431 | 1.45M | 0U, // VLD3LNd16Pseudo |
3432 | 1.45M | 0U, // VLD3LNd16Pseudo_UPD |
3433 | 1.45M | 28633434U, // VLD3LNd16_UPD |
3434 | 1.45M | 29149530U, // VLD3LNd32 |
3435 | 1.45M | 0U, // VLD3LNd32Pseudo |
3436 | 1.45M | 0U, // VLD3LNd32Pseudo_UPD |
3437 | 1.45M | 29157722U, // VLD3LNd32_UPD |
3438 | 1.45M | 29673818U, // VLD3LNd8 |
3439 | 1.45M | 0U, // VLD3LNd8Pseudo |
3440 | 1.45M | 0U, // VLD3LNd8Pseudo_UPD |
3441 | 1.45M | 29682010U, // VLD3LNd8_UPD |
3442 | 1.45M | 28625242U, // VLD3LNq16 |
3443 | 1.45M | 0U, // VLD3LNq16Pseudo |
3444 | 1.45M | 0U, // VLD3LNq16Pseudo_UPD |
3445 | 1.45M | 28633434U, // VLD3LNq16_UPD |
3446 | 1.45M | 29149530U, // VLD3LNq32 |
3447 | 1.45M | 0U, // VLD3LNq32Pseudo |
3448 | 1.45M | 0U, // VLD3LNq32Pseudo_UPD |
3449 | 1.45M | 29157722U, // VLD3LNq32_UPD |
3450 | 1.45M | 28363098U, // VLD3d16 |
3451 | 1.45M | 0U, // VLD3d16Pseudo |
3452 | 1.45M | 0U, // VLD3d16Pseudo_UPD |
3453 | 1.45M | 28617050U, // VLD3d16_UPD |
3454 | 1.45M | 28887386U, // VLD3d32 |
3455 | 1.45M | 0U, // VLD3d32Pseudo |
3456 | 1.45M | 0U, // VLD3d32Pseudo_UPD |
3457 | 1.45M | 29141338U, // VLD3d32_UPD |
3458 | 1.45M | 29411674U, // VLD3d8 |
3459 | 1.45M | 0U, // VLD3d8Pseudo |
3460 | 1.45M | 0U, // VLD3d8Pseudo_UPD |
3461 | 1.45M | 29665626U, // VLD3d8_UPD |
3462 | 1.45M | 28363098U, // VLD3q16 |
3463 | 1.45M | 0U, // VLD3q16Pseudo_UPD |
3464 | 1.45M | 28617050U, // VLD3q16_UPD |
3465 | 1.45M | 0U, // VLD3q16oddPseudo |
3466 | 1.45M | 0U, // VLD3q16oddPseudo_UPD |
3467 | 1.45M | 28887386U, // VLD3q32 |
3468 | 1.45M | 0U, // VLD3q32Pseudo_UPD |
3469 | 1.45M | 29141338U, // VLD3q32_UPD |
3470 | 1.45M | 0U, // VLD3q32oddPseudo |
3471 | 1.45M | 0U, // VLD3q32oddPseudo_UPD |
3472 | 1.45M | 29411674U, // VLD3q8 |
3473 | 1.45M | 0U, // VLD3q8Pseudo_UPD |
3474 | 1.45M | 29665626U, // VLD3q8_UPD |
3475 | 1.45M | 0U, // VLD3q8oddPseudo |
3476 | 1.45M | 0U, // VLD3q8oddPseudo_UPD |
3477 | 1.45M | 28445046U, // VLD4DUPd16 |
3478 | 1.45M | 0U, // VLD4DUPd16Pseudo |
3479 | 1.45M | 0U, // VLD4DUPd16Pseudo_UPD |
3480 | 1.45M | 28641654U, // VLD4DUPd16_UPD |
3481 | 1.45M | 28969334U, // VLD4DUPd32 |
3482 | 1.45M | 0U, // VLD4DUPd32Pseudo |
3483 | 1.45M | 0U, // VLD4DUPd32Pseudo_UPD |
3484 | 1.45M | 29165942U, // VLD4DUPd32_UPD |
3485 | 1.45M | 29493622U, // VLD4DUPd8 |
3486 | 1.45M | 0U, // VLD4DUPd8Pseudo |
3487 | 1.45M | 0U, // VLD4DUPd8Pseudo_UPD |
3488 | 1.45M | 29690230U, // VLD4DUPd8_UPD |
3489 | 1.45M | 28445046U, // VLD4DUPq16 |
3490 | 1.45M | 0U, // VLD4DUPq16EvenPseudo |
3491 | 1.45M | 0U, // VLD4DUPq16OddPseudo |
3492 | 1.45M | 0U, // VLD4DUPq16OddPseudo_UPD |
3493 | 1.45M | 28641654U, // VLD4DUPq16_UPD |
3494 | 1.45M | 28969334U, // VLD4DUPq32 |
3495 | 1.45M | 0U, // VLD4DUPq32EvenPseudo |
3496 | 1.45M | 0U, // VLD4DUPq32OddPseudo |
3497 | 1.45M | 0U, // VLD4DUPq32OddPseudo_UPD |
3498 | 1.45M | 29165942U, // VLD4DUPq32_UPD |
3499 | 1.45M | 29493622U, // VLD4DUPq8 |
3500 | 1.45M | 0U, // VLD4DUPq8EvenPseudo |
3501 | 1.45M | 0U, // VLD4DUPq8OddPseudo |
3502 | 1.45M | 0U, // VLD4DUPq8OddPseudo_UPD |
3503 | 1.45M | 29690230U, // VLD4DUPq8_UPD |
3504 | 1.45M | 28633462U, // VLD4LNd16 |
3505 | 1.45M | 0U, // VLD4LNd16Pseudo |
3506 | 1.45M | 0U, // VLD4LNd16Pseudo_UPD |
3507 | 1.45M | 28649846U, // VLD4LNd16_UPD |
3508 | 1.45M | 29157750U, // VLD4LNd32 |
3509 | 1.45M | 0U, // VLD4LNd32Pseudo |
3510 | 1.45M | 0U, // VLD4LNd32Pseudo_UPD |
3511 | 1.45M | 29174134U, // VLD4LNd32_UPD |
3512 | 1.45M | 29682038U, // VLD4LNd8 |
3513 | 1.45M | 0U, // VLD4LNd8Pseudo |
3514 | 1.45M | 0U, // VLD4LNd8Pseudo_UPD |
3515 | 1.45M | 29698422U, // VLD4LNd8_UPD |
3516 | 1.45M | 28633462U, // VLD4LNq16 |
3517 | 1.45M | 0U, // VLD4LNq16Pseudo |
3518 | 1.45M | 0U, // VLD4LNq16Pseudo_UPD |
3519 | 1.45M | 28649846U, // VLD4LNq16_UPD |
3520 | 1.45M | 29157750U, // VLD4LNq32 |
3521 | 1.45M | 0U, // VLD4LNq32Pseudo |
3522 | 1.45M | 0U, // VLD4LNq32Pseudo_UPD |
3523 | 1.45M | 29174134U, // VLD4LNq32_UPD |
3524 | 1.45M | 28445046U, // VLD4d16 |
3525 | 1.45M | 0U, // VLD4d16Pseudo |
3526 | 1.45M | 0U, // VLD4d16Pseudo_UPD |
3527 | 1.45M | 28641654U, // VLD4d16_UPD |
3528 | 1.45M | 28969334U, // VLD4d32 |
3529 | 1.45M | 0U, // VLD4d32Pseudo |
3530 | 1.45M | 0U, // VLD4d32Pseudo_UPD |
3531 | 1.45M | 29165942U, // VLD4d32_UPD |
3532 | 1.45M | 29493622U, // VLD4d8 |
3533 | 1.45M | 0U, // VLD4d8Pseudo |
3534 | 1.45M | 0U, // VLD4d8Pseudo_UPD |
3535 | 1.45M | 29690230U, // VLD4d8_UPD |
3536 | 1.45M | 28445046U, // VLD4q16 |
3537 | 1.45M | 0U, // VLD4q16Pseudo_UPD |
3538 | 1.45M | 28641654U, // VLD4q16_UPD |
3539 | 1.45M | 0U, // VLD4q16oddPseudo |
3540 | 1.45M | 0U, // VLD4q16oddPseudo_UPD |
3541 | 1.45M | 28969334U, // VLD4q32 |
3542 | 1.45M | 0U, // VLD4q32Pseudo_UPD |
3543 | 1.45M | 29165942U, // VLD4q32_UPD |
3544 | 1.45M | 0U, // VLD4q32oddPseudo |
3545 | 1.45M | 0U, // VLD4q32oddPseudo_UPD |
3546 | 1.45M | 29493622U, // VLD4q8 |
3547 | 1.45M | 0U, // VLD4q8Pseudo_UPD |
3548 | 1.45M | 29690230U, // VLD4q8_UPD |
3549 | 1.45M | 0U, // VLD4q8oddPseudo |
3550 | 1.45M | 0U, // VLD4q8oddPseudo_UPD |
3551 | 1.45M | 875064290U, // VLDMDDB_UPD |
3552 | 1.45M | 2730766U, // VLDMDIA |
3553 | 1.45M | 875064078U, // VLDMDIA_UPD |
3554 | 1.45M | 0U, // VLDMQIA |
3555 | 1.45M | 875064290U, // VLDMSDB_UPD |
3556 | 1.45M | 2730766U, // VLDMSIA |
3557 | 1.45M | 875064078U, // VLDMSIA_UPD |
3558 | 1.45M | 2683301U, // VLDRD |
3559 | 1.45M | 586149U, // VLDRH |
3560 | 1.45M | 2683301U, // VLDRS |
3561 | 1.45M | 2580050341U, // VLDR_FPCXTNS_off |
3562 | 1.45M | 701034917U, // VLDR_FPCXTNS_post |
3563 | 1.45M | 2647191973U, // VLDR_FPCXTNS_pre |
3564 | 1.45M | 2580574629U, // VLDR_FPCXTS_off |
3565 | 1.45M | 701559205U, // VLDR_FPCXTS_post |
3566 | 1.45M | 2647716261U, // VLDR_FPCXTS_pre |
3567 | 1.45M | 2581098917U, // VLDR_FPSCR_NZCVQC_off |
3568 | 1.45M | 702083493U, // VLDR_FPSCR_NZCVQC_post |
3569 | 1.45M | 2648240549U, // VLDR_FPSCR_NZCVQC_pre |
3570 | 1.45M | 2581623205U, // VLDR_FPSCR_off |
3571 | 1.45M | 702607781U, // VLDR_FPSCR_post |
3572 | 1.45M | 2648764837U, // VLDR_FPSCR_pre |
3573 | 1.45M | 2716397989U, // VLDR_P0_off |
3574 | 1.45M | 1642639781U, // VLDR_P0_post |
3575 | 1.45M | 2783490469U, // VLDR_P0_pre |
3576 | 1.45M | 2582671781U, // VLDR_VPR_off |
3577 | 1.45M | 703656357U, // VLDR_VPR_post |
3578 | 1.45M | 2649813413U, // VLDR_VPR_pre |
3579 | 1.45M | 2732105U, // VLLDM |
3580 | 1.45M | 2732140U, // VLSTM |
3581 | 1.45M | 7926951U, // VMAXfd |
3582 | 1.45M | 7926951U, // VMAXfq |
3583 | 1.45M | 7402663U, // VMAXhd |
3584 | 1.45M | 7402663U, // VMAXhq |
3585 | 1.45M | 12121255U, // VMAXsv16i8 |
3586 | 1.45M | 11596967U, // VMAXsv2i32 |
3587 | 1.45M | 11072679U, // VMAXsv4i16 |
3588 | 1.45M | 11596967U, // VMAXsv4i32 |
3589 | 1.45M | 11072679U, // VMAXsv8i16 |
3590 | 1.45M | 12121255U, // VMAXsv8i8 |
3591 | 1.45M | 13694119U, // VMAXuv16i8 |
3592 | 1.45M | 13169831U, // VMAXuv2i32 |
3593 | 1.45M | 12645543U, // VMAXuv4i16 |
3594 | 1.45M | 13169831U, // VMAXuv4i32 |
3595 | 1.45M | 12645543U, // VMAXuv8i16 |
3596 | 1.45M | 13694119U, // VMAXuv8i8 |
3597 | 1.45M | 7925916U, // VMINfd |
3598 | 1.45M | 7925916U, // VMINfq |
3599 | 1.45M | 7401628U, // VMINhd |
3600 | 1.45M | 7401628U, // VMINhq |
3601 | 1.45M | 12120220U, // VMINsv16i8 |
3602 | 1.45M | 11595932U, // VMINsv2i32 |
3603 | 1.45M | 11071644U, // VMINsv4i16 |
3604 | 1.45M | 11595932U, // VMINsv4i32 |
3605 | 1.45M | 11071644U, // VMINsv8i16 |
3606 | 1.45M | 12120220U, // VMINsv8i8 |
3607 | 1.45M | 13693084U, // VMINuv16i8 |
3608 | 1.45M | 13168796U, // VMINuv2i32 |
3609 | 1.45M | 12644508U, // VMINuv4i16 |
3610 | 1.45M | 13168796U, // VMINuv4i32 |
3611 | 1.45M | 12644508U, // VMINuv8i16 |
3612 | 1.45M | 13693084U, // VMINuv8i8 |
3613 | 1.45M | 1147710260U, // VMLAD |
3614 | 1.45M | 7383860U, // VMLAH |
3615 | 1.45M | 11587401U, // VMLALslsv2i32 |
3616 | 1.45M | 11063113U, // VMLALslsv4i16 |
3617 | 1.45M | 13160265U, // VMLALsluv2i32 |
3618 | 1.45M | 12635977U, // VMLALsluv4i16 |
3619 | 1.45M | 11579209U, // VMLALsv2i64 |
3620 | 1.45M | 11054921U, // VMLALsv4i32 |
3621 | 1.45M | 12103497U, // VMLALsv8i16 |
3622 | 1.45M | 13152073U, // VMLALuv2i64 |
3623 | 1.45M | 12627785U, // VMLALuv4i32 |
3624 | 1.45M | 13676361U, // VMLALuv8i16 |
3625 | 1.45M | 7908148U, // VMLAS |
3626 | 1.45M | 7908148U, // VMLAfd |
3627 | 1.45M | 7908148U, // VMLAfq |
3628 | 1.45M | 7383860U, // VMLAhd |
3629 | 1.45M | 7383860U, // VMLAhq |
3630 | 1.45M | 7916340U, // VMLAslfd |
3631 | 1.45M | 7916340U, // VMLAslfq |
3632 | 1.45M | 7392052U, // VMLAslhd |
3633 | 1.45M | 7392052U, // VMLAslhq |
3634 | 1.45M | 14207796U, // VMLAslv2i32 |
3635 | 1.45M | 14732084U, // VMLAslv4i16 |
3636 | 1.45M | 14207796U, // VMLAslv4i32 |
3637 | 1.45M | 14732084U, // VMLAslv8i16 |
3638 | 1.45M | 15248180U, // VMLAv16i8 |
3639 | 1.45M | 14199604U, // VMLAv2i32 |
3640 | 1.45M | 14723892U, // VMLAv4i16 |
3641 | 1.45M | 14199604U, // VMLAv4i32 |
3642 | 1.45M | 14723892U, // VMLAv8i16 |
3643 | 1.45M | 15248180U, // VMLAv8i8 |
3644 | 1.45M | 1147712055U, // VMLSD |
3645 | 1.45M | 7385655U, // VMLSH |
3646 | 1.45M | 11587618U, // VMLSLslsv2i32 |
3647 | 1.45M | 11063330U, // VMLSLslsv4i16 |
3648 | 1.45M | 13160482U, // VMLSLsluv2i32 |
3649 | 1.45M | 12636194U, // VMLSLsluv4i16 |
3650 | 1.45M | 11579426U, // VMLSLsv2i64 |
3651 | 1.45M | 11055138U, // VMLSLsv4i32 |
3652 | 1.45M | 12103714U, // VMLSLsv8i16 |
3653 | 1.45M | 13152290U, // VMLSLuv2i64 |
3654 | 1.45M | 12628002U, // VMLSLuv4i32 |
3655 | 1.45M | 13676578U, // VMLSLuv8i16 |
3656 | 1.45M | 7909943U, // VMLSS |
3657 | 1.45M | 7909943U, // VMLSfd |
3658 | 1.45M | 7909943U, // VMLSfq |
3659 | 1.45M | 7385655U, // VMLShd |
3660 | 1.45M | 7385655U, // VMLShq |
3661 | 1.45M | 7918135U, // VMLSslfd |
3662 | 1.45M | 7918135U, // VMLSslfq |
3663 | 1.45M | 7393847U, // VMLSslhd |
3664 | 1.45M | 7393847U, // VMLSslhq |
3665 | 1.45M | 14209591U, // VMLSslv2i32 |
3666 | 1.45M | 14733879U, // VMLSslv4i16 |
3667 | 1.45M | 14209591U, // VMLSslv4i32 |
3668 | 1.45M | 14733879U, // VMLSslv8i16 |
3669 | 1.45M | 15249975U, // VMLSv16i8 |
3670 | 1.45M | 14201399U, // VMLSv2i32 |
3671 | 1.45M | 14725687U, // VMLSv4i16 |
3672 | 1.45M | 14201399U, // VMLSv4i32 |
3673 | 1.45M | 14725687U, // VMLSv8i16 |
3674 | 1.45M | 15249975U, // VMLSv8i8 |
3675 | 1.45M | 808543674U, // VMMLA |
3676 | 1.45M | 1147696202U, // VMOVD |
3677 | 1.45M | 2683978U, // VMOVDRR |
3678 | 1.45M | 875644323U, // VMOVH |
3679 | 1.45M | 7369802U, // VMOVHR |
3680 | 1.45M | 11563075U, // VMOVLsv2i64 |
3681 | 1.45M | 11038787U, // VMOVLsv4i32 |
3682 | 1.45M | 12087363U, // VMOVLsv8i16 |
3683 | 1.45M | 13135939U, // VMOVLuv2i64 |
3684 | 1.45M | 12611651U, // VMOVLuv4i32 |
3685 | 1.45M | 13660227U, // VMOVLuv8i16 |
3686 | 1.45M | 895512829U, // VMOVNv2i32 |
3687 | 1.45M | 14184701U, // VMOVNv4i16 |
3688 | 1.45M | 14708989U, // VMOVNv8i8 |
3689 | 1.45M | 7369802U, // VMOVRH |
3690 | 1.45M | 2683978U, // VMOVRRD |
3691 | 1.45M | 2667594U, // VMOVRRS |
3692 | 1.45M | 2651210U, // VMOVRS |
3693 | 1.45M | 7894090U, // VMOVS |
3694 | 1.45M | 2651210U, // VMOVSR |
3695 | 1.45M | 2667594U, // VMOVSRR |
3696 | 1.45M | 15234122U, // VMOVv16i8 |
3697 | 1.45M | 2036364362U, // VMOVv1i64 |
3698 | 1.45M | 7894090U, // VMOVv2f32 |
3699 | 1.45M | 14185546U, // VMOVv2i32 |
3700 | 1.45M | 2036364362U, // VMOVv2i64 |
3701 | 1.45M | 7894090U, // VMOVv4f32 |
3702 | 1.45M | 14709834U, // VMOVv4i16 |
3703 | 1.45M | 14185546U, // VMOVv4i32 |
3704 | 1.45M | 14709834U, // VMOVv8i16 |
3705 | 1.45M | 15234122U, // VMOVv8i8 |
3706 | 1.45M | 2732633U, // VMRS |
3707 | 1.45M | 2732633U, // VMRS_FPCXTNS |
3708 | 1.45M | 2732633U, // VMRS_FPCXTS |
3709 | 1.45M | 2732633U, // VMRS_FPEXC |
3710 | 1.45M | 2732633U, // VMRS_FPINST |
3711 | 1.45M | 2732633U, // VMRS_FPINST2 |
3712 | 1.45M | 2650713U, // VMRS_FPSCR_NZCVQC |
3713 | 1.45M | 2732633U, // VMRS_FPSID |
3714 | 1.45M | 2732633U, // VMRS_MVFR0 |
3715 | 1.45M | 2732633U, // VMRS_MVFR1 |
3716 | 1.45M | 2732633U, // VMRS_MVFR2 |
3717 | 1.45M | 2650713U, // VMRS_P0 |
3718 | 1.45M | 2732633U, // VMRS_VPR |
3719 | 1.45M | 31568365U, // VMSR |
3720 | 1.45M | 29995501U, // VMSR_FPCXTNS |
3721 | 1.45M | 30519789U, // VMSR_FPCXTS |
3722 | 1.45M | 33141229U, // VMSR_FPEXC |
3723 | 1.45M | 33665517U, // VMSR_FPINST |
3724 | 1.45M | 34189805U, // VMSR_FPINST2 |
3725 | 1.45M | 903377389U, // VMSR_FPSCR_NZCVQC |
3726 | 1.45M | 34714093U, // VMSR_FPSID |
3727 | 1.45M | 904425965U, // VMSR_P0 |
3728 | 1.45M | 32616941U, // VMSR_VPR |
3729 | 1.45M | 1147727934U, // VMULD |
3730 | 1.45M | 7401534U, // VMULH |
3731 | 1.45M | 875643746U, // VMULLp64 |
3732 | 1.45M | 24178671U, // VMULLp8 |
3733 | 1.45M | 11579375U, // VMULLslsv2i32 |
3734 | 1.45M | 11055087U, // VMULLslsv4i16 |
3735 | 1.45M | 13152239U, // VMULLsluv2i32 |
3736 | 1.45M | 12627951U, // VMULLsluv4i16 |
3737 | 1.45M | 11595759U, // VMULLsv2i64 |
3738 | 1.45M | 11071471U, // VMULLsv4i32 |
3739 | 1.45M | 12120047U, // VMULLsv8i16 |
3740 | 1.45M | 13168623U, // VMULLuv2i64 |
3741 | 1.45M | 12644335U, // VMULLuv4i32 |
3742 | 1.45M | 13692911U, // VMULLuv8i16 |
3743 | 1.45M | 7925822U, // VMULS |
3744 | 1.45M | 7925822U, // VMULfd |
3745 | 1.45M | 7925822U, // VMULfq |
3746 | 1.45M | 7401534U, // VMULhd |
3747 | 1.45M | 7401534U, // VMULhq |
3748 | 1.45M | 24178750U, // VMULpd |
3749 | 1.45M | 24178750U, // VMULpq |
3750 | 1.45M | 7909438U, // VMULslfd |
3751 | 1.45M | 7909438U, // VMULslfq |
3752 | 1.45M | 7385150U, // VMULslhd |
3753 | 1.45M | 7385150U, // VMULslhq |
3754 | 1.45M | 14200894U, // VMULslv2i32 |
3755 | 1.45M | 14725182U, // VMULslv4i16 |
3756 | 1.45M | 14200894U, // VMULslv4i32 |
3757 | 1.45M | 14725182U, // VMULslv8i16 |
3758 | 1.45M | 15265854U, // VMULv16i8 |
3759 | 1.45M | 14217278U, // VMULv2i32 |
3760 | 1.45M | 14741566U, // VMULv4i16 |
3761 | 1.45M | 14217278U, // VMULv4i32 |
3762 | 1.45M | 14741566U, // VMULv8i16 |
3763 | 1.45M | 15265854U, // VMULv8i8 |
3764 | 1.45M | 2650353U, // VMVNd |
3765 | 1.45M | 2650353U, // VMVNq |
3766 | 1.45M | 14184689U, // VMVNv2i32 |
3767 | 1.45M | 14708977U, // VMVNv4i16 |
3768 | 1.45M | 14184689U, // VMVNv4i32 |
3769 | 1.45M | 14708977U, // VMVNv8i16 |
3770 | 1.45M | 1147694595U, // VNEGD |
3771 | 1.45M | 7368195U, // VNEGH |
3772 | 1.45M | 7892483U, // VNEGS |
3773 | 1.45M | 7892483U, // VNEGf32q |
3774 | 1.45M | 7892483U, // VNEGfd |
3775 | 1.45M | 7368195U, // VNEGhd |
3776 | 1.45M | 7368195U, // VNEGhq |
3777 | 1.45M | 11038211U, // VNEGs16d |
3778 | 1.45M | 11038211U, // VNEGs16q |
3779 | 1.45M | 11562499U, // VNEGs32d |
3780 | 1.45M | 11562499U, // VNEGs32q |
3781 | 1.45M | 12086787U, // VNEGs8d |
3782 | 1.45M | 12086787U, // VNEGs8q |
3783 | 1.45M | 1147710254U, // VNMLAD |
3784 | 1.45M | 7383854U, // VNMLAH |
3785 | 1.45M | 7908142U, // VNMLAS |
3786 | 1.45M | 1147712049U, // VNMLSD |
3787 | 1.45M | 7385649U, // VNMLSH |
3788 | 1.45M | 7909937U, // VNMLSS |
3789 | 1.45M | 1147727928U, // VNMULD |
3790 | 1.45M | 7401528U, // VNMULH |
3791 | 1.45M | 7925816U, // VNMULS |
3792 | 1.45M | 2683073U, // VORNd |
3793 | 1.45M | 2683073U, // VORNq |
3794 | 1.45M | 2683357U, // VORRd |
3795 | 1.45M | 14217693U, // VORRiv2i32 |
3796 | 1.45M | 14741981U, // VORRiv4i16 |
3797 | 1.45M | 14217693U, // VORRiv4i32 |
3798 | 1.45M | 14741981U, // VORRiv8i16 |
3799 | 1.45M | 2683357U, // VORRq |
3800 | 1.45M | 12119854U, // VPADALsv16i8 |
3801 | 1.45M | 11595566U, // VPADALsv2i32 |
3802 | 1.45M | 11071278U, // VPADALsv4i16 |
3803 | 1.45M | 11595566U, // VPADALsv4i32 |
3804 | 1.45M | 11071278U, // VPADALsv8i16 |
3805 | 1.45M | 12119854U, // VPADALsv8i8 |
3806 | 1.45M | 13692718U, // VPADALuv16i8 |
3807 | 1.45M | 13168430U, // VPADALuv2i32 |
3808 | 1.45M | 12644142U, // VPADALuv4i16 |
3809 | 1.45M | 13168430U, // VPADALuv4i32 |
3810 | 1.45M | 12644142U, // VPADALuv8i16 |
3811 | 1.45M | 13692718U, // VPADALuv8i8 |
3812 | 1.45M | 12087146U, // VPADDLsv16i8 |
3813 | 1.45M | 11562858U, // VPADDLsv2i32 |
3814 | 1.45M | 11038570U, // VPADDLsv4i16 |
3815 | 1.45M | 11562858U, // VPADDLsv4i32 |
3816 | 1.45M | 11038570U, // VPADDLsv8i16 |
3817 | 1.45M | 12087146U, // VPADDLsv8i8 |
3818 | 1.45M | 13660010U, // VPADDLuv16i8 |
3819 | 1.45M | 13135722U, // VPADDLuv2i32 |
3820 | 1.45M | 12611434U, // VPADDLuv4i16 |
3821 | 1.45M | 13135722U, // VPADDLuv4i32 |
3822 | 1.45M | 12611434U, // VPADDLuv8i16 |
3823 | 1.45M | 13660010U, // VPADDLuv8i8 |
3824 | 1.45M | 7925099U, // VPADDf |
3825 | 1.45M | 7400811U, // VPADDh |
3826 | 1.45M | 14740843U, // VPADDi16 |
3827 | 1.45M | 14216555U, // VPADDi32 |
3828 | 1.45M | 15265131U, // VPADDi8 |
3829 | 1.45M | 7926945U, // VPMAXf |
3830 | 1.45M | 7402657U, // VPMAXh |
3831 | 1.45M | 11072673U, // VPMAXs16 |
3832 | 1.45M | 11596961U, // VPMAXs32 |
3833 | 1.45M | 12121249U, // VPMAXs8 |
3834 | 1.45M | 12645537U, // VPMAXu16 |
3835 | 1.45M | 13169825U, // VPMAXu32 |
3836 | 1.45M | 13694113U, // VPMAXu8 |
3837 | 1.45M | 7925910U, // VPMINf |
3838 | 1.45M | 7401622U, // VPMINh |
3839 | 1.45M | 11071638U, // VPMINs16 |
3840 | 1.45M | 11595926U, // VPMINs32 |
3841 | 1.45M | 12120214U, // VPMINs8 |
3842 | 1.45M | 12644502U, // VPMINu16 |
3843 | 1.45M | 13168790U, // VPMINu32 |
3844 | 1.45M | 13693078U, // VPMINu8 |
3845 | 1.45M | 12087830U, // VQABSv16i8 |
3846 | 1.45M | 11563542U, // VQABSv2i32 |
3847 | 1.45M | 11039254U, // VQABSv4i16 |
3848 | 1.45M | 11563542U, // VQABSv4i32 |
3849 | 1.45M | 11039254U, // VQABSv8i16 |
3850 | 1.45M | 12087830U, // VQABSv8i8 |
3851 | 1.45M | 12119409U, // VQADDsv16i8 |
3852 | 1.45M | 907603313U, // VQADDsv1i64 |
3853 | 1.45M | 11595121U, // VQADDsv2i32 |
3854 | 1.45M | 907603313U, // VQADDsv2i64 |
3855 | 1.45M | 11070833U, // VQADDsv4i16 |
3856 | 1.45M | 11595121U, // VQADDsv4i32 |
3857 | 1.45M | 11070833U, // VQADDsv8i16 |
3858 | 1.45M | 12119409U, // VQADDsv8i8 |
3859 | 1.45M | 13692273U, // VQADDuv16i8 |
3860 | 1.45M | 22605169U, // VQADDuv1i64 |
3861 | 1.45M | 13167985U, // VQADDuv2i32 |
3862 | 1.45M | 22605169U, // VQADDuv2i64 |
3863 | 1.45M | 12643697U, // VQADDuv4i16 |
3864 | 1.45M | 13167985U, // VQADDuv4i32 |
3865 | 1.45M | 12643697U, // VQADDuv8i16 |
3866 | 1.45M | 13692273U, // VQADDuv8i8 |
3867 | 1.45M | 11587381U, // VQDMLALslv2i32 |
3868 | 1.45M | 11063093U, // VQDMLALslv4i16 |
3869 | 1.45M | 11579189U, // VQDMLALv2i64 |
3870 | 1.45M | 11054901U, // VQDMLALv4i32 |
3871 | 1.45M | 11587610U, // VQDMLSLslv2i32 |
3872 | 1.45M | 11063322U, // VQDMLSLslv4i16 |
3873 | 1.45M | 11579418U, // VQDMLSLv2i64 |
3874 | 1.45M | 11055130U, // VQDMLSLv4i32 |
3875 | 1.45M | 11578977U, // VQDMULHslv2i32 |
3876 | 1.45M | 11054689U, // VQDMULHslv4i16 |
3877 | 1.45M | 11578977U, // VQDMULHslv4i32 |
3878 | 1.45M | 11054689U, // VQDMULHslv8i16 |
3879 | 1.45M | 11595361U, // VQDMULHv2i32 |
3880 | 1.45M | 11071073U, // VQDMULHv4i16 |
3881 | 1.45M | 11595361U, // VQDMULHv4i32 |
3882 | 1.45M | 11071073U, // VQDMULHv8i16 |
3883 | 1.45M | 11579355U, // VQDMULLslv2i32 |
3884 | 1.45M | 11055067U, // VQDMULLslv4i16 |
3885 | 1.45M | 11595739U, // VQDMULLv2i64 |
3886 | 1.45M | 11071451U, // VQDMULLv4i32 |
3887 | 1.45M | 907571433U, // VQMOVNsuv2i32 |
3888 | 1.45M | 11563241U, // VQMOVNsuv4i16 |
3889 | 1.45M | 11038953U, // VQMOVNsuv8i8 |
3890 | 1.45M | 907571446U, // VQMOVNsv2i32 |
3891 | 1.45M | 11563254U, // VQMOVNsv4i16 |
3892 | 1.45M | 11038966U, // VQMOVNsv8i8 |
3893 | 1.45M | 22573302U, // VQMOVNuv2i32 |
3894 | 1.45M | 13136118U, // VQMOVNuv4i16 |
3895 | 1.45M | 12611830U, // VQMOVNuv8i8 |
3896 | 1.45M | 12086781U, // VQNEGv16i8 |
3897 | 1.45M | 11562493U, // VQNEGv2i32 |
3898 | 1.45M | 11038205U, // VQNEGv4i16 |
3899 | 1.45M | 11562493U, // VQNEGv4i32 |
3900 | 1.45M | 11038205U, // VQNEGv8i16 |
3901 | 1.45M | 12086781U, // VQNEGv8i8 |
3902 | 1.45M | 11587101U, // VQRDMLAHslv2i32 |
3903 | 1.45M | 11062813U, // VQRDMLAHslv4i16 |
3904 | 1.45M | 11587101U, // VQRDMLAHslv4i32 |
3905 | 1.45M | 11062813U, // VQRDMLAHslv8i16 |
3906 | 1.45M | 11578909U, // VQRDMLAHv2i32 |
3907 | 1.45M | 11054621U, // VQRDMLAHv4i16 |
3908 | 1.45M | 11578909U, // VQRDMLAHv4i32 |
3909 | 1.45M | 11054621U, // VQRDMLAHv8i16 |
3910 | 1.45M | 11587230U, // VQRDMLSHslv2i32 |
3911 | 1.45M | 11062942U, // VQRDMLSHslv4i16 |
3912 | 1.45M | 11587230U, // VQRDMLSHslv4i32 |
3913 | 1.45M | 11062942U, // VQRDMLSHslv8i16 |
3914 | 1.45M | 11579038U, // VQRDMLSHv2i32 |
3915 | 1.45M | 11054750U, // VQRDMLSHv4i16 |
3916 | 1.45M | 11579038U, // VQRDMLSHv4i32 |
3917 | 1.45M | 11054750U, // VQRDMLSHv8i16 |
3918 | 1.45M | 11578985U, // VQRDMULHslv2i32 |
3919 | 1.45M | 11054697U, // VQRDMULHslv4i16 |
3920 | 1.45M | 11578985U, // VQRDMULHslv4i32 |
3921 | 1.45M | 11054697U, // VQRDMULHslv8i16 |
3922 | 1.45M | 11595369U, // VQRDMULHv2i32 |
3923 | 1.45M | 11071081U, // VQRDMULHv4i16 |
3924 | 1.45M | 11595369U, // VQRDMULHv4i32 |
3925 | 1.45M | 11071081U, // VQRDMULHv8i16 |
3926 | 1.45M | 12119962U, // VQRSHLsv16i8 |
3927 | 1.45M | 907603866U, // VQRSHLsv1i64 |
3928 | 1.45M | 11595674U, // VQRSHLsv2i32 |
3929 | 1.45M | 907603866U, // VQRSHLsv2i64 |
3930 | 1.45M | 11071386U, // VQRSHLsv4i16 |
3931 | 1.45M | 11595674U, // VQRSHLsv4i32 |
3932 | 1.45M | 11071386U, // VQRSHLsv8i16 |
3933 | 1.45M | 12119962U, // VQRSHLsv8i8 |
3934 | 1.45M | 13692826U, // VQRSHLuv16i8 |
3935 | 1.45M | 22605722U, // VQRSHLuv1i64 |
3936 | 1.45M | 13168538U, // VQRSHLuv2i32 |
3937 | 1.45M | 22605722U, // VQRSHLuv2i64 |
3938 | 1.45M | 12644250U, // VQRSHLuv4i16 |
3939 | 1.45M | 13168538U, // VQRSHLuv4i32 |
3940 | 1.45M | 12644250U, // VQRSHLuv8i16 |
3941 | 1.45M | 13692826U, // VQRSHLuv8i8 |
3942 | 1.45M | 907604140U, // VQRSHRNsv2i32 |
3943 | 1.45M | 11595948U, // VQRSHRNsv4i16 |
3944 | 1.45M | 11071660U, // VQRSHRNsv8i8 |
3945 | 1.45M | 22605996U, // VQRSHRNuv2i32 |
3946 | 1.45M | 13168812U, // VQRSHRNuv4i16 |
3947 | 1.45M | 12644524U, // VQRSHRNuv8i8 |
3948 | 1.45M | 907604192U, // VQRSHRUNv2i32 |
3949 | 1.45M | 11596000U, // VQRSHRUNv4i16 |
3950 | 1.45M | 11071712U, // VQRSHRUNv8i8 |
3951 | 1.45M | 12119949U, // VQSHLsiv16i8 |
3952 | 1.45M | 907603853U, // VQSHLsiv1i64 |
3953 | 1.45M | 11595661U, // VQSHLsiv2i32 |
3954 | 1.45M | 907603853U, // VQSHLsiv2i64 |
3955 | 1.45M | 11071373U, // VQSHLsiv4i16 |
3956 | 1.45M | 11595661U, // VQSHLsiv4i32 |
3957 | 1.45M | 11071373U, // VQSHLsiv8i16 |
3958 | 1.45M | 12119949U, // VQSHLsiv8i8 |
3959 | 1.45M | 12121029U, // VQSHLsuv16i8 |
3960 | 1.45M | 907604933U, // VQSHLsuv1i64 |
3961 | 1.45M | 11596741U, // VQSHLsuv2i32 |
3962 | 1.45M | 907604933U, // VQSHLsuv2i64 |
3963 | 1.45M | 11072453U, // VQSHLsuv4i16 |
3964 | 1.45M | 11596741U, // VQSHLsuv4i32 |
3965 | 1.45M | 11072453U, // VQSHLsuv8i16 |
3966 | 1.45M | 12121029U, // VQSHLsuv8i8 |
3967 | 1.45M | 12119949U, // VQSHLsv16i8 |
3968 | 1.45M | 907603853U, // VQSHLsv1i64 |
3969 | 1.45M | 11595661U, // VQSHLsv2i32 |
3970 | 1.45M | 907603853U, // VQSHLsv2i64 |
3971 | 1.45M | 11071373U, // VQSHLsv4i16 |
3972 | 1.45M | 11595661U, // VQSHLsv4i32 |
3973 | 1.45M | 11071373U, // VQSHLsv8i16 |
3974 | 1.45M | 12119949U, // VQSHLsv8i8 |
3975 | 1.45M | 13692813U, // VQSHLuiv16i8 |
3976 | 1.45M | 22605709U, // VQSHLuiv1i64 |
3977 | 1.45M | 13168525U, // VQSHLuiv2i32 |
3978 | 1.45M | 22605709U, // VQSHLuiv2i64 |
3979 | 1.45M | 12644237U, // VQSHLuiv4i16 |
3980 | 1.45M | 13168525U, // VQSHLuiv4i32 |
3981 | 1.45M | 12644237U, // VQSHLuiv8i16 |
3982 | 1.45M | 13692813U, // VQSHLuiv8i8 |
3983 | 1.45M | 13692813U, // VQSHLuv16i8 |
3984 | 1.45M | 22605709U, // VQSHLuv1i64 |
3985 | 1.45M | 13168525U, // VQSHLuv2i32 |
3986 | 1.45M | 22605709U, // VQSHLuv2i64 |
3987 | 1.45M | 12644237U, // VQSHLuv4i16 |
3988 | 1.45M | 13168525U, // VQSHLuv4i32 |
3989 | 1.45M | 12644237U, // VQSHLuv8i16 |
3990 | 1.45M | 13692813U, // VQSHLuv8i8 |
3991 | 1.45M | 907604133U, // VQSHRNsv2i32 |
3992 | 1.45M | 11595941U, // VQSHRNsv4i16 |
3993 | 1.45M | 11071653U, // VQSHRNsv8i8 |
3994 | 1.45M | 22605989U, // VQSHRNuv2i32 |
3995 | 1.45M | 13168805U, // VQSHRNuv4i16 |
3996 | 1.45M | 12644517U, // VQSHRNuv8i8 |
3997 | 1.45M | 907604184U, // VQSHRUNv2i32 |
3998 | 1.45M | 11595992U, // VQSHRUNv4i16 |
3999 | 1.45M | 11071704U, // VQSHRUNv8i8 |
4000 | 1.45M | 12119247U, // VQSUBsv16i8 |
4001 | 1.45M | 907603151U, // VQSUBsv1i64 |
4002 | 1.45M | 11594959U, // VQSUBsv2i32 |
4003 | 1.45M | 907603151U, // VQSUBsv2i64 |
4004 | 1.45M | 11070671U, // VQSUBsv4i16 |
4005 | 1.45M | 11594959U, // VQSUBsv4i32 |
4006 | 1.45M | 11070671U, // VQSUBsv8i16 |
4007 | 1.45M | 12119247U, // VQSUBsv8i8 |
4008 | 1.45M | 13692111U, // VQSUBuv16i8 |
4009 | 1.45M | 22605007U, // VQSUBuv1i64 |
4010 | 1.45M | 13167823U, // VQSUBuv2i32 |
4011 | 1.45M | 22605007U, // VQSUBuv2i64 |
4012 | 1.45M | 12643535U, // VQSUBuv4i16 |
4013 | 1.45M | 13167823U, // VQSUBuv4i32 |
4014 | 1.45M | 12643535U, // VQSUBuv8i16 |
4015 | 1.45M | 13692111U, // VQSUBuv8i8 |
4016 | 1.45M | 895545479U, // VRADDHNv2i32 |
4017 | 1.45M | 14217351U, // VRADDHNv4i16 |
4018 | 1.45M | 14741639U, // VRADDHNv8i8 |
4019 | 1.45M | 13135319U, // VRECPEd |
4020 | 1.45M | 7892439U, // VRECPEfd |
4021 | 1.45M | 7892439U, // VRECPEfq |
4022 | 1.45M | 7368151U, // VRECPEhd |
4023 | 1.45M | 7368151U, // VRECPEhq |
4024 | 1.45M | 13135319U, // VRECPEq |
4025 | 1.45M | 7926354U, // VRECPSfd |
4026 | 1.45M | 7926354U, // VRECPSfq |
4027 | 1.45M | 7402066U, // VRECPShd |
4028 | 1.45M | 7402066U, // VRECPShq |
4029 | 1.45M | 1599992U, // VREV16d8 |
4030 | 1.45M | 1599992U, // VREV16q8 |
4031 | 1.45M | 551193U, // VREV32d16 |
4032 | 1.45M | 1599769U, // VREV32d8 |
4033 | 1.45M | 551193U, // VREV32q16 |
4034 | 1.45M | 1599769U, // VREV32q8 |
4035 | 1.45M | 551279U, // VREV64d16 |
4036 | 1.45M | 1075567U, // VREV64d32 |
4037 | 1.45M | 1599855U, // VREV64d8 |
4038 | 1.45M | 551279U, // VREV64q16 |
4039 | 1.45M | 1075567U, // VREV64q32 |
4040 | 1.45M | 1599855U, // VREV64q8 |
4041 | 1.45M | 12119390U, // VRHADDsv16i8 |
4042 | 1.45M | 11595102U, // VRHADDsv2i32 |
4043 | 1.45M | 11070814U, // VRHADDsv4i16 |
4044 | 1.45M | 11595102U, // VRHADDsv4i32 |
4045 | 1.45M | 11070814U, // VRHADDsv8i16 |
4046 | 1.45M | 12119390U, // VRHADDsv8i8 |
4047 | 1.45M | 13692254U, // VRHADDuv16i8 |
4048 | 1.45M | 13167966U, // VRHADDuv2i32 |
4049 | 1.45M | 12643678U, // VRHADDuv4i16 |
4050 | 1.45M | 13167966U, // VRHADDuv4i32 |
4051 | 1.45M | 12643678U, // VRHADDuv8i16 |
4052 | 1.45M | 13692254U, // VRHADDuv8i8 |
4053 | 1.45M | 875643626U, // VRINTAD |
4054 | 1.45M | 875644148U, // VRINTAH |
4055 | 1.45M | 875643275U, // VRINTANDf |
4056 | 1.45M | 875644148U, // VRINTANDh |
4057 | 1.45M | 875643275U, // VRINTANQf |
4058 | 1.45M | 875644148U, // VRINTANQh |
4059 | 1.45M | 875643275U, // VRINTAS |
4060 | 1.45M | 875643674U, // VRINTMD |
4061 | 1.45M | 875644229U, // VRINTMH |
4062 | 1.45M | 875643334U, // VRINTMNDf |
4063 | 1.45M | 875644229U, // VRINTMNDh |
4064 | 1.45M | 875643334U, // VRINTMNQf |
4065 | 1.45M | 875644229U, // VRINTMNQh |
4066 | 1.45M | 875643334U, // VRINTMS |
4067 | 1.45M | 875643686U, // VRINTND |
4068 | 1.45M | 875644241U, // VRINTNH |
4069 | 1.45M | 875643346U, // VRINTNNDf |
4070 | 1.45M | 875644241U, // VRINTNNDh |
4071 | 1.45M | 875643346U, // VRINTNNQf |
4072 | 1.45M | 875644241U, // VRINTNNQh |
4073 | 1.45M | 875643346U, // VRINTNS |
4074 | 1.45M | 875643698U, // VRINTPD |
4075 | 1.45M | 875644253U, // VRINTPH |
4076 | 1.45M | 875643358U, // VRINTPNDf |
4077 | 1.45M | 875644253U, // VRINTPNDh |
4078 | 1.45M | 875643358U, // VRINTPNQf |
4079 | 1.45M | 875644253U, // VRINTPNQh |
4080 | 1.45M | 875643358U, // VRINTPS |
4081 | 1.45M | 1147695608U, // VRINTRD |
4082 | 1.45M | 7369208U, // VRINTRH |
4083 | 1.45M | 7893496U, // VRINTRS |
4084 | 1.45M | 1147696582U, // VRINTXD |
4085 | 1.45M | 7370182U, // VRINTXH |
4086 | 1.45M | 875643406U, // VRINTXNDf |
4087 | 1.45M | 875644311U, // VRINTXNDh |
4088 | 1.45M | 875643406U, // VRINTXNQf |
4089 | 1.45M | 875644311U, // VRINTXNQh |
4090 | 1.45M | 7894470U, // VRINTXS |
4091 | 1.45M | 1147696632U, // VRINTZD |
4092 | 1.45M | 7370232U, // VRINTZH |
4093 | 1.45M | 875643418U, // VRINTZNDf |
4094 | 1.45M | 875644334U, // VRINTZNDh |
4095 | 1.45M | 875643418U, // VRINTZNQf |
4096 | 1.45M | 875644334U, // VRINTZNQh |
4097 | 1.45M | 7894520U, // VRINTZS |
4098 | 1.45M | 12119969U, // VRSHLsv16i8 |
4099 | 1.45M | 907603873U, // VRSHLsv1i64 |
4100 | 1.45M | 11595681U, // VRSHLsv2i32 |
4101 | 1.45M | 907603873U, // VRSHLsv2i64 |
4102 | 1.45M | 11071393U, // VRSHLsv4i16 |
4103 | 1.45M | 11595681U, // VRSHLsv4i32 |
4104 | 1.45M | 11071393U, // VRSHLsv8i16 |
4105 | 1.45M | 12119969U, // VRSHLsv8i8 |
4106 | 1.45M | 13692833U, // VRSHLuv16i8 |
4107 | 1.45M | 22605729U, // VRSHLuv1i64 |
4108 | 1.45M | 13168545U, // VRSHLuv2i32 |
4109 | 1.45M | 22605729U, // VRSHLuv2i64 |
4110 | 1.45M | 12644257U, // VRSHLuv4i16 |
4111 | 1.45M | 13168545U, // VRSHLuv4i32 |
4112 | 1.45M | 12644257U, // VRSHLuv8i16 |
4113 | 1.45M | 13692833U, // VRSHLuv8i8 |
4114 | 1.45M | 895545524U, // VRSHRNv2i32 |
4115 | 1.45M | 14217396U, // VRSHRNv4i16 |
4116 | 1.45M | 14741684U, // VRSHRNv8i8 |
4117 | 1.45M | 12120509U, // VRSHRsv16i8 |
4118 | 1.45M | 907604413U, // VRSHRsv1i64 |
4119 | 1.45M | 11596221U, // VRSHRsv2i32 |
4120 | 1.45M | 907604413U, // VRSHRsv2i64 |
4121 | 1.45M | 11071933U, // VRSHRsv4i16 |
4122 | 1.45M | 11596221U, // VRSHRsv4i32 |
4123 | 1.45M | 11071933U, // VRSHRsv8i16 |
4124 | 1.45M | 12120509U, // VRSHRsv8i8 |
4125 | 1.45M | 13693373U, // VRSHRuv16i8 |
4126 | 1.45M | 22606269U, // VRSHRuv1i64 |
4127 | 1.45M | 13169085U, // VRSHRuv2i32 |
4128 | 1.45M | 22606269U, // VRSHRuv2i64 |
4129 | 1.45M | 12644797U, // VRSHRuv4i16 |
4130 | 1.45M | 13169085U, // VRSHRuv4i32 |
4131 | 1.45M | 12644797U, // VRSHRuv8i16 |
4132 | 1.45M | 13693373U, // VRSHRuv8i8 |
4133 | 1.45M | 13135332U, // VRSQRTEd |
4134 | 1.45M | 7892452U, // VRSQRTEfd |
4135 | 1.45M | 7892452U, // VRSQRTEfq |
4136 | 1.45M | 7368164U, // VRSQRTEhd |
4137 | 1.45M | 7368164U, // VRSQRTEhq |
4138 | 1.45M | 13135332U, // VRSQRTEq |
4139 | 1.45M | 7926376U, // VRSQRTSfd |
4140 | 1.45M | 7926376U, // VRSQRTSfq |
4141 | 1.45M | 7402088U, // VRSQRTShd |
4142 | 1.45M | 7402088U, // VRSQRTShq |
4143 | 1.45M | 12102490U, // VRSRAsv16i8 |
4144 | 1.45M | 840477530U, // VRSRAsv1i64 |
4145 | 1.45M | 11578202U, // VRSRAsv2i32 |
4146 | 1.45M | 840477530U, // VRSRAsv2i64 |
4147 | 1.45M | 11053914U, // VRSRAsv4i16 |
4148 | 1.45M | 11578202U, // VRSRAsv4i32 |
4149 | 1.45M | 11053914U, // VRSRAsv8i16 |
4150 | 1.45M | 12102490U, // VRSRAsv8i8 |
4151 | 1.45M | 13675354U, // VRSRAuv16i8 |
4152 | 1.45M | 22588250U, // VRSRAuv1i64 |
4153 | 1.45M | 13151066U, // VRSRAuv2i32 |
4154 | 1.45M | 22588250U, // VRSRAuv2i64 |
4155 | 1.45M | 12626778U, // VRSRAuv4i16 |
4156 | 1.45M | 13151066U, // VRSRAuv4i32 |
4157 | 1.45M | 12626778U, // VRSRAuv8i16 |
4158 | 1.45M | 13675354U, // VRSRAuv8i8 |
4159 | 1.45M | 895545464U, // VRSUBHNv2i32 |
4160 | 1.45M | 14217336U, // VRSUBHNv4i16 |
4161 | 1.45M | 14741624U, // VRSUBHNv8i8 |
4162 | 1.45M | 2821312605U, // VSCCLRMD |
4163 | 1.45M | 2821312605U, // VSCCLRMS |
4164 | 1.45M | 808543916U, // VSDOTD |
4165 | 1.45M | 808543916U, // VSDOTDI |
4166 | 1.45M | 808543916U, // VSDOTQ |
4167 | 1.45M | 808543916U, // VSDOTQI |
4168 | 1.45M | 875643710U, // VSELEQD |
4169 | 1.45M | 875644265U, // VSELEQH |
4170 | 1.45M | 875643370U, // VSELEQS |
4171 | 1.45M | 875643638U, // VSELGED |
4172 | 1.45M | 875644171U, // VSELGEH |
4173 | 1.45M | 875643298U, // VSELGES |
4174 | 1.45M | 875643734U, // VSELGTD |
4175 | 1.45M | 875644299U, // VSELGTH |
4176 | 1.45M | 875643394U, // VSELGTS |
4177 | 1.45M | 875643722U, // VSELVSD |
4178 | 1.45M | 875644287U, // VSELVSH |
4179 | 1.45M | 875643382U, // VSELVSS |
4180 | 1.45M | 570442U, // VSETLNi16 |
4181 | 1.45M | 1094730U, // VSETLNi32 |
4182 | 1.45M | 1619018U, // VSETLNi8 |
4183 | 1.45M | 14741456U, // VSHLLi16 |
4184 | 1.45M | 14217168U, // VSHLLi32 |
4185 | 1.45M | 15265744U, // VSHLLi8 |
4186 | 1.45M | 11595728U, // VSHLLsv2i64 |
4187 | 1.45M | 11071440U, // VSHLLsv4i32 |
4188 | 1.45M | 12120016U, // VSHLLsv8i16 |
4189 | 1.45M | 13168592U, // VSHLLuv2i64 |
4190 | 1.45M | 12644304U, // VSHLLuv4i32 |
4191 | 1.45M | 13692880U, // VSHLLuv8i16 |
4192 | 1.45M | 15265703U, // VSHLiv16i8 |
4193 | 1.45M | 895545255U, // VSHLiv1i64 |
4194 | 1.45M | 14217127U, // VSHLiv2i32 |
4195 | 1.45M | 895545255U, // VSHLiv2i64 |
4196 | 1.45M | 14741415U, // VSHLiv4i16 |
4197 | 1.45M | 14217127U, // VSHLiv4i32 |
4198 | 1.45M | 14741415U, // VSHLiv8i16 |
4199 | 1.45M | 15265703U, // VSHLiv8i8 |
4200 | 1.45M | 12119975U, // VSHLsv16i8 |
4201 | 1.45M | 907603879U, // VSHLsv1i64 |
4202 | 1.45M | 11595687U, // VSHLsv2i32 |
4203 | 1.45M | 907603879U, // VSHLsv2i64 |
4204 | 1.45M | 11071399U, // VSHLsv4i16 |
4205 | 1.45M | 11595687U, // VSHLsv4i32 |
4206 | 1.45M | 11071399U, // VSHLsv8i16 |
4207 | 1.45M | 12119975U, // VSHLsv8i8 |
4208 | 1.45M | 13692839U, // VSHLuv16i8 |
4209 | 1.45M | 22605735U, // VSHLuv1i64 |
4210 | 1.45M | 13168551U, // VSHLuv2i32 |
4211 | 1.45M | 22605735U, // VSHLuv2i64 |
4212 | 1.45M | 12644263U, // VSHLuv4i16 |
4213 | 1.45M | 13168551U, // VSHLuv4i32 |
4214 | 1.45M | 12644263U, // VSHLuv8i16 |
4215 | 1.45M | 13692839U, // VSHLuv8i8 |
4216 | 1.45M | 895545531U, // VSHRNv2i32 |
4217 | 1.45M | 14217403U, // VSHRNv4i16 |
4218 | 1.45M | 14741691U, // VSHRNv8i8 |
4219 | 1.45M | 12120515U, // VSHRsv16i8 |
4220 | 1.45M | 907604419U, // VSHRsv1i64 |
4221 | 1.45M | 11596227U, // VSHRsv2i32 |
4222 | 1.45M | 907604419U, // VSHRsv2i64 |
4223 | 1.45M | 11071939U, // VSHRsv4i16 |
4224 | 1.45M | 11596227U, // VSHRsv4i32 |
4225 | 1.45M | 11071939U, // VSHRsv8i16 |
4226 | 1.45M | 12120515U, // VSHRsv8i8 |
4227 | 1.45M | 13693379U, // VSHRuv16i8 |
4228 | 1.45M | 22606275U, // VSHRuv1i64 |
4229 | 1.45M | 13169091U, // VSHRuv2i32 |
4230 | 1.45M | 22606275U, // VSHRuv2i64 |
4231 | 1.45M | 12644803U, // VSHRuv4i16 |
4232 | 1.45M | 13169091U, // VSHRuv4i32 |
4233 | 1.45M | 12644803U, // VSHRuv8i16 |
4234 | 1.45M | 13693379U, // VSHRuv8i8 |
4235 | 1.45M | 35713960U, // VSHTOD |
4236 | 1.45M | 1157690280U, // VSHTOH |
4237 | 1.45M | 36238248U, // VSHTOS |
4238 | 1.45M | 1110471592U, // VSITOD |
4239 | 1.45M | 1110995880U, // VSITOH |
4240 | 1.45M | 1092121512U, // VSITOS |
4241 | 1.45M | 1617672U, // VSLIv16i8 |
4242 | 1.45M | 15773448U, // VSLIv1i64 |
4243 | 1.45M | 1093384U, // VSLIv2i32 |
4244 | 1.45M | 15773448U, // VSLIv2i64 |
4245 | 1.45M | 569096U, // VSLIv4i16 |
4246 | 1.45M | 1093384U, // VSLIv4i32 |
4247 | 1.45M | 569096U, // VSLIv8i16 |
4248 | 1.45M | 1617672U, // VSLIv8i8 |
4249 | 1.45M | 1177613224U, // VSLTOD |
4250 | 1.45M | 1178137512U, // VSLTOH |
4251 | 1.45M | 1159263144U, // VSLTOS |
4252 | 1.45M | 808543894U, // VSMMLA |
4253 | 1.45M | 1147695975U, // VSQRTD |
4254 | 1.45M | 7369575U, // VSQRTH |
4255 | 1.45M | 7893863U, // VSQRTS |
4256 | 1.45M | 12102496U, // VSRAsv16i8 |
4257 | 1.45M | 840477536U, // VSRAsv1i64 |
4258 | 1.45M | 11578208U, // VSRAsv2i32 |
4259 | 1.45M | 840477536U, // VSRAsv2i64 |
4260 | 1.45M | 11053920U, // VSRAsv4i16 |
4261 | 1.45M | 11578208U, // VSRAsv4i32 |
4262 | 1.45M | 11053920U, // VSRAsv8i16 |
4263 | 1.45M | 12102496U, // VSRAsv8i8 |
4264 | 1.45M | 13675360U, // VSRAuv16i8 |
4265 | 1.45M | 22588256U, // VSRAuv1i64 |
4266 | 1.45M | 13151072U, // VSRAuv2i32 |
4267 | 1.45M | 22588256U, // VSRAuv2i64 |
4268 | 1.45M | 12626784U, // VSRAuv4i16 |
4269 | 1.45M | 13151072U, // VSRAuv4i32 |
4270 | 1.45M | 12626784U, // VSRAuv8i16 |
4271 | 1.45M | 13675360U, // VSRAuv8i8 |
4272 | 1.45M | 1617677U, // VSRIv16i8 |
4273 | 1.45M | 15773453U, // VSRIv1i64 |
4274 | 1.45M | 1093389U, // VSRIv2i32 |
4275 | 1.45M | 15773453U, // VSRIv2i64 |
4276 | 1.45M | 569101U, // VSRIv4i16 |
4277 | 1.45M | 1093389U, // VSRIv4i32 |
4278 | 1.45M | 569101U, // VSRIv8i16 |
4279 | 1.45M | 1617677U, // VSRIv8i8 |
4280 | 1.45M | 833661199U, // VST1LNd16 |
4281 | 1.45M | 2914126095U, // VST1LNd16_UPD |
4282 | 1.45M | 834185487U, // VST1LNd32 |
4283 | 1.45M | 2914650383U, // VST1LNd32_UPD |
4284 | 1.45M | 834709775U, // VST1LNd8 |
4285 | 1.45M | 2915174671U, // VST1LNd8_UPD |
4286 | 1.45M | 0U, // VST1LNq16Pseudo |
4287 | 1.45M | 0U, // VST1LNq16Pseudo_UPD |
4288 | 1.45M | 0U, // VST1LNq32Pseudo |
4289 | 1.45M | 0U, // VST1LNq32Pseudo_UPD |
4290 | 1.45M | 0U, // VST1LNq8Pseudo |
4291 | 1.45M | 0U, // VST1LNq8Pseudo_UPD |
4292 | 1.45M | 2953373967U, // VST1d16 |
4293 | 1.45M | 3020482831U, // VST1d16Q |
4294 | 1.45M | 0U, // VST1d16QPseudo |
4295 | 1.45M | 0U, // VST1d16QPseudoWB_fixed |
4296 | 1.45M | 0U, // VST1d16QPseudoWB_register |
4297 | 1.45M | 3087575311U, // VST1d16Qwb_fixed |
4298 | 1.45M | 3154692367U, // VST1d16Qwb_register |
4299 | 1.45M | 3221809423U, // VST1d16T |
4300 | 1.45M | 0U, // VST1d16TPseudo |
4301 | 1.45M | 0U, // VST1d16TPseudoWB_fixed |
4302 | 1.45M | 0U, // VST1d16TPseudoWB_register |
4303 | 1.45M | 3288901903U, // VST1d16Twb_fixed |
4304 | 1.45M | 3356018959U, // VST1d16Twb_register |
4305 | 1.45M | 3423119631U, // VST1d16wb_fixed |
4306 | 1.45M | 3490236687U, // VST1d16wb_register |
4307 | 1.45M | 2953898255U, // VST1d32 |
4308 | 1.45M | 3021007119U, // VST1d32Q |
4309 | 1.45M | 0U, // VST1d32QPseudo |
4310 | 1.45M | 0U, // VST1d32QPseudoWB_fixed |
4311 | 1.45M | 0U, // VST1d32QPseudoWB_register |
4312 | 1.45M | 3088099599U, // VST1d32Qwb_fixed |
4313 | 1.45M | 3155216655U, // VST1d32Qwb_register |
4314 | 1.45M | 3222333711U, // VST1d32T |
4315 | 1.45M | 0U, // VST1d32TPseudo |
4316 | 1.45M | 0U, // VST1d32TPseudoWB_fixed |
4317 | 1.45M | 0U, // VST1d32TPseudoWB_register |
4318 | 1.45M | 3289426191U, // VST1d32Twb_fixed |
4319 | 1.45M | 3356543247U, // VST1d32Twb_register |
4320 | 1.45M | 3423643919U, // VST1d32wb_fixed |
4321 | 1.45M | 3490760975U, // VST1d32wb_register |
4322 | 1.45M | 2968578319U, // VST1d64 |
4323 | 1.45M | 3035687183U, // VST1d64Q |
4324 | 1.45M | 0U, // VST1d64QPseudo |
4325 | 1.45M | 0U, // VST1d64QPseudoWB_fixed |
4326 | 1.45M | 0U, // VST1d64QPseudoWB_register |
4327 | 1.45M | 3102779663U, // VST1d64Qwb_fixed |
4328 | 1.45M | 3169896719U, // VST1d64Qwb_register |
4329 | 1.45M | 3237013775U, // VST1d64T |
4330 | 1.45M | 0U, // VST1d64TPseudo |
4331 | 1.45M | 0U, // VST1d64TPseudoWB_fixed |
4332 | 1.45M | 0U, // VST1d64TPseudoWB_register |
4333 | 1.45M | 3304106255U, // VST1d64Twb_fixed |
4334 | 1.45M | 3371223311U, // VST1d64Twb_register |
4335 | 1.45M | 3438323983U, // VST1d64wb_fixed |
4336 | 1.45M | 3505441039U, // VST1d64wb_register |
4337 | 1.45M | 2954422543U, // VST1d8 |
4338 | 1.45M | 3021531407U, // VST1d8Q |
4339 | 1.45M | 0U, // VST1d8QPseudo |
4340 | 1.45M | 0U, // VST1d8QPseudoWB_fixed |
4341 | 1.45M | 0U, // VST1d8QPseudoWB_register |
4342 | 1.45M | 3088623887U, // VST1d8Qwb_fixed |
4343 | 1.45M | 3155740943U, // VST1d8Qwb_register |
4344 | 1.45M | 3222857999U, // VST1d8T |
4345 | 1.45M | 0U, // VST1d8TPseudo |
4346 | 1.45M | 0U, // VST1d8TPseudoWB_fixed |
4347 | 1.45M | 0U, // VST1d8TPseudoWB_register |
4348 | 1.45M | 3289950479U, // VST1d8Twb_fixed |
4349 | 1.45M | 3357067535U, // VST1d8Twb_register |
4350 | 1.45M | 3424168207U, // VST1d8wb_fixed |
4351 | 1.45M | 3491285263U, // VST1d8wb_register |
4352 | 1.45M | 3557353743U, // VST1q16 |
4353 | 1.45M | 0U, // VST1q16HighQPseudo |
4354 | 1.45M | 0U, // VST1q16HighQPseudo_UPD |
4355 | 1.45M | 0U, // VST1q16HighTPseudo |
4356 | 1.45M | 0U, // VST1q16HighTPseudo_UPD |
4357 | 1.45M | 0U, // VST1q16LowQPseudo_UPD |
4358 | 1.45M | 0U, // VST1q16LowTPseudo_UPD |
4359 | 1.45M | 3624446223U, // VST1q16wb_fixed |
4360 | 1.45M | 3691563279U, // VST1q16wb_register |
4361 | 1.45M | 3557878031U, // VST1q32 |
4362 | 1.45M | 0U, // VST1q32HighQPseudo |
4363 | 1.45M | 0U, // VST1q32HighQPseudo_UPD |
4364 | 1.45M | 0U, // VST1q32HighTPseudo |
4365 | 1.45M | 0U, // VST1q32HighTPseudo_UPD |
4366 | 1.45M | 0U, // VST1q32LowQPseudo_UPD |
4367 | 1.45M | 0U, // VST1q32LowTPseudo_UPD |
4368 | 1.45M | 3624970511U, // VST1q32wb_fixed |
4369 | 1.45M | 3692087567U, // VST1q32wb_register |
4370 | 1.45M | 3572558095U, // VST1q64 |
4371 | 1.45M | 0U, // VST1q64HighQPseudo |
4372 | 1.45M | 0U, // VST1q64HighQPseudo_UPD |
4373 | 1.45M | 0U, // VST1q64HighTPseudo |
4374 | 1.45M | 0U, // VST1q64HighTPseudo_UPD |
4375 | 1.45M | 0U, // VST1q64LowQPseudo_UPD |
4376 | 1.45M | 0U, // VST1q64LowTPseudo_UPD |
4377 | 1.45M | 3639650575U, // VST1q64wb_fixed |
4378 | 1.45M | 3706767631U, // VST1q64wb_register |
4379 | 1.45M | 3558402319U, // VST1q8 |
4380 | 1.45M | 0U, // VST1q8HighQPseudo |
4381 | 1.45M | 0U, // VST1q8HighQPseudo_UPD |
4382 | 1.45M | 0U, // VST1q8HighTPseudo |
4383 | 1.45M | 0U, // VST1q8HighTPseudo_UPD |
4384 | 1.45M | 0U, // VST1q8LowQPseudo_UPD |
4385 | 1.45M | 0U, // VST1q8LowTPseudo_UPD |
4386 | 1.45M | 3625494799U, // VST1q8wb_fixed |
4387 | 1.45M | 3692611855U, // VST1q8wb_register |
4388 | 1.45M | 833669456U, // VST2LNd16 |
4389 | 1.45M | 0U, // VST2LNd16Pseudo |
4390 | 1.45M | 0U, // VST2LNd16Pseudo_UPD |
4391 | 1.45M | 2914298192U, // VST2LNd16_UPD |
4392 | 1.45M | 834193744U, // VST2LNd32 |
4393 | 1.45M | 0U, // VST2LNd32Pseudo |
4394 | 1.45M | 0U, // VST2LNd32Pseudo_UPD |
4395 | 1.45M | 2914822480U, // VST2LNd32_UPD |
4396 | 1.45M | 834718032U, // VST2LNd8 |
4397 | 1.45M | 0U, // VST2LNd8Pseudo |
4398 | 1.45M | 0U, // VST2LNd8Pseudo_UPD |
4399 | 1.45M | 2915346768U, // VST2LNd8_UPD |
4400 | 1.45M | 833669456U, // VST2LNq16 |
4401 | 1.45M | 0U, // VST2LNq16Pseudo |
4402 | 1.45M | 0U, // VST2LNq16Pseudo_UPD |
4403 | 1.45M | 2914298192U, // VST2LNq16_UPD |
4404 | 1.45M | 834193744U, // VST2LNq32 |
4405 | 1.45M | 0U, // VST2LNq32Pseudo |
4406 | 1.45M | 0U, // VST2LNq32Pseudo_UPD |
4407 | 1.45M | 2914822480U, // VST2LNq32_UPD |
4408 | 1.45M | 3758680400U, // VST2b16 |
4409 | 1.45M | 3825772880U, // VST2b16wb_fixed |
4410 | 1.45M | 3892889936U, // VST2b16wb_register |
4411 | 1.45M | 3759204688U, // VST2b32 |
4412 | 1.45M | 3826297168U, // VST2b32wb_fixed |
4413 | 1.45M | 3893414224U, // VST2b32wb_register |
4414 | 1.45M | 3759728976U, // VST2b8 |
4415 | 1.45M | 3826821456U, // VST2b8wb_fixed |
4416 | 1.45M | 3893938512U, // VST2b8wb_register |
4417 | 1.45M | 3557353808U, // VST2d16 |
4418 | 1.45M | 3624446288U, // VST2d16wb_fixed |
4419 | 1.45M | 3691563344U, // VST2d16wb_register |
4420 | 1.45M | 3557878096U, // VST2d32 |
4421 | 1.45M | 3624970576U, // VST2d32wb_fixed |
4422 | 1.45M | 3692087632U, // VST2d32wb_register |
4423 | 1.45M | 3558402384U, // VST2d8 |
4424 | 1.45M | 3625494864U, // VST2d8wb_fixed |
4425 | 1.45M | 3692611920U, // VST2d8wb_register |
4426 | 1.45M | 3020482896U, // VST2q16 |
4427 | 1.45M | 0U, // VST2q16Pseudo |
4428 | 1.45M | 0U, // VST2q16PseudoWB_fixed |
4429 | 1.45M | 0U, // VST2q16PseudoWB_register |
4430 | 1.45M | 3087575376U, // VST2q16wb_fixed |
4431 | 1.45M | 3154692432U, // VST2q16wb_register |
4432 | 1.45M | 3021007184U, // VST2q32 |
4433 | 1.45M | 0U, // VST2q32Pseudo |
4434 | 1.45M | 0U, // VST2q32PseudoWB_fixed |
4435 | 1.45M | 0U, // VST2q32PseudoWB_register |
4436 | 1.45M | 3088099664U, // VST2q32wb_fixed |
4437 | 1.45M | 3155216720U, // VST2q32wb_register |
4438 | 1.45M | 3021531472U, // VST2q8 |
4439 | 1.45M | 0U, // VST2q8Pseudo |
4440 | 1.45M | 0U, // VST2q8PseudoWB_fixed |
4441 | 1.45M | 0U, // VST2q8PseudoWB_register |
4442 | 1.45M | 3088623952U, // VST2q8wb_fixed |
4443 | 1.45M | 3155741008U, // VST2q8wb_register |
4444 | 1.45M | 833751397U, // VST3LNd16 |
4445 | 1.45M | 0U, // VST3LNd16Pseudo |
4446 | 1.45M | 0U, // VST3LNd16Pseudo_UPD |
4447 | 1.45M | 2914322789U, // VST3LNd16_UPD |
4448 | 1.45M | 834275685U, // VST3LNd32 |
4449 | 1.45M | 0U, // VST3LNd32Pseudo |
4450 | 1.45M | 0U, // VST3LNd32Pseudo_UPD |
4451 | 1.45M | 2914847077U, // VST3LNd32_UPD |
4452 | 1.45M | 834799973U, // VST3LNd8 |
4453 | 1.45M | 0U, // VST3LNd8Pseudo |
4454 | 1.45M | 0U, // VST3LNd8Pseudo_UPD |
4455 | 1.45M | 2915371365U, // VST3LNd8_UPD |
4456 | 1.45M | 833751397U, // VST3LNq16 |
4457 | 1.45M | 0U, // VST3LNq16Pseudo |
4458 | 1.45M | 0U, // VST3LNq16Pseudo_UPD |
4459 | 1.45M | 2914322789U, // VST3LNq16_UPD |
4460 | 1.45M | 834275685U, // VST3LNq32 |
4461 | 1.45M | 0U, // VST3LNq32Pseudo |
4462 | 1.45M | 0U, // VST3LNq32Pseudo_UPD |
4463 | 1.45M | 2914847077U, // VST3LNq32_UPD |
4464 | 1.45M | 833669477U, // VST3d16 |
4465 | 1.45M | 0U, // VST3d16Pseudo |
4466 | 1.45M | 0U, // VST3d16Pseudo_UPD |
4467 | 1.45M | 2914298213U, // VST3d16_UPD |
4468 | 1.45M | 834193765U, // VST3d32 |
4469 | 1.45M | 0U, // VST3d32Pseudo |
4470 | 1.45M | 0U, // VST3d32Pseudo_UPD |
4471 | 1.45M | 2914822501U, // VST3d32_UPD |
4472 | 1.45M | 834718053U, // VST3d8 |
4473 | 1.45M | 0U, // VST3d8Pseudo |
4474 | 1.45M | 0U, // VST3d8Pseudo_UPD |
4475 | 1.45M | 2915346789U, // VST3d8_UPD |
4476 | 1.45M | 833669477U, // VST3q16 |
4477 | 1.45M | 0U, // VST3q16Pseudo_UPD |
4478 | 1.45M | 2914298213U, // VST3q16_UPD |
4479 | 1.45M | 0U, // VST3q16oddPseudo |
4480 | 1.45M | 0U, // VST3q16oddPseudo_UPD |
4481 | 1.45M | 834193765U, // VST3q32 |
4482 | 1.45M | 0U, // VST3q32Pseudo_UPD |
4483 | 1.45M | 2914822501U, // VST3q32_UPD |
4484 | 1.45M | 0U, // VST3q32oddPseudo |
4485 | 1.45M | 0U, // VST3q32oddPseudo_UPD |
4486 | 1.45M | 834718053U, // VST3q8 |
4487 | 1.45M | 0U, // VST3q8Pseudo_UPD |
4488 | 1.45M | 2915346789U, // VST3q8_UPD |
4489 | 1.45M | 0U, // VST3q8oddPseudo |
4490 | 1.45M | 0U, // VST3q8oddPseudo_UPD |
4491 | 1.45M | 833923451U, // VST4LNd16 |
4492 | 1.45M | 0U, // VST4LNd16Pseudo |
4493 | 1.45M | 0U, // VST4LNd16Pseudo_UPD |
4494 | 1.45M | 2914306427U, // VST4LNd16_UPD |
4495 | 1.45M | 834447739U, // VST4LNd32 |
4496 | 1.45M | 0U, // VST4LNd32Pseudo |
4497 | 1.45M | 0U, // VST4LNd32Pseudo_UPD |
4498 | 1.45M | 2914830715U, // VST4LNd32_UPD |
4499 | 1.45M | 834972027U, // VST4LNd8 |
4500 | 1.45M | 0U, // VST4LNd8Pseudo |
4501 | 1.45M | 0U, // VST4LNd8Pseudo_UPD |
4502 | 1.45M | 2915355003U, // VST4LNd8_UPD |
4503 | 1.45M | 833923451U, // VST4LNq16 |
4504 | 1.45M | 0U, // VST4LNq16Pseudo |
4505 | 1.45M | 0U, // VST4LNq16Pseudo_UPD |
4506 | 1.45M | 2914306427U, // VST4LNq16_UPD |
4507 | 1.45M | 834447739U, // VST4LNq32 |
4508 | 1.45M | 0U, // VST4LNq32Pseudo |
4509 | 1.45M | 0U, // VST4LNq32Pseudo_UPD |
4510 | 1.45M | 2914830715U, // VST4LNq32_UPD |
4511 | 1.45M | 833751419U, // VST4d16 |
4512 | 1.45M | 0U, // VST4d16Pseudo |
4513 | 1.45M | 0U, // VST4d16Pseudo_UPD |
4514 | 1.45M | 2914322811U, // VST4d16_UPD |
4515 | 1.45M | 834275707U, // VST4d32 |
4516 | 1.45M | 0U, // VST4d32Pseudo |
4517 | 1.45M | 0U, // VST4d32Pseudo_UPD |
4518 | 1.45M | 2914847099U, // VST4d32_UPD |
4519 | 1.45M | 834799995U, // VST4d8 |
4520 | 1.45M | 0U, // VST4d8Pseudo |
4521 | 1.45M | 0U, // VST4d8Pseudo_UPD |
4522 | 1.45M | 2915371387U, // VST4d8_UPD |
4523 | 1.45M | 833751419U, // VST4q16 |
4524 | 1.45M | 0U, // VST4q16Pseudo_UPD |
4525 | 1.45M | 2914322811U, // VST4q16_UPD |
4526 | 1.45M | 0U, // VST4q16oddPseudo |
4527 | 1.45M | 0U, // VST4q16oddPseudo_UPD |
4528 | 1.45M | 834275707U, // VST4q32 |
4529 | 1.45M | 0U, // VST4q32Pseudo_UPD |
4530 | 1.45M | 2914847099U, // VST4q32_UPD |
4531 | 1.45M | 0U, // VST4q32oddPseudo |
4532 | 1.45M | 0U, // VST4q32oddPseudo_UPD |
4533 | 1.45M | 834799995U, // VST4q8 |
4534 | 1.45M | 0U, // VST4q8Pseudo_UPD |
4535 | 1.45M | 2915371387U, // VST4q8_UPD |
4536 | 1.45M | 0U, // VST4q8oddPseudo |
4537 | 1.45M | 0U, // VST4q8oddPseudo_UPD |
4538 | 1.45M | 875064297U, // VSTMDDB_UPD |
4539 | 1.45M | 2730773U, // VSTMDIA |
4540 | 1.45M | 875064085U, // VSTMDIA_UPD |
4541 | 1.45M | 0U, // VSTMQIA |
4542 | 1.45M | 875064297U, // VSTMSDB_UPD |
4543 | 1.45M | 2730773U, // VSTMSIA |
4544 | 1.45M | 875064085U, // VSTMSIA_UPD |
4545 | 1.45M | 2683391U, // VSTRD |
4546 | 1.45M | 586239U, // VSTRH |
4547 | 1.45M | 2683391U, // VSTRS |
4548 | 1.45M | 2580050431U, // VSTR_FPCXTNS_off |
4549 | 1.45M | 701035007U, // VSTR_FPCXTNS_post |
4550 | 1.45M | 2647192063U, // VSTR_FPCXTNS_pre |
4551 | 1.45M | 2580574719U, // VSTR_FPCXTS_off |
4552 | 1.45M | 701559295U, // VSTR_FPCXTS_post |
4553 | 1.45M | 2647716351U, // VSTR_FPCXTS_pre |
4554 | 1.45M | 2581099007U, // VSTR_FPSCR_NZCVQC_off |
4555 | 1.45M | 702083583U, // VSTR_FPSCR_NZCVQC_post |
4556 | 1.45M | 2648240639U, // VSTR_FPSCR_NZCVQC_pre |
4557 | 1.45M | 2581623295U, // VSTR_FPSCR_off |
4558 | 1.45M | 702607871U, // VSTR_FPSCR_post |
4559 | 1.45M | 2648764927U, // VSTR_FPSCR_pre |
4560 | 1.45M | 2716398079U, // VSTR_P0_off |
4561 | 1.45M | 1642639871U, // VSTR_P0_post |
4562 | 1.45M | 2783490559U, // VSTR_P0_pre |
4563 | 1.45M | 2582671871U, // VSTR_VPR_off |
4564 | 1.45M | 703656447U, // VSTR_VPR_post |
4565 | 1.45M | 2649813503U, // VSTR_VPR_pre |
4566 | 1.45M | 1147727061U, // VSUBD |
4567 | 1.45M | 7400661U, // VSUBH |
4568 | 1.45M | 895545472U, // VSUBHNv2i32 |
4569 | 1.45M | 14217344U, // VSUBHNv4i16 |
4570 | 1.45M | 14741632U, // VSUBHNv8i8 |
4571 | 1.45M | 11595604U, // VSUBLsv2i64 |
4572 | 1.45M | 11071316U, // VSUBLsv4i32 |
4573 | 1.45M | 12119892U, // VSUBLsv8i16 |
4574 | 1.45M | 13168468U, // VSUBLuv2i64 |
4575 | 1.45M | 12644180U, // VSUBLuv4i32 |
4576 | 1.45M | 13692756U, // VSUBLuv8i16 |
4577 | 1.45M | 7924949U, // VSUBS |
4578 | 1.45M | 11596885U, // VSUBWsv2i64 |
4579 | 1.45M | 11072597U, // VSUBWsv4i32 |
4580 | 1.45M | 12121173U, // VSUBWsv8i16 |
4581 | 1.45M | 13169749U, // VSUBWuv2i64 |
4582 | 1.45M | 12645461U, // VSUBWuv4i32 |
4583 | 1.45M | 13694037U, // VSUBWuv8i16 |
4584 | 1.45M | 7924949U, // VSUBfd |
4585 | 1.45M | 7924949U, // VSUBfq |
4586 | 1.45M | 7400661U, // VSUBhd |
4587 | 1.45M | 7400661U, // VSUBhq |
4588 | 1.45M | 15264981U, // VSUBv16i8 |
4589 | 1.45M | 895544533U, // VSUBv1i64 |
4590 | 1.45M | 14216405U, // VSUBv2i32 |
4591 | 1.45M | 895544533U, // VSUBv2i64 |
4592 | 1.45M | 14740693U, // VSUBv4i16 |
4593 | 1.45M | 14216405U, // VSUBv4i32 |
4594 | 1.45M | 14740693U, // VSUBv8i16 |
4595 | 1.45M | 15264981U, // VSUBv8i8 |
4596 | 1.45M | 808543937U, // VSUDOTDI |
4597 | 1.45M | 808543937U, // VSUDOTQI |
4598 | 1.45M | 2666883U, // VSWPd |
4599 | 1.45M | 2666883U, // VSWPq |
4600 | 1.45M | 1634127U, // VTBL1 |
4601 | 1.45M | 1634127U, // VTBL2 |
4602 | 1.45M | 1634127U, // VTBL3 |
4603 | 1.45M | 0U, // VTBL3Pseudo |
4604 | 1.45M | 1634127U, // VTBL4 |
4605 | 1.45M | 0U, // VTBL4Pseudo |
4606 | 1.45M | 1619202U, // VTBX1 |
4607 | 1.45M | 1619202U, // VTBX2 |
4608 | 1.45M | 1619202U, // VTBX3 |
4609 | 1.45M | 0U, // VTBX3Pseudo |
4610 | 1.45M | 1619202U, // VTBX4 |
4611 | 1.45M | 0U, // VTBX4Pseudo |
4612 | 1.45M | 37811112U, // VTOSHD |
4613 | 1.45M | 1160311720U, // VTOSHH |
4614 | 1.45M | 38335400U, // VTOSHS |
4615 | 1.45M | 1101558276U, // VTOSIRD |
4616 | 1.45M | 1112568324U, // VTOSIRH |
4617 | 1.45M | 1093693956U, // VTOSIRS |
4618 | 1.45M | 1101558696U, // VTOSIZD |
4619 | 1.45M | 1112568744U, // VTOSIZH |
4620 | 1.45M | 1093694376U, // VTOSIZS |
4621 | 1.45M | 1168700328U, // VTOSLD |
4622 | 1.45M | 1179710376U, // VTOSLH |
4623 | 1.45M | 1160836008U, // VTOSLS |
4624 | 1.45M | 39383976U, // VTOUHD |
4625 | 1.45M | 1161360296U, // VTOUHH |
4626 | 1.45M | 39908264U, // VTOUHS |
4627 | 1.45M | 1114141188U, // VTOUIRD |
4628 | 1.45M | 1114665476U, // VTOUIRH |
4629 | 1.45M | 1094742532U, // VTOUIRS |
4630 | 1.45M | 1114141608U, // VTOUIZD |
4631 | 1.45M | 1114665896U, // VTOUIZH |
4632 | 1.45M | 1094742952U, // VTOUIZS |
4633 | 1.45M | 1181283240U, // VTOULD |
4634 | 1.45M | 1181807528U, // VTOULH |
4635 | 1.45M | 1161884584U, // VTOULS |
4636 | 1.45M | 569542U, // VTRNd16 |
4637 | 1.45M | 1093830U, // VTRNd32 |
4638 | 1.45M | 1618118U, // VTRNd8 |
4639 | 1.45M | 569542U, // VTRNq16 |
4640 | 1.45M | 1093830U, // VTRNq32 |
4641 | 1.45M | 1618118U, // VTRNq8 |
4642 | 1.45M | 1635191U, // VTSTv16i8 |
4643 | 1.45M | 1110903U, // VTSTv2i32 |
4644 | 1.45M | 586615U, // VTSTv4i16 |
4645 | 1.45M | 1110903U, // VTSTv4i32 |
4646 | 1.45M | 586615U, // VTSTv8i16 |
4647 | 1.45M | 1635191U, // VTSTv8i8 |
4648 | 1.45M | 808543948U, // VUDOTD |
4649 | 1.45M | 808543948U, // VUDOTDI |
4650 | 1.45M | 808543948U, // VUDOTQ |
4651 | 1.45M | 808543948U, // VUDOTQI |
4652 | 1.45M | 41481128U, // VUHTOD |
4653 | 1.45M | 1158214568U, // VUHTOH |
4654 | 1.45M | 42005416U, // VUHTOS |
4655 | 1.45M | 1116238760U, // VUITOD |
4656 | 1.45M | 1116763048U, // VUITOH |
4657 | 1.45M | 1092645800U, // VUITOS |
4658 | 1.45M | 1183380392U, // VULTOD |
4659 | 1.45M | 1183904680U, // VULTOH |
4660 | 1.45M | 1159787432U, // VULTOS |
4661 | 1.45M | 808543926U, // VUMMLA |
4662 | 1.45M | 808543905U, // VUSDOTD |
4663 | 1.45M | 808543905U, // VUSDOTDI |
4664 | 1.45M | 808543905U, // VUSDOTQ |
4665 | 1.45M | 808543905U, // VUSDOTQI |
4666 | 1.45M | 808543882U, // VUSMMLA |
4667 | 1.45M | 569736U, // VUZPd16 |
4668 | 1.45M | 1618312U, // VUZPd8 |
4669 | 1.45M | 569736U, // VUZPq16 |
4670 | 1.45M | 1094024U, // VUZPq32 |
4671 | 1.45M | 1618312U, // VUZPq8 |
4672 | 1.45M | 569612U, // VZIPd16 |
4673 | 1.45M | 1618188U, // VZIPd8 |
4674 | 1.45M | 569612U, // VZIPq16 |
4675 | 1.45M | 1093900U, // VZIPq32 |
4676 | 1.45M | 1618188U, // VZIPq8 |
4677 | 1.45M | 2730724U, // sysLDMDA |
4678 | 1.45M | 875064036U, // sysLDMDA_UPD |
4679 | 1.45M | 2730979U, // sysLDMDB |
4680 | 1.45M | 875064291U, // sysLDMDB_UPD |
4681 | 1.45M | 2732107U, // sysLDMIA |
4682 | 1.45M | 875065419U, // sysLDMIA_UPD |
4683 | 1.45M | 2730998U, // sysLDMIB |
4684 | 1.45M | 875064310U, // sysLDMIB_UPD |
4685 | 1.45M | 2730730U, // sysSTMDA |
4686 | 1.45M | 875064042U, // sysSTMDA_UPD |
4687 | 1.45M | 2730986U, // sysSTMDB |
4688 | 1.45M | 875064298U, // sysSTMDB_UPD |
4689 | 1.45M | 2732142U, // sysSTMIA |
4690 | 1.45M | 875065454U, // sysSTMIA_UPD |
4691 | 1.45M | 2731004U, // sysSTMIB |
4692 | 1.45M | 875064316U, // sysSTMIB_UPD |
4693 | 1.45M | 2632970U, // t2ADCri |
4694 | 1.45M | 43527434U, // t2ADCrr |
4695 | 1.45M | 43584778U, // t2ADCrs |
4696 | 1.45M | 43527502U, // t2ADDri |
4697 | 1.45M | 2683996U, // t2ADDri12 |
4698 | 1.45M | 43527502U, // t2ADDrr |
4699 | 1.45M | 43584846U, // t2ADDrs |
4700 | 1.45M | 43527502U, // t2ADDspImm |
4701 | 1.45M | 2683996U, // t2ADDspImm12 |
4702 | 1.45M | 43544993U, // t2ADR |
4703 | 1.45M | 2633103U, // t2ANDri |
4704 | 1.45M | 43527567U, // t2ANDrr |
4705 | 1.45M | 43584911U, // t2ANDrs |
4706 | 1.45M | 43528674U, // t2ASRri |
4707 | 1.45M | 43528674U, // t2ASRrr |
4708 | 1.45M | 4413U, // t2AUT |
4709 | 1.45M | 808046091U, // t2AUTG |
4710 | 1.45M | 983149492U, // t2B |
4711 | 1.45M | 2682130U, // t2BFC |
4712 | 1.45M | 2666240U, // t2BFI |
4713 | 1.45M | 942174077U, // t2BFLi |
4714 | 1.45M | 942175649U, // t2BFLr |
4715 | 1.45M | 942173676U, // t2BFi |
4716 | 1.45M | 3962668948U, // t2BFic |
4717 | 1.45M | 942175570U, // t2BFr |
4718 | 1.45M | 2632983U, // t2BICri |
4719 | 1.45M | 43527447U, // t2BICrr |
4720 | 1.45M | 43584791U, // t2BICrs |
4721 | 1.45M | 1917U, // t2BTI |
4722 | 1.45M | 808047516U, // t2BXAUT |
4723 | 1.45M | 2731794U, // t2BXJ |
4724 | 1.45M | 983149492U, // t2Bcc |
4725 | 1.45M | 1277825288U, // t2CDP |
4726 | 1.45M | 1277823290U, // t2CDP2 |
4727 | 1.45M | 4314437U, // t2CLREX |
4728 | 1.45M | 2821312608U, // t2CLRM |
4729 | 1.45M | 2651636U, // t2CLZ |
4730 | 1.45M | 43544737U, // t2CMNri |
4731 | 1.45M | 43544737U, // t2CMNzrr |
4732 | 1.45M | 43577505U, // t2CMNzrs |
4733 | 1.45M | 43544850U, // t2CMPri |
4734 | 1.45M | 43544850U, // t2CMPrr |
4735 | 1.45M | 43577618U, // t2CMPrs |
4736 | 1.45M | 4278196U, // t2CPS1p |
4737 | 1.45M | 1452986965U, // t2CPS2p |
4738 | 1.45M | 1412092501U, // t2CPS3p |
4739 | 1.45M | 875644665U, // t2CRC32B |
4740 | 1.45M | 875644673U, // t2CRC32CB |
4741 | 1.45M | 875644783U, // t2CRC32CH |
4742 | 1.45M | 875644903U, // t2CRC32CW |
4743 | 1.45M | 875644775U, // t2CRC32H |
4744 | 1.45M | 875644895U, // t2CRC32W |
4745 | 1.45M | 875644822U, // t2CSEL |
4746 | 1.45M | 875644716U, // t2CSINC |
4747 | 1.45M | 875644874U, // t2CSINV |
4748 | 1.45M | 875644768U, // t2CSNEG |
4749 | 1.45M | 2731508U, // t2DBG |
4750 | 1.45M | 4311305U, // t2DCPS1 |
4751 | 1.45M | 4311370U, // t2DCPS2 |
4752 | 1.45M | 4311391U, // t2DCPS3 |
4753 | 1.45M | 875644842U, // t2DLS |
4754 | 1.45M | 4029262885U, // t2DMB |
4755 | 1.45M | 4029262981U, // t2DSB |
4756 | 1.45M | 2634192U, // t2EORri |
4757 | 1.45M | 43528656U, // t2EORrr |
4758 | 1.45M | 43586000U, // t2EORrs |
4759 | 1.45M | 43627272U, // t2HINT |
4760 | 1.45M | 4278225U, // t2HVC |
4761 | 1.45M | 4096371849U, // t2ISB |
4762 | 1.45M | 69751512U, // t2IT |
4763 | 1.45M | 0U, // t2Int_eh_sjlj_setjmp |
4764 | 1.45M | 0U, // t2Int_eh_sjlj_setjmp_nofp |
4765 | 1.45M | 2648800U, // t2LDA |
4766 | 1.45M | 2649009U, // t2LDAB |
4767 | 1.45M | 2651443U, // t2LDAEX |
4768 | 1.45M | 2649320U, // t2LDAEXB |
4769 | 1.45M | 2682283U, // t2LDAEXD |
4770 | 1.45M | 2649816U, // t2LDAEXH |
4771 | 1.45M | 2649616U, // t2LDAH |
4772 | 1.45M | 1277734678U, // t2LDC2L_OFFSET |
4773 | 1.45M | 1277734678U, // t2LDC2L_OPTION |
4774 | 1.45M | 1277734678U, // t2LDC2L_POST |
4775 | 1.45M | 1009307414U, // t2LDC2L_PRE |
4776 | 1.45M | 1277733152U, // t2LDC2_OFFSET |
4777 | 1.45M | 1277733152U, // t2LDC2_OPTION |
4778 | 1.45M | 1277733152U, // t2LDC2_POST |
4779 | 1.45M | 1009305888U, // t2LDC2_PRE |
4780 | 1.45M | 1277734746U, // t2LDCL_OFFSET |
4781 | 1.45M | 1277734746U, // t2LDCL_OPTION |
4782 | 1.45M | 1277734746U, // t2LDCL_POST |
4783 | 1.45M | 1009307482U, // t2LDCL_PRE |
4784 | 1.45M | 1277734158U, // t2LDC_OFFSET |
4785 | 1.45M | 1277734158U, // t2LDC_OPTION |
4786 | 1.45M | 1277734158U, // t2LDC_POST |
4787 | 1.45M | 1009306894U, // t2LDC_PRE |
4788 | 1.45M | 2730979U, // t2LDMDB |
4789 | 1.45M | 875064291U, // t2LDMDB_UPD |
4790 | 1.45M | 43626571U, // t2LDMIA |
4791 | 1.45M | 915959883U, // t2LDMIA_UPD |
4792 | 1.45M | 2683552U, // t2LDRBT |
4793 | 1.45M | 2665594U, // t2LDRB_POST |
4794 | 1.45M | 2665594U, // t2LDRB_PRE |
4795 | 1.45M | 43576442U, // t2LDRBi12 |
4796 | 1.45M | 2681978U, // t2LDRBi8 |
4797 | 1.45M | 43543674U, // t2LDRBpci |
4798 | 1.45M | 43560058U, // t2LDRBs |
4799 | 1.45M | 2674068U, // t2LDRD_POST |
4800 | 1.45M | 2674068U, // t2LDRD_PRE |
4801 | 1.45M | 2665876U, // t2LDRDi8 |
4802 | 1.45M | 2684223U, // t2LDREX |
4803 | 1.45M | 2649334U, // t2LDREXB |
4804 | 1.45M | 2682297U, // t2LDREXD |
4805 | 1.45M | 2649830U, // t2LDREXH |
4806 | 1.45M | 2683587U, // t2LDRHT |
4807 | 1.45M | 2666112U, // t2LDRH_POST |
4808 | 1.45M | 2666112U, // t2LDRH_PRE |
4809 | 1.45M | 43576960U, // t2LDRHi12 |
4810 | 1.45M | 2682496U, // t2LDRHi8 |
4811 | 1.45M | 43544192U, // t2LDRHpci |
4812 | 1.45M | 43560576U, // t2LDRHs |
4813 | 1.45M | 2683564U, // t2LDRSBT |
4814 | 1.45M | 2665613U, // t2LDRSB_POST |
4815 | 1.45M | 2665613U, // t2LDRSB_PRE |
4816 | 1.45M | 43576461U, // t2LDRSBi12 |
4817 | 1.45M | 2681997U, // t2LDRSBi8 |
4818 | 1.45M | 43543693U, // t2LDRSBpci |
4819 | 1.45M | 43560077U, // t2LDRSBs |
4820 | 1.45M | 2683599U, // t2LDRSHT |
4821 | 1.45M | 2666151U, // t2LDRSH_POST |
4822 | 1.45M | 2666151U, // t2LDRSH_PRE |
4823 | 1.45M | 43576999U, // t2LDRSHi12 |
4824 | 1.45M | 2682535U, // t2LDRSHi8 |
4825 | 1.45M | 43544231U, // t2LDRSHpci |
4826 | 1.45M | 43560615U, // t2LDRSHs |
4827 | 1.45M | 2683746U, // t2LDRT |
4828 | 1.45M | 2666918U, // t2LDR_POST |
4829 | 1.45M | 2666918U, // t2LDR_PRE |
4830 | 1.45M | 43577766U, // t2LDRi12 |
4831 | 1.45M | 2683302U, // t2LDRi8 |
4832 | 1.45M | 43544998U, // t2LDRpci |
4833 | 1.45M | 43561382U, // t2LDRs |
4834 | 1.45M | 4294487U, // t2LE |
4835 | 1.45M | 1882285911U, // t2LEUpdate |
4836 | 1.45M | 43528222U, // t2LSLri |
4837 | 1.45M | 43528222U, // t2LSLrr |
4838 | 1.45M | 43528681U, // t2LSRri |
4839 | 1.45M | 43528681U, // t2LSRrr |
4840 | 1.45M | 1277825437U, // t2MCR |
4841 | 1.45M | 1277823295U, // t2MCR2 |
4842 | 1.45M | 1277743576U, // t2MCRR |
4843 | 1.45M | 1277741380U, // t2MCRR2 |
4844 | 1.45M | 2665252U, // t2MLA |
4845 | 1.45M | 2667053U, // t2MLS |
4846 | 1.45M | 2683821U, // t2MOVTi16 |
4847 | 1.45M | 43553867U, // t2MOVi |
4848 | 1.45M | 2651250U, // t2MOVi16 |
4849 | 1.45M | 43553867U, // t2MOVr |
4850 | 1.45M | 43545182U, // t2MOVsra_flag |
4851 | 1.45M | 43545187U, // t2MOVsrl_flag |
4852 | 1.45M | 1009388837U, // t2MRC |
4853 | 1.45M | 1009387813U, // t2MRC2 |
4854 | 1.45M | 1680395561U, // t2MRRC |
4855 | 1.45M | 1680394538U, // t2MRRC2 |
4856 | 1.45M | 2732634U, // t2MRS_AR |
4857 | 1.45M | 2650714U, // t2MRS_M |
4858 | 1.45M | 2650714U, // t2MRSbanked |
4859 | 1.45M | 2732634U, // t2MRSsys_AR |
4860 | 1.45M | 1747481070U, // t2MSR_AR |
4861 | 1.45M | 1747481070U, // t2MSR_M |
4862 | 1.45M | 1814589934U, // t2MSRbanked |
4863 | 1.45M | 2682926U, // t2MUL |
4864 | 1.45M | 2658546U, // t2MVNi |
4865 | 1.45M | 43553010U, // t2MVNr |
4866 | 1.45M | 43528434U, // t2MVNs |
4867 | 1.45M | 2633922U, // t2ORNri |
4868 | 1.45M | 2633922U, // t2ORNrr |
4869 | 1.45M | 2691266U, // t2ORNrs |
4870 | 1.45M | 2634206U, // t2ORRri |
4871 | 1.45M | 43528670U, // t2ORRrr |
4872 | 1.45M | 43586014U, // t2ORRrs |
4873 | 1.45M | 4378U, // t2PAC |
4874 | 1.45M | 4394U, // t2PACBTI |
4875 | 1.45M | 2731512U, // t2PACG |
4876 | 1.45M | 2667147U, // t2PKHBT |
4877 | 1.45M | 2665630U, // t2PKHTB |
4878 | 1.45M | 4163400801U, // t2PLDWi12 |
4879 | 1.45M | 4230509665U, // t2PLDWi8 |
4880 | 1.45M | 2684001U, // t2PLDWs |
4881 | 1.45M | 4163399043U, // t2PLDi12 |
4882 | 1.45M | 4230507907U, // t2PLDi8 |
4883 | 1.45M | 69840259U, // t2PLDpci |
4884 | 1.45M | 2682243U, // t2PLDs |
4885 | 1.45M | 4163399428U, // t2PLIi12 |
4886 | 1.45M | 4230508292U, // t2PLIi8 |
4887 | 1.45M | 69840644U, // t2PLIpci |
4888 | 1.45M | 2682628U, // t2PLIs |
4889 | 1.45M | 2682226U, // t2QADD |
4890 | 1.45M | 2681301U, // t2QADD16 |
4891 | 1.45M | 2681404U, // t2QADD8 |
4892 | 1.45M | 2684343U, // t2QASX |
4893 | 1.45M | 2682200U, // t2QDADD |
4894 | 1.45M | 2682051U, // t2QDSUB |
4895 | 1.45M | 2684089U, // t2QSAX |
4896 | 1.45M | 2682064U, // t2QSUB |
4897 | 1.45M | 2681263U, // t2QSUB16 |
4898 | 1.45M | 2681365U, // t2QSUB8 |
4899 | 1.45M | 2650838U, // t2RBIT |
4900 | 1.45M | 43545626U, // t2REV |
4901 | 1.45M | 43543033U, // t2REV16 |
4902 | 1.45M | 43544242U, // t2REVSH |
4903 | 1.45M | 2730972U, // t2RFEDB |
4904 | 1.45M | 2730972U, // t2RFEDBW |
4905 | 1.45M | 2730760U, // t2RFEIA |
4906 | 1.45M | 2730760U, // t2RFEIAW |
4907 | 1.45M | 43528660U, // t2RORri |
4908 | 1.45M | 43528660U, // t2RORrr |
4909 | 1.45M | 2659750U, // t2RRX |
4910 | 1.45M | 43527311U, // t2RSBri |
4911 | 1.45M | 2632847U, // t2RSBrr |
4912 | 1.45M | 2690191U, // t2RSBrs |
4913 | 1.45M | 2681308U, // t2SADD16 |
4914 | 1.45M | 2681410U, // t2SADD8 |
4915 | 1.45M | 2684348U, // t2SASX |
4916 | 1.45M | 3206U, // t2SB |
4917 | 1.45M | 2632965U, // t2SBCri |
4918 | 1.45M | 43527429U, // t2SBCrr |
4919 | 1.45M | 43584773U, // t2SBCrs |
4920 | 1.45M | 2667857U, // t2SBFX |
4921 | 1.45M | 2683934U, // t2SDIV |
4922 | 1.45M | 2682745U, // t2SEL |
4923 | 1.45M | 4278172U, // t2SETPAN |
4924 | 1.45M | 4312584U, // t2SG |
4925 | 1.45M | 2681284U, // t2SHADD16 |
4926 | 1.45M | 2681389U, // t2SHADD8 |
4927 | 1.45M | 2684330U, // t2SHASX |
4928 | 1.45M | 2684076U, // t2SHSAX |
4929 | 1.45M | 2681246U, // t2SHSUB16 |
4930 | 1.45M | 2681350U, // t2SHSUB8 |
4931 | 1.45M | 2731297U, // t2SMC |
4932 | 1.45M | 2665410U, // t2SMLABB |
4933 | 1.45M | 2667140U, // t2SMLABT |
4934 | 1.45M | 2665786U, // t2SMLAD |
4935 | 1.45M | 2667783U, // t2SMLADX |
4936 | 1.45M | 2756413U, // t2SMLAL |
4937 | 1.45M | 2755529U, // t2SMLALBB |
4938 | 1.45M | 2757265U, // t2SMLALBT |
4939 | 1.45M | 2755964U, // t2SMLALD |
4940 | 1.45M | 2757909U, // t2SMLALDX |
4941 | 1.45M | 2755748U, // t2SMLALTB |
4942 | 1.45M | 2757507U, // t2SMLALTT |
4943 | 1.45M | 2665623U, // t2SMLATB |
4944 | 1.45M | 2667388U, // t2SMLATT |
4945 | 1.45M | 2665690U, // t2SMLAWB |
4946 | 1.45M | 2667442U, // t2SMLAWT |
4947 | 1.45M | 2665887U, // t2SMLSD |
4948 | 1.45M | 2667813U, // t2SMLSDX |
4949 | 1.45M | 2755975U, // t2SMLSLD |
4950 | 1.45M | 2757917U, // t2SMLSLDX |
4951 | 1.45M | 2665256U, // t2SMMLA |
4952 | 1.45M | 2666902U, // t2SMMLAR |
4953 | 1.45M | 2667051U, // t2SMMLS |
4954 | 1.45M | 2666982U, // t2SMMLSR |
4955 | 1.45M | 2682930U, // t2SMMUL |
4956 | 1.45M | 2683336U, // t2SMMULR |
4957 | 1.45M | 2682176U, // t2SMUAD |
4958 | 1.45M | 2684174U, // t2SMUADX |
4959 | 1.45M | 2681809U, // t2SMULBB |
4960 | 1.45M | 2683545U, // t2SMULBT |
4961 | 1.45M | 2666467U, // t2SMULL |
4962 | 1.45M | 2682028U, // t2SMULTB |
4963 | 1.45M | 2683787U, // t2SMULTT |
4964 | 1.45M | 2682081U, // t2SMULWB |
4965 | 1.45M | 2683833U, // t2SMULWT |
4966 | 1.45M | 2682277U, // t2SMUSD |
4967 | 1.45M | 2684204U, // t2SMUSDX |
4968 | 1.45M | 44149744U, // t2SRSDB |
4969 | 1.45M | 44674032U, // t2SRSDB_UPD |
4970 | 1.45M | 44149532U, // t2SRSIA |
4971 | 1.45M | 44673820U, // t2SRSIA_UPD |
4972 | 1.45M | 2667125U, // t2SSAT |
4973 | 1.45M | 2681322U, // t2SSAT16 |
4974 | 1.45M | 2684094U, // t2SSAX |
4975 | 1.45M | 2681270U, // t2SSUB16 |
4976 | 1.45M | 2681371U, // t2SSUB8 |
4977 | 1.45M | 1277734684U, // t2STC2L_OFFSET |
4978 | 1.45M | 1277734684U, // t2STC2L_OPTION |
4979 | 1.45M | 1277734684U, // t2STC2L_POST |
4980 | 1.45M | 1009307420U, // t2STC2L_PRE |
4981 | 1.45M | 1277733168U, // t2STC2_OFFSET |
4982 | 1.45M | 1277733168U, // t2STC2_OPTION |
4983 | 1.45M | 1277733168U, // t2STC2_POST |
4984 | 1.45M | 1009305904U, // t2STC2_PRE |
4985 | 1.45M | 1277734751U, // t2STCL_OFFSET |
4986 | 1.45M | 1277734751U, // t2STCL_OPTION |
4987 | 1.45M | 1277734751U, // t2STCL_POST |
4988 | 1.45M | 1009307487U, // t2STCL_PRE |
4989 | 1.45M | 1277734194U, // t2STC_OFFSET |
4990 | 1.45M | 1277734194U, // t2STC_OPTION |
4991 | 1.45M | 1277734194U, // t2STC_POST |
4992 | 1.45M | 1009306930U, // t2STC_PRE |
4993 | 1.45M | 2650152U, // t2STL |
4994 | 1.45M | 2649113U, // t2STLB |
4995 | 1.45M | 2684217U, // t2STLEX |
4996 | 1.45M | 2682095U, // t2STLEXB |
4997 | 1.45M | 2665906U, // t2STLEXD |
4998 | 1.45M | 2682591U, // t2STLEXH |
4999 | 1.45M | 2649692U, // t2STLH |
5000 | 1.45M | 2730986U, // t2STMDB |
5001 | 1.45M | 875064298U, // t2STMDB_UPD |
5002 | 1.45M | 43626606U, // t2STMIA |
5003 | 1.45M | 915959918U, // t2STMIA_UPD |
5004 | 1.45M | 2683558U, // t2STRBT |
5005 | 1.45M | 875080832U, // t2STRB_POST |
5006 | 1.45M | 875080832U, // t2STRB_PRE |
5007 | 1.45M | 43576448U, // t2STRBi12 |
5008 | 1.45M | 2681984U, // t2STRBi8 |
5009 | 1.45M | 43560064U, // t2STRBs |
5010 | 1.45M | 875089306U, // t2STRD_POST |
5011 | 1.45M | 875089306U, // t2STRD_PRE |
5012 | 1.45M | 2665882U, // t2STRDi8 |
5013 | 1.45M | 2667851U, // t2STREX |
5014 | 1.45M | 2682109U, // t2STREXB |
5015 | 1.45M | 2665920U, // t2STREXD |
5016 | 1.45M | 2682605U, // t2STREXH |
5017 | 1.45M | 2683593U, // t2STRHT |
5018 | 1.45M | 875081350U, // t2STRH_POST |
5019 | 1.45M | 875081350U, // t2STRH_PRE |
5020 | 1.45M | 43576966U, // t2STRHi12 |
5021 | 1.45M | 2682502U, // t2STRHi8 |
5022 | 1.45M | 43560582U, // t2STRHs |
5023 | 1.45M | 2683757U, // t2STRT |
5024 | 1.45M | 875082240U, // t2STR_POST |
5025 | 1.45M | 875082240U, // t2STR_PRE |
5026 | 1.45M | 43577856U, // t2STRi12 |
5027 | 1.45M | 2683392U, // t2STRi8 |
5028 | 1.45M | 43561472U, // t2STRs |
5029 | 1.45M | 45199905U, // t2SUBS_PC_LR |
5030 | 1.45M | 43527365U, // t2SUBri |
5031 | 1.45M | 2683990U, // t2SUBri12 |
5032 | 1.45M | 43527365U, // t2SUBrr |
5033 | 1.45M | 43584709U, // t2SUBrs |
5034 | 1.45M | 43527365U, // t2SUBspImm |
5035 | 1.45M | 2683990U, // t2SUBspImm12 |
5036 | 1.45M | 2665398U, // t2SXTAB |
5037 | 1.45M | 2664832U, // t2SXTAB16 |
5038 | 1.45M | 2666022U, // t2SXTAH |
5039 | 1.45M | 43576505U, // t2SXTB |
5040 | 1.45M | 2681232U, // t2SXTB16 |
5041 | 1.45M | 43577016U, // t2SXTH |
5042 | 1.45M | 136866776U, // t2TBB |
5043 | 1.45M | 203976242U, // t2TBH |
5044 | 1.45M | 43544978U, // t2TEQri |
5045 | 1.45M | 43544978U, // t2TEQrr |
5046 | 1.45M | 43577746U, // t2TEQrs |
5047 | 1.45M | 271166611U, // t2TSB |
5048 | 1.45M | 43545464U, // t2TSTri |
5049 | 1.45M | 43545464U, // t2TSTrr |
5050 | 1.45M | 43578232U, // t2TSTrs |
5051 | 1.45M | 2651008U, // t2TT |
5052 | 1.45M | 2648940U, // t2TTA |
5053 | 1.45M | 2650751U, // t2TTAT |
5054 | 1.45M | 2651026U, // t2TTT |
5055 | 1.45M | 2681315U, // t2UADD16 |
5056 | 1.45M | 2681416U, // t2UADD8 |
5057 | 1.45M | 2684353U, // t2UASX |
5058 | 1.45M | 2667862U, // t2UBFX |
5059 | 1.45M | 4278232U, // t2UDF |
5060 | 1.45M | 2683939U, // t2UDIV |
5061 | 1.45M | 2681292U, // t2UHADD16 |
5062 | 1.45M | 2681396U, // t2UHADD8 |
5063 | 1.45M | 2684336U, // t2UHASX |
5064 | 1.45M | 2684082U, // t2UHSAX |
5065 | 1.45M | 2681254U, // t2UHSUB16 |
5066 | 1.45M | 2681357U, // t2UHSUB8 |
5067 | 1.45M | 2756386U, // t2UMAAL |
5068 | 1.45M | 2756419U, // t2UMLAL |
5069 | 1.45M | 2666473U, // t2UMULL |
5070 | 1.45M | 2681300U, // t2UQADD16 |
5071 | 1.45M | 2681403U, // t2UQADD8 |
5072 | 1.45M | 2684342U, // t2UQASX |
5073 | 1.45M | 2684088U, // t2UQSAX |
5074 | 1.45M | 2681262U, // t2UQSUB16 |
5075 | 1.45M | 2681364U, // t2UQSUB8 |
5076 | 1.45M | 2681383U, // t2USAD8 |
5077 | 1.45M | 2664959U, // t2USADA8 |
5078 | 1.45M | 2667130U, // t2USAT |
5079 | 1.45M | 2681329U, // t2USAT16 |
5080 | 1.45M | 2684099U, // t2USAX |
5081 | 1.45M | 2681277U, // t2USUB16 |
5082 | 1.45M | 2681377U, // t2USUB8 |
5083 | 1.45M | 2665404U, // t2UXTAB |
5084 | 1.45M | 2664840U, // t2UXTAB16 |
5085 | 1.45M | 2666028U, // t2UXTAH |
5086 | 1.45M | 43576510U, // t2UXTB |
5087 | 1.45M | 2681239U, // t2UXTB16 |
5088 | 1.45M | 43577021U, // t2UXTH |
5089 | 1.45M | 875644847U, // t2WLS |
5090 | 1.45M | 1253920010U, // tADC |
5091 | 1.45M | 2682190U, // tADDhirr |
5092 | 1.45M | 851266894U, // tADDi3 |
5093 | 1.45M | 1253920078U, // tADDi8 |
5094 | 1.45M | 2682190U, // tADDrSP |
5095 | 1.45M | 2682190U, // tADDrSPi |
5096 | 1.45M | 851266894U, // tADDrr |
5097 | 1.45M | 2682190U, // tADDspi |
5098 | 1.45M | 2682190U, // tADDspr |
5099 | 1.45M | 2650529U, // tADR |
5100 | 1.45M | 1253920143U, // tAND |
5101 | 1.45M | 851268066U, // tASRri |
5102 | 1.45M | 1253921250U, // tASRrr |
5103 | 1.45M | 942255028U, // tB |
5104 | 1.45M | 1253920023U, // tBIC |
5105 | 1.45M | 4278212U, // tBKPT |
5106 | 1.45M | 1881788241U, // tBL |
5107 | 1.45M | 808047180U, // tBLXNSr |
5108 | 1.45M | 1881789853U, // tBLXi |
5109 | 1.45M | 808048029U, // tBLXr |
5110 | 1.45M | 2733303U, // tBX |
5111 | 1.45M | 2732615U, // tBXNS |
5112 | 1.45M | 942255028U, // tBcc |
5113 | 1.45M | 3962652676U, // tCBNZ |
5114 | 1.45M | 3962652671U, // tCBZ |
5115 | 1.45M | 2650273U, // tCMNz |
5116 | 1.45M | 2650386U, // tCMPhir |
5117 | 1.45M | 2650386U, // tCMPi8 |
5118 | 1.45M | 2650386U, // tCMPr |
5119 | 1.45M | 1409471061U, // tCPS |
5120 | 1.45M | 1253921232U, // tEOR |
5121 | 1.45M | 2732808U, // tHINT |
5122 | 1.45M | 4278207U, // tHLT |
5123 | 1.45M | 0U, // tInt_WIN_eh_sjlj_longjmp |
5124 | 1.45M | 0U, // tInt_eh_sjlj_longjmp |
5125 | 1.45M | 0U, // tInt_eh_sjlj_setjmp |
5126 | 1.45M | 2732107U, // tLDMIA |
5127 | 1.45M | 2681978U, // tLDRBi |
5128 | 1.45M | 2681978U, // tLDRBr |
5129 | 1.45M | 2682496U, // tLDRHi |
5130 | 1.45M | 2682496U, // tLDRHr |
5131 | 1.45M | 2681997U, // tLDRSB |
5132 | 1.45M | 2682535U, // tLDRSH |
5133 | 1.45M | 2683302U, // tLDRi |
5134 | 1.45M | 2650534U, // tLDRpci |
5135 | 1.45M | 2683302U, // tLDRr |
5136 | 1.45M | 2683302U, // tLDRspi |
5137 | 1.45M | 851267614U, // tLSLri |
5138 | 1.45M | 1253920798U, // tLSLrr |
5139 | 1.45M | 851268073U, // tLSRri |
5140 | 1.45M | 1253921257U, // tLSRrr |
5141 | 1.45M | 875644857U, // tMOVSr |
5142 | 1.45M | 1120228427U, // tMOVi8 |
5143 | 1.45M | 2651211U, // tMOVr |
5144 | 1.45M | 851267630U, // tMUL |
5145 | 1.45M | 1120227570U, // tMVN |
5146 | 1.45M | 1253921246U, // tORR |
5147 | 1.45M | 0U, // tPICADD |
5148 | 1.45M | 2821312790U, // tPOP |
5149 | 1.45M | 2821312173U, // tPUSH |
5150 | 1.45M | 2651162U, // tREV |
5151 | 1.45M | 2648569U, // tREV16 |
5152 | 1.45M | 2649778U, // tREVSH |
5153 | 1.45M | 1253921236U, // tROR |
5154 | 1.45M | 2126859407U, // tRSB |
5155 | 1.45M | 1253920005U, // tSBC |
5156 | 1.45M | 280399U, // tSETEND |
5157 | 1.45M | 875065454U, // tSTMIA_UPD |
5158 | 1.45M | 2681984U, // tSTRBi |
5159 | 1.45M | 2681984U, // tSTRBr |
5160 | 1.45M | 2682502U, // tSTRHi |
5161 | 1.45M | 2682502U, // tSTRHr |
5162 | 1.45M | 2683392U, // tSTRi |
5163 | 1.45M | 2683392U, // tSTRr |
5164 | 1.45M | 2683392U, // tSTRspi |
5165 | 1.45M | 851266757U, // tSUBi3 |
5166 | 1.45M | 1253919941U, // tSUBi8 |
5167 | 1.45M | 851266757U, // tSUBrr |
5168 | 1.45M | 2682053U, // tSUBspi |
5169 | 1.45M | 2731318U, // tSVC |
5170 | 1.45M | 2649273U, // tSXTB |
5171 | 1.45M | 2649784U, // tSXTH |
5172 | 1.45M | 4355U, // tTRAP |
5173 | 1.45M | 2651000U, // tTST |
5174 | 1.45M | 4278107U, // tUDF |
5175 | 1.45M | 2649278U, // tUXTB |
5176 | 1.45M | 2649789U, // tUXTH |
5177 | 1.45M | 2298U, // t__brkdiv0 |
5178 | 1.45M | }; |
5179 | | |
5180 | 1.45M | static const uint32_t OpInfo1[] = { |
5181 | 1.45M | 0U, // PHI |
5182 | 1.45M | 0U, // INLINEASM |
5183 | 1.45M | 0U, // INLINEASM_BR |
5184 | 1.45M | 0U, // CFI_INSTRUCTION |
5185 | 1.45M | 0U, // EH_LABEL |
5186 | 1.45M | 0U, // GC_LABEL |
5187 | 1.45M | 0U, // ANNOTATION_LABEL |
5188 | 1.45M | 0U, // KILL |
5189 | 1.45M | 0U, // EXTRACT_SUBREG |
5190 | 1.45M | 0U, // INSERT_SUBREG |
5191 | 1.45M | 0U, // IMPLICIT_DEF |
5192 | 1.45M | 0U, // SUBREG_TO_REG |
5193 | 1.45M | 0U, // COPY_TO_REGCLASS |
5194 | 1.45M | 0U, // DBG_VALUE |
5195 | 1.45M | 0U, // DBG_VALUE_LIST |
5196 | 1.45M | 0U, // DBG_INSTR_REF |
5197 | 1.45M | 0U, // DBG_PHI |
5198 | 1.45M | 0U, // DBG_LABEL |
5199 | 1.45M | 0U, // REG_SEQUENCE |
5200 | 1.45M | 0U, // COPY |
5201 | 1.45M | 0U, // BUNDLE |
5202 | 1.45M | 0U, // LIFETIME_START |
5203 | 1.45M | 0U, // LIFETIME_END |
5204 | 1.45M | 0U, // PSEUDO_PROBE |
5205 | 1.45M | 0U, // ARITH_FENCE |
5206 | 1.45M | 0U, // STACKMAP |
5207 | 1.45M | 0U, // FENTRY_CALL |
5208 | 1.45M | 0U, // PATCHPOINT |
5209 | 1.45M | 0U, // LOAD_STACK_GUARD |
5210 | 1.45M | 0U, // PREALLOCATED_SETUP |
5211 | 1.45M | 0U, // PREALLOCATED_ARG |
5212 | 1.45M | 0U, // STATEPOINT |
5213 | 1.45M | 0U, // LOCAL_ESCAPE |
5214 | 1.45M | 0U, // FAULTING_OP |
5215 | 1.45M | 0U, // PATCHABLE_OP |
5216 | 1.45M | 0U, // PATCHABLE_FUNCTION_ENTER |
5217 | 1.45M | 0U, // PATCHABLE_RET |
5218 | 1.45M | 0U, // PATCHABLE_FUNCTION_EXIT |
5219 | 1.45M | 0U, // PATCHABLE_TAIL_CALL |
5220 | 1.45M | 0U, // PATCHABLE_EVENT_CALL |
5221 | 1.45M | 0U, // PATCHABLE_TYPED_EVENT_CALL |
5222 | 1.45M | 0U, // ICALL_BRANCH_FUNNEL |
5223 | 1.45M | 0U, // MEMBARRIER |
5224 | 1.45M | 0U, // G_ASSERT_SEXT |
5225 | 1.45M | 0U, // G_ASSERT_ZEXT |
5226 | 1.45M | 0U, // G_ASSERT_ALIGN |
5227 | 1.45M | 0U, // G_ADD |
5228 | 1.45M | 0U, // G_SUB |
5229 | 1.45M | 0U, // G_MUL |
5230 | 1.45M | 0U, // G_SDIV |
5231 | 1.45M | 0U, // G_UDIV |
5232 | 1.45M | 0U, // G_SREM |
5233 | 1.45M | 0U, // G_UREM |
5234 | 1.45M | 0U, // G_SDIVREM |
5235 | 1.45M | 0U, // G_UDIVREM |
5236 | 1.45M | 0U, // G_AND |
5237 | 1.45M | 0U, // G_OR |
5238 | 1.45M | 0U, // G_XOR |
5239 | 1.45M | 0U, // G_IMPLICIT_DEF |
5240 | 1.45M | 0U, // G_PHI |
5241 | 1.45M | 0U, // G_FRAME_INDEX |
5242 | 1.45M | 0U, // G_GLOBAL_VALUE |
5243 | 1.45M | 0U, // G_EXTRACT |
5244 | 1.45M | 0U, // G_UNMERGE_VALUES |
5245 | 1.45M | 0U, // G_INSERT |
5246 | 1.45M | 0U, // G_MERGE_VALUES |
5247 | 1.45M | 0U, // G_BUILD_VECTOR |
5248 | 1.45M | 0U, // G_BUILD_VECTOR_TRUNC |
5249 | 1.45M | 0U, // G_CONCAT_VECTORS |
5250 | 1.45M | 0U, // G_PTRTOINT |
5251 | 1.45M | 0U, // G_INTTOPTR |
5252 | 1.45M | 0U, // G_BITCAST |
5253 | 1.45M | 0U, // G_FREEZE |
5254 | 1.45M | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
5255 | 1.45M | 0U, // G_INTRINSIC_TRUNC |
5256 | 1.45M | 0U, // G_INTRINSIC_ROUND |
5257 | 1.45M | 0U, // G_INTRINSIC_LRINT |
5258 | 1.45M | 0U, // G_INTRINSIC_ROUNDEVEN |
5259 | 1.45M | 0U, // G_READCYCLECOUNTER |
5260 | 1.45M | 0U, // G_LOAD |
5261 | 1.45M | 0U, // G_SEXTLOAD |
5262 | 1.45M | 0U, // G_ZEXTLOAD |
5263 | 1.45M | 0U, // G_INDEXED_LOAD |
5264 | 1.45M | 0U, // G_INDEXED_SEXTLOAD |
5265 | 1.45M | 0U, // G_INDEXED_ZEXTLOAD |
5266 | 1.45M | 0U, // G_STORE |
5267 | 1.45M | 0U, // G_INDEXED_STORE |
5268 | 1.45M | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
5269 | 1.45M | 0U, // G_ATOMIC_CMPXCHG |
5270 | 1.45M | 0U, // G_ATOMICRMW_XCHG |
5271 | 1.45M | 0U, // G_ATOMICRMW_ADD |
5272 | 1.45M | 0U, // G_ATOMICRMW_SUB |
5273 | 1.45M | 0U, // G_ATOMICRMW_AND |
5274 | 1.45M | 0U, // G_ATOMICRMW_NAND |
5275 | 1.45M | 0U, // G_ATOMICRMW_OR |
5276 | 1.45M | 0U, // G_ATOMICRMW_XOR |
5277 | 1.45M | 0U, // G_ATOMICRMW_MAX |
5278 | 1.45M | 0U, // G_ATOMICRMW_MIN |
5279 | 1.45M | 0U, // G_ATOMICRMW_UMAX |
5280 | 1.45M | 0U, // G_ATOMICRMW_UMIN |
5281 | 1.45M | 0U, // G_ATOMICRMW_FADD |
5282 | 1.45M | 0U, // G_ATOMICRMW_FSUB |
5283 | 1.45M | 0U, // G_ATOMICRMW_FMAX |
5284 | 1.45M | 0U, // G_ATOMICRMW_FMIN |
5285 | 1.45M | 0U, // G_ATOMICRMW_UINC_WRAP |
5286 | 1.45M | 0U, // G_ATOMICRMW_UDEC_WRAP |
5287 | 1.45M | 0U, // G_FENCE |
5288 | 1.45M | 0U, // G_BRCOND |
5289 | 1.45M | 0U, // G_BRINDIRECT |
5290 | 1.45M | 0U, // G_INVOKE_REGION_START |
5291 | 1.45M | 0U, // G_INTRINSIC |
5292 | 1.45M | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
5293 | 1.45M | 0U, // G_ANYEXT |
5294 | 1.45M | 0U, // G_TRUNC |
5295 | 1.45M | 0U, // G_CONSTANT |
5296 | 1.45M | 0U, // G_FCONSTANT |
5297 | 1.45M | 0U, // G_VASTART |
5298 | 1.45M | 0U, // G_VAARG |
5299 | 1.45M | 0U, // G_SEXT |
5300 | 1.45M | 0U, // G_SEXT_INREG |
5301 | 1.45M | 0U, // G_ZEXT |
5302 | 1.45M | 0U, // G_SHL |
5303 | 1.45M | 0U, // G_LSHR |
5304 | 1.45M | 0U, // G_ASHR |
5305 | 1.45M | 0U, // G_FSHL |
5306 | 1.45M | 0U, // G_FSHR |
5307 | 1.45M | 0U, // G_ROTR |
5308 | 1.45M | 0U, // G_ROTL |
5309 | 1.45M | 0U, // G_ICMP |
5310 | 1.45M | 0U, // G_FCMP |
5311 | 1.45M | 0U, // G_SELECT |
5312 | 1.45M | 0U, // G_UADDO |
5313 | 1.45M | 0U, // G_UADDE |
5314 | 1.45M | 0U, // G_USUBO |
5315 | 1.45M | 0U, // G_USUBE |
5316 | 1.45M | 0U, // G_SADDO |
5317 | 1.45M | 0U, // G_SADDE |
5318 | 1.45M | 0U, // G_SSUBO |
5319 | 1.45M | 0U, // G_SSUBE |
5320 | 1.45M | 0U, // G_UMULO |
5321 | 1.45M | 0U, // G_SMULO |
5322 | 1.45M | 0U, // G_UMULH |
5323 | 1.45M | 0U, // G_SMULH |
5324 | 1.45M | 0U, // G_UADDSAT |
5325 | 1.45M | 0U, // G_SADDSAT |
5326 | 1.45M | 0U, // G_USUBSAT |
5327 | 1.45M | 0U, // G_SSUBSAT |
5328 | 1.45M | 0U, // G_USHLSAT |
5329 | 1.45M | 0U, // G_SSHLSAT |
5330 | 1.45M | 0U, // G_SMULFIX |
5331 | 1.45M | 0U, // G_UMULFIX |
5332 | 1.45M | 0U, // G_SMULFIXSAT |
5333 | 1.45M | 0U, // G_UMULFIXSAT |
5334 | 1.45M | 0U, // G_SDIVFIX |
5335 | 1.45M | 0U, // G_UDIVFIX |
5336 | 1.45M | 0U, // G_SDIVFIXSAT |
5337 | 1.45M | 0U, // G_UDIVFIXSAT |
5338 | 1.45M | 0U, // G_FADD |
5339 | 1.45M | 0U, // G_FSUB |
5340 | 1.45M | 0U, // G_FMUL |
5341 | 1.45M | 0U, // G_FMA |
5342 | 1.45M | 0U, // G_FMAD |
5343 | 1.45M | 0U, // G_FDIV |
5344 | 1.45M | 0U, // G_FREM |
5345 | 1.45M | 0U, // G_FPOW |
5346 | 1.45M | 0U, // G_FPOWI |
5347 | 1.45M | 0U, // G_FEXP |
5348 | 1.45M | 0U, // G_FEXP2 |
5349 | 1.45M | 0U, // G_FLOG |
5350 | 1.45M | 0U, // G_FLOG2 |
5351 | 1.45M | 0U, // G_FLOG10 |
5352 | 1.45M | 0U, // G_FNEG |
5353 | 1.45M | 0U, // G_FPEXT |
5354 | 1.45M | 0U, // G_FPTRUNC |
5355 | 1.45M | 0U, // G_FPTOSI |
5356 | 1.45M | 0U, // G_FPTOUI |
5357 | 1.45M | 0U, // G_SITOFP |
5358 | 1.45M | 0U, // G_UITOFP |
5359 | 1.45M | 0U, // G_FABS |
5360 | 1.45M | 0U, // G_FCOPYSIGN |
5361 | 1.45M | 0U, // G_IS_FPCLASS |
5362 | 1.45M | 0U, // G_FCANONICALIZE |
5363 | 1.45M | 0U, // G_FMINNUM |
5364 | 1.45M | 0U, // G_FMAXNUM |
5365 | 1.45M | 0U, // G_FMINNUM_IEEE |
5366 | 1.45M | 0U, // G_FMAXNUM_IEEE |
5367 | 1.45M | 0U, // G_FMINIMUM |
5368 | 1.45M | 0U, // G_FMAXIMUM |
5369 | 1.45M | 0U, // G_PTR_ADD |
5370 | 1.45M | 0U, // G_PTRMASK |
5371 | 1.45M | 0U, // G_SMIN |
5372 | 1.45M | 0U, // G_SMAX |
5373 | 1.45M | 0U, // G_UMIN |
5374 | 1.45M | 0U, // G_UMAX |
5375 | 1.45M | 0U, // G_ABS |
5376 | 1.45M | 0U, // G_LROUND |
5377 | 1.45M | 0U, // G_LLROUND |
5378 | 1.45M | 0U, // G_BR |
5379 | 1.45M | 0U, // G_BRJT |
5380 | 1.45M | 0U, // G_INSERT_VECTOR_ELT |
5381 | 1.45M | 0U, // G_EXTRACT_VECTOR_ELT |
5382 | 1.45M | 0U, // G_SHUFFLE_VECTOR |
5383 | 1.45M | 0U, // G_CTTZ |
5384 | 1.45M | 0U, // G_CTTZ_ZERO_UNDEF |
5385 | 1.45M | 0U, // G_CTLZ |
5386 | 1.45M | 0U, // G_CTLZ_ZERO_UNDEF |
5387 | 1.45M | 0U, // G_CTPOP |
5388 | 1.45M | 0U, // G_BSWAP |
5389 | 1.45M | 0U, // G_BITREVERSE |
5390 | 1.45M | 0U, // G_FCEIL |
5391 | 1.45M | 0U, // G_FCOS |
5392 | 1.45M | 0U, // G_FSIN |
5393 | 1.45M | 0U, // G_FSQRT |
5394 | 1.45M | 0U, // G_FFLOOR |
5395 | 1.45M | 0U, // G_FRINT |
5396 | 1.45M | 0U, // G_FNEARBYINT |
5397 | 1.45M | 0U, // G_ADDRSPACE_CAST |
5398 | 1.45M | 0U, // G_BLOCK_ADDR |
5399 | 1.45M | 0U, // G_JUMP_TABLE |
5400 | 1.45M | 0U, // G_DYN_STACKALLOC |
5401 | 1.45M | 0U, // G_STRICT_FADD |
5402 | 1.45M | 0U, // G_STRICT_FSUB |
5403 | 1.45M | 0U, // G_STRICT_FMUL |
5404 | 1.45M | 0U, // G_STRICT_FDIV |
5405 | 1.45M | 0U, // G_STRICT_FREM |
5406 | 1.45M | 0U, // G_STRICT_FMA |
5407 | 1.45M | 0U, // G_STRICT_FSQRT |
5408 | 1.45M | 0U, // G_READ_REGISTER |
5409 | 1.45M | 0U, // G_WRITE_REGISTER |
5410 | 1.45M | 0U, // G_MEMCPY |
5411 | 1.45M | 0U, // G_MEMCPY_INLINE |
5412 | 1.45M | 0U, // G_MEMMOVE |
5413 | 1.45M | 0U, // G_MEMSET |
5414 | 1.45M | 0U, // G_BZERO |
5415 | 1.45M | 0U, // G_VECREDUCE_SEQ_FADD |
5416 | 1.45M | 0U, // G_VECREDUCE_SEQ_FMUL |
5417 | 1.45M | 0U, // G_VECREDUCE_FADD |
5418 | 1.45M | 0U, // G_VECREDUCE_FMUL |
5419 | 1.45M | 0U, // G_VECREDUCE_FMAX |
5420 | 1.45M | 0U, // G_VECREDUCE_FMIN |
5421 | 1.45M | 0U, // G_VECREDUCE_ADD |
5422 | 1.45M | 0U, // G_VECREDUCE_MUL |
5423 | 1.45M | 0U, // G_VECREDUCE_AND |
5424 | 1.45M | 0U, // G_VECREDUCE_OR |
5425 | 1.45M | 0U, // G_VECREDUCE_XOR |
5426 | 1.45M | 0U, // G_VECREDUCE_SMAX |
5427 | 1.45M | 0U, // G_VECREDUCE_SMIN |
5428 | 1.45M | 0U, // G_VECREDUCE_UMAX |
5429 | 1.45M | 0U, // G_VECREDUCE_UMIN |
5430 | 1.45M | 0U, // G_SBFX |
5431 | 1.45M | 0U, // G_UBFX |
5432 | 1.45M | 0U, // ABS |
5433 | 1.45M | 0U, // ADDSri |
5434 | 1.45M | 0U, // ADDSrr |
5435 | 1.45M | 0U, // ADDSrsi |
5436 | 1.45M | 0U, // ADDSrsr |
5437 | 1.45M | 0U, // ADJCALLSTACKDOWN |
5438 | 1.45M | 0U, // ADJCALLSTACKUP |
5439 | 1.45M | 0U, // ASRi |
5440 | 1.45M | 0U, // ASRr |
5441 | 1.45M | 0U, // B |
5442 | 1.45M | 0U, // BCCZi64 |
5443 | 1.45M | 0U, // BCCi64 |
5444 | 1.45M | 0U, // BLX_noip |
5445 | 1.45M | 0U, // BLX_pred_noip |
5446 | 1.45M | 0U, // BL_PUSHLR |
5447 | 1.45M | 0U, // BMOVPCB_CALL |
5448 | 1.45M | 0U, // BMOVPCRX_CALL |
5449 | 1.45M | 0U, // BR_JTadd |
5450 | 1.45M | 0U, // BR_JTm_i12 |
5451 | 1.45M | 0U, // BR_JTm_rs |
5452 | 1.45M | 0U, // BR_JTr |
5453 | 1.45M | 0U, // BX_CALL |
5454 | 1.45M | 0U, // CMP_SWAP_16 |
5455 | 1.45M | 0U, // CMP_SWAP_32 |
5456 | 1.45M | 0U, // CMP_SWAP_64 |
5457 | 1.45M | 0U, // CMP_SWAP_8 |
5458 | 1.45M | 0U, // CONSTPOOL_ENTRY |
5459 | 1.45M | 0U, // COPY_STRUCT_BYVAL_I32 |
5460 | 1.45M | 0U, // ITasm |
5461 | 1.45M | 0U, // Int_eh_sjlj_dispatchsetup |
5462 | 1.45M | 0U, // Int_eh_sjlj_longjmp |
5463 | 1.45M | 0U, // Int_eh_sjlj_setjmp |
5464 | 1.45M | 0U, // Int_eh_sjlj_setjmp_nofp |
5465 | 1.45M | 0U, // Int_eh_sjlj_setup_dispatch |
5466 | 1.45M | 0U, // JUMPTABLE_ADDRS |
5467 | 1.45M | 0U, // JUMPTABLE_INSTS |
5468 | 1.45M | 0U, // JUMPTABLE_TBB |
5469 | 1.45M | 0U, // JUMPTABLE_TBH |
5470 | 1.45M | 0U, // LDMIA_RET |
5471 | 1.45M | 128U, // LDRBT_POST |
5472 | 1.45M | 16384U, // LDRConstPool |
5473 | 1.45M | 128U, // LDRHTii |
5474 | 1.45M | 0U, // LDRLIT_ga_abs |
5475 | 1.45M | 0U, // LDRLIT_ga_pcrel |
5476 | 1.45M | 0U, // LDRLIT_ga_pcrel_ldr |
5477 | 1.45M | 128U, // LDRSBTii |
5478 | 1.45M | 128U, // LDRSHTii |
5479 | 1.45M | 128U, // LDRT_POST |
5480 | 1.45M | 0U, // LEApcrel |
5481 | 1.45M | 0U, // LEApcrelJT |
5482 | 1.45M | 0U, // LOADDUAL |
5483 | 1.45M | 0U, // LSLi |
5484 | 1.45M | 0U, // LSLr |
5485 | 1.45M | 0U, // LSRi |
5486 | 1.45M | 0U, // LSRr |
5487 | 1.45M | 0U, // MEMCPY |
5488 | 1.45M | 0U, // MLAv5 |
5489 | 1.45M | 0U, // MOVCCi |
5490 | 1.45M | 0U, // MOVCCi16 |
5491 | 1.45M | 0U, // MOVCCi32imm |
5492 | 1.45M | 0U, // MOVCCr |
5493 | 1.45M | 0U, // MOVCCsi |
5494 | 1.45M | 0U, // MOVCCsr |
5495 | 1.45M | 0U, // MOVPCRX |
5496 | 1.45M | 0U, // MOVTi16_ga_pcrel |
5497 | 1.45M | 0U, // MOV_ga_pcrel |
5498 | 1.45M | 0U, // MOV_ga_pcrel_ldr |
5499 | 1.45M | 0U, // MOVi16_ga_pcrel |
5500 | 1.45M | 0U, // MOVi32imm |
5501 | 1.45M | 0U, // MOVsra_flag |
5502 | 1.45M | 0U, // MOVsrl_flag |
5503 | 1.45M | 0U, // MQPRCopy |
5504 | 1.45M | 0U, // MQQPRLoad |
5505 | 1.45M | 0U, // MQQPRStore |
5506 | 1.45M | 0U, // MQQQQPRLoad |
5507 | 1.45M | 0U, // MQQQQPRStore |
5508 | 1.45M | 0U, // MULv5 |
5509 | 1.45M | 0U, // MVE_MEMCPYLOOPINST |
5510 | 1.45M | 0U, // MVE_MEMSETLOOPINST |
5511 | 1.45M | 0U, // MVNCCi |
5512 | 1.45M | 0U, // PICADD |
5513 | 1.45M | 0U, // PICLDR |
5514 | 1.45M | 0U, // PICLDRB |
5515 | 1.45M | 0U, // PICLDRH |
5516 | 1.45M | 0U, // PICLDRSB |
5517 | 1.45M | 0U, // PICLDRSH |
5518 | 1.45M | 0U, // PICSTR |
5519 | 1.45M | 0U, // PICSTRB |
5520 | 1.45M | 0U, // PICSTRH |
5521 | 1.45M | 0U, // RORi |
5522 | 1.45M | 0U, // RORr |
5523 | 1.45M | 0U, // RRX |
5524 | 1.45M | 16384U, // RRXi |
5525 | 1.45M | 0U, // RSBSri |
5526 | 1.45M | 0U, // RSBSrsi |
5527 | 1.45M | 0U, // RSBSrsr |
5528 | 1.45M | 0U, // SEH_EpilogEnd |
5529 | 1.45M | 0U, // SEH_EpilogStart |
5530 | 1.45M | 0U, // SEH_Nop |
5531 | 1.45M | 0U, // SEH_Nop_Ret |
5532 | 1.45M | 0U, // SEH_PrologEnd |
5533 | 1.45M | 0U, // SEH_SaveFRegs |
5534 | 1.45M | 0U, // SEH_SaveLR |
5535 | 1.45M | 0U, // SEH_SaveRegs |
5536 | 1.45M | 0U, // SEH_SaveRegs_Ret |
5537 | 1.45M | 0U, // SEH_SaveSP |
5538 | 1.45M | 0U, // SEH_StackAlloc |
5539 | 1.45M | 0U, // SMLALv5 |
5540 | 1.45M | 0U, // SMULLv5 |
5541 | 1.45M | 0U, // SPACE |
5542 | 1.45M | 0U, // STOREDUAL |
5543 | 1.45M | 128U, // STRBT_POST |
5544 | 1.45M | 0U, // STRBi_preidx |
5545 | 1.45M | 0U, // STRBr_preidx |
5546 | 1.45M | 0U, // STRH_preidx |
5547 | 1.45M | 128U, // STRT_POST |
5548 | 1.45M | 0U, // STRi_preidx |
5549 | 1.45M | 0U, // STRr_preidx |
5550 | 1.45M | 0U, // SUBS_PC_LR |
5551 | 1.45M | 0U, // SUBSri |
5552 | 1.45M | 0U, // SUBSrr |
5553 | 1.45M | 0U, // SUBSrsi |
5554 | 1.45M | 0U, // SUBSrsr |
5555 | 1.45M | 0U, // SpeculationBarrierISBDSBEndBB |
5556 | 1.45M | 0U, // SpeculationBarrierSBEndBB |
5557 | 1.45M | 0U, // TAILJMPd |
5558 | 1.45M | 0U, // TAILJMPr |
5559 | 1.45M | 0U, // TAILJMPr4 |
5560 | 1.45M | 0U, // TCRETURNdi |
5561 | 1.45M | 0U, // TCRETURNri |
5562 | 1.45M | 0U, // TPsoft |
5563 | 1.45M | 0U, // UMLALv5 |
5564 | 1.45M | 0U, // UMULLv5 |
5565 | 1.45M | 16640U, // VLD1LNdAsm_16 |
5566 | 1.45M | 16640U, // VLD1LNdAsm_32 |
5567 | 1.45M | 16640U, // VLD1LNdAsm_8 |
5568 | 1.45M | 33024U, // VLD1LNdWB_fixed_Asm_16 |
5569 | 1.45M | 33024U, // VLD1LNdWB_fixed_Asm_32 |
5570 | 1.45M | 33024U, // VLD1LNdWB_fixed_Asm_8 |
5571 | 1.45M | 524544U, // VLD1LNdWB_register_Asm_16 |
5572 | 1.45M | 524544U, // VLD1LNdWB_register_Asm_32 |
5573 | 1.45M | 524544U, // VLD1LNdWB_register_Asm_8 |
5574 | 1.45M | 16640U, // VLD2LNdAsm_16 |
5575 | 1.45M | 16640U, // VLD2LNdAsm_32 |
5576 | 1.45M | 16640U, // VLD2LNdAsm_8 |
5577 | 1.45M | 33024U, // VLD2LNdWB_fixed_Asm_16 |
5578 | 1.45M | 33024U, // VLD2LNdWB_fixed_Asm_32 |
5579 | 1.45M | 33024U, // VLD2LNdWB_fixed_Asm_8 |
5580 | 1.45M | 524544U, // VLD2LNdWB_register_Asm_16 |
5581 | 1.45M | 524544U, // VLD2LNdWB_register_Asm_32 |
5582 | 1.45M | 524544U, // VLD2LNdWB_register_Asm_8 |
5583 | 1.45M | 16640U, // VLD2LNqAsm_16 |
5584 | 1.45M | 16640U, // VLD2LNqAsm_32 |
5585 | 1.45M | 33024U, // VLD2LNqWB_fixed_Asm_16 |
5586 | 1.45M | 33024U, // VLD2LNqWB_fixed_Asm_32 |
5587 | 1.45M | 524544U, // VLD2LNqWB_register_Asm_16 |
5588 | 1.45M | 524544U, // VLD2LNqWB_register_Asm_32 |
5589 | 1.45M | 2U, // VLD3DUPdAsm_16 |
5590 | 1.45M | 2U, // VLD3DUPdAsm_32 |
5591 | 1.45M | 2U, // VLD3DUPdAsm_8 |
5592 | 1.45M | 4U, // VLD3DUPdWB_fixed_Asm_16 |
5593 | 1.45M | 4U, // VLD3DUPdWB_fixed_Asm_32 |
5594 | 1.45M | 4U, // VLD3DUPdWB_fixed_Asm_8 |
5595 | 1.45M | 16768U, // VLD3DUPdWB_register_Asm_16 |
5596 | 1.45M | 16768U, // VLD3DUPdWB_register_Asm_32 |
5597 | 1.45M | 16768U, // VLD3DUPdWB_register_Asm_8 |
5598 | 1.45M | 2U, // VLD3DUPqAsm_16 |
5599 | 1.45M | 2U, // VLD3DUPqAsm_32 |
5600 | 1.45M | 2U, // VLD3DUPqAsm_8 |
5601 | 1.45M | 4U, // VLD3DUPqWB_fixed_Asm_16 |
5602 | 1.45M | 4U, // VLD3DUPqWB_fixed_Asm_32 |
5603 | 1.45M | 4U, // VLD3DUPqWB_fixed_Asm_8 |
5604 | 1.45M | 16768U, // VLD3DUPqWB_register_Asm_16 |
5605 | 1.45M | 16768U, // VLD3DUPqWB_register_Asm_32 |
5606 | 1.45M | 16768U, // VLD3DUPqWB_register_Asm_8 |
5607 | 1.45M | 16640U, // VLD3LNdAsm_16 |
5608 | 1.45M | 16640U, // VLD3LNdAsm_32 |
5609 | 1.45M | 16640U, // VLD3LNdAsm_8 |
5610 | 1.45M | 33024U, // VLD3LNdWB_fixed_Asm_16 |
5611 | 1.45M | 33024U, // VLD3LNdWB_fixed_Asm_32 |
5612 | 1.45M | 33024U, // VLD3LNdWB_fixed_Asm_8 |
5613 | 1.45M | 524544U, // VLD3LNdWB_register_Asm_16 |
5614 | 1.45M | 524544U, // VLD3LNdWB_register_Asm_32 |
5615 | 1.45M | 524544U, // VLD3LNdWB_register_Asm_8 |
5616 | 1.45M | 16640U, // VLD3LNqAsm_16 |
5617 | 1.45M | 16640U, // VLD3LNqAsm_32 |
5618 | 1.45M | 33024U, // VLD3LNqWB_fixed_Asm_16 |
5619 | 1.45M | 33024U, // VLD3LNqWB_fixed_Asm_32 |
5620 | 1.45M | 524544U, // VLD3LNqWB_register_Asm_16 |
5621 | 1.45M | 524544U, // VLD3LNqWB_register_Asm_32 |
5622 | 1.45M | 518U, // VLD3dAsm_16 |
5623 | 1.45M | 518U, // VLD3dAsm_32 |
5624 | 1.45M | 518U, // VLD3dAsm_8 |
5625 | 1.45M | 646U, // VLD3dWB_fixed_Asm_16 |
5626 | 1.45M | 646U, // VLD3dWB_fixed_Asm_32 |
5627 | 1.45M | 646U, // VLD3dWB_fixed_Asm_8 |
5628 | 1.45M | 49926U, // VLD3dWB_register_Asm_16 |
5629 | 1.45M | 49926U, // VLD3dWB_register_Asm_32 |
5630 | 1.45M | 49926U, // VLD3dWB_register_Asm_8 |
5631 | 1.45M | 2U, // VLD3qAsm_16 |
5632 | 1.45M | 2U, // VLD3qAsm_32 |
5633 | 1.45M | 2U, // VLD3qAsm_8 |
5634 | 1.45M | 4U, // VLD3qWB_fixed_Asm_16 |
5635 | 1.45M | 4U, // VLD3qWB_fixed_Asm_32 |
5636 | 1.45M | 4U, // VLD3qWB_fixed_Asm_8 |
5637 | 1.45M | 16768U, // VLD3qWB_register_Asm_16 |
5638 | 1.45M | 16768U, // VLD3qWB_register_Asm_32 |
5639 | 1.45M | 16768U, // VLD3qWB_register_Asm_8 |
5640 | 1.45M | 2U, // VLD4DUPdAsm_16 |
5641 | 1.45M | 2U, // VLD4DUPdAsm_32 |
5642 | 1.45M | 2U, // VLD4DUPdAsm_8 |
5643 | 1.45M | 4U, // VLD4DUPdWB_fixed_Asm_16 |
5644 | 1.45M | 4U, // VLD4DUPdWB_fixed_Asm_32 |
5645 | 1.45M | 4U, // VLD4DUPdWB_fixed_Asm_8 |
5646 | 1.45M | 16768U, // VLD4DUPdWB_register_Asm_16 |
5647 | 1.45M | 16768U, // VLD4DUPdWB_register_Asm_32 |
5648 | 1.45M | 16768U, // VLD4DUPdWB_register_Asm_8 |
5649 | 1.45M | 2U, // VLD4DUPqAsm_16 |
5650 | 1.45M | 2U, // VLD4DUPqAsm_32 |
5651 | 1.45M | 2U, // VLD4DUPqAsm_8 |
5652 | 1.45M | 4U, // VLD4DUPqWB_fixed_Asm_16 |
5653 | 1.45M | 4U, // VLD4DUPqWB_fixed_Asm_32 |
5654 | 1.45M | 4U, // VLD4DUPqWB_fixed_Asm_8 |
5655 | 1.45M | 16768U, // VLD4DUPqWB_register_Asm_16 |
5656 | 1.45M | 16768U, // VLD4DUPqWB_register_Asm_32 |
5657 | 1.45M | 16768U, // VLD4DUPqWB_register_Asm_8 |
5658 | 1.45M | 16640U, // VLD4LNdAsm_16 |
5659 | 1.45M | 16640U, // VLD4LNdAsm_32 |
5660 | 1.45M | 16640U, // VLD4LNdAsm_8 |
5661 | 1.45M | 33024U, // VLD4LNdWB_fixed_Asm_16 |
5662 | 1.45M | 33024U, // VLD4LNdWB_fixed_Asm_32 |
5663 | 1.45M | 33024U, // VLD4LNdWB_fixed_Asm_8 |
5664 | 1.45M | 524544U, // VLD4LNdWB_register_Asm_16 |
5665 | 1.45M | 524544U, // VLD4LNdWB_register_Asm_32 |
5666 | 1.45M | 524544U, // VLD4LNdWB_register_Asm_8 |
5667 | 1.45M | 16640U, // VLD4LNqAsm_16 |
5668 | 1.45M | 16640U, // VLD4LNqAsm_32 |
5669 | 1.45M | 33024U, // VLD4LNqWB_fixed_Asm_16 |
5670 | 1.45M | 33024U, // VLD4LNqWB_fixed_Asm_32 |
5671 | 1.45M | 524544U, // VLD4LNqWB_register_Asm_16 |
5672 | 1.45M | 524544U, // VLD4LNqWB_register_Asm_32 |
5673 | 1.45M | 518U, // VLD4dAsm_16 |
5674 | 1.45M | 518U, // VLD4dAsm_32 |
5675 | 1.45M | 518U, // VLD4dAsm_8 |
5676 | 1.45M | 646U, // VLD4dWB_fixed_Asm_16 |
5677 | 1.45M | 646U, // VLD4dWB_fixed_Asm_32 |
5678 | 1.45M | 646U, // VLD4dWB_fixed_Asm_8 |
5679 | 1.45M | 49926U, // VLD4dWB_register_Asm_16 |
5680 | 1.45M | 49926U, // VLD4dWB_register_Asm_32 |
5681 | 1.45M | 49926U, // VLD4dWB_register_Asm_8 |
5682 | 1.45M | 2U, // VLD4qAsm_16 |
5683 | 1.45M | 2U, // VLD4qAsm_32 |
5684 | 1.45M | 2U, // VLD4qAsm_8 |
5685 | 1.45M | 4U, // VLD4qWB_fixed_Asm_16 |
5686 | 1.45M | 4U, // VLD4qWB_fixed_Asm_32 |
5687 | 1.45M | 4U, // VLD4qWB_fixed_Asm_8 |
5688 | 1.45M | 16768U, // VLD4qWB_register_Asm_16 |
5689 | 1.45M | 16768U, // VLD4qWB_register_Asm_32 |
5690 | 1.45M | 16768U, // VLD4qWB_register_Asm_8 |
5691 | 1.45M | 0U, // VMOVD0 |
5692 | 1.45M | 0U, // VMOVDcc |
5693 | 1.45M | 0U, // VMOVHcc |
5694 | 1.45M | 0U, // VMOVQ0 |
5695 | 1.45M | 0U, // VMOVScc |
5696 | 1.45M | 16640U, // VST1LNdAsm_16 |
5697 | 1.45M | 16640U, // VST1LNdAsm_32 |
5698 | 1.45M | 16640U, // VST1LNdAsm_8 |
5699 | 1.45M | 33024U, // VST1LNdWB_fixed_Asm_16 |
5700 | 1.45M | 33024U, // VST1LNdWB_fixed_Asm_32 |
5701 | 1.45M | 33024U, // VST1LNdWB_fixed_Asm_8 |
5702 | 1.45M | 524544U, // VST1LNdWB_register_Asm_16 |
5703 | 1.45M | 524544U, // VST1LNdWB_register_Asm_32 |
5704 | 1.45M | 524544U, // VST1LNdWB_register_Asm_8 |
5705 | 1.45M | 16640U, // VST2LNdAsm_16 |
5706 | 1.45M | 16640U, // VST2LNdAsm_32 |
5707 | 1.45M | 16640U, // VST2LNdAsm_8 |
5708 | 1.45M | 33024U, // VST2LNdWB_fixed_Asm_16 |
5709 | 1.45M | 33024U, // VST2LNdWB_fixed_Asm_32 |
5710 | 1.45M | 33024U, // VST2LNdWB_fixed_Asm_8 |
5711 | 1.45M | 524544U, // VST2LNdWB_register_Asm_16 |
5712 | 1.45M | 524544U, // VST2LNdWB_register_Asm_32 |
5713 | 1.45M | 524544U, // VST2LNdWB_register_Asm_8 |
5714 | 1.45M | 16640U, // VST2LNqAsm_16 |
5715 | 1.45M | 16640U, // VST2LNqAsm_32 |
5716 | 1.45M | 33024U, // VST2LNqWB_fixed_Asm_16 |
5717 | 1.45M | 33024U, // VST2LNqWB_fixed_Asm_32 |
5718 | 1.45M | 524544U, // VST2LNqWB_register_Asm_16 |
5719 | 1.45M | 524544U, // VST2LNqWB_register_Asm_32 |
5720 | 1.45M | 16640U, // VST3LNdAsm_16 |
5721 | 1.45M | 16640U, // VST3LNdAsm_32 |
5722 | 1.45M | 16640U, // VST3LNdAsm_8 |
5723 | 1.45M | 33024U, // VST3LNdWB_fixed_Asm_16 |
5724 | 1.45M | 33024U, // VST3LNdWB_fixed_Asm_32 |
5725 | 1.45M | 33024U, // VST3LNdWB_fixed_Asm_8 |
5726 | 1.45M | 524544U, // VST3LNdWB_register_Asm_16 |
5727 | 1.45M | 524544U, // VST3LNdWB_register_Asm_32 |
5728 | 1.45M | 524544U, // VST3LNdWB_register_Asm_8 |
5729 | 1.45M | 16640U, // VST3LNqAsm_16 |
5730 | 1.45M | 16640U, // VST3LNqAsm_32 |
5731 | 1.45M | 33024U, // VST3LNqWB_fixed_Asm_16 |
5732 | 1.45M | 33024U, // VST3LNqWB_fixed_Asm_32 |
5733 | 1.45M | 524544U, // VST3LNqWB_register_Asm_16 |
5734 | 1.45M | 524544U, // VST3LNqWB_register_Asm_32 |
5735 | 1.45M | 518U, // VST3dAsm_16 |
5736 | 1.45M | 518U, // VST3dAsm_32 |
5737 | 1.45M | 518U, // VST3dAsm_8 |
5738 | 1.45M | 646U, // VST3dWB_fixed_Asm_16 |
5739 | 1.45M | 646U, // VST3dWB_fixed_Asm_32 |
5740 | 1.45M | 646U, // VST3dWB_fixed_Asm_8 |
5741 | 1.45M | 49926U, // VST3dWB_register_Asm_16 |
5742 | 1.45M | 49926U, // VST3dWB_register_Asm_32 |
5743 | 1.45M | 49926U, // VST3dWB_register_Asm_8 |
5744 | 1.45M | 2U, // VST3qAsm_16 |
5745 | 1.45M | 2U, // VST3qAsm_32 |
5746 | 1.45M | 2U, // VST3qAsm_8 |
5747 | 1.45M | 4U, // VST3qWB_fixed_Asm_16 |
5748 | 1.45M | 4U, // VST3qWB_fixed_Asm_32 |
5749 | 1.45M | 4U, // VST3qWB_fixed_Asm_8 |
5750 | 1.45M | 16768U, // VST3qWB_register_Asm_16 |
5751 | 1.45M | 16768U, // VST3qWB_register_Asm_32 |
5752 | 1.45M | 16768U, // VST3qWB_register_Asm_8 |
5753 | 1.45M | 16640U, // VST4LNdAsm_16 |
5754 | 1.45M | 16640U, // VST4LNdAsm_32 |
5755 | 1.45M | 16640U, // VST4LNdAsm_8 |
5756 | 1.45M | 33024U, // VST4LNdWB_fixed_Asm_16 |
5757 | 1.45M | 33024U, // VST4LNdWB_fixed_Asm_32 |
5758 | 1.45M | 33024U, // VST4LNdWB_fixed_Asm_8 |
5759 | 1.45M | 524544U, // VST4LNdWB_register_Asm_16 |
5760 | 1.45M | 524544U, // VST4LNdWB_register_Asm_32 |
5761 | 1.45M | 524544U, // VST4LNdWB_register_Asm_8 |
5762 | 1.45M | 16640U, // VST4LNqAsm_16 |
5763 | 1.45M | 16640U, // VST4LNqAsm_32 |
5764 | 1.45M | 33024U, // VST4LNqWB_fixed_Asm_16 |
5765 | 1.45M | 33024U, // VST4LNqWB_fixed_Asm_32 |
5766 | 1.45M | 524544U, // VST4LNqWB_register_Asm_16 |
5767 | 1.45M | 524544U, // VST4LNqWB_register_Asm_32 |
5768 | 1.45M | 518U, // VST4dAsm_16 |
5769 | 1.45M | 518U, // VST4dAsm_32 |
5770 | 1.45M | 518U, // VST4dAsm_8 |
5771 | 1.45M | 646U, // VST4dWB_fixed_Asm_16 |
5772 | 1.45M | 646U, // VST4dWB_fixed_Asm_32 |
5773 | 1.45M | 646U, // VST4dWB_fixed_Asm_8 |
5774 | 1.45M | 49926U, // VST4dWB_register_Asm_16 |
5775 | 1.45M | 49926U, // VST4dWB_register_Asm_32 |
5776 | 1.45M | 49926U, // VST4dWB_register_Asm_8 |
5777 | 1.45M | 2U, // VST4qAsm_16 |
5778 | 1.45M | 2U, // VST4qAsm_32 |
5779 | 1.45M | 2U, // VST4qAsm_8 |
5780 | 1.45M | 4U, // VST4qWB_fixed_Asm_16 |
5781 | 1.45M | 4U, // VST4qWB_fixed_Asm_32 |
5782 | 1.45M | 4U, // VST4qWB_fixed_Asm_8 |
5783 | 1.45M | 16768U, // VST4qWB_register_Asm_16 |
5784 | 1.45M | 16768U, // VST4qWB_register_Asm_32 |
5785 | 1.45M | 16768U, // VST4qWB_register_Asm_8 |
5786 | 1.45M | 0U, // WIN__CHKSTK |
5787 | 1.45M | 0U, // WIN__DBZCHK |
5788 | 1.45M | 0U, // t2ABS |
5789 | 1.45M | 0U, // t2ADDSri |
5790 | 1.45M | 0U, // t2ADDSrr |
5791 | 1.45M | 0U, // t2ADDSrs |
5792 | 1.45M | 0U, // t2BF_LabelPseudo |
5793 | 1.45M | 0U, // t2BR_JT |
5794 | 1.45M | 0U, // t2CALL_BTI |
5795 | 1.45M | 0U, // t2DoLoopStart |
5796 | 1.45M | 0U, // t2DoLoopStartTP |
5797 | 1.45M | 0U, // t2LDMIA_RET |
5798 | 1.45M | 16384U, // t2LDRBpcrel |
5799 | 1.45M | 16384U, // t2LDRConstPool |
5800 | 1.45M | 16384U, // t2LDRHpcrel |
5801 | 1.45M | 0U, // t2LDRLIT_ga_pcrel |
5802 | 1.45M | 16384U, // t2LDRSBpcrel |
5803 | 1.45M | 16384U, // t2LDRSHpcrel |
5804 | 1.45M | 896U, // t2LDR_POST_imm |
5805 | 1.45M | 0U, // t2LDR_PRE_imm |
5806 | 1.45M | 0U, // t2LDRpci_pic |
5807 | 1.45M | 16384U, // t2LDRpcrel |
5808 | 1.45M | 0U, // t2LEApcrel |
5809 | 1.45M | 0U, // t2LEApcrelJT |
5810 | 1.45M | 0U, // t2LoopDec |
5811 | 1.45M | 0U, // t2LoopEnd |
5812 | 1.45M | 0U, // t2LoopEndDec |
5813 | 1.45M | 0U, // t2MOVCCasr |
5814 | 1.45M | 0U, // t2MOVCCi |
5815 | 1.45M | 0U, // t2MOVCCi16 |
5816 | 1.45M | 0U, // t2MOVCCi32imm |
5817 | 1.45M | 0U, // t2MOVCClsl |
5818 | 1.45M | 0U, // t2MOVCClsr |
5819 | 1.45M | 0U, // t2MOVCCr |
5820 | 1.45M | 0U, // t2MOVCCror |
5821 | 1.45M | 1024U, // t2MOVSsi |
5822 | 1.45M | 1152U, // t2MOVSsr |
5823 | 1.45M | 0U, // t2MOVTi16_ga_pcrel |
5824 | 1.45M | 0U, // t2MOV_ga_pcrel |
5825 | 1.45M | 0U, // t2MOVi16_ga_pcrel |
5826 | 1.45M | 0U, // t2MOVi32imm |
5827 | 1.45M | 1024U, // t2MOVsi |
5828 | 1.45M | 1152U, // t2MOVsr |
5829 | 1.45M | 0U, // t2MVNCCi |
5830 | 1.45M | 0U, // t2RSBSri |
5831 | 1.45M | 0U, // t2RSBSrs |
5832 | 1.45M | 0U, // t2STRB_preidx |
5833 | 1.45M | 0U, // t2STRH_preidx |
5834 | 1.45M | 896U, // t2STR_POST_imm |
5835 | 1.45M | 0U, // t2STR_PRE_imm |
5836 | 1.45M | 0U, // t2STR_preidx |
5837 | 1.45M | 0U, // t2SUBSri |
5838 | 1.45M | 0U, // t2SUBSrr |
5839 | 1.45M | 0U, // t2SUBSrs |
5840 | 1.45M | 0U, // t2SpeculationBarrierISBDSBEndBB |
5841 | 1.45M | 0U, // t2SpeculationBarrierSBEndBB |
5842 | 1.45M | 0U, // t2TBB_JT |
5843 | 1.45M | 0U, // t2TBH_JT |
5844 | 1.45M | 0U, // t2WhileLoopSetup |
5845 | 1.45M | 0U, // t2WhileLoopStart |
5846 | 1.45M | 0U, // t2WhileLoopStartLR |
5847 | 1.45M | 0U, // t2WhileLoopStartTP |
5848 | 1.45M | 0U, // tADCS |
5849 | 1.45M | 0U, // tADDSi3 |
5850 | 1.45M | 0U, // tADDSi8 |
5851 | 1.45M | 0U, // tADDSrr |
5852 | 1.45M | 0U, // tADDframe |
5853 | 1.45M | 0U, // tADJCALLSTACKDOWN |
5854 | 1.45M | 0U, // tADJCALLSTACKUP |
5855 | 1.45M | 0U, // tBLXNS_CALL |
5856 | 1.45M | 0U, // tBLXr_noip |
5857 | 1.45M | 0U, // tBL_PUSHLR |
5858 | 1.45M | 0U, // tBRIND |
5859 | 1.45M | 0U, // tBR_JTr |
5860 | 1.45M | 0U, // tBXNS_RET |
5861 | 1.45M | 0U, // tBX_CALL |
5862 | 1.45M | 0U, // tBX_RET |
5863 | 1.45M | 0U, // tBX_RET_vararg |
5864 | 1.45M | 0U, // tBfar |
5865 | 1.45M | 0U, // tCMP_SWAP_16 |
5866 | 1.45M | 0U, // tCMP_SWAP_32 |
5867 | 1.45M | 0U, // tCMP_SWAP_8 |
5868 | 1.45M | 0U, // tLDMIA_UPD |
5869 | 1.45M | 16384U, // tLDRConstPool |
5870 | 1.45M | 0U, // tLDRLIT_ga_abs |
5871 | 1.45M | 0U, // tLDRLIT_ga_pcrel |
5872 | 1.45M | 0U, // tLDR_postidx |
5873 | 1.45M | 0U, // tLDRpci_pic |
5874 | 1.45M | 0U, // tLEApcrel |
5875 | 1.45M | 0U, // tLEApcrelJT |
5876 | 1.45M | 0U, // tLSLSri |
5877 | 1.45M | 0U, // tMOVCCr_pseudo |
5878 | 1.45M | 0U, // tPOP_RET |
5879 | 1.45M | 0U, // tRSBS |
5880 | 1.45M | 0U, // tSBCS |
5881 | 1.45M | 0U, // tSUBSi3 |
5882 | 1.45M | 0U, // tSUBSi8 |
5883 | 1.45M | 0U, // tSUBSrr |
5884 | 1.45M | 0U, // tTAILJMPd |
5885 | 1.45M | 0U, // tTAILJMPdND |
5886 | 1.45M | 0U, // tTAILJMPr |
5887 | 1.45M | 0U, // tTBB_JT |
5888 | 1.45M | 0U, // tTBH_JT |
5889 | 1.45M | 0U, // tTPsoft |
5890 | 1.45M | 1048576U, // ADCri |
5891 | 1.45M | 0U, // ADCrr |
5892 | 1.45M | 1572864U, // ADCrsi |
5893 | 1.45M | 0U, // ADCrsr |
5894 | 1.45M | 1048576U, // ADDri |
5895 | 1.45M | 0U, // ADDrr |
5896 | 1.45M | 1572864U, // ADDrsi |
5897 | 1.45M | 0U, // ADDrsr |
5898 | 1.45M | 1280U, // ADR |
5899 | 1.45M | 2U, // AESD |
5900 | 1.45M | 2U, // AESE |
5901 | 1.45M | 2U, // AESIMC |
5902 | 1.45M | 2U, // AESMC |
5903 | 1.45M | 1048576U, // ANDri |
5904 | 1.45M | 0U, // ANDrr |
5905 | 1.45M | 1572864U, // ANDrsi |
5906 | 1.45M | 0U, // ANDrsr |
5907 | 1.45M | 2163072U, // BF16VDOTI_VDOTD |
5908 | 1.45M | 2163072U, // BF16VDOTI_VDOTQ |
5909 | 1.45M | 16768U, // BF16VDOTS_VDOTD |
5910 | 1.45M | 16768U, // BF16VDOTS_VDOTQ |
5911 | 1.45M | 2U, // BF16_VCVT |
5912 | 1.45M | 2U, // BF16_VCVTB |
5913 | 1.45M | 2U, // BF16_VCVTT |
5914 | 1.45M | 1408U, // BFC |
5915 | 1.45M | 2622976U, // BFI |
5916 | 1.45M | 1048576U, // BICri |
5917 | 1.45M | 0U, // BICrr |
5918 | 1.45M | 1572864U, // BICrsi |
5919 | 1.45M | 0U, // BICrsr |
5920 | 1.45M | 0U, // BKPT |
5921 | 1.45M | 0U, // BL |
5922 | 1.45M | 0U, // BLX |
5923 | 1.45M | 2U, // BLX_pred |
5924 | 1.45M | 0U, // BLXi |
5925 | 1.45M | 2U, // BL_pred |
5926 | 1.45M | 0U, // BX |
5927 | 1.45M | 2U, // BXJ |
5928 | 1.45M | 0U, // BX_RET |
5929 | 1.45M | 2U, // BX_pred |
5930 | 1.45M | 2U, // Bcc |
5931 | 1.45M | 2U, // CDE_CX1 |
5932 | 1.45M | 16776U, // CDE_CX1A |
5933 | 1.45M | 0U, // CDE_CX1D |
5934 | 1.45M | 522U, // CDE_CX1DA |
5935 | 1.45M | 16768U, // CDE_CX2 |
5936 | 1.45M | 524680U, // CDE_CX2A |
5937 | 1.45M | 524U, // CDE_CX2D |
5938 | 1.45M | 2179850U, // CDE_CX2DA |
5939 | 1.45M | 524672U, // CDE_CX3 |
5940 | 1.45M | 34079112U, // CDE_CX3A |
5941 | 1.45M | 2179852U, // CDE_CX3D |
5942 | 1.45M | 70337290U, // CDE_CX3DA |
5943 | 1.45M | 2U, // CDE_VCX1A_fpdp |
5944 | 1.45M | 2U, // CDE_VCX1A_fpsp |
5945 | 1.45M | 16776U, // CDE_VCX1A_vec |
5946 | 1.45M | 2U, // CDE_VCX1_fpdp |
5947 | 1.45M | 2U, // CDE_VCX1_fpsp |
5948 | 1.45M | 17928U, // CDE_VCX1_vec |
5949 | 1.45M | 18048U, // CDE_VCX2A_fpdp |
5950 | 1.45M | 18048U, // CDE_VCX2A_fpsp |
5951 | 1.45M | 524680U, // CDE_VCX2A_vec |
5952 | 1.45M | 16768U, // CDE_VCX2_fpdp |
5953 | 1.45M | 16768U, // CDE_VCX2_fpsp |
5954 | 1.45M | 3671560U, // CDE_VCX2_vec |
5955 | 1.45M | 4195968U, // CDE_VCX3A_fpdp |
5956 | 1.45M | 4195968U, // CDE_VCX3A_fpsp |
5957 | 1.45M | 34079112U, // CDE_VCX3A_vec |
5958 | 1.45M | 524672U, // CDE_VCX3_fpdp |
5959 | 1.45M | 524672U, // CDE_VCX3_fpsp |
5960 | 1.45M | 37225992U, // CDE_VCX3_vec |
5961 | 1.45M | 99086U, // CDP |
5962 | 1.45M | 0U, // CDP2 |
5963 | 1.45M | 0U, // CLREX |
5964 | 1.45M | 16384U, // CLZ |
5965 | 1.45M | 1792U, // CMNri |
5966 | 1.45M | 16384U, // CMNzrr |
5967 | 1.45M | 1920U, // CMNzrsi |
5968 | 1.45M | 1152U, // CMNzrsr |
5969 | 1.45M | 1792U, // CMPri |
5970 | 1.45M | 16384U, // CMPrr |
5971 | 1.45M | 1920U, // CMPrsi |
5972 | 1.45M | 1152U, // CMPrsr |
5973 | 1.45M | 0U, // CPS1p |
5974 | 1.45M | 2U, // CPS2p |
5975 | 1.45M | 17920U, // CPS3p |
5976 | 1.45M | 17920U, // CRC32B |
5977 | 1.45M | 17920U, // CRC32CB |
5978 | 1.45M | 17920U, // CRC32CH |
5979 | 1.45M | 17920U, // CRC32CW |
5980 | 1.45M | 17920U, // CRC32H |
5981 | 1.45M | 17920U, // CRC32W |
5982 | 1.45M | 2U, // DBG |
5983 | 1.45M | 0U, // DMB |
5984 | 1.45M | 0U, // DSB |
5985 | 1.45M | 1048576U, // EORri |
5986 | 1.45M | 0U, // EORrr |
5987 | 1.45M | 1572864U, // EORrsi |
5988 | 1.45M | 0U, // EORrsr |
5989 | 1.45M | 0U, // ERET |
5990 | 1.45M | 16U, // FCONSTD |
5991 | 1.45M | 2048U, // FCONSTH |
5992 | 1.45M | 2048U, // FCONSTS |
5993 | 1.45M | 530U, // FLDMXDB_UPD |
5994 | 1.45M | 18560U, // FLDMXIA |
5995 | 1.45M | 530U, // FLDMXIA_UPD |
5996 | 1.45M | 0U, // FMSTAT |
5997 | 1.45M | 530U, // FSTMXDB_UPD |
5998 | 1.45M | 18560U, // FSTMXIA |
5999 | 1.45M | 530U, // FSTMXIA_UPD |
6000 | 1.45M | 2U, // HINT |
6001 | 1.45M | 0U, // HLT |
6002 | 1.45M | 0U, // HVC |
6003 | 1.45M | 0U, // ISB |
6004 | 1.45M | 128U, // LDA |
6005 | 1.45M | 128U, // LDAB |
6006 | 1.45M | 128U, // LDAEX |
6007 | 1.45M | 128U, // LDAEXB |
6008 | 1.45M | 0U, // LDAEXD |
6009 | 1.45M | 128U, // LDAEXH |
6010 | 1.45M | 128U, // LDAH |
6011 | 1.45M | 0U, // LDC2L_OFFSET |
6012 | 1.45M | 2304U, // LDC2L_OPTION |
6013 | 1.45M | 2432U, // LDC2L_POST |
6014 | 1.45M | 0U, // LDC2L_PRE |
6015 | 1.45M | 0U, // LDC2_OFFSET |
6016 | 1.45M | 2304U, // LDC2_OPTION |
6017 | 1.45M | 2432U, // LDC2_POST |
6018 | 1.45M | 0U, // LDC2_PRE |
6019 | 1.45M | 2580U, // LDCL_OFFSET |
6020 | 1.45M | 4721300U, // LDCL_OPTION |
6021 | 1.45M | 5245588U, // LDCL_POST |
6022 | 1.45M | 22U, // LDCL_PRE |
6023 | 1.45M | 2580U, // LDC_OFFSET |
6024 | 1.45M | 4721300U, // LDC_OPTION |
6025 | 1.45M | 5245588U, // LDC_POST |
6026 | 1.45M | 22U, // LDC_PRE |
6027 | 1.45M | 18560U, // LDMDA |
6028 | 1.45M | 530U, // LDMDA_UPD |
6029 | 1.45M | 18560U, // LDMDB |
6030 | 1.45M | 530U, // LDMDB_UPD |
6031 | 1.45M | 18560U, // LDMIA |
6032 | 1.45M | 530U, // LDMIA_UPD |
6033 | 1.45M | 18560U, // LDMIB |
6034 | 1.45M | 530U, // LDMIB_UPD |
6035 | 1.45M | 5769856U, // LDRBT_POST_IMM |
6036 | 1.45M | 5769856U, // LDRBT_POST_REG |
6037 | 1.45M | 5769856U, // LDRB_POST_IMM |
6038 | 1.45M | 5769856U, // LDRB_POST_REG |
6039 | 1.45M | 2816U, // LDRB_PRE_IMM |
6040 | 1.45M | 2944U, // LDRB_PRE_REG |
6041 | 1.45M | 3072U, // LDRBi12 |
6042 | 1.45M | 3200U, // LDRBrs |
6043 | 1.45M | 6291456U, // LDRD |
6044 | 1.45M | 40370176U, // LDRD_POST |
6045 | 1.45M | 7340032U, // LDRD_PRE |
6046 | 1.45M | 128U, // LDREX |
6047 | 1.45M | 128U, // LDREXB |
6048 | 1.45M | 0U, // LDREXD |
6049 | 1.45M | 128U, // LDREXH |
6050 | 1.45M | 3328U, // LDRH |
6051 | 1.45M | 7867008U, // LDRHTi |
6052 | 1.45M | 8391296U, // LDRHTr |
6053 | 1.45M | 8915584U, // LDRH_POST |
6054 | 1.45M | 3456U, // LDRH_PRE |
6055 | 1.45M | 3328U, // LDRSB |
6056 | 1.45M | 7867008U, // LDRSBTi |
6057 | 1.45M | 8391296U, // LDRSBTr |
6058 | 1.45M | 8915584U, // LDRSB_POST |
6059 | 1.45M | 3456U, // LDRSB_PRE |
6060 | 1.45M | 3328U, // LDRSH |
6061 | 1.45M | 7867008U, // LDRSHTi |
6062 | 1.45M | 8391296U, // LDRSHTr |
6063 | 1.45M | 8915584U, // LDRSH_POST |
6064 | 1.45M | 3456U, // LDRSH_PRE |
6065 | 1.45M | 5769856U, // LDRT_POST_IMM |
6066 | 1.45M | 5769856U, // LDRT_POST_REG |
6067 | 1.45M | 5769856U, // LDR_POST_IMM |
6068 | 1.45M | 5769856U, // LDR_POST_REG |
6069 | 1.45M | 2816U, // LDR_PRE_IMM |
6070 | 1.45M | 2944U, // LDR_PRE_REG |
6071 | 1.45M | 3072U, // LDRcp |
6072 | 1.45M | 3072U, // LDRi12 |
6073 | 1.45M | 3200U, // LDRrs |
6074 | 1.45M | 103924494U, // MCR |
6075 | 1.45M | 3584U, // MCR2 |
6076 | 1.45M | 137478926U, // MCRR |
6077 | 1.45M | 9437568U, // MCRR2 |
6078 | 1.45M | 33554432U, // MLA |
6079 | 1.45M | 33554432U, // MLS |
6080 | 1.45M | 0U, // MOVPCLR |
6081 | 1.45M | 17920U, // MOVTi16 |
6082 | 1.45M | 1792U, // MOVi |
6083 | 1.45M | 16384U, // MOVi16 |
6084 | 1.45M | 16384U, // MOVr |
6085 | 1.45M | 16384U, // MOVr_TC |
6086 | 1.45M | 1920U, // MOVsi |
6087 | 1.45M | 1152U, // MOVsr |
6088 | 1.45M | 131864U, // MRC |
6089 | 1.45M | 0U, // MRC2 |
6090 | 1.45M | 0U, // MRRC |
6091 | 1.45M | 0U, // MRRC2 |
6092 | 1.45M | 26U, // MRS |
6093 | 1.45M | 3712U, // MRSbanked |
6094 | 1.45M | 28U, // MRSsys |
6095 | 1.45M | 526U, // MSR |
6096 | 1.45M | 0U, // MSRbanked |
6097 | 1.45M | 30U, // MSRi |
6098 | 1.45M | 0U, // MUL |
6099 | 1.45M | 524288U, // MVE_ASRLi |
6100 | 1.45M | 524288U, // MVE_ASRLr |
6101 | 1.45M | 2U, // MVE_DLSTP_16 |
6102 | 1.45M | 2U, // MVE_DLSTP_32 |
6103 | 1.45M | 2U, // MVE_DLSTP_64 |
6104 | 1.45M | 2U, // MVE_DLSTP_8 |
6105 | 1.45M | 0U, // MVE_LCTP |
6106 | 1.45M | 0U, // MVE_LETP |
6107 | 1.45M | 524288U, // MVE_LSLLi |
6108 | 1.45M | 524288U, // MVE_LSLLr |
6109 | 1.45M | 524288U, // MVE_LSRL |
6110 | 1.45M | 17920U, // MVE_SQRSHR |
6111 | 1.45M | 9961472U, // MVE_SQRSHRL |
6112 | 1.45M | 17920U, // MVE_SQSHL |
6113 | 1.45M | 524288U, // MVE_SQSHLL |
6114 | 1.45M | 17920U, // MVE_SRSHR |
6115 | 1.45M | 524288U, // MVE_SRSHRL |
6116 | 1.45M | 17920U, // MVE_UQRSHL |
6117 | 1.45M | 9961472U, // MVE_UQRSHLL |
6118 | 1.45M | 17920U, // MVE_UQSHL |
6119 | 1.45M | 524288U, // MVE_UQSHLL |
6120 | 1.45M | 17920U, // MVE_URSHR |
6121 | 1.45M | 524288U, // MVE_URSHRL |
6122 | 1.45M | 3671552U, // MVE_VABAVs16 |
6123 | 1.45M | 3671552U, // MVE_VABAVs32 |
6124 | 1.45M | 3671552U, // MVE_VABAVs8 |
6125 | 1.45M | 3671552U, // MVE_VABAVu16 |
6126 | 1.45M | 3671552U, // MVE_VABAVu32 |
6127 | 1.45M | 3671552U, // MVE_VABAVu8 |
6128 | 1.45M | 0U, // MVE_VABDf16 |
6129 | 1.45M | 0U, // MVE_VABDf32 |
6130 | 1.45M | 0U, // MVE_VABDs16 |
6131 | 1.45M | 0U, // MVE_VABDs32 |
6132 | 1.45M | 0U, // MVE_VABDs8 |
6133 | 1.45M | 0U, // MVE_VABDu16 |
6134 | 1.45M | 0U, // MVE_VABDu32 |
6135 | 1.45M | 0U, // MVE_VABDu8 |
6136 | 1.45M | 16384U, // MVE_VABSf16 |
6137 | 1.45M | 16384U, // MVE_VABSf32 |
6138 | 1.45M | 16384U, // MVE_VABSs16 |
6139 | 1.45M | 16384U, // MVE_VABSs32 |
6140 | 1.45M | 16384U, // MVE_VABSs8 |
6141 | 1.45M | 3671552U, // MVE_VADC |
6142 | 1.45M | 3671552U, // MVE_VADCI |
6143 | 1.45M | 524288U, // MVE_VADDLVs32acc |
6144 | 1.45M | 0U, // MVE_VADDLVs32no_acc |
6145 | 1.45M | 524288U, // MVE_VADDLVu32acc |
6146 | 1.45M | 0U, // MVE_VADDLVu32no_acc |
6147 | 1.45M | 17920U, // MVE_VADDVs16acc |
6148 | 1.45M | 16384U, // MVE_VADDVs16no_acc |
6149 | 1.45M | 17920U, // MVE_VADDVs32acc |
6150 | 1.45M | 16384U, // MVE_VADDVs32no_acc |
6151 | 1.45M | 17920U, // MVE_VADDVs8acc |
6152 | 1.45M | 16384U, // MVE_VADDVs8no_acc |
6153 | 1.45M | 17920U, // MVE_VADDVu16acc |
6154 | 1.45M | 16384U, // MVE_VADDVu16no_acc |
6155 | 1.45M | 17920U, // MVE_VADDVu32acc |
6156 | 1.45M | 16384U, // MVE_VADDVu32no_acc |
6157 | 1.45M | 17920U, // MVE_VADDVu8acc |
6158 | 1.45M | 16384U, // MVE_VADDVu8no_acc |
6159 | 1.45M | 0U, // MVE_VADD_qr_f16 |
6160 | 1.45M | 0U, // MVE_VADD_qr_f32 |
6161 | 1.45M | 0U, // MVE_VADD_qr_i16 |
6162 | 1.45M | 0U, // MVE_VADD_qr_i32 |
6163 | 1.45M | 0U, // MVE_VADD_qr_i8 |
6164 | 1.45M | 0U, // MVE_VADDf16 |
6165 | 1.45M | 0U, // MVE_VADDf32 |
6166 | 1.45M | 0U, // MVE_VADDi16 |
6167 | 1.45M | 0U, // MVE_VADDi32 |
6168 | 1.45M | 0U, // MVE_VADDi8 |
6169 | 1.45M | 0U, // MVE_VAND |
6170 | 1.45M | 0U, // MVE_VBIC |
6171 | 1.45M | 3840U, // MVE_VBICimmi16 |
6172 | 1.45M | 3840U, // MVE_VBICimmi32 |
6173 | 1.45M | 0U, // MVE_VBRSR16 |
6174 | 1.45M | 0U, // MVE_VBRSR32 |
6175 | 1.45M | 0U, // MVE_VBRSR8 |
6176 | 1.45M | 33554432U, // MVE_VCADDf16 |
6177 | 1.45M | 33554432U, // MVE_VCADDf32 |
6178 | 1.45M | 33554432U, // MVE_VCADDi16 |
6179 | 1.45M | 33554432U, // MVE_VCADDi32 |
6180 | 1.45M | 33554432U, // MVE_VCADDi8 |
6181 | 1.45M | 16384U, // MVE_VCLSs16 |
6182 | 1.45M | 16384U, // MVE_VCLSs32 |
6183 | 1.45M | 16384U, // MVE_VCLSs8 |
6184 | 1.45M | 16384U, // MVE_VCLZs16 |
6185 | 1.45M | 16384U, // MVE_VCLZs32 |
6186 | 1.45M | 16384U, // MVE_VCLZs8 |
6187 | 1.45M | 37225984U, // MVE_VCMLAf16 |
6188 | 1.45M | 37225984U, // MVE_VCMLAf32 |
6189 | 1.45M | 0U, // MVE_VCMPf16 |
6190 | 1.45M | 0U, // MVE_VCMPf16r |
6191 | 1.45M | 0U, // MVE_VCMPf32 |
6192 | 1.45M | 0U, // MVE_VCMPf32r |
6193 | 1.45M | 0U, // MVE_VCMPi16 |
6194 | 1.45M | 0U, // MVE_VCMPi16r |
6195 | 1.45M | 0U, // MVE_VCMPi32 |
6196 | 1.45M | 0U, // MVE_VCMPi32r |
6197 | 1.45M | 0U, // MVE_VCMPi8 |
6198 | 1.45M | 0U, // MVE_VCMPi8r |
6199 | 1.45M | 0U, // MVE_VCMPs16 |
6200 | 1.45M | 0U, // MVE_VCMPs16r |
6201 | 1.45M | 0U, // MVE_VCMPs32 |
6202 | 1.45M | 0U, // MVE_VCMPs32r |
6203 | 1.45M | 0U, // MVE_VCMPs8 |
6204 | 1.45M | 0U, // MVE_VCMPs8r |
6205 | 1.45M | 0U, // MVE_VCMPu16 |
6206 | 1.45M | 0U, // MVE_VCMPu16r |
6207 | 1.45M | 0U, // MVE_VCMPu32 |
6208 | 1.45M | 0U, // MVE_VCMPu32r |
6209 | 1.45M | 0U, // MVE_VCMPu8 |
6210 | 1.45M | 0U, // MVE_VCMPu8r |
6211 | 1.45M | 33554432U, // MVE_VCMULf16 |
6212 | 1.45M | 33554432U, // MVE_VCMULf32 |
6213 | 1.45M | 2U, // MVE_VCTP16 |
6214 | 1.45M | 2U, // MVE_VCTP32 |
6215 | 1.45M | 2U, // MVE_VCTP64 |
6216 | 1.45M | 2U, // MVE_VCTP8 |
6217 | 1.45M | 2U, // MVE_VCVTf16f32bh |
6218 | 1.45M | 2U, // MVE_VCVTf16f32th |
6219 | 1.45M | 536U, // MVE_VCVTf16s16_fix |
6220 | 1.45M | 0U, // MVE_VCVTf16s16n |
6221 | 1.45M | 536U, // MVE_VCVTf16u16_fix |
6222 | 1.45M | 0U, // MVE_VCVTf16u16n |
6223 | 1.45M | 0U, // MVE_VCVTf32f16bh |
6224 | 1.45M | 0U, // MVE_VCVTf32f16th |
6225 | 1.45M | 536U, // MVE_VCVTf32s32_fix |
6226 | 1.45M | 0U, // MVE_VCVTf32s32n |
6227 | 1.45M | 536U, // MVE_VCVTf32u32_fix |
6228 | 1.45M | 0U, // MVE_VCVTf32u32n |
6229 | 1.45M | 536U, // MVE_VCVTs16f16_fix |
6230 | 1.45M | 0U, // MVE_VCVTs16f16a |
6231 | 1.45M | 0U, // MVE_VCVTs16f16m |
6232 | 1.45M | 0U, // MVE_VCVTs16f16n |
6233 | 1.45M | 0U, // MVE_VCVTs16f16p |
6234 | 1.45M | 0U, // MVE_VCVTs16f16z |
6235 | 1.45M | 536U, // MVE_VCVTs32f32_fix |
6236 | 1.45M | 0U, // MVE_VCVTs32f32a |
6237 | 1.45M | 0U, // MVE_VCVTs32f32m |
6238 | 1.45M | 0U, // MVE_VCVTs32f32n |
6239 | 1.45M | 0U, // MVE_VCVTs32f32p |
6240 | 1.45M | 0U, // MVE_VCVTs32f32z |
6241 | 1.45M | 536U, // MVE_VCVTu16f16_fix |
6242 | 1.45M | 0U, // MVE_VCVTu16f16a |
6243 | 1.45M | 0U, // MVE_VCVTu16f16m |
6244 | 1.45M | 0U, // MVE_VCVTu16f16n |
6245 | 1.45M | 0U, // MVE_VCVTu16f16p |
6246 | 1.45M | 0U, // MVE_VCVTu16f16z |
6247 | 1.45M | 536U, // MVE_VCVTu32f32_fix |
6248 | 1.45M | 0U, // MVE_VCVTu32f32a |
6249 | 1.45M | 0U, // MVE_VCVTu32f32m |
6250 | 1.45M | 0U, // MVE_VCVTu32f32n |
6251 | 1.45M | 0U, // MVE_VCVTu32f32p |
6252 | 1.45M | 0U, // MVE_VCVTu32f32z |
6253 | 1.45M | 3670016U, // MVE_VDDUPu16 |
6254 | 1.45M | 3670016U, // MVE_VDDUPu32 |
6255 | 1.45M | 3670016U, // MVE_VDDUPu8 |
6256 | 1.45M | 16384U, // MVE_VDUP16 |
6257 | 1.45M | 16384U, // MVE_VDUP32 |
6258 | 1.45M | 16384U, // MVE_VDUP8 |
6259 | 1.45M | 37224448U, // MVE_VDWDUPu16 |
6260 | 1.45M | 37224448U, // MVE_VDWDUPu32 |
6261 | 1.45M | 37224448U, // MVE_VDWDUPu8 |
6262 | 1.45M | 0U, // MVE_VEOR |
6263 | 1.45M | 3671552U, // MVE_VFMA_qr_Sf16 |
6264 | 1.45M | 3671552U, // MVE_VFMA_qr_Sf32 |
6265 | 1.45M | 3671552U, // MVE_VFMA_qr_f16 |
6266 | 1.45M | 3671552U, // MVE_VFMA_qr_f32 |
6267 | 1.45M | 3671552U, // MVE_VFMAf16 |
6268 | 1.45M | 3671552U, // MVE_VFMAf32 |
6269 | 1.45M | 3671552U, // MVE_VFMSf16 |
6270 | 1.45M | 3671552U, // MVE_VFMSf32 |
6271 | 1.45M | 0U, // MVE_VHADD_qr_s16 |
6272 | 1.45M | 0U, // MVE_VHADD_qr_s32 |
6273 | 1.45M | 0U, // MVE_VHADD_qr_s8 |
6274 | 1.45M | 0U, // MVE_VHADD_qr_u16 |
6275 | 1.45M | 0U, // MVE_VHADD_qr_u32 |
6276 | 1.45M | 0U, // MVE_VHADD_qr_u8 |
6277 | 1.45M | 0U, // MVE_VHADDs16 |
6278 | 1.45M | 0U, // MVE_VHADDs32 |
6279 | 1.45M | 0U, // MVE_VHADDs8 |
6280 | 1.45M | 0U, // MVE_VHADDu16 |
6281 | 1.45M | 0U, // MVE_VHADDu32 |
6282 | 1.45M | 0U, // MVE_VHADDu8 |
6283 | 1.45M | 33554432U, // MVE_VHCADDs16 |
6284 | 1.45M | 33554432U, // MVE_VHCADDs32 |
6285 | 1.45M | 33554432U, // MVE_VHCADDs8 |
6286 | 1.45M | 0U, // MVE_VHSUB_qr_s16 |
6287 | 1.45M | 0U, // MVE_VHSUB_qr_s32 |
6288 | 1.45M | 0U, // MVE_VHSUB_qr_s8 |
6289 | 1.45M | 0U, // MVE_VHSUB_qr_u16 |
6290 | 1.45M | 0U, // MVE_VHSUB_qr_u32 |
6291 | 1.45M | 0U, // MVE_VHSUB_qr_u8 |
6292 | 1.45M | 0U, // MVE_VHSUBs16 |
6293 | 1.45M | 0U, // MVE_VHSUBs32 |
6294 | 1.45M | 0U, // MVE_VHSUBs8 |
6295 | 1.45M | 0U, // MVE_VHSUBu16 |
6296 | 1.45M | 0U, // MVE_VHSUBu32 |
6297 | 1.45M | 0U, // MVE_VHSUBu8 |
6298 | 1.45M | 3670016U, // MVE_VIDUPu16 |
6299 | 1.45M | 3670016U, // MVE_VIDUPu32 |
6300 | 1.45M | 3670016U, // MVE_VIDUPu8 |
6301 | 1.45M | 37224448U, // MVE_VIWDUPu16 |
6302 | 1.45M | 37224448U, // MVE_VIWDUPu32 |
6303 | 1.45M | 37224448U, // MVE_VIWDUPu8 |
6304 | 1.45M | 0U, // MVE_VLD20_16 |
6305 | 1.45M | 0U, // MVE_VLD20_16_wb |
6306 | 1.45M | 0U, // MVE_VLD20_32 |
6307 | 1.45M | 0U, // MVE_VLD20_32_wb |
6308 | 1.45M | 0U, // MVE_VLD20_8 |
6309 | 1.45M | 0U, // MVE_VLD20_8_wb |
6310 | 1.45M | 0U, // MVE_VLD21_16 |
6311 | 1.45M | 0U, // MVE_VLD21_16_wb |
6312 | 1.45M | 0U, // MVE_VLD21_32 |
6313 | 1.45M | 0U, // MVE_VLD21_32_wb |
6314 | 1.45M | 0U, // MVE_VLD21_8 |
6315 | 1.45M | 0U, // MVE_VLD21_8_wb |
6316 | 1.45M | 0U, // MVE_VLD40_16 |
6317 | 1.45M | 0U, // MVE_VLD40_16_wb |
6318 | 1.45M | 0U, // MVE_VLD40_32 |
6319 | 1.45M | 0U, // MVE_VLD40_32_wb |
6320 | 1.45M | 0U, // MVE_VLD40_8 |
6321 | 1.45M | 0U, // MVE_VLD40_8_wb |
6322 | 1.45M | 0U, // MVE_VLD41_16 |
6323 | 1.45M | 0U, // MVE_VLD41_16_wb |
6324 | 1.45M | 0U, // MVE_VLD41_32 |
6325 | 1.45M | 0U, // MVE_VLD41_32_wb |
6326 | 1.45M | 0U, // MVE_VLD41_8 |
6327 | 1.45M | 0U, // MVE_VLD41_8_wb |
6328 | 1.45M | 0U, // MVE_VLD42_16 |
6329 | 1.45M | 0U, // MVE_VLD42_16_wb |
6330 | 1.45M | 0U, // MVE_VLD42_32 |
6331 | 1.45M | 0U, // MVE_VLD42_32_wb |
6332 | 1.45M | 0U, // MVE_VLD42_8 |
6333 | 1.45M | 0U, // MVE_VLD42_8_wb |
6334 | 1.45M | 0U, // MVE_VLD43_16 |
6335 | 1.45M | 0U, // MVE_VLD43_16_wb |
6336 | 1.45M | 0U, // MVE_VLD43_32 |
6337 | 1.45M | 0U, // MVE_VLD43_32_wb |
6338 | 1.45M | 0U, // MVE_VLD43_8 |
6339 | 1.45M | 0U, // MVE_VLD43_8_wb |
6340 | 1.45M | 3968U, // MVE_VLDRBS16 |
6341 | 1.45M | 150144U, // MVE_VLDRBS16_post |
6342 | 1.45M | 4096U, // MVE_VLDRBS16_pre |
6343 | 1.45M | 4224U, // MVE_VLDRBS16_rq |
6344 | 1.45M | 3968U, // MVE_VLDRBS32 |
6345 | 1.45M | 150144U, // MVE_VLDRBS32_post |
6346 | 1.45M | 4096U, // MVE_VLDRBS32_pre |
6347 | 1.45M | 4224U, // MVE_VLDRBS32_rq |
6348 | 1.45M | 3968U, // MVE_VLDRBU16 |
6349 | 1.45M | 150144U, // MVE_VLDRBU16_post |
6350 | 1.45M | 4096U, // MVE_VLDRBU16_pre |
6351 | 1.45M | 4224U, // MVE_VLDRBU16_rq |
6352 | 1.45M | 3968U, // MVE_VLDRBU32 |
6353 | 1.45M | 150144U, // MVE_VLDRBU32_post |
6354 | 1.45M | 4096U, // MVE_VLDRBU32_pre |
6355 | 1.45M | 4224U, // MVE_VLDRBU32_rq |
6356 | 1.45M | 3968U, // MVE_VLDRBU8 |
6357 | 1.45M | 150144U, // MVE_VLDRBU8_post |
6358 | 1.45M | 4352U, // MVE_VLDRBU8_pre |
6359 | 1.45M | 4224U, // MVE_VLDRBU8_rq |
6360 | 1.45M | 3968U, // MVE_VLDRDU64_qi |
6361 | 1.45M | 4096U, // MVE_VLDRDU64_qi_pre |
6362 | 1.45M | 4480U, // MVE_VLDRDU64_rq |
6363 | 1.45M | 4224U, // MVE_VLDRDU64_rq_u |
6364 | 1.45M | 3968U, // MVE_VLDRHS32 |
6365 | 1.45M | 150144U, // MVE_VLDRHS32_post |
6366 | 1.45M | 4096U, // MVE_VLDRHS32_pre |
6367 | 1.45M | 4608U, // MVE_VLDRHS32_rq |
6368 | 1.45M | 4224U, // MVE_VLDRHS32_rq_u |
6369 | 1.45M | 3968U, // MVE_VLDRHU16 |
6370 | 1.45M | 150144U, // MVE_VLDRHU16_post |
6371 | 1.45M | 4352U, // MVE_VLDRHU16_pre |
6372 | 1.45M | 4608U, // MVE_VLDRHU16_rq |
6373 | 1.45M | 4224U, // MVE_VLDRHU16_rq_u |
6374 | 1.45M | 3968U, // MVE_VLDRHU32 |
6375 | 1.45M | 150144U, // MVE_VLDRHU32_post |
6376 | 1.45M | 4096U, // MVE_VLDRHU32_pre |
6377 | 1.45M | 4608U, // MVE_VLDRHU32_rq |
6378 | 1.45M | 4224U, // MVE_VLDRHU32_rq_u |
6379 | 1.45M | 3968U, // MVE_VLDRWU32 |
6380 | 1.45M | 150144U, // MVE_VLDRWU32_post |
6381 | 1.45M | 4352U, // MVE_VLDRWU32_pre |
6382 | 1.45M | 3968U, // MVE_VLDRWU32_qi |
6383 | 1.45M | 4096U, // MVE_VLDRWU32_qi_pre |
6384 | 1.45M | 4736U, // MVE_VLDRWU32_rq |
6385 | 1.45M | 4224U, // MVE_VLDRWU32_rq_u |
6386 | 1.45M | 17920U, // MVE_VMAXAVs16 |
6387 | 1.45M | 17920U, // MVE_VMAXAVs32 |
6388 | 1.45M | 17920U, // MVE_VMAXAVs8 |
6389 | 1.45M | 17920U, // MVE_VMAXAs16 |
6390 | 1.45M | 17920U, // MVE_VMAXAs32 |
6391 | 1.45M | 17920U, // MVE_VMAXAs8 |
6392 | 1.45M | 17920U, // MVE_VMAXNMAVf16 |
6393 | 1.45M | 17920U, // MVE_VMAXNMAVf32 |
6394 | 1.45M | 17920U, // MVE_VMAXNMAf16 |
6395 | 1.45M | 17920U, // MVE_VMAXNMAf32 |
6396 | 1.45M | 17920U, // MVE_VMAXNMVf16 |
6397 | 1.45M | 17920U, // MVE_VMAXNMVf32 |
6398 | 1.45M | 0U, // MVE_VMAXNMf16 |
6399 | 1.45M | 0U, // MVE_VMAXNMf32 |
6400 | 1.45M | 17920U, // MVE_VMAXVs16 |
6401 | 1.45M | 17920U, // MVE_VMAXVs32 |
6402 | 1.45M | 17920U, // MVE_VMAXVs8 |
6403 | 1.45M | 17920U, // MVE_VMAXVu16 |
6404 | 1.45M | 17920U, // MVE_VMAXVu32 |
6405 | 1.45M | 17920U, // MVE_VMAXVu8 |
6406 | 1.45M | 0U, // MVE_VMAXs16 |
6407 | 1.45M | 0U, // MVE_VMAXs32 |
6408 | 1.45M | 0U, // MVE_VMAXs8 |
6409 | 1.45M | 0U, // MVE_VMAXu16 |
6410 | 1.45M | 0U, // MVE_VMAXu32 |
6411 | 1.45M | 0U, // MVE_VMAXu8 |
6412 | 1.45M | 17920U, // MVE_VMINAVs16 |
6413 | 1.45M | 17920U, // MVE_VMINAVs32 |
6414 | 1.45M | 17920U, // MVE_VMINAVs8 |
6415 | 1.45M | 17920U, // MVE_VMINAs16 |
6416 | 1.45M | 17920U, // MVE_VMINAs32 |
6417 | 1.45M | 17920U, // MVE_VMINAs8 |
6418 | 1.45M | 17920U, // MVE_VMINNMAVf16 |
6419 | 1.45M | 17920U, // MVE_VMINNMAVf32 |
6420 | 1.45M | 17920U, // MVE_VMINNMAf16 |
6421 | 1.45M | 17920U, // MVE_VMINNMAf32 |
6422 | 1.45M | 17920U, // MVE_VMINNMVf16 |
6423 | 1.45M | 17920U, // MVE_VMINNMVf32 |
6424 | 1.45M | 0U, // MVE_VMINNMf16 |
6425 | 1.45M | 0U, // MVE_VMINNMf32 |
6426 | 1.45M | 17920U, // MVE_VMINVs16 |
6427 | 1.45M | 17920U, // MVE_VMINVs32 |
6428 | 1.45M | 17920U, // MVE_VMINVs8 |
6429 | 1.45M | 17920U, // MVE_VMINVu16 |
6430 | 1.45M | 17920U, // MVE_VMINVu32 |
6431 | 1.45M | 17920U, // MVE_VMINVu8 |
6432 | 1.45M | 0U, // MVE_VMINs16 |
6433 | 1.45M | 0U, // MVE_VMINs32 |
6434 | 1.45M | 0U, // MVE_VMINs8 |
6435 | 1.45M | 0U, // MVE_VMINu16 |
6436 | 1.45M | 0U, // MVE_VMINu32 |
6437 | 1.45M | 0U, // MVE_VMINu8 |
6438 | 1.45M | 3671552U, // MVE_VMLADAVas16 |
6439 | 1.45M | 3671552U, // MVE_VMLADAVas32 |
6440 | 1.45M | 3671552U, // MVE_VMLADAVas8 |
6441 | 1.45M | 3671552U, // MVE_VMLADAVau16 |
6442 | 1.45M | 3671552U, // MVE_VMLADAVau32 |
6443 | 1.45M | 3671552U, // MVE_VMLADAVau8 |
6444 | 1.45M | 3671552U, // MVE_VMLADAVaxs16 |
6445 | 1.45M | 3671552U, // MVE_VMLADAVaxs32 |
6446 | 1.45M | 3671552U, // MVE_VMLADAVaxs8 |
6447 | 1.45M | 0U, // MVE_VMLADAVs16 |
6448 | 1.45M | 0U, // MVE_VMLADAVs32 |
6449 | 1.45M | 0U, // MVE_VMLADAVs8 |
6450 | 1.45M | 0U, // MVE_VMLADAVu16 |
6451 | 1.45M | 0U, // MVE_VMLADAVu32 |
6452 | 1.45M | 0U, // MVE_VMLADAVu8 |
6453 | 1.45M | 0U, // MVE_VMLADAVxs16 |
6454 | 1.45M | 0U, // MVE_VMLADAVxs32 |
6455 | 1.45M | 0U, // MVE_VMLADAVxs8 |
6456 | 1.45M | 34078720U, // MVE_VMLALDAVas16 |
6457 | 1.45M | 34078720U, // MVE_VMLALDAVas32 |
6458 | 1.45M | 34078720U, // MVE_VMLALDAVau16 |
6459 | 1.45M | 34078720U, // MVE_VMLALDAVau32 |
6460 | 1.45M | 34078720U, // MVE_VMLALDAVaxs16 |
6461 | 1.45M | 34078720U, // MVE_VMLALDAVaxs32 |
6462 | 1.45M | 33554432U, // MVE_VMLALDAVs16 |
6463 | 1.45M | 33554432U, // MVE_VMLALDAVs32 |
6464 | 1.45M | 33554432U, // MVE_VMLALDAVu16 |
6465 | 1.45M | 33554432U, // MVE_VMLALDAVu32 |
6466 | 1.45M | 33554432U, // MVE_VMLALDAVxs16 |
6467 | 1.45M | 33554432U, // MVE_VMLALDAVxs32 |
6468 | 1.45M | 3671552U, // MVE_VMLAS_qr_i16 |
6469 | 1.45M | 3671552U, // MVE_VMLAS_qr_i32 |
6470 | 1.45M | 3671552U, // MVE_VMLAS_qr_i8 |
6471 | 1.45M | 3671552U, // MVE_VMLA_qr_i16 |
6472 | 1.45M | 3671552U, // MVE_VMLA_qr_i32 |
6473 | 1.45M | 3671552U, // MVE_VMLA_qr_i8 |
6474 | 1.45M | 3671552U, // MVE_VMLSDAVas16 |
6475 | 1.45M | 3671552U, // MVE_VMLSDAVas32 |
6476 | 1.45M | 3671552U, // MVE_VMLSDAVas8 |
6477 | 1.45M | 3671552U, // MVE_VMLSDAVaxs16 |
6478 | 1.45M | 3671552U, // MVE_VMLSDAVaxs32 |
6479 | 1.45M | 3671552U, // MVE_VMLSDAVaxs8 |
6480 | 1.45M | 0U, // MVE_VMLSDAVs16 |
6481 | 1.45M | 0U, // MVE_VMLSDAVs32 |
6482 | 1.45M | 0U, // MVE_VMLSDAVs8 |
6483 | 1.45M | 0U, // MVE_VMLSDAVxs16 |
6484 | 1.45M | 0U, // MVE_VMLSDAVxs32 |
6485 | 1.45M | 0U, // MVE_VMLSDAVxs8 |
6486 | 1.45M | 34078720U, // MVE_VMLSLDAVas16 |
6487 | 1.45M | 34078720U, // MVE_VMLSLDAVas32 |
6488 | 1.45M | 34078720U, // MVE_VMLSLDAVaxs16 |
6489 | 1.45M | 34078720U, // MVE_VMLSLDAVaxs32 |
6490 | 1.45M | 33554432U, // MVE_VMLSLDAVs16 |
6491 | 1.45M | 33554432U, // MVE_VMLSLDAVs32 |
6492 | 1.45M | 33554432U, // MVE_VMLSLDAVxs16 |
6493 | 1.45M | 33554432U, // MVE_VMLSLDAVxs32 |
6494 | 1.45M | 16384U, // MVE_VMOVLs16bh |
6495 | 1.45M | 16384U, // MVE_VMOVLs16th |
6496 | 1.45M | 16384U, // MVE_VMOVLs8bh |
6497 | 1.45M | 16384U, // MVE_VMOVLs8th |
6498 | 1.45M | 16384U, // MVE_VMOVLu16bh |
6499 | 1.45M | 16384U, // MVE_VMOVLu16th |
6500 | 1.45M | 16384U, // MVE_VMOVLu8bh |
6501 | 1.45M | 16384U, // MVE_VMOVLu8th |
6502 | 1.45M | 17920U, // MVE_VMOVNi16bh |
6503 | 1.45M | 17920U, // MVE_VMOVNi16th |
6504 | 1.45M | 17920U, // MVE_VMOVNi32bh |
6505 | 1.45M | 17920U, // MVE_VMOVNi32th |
6506 | 1.45M | 163840U, // MVE_VMOV_from_lane_32 |
6507 | 1.45M | 163840U, // MVE_VMOV_from_lane_s16 |
6508 | 1.45M | 163840U, // MVE_VMOV_from_lane_s8 |
6509 | 1.45M | 163840U, // MVE_VMOV_from_lane_u16 |
6510 | 1.45M | 163840U, // MVE_VMOV_from_lane_u8 |
6511 | 1.45M | 32U, // MVE_VMOV_q_rr |
6512 | 1.45M | 167772160U, // MVE_VMOV_rr_q |
6513 | 1.45M | 34U, // MVE_VMOV_to_lane_16 |
6514 | 1.45M | 34U, // MVE_VMOV_to_lane_32 |
6515 | 1.45M | 34U, // MVE_VMOV_to_lane_8 |
6516 | 1.45M | 2048U, // MVE_VMOVimmf32 |
6517 | 1.45M | 4864U, // MVE_VMOVimmi16 |
6518 | 1.45M | 4864U, // MVE_VMOVimmi32 |
6519 | 1.45M | 0U, // MVE_VMOVimmi64 |
6520 | 1.45M | 4864U, // MVE_VMOVimmi8 |
6521 | 1.45M | 0U, // MVE_VMULHs16 |
6522 | 1.45M | 0U, // MVE_VMULHs32 |
6523 | 1.45M | 0U, // MVE_VMULHs8 |
6524 | 1.45M | 0U, // MVE_VMULHu16 |
6525 | 1.45M | 0U, // MVE_VMULHu32 |
6526 | 1.45M | 0U, // MVE_VMULHu8 |
6527 | 1.45M | 0U, // MVE_VMULLBp16 |
6528 | 1.45M | 0U, // MVE_VMULLBp8 |
6529 | 1.45M | 0U, // MVE_VMULLBs16 |
6530 | 1.45M | 0U, // MVE_VMULLBs32 |
6531 | 1.45M | 0U, // MVE_VMULLBs8 |
6532 | 1.45M | 0U, // MVE_VMULLBu16 |
6533 | 1.45M | 0U, // MVE_VMULLBu32 |
6534 | 1.45M | 0U, // MVE_VMULLBu8 |
6535 | 1.45M | 0U, // MVE_VMULLTp16 |
6536 | 1.45M | 0U, // MVE_VMULLTp8 |
6537 | 1.45M | 0U, // MVE_VMULLTs16 |
6538 | 1.45M | 0U, // MVE_VMULLTs32 |
6539 | 1.45M | 0U, // MVE_VMULLTs8 |
6540 | 1.45M | 0U, // MVE_VMULLTu16 |
6541 | 1.45M | 0U, // MVE_VMULLTu32 |
6542 | 1.45M | 0U, // MVE_VMULLTu8 |
6543 | 1.45M | 0U, // MVE_VMUL_qr_f16 |
6544 | 1.45M | 0U, // MVE_VMUL_qr_f32 |
6545 | 1.45M | 0U, // MVE_VMUL_qr_i16 |
6546 | 1.45M | 0U, // MVE_VMUL_qr_i32 |
6547 | 1.45M | 0U, // MVE_VMUL_qr_i8 |
6548 | 1.45M | 0U, // MVE_VMULf16 |
6549 | 1.45M | 0U, // MVE_VMULf32 |
6550 | 1.45M | 0U, // MVE_VMULi16 |
6551 | 1.45M | 0U, // MVE_VMULi32 |
6552 | 1.45M | 0U, // MVE_VMULi8 |
6553 | 1.45M | 16384U, // MVE_VMVN |
6554 | 1.45M | 4864U, // MVE_VMVNimmi16 |
6555 | 1.45M | 4864U, // MVE_VMVNimmi32 |
6556 | 1.45M | 16384U, // MVE_VNEGf16 |
6557 | 1.45M | 16384U, // MVE_VNEGf32 |
6558 | 1.45M | 16384U, // MVE_VNEGs16 |
6559 | 1.45M | 16384U, // MVE_VNEGs32 |
6560 | 1.45M | 16384U, // MVE_VNEGs8 |
6561 | 1.45M | 0U, // MVE_VORN |
6562 | 1.45M | 0U, // MVE_VORR |
6563 | 1.45M | 3840U, // MVE_VORRimmi16 |
6564 | 1.45M | 3840U, // MVE_VORRimmi32 |
6565 | 1.45M | 0U, // MVE_VPNOT |
6566 | 1.45M | 0U, // MVE_VPSEL |
6567 | 1.45M | 0U, // MVE_VPST |
6568 | 1.45M | 0U, // MVE_VPTv16i8 |
6569 | 1.45M | 0U, // MVE_VPTv16i8r |
6570 | 1.45M | 0U, // MVE_VPTv16s8 |
6571 | 1.45M | 0U, // MVE_VPTv16s8r |
6572 | 1.45M | 0U, // MVE_VPTv16u8 |
6573 | 1.45M | 0U, // MVE_VPTv16u8r |
6574 | 1.45M | 0U, // MVE_VPTv4f32 |
6575 | 1.45M | 0U, // MVE_VPTv4f32r |
6576 | 1.45M | 0U, // MVE_VPTv4i32 |
6577 | 1.45M | 0U, // MVE_VPTv4i32r |
6578 | 1.45M | 0U, // MVE_VPTv4s32 |
6579 | 1.45M | 0U, // MVE_VPTv4s32r |
6580 | 1.45M | 0U, // MVE_VPTv4u32 |
6581 | 1.45M | 0U, // MVE_VPTv4u32r |
6582 | 1.45M | 0U, // MVE_VPTv8f16 |
6583 | 1.45M | 0U, // MVE_VPTv8f16r |
6584 | 1.45M | 0U, // MVE_VPTv8i16 |
6585 | 1.45M | 0U, // MVE_VPTv8i16r |
6586 | 1.45M | 0U, // MVE_VPTv8s16 |
6587 | 1.45M | 0U, // MVE_VPTv8s16r |
6588 | 1.45M | 0U, // MVE_VPTv8u16 |
6589 | 1.45M | 0U, // MVE_VPTv8u16r |
6590 | 1.45M | 16384U, // MVE_VQABSs16 |
6591 | 1.45M | 16384U, // MVE_VQABSs32 |
6592 | 1.45M | 16384U, // MVE_VQABSs8 |
6593 | 1.45M | 0U, // MVE_VQADD_qr_s16 |
6594 | 1.45M | 0U, // MVE_VQADD_qr_s32 |
6595 | 1.45M | 0U, // MVE_VQADD_qr_s8 |
6596 | 1.45M | 0U, // MVE_VQADD_qr_u16 |
6597 | 1.45M | 0U, // MVE_VQADD_qr_u32 |
6598 | 1.45M | 0U, // MVE_VQADD_qr_u8 |
6599 | 1.45M | 0U, // MVE_VQADDs16 |
6600 | 1.45M | 0U, // MVE_VQADDs32 |
6601 | 1.45M | 0U, // MVE_VQADDs8 |
6602 | 1.45M | 0U, // MVE_VQADDu16 |
6603 | 1.45M | 0U, // MVE_VQADDu32 |
6604 | 1.45M | 0U, // MVE_VQADDu8 |
6605 | 1.45M | 3671552U, // MVE_VQDMLADHXs16 |
6606 | 1.45M | 3671552U, // MVE_VQDMLADHXs32 |
6607 | 1.45M | 3671552U, // MVE_VQDMLADHXs8 |
6608 | 1.45M | 3671552U, // MVE_VQDMLADHs16 |
6609 | 1.45M | 3671552U, // MVE_VQDMLADHs32 |
6610 | 1.45M | 3671552U, // MVE_VQDMLADHs8 |
6611 | 1.45M | 3671552U, // MVE_VQDMLAH_qrs16 |
6612 | 1.45M | 3671552U, // MVE_VQDMLAH_qrs32 |
6613 | 1.45M | 3671552U, // MVE_VQDMLAH_qrs8 |
6614 | 1.45M | 3671552U, // MVE_VQDMLASH_qrs16 |
6615 | 1.45M | 3671552U, // MVE_VQDMLASH_qrs32 |
6616 | 1.45M | 3671552U, // MVE_VQDMLASH_qrs8 |
6617 | 1.45M | 3671552U, // MVE_VQDMLSDHXs16 |
6618 | 1.45M | 3671552U, // MVE_VQDMLSDHXs32 |
6619 | 1.45M | 3671552U, // MVE_VQDMLSDHXs8 |
6620 | 1.45M | 3671552U, // MVE_VQDMLSDHs16 |
6621 | 1.45M | 3671552U, // MVE_VQDMLSDHs32 |
6622 | 1.45M | 3671552U, // MVE_VQDMLSDHs8 |
6623 | 1.45M | 0U, // MVE_VQDMULH_qr_s16 |
6624 | 1.45M | 0U, // MVE_VQDMULH_qr_s32 |
6625 | 1.45M | 0U, // MVE_VQDMULH_qr_s8 |
6626 | 1.45M | 0U, // MVE_VQDMULHi16 |
6627 | 1.45M | 0U, // MVE_VQDMULHi32 |
6628 | 1.45M | 0U, // MVE_VQDMULHi8 |
6629 | 1.45M | 0U, // MVE_VQDMULL_qr_s16bh |
6630 | 1.45M | 0U, // MVE_VQDMULL_qr_s16th |
6631 | 1.45M | 0U, // MVE_VQDMULL_qr_s32bh |
6632 | 1.45M | 0U, // MVE_VQDMULL_qr_s32th |
6633 | 1.45M | 0U, // MVE_VQDMULLs16bh |
6634 | 1.45M | 0U, // MVE_VQDMULLs16th |
6635 | 1.45M | 0U, // MVE_VQDMULLs32bh |
6636 | 1.45M | 0U, // MVE_VQDMULLs32th |
6637 | 1.45M | 17920U, // MVE_VQMOVNs16bh |
6638 | 1.45M | 17920U, // MVE_VQMOVNs16th |
6639 | 1.45M | 17920U, // MVE_VQMOVNs32bh |
6640 | 1.45M | 17920U, // MVE_VQMOVNs32th |
6641 | 1.45M | 17920U, // MVE_VQMOVNu16bh |
6642 | 1.45M | 17920U, // MVE_VQMOVNu16th |
6643 | 1.45M | 17920U, // MVE_VQMOVNu32bh |
6644 | 1.45M | 17920U, // MVE_VQMOVNu32th |
6645 | 1.45M | 17920U, // MVE_VQMOVUNs16bh |
6646 | 1.45M | 17920U, // MVE_VQMOVUNs16th |
6647 | 1.45M | 17920U, // MVE_VQMOVUNs32bh |
6648 | 1.45M | 17920U, // MVE_VQMOVUNs32th |
6649 | 1.45M | 16384U, // MVE_VQNEGs16 |
6650 | 1.45M | 16384U, // MVE_VQNEGs32 |
6651 | 1.45M | 16384U, // MVE_VQNEGs8 |
6652 | 1.45M | 3671552U, // MVE_VQRDMLADHXs16 |
6653 | 1.45M | 3671552U, // MVE_VQRDMLADHXs32 |
6654 | 1.45M | 3671552U, // MVE_VQRDMLADHXs8 |
6655 | 1.45M | 3671552U, // MVE_VQRDMLADHs16 |
6656 | 1.45M | 3671552U, // MVE_VQRDMLADHs32 |
6657 | 1.45M | 3671552U, // MVE_VQRDMLADHs8 |
6658 | 1.45M | 3671552U, // MVE_VQRDMLAH_qrs16 |
6659 | 1.45M | 3671552U, // MVE_VQRDMLAH_qrs32 |
6660 | 1.45M | 3671552U, // MVE_VQRDMLAH_qrs8 |
6661 | 1.45M | 3671552U, // MVE_VQRDMLASH_qrs16 |
6662 | 1.45M | 3671552U, // MVE_VQRDMLASH_qrs32 |
6663 | 1.45M | 3671552U, // MVE_VQRDMLASH_qrs8 |
6664 | 1.45M | 3671552U, // MVE_VQRDMLSDHXs16 |
6665 | 1.45M | 3671552U, // MVE_VQRDMLSDHXs32 |
6666 | 1.45M | 3671552U, // MVE_VQRDMLSDHXs8 |
6667 | 1.45M | 3671552U, // MVE_VQRDMLSDHs16 |
6668 | 1.45M | 3671552U, // MVE_VQRDMLSDHs32 |
6669 | 1.45M | 3671552U, // MVE_VQRDMLSDHs8 |
6670 | 1.45M | 0U, // MVE_VQRDMULH_qr_s16 |
6671 | 1.45M | 0U, // MVE_VQRDMULH_qr_s32 |
6672 | 1.45M | 0U, // MVE_VQRDMULH_qr_s8 |
6673 | 1.45M | 0U, // MVE_VQRDMULHi16 |
6674 | 1.45M | 0U, // MVE_VQRDMULHi32 |
6675 | 1.45M | 0U, // MVE_VQRDMULHi8 |
6676 | 1.45M | 0U, // MVE_VQRSHL_by_vecs16 |
6677 | 1.45M | 0U, // MVE_VQRSHL_by_vecs32 |
6678 | 1.45M | 0U, // MVE_VQRSHL_by_vecs8 |
6679 | 1.45M | 0U, // MVE_VQRSHL_by_vecu16 |
6680 | 1.45M | 0U, // MVE_VQRSHL_by_vecu32 |
6681 | 1.45M | 0U, // MVE_VQRSHL_by_vecu8 |
6682 | 1.45M | 17920U, // MVE_VQRSHL_qrs16 |
6683 | 1.45M | 17920U, // MVE_VQRSHL_qrs32 |
6684 | 1.45M | 17920U, // MVE_VQRSHL_qrs8 |
6685 | 1.45M | 17920U, // MVE_VQRSHL_qru16 |
6686 | 1.45M | 17920U, // MVE_VQRSHL_qru32 |
6687 | 1.45M | 17920U, // MVE_VQRSHL_qru8 |
6688 | 1.45M | 3671552U, // MVE_VQRSHRNbhs16 |
6689 | 1.45M | 3671552U, // MVE_VQRSHRNbhs32 |
6690 | 1.45M | 3671552U, // MVE_VQRSHRNbhu16 |
6691 | 1.45M | 3671552U, // MVE_VQRSHRNbhu32 |
6692 | 1.45M | 3671552U, // MVE_VQRSHRNths16 |
6693 | 1.45M | 3671552U, // MVE_VQRSHRNths32 |
6694 | 1.45M | 3671552U, // MVE_VQRSHRNthu16 |
6695 | 1.45M | 3671552U, // MVE_VQRSHRNthu32 |
6696 | 1.45M | 3671552U, // MVE_VQRSHRUNs16bh |
6697 | 1.45M | 3671552U, // MVE_VQRSHRUNs16th |
6698 | 1.45M | 3671552U, // MVE_VQRSHRUNs32bh |
6699 | 1.45M | 3671552U, // MVE_VQRSHRUNs32th |
6700 | 1.45M | 0U, // MVE_VQSHLU_imms16 |
6701 | 1.45M | 0U, // MVE_VQSHLU_imms32 |
6702 | 1.45M | 0U, // MVE_VQSHLU_imms8 |
6703 | 1.45M | 0U, // MVE_VQSHL_by_vecs16 |
6704 | 1.45M | 0U, // MVE_VQSHL_by_vecs32 |
6705 | 1.45M | 0U, // MVE_VQSHL_by_vecs8 |
6706 | 1.45M | 0U, // MVE_VQSHL_by_vecu16 |
6707 | 1.45M | 0U, // MVE_VQSHL_by_vecu32 |
6708 | 1.45M | 0U, // MVE_VQSHL_by_vecu8 |
6709 | 1.45M | 17920U, // MVE_VQSHL_qrs16 |
6710 | 1.45M | 17920U, // MVE_VQSHL_qrs32 |
6711 | 1.45M | 17920U, // MVE_VQSHL_qrs8 |
6712 | 1.45M | 17920U, // MVE_VQSHL_qru16 |
6713 | 1.45M | 17920U, // MVE_VQSHL_qru32 |
6714 | 1.45M | 17920U, // MVE_VQSHL_qru8 |
6715 | 1.45M | 0U, // MVE_VQSHLimms16 |
6716 | 1.45M | 0U, // MVE_VQSHLimms32 |
6717 | 1.45M | 0U, // MVE_VQSHLimms8 |
6718 | 1.45M | 0U, // MVE_VQSHLimmu16 |
6719 | 1.45M | 0U, // MVE_VQSHLimmu32 |
6720 | 1.45M | 0U, // MVE_VQSHLimmu8 |
6721 | 1.45M | 3671552U, // MVE_VQSHRNbhs16 |
6722 | 1.45M | 3671552U, // MVE_VQSHRNbhs32 |
6723 | 1.45M | 3671552U, // MVE_VQSHRNbhu16 |
6724 | 1.45M | 3671552U, // MVE_VQSHRNbhu32 |
6725 | 1.45M | 3671552U, // MVE_VQSHRNths16 |
6726 | 1.45M | 3671552U, // MVE_VQSHRNths32 |
6727 | 1.45M | 3671552U, // MVE_VQSHRNthu16 |
6728 | 1.45M | 3671552U, // MVE_VQSHRNthu32 |
6729 | 1.45M | 3671552U, // MVE_VQSHRUNs16bh |
6730 | 1.45M | 3671552U, // MVE_VQSHRUNs16th |
6731 | 1.45M | 3671552U, // MVE_VQSHRUNs32bh |
6732 | 1.45M | 3671552U, // MVE_VQSHRUNs32th |
6733 | 1.45M | 0U, // MVE_VQSUB_qr_s16 |
6734 | 1.45M | 0U, // MVE_VQSUB_qr_s32 |
6735 | 1.45M | 0U, // MVE_VQSUB_qr_s8 |
6736 | 1.45M | 0U, // MVE_VQSUB_qr_u16 |
6737 | 1.45M | 0U, // MVE_VQSUB_qr_u32 |
6738 | 1.45M | 0U, // MVE_VQSUB_qr_u8 |
6739 | 1.45M | 0U, // MVE_VQSUBs16 |
6740 | 1.45M | 0U, // MVE_VQSUBs32 |
6741 | 1.45M | 0U, // MVE_VQSUBs8 |
6742 | 1.45M | 0U, // MVE_VQSUBu16 |
6743 | 1.45M | 0U, // MVE_VQSUBu32 |
6744 | 1.45M | 0U, // MVE_VQSUBu8 |
6745 | 1.45M | 16384U, // MVE_VREV16_8 |
6746 | 1.45M | 16384U, // MVE_VREV32_16 |
6747 | 1.45M | 16384U, // MVE_VREV32_8 |
6748 | 1.45M | 16384U, // MVE_VREV64_16 |
6749 | 1.45M | 16384U, // MVE_VREV64_32 |
6750 | 1.45M | 16384U, // MVE_VREV64_8 |
6751 | 1.45M | 0U, // MVE_VRHADDs16 |
6752 | 1.45M | 0U, // MVE_VRHADDs32 |
6753 | 1.45M | 0U, // MVE_VRHADDs8 |
6754 | 1.45M | 0U, // MVE_VRHADDu16 |
6755 | 1.45M | 0U, // MVE_VRHADDu32 |
6756 | 1.45M | 0U, // MVE_VRHADDu8 |
6757 | 1.45M | 16384U, // MVE_VRINTf16A |
6758 | 1.45M | 16384U, // MVE_VRINTf16M |
6759 | 1.45M | 16384U, // MVE_VRINTf16N |
6760 | 1.45M | 16384U, // MVE_VRINTf16P |
6761 | 1.45M | 16384U, // MVE_VRINTf16X |
6762 | 1.45M | 16384U, // MVE_VRINTf16Z |
6763 | 1.45M | 16384U, // MVE_VRINTf32A |
6764 | 1.45M | 16384U, // MVE_VRINTf32M |
6765 | 1.45M | 16384U, // MVE_VRINTf32N |
6766 | 1.45M | 16384U, // MVE_VRINTf32P |
6767 | 1.45M | 16384U, // MVE_VRINTf32X |
6768 | 1.45M | 16384U, // MVE_VRINTf32Z |
6769 | 1.45M | 34078720U, // MVE_VRMLALDAVHas32 |
6770 | 1.45M | 34078720U, // MVE_VRMLALDAVHau32 |
6771 | 1.45M | 34078720U, // MVE_VRMLALDAVHaxs32 |
6772 | 1.45M | 33554432U, // MVE_VRMLALDAVHs32 |
6773 | 1.45M | 33554432U, // MVE_VRMLALDAVHu32 |
6774 | 1.45M | 33554432U, // MVE_VRMLALDAVHxs32 |
6775 | 1.45M | 34078720U, // MVE_VRMLSLDAVHas32 |
6776 | 1.45M | 34078720U, // MVE_VRMLSLDAVHaxs32 |
6777 | 1.45M | 33554432U, // MVE_VRMLSLDAVHs32 |
6778 | 1.45M | 33554432U, // MVE_VRMLSLDAVHxs32 |
6779 | 1.45M | 0U, // MVE_VRMULHs16 |
6780 | 1.45M | 0U, // MVE_VRMULHs32 |
6781 | 1.45M | 0U, // MVE_VRMULHs8 |
6782 | 1.45M | 0U, // MVE_VRMULHu16 |
6783 | 1.45M | 0U, // MVE_VRMULHu32 |
6784 | 1.45M | 0U, // MVE_VRMULHu8 |
6785 | 1.45M | 0U, // MVE_VRSHL_by_vecs16 |
6786 | 1.45M | 0U, // MVE_VRSHL_by_vecs32 |
6787 | 1.45M | 0U, // MVE_VRSHL_by_vecs8 |
6788 | 1.45M | 0U, // MVE_VRSHL_by_vecu16 |
6789 | 1.45M | 0U, // MVE_VRSHL_by_vecu32 |
6790 | 1.45M | 0U, // MVE_VRSHL_by_vecu8 |
6791 | 1.45M | 17920U, // MVE_VRSHL_qrs16 |
6792 | 1.45M | 17920U, // MVE_VRSHL_qrs32 |
6793 | 1.45M | 17920U, // MVE_VRSHL_qrs8 |
6794 | 1.45M | 17920U, // MVE_VRSHL_qru16 |
6795 | 1.45M | 17920U, // MVE_VRSHL_qru32 |
6796 | 1.45M | 17920U, // MVE_VRSHL_qru8 |
6797 | 1.45M | 3671552U, // MVE_VRSHRNi16bh |
6798 | 1.45M | 3671552U, // MVE_VRSHRNi16th |
6799 | 1.45M | 3671552U, // MVE_VRSHRNi32bh |
6800 | 1.45M | 3671552U, // MVE_VRSHRNi32th |
6801 | 1.45M | 0U, // MVE_VRSHR_imms16 |
6802 | 1.45M | 0U, // MVE_VRSHR_imms32 |
6803 | 1.45M | 0U, // MVE_VRSHR_imms8 |
6804 | 1.45M | 0U, // MVE_VRSHR_immu16 |
6805 | 1.45M | 0U, // MVE_VRSHR_immu32 |
6806 | 1.45M | 0U, // MVE_VRSHR_immu8 |
6807 | 1.45M | 3671552U, // MVE_VSBC |
6808 | 1.45M | 3671552U, // MVE_VSBCI |
6809 | 1.45M | 524672U, // MVE_VSHLC |
6810 | 1.45M | 0U, // MVE_VSHLL_imms16bh |
6811 | 1.45M | 0U, // MVE_VSHLL_imms16th |
6812 | 1.45M | 0U, // MVE_VSHLL_imms8bh |
6813 | 1.45M | 0U, // MVE_VSHLL_imms8th |
6814 | 1.45M | 0U, // MVE_VSHLL_immu16bh |
6815 | 1.45M | 0U, // MVE_VSHLL_immu16th |
6816 | 1.45M | 0U, // MVE_VSHLL_immu8bh |
6817 | 1.45M | 0U, // MVE_VSHLL_immu8th |
6818 | 1.45M | 180224U, // MVE_VSHLL_lws16bh |
6819 | 1.45M | 180224U, // MVE_VSHLL_lws16th |
6820 | 1.45M | 196608U, // MVE_VSHLL_lws8bh |
6821 | 1.45M | 196608U, // MVE_VSHLL_lws8th |
6822 | 1.45M | 180224U, // MVE_VSHLL_lwu16bh |
6823 | 1.45M | 180224U, // MVE_VSHLL_lwu16th |
6824 | 1.45M | 196608U, // MVE_VSHLL_lwu8bh |
6825 | 1.45M | 196608U, // MVE_VSHLL_lwu8th |
6826 | 1.45M | 0U, // MVE_VSHL_by_vecs16 |
6827 | 1.45M | 0U, // MVE_VSHL_by_vecs32 |
6828 | 1.45M | 0U, // MVE_VSHL_by_vecs8 |
6829 | 1.45M | 0U, // MVE_VSHL_by_vecu16 |
6830 | 1.45M | 0U, // MVE_VSHL_by_vecu32 |
6831 | 1.45M | 0U, // MVE_VSHL_by_vecu8 |
6832 | 1.45M | 0U, // MVE_VSHL_immi16 |
6833 | 1.45M | 0U, // MVE_VSHL_immi32 |
6834 | 1.45M | 0U, // MVE_VSHL_immi8 |
6835 | 1.45M | 17920U, // MVE_VSHL_qrs16 |
6836 | 1.45M | 17920U, // MVE_VSHL_qrs32 |
6837 | 1.45M | 17920U, // MVE_VSHL_qrs8 |
6838 | 1.45M | 17920U, // MVE_VSHL_qru16 |
6839 | 1.45M | 17920U, // MVE_VSHL_qru32 |
6840 | 1.45M | 17920U, // MVE_VSHL_qru8 |
6841 | 1.45M | 3671552U, // MVE_VSHRNi16bh |
6842 | 1.45M | 3671552U, // MVE_VSHRNi16th |
6843 | 1.45M | 3671552U, // MVE_VSHRNi32bh |
6844 | 1.45M | 3671552U, // MVE_VSHRNi32th |
6845 | 1.45M | 0U, // MVE_VSHR_imms16 |
6846 | 1.45M | 0U, // MVE_VSHR_imms32 |
6847 | 1.45M | 0U, // MVE_VSHR_imms8 |
6848 | 1.45M | 0U, // MVE_VSHR_immu16 |
6849 | 1.45M | 0U, // MVE_VSHR_immu32 |
6850 | 1.45M | 0U, // MVE_VSHR_immu8 |
6851 | 1.45M | 3671552U, // MVE_VSLIimm16 |
6852 | 1.45M | 3671552U, // MVE_VSLIimm32 |
6853 | 1.45M | 3671552U, // MVE_VSLIimm8 |
6854 | 1.45M | 3671552U, // MVE_VSRIimm16 |
6855 | 1.45M | 3671552U, // MVE_VSRIimm32 |
6856 | 1.45M | 3671552U, // MVE_VSRIimm8 |
6857 | 1.45M | 0U, // MVE_VST20_16 |
6858 | 1.45M | 0U, // MVE_VST20_16_wb |
6859 | 1.45M | 0U, // MVE_VST20_32 |
6860 | 1.45M | 0U, // MVE_VST20_32_wb |
6861 | 1.45M | 0U, // MVE_VST20_8 |
6862 | 1.45M | 0U, // MVE_VST20_8_wb |
6863 | 1.45M | 0U, // MVE_VST21_16 |
6864 | 1.45M | 0U, // MVE_VST21_16_wb |
6865 | 1.45M | 0U, // MVE_VST21_32 |
6866 | 1.45M | 0U, // MVE_VST21_32_wb |
6867 | 1.45M | 0U, // MVE_VST21_8 |
6868 | 1.45M | 0U, // MVE_VST21_8_wb |
6869 | 1.45M | 0U, // MVE_VST40_16 |
6870 | 1.45M | 0U, // MVE_VST40_16_wb |
6871 | 1.45M | 0U, // MVE_VST40_32 |
6872 | 1.45M | 0U, // MVE_VST40_32_wb |
6873 | 1.45M | 0U, // MVE_VST40_8 |
6874 | 1.45M | 0U, // MVE_VST40_8_wb |
6875 | 1.45M | 0U, // MVE_VST41_16 |
6876 | 1.45M | 0U, // MVE_VST41_16_wb |
6877 | 1.45M | 0U, // MVE_VST41_32 |
6878 | 1.45M | 0U, // MVE_VST41_32_wb |
6879 | 1.45M | 0U, // MVE_VST41_8 |
6880 | 1.45M | 0U, // MVE_VST41_8_wb |
6881 | 1.45M | 0U, // MVE_VST42_16 |
6882 | 1.45M | 0U, // MVE_VST42_16_wb |
6883 | 1.45M | 0U, // MVE_VST42_32 |
6884 | 1.45M | 0U, // MVE_VST42_32_wb |
6885 | 1.45M | 0U, // MVE_VST42_8 |
6886 | 1.45M | 0U, // MVE_VST42_8_wb |
6887 | 1.45M | 0U, // MVE_VST43_16 |
6888 | 1.45M | 0U, // MVE_VST43_16_wb |
6889 | 1.45M | 0U, // MVE_VST43_32 |
6890 | 1.45M | 0U, // MVE_VST43_32_wb |
6891 | 1.45M | 0U, // MVE_VST43_8 |
6892 | 1.45M | 0U, // MVE_VST43_8_wb |
6893 | 1.45M | 3968U, // MVE_VSTRB16 |
6894 | 1.45M | 150144U, // MVE_VSTRB16_post |
6895 | 1.45M | 4096U, // MVE_VSTRB16_pre |
6896 | 1.45M | 4224U, // MVE_VSTRB16_rq |
6897 | 1.45M | 3968U, // MVE_VSTRB32 |
6898 | 1.45M | 150144U, // MVE_VSTRB32_post |
6899 | 1.45M | 4096U, // MVE_VSTRB32_pre |
6900 | 1.45M | 4224U, // MVE_VSTRB32_rq |
6901 | 1.45M | 4224U, // MVE_VSTRB8_rq |
6902 | 1.45M | 3968U, // MVE_VSTRBU8 |
6903 | 1.45M | 150144U, // MVE_VSTRBU8_post |
6904 | 1.45M | 4352U, // MVE_VSTRBU8_pre |
6905 | 1.45M | 3968U, // MVE_VSTRD64_qi |
6906 | 1.45M | 4096U, // MVE_VSTRD64_qi_pre |
6907 | 1.45M | 4480U, // MVE_VSTRD64_rq |
6908 | 1.45M | 4224U, // MVE_VSTRD64_rq_u |
6909 | 1.45M | 4608U, // MVE_VSTRH16_rq |
6910 | 1.45M | 4224U, // MVE_VSTRH16_rq_u |
6911 | 1.45M | 3968U, // MVE_VSTRH32 |
6912 | 1.45M | 150144U, // MVE_VSTRH32_post |
6913 | 1.45M | 4096U, // MVE_VSTRH32_pre |
6914 | 1.45M | 4608U, // MVE_VSTRH32_rq |
6915 | 1.45M | 4224U, // MVE_VSTRH32_rq_u |
6916 | 1.45M | 3968U, // MVE_VSTRHU16 |
6917 | 1.45M | 150144U, // MVE_VSTRHU16_post |
6918 | 1.45M | 4352U, // MVE_VSTRHU16_pre |
6919 | 1.45M | 3968U, // MVE_VSTRW32_qi |
6920 | 1.45M | 4096U, // MVE_VSTRW32_qi_pre |
6921 | 1.45M | 4736U, // MVE_VSTRW32_rq |
6922 | 1.45M | 4224U, // MVE_VSTRW32_rq_u |
6923 | 1.45M | 3968U, // MVE_VSTRWU32 |
6924 | 1.45M | 150144U, // MVE_VSTRWU32_post |
6925 | 1.45M | 4352U, // MVE_VSTRWU32_pre |
6926 | 1.45M | 0U, // MVE_VSUB_qr_f16 |
6927 | 1.45M | 0U, // MVE_VSUB_qr_f32 |
6928 | 1.45M | 0U, // MVE_VSUB_qr_i16 |
6929 | 1.45M | 0U, // MVE_VSUB_qr_i32 |
6930 | 1.45M | 0U, // MVE_VSUB_qr_i8 |
6931 | 1.45M | 0U, // MVE_VSUBf16 |
6932 | 1.45M | 0U, // MVE_VSUBf32 |
6933 | 1.45M | 0U, // MVE_VSUBi16 |
6934 | 1.45M | 0U, // MVE_VSUBi32 |
6935 | 1.45M | 0U, // MVE_VSUBi8 |
6936 | 1.45M | 21376U, // MVE_WLSTP_16 |
6937 | 1.45M | 21376U, // MVE_WLSTP_32 |
6938 | 1.45M | 21376U, // MVE_WLSTP_64 |
6939 | 1.45M | 21376U, // MVE_WLSTP_8 |
6940 | 1.45M | 1792U, // MVNi |
6941 | 1.45M | 16384U, // MVNr |
6942 | 1.45M | 1920U, // MVNsi |
6943 | 1.45M | 1152U, // MVNsr |
6944 | 1.45M | 17920U, // NEON_VMAXNMNDf |
6945 | 1.45M | 17920U, // NEON_VMAXNMNDh |
6946 | 1.45M | 17920U, // NEON_VMAXNMNQf |
6947 | 1.45M | 17920U, // NEON_VMAXNMNQh |
6948 | 1.45M | 17920U, // NEON_VMINNMNDf |
6949 | 1.45M | 17920U, // NEON_VMINNMNDh |
6950 | 1.45M | 17920U, // NEON_VMINNMNQf |
6951 | 1.45M | 17920U, // NEON_VMINNMNQh |
6952 | 1.45M | 1048576U, // ORRri |
6953 | 1.45M | 0U, // ORRrr |
6954 | 1.45M | 1572864U, // ORRrsi |
6955 | 1.45M | 0U, // ORRrsr |
6956 | 1.45M | 201326592U, // PKHBT |
6957 | 1.45M | 234881024U, // PKHTB |
6958 | 1.45M | 0U, // PLDWi12 |
6959 | 1.45M | 0U, // PLDWrs |
6960 | 1.45M | 0U, // PLDi12 |
6961 | 1.45M | 0U, // PLDrs |
6962 | 1.45M | 0U, // PLIi12 |
6963 | 1.45M | 0U, // PLIrs |
6964 | 1.45M | 0U, // QADD |
6965 | 1.45M | 0U, // QADD16 |
6966 | 1.45M | 0U, // QADD8 |
6967 | 1.45M | 0U, // QASX |
6968 | 1.45M | 0U, // QDADD |
6969 | 1.45M | 0U, // QDSUB |
6970 | 1.45M | 0U, // QSAX |
6971 | 1.45M | 0U, // QSUB |
6972 | 1.45M | 0U, // QSUB16 |
6973 | 1.45M | 0U, // QSUB8 |
6974 | 1.45M | 16384U, // RBIT |
6975 | 1.45M | 16384U, // REV |
6976 | 1.45M | 16384U, // REV16 |
6977 | 1.45M | 16384U, // REVSH |
6978 | 1.45M | 0U, // RFEDA |
6979 | 1.45M | 0U, // RFEDA_UPD |
6980 | 1.45M | 0U, // RFEDB |
6981 | 1.45M | 0U, // RFEDB_UPD |
6982 | 1.45M | 0U, // RFEIA |
6983 | 1.45M | 0U, // RFEIA_UPD |
6984 | 1.45M | 0U, // RFEIB |
6985 | 1.45M | 0U, // RFEIB_UPD |
6986 | 1.45M | 1048576U, // RSBri |
6987 | 1.45M | 0U, // RSBrr |
6988 | 1.45M | 1572864U, // RSBrsi |
6989 | 1.45M | 0U, // RSBrsr |
6990 | 1.45M | 1048576U, // RSCri |
6991 | 1.45M | 0U, // RSCrr |
6992 | 1.45M | 1572864U, // RSCrsi |
6993 | 1.45M | 0U, // RSCrsr |
6994 | 1.45M | 0U, // SADD16 |
6995 | 1.45M | 0U, // SADD8 |
6996 | 1.45M | 0U, // SASX |
6997 | 1.45M | 0U, // SB |
6998 | 1.45M | 1048576U, // SBCri |
6999 | 1.45M | 0U, // SBCrr |
7000 | 1.45M | 1572864U, // SBCrsi |
7001 | 1.45M | 0U, // SBCrsr |
7002 | 1.45M | 33554432U, // SBFX |
7003 | 1.45M | 0U, // SDIV |
7004 | 1.45M | 0U, // SEL |
7005 | 1.45M | 0U, // SETEND |
7006 | 1.45M | 0U, // SETPAN |
7007 | 1.45M | 16768U, // SHA1C |
7008 | 1.45M | 2U, // SHA1H |
7009 | 1.45M | 16768U, // SHA1M |
7010 | 1.45M | 16768U, // SHA1P |
7011 | 1.45M | 16768U, // SHA1SU0 |
7012 | 1.45M | 2U, // SHA1SU1 |
7013 | 1.45M | 16768U, // SHA256H |
7014 | 1.45M | 16768U, // SHA256H2 |
7015 | 1.45M | 2U, // SHA256SU0 |
7016 | 1.45M | 16768U, // SHA256SU1 |
7017 | 1.45M | 0U, // SHADD16 |
7018 | 1.45M | 0U, // SHADD8 |
7019 | 1.45M | 0U, // SHASX |
7020 | 1.45M | 0U, // SHSAX |
7021 | 1.45M | 0U, // SHSUB16 |
7022 | 1.45M | 0U, // SHSUB8 |
7023 | 1.45M | 2U, // SMC |
7024 | 1.45M | 33554432U, // SMLABB |
7025 | 1.45M | 33554432U, // SMLABT |
7026 | 1.45M | 33554432U, // SMLAD |
7027 | 1.45M | 33554432U, // SMLADX |
7028 | 1.45M | 0U, // SMLAL |
7029 | 1.45M | 33554432U, // SMLALBB |
7030 | 1.45M | 33554432U, // SMLALBT |
7031 | 1.45M | 33554432U, // SMLALD |
7032 | 1.45M | 33554432U, // SMLALDX |
7033 | 1.45M | 33554432U, // SMLALTB |
7034 | 1.45M | 33554432U, // SMLALTT |
7035 | 1.45M | 33554432U, // SMLATB |
7036 | 1.45M | 33554432U, // SMLATT |
7037 | 1.45M | 33554432U, // SMLAWB |
7038 | 1.45M | 33554432U, // SMLAWT |
7039 | 1.45M | 33554432U, // SMLSD |
7040 | 1.45M | 33554432U, // SMLSDX |
7041 | 1.45M | 33554432U, // SMLSLD |
7042 | 1.45M | 33554432U, // SMLSLDX |
7043 | 1.45M | 33554432U, // SMMLA |
7044 | 1.45M | 33554432U, // SMMLAR |
7045 | 1.45M | 33554432U, // SMMLS |
7046 | 1.45M | 33554432U, // SMMLSR |
7047 | 1.45M | 0U, // SMMUL |
7048 | 1.45M | 0U, // SMMULR |
7049 | 1.45M | 0U, // SMUAD |
7050 | 1.45M | 0U, // SMUADX |
7051 | 1.45M | 0U, // SMULBB |
7052 | 1.45M | 0U, // SMULBT |
7053 | 1.45M | 33554432U, // SMULL |
7054 | 1.45M | 0U, // SMULTB |
7055 | 1.45M | 0U, // SMULTT |
7056 | 1.45M | 0U, // SMULWB |
7057 | 1.45M | 0U, // SMULWT |
7058 | 1.45M | 0U, // SMUSD |
7059 | 1.45M | 0U, // SMUSDX |
7060 | 1.45M | 0U, // SRSDA |
7061 | 1.45M | 0U, // SRSDA_UPD |
7062 | 1.45M | 0U, // SRSDB |
7063 | 1.45M | 0U, // SRSDB_UPD |
7064 | 1.45M | 0U, // SRSIA |
7065 | 1.45M | 0U, // SRSIA_UPD |
7066 | 1.45M | 0U, // SRSIB |
7067 | 1.45M | 0U, // SRSIB_UPD |
7068 | 1.45M | 218112U, // SSAT |
7069 | 1.45M | 21504U, // SSAT16 |
7070 | 1.45M | 0U, // SSAX |
7071 | 1.45M | 0U, // SSUB16 |
7072 | 1.45M | 0U, // SSUB8 |
7073 | 1.45M | 0U, // STC2L_OFFSET |
7074 | 1.45M | 2304U, // STC2L_OPTION |
7075 | 1.45M | 2432U, // STC2L_POST |
7076 | 1.45M | 0U, // STC2L_PRE |
7077 | 1.45M | 0U, // STC2_OFFSET |
7078 | 1.45M | 2304U, // STC2_OPTION |
7079 | 1.45M | 2432U, // STC2_POST |
7080 | 1.45M | 0U, // STC2_PRE |
7081 | 1.45M | 2580U, // STCL_OFFSET |
7082 | 1.45M | 4721300U, // STCL_OPTION |
7083 | 1.45M | 5245588U, // STCL_POST |
7084 | 1.45M | 22U, // STCL_PRE |
7085 | 1.45M | 2580U, // STC_OFFSET |
7086 | 1.45M | 4721300U, // STC_OPTION |
7087 | 1.45M | 5245588U, // STC_POST |
7088 | 1.45M | 22U, // STC_PRE |
7089 | 1.45M | 128U, // STL |
7090 | 1.45M | 128U, // STLB |
7091 | 1.45M | 10485760U, // STLEX |
7092 | 1.45M | 10485760U, // STLEXB |
7093 | 1.45M | 5248U, // STLEXD |
7094 | 1.45M | 10485760U, // STLEXH |
7095 | 1.45M | 128U, // STLH |
7096 | 1.45M | 18560U, // STMDA |
7097 | 1.45M | 530U, // STMDA_UPD |
7098 | 1.45M | 18560U, // STMDB |
7099 | 1.45M | 530U, // STMDB_UPD |
7100 | 1.45M | 18560U, // STMIA |
7101 | 1.45M | 530U, // STMIA_UPD |
7102 | 1.45M | 18560U, // STMIB |
7103 | 1.45M | 530U, // STMIB_UPD |
7104 | 1.45M | 5769856U, // STRBT_POST_IMM |
7105 | 1.45M | 5769856U, // STRBT_POST_REG |
7106 | 1.45M | 5769856U, // STRB_POST_IMM |
7107 | 1.45M | 5769856U, // STRB_POST_REG |
7108 | 1.45M | 2816U, // STRB_PRE_IMM |
7109 | 1.45M | 2944U, // STRB_PRE_REG |
7110 | 1.45M | 3072U, // STRBi12 |
7111 | 1.45M | 3200U, // STRBrs |
7112 | 1.45M | 6291456U, // STRD |
7113 | 1.45M | 40371712U, // STRD_POST |
7114 | 1.45M | 7341568U, // STRD_PRE |
7115 | 1.45M | 10485760U, // STREX |
7116 | 1.45M | 10485760U, // STREXB |
7117 | 1.45M | 5248U, // STREXD |
7118 | 1.45M | 10485760U, // STREXH |
7119 | 1.45M | 3328U, // STRH |
7120 | 1.45M | 7867008U, // STRHTi |
7121 | 1.45M | 8391296U, // STRHTr |
7122 | 1.45M | 8915584U, // STRH_POST |
7123 | 1.45M | 3456U, // STRH_PRE |
7124 | 1.45M | 5769856U, // STRT_POST_IMM |
7125 | 1.45M | 5769856U, // STRT_POST_REG |
7126 | 1.45M | 5769856U, // STR_POST_IMM |
7127 | 1.45M | 5769856U, // STR_POST_REG |
7128 | 1.45M | 2816U, // STR_PRE_IMM |
7129 | 1.45M | 2944U, // STR_PRE_REG |
7130 | 1.45M | 3072U, // STRi12 |
7131 | 1.45M | 3200U, // STRrs |
7132 | 1.45M | 1048576U, // SUBri |
7133 | 1.45M | 0U, // SUBrr |
7134 | 1.45M | 1572864U, // SUBrsi |
7135 | 1.45M | 0U, // SUBrsr |
7136 | 1.45M | 2U, // SVC |
7137 | 1.45M | 10485760U, // SWP |
7138 | 1.45M | 10485760U, // SWPB |
7139 | 1.45M | 268435456U, // SXTAB |
7140 | 1.45M | 268435456U, // SXTAB16 |
7141 | 1.45M | 268435456U, // SXTAH |
7142 | 1.45M | 229376U, // SXTB |
7143 | 1.45M | 229376U, // SXTB16 |
7144 | 1.45M | 229376U, // SXTH |
7145 | 1.45M | 1792U, // TEQri |
7146 | 1.45M | 16384U, // TEQrr |
7147 | 1.45M | 1920U, // TEQrsi |
7148 | 1.45M | 1152U, // TEQrsr |
7149 | 1.45M | 0U, // TRAP |
7150 | 1.45M | 0U, // TRAPNaCl |
7151 | 1.45M | 0U, // TSB |
7152 | 1.45M | 1792U, // TSTri |
7153 | 1.45M | 16384U, // TSTrr |
7154 | 1.45M | 1920U, // TSTrsi |
7155 | 1.45M | 1152U, // TSTrsr |
7156 | 1.45M | 0U, // UADD16 |
7157 | 1.45M | 0U, // UADD8 |
7158 | 1.45M | 0U, // UASX |
7159 | 1.45M | 33554432U, // UBFX |
7160 | 1.45M | 0U, // UDF |
7161 | 1.45M | 0U, // UDIV |
7162 | 1.45M | 0U, // UHADD16 |
7163 | 1.45M | 0U, // UHADD8 |
7164 | 1.45M | 0U, // UHASX |
7165 | 1.45M | 0U, // UHSAX |
7166 | 1.45M | 0U, // UHSUB16 |
7167 | 1.45M | 0U, // UHSUB8 |
7168 | 1.45M | 33554432U, // UMAAL |
7169 | 1.45M | 0U, // UMLAL |
7170 | 1.45M | 33554432U, // UMULL |
7171 | 1.45M | 0U, // UQADD16 |
7172 | 1.45M | 0U, // UQADD8 |
7173 | 1.45M | 0U, // UQASX |
7174 | 1.45M | 0U, // UQSAX |
7175 | 1.45M | 0U, // UQSUB16 |
7176 | 1.45M | 0U, // UQSUB8 |
7177 | 1.45M | 0U, // USAD8 |
7178 | 1.45M | 33554432U, // USADA8 |
7179 | 1.45M | 301989888U, // USAT |
7180 | 1.45M | 0U, // USAT16 |
7181 | 1.45M | 0U, // USAX |
7182 | 1.45M | 0U, // USUB16 |
7183 | 1.45M | 0U, // USUB8 |
7184 | 1.45M | 268435456U, // UXTAB |
7185 | 1.45M | 268435456U, // UXTAB16 |
7186 | 1.45M | 268435456U, // UXTAH |
7187 | 1.45M | 229376U, // UXTB |
7188 | 1.45M | 229376U, // UXTB16 |
7189 | 1.45M | 229376U, // UXTH |
7190 | 1.45M | 3671552U, // VABALsv2i64 |
7191 | 1.45M | 3671552U, // VABALsv4i32 |
7192 | 1.45M | 3671552U, // VABALsv8i16 |
7193 | 1.45M | 3671552U, // VABALuv2i64 |
7194 | 1.45M | 3671552U, // VABALuv4i32 |
7195 | 1.45M | 3671552U, // VABALuv8i16 |
7196 | 1.45M | 3671552U, // VABAsv16i8 |
7197 | 1.45M | 3671552U, // VABAsv2i32 |
7198 | 1.45M | 3671552U, // VABAsv4i16 |
7199 | 1.45M | 3671552U, // VABAsv4i32 |
7200 | 1.45M | 3671552U, // VABAsv8i16 |
7201 | 1.45M | 3671552U, // VABAsv8i8 |
7202 | 1.45M | 3671552U, // VABAuv16i8 |
7203 | 1.45M | 3671552U, // VABAuv2i32 |
7204 | 1.45M | 3671552U, // VABAuv4i16 |
7205 | 1.45M | 3671552U, // VABAuv4i32 |
7206 | 1.45M | 3671552U, // VABAuv8i16 |
7207 | 1.45M | 3671552U, // VABAuv8i8 |
7208 | 1.45M | 0U, // VABDLsv2i64 |
7209 | 1.45M | 0U, // VABDLsv4i32 |
7210 | 1.45M | 0U, // VABDLsv8i16 |
7211 | 1.45M | 0U, // VABDLuv2i64 |
7212 | 1.45M | 0U, // VABDLuv4i32 |
7213 | 1.45M | 0U, // VABDLuv8i16 |
7214 | 1.45M | 0U, // VABDfd |
7215 | 1.45M | 0U, // VABDfq |
7216 | 1.45M | 0U, // VABDhd |
7217 | 1.45M | 0U, // VABDhq |
7218 | 1.45M | 0U, // VABDsv16i8 |
7219 | 1.45M | 0U, // VABDsv2i32 |
7220 | 1.45M | 0U, // VABDsv4i16 |
7221 | 1.45M | 0U, // VABDsv4i32 |
7222 | 1.45M | 0U, // VABDsv8i16 |
7223 | 1.45M | 0U, // VABDsv8i8 |
7224 | 1.45M | 0U, // VABDuv16i8 |
7225 | 1.45M | 0U, // VABDuv2i32 |
7226 | 1.45M | 0U, // VABDuv4i16 |
7227 | 1.45M | 0U, // VABDuv4i32 |
7228 | 1.45M | 0U, // VABDuv8i16 |
7229 | 1.45M | 0U, // VABDuv8i8 |
7230 | 1.45M | 526U, // VABSD |
7231 | 1.45M | 16384U, // VABSH |
7232 | 1.45M | 16384U, // VABSS |
7233 | 1.45M | 16384U, // VABSfd |
7234 | 1.45M | 16384U, // VABSfq |
7235 | 1.45M | 16384U, // VABShd |
7236 | 1.45M | 16384U, // VABShq |
7237 | 1.45M | 16384U, // VABSv16i8 |
7238 | 1.45M | 16384U, // VABSv2i32 |
7239 | 1.45M | 16384U, // VABSv4i16 |
7240 | 1.45M | 16384U, // VABSv4i32 |
7241 | 1.45M | 16384U, // VABSv8i16 |
7242 | 1.45M | 16384U, // VABSv8i8 |
7243 | 1.45M | 0U, // VACGEfd |
7244 | 1.45M | 0U, // VACGEfq |
7245 | 1.45M | 0U, // VACGEhd |
7246 | 1.45M | 0U, // VACGEhq |
7247 | 1.45M | 0U, // VACGTfd |
7248 | 1.45M | 0U, // VACGTfq |
7249 | 1.45M | 0U, // VACGThd |
7250 | 1.45M | 0U, // VACGThq |
7251 | 1.45M | 2212622U, // VADDD |
7252 | 1.45M | 0U, // VADDH |
7253 | 1.45M | 17920U, // VADDHNv2i32 |
7254 | 1.45M | 0U, // VADDHNv4i16 |
7255 | 1.45M | 0U, // VADDHNv8i8 |
7256 | 1.45M | 0U, // VADDLsv2i64 |
7257 | 1.45M | 0U, // VADDLsv4i32 |
7258 | 1.45M | 0U, // VADDLsv8i16 |
7259 | 1.45M | 0U, // VADDLuv2i64 |
7260 | 1.45M | 0U, // VADDLuv4i32 |
7261 | 1.45M | 0U, // VADDLuv8i16 |
7262 | 1.45M | 0U, // VADDS |
7263 | 1.45M | 0U, // VADDWsv2i64 |
7264 | 1.45M | 0U, // VADDWsv4i32 |
7265 | 1.45M | 0U, // VADDWsv8i16 |
7266 | 1.45M | 0U, // VADDWuv2i64 |
7267 | 1.45M | 0U, // VADDWuv4i32 |
7268 | 1.45M | 0U, // VADDWuv8i16 |
7269 | 1.45M | 0U, // VADDfd |
7270 | 1.45M | 0U, // VADDfq |
7271 | 1.45M | 0U, // VADDhd |
7272 | 1.45M | 0U, // VADDhq |
7273 | 1.45M | 0U, // VADDv16i8 |
7274 | 1.45M | 17920U, // VADDv1i64 |
7275 | 1.45M | 0U, // VADDv2i32 |
7276 | 1.45M | 17920U, // VADDv2i64 |
7277 | 1.45M | 0U, // VADDv4i16 |
7278 | 1.45M | 0U, // VADDv4i32 |
7279 | 1.45M | 0U, // VADDv8i16 |
7280 | 1.45M | 0U, // VADDv8i8 |
7281 | 1.45M | 0U, // VANDd |
7282 | 1.45M | 0U, // VANDq |
7283 | 1.45M | 16768U, // VBF16MALBQ |
7284 | 1.45M | 2163072U, // VBF16MALBQI |
7285 | 1.45M | 16768U, // VBF16MALTQ |
7286 | 1.45M | 2163072U, // VBF16MALTQI |
7287 | 1.45M | 0U, // VBICd |
7288 | 1.45M | 4864U, // VBICiv2i32 |
7289 | 1.45M | 4864U, // VBICiv4i16 |
7290 | 1.45M | 4864U, // VBICiv4i32 |
7291 | 1.45M | 4864U, // VBICiv8i16 |
7292 | 1.45M | 0U, // VBICq |
7293 | 1.45M | 3671552U, // VBIFd |
7294 | 1.45M | 3671552U, // VBIFq |
7295 | 1.45M | 3671552U, // VBITd |
7296 | 1.45M | 3671552U, // VBITq |
7297 | 1.45M | 3671552U, // VBSLd |
7298 | 1.45M | 3671552U, // VBSLq |
7299 | 1.45M | 0U, // VBSPd |
7300 | 1.45M | 0U, // VBSPq |
7301 | 1.45M | 11011584U, // VCADDv2f32 |
7302 | 1.45M | 11011584U, // VCADDv4f16 |
7303 | 1.45M | 11011584U, // VCADDv4f32 |
7304 | 1.45M | 11011584U, // VCADDv8f16 |
7305 | 1.45M | 0U, // VCEQfd |
7306 | 1.45M | 0U, // VCEQfq |
7307 | 1.45M | 0U, // VCEQhd |
7308 | 1.45M | 0U, // VCEQhq |
7309 | 1.45M | 0U, // VCEQv16i8 |
7310 | 1.45M | 0U, // VCEQv2i32 |
7311 | 1.45M | 0U, // VCEQv4i16 |
7312 | 1.45M | 0U, // VCEQv4i32 |
7313 | 1.45M | 0U, // VCEQv8i16 |
7314 | 1.45M | 0U, // VCEQv8i8 |
7315 | 1.45M | 245760U, // VCEQzv16i8 |
7316 | 1.45M | 245760U, // VCEQzv2f32 |
7317 | 1.45M | 245760U, // VCEQzv2i32 |
7318 | 1.45M | 245760U, // VCEQzv4f16 |
7319 | 1.45M | 245760U, // VCEQzv4f32 |
7320 | 1.45M | 245760U, // VCEQzv4i16 |
7321 | 1.45M | 245760U, // VCEQzv4i32 |
7322 | 1.45M | 245760U, // VCEQzv8f16 |
7323 | 1.45M | 245760U, // VCEQzv8i16 |
7324 | 1.45M | 245760U, // VCEQzv8i8 |
7325 | 1.45M | 0U, // VCGEfd |
7326 | 1.45M | 0U, // VCGEfq |
7327 | 1.45M | 0U, // VCGEhd |
7328 | 1.45M | 0U, // VCGEhq |
7329 | 1.45M | 0U, // VCGEsv16i8 |
7330 | 1.45M | 0U, // VCGEsv2i32 |
7331 | 1.45M | 0U, // VCGEsv4i16 |
7332 | 1.45M | 0U, // VCGEsv4i32 |
7333 | 1.45M | 0U, // VCGEsv8i16 |
7334 | 1.45M | 0U, // VCGEsv8i8 |
7335 | 1.45M | 0U, // VCGEuv16i8 |
7336 | 1.45M | 0U, // VCGEuv2i32 |
7337 | 1.45M | 0U, // VCGEuv4i16 |
7338 | 1.45M | 0U, // VCGEuv4i32 |
7339 | 1.45M | 0U, // VCGEuv8i16 |
7340 | 1.45M | 0U, // VCGEuv8i8 |
7341 | 1.45M | 245760U, // VCGEzv16i8 |
7342 | 1.45M | 245760U, // VCGEzv2f32 |
7343 | 1.45M | 245760U, // VCGEzv2i32 |
7344 | 1.45M | 245760U, // VCGEzv4f16 |
7345 | 1.45M | 245760U, // VCGEzv4f32 |
7346 | 1.45M | 245760U, // VCGEzv4i16 |
7347 | 1.45M | 245760U, // VCGEzv4i32 |
7348 | 1.45M | 245760U, // VCGEzv8f16 |
7349 | 1.45M | 245760U, // VCGEzv8i16 |
7350 | 1.45M | 245760U, // VCGEzv8i8 |
7351 | 1.45M | 0U, // VCGTfd |
7352 | 1.45M | 0U, // VCGTfq |
7353 | 1.45M | 0U, // VCGThd |
7354 | 1.45M | 0U, // VCGThq |
7355 | 1.45M | 0U, // VCGTsv16i8 |
7356 | 1.45M | 0U, // VCGTsv2i32 |
7357 | 1.45M | 0U, // VCGTsv4i16 |
7358 | 1.45M | 0U, // VCGTsv4i32 |
7359 | 1.45M | 0U, // VCGTsv8i16 |
7360 | 1.45M | 0U, // VCGTsv8i8 |
7361 | 1.45M | 0U, // VCGTuv16i8 |
7362 | 1.45M | 0U, // VCGTuv2i32 |
7363 | 1.45M | 0U, // VCGTuv4i16 |
7364 | 1.45M | 0U, // VCGTuv4i32 |
7365 | 1.45M | 0U, // VCGTuv8i16 |
7366 | 1.45M | 0U, // VCGTuv8i8 |
7367 | 1.45M | 245760U, // VCGTzv16i8 |
7368 | 1.45M | 245760U, // VCGTzv2f32 |
7369 | 1.45M | 245760U, // VCGTzv2i32 |
7370 | 1.45M | 245760U, // VCGTzv4f16 |
7371 | 1.45M | 245760U, // VCGTzv4f32 |
7372 | 1.45M | 245760U, // VCGTzv4i16 |
7373 | 1.45M | 245760U, // VCGTzv4i32 |
7374 | 1.45M | 245760U, // VCGTzv8f16 |
7375 | 1.45M | 245760U, // VCGTzv8i16 |
7376 | 1.45M | 245760U, // VCGTzv8i8 |
7377 | 1.45M | 245760U, // VCLEzv16i8 |
7378 | 1.45M | 245760U, // VCLEzv2f32 |
7379 | 1.45M | 245760U, // VCLEzv2i32 |
7380 | 1.45M | 245760U, // VCLEzv4f16 |
7381 | 1.45M | 245760U, // VCLEzv4f32 |
7382 | 1.45M | 245760U, // VCLEzv4i16 |
7383 | 1.45M | 245760U, // VCLEzv4i32 |
7384 | 1.45M | 245760U, // VCLEzv8f16 |
7385 | 1.45M | 245760U, // VCLEzv8i16 |
7386 | 1.45M | 245760U, // VCLEzv8i8 |
7387 | 1.45M | 16384U, // VCLSv16i8 |
7388 | 1.45M | 16384U, // VCLSv2i32 |
7389 | 1.45M | 16384U, // VCLSv4i16 |
7390 | 1.45M | 16384U, // VCLSv4i32 |
7391 | 1.45M | 16384U, // VCLSv8i16 |
7392 | 1.45M | 16384U, // VCLSv8i8 |
7393 | 1.45M | 245760U, // VCLTzv16i8 |
7394 | 1.45M | 245760U, // VCLTzv2f32 |
7395 | 1.45M | 245760U, // VCLTzv2i32 |
7396 | 1.45M | 245760U, // VCLTzv4f16 |
7397 | 1.45M | 245760U, // VCLTzv4f32 |
7398 | 1.45M | 245760U, // VCLTzv4i16 |
7399 | 1.45M | 245760U, // VCLTzv4i32 |
7400 | 1.45M | 245760U, // VCLTzv8f16 |
7401 | 1.45M | 245760U, // VCLTzv8i16 |
7402 | 1.45M | 245760U, // VCLTzv8i8 |
7403 | 1.45M | 16384U, // VCLZv16i8 |
7404 | 1.45M | 16384U, // VCLZv2i32 |
7405 | 1.45M | 16384U, // VCLZv4i16 |
7406 | 1.45M | 16384U, // VCLZv4i32 |
7407 | 1.45M | 16384U, // VCLZv8i16 |
7408 | 1.45M | 16384U, // VCLZv8i8 |
7409 | 1.45M | 11534720U, // VCMLAv2f32 |
7410 | 1.45M | 338755968U, // VCMLAv2f32_indexed |
7411 | 1.45M | 11534720U, // VCMLAv4f16 |
7412 | 1.45M | 338755968U, // VCMLAv4f16_indexed |
7413 | 1.45M | 11534720U, // VCMLAv4f32 |
7414 | 1.45M | 338755968U, // VCMLAv4f32_indexed |
7415 | 1.45M | 11534720U, // VCMLAv8f16 |
7416 | 1.45M | 338755968U, // VCMLAv8f16_indexed |
7417 | 1.45M | 526U, // VCMPD |
7418 | 1.45M | 526U, // VCMPED |
7419 | 1.45M | 16384U, // VCMPEH |
7420 | 1.45M | 16384U, // VCMPES |
7421 | 1.45M | 0U, // VCMPEZD |
7422 | 1.45M | 36U, // VCMPEZH |
7423 | 1.45M | 36U, // VCMPEZS |
7424 | 1.45M | 16384U, // VCMPH |
7425 | 1.45M | 16384U, // VCMPS |
7426 | 1.45M | 0U, // VCMPZD |
7427 | 1.45M | 36U, // VCMPZH |
7428 | 1.45M | 36U, // VCMPZS |
7429 | 1.45M | 16384U, // VCNTd |
7430 | 1.45M | 16384U, // VCNTq |
7431 | 1.45M | 2U, // VCVTANSDf |
7432 | 1.45M | 2U, // VCVTANSDh |
7433 | 1.45M | 2U, // VCVTANSQf |
7434 | 1.45M | 2U, // VCVTANSQh |
7435 | 1.45M | 2U, // VCVTANUDf |
7436 | 1.45M | 2U, // VCVTANUDh |
7437 | 1.45M | 2U, // VCVTANUQf |
7438 | 1.45M | 2U, // VCVTANUQh |
7439 | 1.45M | 2U, // VCVTASD |
7440 | 1.45M | 2U, // VCVTASH |
7441 | 1.45M | 2U, // VCVTASS |
7442 | 1.45M | 2U, // VCVTAUD |
7443 | 1.45M | 2U, // VCVTAUH |
7444 | 1.45M | 2U, // VCVTAUS |
7445 | 1.45M | 0U, // VCVTBDH |
7446 | 1.45M | 0U, // VCVTBHD |
7447 | 1.45M | 0U, // VCVTBHS |
7448 | 1.45M | 2U, // VCVTBSH |
7449 | 1.45M | 0U, // VCVTDS |
7450 | 1.45M | 2U, // VCVTMNSDf |
7451 | 1.45M | 2U, // VCVTMNSDh |
7452 | 1.45M | 2U, // VCVTMNSQf |
7453 | 1.45M | 2U, // VCVTMNSQh |
7454 | 1.45M | 2U, // VCVTMNUDf |
7455 | 1.45M | 2U, // VCVTMNUDh |
7456 | 1.45M | 2U, // VCVTMNUQf |
7457 | 1.45M | 2U, // VCVTMNUQh |
7458 | 1.45M | 2U, // VCVTMSD |
7459 | 1.45M | 2U, // VCVTMSH |
7460 | 1.45M | 2U, // VCVTMSS |
7461 | 1.45M | 2U, // VCVTMUD |
7462 | 1.45M | 2U, // VCVTMUH |
7463 | 1.45M | 2U, // VCVTMUS |
7464 | 1.45M | 2U, // VCVTNNSDf |
7465 | 1.45M | 2U, // VCVTNNSDh |
7466 | 1.45M | 2U, // VCVTNNSQf |
7467 | 1.45M | 2U, // VCVTNNSQh |
7468 | 1.45M | 2U, // VCVTNNUDf |
7469 | 1.45M | 2U, // VCVTNNUDh |
7470 | 1.45M | 2U, // VCVTNNUQf |
7471 | 1.45M | 2U, // VCVTNNUQh |
7472 | 1.45M | 2U, // VCVTNSD |
7473 | 1.45M | 2U, // VCVTNSH |
7474 | 1.45M | 2U, // VCVTNSS |
7475 | 1.45M | 2U, // VCVTNUD |
7476 | 1.45M | 2U, // VCVTNUH |
7477 | 1.45M | 2U, // VCVTNUS |
7478 | 1.45M | 2U, // VCVTPNSDf |
7479 | 1.45M | 2U, // VCVTPNSDh |
7480 | 1.45M | 2U, // VCVTPNSQf |
7481 | 1.45M | 2U, // VCVTPNSQh |
7482 | 1.45M | 2U, // VCVTPNUDf |
7483 | 1.45M | 2U, // VCVTPNUDh |
7484 | 1.45M | 2U, // VCVTPNUQf |
7485 | 1.45M | 2U, // VCVTPNUQh |
7486 | 1.45M | 2U, // VCVTPSD |
7487 | 1.45M | 2U, // VCVTPSH |
7488 | 1.45M | 2U, // VCVTPSS |
7489 | 1.45M | 2U, // VCVTPUD |
7490 | 1.45M | 2U, // VCVTPUH |
7491 | 1.45M | 2U, // VCVTPUS |
7492 | 1.45M | 0U, // VCVTSD |
7493 | 1.45M | 0U, // VCVTTDH |
7494 | 1.45M | 0U, // VCVTTHD |
7495 | 1.45M | 0U, // VCVTTHS |
7496 | 1.45M | 2U, // VCVTTSH |
7497 | 1.45M | 2U, // VCVTf2h |
7498 | 1.45M | 0U, // VCVTf2sd |
7499 | 1.45M | 0U, // VCVTf2sq |
7500 | 1.45M | 0U, // VCVTf2ud |
7501 | 1.45M | 0U, // VCVTf2uq |
7502 | 1.45M | 536U, // VCVTf2xsd |
7503 | 1.45M | 536U, // VCVTf2xsq |
7504 | 1.45M | 536U, // VCVTf2xud |
7505 | 1.45M | 536U, // VCVTf2xuq |
7506 | 1.45M | 0U, // VCVTh2f |
7507 | 1.45M | 0U, // VCVTh2sd |
7508 | 1.45M | 0U, // VCVTh2sq |
7509 | 1.45M | 0U, // VCVTh2ud |
7510 | 1.45M | 0U, // VCVTh2uq |
7511 | 1.45M | 536U, // VCVTh2xsd |
7512 | 1.45M | 536U, // VCVTh2xsq |
7513 | 1.45M | 536U, // VCVTh2xud |
7514 | 1.45M | 536U, // VCVTh2xuq |
7515 | 1.45M | 0U, // VCVTs2fd |
7516 | 1.45M | 0U, // VCVTs2fq |
7517 | 1.45M | 0U, // VCVTs2hd |
7518 | 1.45M | 0U, // VCVTs2hq |
7519 | 1.45M | 0U, // VCVTu2fd |
7520 | 1.45M | 0U, // VCVTu2fq |
7521 | 1.45M | 0U, // VCVTu2hd |
7522 | 1.45M | 0U, // VCVTu2hq |
7523 | 1.45M | 536U, // VCVTxs2fd |
7524 | 1.45M | 536U, // VCVTxs2fq |
7525 | 1.45M | 536U, // VCVTxs2hd |
7526 | 1.45M | 536U, // VCVTxs2hq |
7527 | 1.45M | 536U, // VCVTxu2fd |
7528 | 1.45M | 536U, // VCVTxu2fq |
7529 | 1.45M | 536U, // VCVTxu2hd |
7530 | 1.45M | 536U, // VCVTxu2hq |
7531 | 1.45M | 2212622U, // VDIVD |
7532 | 1.45M | 0U, // VDIVH |
7533 | 1.45M | 0U, // VDIVS |
7534 | 1.45M | 16384U, // VDUP16d |
7535 | 1.45M | 16384U, // VDUP16q |
7536 | 1.45M | 16384U, // VDUP32d |
7537 | 1.45M | 16384U, // VDUP32q |
7538 | 1.45M | 16384U, // VDUP8d |
7539 | 1.45M | 16384U, // VDUP8q |
7540 | 1.45M | 163840U, // VDUPLN16d |
7541 | 1.45M | 163840U, // VDUPLN16q |
7542 | 1.45M | 163840U, // VDUPLN32d |
7543 | 1.45M | 163840U, // VDUPLN32q |
7544 | 1.45M | 163840U, // VDUPLN8d |
7545 | 1.45M | 163840U, // VDUPLN8q |
7546 | 1.45M | 0U, // VEORd |
7547 | 1.45M | 0U, // VEORq |
7548 | 1.45M | 33554432U, // VEXTd16 |
7549 | 1.45M | 33554432U, // VEXTd32 |
7550 | 1.45M | 33554432U, // VEXTd8 |
7551 | 1.45M | 33554432U, // VEXTq16 |
7552 | 1.45M | 33554432U, // VEXTq32 |
7553 | 1.45M | 33554432U, // VEXTq64 |
7554 | 1.45M | 33554432U, // VEXTq8 |
7555 | 1.45M | 49944U, // VFMAD |
7556 | 1.45M | 3671552U, // VFMAH |
7557 | 1.45M | 17920U, // VFMALD |
7558 | 1.45M | 263680U, // VFMALDI |
7559 | 1.45M | 17920U, // VFMALQ |
7560 | 1.45M | 263680U, // VFMALQI |
7561 | 1.45M | 3671552U, // VFMAS |
7562 | 1.45M | 3671552U, // VFMAfd |
7563 | 1.45M | 3671552U, // VFMAfq |
7564 | 1.45M | 3671552U, // VFMAhd |
7565 | 1.45M | 3671552U, // VFMAhq |
7566 | 1.45M | 49944U, // VFMSD |
7567 | 1.45M | 3671552U, // VFMSH |
7568 | 1.45M | 17920U, // VFMSLD |
7569 | 1.45M | 263680U, // VFMSLDI |
7570 | 1.45M | 17920U, // VFMSLQ |
7571 | 1.45M | 263680U, // VFMSLQI |
7572 | 1.45M | 3671552U, // VFMSS |
7573 | 1.45M | 3671552U, // VFMSfd |
7574 | 1.45M | 3671552U, // VFMSfq |
7575 | 1.45M | 3671552U, // VFMShd |
7576 | 1.45M | 3671552U, // VFMShq |
7577 | 1.45M | 49944U, // VFNMAD |
7578 | 1.45M | 3671552U, // VFNMAH |
7579 | 1.45M | 3671552U, // VFNMAS |
7580 | 1.45M | 49944U, // VFNMSD |
7581 | 1.45M | 3671552U, // VFNMSH |
7582 | 1.45M | 3671552U, // VFNMSS |
7583 | 1.45M | 17920U, // VFP_VMAXNMD |
7584 | 1.45M | 17920U, // VFP_VMAXNMH |
7585 | 1.45M | 17920U, // VFP_VMAXNMS |
7586 | 1.45M | 17920U, // VFP_VMINNMD |
7587 | 1.45M | 17920U, // VFP_VMINNMH |
7588 | 1.45M | 17920U, // VFP_VMINNMS |
7589 | 1.45M | 163840U, // VGETLNi32 |
7590 | 1.45M | 163840U, // VGETLNs16 |
7591 | 1.45M | 163840U, // VGETLNs8 |
7592 | 1.45M | 163840U, // VGETLNu16 |
7593 | 1.45M | 163840U, // VGETLNu8 |
7594 | 1.45M | 0U, // VHADDsv16i8 |
7595 | 1.45M | 0U, // VHADDsv2i32 |
7596 | 1.45M | 0U, // VHADDsv4i16 |
7597 | 1.45M | 0U, // VHADDsv4i32 |
7598 | 1.45M | 0U, // VHADDsv8i16 |
7599 | 1.45M | 0U, // VHADDsv8i8 |
7600 | 1.45M | 0U, // VHADDuv16i8 |
7601 | 1.45M | 0U, // VHADDuv2i32 |
7602 | 1.45M | 0U, // VHADDuv4i16 |
7603 | 1.45M | 0U, // VHADDuv4i32 |
7604 | 1.45M | 0U, // VHADDuv8i16 |
7605 | 1.45M | 0U, // VHADDuv8i8 |
7606 | 1.45M | 0U, // VHSUBsv16i8 |
7607 | 1.45M | 0U, // VHSUBsv2i32 |
7608 | 1.45M | 0U, // VHSUBsv4i16 |
7609 | 1.45M | 0U, // VHSUBsv4i32 |
7610 | 1.45M | 0U, // VHSUBsv8i16 |
7611 | 1.45M | 0U, // VHSUBsv8i8 |
7612 | 1.45M | 0U, // VHSUBuv16i8 |
7613 | 1.45M | 0U, // VHSUBuv2i32 |
7614 | 1.45M | 0U, // VHSUBuv4i16 |
7615 | 1.45M | 0U, // VHSUBuv4i32 |
7616 | 1.45M | 0U, // VHSUBuv8i16 |
7617 | 1.45M | 0U, // VHSUBuv8i8 |
7618 | 1.45M | 2U, // VINSH |
7619 | 1.45M | 0U, // VJCVT |
7620 | 1.45M | 518U, // VLD1DUPd16 |
7621 | 1.45M | 678U, // VLD1DUPd16wb_fixed |
7622 | 1.45M | 2179878U, // VLD1DUPd16wb_register |
7623 | 1.45M | 518U, // VLD1DUPd32 |
7624 | 1.45M | 678U, // VLD1DUPd32wb_fixed |
7625 | 1.45M | 2179878U, // VLD1DUPd32wb_register |
7626 | 1.45M | 518U, // VLD1DUPd8 |
7627 | 1.45M | 678U, // VLD1DUPd8wb_fixed |
7628 | 1.45M | 2179878U, // VLD1DUPd8wb_register |
7629 | 1.45M | 518U, // VLD1DUPq16 |
7630 | 1.45M | 678U, // VLD1DUPq16wb_fixed |
7631 | 1.45M | 2179878U, // VLD1DUPq16wb_register |
7632 | 1.45M | 518U, // VLD1DUPq32 |
7633 | 1.45M | 678U, // VLD1DUPq32wb_fixed |
7634 | 1.45M | 2179878U, // VLD1DUPq32wb_register |
7635 | 1.45M | 518U, // VLD1DUPq8 |
7636 | 1.45M | 678U, // VLD1DUPq8wb_fixed |
7637 | 1.45M | 2179878U, // VLD1DUPq8wb_register |
7638 | 1.45M | 12342568U, // VLD1LNd16 |
7639 | 1.45M | 12866984U, // VLD1LNd16_UPD |
7640 | 1.45M | 12342568U, // VLD1LNd32 |
7641 | 1.45M | 12866984U, // VLD1LNd32_UPD |
7642 | 1.45M | 12342568U, // VLD1LNd8 |
7643 | 1.45M | 12866984U, // VLD1LNd8_UPD |
7644 | 1.45M | 0U, // VLD1LNq16Pseudo |
7645 | 1.45M | 0U, // VLD1LNq16Pseudo_UPD |
7646 | 1.45M | 0U, // VLD1LNq32Pseudo |
7647 | 1.45M | 0U, // VLD1LNq32Pseudo_UPD |
7648 | 1.45M | 0U, // VLD1LNq8Pseudo |
7649 | 1.45M | 0U, // VLD1LNq8Pseudo_UPD |
7650 | 1.45M | 518U, // VLD1d16 |
7651 | 1.45M | 518U, // VLD1d16Q |
7652 | 1.45M | 0U, // VLD1d16QPseudo |
7653 | 1.45M | 0U, // VLD1d16QPseudoWB_fixed |
7654 | 1.45M | 0U, // VLD1d16QPseudoWB_register |
7655 | 1.45M | 678U, // VLD1d16Qwb_fixed |
7656 | 1.45M | 2179878U, // VLD1d16Qwb_register |
7657 | 1.45M | 518U, // VLD1d16T |
7658 | 1.45M | 0U, // VLD1d16TPseudo |
7659 | 1.45M | 0U, // VLD1d16TPseudoWB_fixed |
7660 | 1.45M | 0U, // VLD1d16TPseudoWB_register |
7661 | 1.45M | 678U, // VLD1d16Twb_fixed |
7662 | 1.45M | 2179878U, // VLD1d16Twb_register |
7663 | 1.45M | 678U, // VLD1d16wb_fixed |
7664 | 1.45M | 2179878U, // VLD1d16wb_register |
7665 | 1.45M | 518U, // VLD1d32 |
7666 | 1.45M | 518U, // VLD1d32Q |
7667 | 1.45M | 0U, // VLD1d32QPseudo |
7668 | 1.45M | 0U, // VLD1d32QPseudoWB_fixed |
7669 | 1.45M | 0U, // VLD1d32QPseudoWB_register |
7670 | 1.45M | 678U, // VLD1d32Qwb_fixed |
7671 | 1.45M | 2179878U, // VLD1d32Qwb_register |
7672 | 1.45M | 518U, // VLD1d32T |
7673 | 1.45M | 0U, // VLD1d32TPseudo |
7674 | 1.45M | 0U, // VLD1d32TPseudoWB_fixed |
7675 | 1.45M | 0U, // VLD1d32TPseudoWB_register |
7676 | 1.45M | 678U, // VLD1d32Twb_fixed |
7677 | 1.45M | 2179878U, // VLD1d32Twb_register |
7678 | 1.45M | 678U, // VLD1d32wb_fixed |
7679 | 1.45M | 2179878U, // VLD1d32wb_register |
7680 | 1.45M | 518U, // VLD1d64 |
7681 | 1.45M | 518U, // VLD1d64Q |
7682 | 1.45M | 0U, // VLD1d64QPseudo |
7683 | 1.45M | 0U, // VLD1d64QPseudoWB_fixed |
7684 | 1.45M | 0U, // VLD1d64QPseudoWB_register |
7685 | 1.45M | 678U, // VLD1d64Qwb_fixed |
7686 | 1.45M | 2179878U, // VLD1d64Qwb_register |
7687 | 1.45M | 518U, // VLD1d64T |
7688 | 1.45M | 0U, // VLD1d64TPseudo |
7689 | 1.45M | 0U, // VLD1d64TPseudoWB_fixed |
7690 | 1.45M | 0U, // VLD1d64TPseudoWB_register |
7691 | 1.45M | 678U, // VLD1d64Twb_fixed |
7692 | 1.45M | 2179878U, // VLD1d64Twb_register |
7693 | 1.45M | 678U, // VLD1d64wb_fixed |
7694 | 1.45M | 2179878U, // VLD1d64wb_register |
7695 | 1.45M | 518U, // VLD1d8 |
7696 | 1.45M | 518U, // VLD1d8Q |
7697 | 1.45M | 0U, // VLD1d8QPseudo |
7698 | 1.45M | 0U, // VLD1d8QPseudoWB_fixed |
7699 | 1.45M | 0U, // VLD1d8QPseudoWB_register |
7700 | 1.45M | 678U, // VLD1d8Qwb_fixed |
7701 | 1.45M | 2179878U, // VLD1d8Qwb_register |
7702 | 1.45M | 518U, // VLD1d8T |
7703 | 1.45M | 0U, // VLD1d8TPseudo |
7704 | 1.45M | 0U, // VLD1d8TPseudoWB_fixed |
7705 | 1.45M | 0U, // VLD1d8TPseudoWB_register |
7706 | 1.45M | 678U, // VLD1d8Twb_fixed |
7707 | 1.45M | 2179878U, // VLD1d8Twb_register |
7708 | 1.45M | 678U, // VLD1d8wb_fixed |
7709 | 1.45M | 2179878U, // VLD1d8wb_register |
7710 | 1.45M | 518U, // VLD1q16 |
7711 | 1.45M | 0U, // VLD1q16HighQPseudo |
7712 | 1.45M | 0U, // VLD1q16HighQPseudo_UPD |
7713 | 1.45M | 0U, // VLD1q16HighTPseudo |
7714 | 1.45M | 0U, // VLD1q16HighTPseudo_UPD |
7715 | 1.45M | 0U, // VLD1q16LowQPseudo_UPD |
7716 | 1.45M | 0U, // VLD1q16LowTPseudo_UPD |
7717 | 1.45M | 678U, // VLD1q16wb_fixed |
7718 | 1.45M | 2179878U, // VLD1q16wb_register |
7719 | 1.45M | 518U, // VLD1q32 |
7720 | 1.45M | 0U, // VLD1q32HighQPseudo |
7721 | 1.45M | 0U, // VLD1q32HighQPseudo_UPD |
7722 | 1.45M | 0U, // VLD1q32HighTPseudo |
7723 | 1.45M | 0U, // VLD1q32HighTPseudo_UPD |
7724 | 1.45M | 0U, // VLD1q32LowQPseudo_UPD |
7725 | 1.45M | 0U, // VLD1q32LowTPseudo_UPD |
7726 | 1.45M | 678U, // VLD1q32wb_fixed |
7727 | 1.45M | 2179878U, // VLD1q32wb_register |
7728 | 1.45M | 518U, // VLD1q64 |
7729 | 1.45M | 0U, // VLD1q64HighQPseudo |
7730 | 1.45M | 0U, // VLD1q64HighQPseudo_UPD |
7731 | 1.45M | 0U, // VLD1q64HighTPseudo |
7732 | 1.45M | 0U, // VLD1q64HighTPseudo_UPD |
7733 | 1.45M | 0U, // VLD1q64LowQPseudo_UPD |
7734 | 1.45M | 0U, // VLD1q64LowTPseudo_UPD |
7735 | 1.45M | 678U, // VLD1q64wb_fixed |
7736 | 1.45M | 2179878U, // VLD1q64wb_register |
7737 | 1.45M | 518U, // VLD1q8 |
7738 | 1.45M | 0U, // VLD1q8HighQPseudo |
7739 | 1.45M | 0U, // VLD1q8HighQPseudo_UPD |
7740 | 1.45M | 0U, // VLD1q8HighTPseudo |
7741 | 1.45M | 0U, // VLD1q8HighTPseudo_UPD |
7742 | 1.45M | 0U, // VLD1q8LowQPseudo_UPD |
7743 | 1.45M | 0U, // VLD1q8LowTPseudo_UPD |
7744 | 1.45M | 678U, // VLD1q8wb_fixed |
7745 | 1.45M | 2179878U, // VLD1q8wb_register |
7746 | 1.45M | 518U, // VLD2DUPd16 |
7747 | 1.45M | 678U, // VLD2DUPd16wb_fixed |
7748 | 1.45M | 2179878U, // VLD2DUPd16wb_register |
7749 | 1.45M | 518U, // VLD2DUPd16x2 |
7750 | 1.45M | 678U, // VLD2DUPd16x2wb_fixed |
7751 | 1.45M | 2179878U, // VLD2DUPd16x2wb_register |
7752 | 1.45M | 518U, // VLD2DUPd32 |
7753 | 1.45M | 678U, // VLD2DUPd32wb_fixed |
7754 | 1.45M | 2179878U, // VLD2DUPd32wb_register |
7755 | 1.45M | 518U, // VLD2DUPd32x2 |
7756 | 1.45M | 678U, // VLD2DUPd32x2wb_fixed |
7757 | 1.45M | 2179878U, // VLD2DUPd32x2wb_register |
7758 | 1.45M | 518U, // VLD2DUPd8 |
7759 | 1.45M | 678U, // VLD2DUPd8wb_fixed |
7760 | 1.45M | 2179878U, // VLD2DUPd8wb_register |
7761 | 1.45M | 518U, // VLD2DUPd8x2 |
7762 | 1.45M | 678U, // VLD2DUPd8x2wb_fixed |
7763 | 1.45M | 2179878U, // VLD2DUPd8x2wb_register |
7764 | 1.45M | 0U, // VLD2DUPq16EvenPseudo |
7765 | 1.45M | 0U, // VLD2DUPq16OddPseudo |
7766 | 1.45M | 0U, // VLD2DUPq16OddPseudoWB_fixed |
7767 | 1.45M | 0U, // VLD2DUPq16OddPseudoWB_register |
7768 | 1.45M | 0U, // VLD2DUPq32EvenPseudo |
7769 | 1.45M | 0U, // VLD2DUPq32OddPseudo |
7770 | 1.45M | 0U, // VLD2DUPq32OddPseudoWB_fixed |
7771 | 1.45M | 0U, // VLD2DUPq32OddPseudoWB_register |
7772 | 1.45M | 0U, // VLD2DUPq8EvenPseudo |
7773 | 1.45M | 0U, // VLD2DUPq8OddPseudo |
7774 | 1.45M | 0U, // VLD2DUPq8OddPseudoWB_fixed |
7775 | 1.45M | 0U, // VLD2DUPq8OddPseudoWB_register |
7776 | 1.45M | 13407656U, // VLD2LNd16 |
7777 | 1.45M | 0U, // VLD2LNd16Pseudo |
7778 | 1.45M | 0U, // VLD2LNd16Pseudo_UPD |
7779 | 1.45M | 13948456U, // VLD2LNd16_UPD |
7780 | 1.45M | 13407656U, // VLD2LNd32 |
7781 | 1.45M | 0U, // VLD2LNd32Pseudo |
7782 | 1.45M | 0U, // VLD2LNd32Pseudo_UPD |
7783 | 1.45M | 13948456U, // VLD2LNd32_UPD |
7784 | 1.45M | 13407656U, // VLD2LNd8 |
7785 | 1.45M | 0U, // VLD2LNd8Pseudo |
7786 | 1.45M | 0U, // VLD2LNd8Pseudo_UPD |
7787 | 1.45M | 13948456U, // VLD2LNd8_UPD |
7788 | 1.45M | 13407656U, // VLD2LNq16 |
7789 | 1.45M | 0U, // VLD2LNq16Pseudo |
7790 | 1.45M | 0U, // VLD2LNq16Pseudo_UPD |
7791 | 1.45M | 13948456U, // VLD2LNq16_UPD |
7792 | 1.45M | 13407656U, // VLD2LNq32 |
7793 | 1.45M | 0U, // VLD2LNq32Pseudo |
7794 | 1.45M | 0U, // VLD2LNq32Pseudo_UPD |
7795 | 1.45M | 13948456U, // VLD2LNq32_UPD |
7796 | 1.45M | 518U, // VLD2b16 |
7797 | 1.45M | 678U, // VLD2b16wb_fixed |
7798 | 1.45M | 2179878U, // VLD2b16wb_register |
7799 | 1.45M | 518U, // VLD2b32 |
7800 | 1.45M | 678U, // VLD2b32wb_fixed |
7801 | 1.45M | 2179878U, // VLD2b32wb_register |
7802 | 1.45M | 518U, // VLD2b8 |
7803 | 1.45M | 678U, // VLD2b8wb_fixed |
7804 | 1.45M | 2179878U, // VLD2b8wb_register |
7805 | 1.45M | 518U, // VLD2d16 |
7806 | 1.45M | 678U, // VLD2d16wb_fixed |
7807 | 1.45M | 2179878U, // VLD2d16wb_register |
7808 | 1.45M | 518U, // VLD2d32 |
7809 | 1.45M | 678U, // VLD2d32wb_fixed |
7810 | 1.45M | 2179878U, // VLD2d32wb_register |
7811 | 1.45M | 518U, // VLD2d8 |
7812 | 1.45M | 678U, // VLD2d8wb_fixed |
7813 | 1.45M | 2179878U, // VLD2d8wb_register |
7814 | 1.45M | 518U, // VLD2q16 |
7815 | 1.45M | 0U, // VLD2q16Pseudo |
7816 | 1.45M | 0U, // VLD2q16PseudoWB_fixed |
7817 | 1.45M | 0U, // VLD2q16PseudoWB_register |
7818 | 1.45M | 678U, // VLD2q16wb_fixed |
7819 | 1.45M | 2179878U, // VLD2q16wb_register |
7820 | 1.45M | 518U, // VLD2q32 |
7821 | 1.45M | 0U, // VLD2q32Pseudo |
7822 | 1.45M | 0U, // VLD2q32PseudoWB_fixed |
7823 | 1.45M | 0U, // VLD2q32PseudoWB_register |
7824 | 1.45M | 678U, // VLD2q32wb_fixed |
7825 | 1.45M | 2179878U, // VLD2q32wb_register |
7826 | 1.45M | 518U, // VLD2q8 |
7827 | 1.45M | 0U, // VLD2q8Pseudo |
7828 | 1.45M | 0U, // VLD2q8PseudoWB_fixed |
7829 | 1.45M | 0U, // VLD2q8PseudoWB_register |
7830 | 1.45M | 678U, // VLD2q8wb_fixed |
7831 | 1.45M | 2179878U, // VLD2q8wb_register |
7832 | 1.45M | 333482U, // VLD3DUPd16 |
7833 | 1.45M | 0U, // VLD3DUPd16Pseudo |
7834 | 1.45M | 0U, // VLD3DUPd16Pseudo_UPD |
7835 | 1.45M | 14505642U, // VLD3DUPd16_UPD |
7836 | 1.45M | 333482U, // VLD3DUPd32 |
7837 | 1.45M | 0U, // VLD3DUPd32Pseudo |
7838 | 1.45M | 0U, // VLD3DUPd32Pseudo_UPD |
7839 | 1.45M | 14505642U, // VLD3DUPd32_UPD |
7840 | 1.45M | 333482U, // VLD3DUPd8 |
7841 | 1.45M | 0U, // VLD3DUPd8Pseudo |
7842 | 1.45M | 0U, // VLD3DUPd8Pseudo_UPD |
7843 | 1.45M | 14505642U, // VLD3DUPd8_UPD |
7844 | 1.45M | 333482U, // VLD3DUPq16 |
7845 | 1.45M | 0U, // VLD3DUPq16EvenPseudo |
7846 | 1.45M | 0U, // VLD3DUPq16OddPseudo |
7847 | 1.45M | 0U, // VLD3DUPq16OddPseudo_UPD |
7848 | 1.45M | 14505642U, // VLD3DUPq16_UPD |
7849 | 1.45M | 333482U, // VLD3DUPq32 |
7850 | 1.45M | 0U, // VLD3DUPq32EvenPseudo |
7851 | 1.45M | 0U, // VLD3DUPq32OddPseudo |
7852 | 1.45M | 0U, // VLD3DUPq32OddPseudo_UPD |
7853 | 1.45M | 14505642U, // VLD3DUPq32_UPD |
7854 | 1.45M | 333482U, // VLD3DUPq8 |
7855 | 1.45M | 0U, // VLD3DUPq8EvenPseudo |
7856 | 1.45M | 0U, // VLD3DUPq8OddPseudo |
7857 | 1.45M | 0U, // VLD3DUPq8OddPseudo_UPD |
7858 | 1.45M | 14505642U, // VLD3DUPq8_UPD |
7859 | 1.45M | 14997032U, // VLD3LNd16 |
7860 | 1.45M | 0U, // VLD3LNd16Pseudo |
7861 | 1.45M | 0U, // VLD3LNd16Pseudo_UPD |
7862 | 1.45M | 15488808U, // VLD3LNd16_UPD |
7863 | 1.45M | 14997032U, // VLD3LNd32 |
7864 | 1.45M | 0U, // VLD3LNd32Pseudo |
7865 | 1.45M | 0U, // VLD3LNd32Pseudo_UPD |
7866 | 1.45M | 15488808U, // VLD3LNd32_UPD |
7867 | 1.45M | 14997032U, // VLD3LNd8 |
7868 | 1.45M | 0U, // VLD3LNd8Pseudo |
7869 | 1.45M | 0U, // VLD3LNd8Pseudo_UPD |
7870 | 1.45M | 15488808U, // VLD3LNd8_UPD |
7871 | 1.45M | 14997032U, // VLD3LNq16 |
7872 | 1.45M | 0U, // VLD3LNq16Pseudo |
7873 | 1.45M | 0U, // VLD3LNq16Pseudo_UPD |
7874 | 1.45M | 15488808U, // VLD3LNq16_UPD |
7875 | 1.45M | 14997032U, // VLD3LNq32 |
7876 | 1.45M | 0U, // VLD3LNq32Pseudo |
7877 | 1.45M | 0U, // VLD3LNq32Pseudo_UPD |
7878 | 1.45M | 15488808U, // VLD3LNq32_UPD |
7879 | 1.45M | 369098752U, // VLD3d16 |
7880 | 1.45M | 0U, // VLD3d16Pseudo |
7881 | 1.45M | 0U, // VLD3d16Pseudo_UPD |
7882 | 1.45M | 369098752U, // VLD3d16_UPD |
7883 | 1.45M | 369098752U, // VLD3d32 |
7884 | 1.45M | 0U, // VLD3d32Pseudo |
7885 | 1.45M | 0U, // VLD3d32Pseudo_UPD |
7886 | 1.45M | 369098752U, // VLD3d32_UPD |
7887 | 1.45M | 369098752U, // VLD3d8 |
7888 | 1.45M | 0U, // VLD3d8Pseudo |
7889 | 1.45M | 0U, // VLD3d8Pseudo_UPD |
7890 | 1.45M | 369098752U, // VLD3d8_UPD |
7891 | 1.45M | 369098752U, // VLD3q16 |
7892 | 1.45M | 0U, // VLD3q16Pseudo_UPD |
7893 | 1.45M | 369098752U, // VLD3q16_UPD |
7894 | 1.45M | 0U, // VLD3q16oddPseudo |
7895 | 1.45M | 0U, // VLD3q16oddPseudo_UPD |
7896 | 1.45M | 369098752U, // VLD3q32 |
7897 | 1.45M | 0U, // VLD3q32Pseudo_UPD |
7898 | 1.45M | 369098752U, // VLD3q32_UPD |
7899 | 1.45M | 0U, // VLD3q32oddPseudo |
7900 | 1.45M | 0U, // VLD3q32oddPseudo_UPD |
7901 | 1.45M | 369098752U, // VLD3q8 |
7902 | 1.45M | 0U, // VLD3q8Pseudo_UPD |
7903 | 1.45M | 369098752U, // VLD3q8_UPD |
7904 | 1.45M | 0U, // VLD3q8oddPseudo |
7905 | 1.45M | 0U, // VLD3q8oddPseudo_UPD |
7906 | 1.45M | 2447274U, // VLD4DUPd16 |
7907 | 1.45M | 0U, // VLD4DUPd16Pseudo |
7908 | 1.45M | 0U, // VLD4DUPd16Pseudo_UPD |
7909 | 1.45M | 366506U, // VLD4DUPd16_UPD |
7910 | 1.45M | 2447274U, // VLD4DUPd32 |
7911 | 1.45M | 0U, // VLD4DUPd32Pseudo |
7912 | 1.45M | 0U, // VLD4DUPd32Pseudo_UPD |
7913 | 1.45M | 366506U, // VLD4DUPd32_UPD |
7914 | 1.45M | 2447274U, // VLD4DUPd8 |
7915 | 1.45M | 0U, // VLD4DUPd8Pseudo |
7916 | 1.45M | 0U, // VLD4DUPd8Pseudo_UPD |
7917 | 1.45M | 366506U, // VLD4DUPd8_UPD |
7918 | 1.45M | 2447274U, // VLD4DUPq16 |
7919 | 1.45M | 0U, // VLD4DUPq16EvenPseudo |
7920 | 1.45M | 0U, // VLD4DUPq16OddPseudo |
7921 | 1.45M | 0U, // VLD4DUPq16OddPseudo_UPD |
7922 | 1.45M | 366506U, // VLD4DUPq16_UPD |
7923 | 1.45M | 2447274U, // VLD4DUPq32 |
7924 | 1.45M | 0U, // VLD4DUPq32EvenPseudo |
7925 | 1.45M | 0U, // VLD4DUPq32OddPseudo |
7926 | 1.45M | 0U, // VLD4DUPq32OddPseudo_UPD |
7927 | 1.45M | 366506U, // VLD4DUPq32_UPD |
7928 | 1.45M | 2447274U, // VLD4DUPq8 |
7929 | 1.45M | 0U, // VLD4DUPq8EvenPseudo |
7930 | 1.45M | 0U, // VLD4DUPq8OddPseudo |
7931 | 1.45M | 0U, // VLD4DUPq8OddPseudo_UPD |
7932 | 1.45M | 366506U, // VLD4DUPq8_UPD |
7933 | 1.45M | 406624040U, // VLD4LNd16 |
7934 | 1.45M | 0U, // VLD4LNd16Pseudo |
7935 | 1.45M | 0U, // VLD4LNd16Pseudo_UPD |
7936 | 1.45M | 6184U, // VLD4LNd16_UPD |
7937 | 1.45M | 406624040U, // VLD4LNd32 |
7938 | 1.45M | 0U, // VLD4LNd32Pseudo |
7939 | 1.45M | 0U, // VLD4LNd32Pseudo_UPD |
7940 | 1.45M | 6184U, // VLD4LNd32_UPD |
7941 | 1.45M | 406624040U, // VLD4LNd8 |
7942 | 1.45M | 0U, // VLD4LNd8Pseudo |
7943 | 1.45M | 0U, // VLD4LNd8Pseudo_UPD |
7944 | 1.45M | 6184U, // VLD4LNd8_UPD |
7945 | 1.45M | 406624040U, // VLD4LNq16 |
7946 | 1.45M | 0U, // VLD4LNq16Pseudo |
7947 | 1.45M | 0U, // VLD4LNq16Pseudo_UPD |
7948 | 1.45M | 6184U, // VLD4LNq16_UPD |
7949 | 1.45M | 406624040U, // VLD4LNq32 |
7950 | 1.45M | 0U, // VLD4LNq32Pseudo |
7951 | 1.45M | 0U, // VLD4LNq32Pseudo_UPD |
7952 | 1.45M | 6184U, // VLD4LNq32_UPD |
7953 | 1.45M | 33554432U, // VLD4d16 |
7954 | 1.45M | 0U, // VLD4d16Pseudo |
7955 | 1.45M | 0U, // VLD4d16Pseudo_UPD |
7956 | 1.45M | 33554432U, // VLD4d16_UPD |
7957 | 1.45M | 33554432U, // VLD4d32 |
7958 | 1.45M | 0U, // VLD4d32Pseudo |
7959 | 1.45M | 0U, // VLD4d32Pseudo_UPD |
7960 | 1.45M | 33554432U, // VLD4d32_UPD |
7961 | 1.45M | 33554432U, // VLD4d8 |
7962 | 1.45M | 0U, // VLD4d8Pseudo |
7963 | 1.45M | 0U, // VLD4d8Pseudo_UPD |
7964 | 1.45M | 33554432U, // VLD4d8_UPD |
7965 | 1.45M | 33554432U, // VLD4q16 |
7966 | 1.45M | 0U, // VLD4q16Pseudo_UPD |
7967 | 1.45M | 33554432U, // VLD4q16_UPD |
7968 | 1.45M | 0U, // VLD4q16oddPseudo |
7969 | 1.45M | 0U, // VLD4q16oddPseudo_UPD |
7970 | 1.45M | 33554432U, // VLD4q32 |
7971 | 1.45M | 0U, // VLD4q32Pseudo_UPD |
7972 | 1.45M | 33554432U, // VLD4q32_UPD |
7973 | 1.45M | 0U, // VLD4q32oddPseudo |
7974 | 1.45M | 0U, // VLD4q32oddPseudo_UPD |
7975 | 1.45M | 33554432U, // VLD4q8 |
7976 | 1.45M | 0U, // VLD4q8Pseudo_UPD |
7977 | 1.45M | 33554432U, // VLD4q8_UPD |
7978 | 1.45M | 0U, // VLD4q8oddPseudo |
7979 | 1.45M | 0U, // VLD4q8oddPseudo_UPD |
7980 | 1.45M | 530U, // VLDMDDB_UPD |
7981 | 1.45M | 18560U, // VLDMDIA |
7982 | 1.45M | 530U, // VLDMDIA_UPD |
7983 | 1.45M | 0U, // VLDMQIA |
7984 | 1.45M | 530U, // VLDMSDB_UPD |
7985 | 1.45M | 18560U, // VLDMSIA |
7986 | 1.45M | 530U, // VLDMSIA_UPD |
7987 | 1.45M | 6272U, // VLDRD |
7988 | 1.45M | 6400U, // VLDRH |
7989 | 1.45M | 6272U, // VLDRS |
7990 | 1.45M | 0U, // VLDR_FPCXTNS_off |
7991 | 1.45M | 44U, // VLDR_FPCXTNS_post |
7992 | 1.45M | 0U, // VLDR_FPCXTNS_pre |
7993 | 1.45M | 0U, // VLDR_FPCXTS_off |
7994 | 1.45M | 44U, // VLDR_FPCXTS_post |
7995 | 1.45M | 0U, // VLDR_FPCXTS_pre |
7996 | 1.45M | 0U, // VLDR_FPSCR_NZCVQC_off |
7997 | 1.45M | 44U, // VLDR_FPSCR_NZCVQC_post |
7998 | 1.45M | 0U, // VLDR_FPSCR_NZCVQC_pre |
7999 | 1.45M | 0U, // VLDR_FPSCR_off |
8000 | 1.45M | 44U, // VLDR_FPSCR_post |
8001 | 1.45M | 0U, // VLDR_FPSCR_pre |
8002 | 1.45M | 0U, // VLDR_P0_off |
8003 | 1.45M | 46U, // VLDR_P0_post |
8004 | 1.45M | 0U, // VLDR_P0_pre |
8005 | 1.45M | 0U, // VLDR_VPR_off |
8006 | 1.45M | 44U, // VLDR_VPR_post |
8007 | 1.45M | 0U, // VLDR_VPR_pre |
8008 | 1.45M | 2U, // VLLDM |
8009 | 1.45M | 2U, // VLSTM |
8010 | 1.45M | 0U, // VMAXfd |
8011 | 1.45M | 0U, // VMAXfq |
8012 | 1.45M | 0U, // VMAXhd |
8013 | 1.45M | 0U, // VMAXhq |
8014 | 1.45M | 0U, // VMAXsv16i8 |
8015 | 1.45M | 0U, // VMAXsv2i32 |
8016 | 1.45M | 0U, // VMAXsv4i16 |
8017 | 1.45M | 0U, // VMAXsv4i32 |
8018 | 1.45M | 0U, // VMAXsv8i16 |
8019 | 1.45M | 0U, // VMAXsv8i8 |
8020 | 1.45M | 0U, // VMAXuv16i8 |
8021 | 1.45M | 0U, // VMAXuv2i32 |
8022 | 1.45M | 0U, // VMAXuv4i16 |
8023 | 1.45M | 0U, // VMAXuv4i32 |
8024 | 1.45M | 0U, // VMAXuv8i16 |
8025 | 1.45M | 0U, // VMAXuv8i8 |
8026 | 1.45M | 0U, // VMINfd |
8027 | 1.45M | 0U, // VMINfq |
8028 | 1.45M | 0U, // VMINhd |
8029 | 1.45M | 0U, // VMINhq |
8030 | 1.45M | 0U, // VMINsv16i8 |
8031 | 1.45M | 0U, // VMINsv2i32 |
8032 | 1.45M | 0U, // VMINsv4i16 |
8033 | 1.45M | 0U, // VMINsv4i32 |
8034 | 1.45M | 0U, // VMINsv8i16 |
8035 | 1.45M | 0U, // VMINsv8i8 |
8036 | 1.45M | 0U, // VMINuv16i8 |
8037 | 1.45M | 0U, // VMINuv2i32 |
8038 | 1.45M | 0U, // VMINuv4i16 |
8039 | 1.45M | 0U, // VMINuv4i32 |
8040 | 1.45M | 0U, // VMINuv8i16 |
8041 | 1.45M | 0U, // VMINuv8i8 |
8042 | 1.45M | 49944U, // VMLAD |
8043 | 1.45M | 3671552U, // VMLAH |
8044 | 1.45M | 439879168U, // VMLALslsv2i32 |
8045 | 1.45M | 439879168U, // VMLALslsv4i16 |
8046 | 1.45M | 439879168U, // VMLALsluv2i32 |
8047 | 1.45M | 439879168U, // VMLALsluv4i16 |
8048 | 1.45M | 3671552U, // VMLALsv2i64 |
8049 | 1.45M | 3671552U, // VMLALsv4i32 |
8050 | 1.45M | 3671552U, // VMLALsv8i16 |
8051 | 1.45M | 3671552U, // VMLALuv2i64 |
8052 | 1.45M | 3671552U, // VMLALuv4i32 |
8053 | 1.45M | 3671552U, // VMLALuv8i16 |
8054 | 1.45M | 3671552U, // VMLAS |
8055 | 1.45M | 3671552U, // VMLAfd |
8056 | 1.45M | 3671552U, // VMLAfq |
8057 | 1.45M | 3671552U, // VMLAhd |
8058 | 1.45M | 3671552U, // VMLAhq |
8059 | 1.45M | 439879168U, // VMLAslfd |
8060 | 1.45M | 439879168U, // VMLAslfq |
8061 | 1.45M | 439879168U, // VMLAslhd |
8062 | 1.45M | 439879168U, // VMLAslhq |
8063 | 1.45M | 439879168U, // VMLAslv2i32 |
8064 | 1.45M | 439879168U, // VMLAslv4i16 |
8065 | 1.45M | 439879168U, // VMLAslv4i32 |
8066 | 1.45M | 439879168U, // VMLAslv8i16 |
8067 | 1.45M | 3671552U, // VMLAv16i8 |
8068 | 1.45M | 3671552U, // VMLAv2i32 |
8069 | 1.45M | 3671552U, // VMLAv4i16 |
8070 | 1.45M | 3671552U, // VMLAv4i32 |
8071 | 1.45M | 3671552U, // VMLAv8i16 |
8072 | 1.45M | 3671552U, // VMLAv8i8 |
8073 | 1.45M | 49944U, // VMLSD |
8074 | 1.45M | 3671552U, // VMLSH |
8075 | 1.45M | 439879168U, // VMLSLslsv2i32 |
8076 | 1.45M | 439879168U, // VMLSLslsv4i16 |
8077 | 1.45M | 439879168U, // VMLSLsluv2i32 |
8078 | 1.45M | 439879168U, // VMLSLsluv4i16 |
8079 | 1.45M | 3671552U, // VMLSLsv2i64 |
8080 | 1.45M | 3671552U, // VMLSLsv4i32 |
8081 | 1.45M | 3671552U, // VMLSLsv8i16 |
8082 | 1.45M | 3671552U, // VMLSLuv2i64 |
8083 | 1.45M | 3671552U, // VMLSLuv4i32 |
8084 | 1.45M | 3671552U, // VMLSLuv8i16 |
8085 | 1.45M | 3671552U, // VMLSS |
8086 | 1.45M | 3671552U, // VMLSfd |
8087 | 1.45M | 3671552U, // VMLSfq |
8088 | 1.45M | 3671552U, // VMLShd |
8089 | 1.45M | 3671552U, // VMLShq |
8090 | 1.45M | 439879168U, // VMLSslfd |
8091 | 1.45M | 439879168U, // VMLSslfq |
8092 | 1.45M | 439879168U, // VMLSslhd |
8093 | 1.45M | 439879168U, // VMLSslhq |
8094 | 1.45M | 439879168U, // VMLSslv2i32 |
8095 | 1.45M | 439879168U, // VMLSslv4i16 |
8096 | 1.45M | 439879168U, // VMLSslv4i32 |
8097 | 1.45M | 439879168U, // VMLSslv8i16 |
8098 | 1.45M | 3671552U, // VMLSv16i8 |
8099 | 1.45M | 3671552U, // VMLSv2i32 |
8100 | 1.45M | 3671552U, // VMLSv4i16 |
8101 | 1.45M | 3671552U, // VMLSv4i32 |
8102 | 1.45M | 3671552U, // VMLSv8i16 |
8103 | 1.45M | 3671552U, // VMLSv8i8 |
8104 | 1.45M | 16768U, // VMMLA |
8105 | 1.45M | 526U, // VMOVD |
8106 | 1.45M | 0U, // VMOVDRR |
8107 | 1.45M | 2U, // VMOVH |
8108 | 1.45M | 16384U, // VMOVHR |
8109 | 1.45M | 16384U, // VMOVLsv2i64 |
8110 | 1.45M | 16384U, // VMOVLsv4i32 |
8111 | 1.45M | 16384U, // VMOVLsv8i16 |
8112 | 1.45M | 16384U, // VMOVLuv2i64 |
8113 | 1.45M | 16384U, // VMOVLuv4i32 |
8114 | 1.45M | 16384U, // VMOVLuv8i16 |
8115 | 1.45M | 2U, // VMOVNv2i32 |
8116 | 1.45M | 16384U, // VMOVNv4i16 |
8117 | 1.45M | 16384U, // VMOVNv8i8 |
8118 | 1.45M | 16384U, // VMOVRH |
8119 | 1.45M | 0U, // VMOVRRD |
8120 | 1.45M | 33554432U, // VMOVRRS |
8121 | 1.45M | 16384U, // VMOVRS |
8122 | 1.45M | 16384U, // VMOVS |
8123 | 1.45M | 16384U, // VMOVSR |
8124 | 1.45M | 33554432U, // VMOVSRR |
8125 | 1.45M | 4864U, // VMOVv16i8 |
8126 | 1.45M | 0U, // VMOVv1i64 |
8127 | 1.45M | 2048U, // VMOVv2f32 |
8128 | 1.45M | 4864U, // VMOVv2i32 |
8129 | 1.45M | 0U, // VMOVv2i64 |
8130 | 1.45M | 2048U, // VMOVv4f32 |
8131 | 1.45M | 4864U, // VMOVv4i16 |
8132 | 1.45M | 4864U, // VMOVv4i32 |
8133 | 1.45M | 4864U, // VMOVv8i16 |
8134 | 1.45M | 4864U, // VMOVv8i8 |
8135 | 1.45M | 48U, // VMRS |
8136 | 1.45M | 50U, // VMRS_FPCXTNS |
8137 | 1.45M | 52U, // VMRS_FPCXTS |
8138 | 1.45M | 54U, // VMRS_FPEXC |
8139 | 1.45M | 56U, // VMRS_FPINST |
8140 | 1.45M | 58U, // VMRS_FPINST2 |
8141 | 1.45M | 60U, // VMRS_FPSCR_NZCVQC |
8142 | 1.45M | 62U, // VMRS_FPSID |
8143 | 1.45M | 64U, // VMRS_MVFR0 |
8144 | 1.45M | 66U, // VMRS_MVFR1 |
8145 | 1.45M | 68U, // VMRS_MVFR2 |
8146 | 1.45M | 70U, // VMRS_P0 |
8147 | 1.45M | 72U, // VMRS_VPR |
8148 | 1.45M | 2U, // VMSR |
8149 | 1.45M | 2U, // VMSR_FPCXTNS |
8150 | 1.45M | 2U, // VMSR_FPCXTS |
8151 | 1.45M | 0U, // VMSR_FPEXC |
8152 | 1.45M | 0U, // VMSR_FPINST |
8153 | 1.45M | 0U, // VMSR_FPINST2 |
8154 | 1.45M | 2U, // VMSR_FPSCR_NZCVQC |
8155 | 1.45M | 0U, // VMSR_FPSID |
8156 | 1.45M | 2U, // VMSR_P0 |
8157 | 1.45M | 2U, // VMSR_VPR |
8158 | 1.45M | 2212622U, // VMULD |
8159 | 1.45M | 0U, // VMULH |
8160 | 1.45M | 17920U, // VMULLp64 |
8161 | 1.45M | 0U, // VMULLp8 |
8162 | 1.45M | 167772160U, // VMULLslsv2i32 |
8163 | 1.45M | 167772160U, // VMULLslsv4i16 |
8164 | 1.45M | 167772160U, // VMULLsluv2i32 |
8165 | 1.45M | 167772160U, // VMULLsluv4i16 |
8166 | 1.45M | 0U, // VMULLsv2i64 |
8167 | 1.45M | 0U, // VMULLsv4i32 |
8168 | 1.45M | 0U, // VMULLsv8i16 |
8169 | 1.45M | 0U, // VMULLuv2i64 |
8170 | 1.45M | 0U, // VMULLuv4i32 |
8171 | 1.45M | 0U, // VMULLuv8i16 |
8172 | 1.45M | 0U, // VMULS |
8173 | 1.45M | 0U, // VMULfd |
8174 | 1.45M | 0U, // VMULfq |
8175 | 1.45M | 0U, // VMULhd |
8176 | 1.45M | 0U, // VMULhq |
8177 | 1.45M | 0U, // VMULpd |
8178 | 1.45M | 0U, // VMULpq |
8179 | 1.45M | 167772160U, // VMULslfd |
8180 | 1.45M | 167772160U, // VMULslfq |
8181 | 1.45M | 167772160U, // VMULslhd |
8182 | 1.45M | 167772160U, // VMULslhq |
8183 | 1.45M | 167772160U, // VMULslv2i32 |
8184 | 1.45M | 167772160U, // VMULslv4i16 |
8185 | 1.45M | 167772160U, // VMULslv4i32 |
8186 | 1.45M | 167772160U, // VMULslv8i16 |
8187 | 1.45M | 0U, // VMULv16i8 |
8188 | 1.45M | 0U, // VMULv2i32 |
8189 | 1.45M | 0U, // VMULv4i16 |
8190 | 1.45M | 0U, // VMULv4i32 |
8191 | 1.45M | 0U, // VMULv8i16 |
8192 | 1.45M | 0U, // VMULv8i8 |
8193 | 1.45M | 16384U, // VMVNd |
8194 | 1.45M | 16384U, // VMVNq |
8195 | 1.45M | 4864U, // VMVNv2i32 |
8196 | 1.45M | 4864U, // VMVNv4i16 |
8197 | 1.45M | 4864U, // VMVNv4i32 |
8198 | 1.45M | 4864U, // VMVNv8i16 |
8199 | 1.45M | 526U, // VNEGD |
8200 | 1.45M | 16384U, // VNEGH |
8201 | 1.45M | 16384U, // VNEGS |
8202 | 1.45M | 16384U, // VNEGf32q |
8203 | 1.45M | 16384U, // VNEGfd |
8204 | 1.45M | 16384U, // VNEGhd |
8205 | 1.45M | 16384U, // VNEGhq |
8206 | 1.45M | 16384U, // VNEGs16d |
8207 | 1.45M | 16384U, // VNEGs16q |
8208 | 1.45M | 16384U, // VNEGs32d |
8209 | 1.45M | 16384U, // VNEGs32q |
8210 | 1.45M | 16384U, // VNEGs8d |
8211 | 1.45M | 16384U, // VNEGs8q |
8212 | 1.45M | 49944U, // VNMLAD |
8213 | 1.45M | 3671552U, // VNMLAH |
8214 | 1.45M | 3671552U, // VNMLAS |
8215 | 1.45M | 49944U, // VNMLSD |
8216 | 1.45M | 3671552U, // VNMLSH |
8217 | 1.45M | 3671552U, // VNMLSS |
8218 | 1.45M | 2212622U, // VNMULD |
8219 | 1.45M | 0U, // VNMULH |
8220 | 1.45M | 0U, // VNMULS |
8221 | 1.45M | 0U, // VORNd |
8222 | 1.45M | 0U, // VORNq |
8223 | 1.45M | 0U, // VORRd |
8224 | 1.45M | 4864U, // VORRiv2i32 |
8225 | 1.45M | 4864U, // VORRiv4i16 |
8226 | 1.45M | 4864U, // VORRiv4i32 |
8227 | 1.45M | 4864U, // VORRiv8i16 |
8228 | 1.45M | 0U, // VORRq |
8229 | 1.45M | 17920U, // VPADALsv16i8 |
8230 | 1.45M | 17920U, // VPADALsv2i32 |
8231 | 1.45M | 17920U, // VPADALsv4i16 |
8232 | 1.45M | 17920U, // VPADALsv4i32 |
8233 | 1.45M | 17920U, // VPADALsv8i16 |
8234 | 1.45M | 17920U, // VPADALsv8i8 |
8235 | 1.45M | 17920U, // VPADALuv16i8 |
8236 | 1.45M | 17920U, // VPADALuv2i32 |
8237 | 1.45M | 17920U, // VPADALuv4i16 |
8238 | 1.45M | 17920U, // VPADALuv4i32 |
8239 | 1.45M | 17920U, // VPADALuv8i16 |
8240 | 1.45M | 17920U, // VPADALuv8i8 |
8241 | 1.45M | 16384U, // VPADDLsv16i8 |
8242 | 1.45M | 16384U, // VPADDLsv2i32 |
8243 | 1.45M | 16384U, // VPADDLsv4i16 |
8244 | 1.45M | 16384U, // VPADDLsv4i32 |
8245 | 1.45M | 16384U, // VPADDLsv8i16 |
8246 | 1.45M | 16384U, // VPADDLsv8i8 |
8247 | 1.45M | 16384U, // VPADDLuv16i8 |
8248 | 1.45M | 16384U, // VPADDLuv2i32 |
8249 | 1.45M | 16384U, // VPADDLuv4i16 |
8250 | 1.45M | 16384U, // VPADDLuv4i32 |
8251 | 1.45M | 16384U, // VPADDLuv8i16 |
8252 | 1.45M | 16384U, // VPADDLuv8i8 |
8253 | 1.45M | 0U, // VPADDf |
8254 | 1.45M | 0U, // VPADDh |
8255 | 1.45M | 0U, // VPADDi16 |
8256 | 1.45M | 0U, // VPADDi32 |
8257 | 1.45M | 0U, // VPADDi8 |
8258 | 1.45M | 0U, // VPMAXf |
8259 | 1.45M | 0U, // VPMAXh |
8260 | 1.45M | 0U, // VPMAXs16 |
8261 | 1.45M | 0U, // VPMAXs32 |
8262 | 1.45M | 0U, // VPMAXs8 |
8263 | 1.45M | 0U, // VPMAXu16 |
8264 | 1.45M | 0U, // VPMAXu32 |
8265 | 1.45M | 0U, // VPMAXu8 |
8266 | 1.45M | 0U, // VPMINf |
8267 | 1.45M | 0U, // VPMINh |
8268 | 1.45M | 0U, // VPMINs16 |
8269 | 1.45M | 0U, // VPMINs32 |
8270 | 1.45M | 0U, // VPMINs8 |
8271 | 1.45M | 0U, // VPMINu16 |
8272 | 1.45M | 0U, // VPMINu32 |
8273 | 1.45M | 0U, // VPMINu8 |
8274 | 1.45M | 16384U, // VQABSv16i8 |
8275 | 1.45M | 16384U, // VQABSv2i32 |
8276 | 1.45M | 16384U, // VQABSv4i16 |
8277 | 1.45M | 16384U, // VQABSv4i32 |
8278 | 1.45M | 16384U, // VQABSv8i16 |
8279 | 1.45M | 16384U, // VQABSv8i8 |
8280 | 1.45M | 0U, // VQADDsv16i8 |
8281 | 1.45M | 17920U, // VQADDsv1i64 |
8282 | 1.45M | 0U, // VQADDsv2i32 |
8283 | 1.45M | 17920U, // VQADDsv2i64 |
8284 | 1.45M | 0U, // VQADDsv4i16 |
8285 | 1.45M | 0U, // VQADDsv4i32 |
8286 | 1.45M | 0U, // VQADDsv8i16 |
8287 | 1.45M | 0U, // VQADDsv8i8 |
8288 | 1.45M | 0U, // VQADDuv16i8 |
8289 | 1.45M | 0U, // VQADDuv1i64 |
8290 | 1.45M | 0U, // VQADDuv2i32 |
8291 | 1.45M | 0U, // VQADDuv2i64 |
8292 | 1.45M | 0U, // VQADDuv4i16 |
8293 | 1.45M | 0U, // VQADDuv4i32 |
8294 | 1.45M | 0U, // VQADDuv8i16 |
8295 | 1.45M | 0U, // VQADDuv8i8 |
8296 | 1.45M | 439879168U, // VQDMLALslv2i32 |
8297 | 1.45M | 439879168U, // VQDMLALslv4i16 |
8298 | 1.45M | 3671552U, // VQDMLALv2i64 |
8299 | 1.45M | 3671552U, // VQDMLALv4i32 |
8300 | 1.45M | 439879168U, // VQDMLSLslv2i32 |
8301 | 1.45M | 439879168U, // VQDMLSLslv4i16 |
8302 | 1.45M | 3671552U, // VQDMLSLv2i64 |
8303 | 1.45M | 3671552U, // VQDMLSLv4i32 |
8304 | 1.45M | 167772160U, // VQDMULHslv2i32 |
8305 | 1.45M | 167772160U, // VQDMULHslv4i16 |
8306 | 1.45M | 167772160U, // VQDMULHslv4i32 |
8307 | 1.45M | 167772160U, // VQDMULHslv8i16 |
8308 | 1.45M | 0U, // VQDMULHv2i32 |
8309 | 1.45M | 0U, // VQDMULHv4i16 |
8310 | 1.45M | 0U, // VQDMULHv4i32 |
8311 | 1.45M | 0U, // VQDMULHv8i16 |
8312 | 1.45M | 167772160U, // VQDMULLslv2i32 |
8313 | 1.45M | 167772160U, // VQDMULLslv4i16 |
8314 | 1.45M | 0U, // VQDMULLv2i64 |
8315 | 1.45M | 0U, // VQDMULLv4i32 |
8316 | 1.45M | 2U, // VQMOVNsuv2i32 |
8317 | 1.45M | 16384U, // VQMOVNsuv4i16 |
8318 | 1.45M | 16384U, // VQMOVNsuv8i8 |
8319 | 1.45M | 2U, // VQMOVNsv2i32 |
8320 | 1.45M | 16384U, // VQMOVNsv4i16 |
8321 | 1.45M | 16384U, // VQMOVNsv8i8 |
8322 | 1.45M | 16384U, // VQMOVNuv2i32 |
8323 | 1.45M | 16384U, // VQMOVNuv4i16 |
8324 | 1.45M | 16384U, // VQMOVNuv8i8 |
8325 | 1.45M | 16384U, // VQNEGv16i8 |
8326 | 1.45M | 16384U, // VQNEGv2i32 |
8327 | 1.45M | 16384U, // VQNEGv4i16 |
8328 | 1.45M | 16384U, // VQNEGv4i32 |
8329 | 1.45M | 16384U, // VQNEGv8i16 |
8330 | 1.45M | 16384U, // VQNEGv8i8 |
8331 | 1.45M | 439879168U, // VQRDMLAHslv2i32 |
8332 | 1.45M | 439879168U, // VQRDMLAHslv4i16 |
8333 | 1.45M | 439879168U, // VQRDMLAHslv4i32 |
8334 | 1.45M | 439879168U, // VQRDMLAHslv8i16 |
8335 | 1.45M | 3671552U, // VQRDMLAHv2i32 |
8336 | 1.45M | 3671552U, // VQRDMLAHv4i16 |
8337 | 1.45M | 3671552U, // VQRDMLAHv4i32 |
8338 | 1.45M | 3671552U, // VQRDMLAHv8i16 |
8339 | 1.45M | 439879168U, // VQRDMLSHslv2i32 |
8340 | 1.45M | 439879168U, // VQRDMLSHslv4i16 |
8341 | 1.45M | 439879168U, // VQRDMLSHslv4i32 |
8342 | 1.45M | 439879168U, // VQRDMLSHslv8i16 |
8343 | 1.45M | 3671552U, // VQRDMLSHv2i32 |
8344 | 1.45M | 3671552U, // VQRDMLSHv4i16 |
8345 | 1.45M | 3671552U, // VQRDMLSHv4i32 |
8346 | 1.45M | 3671552U, // VQRDMLSHv8i16 |
8347 | 1.45M | 167772160U, // VQRDMULHslv2i32 |
8348 | 1.45M | 167772160U, // VQRDMULHslv4i16 |
8349 | 1.45M | 167772160U, // VQRDMULHslv4i32 |
8350 | 1.45M | 167772160U, // VQRDMULHslv8i16 |
8351 | 1.45M | 0U, // VQRDMULHv2i32 |
8352 | 1.45M | 0U, // VQRDMULHv4i16 |
8353 | 1.45M | 0U, // VQRDMULHv4i32 |
8354 | 1.45M | 0U, // VQRDMULHv8i16 |
8355 | 1.45M | 0U, // VQRSHLsv16i8 |
8356 | 1.45M | 17920U, // VQRSHLsv1i64 |
8357 | 1.45M | 0U, // VQRSHLsv2i32 |
8358 | 1.45M | 17920U, // VQRSHLsv2i64 |
8359 | 1.45M | 0U, // VQRSHLsv4i16 |
8360 | 1.45M | 0U, // VQRSHLsv4i32 |
8361 | 1.45M | 0U, // VQRSHLsv8i16 |
8362 | 1.45M | 0U, // VQRSHLsv8i8 |
8363 | 1.45M | 0U, // VQRSHLuv16i8 |
8364 | 1.45M | 0U, // VQRSHLuv1i64 |
8365 | 1.45M | 0U, // VQRSHLuv2i32 |
8366 | 1.45M | 0U, // VQRSHLuv2i64 |
8367 | 1.45M | 0U, // VQRSHLuv4i16 |
8368 | 1.45M | 0U, // VQRSHLuv4i32 |
8369 | 1.45M | 0U, // VQRSHLuv8i16 |
8370 | 1.45M | 0U, // VQRSHLuv8i8 |
8371 | 1.45M | 17920U, // VQRSHRNsv2i32 |
8372 | 1.45M | 0U, // VQRSHRNsv4i16 |
8373 | 1.45M | 0U, // VQRSHRNsv8i8 |
8374 | 1.45M | 0U, // VQRSHRNuv2i32 |
8375 | 1.45M | 0U, // VQRSHRNuv4i16 |
8376 | 1.45M | 0U, // VQRSHRNuv8i8 |
8377 | 1.45M | 17920U, // VQRSHRUNv2i32 |
8378 | 1.45M | 0U, // VQRSHRUNv4i16 |
8379 | 1.45M | 0U, // VQRSHRUNv8i8 |
8380 | 1.45M | 0U, // VQSHLsiv16i8 |
8381 | 1.45M | 17920U, // VQSHLsiv1i64 |
8382 | 1.45M | 0U, // VQSHLsiv2i32 |
8383 | 1.45M | 17920U, // VQSHLsiv2i64 |
8384 | 1.45M | 0U, // VQSHLsiv4i16 |
8385 | 1.45M | 0U, // VQSHLsiv4i32 |
8386 | 1.45M | 0U, // VQSHLsiv8i16 |
8387 | 1.45M | 0U, // VQSHLsiv8i8 |
8388 | 1.45M | 0U, // VQSHLsuv16i8 |
8389 | 1.45M | 17920U, // VQSHLsuv1i64 |
8390 | 1.45M | 0U, // VQSHLsuv2i32 |
8391 | 1.45M | 17920U, // VQSHLsuv2i64 |
8392 | 1.45M | 0U, // VQSHLsuv4i16 |
8393 | 1.45M | 0U, // VQSHLsuv4i32 |
8394 | 1.45M | 0U, // VQSHLsuv8i16 |
8395 | 1.45M | 0U, // VQSHLsuv8i8 |
8396 | 1.45M | 0U, // VQSHLsv16i8 |
8397 | 1.45M | 17920U, // VQSHLsv1i64 |
8398 | 1.45M | 0U, // VQSHLsv2i32 |
8399 | 1.45M | 17920U, // VQSHLsv2i64 |
8400 | 1.45M | 0U, // VQSHLsv4i16 |
8401 | 1.45M | 0U, // VQSHLsv4i32 |
8402 | 1.45M | 0U, // VQSHLsv8i16 |
8403 | 1.45M | 0U, // VQSHLsv8i8 |
8404 | 1.45M | 0U, // VQSHLuiv16i8 |
8405 | 1.45M | 0U, // VQSHLuiv1i64 |
8406 | 1.45M | 0U, // VQSHLuiv2i32 |
8407 | 1.45M | 0U, // VQSHLuiv2i64 |
8408 | 1.45M | 0U, // VQSHLuiv4i16 |
8409 | 1.45M | 0U, // VQSHLuiv4i32 |
8410 | 1.45M | 0U, // VQSHLuiv8i16 |
8411 | 1.45M | 0U, // VQSHLuiv8i8 |
8412 | 1.45M | 0U, // VQSHLuv16i8 |
8413 | 1.45M | 0U, // VQSHLuv1i64 |
8414 | 1.45M | 0U, // VQSHLuv2i32 |
8415 | 1.45M | 0U, // VQSHLuv2i64 |
8416 | 1.45M | 0U, // VQSHLuv4i16 |
8417 | 1.45M | 0U, // VQSHLuv4i32 |
8418 | 1.45M | 0U, // VQSHLuv8i16 |
8419 | 1.45M | 0U, // VQSHLuv8i8 |
8420 | 1.45M | 17920U, // VQSHRNsv2i32 |
8421 | 1.45M | 0U, // VQSHRNsv4i16 |
8422 | 1.45M | 0U, // VQSHRNsv8i8 |
8423 | 1.45M | 0U, // VQSHRNuv2i32 |
8424 | 1.45M | 0U, // VQSHRNuv4i16 |
8425 | 1.45M | 0U, // VQSHRNuv8i8 |
8426 | 1.45M | 17920U, // VQSHRUNv2i32 |
8427 | 1.45M | 0U, // VQSHRUNv4i16 |
8428 | 1.45M | 0U, // VQSHRUNv8i8 |
8429 | 1.45M | 0U, // VQSUBsv16i8 |
8430 | 1.45M | 17920U, // VQSUBsv1i64 |
8431 | 1.45M | 0U, // VQSUBsv2i32 |
8432 | 1.45M | 17920U, // VQSUBsv2i64 |
8433 | 1.45M | 0U, // VQSUBsv4i16 |
8434 | 1.45M | 0U, // VQSUBsv4i32 |
8435 | 1.45M | 0U, // VQSUBsv8i16 |
8436 | 1.45M | 0U, // VQSUBsv8i8 |
8437 | 1.45M | 0U, // VQSUBuv16i8 |
8438 | 1.45M | 0U, // VQSUBuv1i64 |
8439 | 1.45M | 0U, // VQSUBuv2i32 |
8440 | 1.45M | 0U, // VQSUBuv2i64 |
8441 | 1.45M | 0U, // VQSUBuv4i16 |
8442 | 1.45M | 0U, // VQSUBuv4i32 |
8443 | 1.45M | 0U, // VQSUBuv8i16 |
8444 | 1.45M | 0U, // VQSUBuv8i8 |
8445 | 1.45M | 17920U, // VRADDHNv2i32 |
8446 | 1.45M | 0U, // VRADDHNv4i16 |
8447 | 1.45M | 0U, // VRADDHNv8i8 |
8448 | 1.45M | 16384U, // VRECPEd |
8449 | 1.45M | 16384U, // VRECPEfd |
8450 | 1.45M | 16384U, // VRECPEfq |
8451 | 1.45M | 16384U, // VRECPEhd |
8452 | 1.45M | 16384U, // VRECPEhq |
8453 | 1.45M | 16384U, // VRECPEq |
8454 | 1.45M | 0U, // VRECPSfd |
8455 | 1.45M | 0U, // VRECPSfq |
8456 | 1.45M | 0U, // VRECPShd |
8457 | 1.45M | 0U, // VRECPShq |
8458 | 1.45M | 16384U, // VREV16d8 |
8459 | 1.45M | 16384U, // VREV16q8 |
8460 | 1.45M | 16384U, // VREV32d16 |
8461 | 1.45M | 16384U, // VREV32d8 |
8462 | 1.45M | 16384U, // VREV32q16 |
8463 | 1.45M | 16384U, // VREV32q8 |
8464 | 1.45M | 16384U, // VREV64d16 |
8465 | 1.45M | 16384U, // VREV64d32 |
8466 | 1.45M | 16384U, // VREV64d8 |
8467 | 1.45M | 16384U, // VREV64q16 |
8468 | 1.45M | 16384U, // VREV64q32 |
8469 | 1.45M | 16384U, // VREV64q8 |
8470 | 1.45M | 0U, // VRHADDsv16i8 |
8471 | 1.45M | 0U, // VRHADDsv2i32 |
8472 | 1.45M | 0U, // VRHADDsv4i16 |
8473 | 1.45M | 0U, // VRHADDsv4i32 |
8474 | 1.45M | 0U, // VRHADDsv8i16 |
8475 | 1.45M | 0U, // VRHADDsv8i8 |
8476 | 1.45M | 0U, // VRHADDuv16i8 |
8477 | 1.45M | 0U, // VRHADDuv2i32 |
8478 | 1.45M | 0U, // VRHADDuv4i16 |
8479 | 1.45M | 0U, // VRHADDuv4i32 |
8480 | 1.45M | 0U, // VRHADDuv8i16 |
8481 | 1.45M | 0U, // VRHADDuv8i8 |
8482 | 1.45M | 2U, // VRINTAD |
8483 | 1.45M | 2U, // VRINTAH |
8484 | 1.45M | 2U, // VRINTANDf |
8485 | 1.45M | 2U, // VRINTANDh |
8486 | 1.45M | 2U, // VRINTANQf |
8487 | 1.45M | 2U, // VRINTANQh |
8488 | 1.45M | 2U, // VRINTAS |
8489 | 1.45M | 2U, // VRINTMD |
8490 | 1.45M | 2U, // VRINTMH |
8491 | 1.45M | 2U, // VRINTMNDf |
8492 | 1.45M | 2U, // VRINTMNDh |
8493 | 1.45M | 2U, // VRINTMNQf |
8494 | 1.45M | 2U, // VRINTMNQh |
8495 | 1.45M | 2U, // VRINTMS |
8496 | 1.45M | 2U, // VRINTND |
8497 | 1.45M | 2U, // VRINTNH |
8498 | 1.45M | 2U, // VRINTNNDf |
8499 | 1.45M | 2U, // VRINTNNDh |
8500 | 1.45M | 2U, // VRINTNNQf |
8501 | 1.45M | 2U, // VRINTNNQh |
8502 | 1.45M | 2U, // VRINTNS |
8503 | 1.45M | 2U, // VRINTPD |
8504 | 1.45M | 2U, // VRINTPH |
8505 | 1.45M | 2U, // VRINTPNDf |
8506 | 1.45M | 2U, // VRINTPNDh |
8507 | 1.45M | 2U, // VRINTPNQf |
8508 | 1.45M | 2U, // VRINTPNQh |
8509 | 1.45M | 2U, // VRINTPS |
8510 | 1.45M | 526U, // VRINTRD |
8511 | 1.45M | 16384U, // VRINTRH |
8512 | 1.45M | 16384U, // VRINTRS |
8513 | 1.45M | 526U, // VRINTXD |
8514 | 1.45M | 16384U, // VRINTXH |
8515 | 1.45M | 2U, // VRINTXNDf |
8516 | 1.45M | 2U, // VRINTXNDh |
8517 | 1.45M | 2U, // VRINTXNQf |
8518 | 1.45M | 2U, // VRINTXNQh |
8519 | 1.45M | 16384U, // VRINTXS |
8520 | 1.45M | 526U, // VRINTZD |
8521 | 1.45M | 16384U, // VRINTZH |
8522 | 1.45M | 2U, // VRINTZNDf |
8523 | 1.45M | 2U, // VRINTZNDh |
8524 | 1.45M | 2U, // VRINTZNQf |
8525 | 1.45M | 2U, // VRINTZNQh |
8526 | 1.45M | 16384U, // VRINTZS |
8527 | 1.45M | 0U, // VRSHLsv16i8 |
8528 | 1.45M | 17920U, // VRSHLsv1i64 |
8529 | 1.45M | 0U, // VRSHLsv2i32 |
8530 | 1.45M | 17920U, // VRSHLsv2i64 |
8531 | 1.45M | 0U, // VRSHLsv4i16 |
8532 | 1.45M | 0U, // VRSHLsv4i32 |
8533 | 1.45M | 0U, // VRSHLsv8i16 |
8534 | 1.45M | 0U, // VRSHLsv8i8 |
8535 | 1.45M | 0U, // VRSHLuv16i8 |
8536 | 1.45M | 0U, // VRSHLuv1i64 |
8537 | 1.45M | 0U, // VRSHLuv2i32 |
8538 | 1.45M | 0U, // VRSHLuv2i64 |
8539 | 1.45M | 0U, // VRSHLuv4i16 |
8540 | 1.45M | 0U, // VRSHLuv4i32 |
8541 | 1.45M | 0U, // VRSHLuv8i16 |
8542 | 1.45M | 0U, // VRSHLuv8i8 |
8543 | 1.45M | 17920U, // VRSHRNv2i32 |
8544 | 1.45M | 0U, // VRSHRNv4i16 |
8545 | 1.45M | 0U, // VRSHRNv8i8 |
8546 | 1.45M | 0U, // VRSHRsv16i8 |
8547 | 1.45M | 17920U, // VRSHRsv1i64 |
8548 | 1.45M | 0U, // VRSHRsv2i32 |
8549 | 1.45M | 17920U, // VRSHRsv2i64 |
8550 | 1.45M | 0U, // VRSHRsv4i16 |
8551 | 1.45M | 0U, // VRSHRsv4i32 |
8552 | 1.45M | 0U, // VRSHRsv8i16 |
8553 | 1.45M | 0U, // VRSHRsv8i8 |
8554 | 1.45M | 0U, // VRSHRuv16i8 |
8555 | 1.45M | 0U, // VRSHRuv1i64 |
8556 | 1.45M | 0U, // VRSHRuv2i32 |
8557 | 1.45M | 0U, // VRSHRuv2i64 |
8558 | 1.45M | 0U, // VRSHRuv4i16 |
8559 | 1.45M | 0U, // VRSHRuv4i32 |
8560 | 1.45M | 0U, // VRSHRuv8i16 |
8561 | 1.45M | 0U, // VRSHRuv8i8 |
8562 | 1.45M | 16384U, // VRSQRTEd |
8563 | 1.45M | 16384U, // VRSQRTEfd |
8564 | 1.45M | 16384U, // VRSQRTEfq |
8565 | 1.45M | 16384U, // VRSQRTEhd |
8566 | 1.45M | 16384U, // VRSQRTEhq |
8567 | 1.45M | 16384U, // VRSQRTEq |
8568 | 1.45M | 0U, // VRSQRTSfd |
8569 | 1.45M | 0U, // VRSQRTSfq |
8570 | 1.45M | 0U, // VRSQRTShd |
8571 | 1.45M | 0U, // VRSQRTShq |
8572 | 1.45M | 3671552U, // VRSRAsv16i8 |
8573 | 1.45M | 16768U, // VRSRAsv1i64 |
8574 | 1.45M | 3671552U, // VRSRAsv2i32 |
8575 | 1.45M | 16768U, // VRSRAsv2i64 |
8576 | 1.45M | 3671552U, // VRSRAsv4i16 |
8577 | 1.45M | 3671552U, // VRSRAsv4i32 |
8578 | 1.45M | 3671552U, // VRSRAsv8i16 |
8579 | 1.45M | 3671552U, // VRSRAsv8i8 |
8580 | 1.45M | 3671552U, // VRSRAuv16i8 |
8581 | 1.45M | 3671552U, // VRSRAuv1i64 |
8582 | 1.45M | 3671552U, // VRSRAuv2i32 |
8583 | 1.45M | 3671552U, // VRSRAuv2i64 |
8584 | 1.45M | 3671552U, // VRSRAuv4i16 |
8585 | 1.45M | 3671552U, // VRSRAuv4i32 |
8586 | 1.45M | 3671552U, // VRSRAuv8i16 |
8587 | 1.45M | 3671552U, // VRSRAuv8i8 |
8588 | 1.45M | 17920U, // VRSUBHNv2i32 |
8589 | 1.45M | 0U, // VRSUBHNv4i16 |
8590 | 1.45M | 0U, // VRSUBHNv8i8 |
8591 | 1.45M | 0U, // VSCCLRMD |
8592 | 1.45M | 0U, // VSCCLRMS |
8593 | 1.45M | 16768U, // VSDOTD |
8594 | 1.45M | 2163072U, // VSDOTDI |
8595 | 1.45M | 16768U, // VSDOTQ |
8596 | 1.45M | 2163072U, // VSDOTQI |
8597 | 1.45M | 17920U, // VSELEQD |
8598 | 1.45M | 17920U, // VSELEQH |
8599 | 1.45M | 17920U, // VSELEQS |
8600 | 1.45M | 17920U, // VSELGED |
8601 | 1.45M | 17920U, // VSELGEH |
8602 | 1.45M | 17920U, // VSELGES |
8603 | 1.45M | 17920U, // VSELGTD |
8604 | 1.45M | 17920U, // VSELGTH |
8605 | 1.45M | 17920U, // VSELGTS |
8606 | 1.45M | 17920U, // VSELVSD |
8607 | 1.45M | 17920U, // VSELVSH |
8608 | 1.45M | 17920U, // VSELVSS |
8609 | 1.45M | 34U, // VSETLNi16 |
8610 | 1.45M | 34U, // VSETLNi32 |
8611 | 1.45M | 34U, // VSETLNi8 |
8612 | 1.45M | 0U, // VSHLLi16 |
8613 | 1.45M | 0U, // VSHLLi32 |
8614 | 1.45M | 0U, // VSHLLi8 |
8615 | 1.45M | 0U, // VSHLLsv2i64 |
8616 | 1.45M | 0U, // VSHLLsv4i32 |
8617 | 1.45M | 0U, // VSHLLsv8i16 |
8618 | 1.45M | 0U, // VSHLLuv2i64 |
8619 | 1.45M | 0U, // VSHLLuv4i32 |
8620 | 1.45M | 0U, // VSHLLuv8i16 |
8621 | 1.45M | 0U, // VSHLiv16i8 |
8622 | 1.45M | 17920U, // VSHLiv1i64 |
8623 | 1.45M | 0U, // VSHLiv2i32 |
8624 | 1.45M | 17920U, // VSHLiv2i64 |
8625 | 1.45M | 0U, // VSHLiv4i16 |
8626 | 1.45M | 0U, // VSHLiv4i32 |
8627 | 1.45M | 0U, // VSHLiv8i16 |
8628 | 1.45M | 0U, // VSHLiv8i8 |
8629 | 1.45M | 0U, // VSHLsv16i8 |
8630 | 1.45M | 17920U, // VSHLsv1i64 |
8631 | 1.45M | 0U, // VSHLsv2i32 |
8632 | 1.45M | 17920U, // VSHLsv2i64 |
8633 | 1.45M | 0U, // VSHLsv4i16 |
8634 | 1.45M | 0U, // VSHLsv4i32 |
8635 | 1.45M | 0U, // VSHLsv8i16 |
8636 | 1.45M | 0U, // VSHLsv8i8 |
8637 | 1.45M | 0U, // VSHLuv16i8 |
8638 | 1.45M | 0U, // VSHLuv1i64 |
8639 | 1.45M | 0U, // VSHLuv2i32 |
8640 | 1.45M | 0U, // VSHLuv2i64 |
8641 | 1.45M | 0U, // VSHLuv4i16 |
8642 | 1.45M | 0U, // VSHLuv4i32 |
8643 | 1.45M | 0U, // VSHLuv8i16 |
8644 | 1.45M | 0U, // VSHLuv8i8 |
8645 | 1.45M | 17920U, // VSHRNv2i32 |
8646 | 1.45M | 0U, // VSHRNv4i16 |
8647 | 1.45M | 0U, // VSHRNv8i8 |
8648 | 1.45M | 0U, // VSHRsv16i8 |
8649 | 1.45M | 17920U, // VSHRsv1i64 |
8650 | 1.45M | 0U, // VSHRsv2i32 |
8651 | 1.45M | 17920U, // VSHRsv2i64 |
8652 | 1.45M | 0U, // VSHRsv4i16 |
8653 | 1.45M | 0U, // VSHRsv4i32 |
8654 | 1.45M | 0U, // VSHRsv8i16 |
8655 | 1.45M | 0U, // VSHRsv8i8 |
8656 | 1.45M | 0U, // VSHRuv16i8 |
8657 | 1.45M | 0U, // VSHRuv1i64 |
8658 | 1.45M | 0U, // VSHRuv2i32 |
8659 | 1.45M | 0U, // VSHRuv2i64 |
8660 | 1.45M | 0U, // VSHRuv4i16 |
8661 | 1.45M | 0U, // VSHRuv4i32 |
8662 | 1.45M | 0U, // VSHRuv8i16 |
8663 | 1.45M | 0U, // VSHRuv8i8 |
8664 | 1.45M | 0U, // VSHTOD |
8665 | 1.45M | 74U, // VSHTOH |
8666 | 1.45M | 0U, // VSHTOS |
8667 | 1.45M | 0U, // VSITOD |
8668 | 1.45M | 0U, // VSITOH |
8669 | 1.45M | 0U, // VSITOS |
8670 | 1.45M | 3671552U, // VSLIv16i8 |
8671 | 1.45M | 3671552U, // VSLIv1i64 |
8672 | 1.45M | 3671552U, // VSLIv2i32 |
8673 | 1.45M | 3671552U, // VSLIv2i64 |
8674 | 1.45M | 3671552U, // VSLIv4i16 |
8675 | 1.45M | 3671552U, // VSLIv4i32 |
8676 | 1.45M | 3671552U, // VSLIv8i16 |
8677 | 1.45M | 3671552U, // VSLIv8i8 |
8678 | 1.45M | 76U, // VSLTOD |
8679 | 1.45M | 76U, // VSLTOH |
8680 | 1.45M | 76U, // VSLTOS |
8681 | 1.45M | 16768U, // VSMMLA |
8682 | 1.45M | 526U, // VSQRTD |
8683 | 1.45M | 16384U, // VSQRTH |
8684 | 1.45M | 16384U, // VSQRTS |
8685 | 1.45M | 3671552U, // VSRAsv16i8 |
8686 | 1.45M | 16768U, // VSRAsv1i64 |
8687 | 1.45M | 3671552U, // VSRAsv2i32 |
8688 | 1.45M | 16768U, // VSRAsv2i64 |
8689 | 1.45M | 3671552U, // VSRAsv4i16 |
8690 | 1.45M | 3671552U, // VSRAsv4i32 |
8691 | 1.45M | 3671552U, // VSRAsv8i16 |
8692 | 1.45M | 3671552U, // VSRAsv8i8 |
8693 | 1.45M | 3671552U, // VSRAuv16i8 |
8694 | 1.45M | 3671552U, // VSRAuv1i64 |
8695 | 1.45M | 3671552U, // VSRAuv2i32 |
8696 | 1.45M | 3671552U, // VSRAuv2i64 |
8697 | 1.45M | 3671552U, // VSRAuv4i16 |
8698 | 1.45M | 3671552U, // VSRAuv4i32 |
8699 | 1.45M | 3671552U, // VSRAuv8i16 |
8700 | 1.45M | 3671552U, // VSRAuv8i8 |
8701 | 1.45M | 3671552U, // VSRIv16i8 |
8702 | 1.45M | 3671552U, // VSRIv1i64 |
8703 | 1.45M | 3671552U, // VSRIv2i32 |
8704 | 1.45M | 3671552U, // VSRIv2i64 |
8705 | 1.45M | 3671552U, // VSRIv4i16 |
8706 | 1.45M | 3671552U, // VSRIv4i32 |
8707 | 1.45M | 3671552U, // VSRIv8i16 |
8708 | 1.45M | 3671552U, // VSRIv8i8 |
8709 | 1.45M | 6568U, // VST1LNd16 |
8710 | 1.45M | 482105896U, // VST1LNd16_UPD |
8711 | 1.45M | 6568U, // VST1LNd32 |
8712 | 1.45M | 482105896U, // VST1LNd32_UPD |
8713 | 1.45M | 6568U, // VST1LNd8 |
8714 | 1.45M | 482105896U, // VST1LNd8_UPD |
8715 | 1.45M | 0U, // VST1LNq16Pseudo |
8716 | 1.45M | 0U, // VST1LNq16Pseudo_UPD |
8717 | 1.45M | 0U, // VST1LNq32Pseudo |
8718 | 1.45M | 0U, // VST1LNq32Pseudo_UPD |
8719 | 1.45M | 0U, // VST1LNq8Pseudo |
8720 | 1.45M | 0U, // VST1LNq8Pseudo_UPD |
8721 | 1.45M | 0U, // VST1d16 |
8722 | 1.45M | 0U, // VST1d16Q |
8723 | 1.45M | 0U, // VST1d16QPseudo |
8724 | 1.45M | 0U, // VST1d16QPseudoWB_fixed |
8725 | 1.45M | 0U, // VST1d16QPseudoWB_register |
8726 | 1.45M | 0U, // VST1d16Qwb_fixed |
8727 | 1.45M | 0U, // VST1d16Qwb_register |
8728 | 1.45M | 0U, // VST1d16T |
8729 | 1.45M | 0U, // VST1d16TPseudo |
8730 | 1.45M | 0U, // VST1d16TPseudoWB_fixed |
8731 | 1.45M | 0U, // VST1d16TPseudoWB_register |
8732 | 1.45M | 0U, // VST1d16Twb_fixed |
8733 | 1.45M | 0U, // VST1d16Twb_register |
8734 | 1.45M | 0U, // VST1d16wb_fixed |
8735 | 1.45M | 0U, // VST1d16wb_register |
8736 | 1.45M | 0U, // VST1d32 |
8737 | 1.45M | 0U, // VST1d32Q |
8738 | 1.45M | 0U, // VST1d32QPseudo |
8739 | 1.45M | 0U, // VST1d32QPseudoWB_fixed |
8740 | 1.45M | 0U, // VST1d32QPseudoWB_register |
8741 | 1.45M | 0U, // VST1d32Qwb_fixed |
8742 | 1.45M | 0U, // VST1d32Qwb_register |
8743 | 1.45M | 0U, // VST1d32T |
8744 | 1.45M | 0U, // VST1d32TPseudo |
8745 | 1.45M | 0U, // VST1d32TPseudoWB_fixed |
8746 | 1.45M | 0U, // VST1d32TPseudoWB_register |
8747 | 1.45M | 0U, // VST1d32Twb_fixed |
8748 | 1.45M | 0U, // VST1d32Twb_register |
8749 | 1.45M | 0U, // VST1d32wb_fixed |
8750 | 1.45M | 0U, // VST1d32wb_register |
8751 | 1.45M | 0U, // VST1d64 |
8752 | 1.45M | 0U, // VST1d64Q |
8753 | 1.45M | 0U, // VST1d64QPseudo |
8754 | 1.45M | 0U, // VST1d64QPseudoWB_fixed |
8755 | 1.45M | 0U, // VST1d64QPseudoWB_register |
8756 | 1.45M | 0U, // VST1d64Qwb_fixed |
8757 | 1.45M | 0U, // VST1d64Qwb_register |
8758 | 1.45M | 0U, // VST1d64T |
8759 | 1.45M | 0U, // VST1d64TPseudo |
8760 | 1.45M | 0U, // VST1d64TPseudoWB_fixed |
8761 | 1.45M | 0U, // VST1d64TPseudoWB_register |
8762 | 1.45M | 0U, // VST1d64Twb_fixed |
8763 | 1.45M | 0U, // VST1d64Twb_register |
8764 | 1.45M | 0U, // VST1d64wb_fixed |
8765 | 1.45M | 0U, // VST1d64wb_register |
8766 | 1.45M | 0U, // VST1d8 |
8767 | 1.45M | 0U, // VST1d8Q |
8768 | 1.45M | 0U, // VST1d8QPseudo |
8769 | 1.45M | 0U, // VST1d8QPseudoWB_fixed |
8770 | 1.45M | 0U, // VST1d8QPseudoWB_register |
8771 | 1.45M | 0U, // VST1d8Qwb_fixed |
8772 | 1.45M | 0U, // VST1d8Qwb_register |
8773 | 1.45M | 0U, // VST1d8T |
8774 | 1.45M | 0U, // VST1d8TPseudo |
8775 | 1.45M | 0U, // VST1d8TPseudoWB_fixed |
8776 | 1.45M | 0U, // VST1d8TPseudoWB_register |
8777 | 1.45M | 0U, // VST1d8Twb_fixed |
8778 | 1.45M | 0U, // VST1d8Twb_register |
8779 | 1.45M | 0U, // VST1d8wb_fixed |
8780 | 1.45M | 0U, // VST1d8wb_register |
8781 | 1.45M | 0U, // VST1q16 |
8782 | 1.45M | 0U, // VST1q16HighQPseudo |
8783 | 1.45M | 0U, // VST1q16HighQPseudo_UPD |
8784 | 1.45M | 0U, // VST1q16HighTPseudo |
8785 | 1.45M | 0U, // VST1q16HighTPseudo_UPD |
8786 | 1.45M | 0U, // VST1q16LowQPseudo_UPD |
8787 | 1.45M | 0U, // VST1q16LowTPseudo_UPD |
8788 | 1.45M | 0U, // VST1q16wb_fixed |
8789 | 1.45M | 0U, // VST1q16wb_register |
8790 | 1.45M | 0U, // VST1q32 |
8791 | 1.45M | 0U, // VST1q32HighQPseudo |
8792 | 1.45M | 0U, // VST1q32HighQPseudo_UPD |
8793 | 1.45M | 0U, // VST1q32HighTPseudo |
8794 | 1.45M | 0U, // VST1q32HighTPseudo_UPD |
8795 | 1.45M | 0U, // VST1q32LowQPseudo_UPD |
8796 | 1.45M | 0U, // VST1q32LowTPseudo_UPD |
8797 | 1.45M | 0U, // VST1q32wb_fixed |
8798 | 1.45M | 0U, // VST1q32wb_register |
8799 | 1.45M | 0U, // VST1q64 |
8800 | 1.45M | 0U, // VST1q64HighQPseudo |
8801 | 1.45M | 0U, // VST1q64HighQPseudo_UPD |
8802 | 1.45M | 0U, // VST1q64HighTPseudo |
8803 | 1.45M | 0U, // VST1q64HighTPseudo_UPD |
8804 | 1.45M | 0U, // VST1q64LowQPseudo_UPD |
8805 | 1.45M | 0U, // VST1q64LowTPseudo_UPD |
8806 | 1.45M | 0U, // VST1q64wb_fixed |
8807 | 1.45M | 0U, // VST1q64wb_register |
8808 | 1.45M | 0U, // VST1q8 |
8809 | 1.45M | 0U, // VST1q8HighQPseudo |
8810 | 1.45M | 0U, // VST1q8HighQPseudo_UPD |
8811 | 1.45M | 0U, // VST1q8HighTPseudo |
8812 | 1.45M | 0U, // VST1q8HighTPseudo_UPD |
8813 | 1.45M | 0U, // VST1q8LowQPseudo_UPD |
8814 | 1.45M | 0U, // VST1q8LowTPseudo_UPD |
8815 | 1.45M | 0U, // VST1q8wb_fixed |
8816 | 1.45M | 0U, // VST1q8wb_register |
8817 | 1.45M | 406623528U, // VST2LNd16 |
8818 | 1.45M | 0U, // VST2LNd16Pseudo |
8819 | 1.45M | 0U, // VST2LNd16Pseudo_UPD |
8820 | 1.45M | 407147944U, // VST2LNd16_UPD |
8821 | 1.45M | 406623528U, // VST2LNd32 |
8822 | 1.45M | 0U, // VST2LNd32Pseudo |
8823 | 1.45M | 0U, // VST2LNd32Pseudo_UPD |
8824 | 1.45M | 407147944U, // VST2LNd32_UPD |
8825 | 1.45M | 406623528U, // VST2LNd8 |
8826 | 1.45M | 0U, // VST2LNd8Pseudo |
8827 | 1.45M | 0U, // VST2LNd8Pseudo_UPD |
8828 | 1.45M | 407147944U, // VST2LNd8_UPD |
8829 | 1.45M | 406623528U, // VST2LNq16 |
8830 | 1.45M | 0U, // VST2LNq16Pseudo |
8831 | 1.45M | 0U, // VST2LNq16Pseudo_UPD |
8832 | 1.45M | 407147944U, // VST2LNq16_UPD |
8833 | 1.45M | 406623528U, // VST2LNq32 |
8834 | 1.45M | 0U, // VST2LNq32Pseudo |
8835 | 1.45M | 0U, // VST2LNq32Pseudo_UPD |
8836 | 1.45M | 407147944U, // VST2LNq32_UPD |
8837 | 1.45M | 0U, // VST2b16 |
8838 | 1.45M | 0U, // VST2b16wb_fixed |
8839 | 1.45M | 0U, // VST2b16wb_register |
8840 | 1.45M | 0U, // VST2b32 |
8841 | 1.45M | 0U, // VST2b32wb_fixed |
8842 | 1.45M | 0U, // VST2b32wb_register |
8843 | 1.45M | 0U, // VST2b8 |
8844 | 1.45M | 0U, // VST2b8wb_fixed |
8845 | 1.45M | 0U, // VST2b8wb_register |
8846 | 1.45M | 0U, // VST2d16 |
8847 | 1.45M | 0U, // VST2d16wb_fixed |
8848 | 1.45M | 0U, // VST2d16wb_register |
8849 | 1.45M | 0U, // VST2d32 |
8850 | 1.45M | 0U, // VST2d32wb_fixed |
8851 | 1.45M | 0U, // VST2d32wb_register |
8852 | 1.45M | 0U, // VST2d8 |
8853 | 1.45M | 0U, // VST2d8wb_fixed |
8854 | 1.45M | 0U, // VST2d8wb_register |
8855 | 1.45M | 0U, // VST2q16 |
8856 | 1.45M | 0U, // VST2q16Pseudo |
8857 | 1.45M | 0U, // VST2q16PseudoWB_fixed |
8858 | 1.45M | 0U, // VST2q16PseudoWB_register |
8859 | 1.45M | 0U, // VST2q16wb_fixed |
8860 | 1.45M | 0U, // VST2q16wb_register |
8861 | 1.45M | 0U, // VST2q32 |
8862 | 1.45M | 0U, // VST2q32Pseudo |
8863 | 1.45M | 0U, // VST2q32PseudoWB_fixed |
8864 | 1.45M | 0U, // VST2q32PseudoWB_register |
8865 | 1.45M | 0U, // VST2q32wb_fixed |
8866 | 1.45M | 0U, // VST2q32wb_register |
8867 | 1.45M | 0U, // VST2q8 |
8868 | 1.45M | 0U, // VST2q8Pseudo |
8869 | 1.45M | 0U, // VST2q8PseudoWB_fixed |
8870 | 1.45M | 0U, // VST2q8PseudoWB_register |
8871 | 1.45M | 0U, // VST2q8wb_fixed |
8872 | 1.45M | 0U, // VST2q8wb_register |
8873 | 1.45M | 406624808U, // VST3LNd16 |
8874 | 1.45M | 0U, // VST3LNd16Pseudo |
8875 | 1.45M | 0U, // VST3LNd16Pseudo_UPD |
8876 | 1.45M | 6824U, // VST3LNd16_UPD |
8877 | 1.45M | 406624808U, // VST3LNd32 |
8878 | 1.45M | 0U, // VST3LNd32Pseudo |
8879 | 1.45M | 0U, // VST3LNd32Pseudo_UPD |
8880 | 1.45M | 6824U, // VST3LNd32_UPD |
8881 | 1.45M | 406624808U, // VST3LNd8 |
8882 | 1.45M | 0U, // VST3LNd8Pseudo |
8883 | 1.45M | 0U, // VST3LNd8Pseudo_UPD |
8884 | 1.45M | 6824U, // VST3LNd8_UPD |
8885 | 1.45M | 406624808U, // VST3LNq16 |
8886 | 1.45M | 0U, // VST3LNq16Pseudo |
8887 | 1.45M | 0U, // VST3LNq16Pseudo_UPD |
8888 | 1.45M | 6824U, // VST3LNq16_UPD |
8889 | 1.45M | 406624808U, // VST3LNq32 |
8890 | 1.45M | 0U, // VST3LNq32Pseudo |
8891 | 1.45M | 0U, // VST3LNq32Pseudo_UPD |
8892 | 1.45M | 6824U, // VST3LNq32_UPD |
8893 | 1.45M | 369623424U, // VST3d16 |
8894 | 1.45M | 0U, // VST3d16Pseudo |
8895 | 1.45M | 0U, // VST3d16Pseudo_UPD |
8896 | 1.45M | 383744U, // VST3d16_UPD |
8897 | 1.45M | 369623424U, // VST3d32 |
8898 | 1.45M | 0U, // VST3d32Pseudo |
8899 | 1.45M | 0U, // VST3d32Pseudo_UPD |
8900 | 1.45M | 383744U, // VST3d32_UPD |
8901 | 1.45M | 369623424U, // VST3d8 |
8902 | 1.45M | 0U, // VST3d8Pseudo |
8903 | 1.45M | 0U, // VST3d8Pseudo_UPD |
8904 | 1.45M | 383744U, // VST3d8_UPD |
8905 | 1.45M | 369623424U, // VST3q16 |
8906 | 1.45M | 0U, // VST3q16Pseudo_UPD |
8907 | 1.45M | 383744U, // VST3q16_UPD |
8908 | 1.45M | 0U, // VST3q16oddPseudo |
8909 | 1.45M | 0U, // VST3q16oddPseudo_UPD |
8910 | 1.45M | 369623424U, // VST3q32 |
8911 | 1.45M | 0U, // VST3q32Pseudo_UPD |
8912 | 1.45M | 383744U, // VST3q32_UPD |
8913 | 1.45M | 0U, // VST3q32oddPseudo |
8914 | 1.45M | 0U, // VST3q32oddPseudo_UPD |
8915 | 1.45M | 369623424U, // VST3q8 |
8916 | 1.45M | 0U, // VST3q8Pseudo_UPD |
8917 | 1.45M | 383744U, // VST3q8_UPD |
8918 | 1.45M | 0U, // VST3q8oddPseudo |
8919 | 1.45M | 0U, // VST3q8oddPseudo_UPD |
8920 | 1.45M | 406623656U, // VST4LNd16 |
8921 | 1.45M | 0U, // VST4LNd16Pseudo |
8922 | 1.45M | 0U, // VST4LNd16Pseudo_UPD |
8923 | 1.45M | 398888U, // VST4LNd16_UPD |
8924 | 1.45M | 406623656U, // VST4LNd32 |
8925 | 1.45M | 0U, // VST4LNd32Pseudo |
8926 | 1.45M | 0U, // VST4LNd32Pseudo_UPD |
8927 | 1.45M | 398888U, // VST4LNd32_UPD |
8928 | 1.45M | 406623656U, // VST4LNd8 |
8929 | 1.45M | 0U, // VST4LNd8Pseudo |
8930 | 1.45M | 0U, // VST4LNd8Pseudo_UPD |
8931 | 1.45M | 398888U, // VST4LNd8_UPD |
8932 | 1.45M | 406623656U, // VST4LNq16 |
8933 | 1.45M | 0U, // VST4LNq16Pseudo |
8934 | 1.45M | 0U, // VST4LNq16Pseudo_UPD |
8935 | 1.45M | 398888U, // VST4LNq16_UPD |
8936 | 1.45M | 406623656U, // VST4LNq32 |
8937 | 1.45M | 0U, // VST4LNq32Pseudo |
8938 | 1.45M | 0U, // VST4LNq32Pseudo_UPD |
8939 | 1.45M | 398888U, // VST4LNq32_UPD |
8940 | 1.45M | 34079104U, // VST4d16 |
8941 | 1.45M | 0U, // VST4d16Pseudo |
8942 | 1.45M | 0U, // VST4d16Pseudo_UPD |
8943 | 1.45M | 15735552U, // VST4d16_UPD |
8944 | 1.45M | 34079104U, // VST4d32 |
8945 | 1.45M | 0U, // VST4d32Pseudo |
8946 | 1.45M | 0U, // VST4d32Pseudo_UPD |
8947 | 1.45M | 15735552U, // VST4d32_UPD |
8948 | 1.45M | 34079104U, // VST4d8 |
8949 | 1.45M | 0U, // VST4d8Pseudo |
8950 | 1.45M | 0U, // VST4d8Pseudo_UPD |
8951 | 1.45M | 15735552U, // VST4d8_UPD |
8952 | 1.45M | 34079104U, // VST4q16 |
8953 | 1.45M | 0U, // VST4q16Pseudo_UPD |
8954 | 1.45M | 15735552U, // VST4q16_UPD |
8955 | 1.45M | 0U, // VST4q16oddPseudo |
8956 | 1.45M | 0U, // VST4q16oddPseudo_UPD |
8957 | 1.45M | 34079104U, // VST4q32 |
8958 | 1.45M | 0U, // VST4q32Pseudo_UPD |
8959 | 1.45M | 15735552U, // VST4q32_UPD |
8960 | 1.45M | 0U, // VST4q32oddPseudo |
8961 | 1.45M | 0U, // VST4q32oddPseudo_UPD |
8962 | 1.45M | 34079104U, // VST4q8 |
8963 | 1.45M | 0U, // VST4q8Pseudo_UPD |
8964 | 1.45M | 15735552U, // VST4q8_UPD |
8965 | 1.45M | 0U, // VST4q8oddPseudo |
8966 | 1.45M | 0U, // VST4q8oddPseudo_UPD |
8967 | 1.45M | 530U, // VSTMDDB_UPD |
8968 | 1.45M | 18560U, // VSTMDIA |
8969 | 1.45M | 530U, // VSTMDIA_UPD |
8970 | 1.45M | 0U, // VSTMQIA |
8971 | 1.45M | 530U, // VSTMSDB_UPD |
8972 | 1.45M | 18560U, // VSTMSIA |
8973 | 1.45M | 530U, // VSTMSIA_UPD |
8974 | 1.45M | 6272U, // VSTRD |
8975 | 1.45M | 6400U, // VSTRH |
8976 | 1.45M | 6272U, // VSTRS |
8977 | 1.45M | 0U, // VSTR_FPCXTNS_off |
8978 | 1.45M | 44U, // VSTR_FPCXTNS_post |
8979 | 1.45M | 0U, // VSTR_FPCXTNS_pre |
8980 | 1.45M | 0U, // VSTR_FPCXTS_off |
8981 | 1.45M | 44U, // VSTR_FPCXTS_post |
8982 | 1.45M | 0U, // VSTR_FPCXTS_pre |
8983 | 1.45M | 0U, // VSTR_FPSCR_NZCVQC_off |
8984 | 1.45M | 44U, // VSTR_FPSCR_NZCVQC_post |
8985 | 1.45M | 0U, // VSTR_FPSCR_NZCVQC_pre |
8986 | 1.45M | 0U, // VSTR_FPSCR_off |
8987 | 1.45M | 44U, // VSTR_FPSCR_post |
8988 | 1.45M | 0U, // VSTR_FPSCR_pre |
8989 | 1.45M | 0U, // VSTR_P0_off |
8990 | 1.45M | 46U, // VSTR_P0_post |
8991 | 1.45M | 0U, // VSTR_P0_pre |
8992 | 1.45M | 0U, // VSTR_VPR_off |
8993 | 1.45M | 44U, // VSTR_VPR_post |
8994 | 1.45M | 0U, // VSTR_VPR_pre |
8995 | 1.45M | 2212622U, // VSUBD |
8996 | 1.45M | 0U, // VSUBH |
8997 | 1.45M | 17920U, // VSUBHNv2i32 |
8998 | 1.45M | 0U, // VSUBHNv4i16 |
8999 | 1.45M | 0U, // VSUBHNv8i8 |
9000 | 1.45M | 0U, // VSUBLsv2i64 |
9001 | 1.45M | 0U, // VSUBLsv4i32 |
9002 | 1.45M | 0U, // VSUBLsv8i16 |
9003 | 1.45M | 0U, // VSUBLuv2i64 |
9004 | 1.45M | 0U, // VSUBLuv4i32 |
9005 | 1.45M | 0U, // VSUBLuv8i16 |
9006 | 1.45M | 0U, // VSUBS |
9007 | 1.45M | 0U, // VSUBWsv2i64 |
9008 | 1.45M | 0U, // VSUBWsv4i32 |
9009 | 1.45M | 0U, // VSUBWsv8i16 |
9010 | 1.45M | 0U, // VSUBWuv2i64 |
9011 | 1.45M | 0U, // VSUBWuv4i32 |
9012 | 1.45M | 0U, // VSUBWuv8i16 |
9013 | 1.45M | 0U, // VSUBfd |
9014 | 1.45M | 0U, // VSUBfq |
9015 | 1.45M | 0U, // VSUBhd |
9016 | 1.45M | 0U, // VSUBhq |
9017 | 1.45M | 0U, // VSUBv16i8 |
9018 | 1.45M | 17920U, // VSUBv1i64 |
9019 | 1.45M | 0U, // VSUBv2i32 |
9020 | 1.45M | 17920U, // VSUBv2i64 |
9021 | 1.45M | 0U, // VSUBv4i16 |
9022 | 1.45M | 0U, // VSUBv4i32 |
9023 | 1.45M | 0U, // VSUBv8i16 |
9024 | 1.45M | 0U, // VSUBv8i8 |
9025 | 1.45M | 2163072U, // VSUDOTDI |
9026 | 1.45M | 2163072U, // VSUDOTQI |
9027 | 1.45M | 16384U, // VSWPd |
9028 | 1.45M | 16384U, // VSWPq |
9029 | 1.45M | 7040U, // VTBL1 |
9030 | 1.45M | 7168U, // VTBL2 |
9031 | 1.45M | 7296U, // VTBL3 |
9032 | 1.45M | 0U, // VTBL3Pseudo |
9033 | 1.45M | 7424U, // VTBL4 |
9034 | 1.45M | 0U, // VTBL4Pseudo |
9035 | 1.45M | 7552U, // VTBX1 |
9036 | 1.45M | 7680U, // VTBX2 |
9037 | 1.45M | 7808U, // VTBX3 |
9038 | 1.45M | 0U, // VTBX3Pseudo |
9039 | 1.45M | 7936U, // VTBX4 |
9040 | 1.45M | 0U, // VTBX4Pseudo |
9041 | 1.45M | 0U, // VTOSHD |
9042 | 1.45M | 74U, // VTOSHH |
9043 | 1.45M | 0U, // VTOSHS |
9044 | 1.45M | 0U, // VTOSIRD |
9045 | 1.45M | 0U, // VTOSIRH |
9046 | 1.45M | 0U, // VTOSIRS |
9047 | 1.45M | 0U, // VTOSIZD |
9048 | 1.45M | 0U, // VTOSIZH |
9049 | 1.45M | 0U, // VTOSIZS |
9050 | 1.45M | 76U, // VTOSLD |
9051 | 1.45M | 76U, // VTOSLH |
9052 | 1.45M | 76U, // VTOSLS |
9053 | 1.45M | 0U, // VTOUHD |
9054 | 1.45M | 74U, // VTOUHH |
9055 | 1.45M | 0U, // VTOUHS |
9056 | 1.45M | 0U, // VTOUIRD |
9057 | 1.45M | 0U, // VTOUIRH |
9058 | 1.45M | 0U, // VTOUIRS |
9059 | 1.45M | 0U, // VTOUIZD |
9060 | 1.45M | 0U, // VTOUIZH |
9061 | 1.45M | 0U, // VTOUIZS |
9062 | 1.45M | 76U, // VTOULD |
9063 | 1.45M | 76U, // VTOULH |
9064 | 1.45M | 76U, // VTOULS |
9065 | 1.45M | 16384U, // VTRNd16 |
9066 | 1.45M | 16384U, // VTRNd32 |
9067 | 1.45M | 16384U, // VTRNd8 |
9068 | 1.45M | 16384U, // VTRNq16 |
9069 | 1.45M | 16384U, // VTRNq32 |
9070 | 1.45M | 16384U, // VTRNq8 |
9071 | 1.45M | 0U, // VTSTv16i8 |
9072 | 1.45M | 0U, // VTSTv2i32 |
9073 | 1.45M | 0U, // VTSTv4i16 |
9074 | 1.45M | 0U, // VTSTv4i32 |
9075 | 1.45M | 0U, // VTSTv8i16 |
9076 | 1.45M | 0U, // VTSTv8i8 |
9077 | 1.45M | 16768U, // VUDOTD |
9078 | 1.45M | 2163072U, // VUDOTDI |
9079 | 1.45M | 16768U, // VUDOTQ |
9080 | 1.45M | 2163072U, // VUDOTQI |
9081 | 1.45M | 0U, // VUHTOD |
9082 | 1.45M | 74U, // VUHTOH |
9083 | 1.45M | 0U, // VUHTOS |
9084 | 1.45M | 0U, // VUITOD |
9085 | 1.45M | 0U, // VUITOH |
9086 | 1.45M | 0U, // VUITOS |
9087 | 1.45M | 76U, // VULTOD |
9088 | 1.45M | 76U, // VULTOH |
9089 | 1.45M | 76U, // VULTOS |
9090 | 1.45M | 16768U, // VUMMLA |
9091 | 1.45M | 16768U, // VUSDOTD |
9092 | 1.45M | 2163072U, // VUSDOTDI |
9093 | 1.45M | 16768U, // VUSDOTQ |
9094 | 1.45M | 2163072U, // VUSDOTQI |
9095 | 1.45M | 16768U, // VUSMMLA |
9096 | 1.45M | 16384U, // VUZPd16 |
9097 | 1.45M | 16384U, // VUZPd8 |
9098 | 1.45M | 16384U, // VUZPq16 |
9099 | 1.45M | 16384U, // VUZPq32 |
9100 | 1.45M | 16384U, // VUZPq8 |
9101 | 1.45M | 16384U, // VZIPd16 |
9102 | 1.45M | 16384U, // VZIPd8 |
9103 | 1.45M | 16384U, // VZIPq16 |
9104 | 1.45M | 16384U, // VZIPq32 |
9105 | 1.45M | 16384U, // VZIPq8 |
9106 | 1.45M | 411776U, // sysLDMDA |
9107 | 1.45M | 8082U, // sysLDMDA_UPD |
9108 | 1.45M | 411776U, // sysLDMDB |
9109 | 1.45M | 8082U, // sysLDMDB_UPD |
9110 | 1.45M | 411776U, // sysLDMIA |
9111 | 1.45M | 8082U, // sysLDMIA_UPD |
9112 | 1.45M | 411776U, // sysLDMIB |
9113 | 1.45M | 8082U, // sysLDMIB_UPD |
9114 | 1.45M | 411776U, // sysSTMDA |
9115 | 1.45M | 8082U, // sysSTMDA_UPD |
9116 | 1.45M | 411776U, // sysSTMDB |
9117 | 1.45M | 8082U, // sysSTMDB_UPD |
9118 | 1.45M | 411776U, // sysSTMIA |
9119 | 1.45M | 8082U, // sysSTMIA_UPD |
9120 | 1.45M | 411776U, // sysSTMIB |
9121 | 1.45M | 8082U, // sysSTMIB_UPD |
9122 | 1.45M | 0U, // t2ADCri |
9123 | 1.45M | 0U, // t2ADCrr |
9124 | 1.45M | 16252928U, // t2ADCrs |
9125 | 1.45M | 0U, // t2ADDri |
9126 | 1.45M | 0U, // t2ADDri12 |
9127 | 1.45M | 0U, // t2ADDrr |
9128 | 1.45M | 16252928U, // t2ADDrs |
9129 | 1.45M | 0U, // t2ADDspImm |
9130 | 1.45M | 0U, // t2ADDspImm12 |
9131 | 1.45M | 1280U, // t2ADR |
9132 | 1.45M | 0U, // t2ANDri |
9133 | 1.45M | 0U, // t2ANDrr |
9134 | 1.45M | 16252928U, // t2ANDrs |
9135 | 1.45M | 16777216U, // t2ASRri |
9136 | 1.45M | 0U, // t2ASRrr |
9137 | 1.45M | 0U, // t2AUT |
9138 | 1.45M | 524672U, // t2AUTG |
9139 | 1.45M | 2U, // t2B |
9140 | 1.45M | 1408U, // t2BFC |
9141 | 1.45M | 2622976U, // t2BFI |
9142 | 1.45M | 8192U, // t2BFLi |
9143 | 1.45M | 16384U, // t2BFLr |
9144 | 1.45M | 8192U, // t2BFi |
9145 | 1.45M | 17306496U, // t2BFic |
9146 | 1.45M | 16384U, // t2BFr |
9147 | 1.45M | 0U, // t2BICri |
9148 | 1.45M | 0U, // t2BICrr |
9149 | 1.45M | 16252928U, // t2BICrs |
9150 | 1.45M | 0U, // t2BTI |
9151 | 1.45M | 524672U, // t2BXAUT |
9152 | 1.45M | 2U, // t2BXJ |
9153 | 1.45M | 2U, // t2Bcc |
9154 | 1.45M | 99086U, // t2CDP |
9155 | 1.45M | 99086U, // t2CDP2 |
9156 | 1.45M | 0U, // t2CLREX |
9157 | 1.45M | 0U, // t2CLRM |
9158 | 1.45M | 16384U, // t2CLZ |
9159 | 1.45M | 16384U, // t2CMNri |
9160 | 1.45M | 16384U, // t2CMNzrr |
9161 | 1.45M | 1024U, // t2CMNzrs |
9162 | 1.45M | 16384U, // t2CMPri |
9163 | 1.45M | 16384U, // t2CMPrr |
9164 | 1.45M | 1024U, // t2CMPrs |
9165 | 1.45M | 0U, // t2CPS1p |
9166 | 1.45M | 2U, // t2CPS2p |
9167 | 1.45M | 17920U, // t2CPS3p |
9168 | 1.45M | 17920U, // t2CRC32B |
9169 | 1.45M | 17920U, // t2CRC32CB |
9170 | 1.45M | 17920U, // t2CRC32CH |
9171 | 1.45M | 17920U, // t2CRC32CW |
9172 | 1.45M | 17920U, // t2CRC32H |
9173 | 1.45M | 17920U, // t2CRC32W |
9174 | 1.45M | 17303040U, // t2CSEL |
9175 | 1.45M | 17303040U, // t2CSINC |
9176 | 1.45M | 17303040U, // t2CSINV |
9177 | 1.45M | 17303040U, // t2CSNEG |
9178 | 1.45M | 2U, // t2DBG |
9179 | 1.45M | 0U, // t2DCPS1 |
9180 | 1.45M | 0U, // t2DCPS2 |
9181 | 1.45M | 0U, // t2DCPS3 |
9182 | 1.45M | 2U, // t2DLS |
9183 | 1.45M | 0U, // t2DMB |
9184 | 1.45M | 0U, // t2DSB |
9185 | 1.45M | 0U, // t2EORri |
9186 | 1.45M | 0U, // t2EORrr |
9187 | 1.45M | 16252928U, // t2EORrs |
9188 | 1.45M | 2U, // t2HINT |
9189 | 1.45M | 0U, // t2HVC |
9190 | 1.45M | 0U, // t2ISB |
9191 | 1.45M | 0U, // t2IT |
9192 | 1.45M | 0U, // t2Int_eh_sjlj_setjmp |
9193 | 1.45M | 0U, // t2Int_eh_sjlj_setjmp_nofp |
9194 | 1.45M | 128U, // t2LDA |
9195 | 1.45M | 128U, // t2LDAB |
9196 | 1.45M | 128U, // t2LDAEX |
9197 | 1.45M | 128U, // t2LDAEXB |
9198 | 1.45M | 10485760U, // t2LDAEXD |
9199 | 1.45M | 128U, // t2LDAEXH |
9200 | 1.45M | 128U, // t2LDAH |
9201 | 1.45M | 2580U, // t2LDC2L_OFFSET |
9202 | 1.45M | 4721300U, // t2LDC2L_OPTION |
9203 | 1.45M | 5245588U, // t2LDC2L_POST |
9204 | 1.45M | 22U, // t2LDC2L_PRE |
9205 | 1.45M | 2580U, // t2LDC2_OFFSET |
9206 | 1.45M | 4721300U, // t2LDC2_OPTION |
9207 | 1.45M | 5245588U, // t2LDC2_POST |
9208 | 1.45M | 22U, // t2LDC2_PRE |
9209 | 1.45M | 2580U, // t2LDCL_OFFSET |
9210 | 1.45M | 4721300U, // t2LDCL_OPTION |
9211 | 1.45M | 5245588U, // t2LDCL_POST |
9212 | 1.45M | 22U, // t2LDCL_PRE |
9213 | 1.45M | 2580U, // t2LDC_OFFSET |
9214 | 1.45M | 4721300U, // t2LDC_OPTION |
9215 | 1.45M | 5245588U, // t2LDC_POST |
9216 | 1.45M | 22U, // t2LDC_PRE |
9217 | 1.45M | 18560U, // t2LDMDB |
9218 | 1.45M | 530U, // t2LDMDB_UPD |
9219 | 1.45M | 18560U, // t2LDMIA |
9220 | 1.45M | 530U, // t2LDMIA_UPD |
9221 | 1.45M | 3968U, // t2LDRBT |
9222 | 1.45M | 150144U, // t2LDRB_POST |
9223 | 1.45M | 4352U, // t2LDRB_PRE |
9224 | 1.45M | 3072U, // t2LDRBi12 |
9225 | 1.45M | 3968U, // t2LDRBi8 |
9226 | 1.45M | 8320U, // t2LDRBpci |
9227 | 1.45M | 8448U, // t2LDRBs |
9228 | 1.45M | 510132224U, // t2LDRD_POST |
9229 | 1.45M | 17825792U, // t2LDRD_PRE |
9230 | 1.45M | 18350080U, // t2LDRDi8 |
9231 | 1.45M | 8576U, // t2LDREX |
9232 | 1.45M | 128U, // t2LDREXB |
9233 | 1.45M | 10485760U, // t2LDREXD |
9234 | 1.45M | 128U, // t2LDREXH |
9235 | 1.45M | 3968U, // t2LDRHT |
9236 | 1.45M | 150144U, // t2LDRH_POST |
9237 | 1.45M | 4352U, // t2LDRH_PRE |
9238 | 1.45M | 3072U, // t2LDRHi12 |
9239 | 1.45M | 3968U, // t2LDRHi8 |
9240 | 1.45M | 8320U, // t2LDRHpci |
9241 | 1.45M | 8448U, // t2LDRHs |
9242 | 1.45M | 3968U, // t2LDRSBT |
9243 | 1.45M | 150144U, // t2LDRSB_POST |
9244 | 1.45M | 4352U, // t2LDRSB_PRE |
9245 | 1.45M | 3072U, // t2LDRSBi12 |
9246 | 1.45M | 3968U, // t2LDRSBi8 |
9247 | 1.45M | 8320U, // t2LDRSBpci |
9248 | 1.45M | 8448U, // t2LDRSBs |
9249 | 1.45M | 3968U, // t2LDRSHT |
9250 | 1.45M | 150144U, // t2LDRSH_POST |
9251 | 1.45M | 4352U, // t2LDRSH_PRE |
9252 | 1.45M | 3072U, // t2LDRSHi12 |
9253 | 1.45M | 3968U, // t2LDRSHi8 |
9254 | 1.45M | 8320U, // t2LDRSHpci |
9255 | 1.45M | 8448U, // t2LDRSHs |
9256 | 1.45M | 3968U, // t2LDRT |
9257 | 1.45M | 150144U, // t2LDR_POST |
9258 | 1.45M | 4352U, // t2LDR_PRE |
9259 | 1.45M | 3072U, // t2LDRi12 |
9260 | 1.45M | 3968U, // t2LDRi8 |
9261 | 1.45M | 8320U, // t2LDRpci |
9262 | 1.45M | 8448U, // t2LDRs |
9263 | 1.45M | 0U, // t2LE |
9264 | 1.45M | 0U, // t2LEUpdate |
9265 | 1.45M | 0U, // t2LSLri |
9266 | 1.45M | 0U, // t2LSLrr |
9267 | 1.45M | 16777216U, // t2LSRri |
9268 | 1.45M | 0U, // t2LSRrr |
9269 | 1.45M | 103924494U, // t2MCR |
9270 | 1.45M | 103924494U, // t2MCR2 |
9271 | 1.45M | 137478926U, // t2MCRR |
9272 | 1.45M | 137478926U, // t2MCRR2 |
9273 | 1.45M | 33554432U, // t2MLA |
9274 | 1.45M | 33554432U, // t2MLS |
9275 | 1.45M | 17920U, // t2MOVTi16 |
9276 | 1.45M | 16384U, // t2MOVi |
9277 | 1.45M | 16384U, // t2MOVi16 |
9278 | 1.45M | 16384U, // t2MOVr |
9279 | 1.45M | 425984U, // t2MOVsra_flag |
9280 | 1.45M | 425984U, // t2MOVsrl_flag |
9281 | 1.45M | 131864U, // t2MRC |
9282 | 1.45M | 131864U, // t2MRC2 |
9283 | 1.45M | 0U, // t2MRRC |
9284 | 1.45M | 0U, // t2MRRC2 |
9285 | 1.45M | 26U, // t2MRS_AR |
9286 | 1.45M | 8704U, // t2MRS_M |
9287 | 1.45M | 3712U, // t2MRSbanked |
9288 | 1.45M | 28U, // t2MRSsys_AR |
9289 | 1.45M | 526U, // t2MSR_AR |
9290 | 1.45M | 526U, // t2MSR_M |
9291 | 1.45M | 0U, // t2MSRbanked |
9292 | 1.45M | 0U, // t2MUL |
9293 | 1.45M | 16384U, // t2MVNi |
9294 | 1.45M | 16384U, // t2MVNr |
9295 | 1.45M | 1024U, // t2MVNs |
9296 | 1.45M | 0U, // t2ORNri |
9297 | 1.45M | 0U, // t2ORNrr |
9298 | 1.45M | 16252928U, // t2ORNrs |
9299 | 1.45M | 0U, // t2ORRri |
9300 | 1.45M | 0U, // t2ORRrr |
9301 | 1.45M | 16252928U, // t2ORRrs |
9302 | 1.45M | 0U, // t2PAC |
9303 | 1.45M | 0U, // t2PACBTI |
9304 | 1.45M | 524672U, // t2PACG |
9305 | 1.45M | 201326592U, // t2PKHBT |
9306 | 1.45M | 234881024U, // t2PKHTB |
9307 | 1.45M | 0U, // t2PLDWi12 |
9308 | 1.45M | 0U, // t2PLDWi8 |
9309 | 1.45M | 1U, // t2PLDWs |
9310 | 1.45M | 0U, // t2PLDi12 |
9311 | 1.45M | 0U, // t2PLDi8 |
9312 | 1.45M | 1U, // t2PLDpci |
9313 | 1.45M | 1U, // t2PLDs |
9314 | 1.45M | 0U, // t2PLIi12 |
9315 | 1.45M | 0U, // t2PLIi8 |
9316 | 1.45M | 1U, // t2PLIpci |
9317 | 1.45M | 1U, // t2PLIs |
9318 | 1.45M | 0U, // t2QADD |
9319 | 1.45M | 0U, // t2QADD16 |
9320 | 1.45M | 0U, // t2QADD8 |
9321 | 1.45M | 0U, // t2QASX |
9322 | 1.45M | 0U, // t2QDADD |
9323 | 1.45M | 0U, // t2QDSUB |
9324 | 1.45M | 0U, // t2QSAX |
9325 | 1.45M | 0U, // t2QSUB |
9326 | 1.45M | 0U, // t2QSUB16 |
9327 | 1.45M | 0U, // t2QSUB8 |
9328 | 1.45M | 16384U, // t2RBIT |
9329 | 1.45M | 16384U, // t2REV |
9330 | 1.45M | 16384U, // t2REV16 |
9331 | 1.45M | 16384U, // t2REVSH |
9332 | 1.45M | 2U, // t2RFEDB |
9333 | 1.45M | 4U, // t2RFEDBW |
9334 | 1.45M | 2U, // t2RFEIA |
9335 | 1.45M | 4U, // t2RFEIAW |
9336 | 1.45M | 0U, // t2RORri |
9337 | 1.45M | 0U, // t2RORrr |
9338 | 1.45M | 16384U, // t2RRX |
9339 | 1.45M | 0U, // t2RSBri |
9340 | 1.45M | 0U, // t2RSBrr |
9341 | 1.45M | 16252928U, // t2RSBrs |
9342 | 1.45M | 0U, // t2SADD16 |
9343 | 1.45M | 0U, // t2SADD8 |
9344 | 1.45M | 0U, // t2SASX |
9345 | 1.45M | 0U, // t2SB |
9346 | 1.45M | 0U, // t2SBCri |
9347 | 1.45M | 0U, // t2SBCrr |
9348 | 1.45M | 16252928U, // t2SBCrs |
9349 | 1.45M | 33554432U, // t2SBFX |
9350 | 1.45M | 0U, // t2SDIV |
9351 | 1.45M | 0U, // t2SEL |
9352 | 1.45M | 0U, // t2SETPAN |
9353 | 1.45M | 0U, // t2SG |
9354 | 1.45M | 0U, // t2SHADD16 |
9355 | 1.45M | 0U, // t2SHADD8 |
9356 | 1.45M | 0U, // t2SHASX |
9357 | 1.45M | 0U, // t2SHSAX |
9358 | 1.45M | 0U, // t2SHSUB16 |
9359 | 1.45M | 0U, // t2SHSUB8 |
9360 | 1.45M | 2U, // t2SMC |
9361 | 1.45M | 33554432U, // t2SMLABB |
9362 | 1.45M | 33554432U, // t2SMLABT |
9363 | 1.45M | 33554432U, // t2SMLAD |
9364 | 1.45M | 33554432U, // t2SMLADX |
9365 | 1.45M | 33554432U, // t2SMLAL |
9366 | 1.45M | 33554432U, // t2SMLALBB |
9367 | 1.45M | 33554432U, // t2SMLALBT |
9368 | 1.45M | 33554432U, // t2SMLALD |
9369 | 1.45M | 33554432U, // t2SMLALDX |
9370 | 1.45M | 33554432U, // t2SMLALTB |
9371 | 1.45M | 33554432U, // t2SMLALTT |
9372 | 1.45M | 33554432U, // t2SMLATB |
9373 | 1.45M | 33554432U, // t2SMLATT |
9374 | 1.45M | 33554432U, // t2SMLAWB |
9375 | 1.45M | 33554432U, // t2SMLAWT |
9376 | 1.45M | 33554432U, // t2SMLSD |
9377 | 1.45M | 33554432U, // t2SMLSDX |
9378 | 1.45M | 33554432U, // t2SMLSLD |
9379 | 1.45M | 33554432U, // t2SMLSLDX |
9380 | 1.45M | 33554432U, // t2SMMLA |
9381 | 1.45M | 33554432U, // t2SMMLAR |
9382 | 1.45M | 33554432U, // t2SMMLS |
9383 | 1.45M | 33554432U, // t2SMMLSR |
9384 | 1.45M | 0U, // t2SMMUL |
9385 | 1.45M | 0U, // t2SMMULR |
9386 | 1.45M | 0U, // t2SMUAD |
9387 | 1.45M | 0U, // t2SMUADX |
9388 | 1.45M | 0U, // t2SMULBB |
9389 | 1.45M | 0U, // t2SMULBT |
9390 | 1.45M | 33554432U, // t2SMULL |
9391 | 1.45M | 0U, // t2SMULTB |
9392 | 1.45M | 0U, // t2SMULTT |
9393 | 1.45M | 0U, // t2SMULWB |
9394 | 1.45M | 0U, // t2SMULWT |
9395 | 1.45M | 0U, // t2SMUSD |
9396 | 1.45M | 0U, // t2SMUSDX |
9397 | 1.45M | 0U, // t2SRSDB |
9398 | 1.45M | 0U, // t2SRSDB_UPD |
9399 | 1.45M | 0U, // t2SRSIA |
9400 | 1.45M | 0U, // t2SRSIA_UPD |
9401 | 1.45M | 218112U, // t2SSAT |
9402 | 1.45M | 21504U, // t2SSAT16 |
9403 | 1.45M | 0U, // t2SSAX |
9404 | 1.45M | 0U, // t2SSUB16 |
9405 | 1.45M | 0U, // t2SSUB8 |
9406 | 1.45M | 2580U, // t2STC2L_OFFSET |
9407 | 1.45M | 4721300U, // t2STC2L_OPTION |
9408 | 1.45M | 5245588U, // t2STC2L_POST |
9409 | 1.45M | 22U, // t2STC2L_PRE |
9410 | 1.45M | 2580U, // t2STC2_OFFSET |
9411 | 1.45M | 4721300U, // t2STC2_OPTION |
9412 | 1.45M | 5245588U, // t2STC2_POST |
9413 | 1.45M | 22U, // t2STC2_PRE |
9414 | 1.45M | 2580U, // t2STCL_OFFSET |
9415 | 1.45M | 4721300U, // t2STCL_OPTION |
9416 | 1.45M | 5245588U, // t2STCL_POST |
9417 | 1.45M | 22U, // t2STCL_PRE |
9418 | 1.45M | 2580U, // t2STC_OFFSET |
9419 | 1.45M | 4721300U, // t2STC_OPTION |
9420 | 1.45M | 5245588U, // t2STC_POST |
9421 | 1.45M | 22U, // t2STC_PRE |
9422 | 1.45M | 128U, // t2STL |
9423 | 1.45M | 128U, // t2STLB |
9424 | 1.45M | 10485760U, // t2STLEX |
9425 | 1.45M | 10485760U, // t2STLEXB |
9426 | 1.45M | 33554432U, // t2STLEXD |
9427 | 1.45M | 10485760U, // t2STLEXH |
9428 | 1.45M | 128U, // t2STLH |
9429 | 1.45M | 18560U, // t2STMDB |
9430 | 1.45M | 530U, // t2STMDB_UPD |
9431 | 1.45M | 18560U, // t2STMIA |
9432 | 1.45M | 530U, // t2STMIA_UPD |
9433 | 1.45M | 3968U, // t2STRBT |
9434 | 1.45M | 150144U, // t2STRB_POST |
9435 | 1.45M | 4352U, // t2STRB_PRE |
9436 | 1.45M | 3072U, // t2STRBi12 |
9437 | 1.45M | 3968U, // t2STRBi8 |
9438 | 1.45M | 8448U, // t2STRBs |
9439 | 1.45M | 510133760U, // t2STRD_POST |
9440 | 1.45M | 17827328U, // t2STRD_PRE |
9441 | 1.45M | 18350080U, // t2STRDi8 |
9442 | 1.45M | 18874368U, // t2STREX |
9443 | 1.45M | 10485760U, // t2STREXB |
9444 | 1.45M | 33554432U, // t2STREXD |
9445 | 1.45M | 10485760U, // t2STREXH |
9446 | 1.45M | 3968U, // t2STRHT |
9447 | 1.45M | 150144U, // t2STRH_POST |
9448 | 1.45M | 4352U, // t2STRH_PRE |
9449 | 1.45M | 3072U, // t2STRHi12 |
9450 | 1.45M | 3968U, // t2STRHi8 |
9451 | 1.45M | 8448U, // t2STRHs |
9452 | 1.45M | 3968U, // t2STRT |
9453 | 1.45M | 150144U, // t2STR_POST |
9454 | 1.45M | 4352U, // t2STR_PRE |
9455 | 1.45M | 3072U, // t2STRi12 |
9456 | 1.45M | 3968U, // t2STRi8 |
9457 | 1.45M | 8448U, // t2STRs |
9458 | 1.45M | 0U, // t2SUBS_PC_LR |
9459 | 1.45M | 0U, // t2SUBri |
9460 | 1.45M | 0U, // t2SUBri12 |
9461 | 1.45M | 0U, // t2SUBrr |
9462 | 1.45M | 16252928U, // t2SUBrs |
9463 | 1.45M | 0U, // t2SUBspImm |
9464 | 1.45M | 0U, // t2SUBspImm12 |
9465 | 1.45M | 268435456U, // t2SXTAB |
9466 | 1.45M | 268435456U, // t2SXTAB16 |
9467 | 1.45M | 268435456U, // t2SXTAH |
9468 | 1.45M | 229376U, // t2SXTB |
9469 | 1.45M | 229376U, // t2SXTB16 |
9470 | 1.45M | 229376U, // t2SXTH |
9471 | 1.45M | 1U, // t2TBB |
9472 | 1.45M | 1U, // t2TBH |
9473 | 1.45M | 16384U, // t2TEQri |
9474 | 1.45M | 16384U, // t2TEQrr |
9475 | 1.45M | 1024U, // t2TEQrs |
9476 | 1.45M | 1U, // t2TSB |
9477 | 1.45M | 16384U, // t2TSTri |
9478 | 1.45M | 16384U, // t2TSTrr |
9479 | 1.45M | 1024U, // t2TSTrs |
9480 | 1.45M | 16384U, // t2TT |
9481 | 1.45M | 16384U, // t2TTA |
9482 | 1.45M | 16384U, // t2TTAT |
9483 | 1.45M | 16384U, // t2TTT |
9484 | 1.45M | 0U, // t2UADD16 |
9485 | 1.45M | 0U, // t2UADD8 |
9486 | 1.45M | 0U, // t2UASX |
9487 | 1.45M | 33554432U, // t2UBFX |
9488 | 1.45M | 0U, // t2UDF |
9489 | 1.45M | 0U, // t2UDIV |
9490 | 1.45M | 0U, // t2UHADD16 |
9491 | 1.45M | 0U, // t2UHADD8 |
9492 | 1.45M | 0U, // t2UHASX |
9493 | 1.45M | 0U, // t2UHSAX |
9494 | 1.45M | 0U, // t2UHSUB16 |
9495 | 1.45M | 0U, // t2UHSUB8 |
9496 | 1.45M | 33554432U, // t2UMAAL |
9497 | 1.45M | 33554432U, // t2UMLAL |
9498 | 1.45M | 33554432U, // t2UMULL |
9499 | 1.45M | 0U, // t2UQADD16 |
9500 | 1.45M | 0U, // t2UQADD8 |
9501 | 1.45M | 0U, // t2UQASX |
9502 | 1.45M | 0U, // t2UQSAX |
9503 | 1.45M | 0U, // t2UQSUB16 |
9504 | 1.45M | 0U, // t2UQSUB8 |
9505 | 1.45M | 0U, // t2USAD8 |
9506 | 1.45M | 33554432U, // t2USADA8 |
9507 | 1.45M | 301989888U, // t2USAT |
9508 | 1.45M | 0U, // t2USAT16 |
9509 | 1.45M | 0U, // t2USAX |
9510 | 1.45M | 0U, // t2USUB16 |
9511 | 1.45M | 0U, // t2USUB8 |
9512 | 1.45M | 268435456U, // t2UXTAB |
9513 | 1.45M | 268435456U, // t2UXTAB16 |
9514 | 1.45M | 268435456U, // t2UXTAH |
9515 | 1.45M | 229376U, // t2UXTB |
9516 | 1.45M | 229376U, // t2UXTB16 |
9517 | 1.45M | 229376U, // t2UXTH |
9518 | 1.45M | 21376U, // t2WLS |
9519 | 1.45M | 2U, // tADC |
9520 | 1.45M | 17920U, // tADDhirr |
9521 | 1.45M | 16768U, // tADDi3 |
9522 | 1.45M | 2U, // tADDi8 |
9523 | 1.45M | 0U, // tADDrSP |
9524 | 1.45M | 19398656U, // tADDrSPi |
9525 | 1.45M | 16768U, // tADDrr |
9526 | 1.45M | 8832U, // tADDspi |
9527 | 1.45M | 17920U, // tADDspr |
9528 | 1.45M | 8960U, // tADR |
9529 | 1.45M | 2U, // tAND |
9530 | 1.45M | 9088U, // tASRri |
9531 | 1.45M | 2U, // tASRrr |
9532 | 1.45M | 2U, // tB |
9533 | 1.45M | 2U, // tBIC |
9534 | 1.45M | 0U, // tBKPT |
9535 | 1.45M | 0U, // tBL |
9536 | 1.45M | 2U, // tBLXNSr |
9537 | 1.45M | 0U, // tBLXi |
9538 | 1.45M | 2U, // tBLXr |
9539 | 1.45M | 2U, // tBX |
9540 | 1.45M | 2U, // tBXNS |
9541 | 1.45M | 2U, // tBcc |
9542 | 1.45M | 2U, // tCBNZ |
9543 | 1.45M | 2U, // tCBZ |
9544 | 1.45M | 16384U, // tCMNz |
9545 | 1.45M | 16384U, // tCMPhir |
9546 | 1.45M | 16384U, // tCMPi8 |
9547 | 1.45M | 16384U, // tCMPr |
9548 | 1.45M | 2U, // tCPS |
9549 | 1.45M | 2U, // tEOR |
9550 | 1.45M | 2U, // tHINT |
9551 | 1.45M | 0U, // tHLT |
9552 | 1.45M | 0U, // tInt_WIN_eh_sjlj_longjmp |
9553 | 1.45M | 0U, // tInt_eh_sjlj_longjmp |
9554 | 1.45M | 0U, // tInt_eh_sjlj_setjmp |
9555 | 1.45M | 18560U, // tLDMIA |
9556 | 1.45M | 9216U, // tLDRBi |
9557 | 1.45M | 9344U, // tLDRBr |
9558 | 1.45M | 9472U, // tLDRHi |
9559 | 1.45M | 9344U, // tLDRHr |
9560 | 1.45M | 9344U, // tLDRSB |
9561 | 1.45M | 9344U, // tLDRSH |
9562 | 1.45M | 9600U, // tLDRi |
9563 | 1.45M | 8320U, // tLDRpci |
9564 | 1.45M | 9344U, // tLDRr |
9565 | 1.45M | 9728U, // tLDRspi |
9566 | 1.45M | 16768U, // tLSLri |
9567 | 1.45M | 2U, // tLSLrr |
9568 | 1.45M | 9088U, // tLSRri |
9569 | 1.45M | 2U, // tLSRrr |
9570 | 1.45M | 2U, // tMOVSr |
9571 | 1.45M | 0U, // tMOVi8 |
9572 | 1.45M | 16384U, // tMOVr |
9573 | 1.45M | 16768U, // tMUL |
9574 | 1.45M | 0U, // tMVN |
9575 | 1.45M | 2U, // tORR |
9576 | 1.45M | 0U, // tPICADD |
9577 | 1.45M | 0U, // tPOP |
9578 | 1.45M | 0U, // tPUSH |
9579 | 1.45M | 16384U, // tREV |
9580 | 1.45M | 16384U, // tREV16 |
9581 | 1.45M | 16384U, // tREVSH |
9582 | 1.45M | 2U, // tROR |
9583 | 1.45M | 0U, // tRSB |
9584 | 1.45M | 2U, // tSBC |
9585 | 1.45M | 0U, // tSETEND |
9586 | 1.45M | 530U, // tSTMIA_UPD |
9587 | 1.45M | 9216U, // tSTRBi |
9588 | 1.45M | 9344U, // tSTRBr |
9589 | 1.45M | 9472U, // tSTRHi |
9590 | 1.45M | 9344U, // tSTRHr |
9591 | 1.45M | 9600U, // tSTRi |
9592 | 1.45M | 9344U, // tSTRr |
9593 | 1.45M | 9728U, // tSTRspi |
9594 | 1.45M | 16768U, // tSUBi3 |
9595 | 1.45M | 2U, // tSUBi8 |
9596 | 1.45M | 16768U, // tSUBrr |
9597 | 1.45M | 8832U, // tSUBspi |
9598 | 1.45M | 2U, // tSVC |
9599 | 1.45M | 16384U, // tSXTB |
9600 | 1.45M | 16384U, // tSXTH |
9601 | 1.45M | 0U, // tTRAP |
9602 | 1.45M | 16384U, // tTST |
9603 | 1.45M | 0U, // tUDF |
9604 | 1.45M | 16384U, // tUXTB |
9605 | 1.45M | 16384U, // tUXTH |
9606 | 1.45M | 0U, // t__brkdiv0 |
9607 | 1.45M | }; |
9608 | | |
9609 | | // Emit the opcode for the instruction. |
9610 | 1.45M | uint64_t Bits = 0; |
9611 | 1.45M | Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; |
9612 | 1.45M | Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; |
9613 | 1.45M | MnemonicBitsInfo MBI = { |
9614 | 1.45M | #ifndef CAPSTONE_DIET |
9615 | 1.45M | AsmStrs + (Bits & 8191) - 1, |
9616 | | #else |
9617 | | NULL, |
9618 | | #endif // CAPSTONE_DIET |
9619 | 1.45M | Bits |
9620 | 1.45M | }; |
9621 | 1.45M | return MBI; |
9622 | 1.45M | } |
9623 | | |
9624 | | /// printInstruction - This method is automatically generated by tablegen |
9625 | | /// from the instruction set description. |
9626 | | void printInstruction(MCInst *MI, uint64_t Address, SStream *O) |
9627 | 1.45M | { |
9628 | 1.45M | SStream_concat0(O, ""); |
9629 | 1.45M | MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); |
9630 | | |
9631 | 1.45M | SStream_concat0(O, MnemonicInfo.first); |
9632 | | |
9633 | 1.45M | uint64_t Bits = MnemonicInfo.second; |
9634 | 1.45M | assert(Bits != 0 && "Cannot print this instruction."); |
9635 | | |
9636 | | // Fragment 0 encoded into 6 bits for 43 unique commands. |
9637 | 1.45M | switch ((uint32_t)((Bits >> 13) & 63)) { |
9638 | 0 | default: |
9639 | 0 | assert(0 && "Invalid command number."); |
9640 | 947 | case 0: |
9641 | | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
9642 | 947 | return; |
9643 | 0 | break; |
9644 | 22.6k | case 1: |
9645 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... |
9646 | 22.6k | printSBitModifierOperand(MI, 5, O); |
9647 | 22.6k | printPredicateOperand(MI, 3, O); |
9648 | 22.6k | break; |
9649 | 18.3k | case 2: |
9650 | | // ITasm, t2IT |
9651 | 18.3k | printThumbITMask(MI, 1, O); |
9652 | 18.3k | break; |
9653 | 165k | case 3: |
9654 | | // LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRB... |
9655 | 165k | printPredicateOperand(MI, 2, O); |
9656 | 165k | break; |
9657 | 1.67k | case 4: |
9658 | | // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... |
9659 | 1.67k | printSBitModifierOperand(MI, 4, O); |
9660 | 1.67k | printPredicateOperand(MI, 2, O); |
9661 | 1.67k | break; |
9662 | 69.4k | case 5: |
9663 | | // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... |
9664 | 69.4k | printPredicateOperand(MI, 4, O); |
9665 | 69.4k | break; |
9666 | 59.9k | case 6: |
9667 | | // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... |
9668 | 59.9k | printPredicateOperand(MI, 5, O); |
9669 | 59.9k | break; |
9670 | 351k | case 7: |
9671 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... |
9672 | 351k | printPredicateOperand(MI, 3, O); |
9673 | 351k | break; |
9674 | 15.5k | case 8: |
9675 | | // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... |
9676 | 15.5k | printSBitModifierOperand(MI, 6, O); |
9677 | 15.5k | printPredicateOperand(MI, 4, O); |
9678 | 15.5k | break; |
9679 | 5.54k | case 9: |
9680 | | // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... |
9681 | 5.54k | printSBitModifierOperand(MI, 7, O); |
9682 | 5.54k | printPredicateOperand(MI, 5, O); |
9683 | 5.54k | SStream_concat0(O, "\t"); |
9684 | 5.54k | printOperand(MI, 0, O); |
9685 | 5.54k | SStream_concat0(O, ", "); |
9686 | 5.54k | printOperand(MI, 1, O); |
9687 | 5.54k | SStream_concat0(O, ", "); |
9688 | 5.54k | printSORegRegOperand(MI, 2, O); |
9689 | 5.54k | return; |
9690 | 0 | break; |
9691 | 162k | case 10: |
9692 | | // AESD, AESE, AESIMC, AESMC, BKPT, BLX, BX, CPS1p, CRC32B, CRC32CB, CRC3... |
9693 | 162k | printOperand(MI, 0, O); |
9694 | 162k | break; |
9695 | 1.13k | case 11: |
9696 | | // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MV... |
9697 | 1.13k | printOperand(MI, 1, O); |
9698 | 1.13k | break; |
9699 | 990 | case 12: |
9700 | | // BL, BLXi, t2BFic, t2LE |
9701 | 990 | printOperandAddr(MI, Address, 0, O); |
9702 | 990 | break; |
9703 | 79.5k | case 13: |
9704 | | // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... |
9705 | 79.5k | printPredicateOperand(MI, 1, O); |
9706 | 79.5k | break; |
9707 | 17.6k | case 14: |
9708 | | // BX_RET, ERET, FMSTAT, MOVPCLR, MVE_LCTP, VSCCLRMD, VSCCLRMS, t2AUTG, t... |
9709 | 17.6k | printPredicateOperand(MI, 0, O); |
9710 | 17.6k | break; |
9711 | 1.95k | case 15: |
9712 | | // CDE_CX1, CDE_CX1D, CDE_CX2, CDE_CX2D, CDE_CX3, CDE_CX3D, CDE_VCX1A_fpd... |
9713 | 1.95k | printPImmediate(MI, 1, O); |
9714 | 1.95k | SStream_concat0(O, ", "); |
9715 | 1.95k | break; |
9716 | 46.6k | case 16: |
9717 | | // CDE_CX3A, CDE_CX3DA, CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, ... |
9718 | 46.6k | printPredicateOperand(MI, 6, O); |
9719 | 46.6k | break; |
9720 | 16.8k | case 17: |
9721 | | // CDE_VCX1A_vec, CDE_VCX2_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, ... |
9722 | 16.8k | printVPTPredicateOperand(MI, 4, O); |
9723 | 16.8k | break; |
9724 | 14.3k | case 18: |
9725 | | // CDE_VCX1_vec, MVE_VABDf16, MVE_VABDf32, MVE_VABDs16, MVE_VABDs32, MVE_... |
9726 | 14.3k | printVPTPredicateOperand(MI, 3, O); |
9727 | 14.3k | break; |
9728 | 3.46k | case 19: |
9729 | | // CDE_VCX2A_vec, CDE_VCX3_vec, MVE_VADC, MVE_VADDLVs32acc, MVE_VADDLVu32... |
9730 | 3.46k | printVPTPredicateOperand(MI, 5, O); |
9731 | 3.46k | break; |
9732 | 1.49k | case 20: |
9733 | | // CDE_VCX3A_vec, MVE_VMLALDAVas16, MVE_VMLALDAVas32, MVE_VMLALDAVau16, M... |
9734 | 1.49k | printVPTPredicateOperand(MI, 6, O); |
9735 | 1.49k | break; |
9736 | 5.13k | case 21: |
9737 | | // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION... |
9738 | 5.13k | printPImmediate(MI, 0, O); |
9739 | 5.13k | SStream_concat0(O, ", "); |
9740 | 5.13k | break; |
9741 | 1.59k | case 22: |
9742 | | // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS |
9743 | 1.59k | printCPSIMod(MI, 0, O); |
9744 | 1.59k | break; |
9745 | 601 | case 23: |
9746 | | // DMB, DSB |
9747 | 601 | printMemBOption(MI, 0, O); |
9748 | 601 | return; |
9749 | 0 | break; |
9750 | 397 | case 24: |
9751 | | // ISB |
9752 | 397 | printInstSyncBOption(MI, 0, O); |
9753 | 397 | return; |
9754 | 0 | break; |
9755 | 194 | case 25: |
9756 | | // MRRC2 |
9757 | 194 | printPImmediate(MI, 2, O); |
9758 | 194 | SStream_concat0(O, ", "); |
9759 | 194 | printOperand(MI, 3, O); |
9760 | 194 | SStream_concat0(O, ", "); |
9761 | 194 | printOperand(MI, 0, O); |
9762 | 194 | SStream_concat0(O, ", "); |
9763 | 194 | printOperand(MI, 1, O); |
9764 | 194 | SStream_concat0(O, ", "); |
9765 | 194 | printCImmediate(MI, 4, O); |
9766 | 194 | return; |
9767 | 0 | break; |
9768 | 3.66k | case 26: |
9769 | | // MVE_VABSf16, MVE_VABSf32, MVE_VABSs16, MVE_VABSs32, MVE_VABSs8, MVE_VA... |
9770 | 3.66k | printVPTPredicateOperand(MI, 2, O); |
9771 | 3.66k | break; |
9772 | 743 | case 27: |
9773 | | // MVE_VLD20_16, MVE_VLD20_16_wb, MVE_VLD20_32, MVE_VLD20_32_wb, MVE_VLD2... |
9774 | 743 | printMVEVectorList_2(MI, 0, O); |
9775 | 743 | SStream_concat0(O, ", "); |
9776 | 743 | break; |
9777 | 759 | case 28: |
9778 | | // MVE_VLD40_16, MVE_VLD40_16_wb, MVE_VLD40_32, MVE_VLD40_32_wb, MVE_VLD4... |
9779 | 759 | printMVEVectorList_4(MI, 0, O); |
9780 | 759 | SStream_concat0(O, ", "); |
9781 | 759 | break; |
9782 | 9.96k | case 29: |
9783 | | // MVE_VPST, MVE_VPTv16i8, MVE_VPTv16i8r, MVE_VPTv16s8, MVE_VPTv16s8r, MV... |
9784 | 9.96k | printVPTMask(MI, 0, O); |
9785 | 9.96k | break; |
9786 | 91 | case 30: |
9787 | | // MVE_VST20_16_wb, MVE_VST20_32_wb, MVE_VST20_8_wb, MVE_VST21_16_wb, MVE... |
9788 | 91 | printMVEVectorList_2(MI, 1, O); |
9789 | 91 | SStream_concat0(O, ", "); |
9790 | 91 | printAddrMode7Operand(MI, 2, O); |
9791 | 91 | SStream_concat1(O, '!'); |
9792 | 91 | return; |
9793 | 0 | break; |
9794 | 112 | case 31: |
9795 | | // MVE_VST40_16_wb, MVE_VST40_32_wb, MVE_VST40_8_wb, MVE_VST41_16_wb, MVE... |
9796 | 112 | printMVEVectorList_4(MI, 1, O); |
9797 | 112 | SStream_concat0(O, ", "); |
9798 | 112 | printAddrMode7Operand(MI, 2, O); |
9799 | 112 | SStream_concat1(O, '!'); |
9800 | 112 | return; |
9801 | 0 | break; |
9802 | 42 | case 32: |
9803 | | // PLDWi12, PLDi12, PLIi12 |
9804 | 42 | printAddrModeImm12Operand_0(MI, 0, O); |
9805 | 42 | return; |
9806 | 0 | break; |
9807 | 78 | case 33: |
9808 | | // PLDWrs, PLDrs, PLIrs |
9809 | 78 | printAddrMode2Operand(MI, 0, O); |
9810 | 78 | return; |
9811 | 0 | break; |
9812 | 162 | case 34: |
9813 | | // SETEND, tSETEND |
9814 | 162 | printSetendOperand(MI, 0, O); |
9815 | 162 | return; |
9816 | 0 | break; |
9817 | 407 | case 35: |
9818 | | // SMLAL, UMLAL |
9819 | 407 | printSBitModifierOperand(MI, 8, O); |
9820 | 407 | printPredicateOperand(MI, 6, O); |
9821 | 407 | SStream_concat0(O, "\t"); |
9822 | 407 | printOperand(MI, 0, O); |
9823 | 407 | SStream_concat0(O, ", "); |
9824 | 407 | printOperand(MI, 1, O); |
9825 | 407 | SStream_concat0(O, ", "); |
9826 | 407 | printOperand(MI, 2, O); |
9827 | 407 | SStream_concat0(O, ", "); |
9828 | 407 | printOperand(MI, 3, O); |
9829 | 407 | return; |
9830 | 0 | break; |
9831 | 0 | case 36: |
9832 | | // TSB |
9833 | 0 | printTraceSyncBOption(MI, 0, O); |
9834 | 0 | return; |
9835 | 0 | break; |
9836 | 6.83k | case 37: |
9837 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... |
9838 | 6.83k | printPredicateOperand(MI, 7, O); |
9839 | 6.83k | break; |
9840 | 3.09k | case 38: |
9841 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
9842 | 3.09k | printPredicateOperand(MI, 9, O); |
9843 | 3.09k | break; |
9844 | 2.18k | case 39: |
9845 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
9846 | 2.18k | printPredicateOperand(MI, 11, O); |
9847 | 2.18k | break; |
9848 | 7.21k | case 40: |
9849 | | // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... |
9850 | 7.21k | printPredicateOperand(MI, 8, O); |
9851 | 7.21k | break; |
9852 | 1.22k | case 41: |
9853 | | // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... |
9854 | 1.22k | printPredicateOperand(MI, 13, O); |
9855 | 1.22k | break; |
9856 | 349k | case 42: |
9857 | | // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... |
9858 | 349k | printSBitModifierOperand(MI, 1, O); |
9859 | 349k | break; |
9860 | 1.45M | } |
9861 | | |
9862 | | // Fragment 1 encoded into 7 bits for 89 unique commands. |
9863 | 1.44M | switch ((uint32_t)((Bits >> 19) & 127)) { |
9864 | 0 | default: |
9865 | 0 | assert(0 && "Invalid command number."); |
9866 | 417 | case 0: |
9867 | | // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT... |
9868 | 417 | SStream_concat1(O, ' '); |
9869 | 417 | break; |
9870 | 9.73k | case 1: |
9871 | | // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... |
9872 | 9.73k | SStream_concat0(O, ".16\t"); |
9873 | 9.73k | ARM_add_vector_size(MI, 16); |
9874 | 9.73k | break; |
9875 | 13.2k | case 2: |
9876 | | // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... |
9877 | 13.2k | SStream_concat0(O, ".32\t"); |
9878 | 13.2k | ARM_add_vector_size(MI, 32); |
9879 | 13.2k | break; |
9880 | 13.0k | case 3: |
9881 | | // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... |
9882 | 13.0k | SStream_concat0(O, ".8\t"); |
9883 | 13.0k | ARM_add_vector_size(MI, 8); |
9884 | 13.0k | break; |
9885 | 0 | case 4: |
9886 | | // t2LDR_POST_imm, t2LDR_PRE_imm, t2STR_POST_imm, t2STR_PRE_imm |
9887 | 0 | SStream_concat0(O, ".w "); |
9888 | 0 | printOperand(MI, 0, O); |
9889 | 0 | SStream_concat0(O, ", "); |
9890 | 0 | break; |
9891 | 742k | case 5: |
9892 | | // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... |
9893 | 742k | SStream_concat0(O, "\t"); |
9894 | 742k | break; |
9895 | 158k | case 6: |
9896 | | // AESD, AESE, AESIMC, AESMC, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS... |
9897 | 158k | SStream_concat0(O, ", "); |
9898 | 158k | break; |
9899 | 19 | case 7: |
9900 | | // BF16_VCVT, BF16_VCVTB, BF16_VCVTT |
9901 | 19 | SStream_concat0(O, ".bf16.f32\t"); |
9902 | 19 | printOperand(MI, 0, O); |
9903 | 19 | SStream_concat0(O, ", "); |
9904 | 19 | break; |
9905 | 5.53k | case 8: |
9906 | | // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... |
9907 | 5.53k | return; |
9908 | 0 | break; |
9909 | 19 | case 9: |
9910 | | // BX_RET |
9911 | 19 | SStream_concat0(O, "\tlr"); |
9912 | 19 | return; |
9913 | 0 | break; |
9914 | 0 | case 10: |
9915 | | // CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX1_fp... |
9916 | 0 | printOperand(MI, 0, O); |
9917 | 0 | SStream_concat0(O, ", "); |
9918 | 0 | break; |
9919 | 0 | case 11: |
9920 | | // CDE_CX1D, CDE_CX2D, CDE_CX3D |
9921 | 0 | printGPRPairOperand(MI, 0, O); |
9922 | 0 | SStream_concat0(O, ", "); |
9923 | 0 | printOperand(MI, 2, O); |
9924 | 0 | break; |
9925 | 2.18k | case 12: |
9926 | | // CDP2, MCR2, MCRR2 |
9927 | 2.18k | printOperand(MI, 1, O); |
9928 | 2.18k | SStream_concat0(O, ", "); |
9929 | 2.18k | break; |
9930 | 1.62k | case 13: |
9931 | | // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... |
9932 | 1.62k | SStream_concat0(O, ".f64\t"); |
9933 | 1.62k | ARM_add_vector_data(MI, ARM_VECTORDATA_F64); |
9934 | 1.62k | printOperand(MI, 0, O); |
9935 | 1.62k | break; |
9936 | 6.90k | case 14: |
9937 | | // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V... |
9938 | 6.90k | SStream_concat0(O, ".f16\t"); |
9939 | 6.90k | ARM_add_vector_data(MI, ARM_VECTORDATA_F16); |
9940 | 6.90k | break; |
9941 | 6.09k | case 15: |
9942 | | // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V... |
9943 | 6.09k | SStream_concat0(O, ".f32\t"); |
9944 | 6.09k | ARM_add_vector_data(MI, ARM_VECTORDATA_F32); |
9945 | 6.09k | break; |
9946 | 68 | case 16: |
9947 | | // FMSTAT |
9948 | 68 | SStream_concat0(O, "\tAPSR_nzcv, fpscr"); |
9949 | 68 | return; |
9950 | 0 | break; |
9951 | 2.94k | case 17: |
9952 | | // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION, LDC2... |
9953 | 2.94k | printCImmediate(MI, 1, O); |
9954 | 2.94k | SStream_concat0(O, ", "); |
9955 | 2.94k | break; |
9956 | 1.31k | case 18: |
9957 | | // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE |
9958 | 1.31k | printCImmediate(MI, 2, O); |
9959 | 1.31k | SStream_concat0(O, ", "); |
9960 | 1.31k | printAddrMode5Operand_1(MI, 3, O); |
9961 | 1.31k | SStream_concat1(O, '!'); |
9962 | 1.31k | return; |
9963 | 0 | break; |
9964 | 20 | case 19: |
9965 | | // MOVPCLR |
9966 | 20 | SStream_concat0(O, "\tpc, lr"); |
9967 | 20 | return; |
9968 | 0 | break; |
9969 | 636 | case 20: |
9970 | | // MRC2 |
9971 | 636 | printOperand(MI, 2, O); |
9972 | 636 | SStream_concat0(O, ", "); |
9973 | 636 | printOperand(MI, 0, O); |
9974 | 636 | SStream_concat0(O, ", "); |
9975 | 636 | printCImmediate(MI, 3, O); |
9976 | 636 | SStream_concat0(O, ", "); |
9977 | 636 | printCImmediate(MI, 4, O); |
9978 | 636 | SStream_concat0(O, ", "); |
9979 | 636 | printOperand(MI, 5, O); |
9980 | 636 | return; |
9981 | 0 | break; |
9982 | 5.90k | case 21: |
9983 | | // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n... |
9984 | 5.90k | SStream_concat0(O, ".s16\t"); |
9985 | 5.90k | ARM_add_vector_data(MI, ARM_VECTORDATA_S16); |
9986 | 5.90k | break; |
9987 | 8.14k | case 22: |
9988 | | // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3... |
9989 | 8.14k | SStream_concat0(O, ".s32\t"); |
9990 | 8.14k | ARM_add_vector_data(MI, ARM_VECTORDATA_S32); |
9991 | 8.14k | break; |
9992 | 4.24k | case 23: |
9993 | | // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc... |
9994 | 4.24k | SStream_concat0(O, ".s8\t"); |
9995 | 4.24k | ARM_add_vector_data(MI, ARM_VECTORDATA_S8); |
9996 | 4.24k | break; |
9997 | 6.76k | case 24: |
9998 | | // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC... |
9999 | 6.76k | SStream_concat0(O, ".u16\t"); |
10000 | 6.76k | ARM_add_vector_data(MI, ARM_VECTORDATA_U16); |
10001 | 6.76k | break; |
10002 | 10.0k | case 25: |
10003 | | // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_... |
10004 | 10.0k | SStream_concat0(O, ".u32\t"); |
10005 | 10.0k | ARM_add_vector_data(MI, ARM_VECTORDATA_U32); |
10006 | 10.0k | break; |
10007 | 7.91k | case 26: |
10008 | | // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8... |
10009 | 7.91k | SStream_concat0(O, ".u8\t"); |
10010 | 7.91k | ARM_add_vector_data(MI, ARM_VECTORDATA_U8); |
10011 | 7.91k | break; |
10012 | 7.07k | case 27: |
10013 | | // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE... |
10014 | 7.07k | SStream_concat0(O, ".i32\t"); |
10015 | 7.07k | ARM_add_vector_data(MI, ARM_VECTORDATA_I32); |
10016 | 7.07k | break; |
10017 | 3.19k | case 28: |
10018 | | // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1... |
10019 | 3.19k | SStream_concat0(O, ".i16\t"); |
10020 | 3.19k | ARM_add_vector_data(MI, ARM_VECTORDATA_I16); |
10021 | 3.19k | break; |
10022 | 1.45k | case 29: |
10023 | | // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V... |
10024 | 1.45k | SStream_concat0(O, ".i8\t"); |
10025 | 1.45k | ARM_add_vector_data(MI, ARM_VECTORDATA_I8); |
10026 | 1.45k | break; |
10027 | 2.88k | case 30: |
10028 | | // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS... |
10029 | 2.88k | SStream_concat0(O, ".64\t"); |
10030 | 2.88k | ARM_add_vector_size(MI, 64); |
10031 | 2.88k | break; |
10032 | 779 | case 31: |
10033 | | // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h |
10034 | 779 | SStream_concat0(O, ".f16.f32\t"); |
10035 | 779 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32); |
10036 | 779 | printOperand(MI, 0, O); |
10037 | 779 | SStream_concat0(O, ", "); |
10038 | 779 | break; |
10039 | 59 | case 32: |
10040 | | // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC... |
10041 | 59 | SStream_concat0(O, ".f16.s16\t"); |
10042 | 59 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16S16); |
10043 | 59 | printOperand(MI, 0, O); |
10044 | 59 | SStream_concat0(O, ", "); |
10045 | 59 | printOperand(MI, 1, O); |
10046 | 59 | break; |
10047 | 172 | case 33: |
10048 | | // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC... |
10049 | 172 | SStream_concat0(O, ".f16.u16\t"); |
10050 | 172 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16U16); |
10051 | 172 | printOperand(MI, 0, O); |
10052 | 172 | SStream_concat0(O, ", "); |
10053 | 172 | printOperand(MI, 1, O); |
10054 | 172 | break; |
10055 | 364 | case 34: |
10056 | | // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f |
10057 | 364 | SStream_concat0(O, ".f32.f16\t"); |
10058 | 364 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32F16); |
10059 | 364 | printOperand(MI, 0, O); |
10060 | 364 | SStream_concat0(O, ", "); |
10061 | 364 | printOperand(MI, 1, O); |
10062 | 364 | return; |
10063 | 0 | break; |
10064 | 433 | case 35: |
10065 | | // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC... |
10066 | 433 | SStream_concat0(O, ".f32.s32\t"); |
10067 | 433 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32S32); |
10068 | 433 | printOperand(MI, 0, O); |
10069 | 433 | SStream_concat0(O, ", "); |
10070 | 433 | printOperand(MI, 1, O); |
10071 | 433 | break; |
10072 | 712 | case 36: |
10073 | | // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC... |
10074 | 712 | SStream_concat0(O, ".f32.u32\t"); |
10075 | 712 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32U32); |
10076 | 712 | printOperand(MI, 0, O); |
10077 | 712 | SStream_concat0(O, ", "); |
10078 | 712 | printOperand(MI, 1, O); |
10079 | 712 | break; |
10080 | 1.00k | case 37: |
10081 | | // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,... |
10082 | 1.00k | SStream_concat0(O, ".s16.f16\t"); |
10083 | 1.00k | ARM_add_vector_data(MI, ARM_VECTORDATA_S16F16); |
10084 | 1.00k | printOperand(MI, 0, O); |
10085 | 1.00k | SStream_concat0(O, ", "); |
10086 | 1.00k | printOperand(MI, 1, O); |
10087 | 1.00k | break; |
10088 | 176 | case 38: |
10089 | | // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,... |
10090 | 176 | SStream_concat0(O, ".s32.f32\t"); |
10091 | 176 | ARM_add_vector_data(MI, ARM_VECTORDATA_S32F32); |
10092 | 176 | printOperand(MI, 0, O); |
10093 | 176 | SStream_concat0(O, ", "); |
10094 | 176 | printOperand(MI, 1, O); |
10095 | 176 | break; |
10096 | 444 | case 39: |
10097 | | // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,... |
10098 | 444 | SStream_concat0(O, ".u16.f16\t"); |
10099 | 444 | ARM_add_vector_data(MI, ARM_VECTORDATA_U16F16); |
10100 | 444 | printOperand(MI, 0, O); |
10101 | 444 | SStream_concat0(O, ", "); |
10102 | 444 | printOperand(MI, 1, O); |
10103 | 444 | break; |
10104 | 627 | case 40: |
10105 | | // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,... |
10106 | 627 | SStream_concat0(O, ".u32.f32\t"); |
10107 | 627 | ARM_add_vector_data(MI, ARM_VECTORDATA_U32F32); |
10108 | 627 | printOperand(MI, 0, O); |
10109 | 627 | SStream_concat0(O, ", "); |
10110 | 627 | printOperand(MI, 1, O); |
10111 | 627 | break; |
10112 | 644 | case 41: |
10113 | | // MVE_VLD20_16, MVE_VLD20_32, MVE_VLD20_8, MVE_VLD21_16, MVE_VLD21_32, M... |
10114 | 644 | printAddrMode7Operand(MI, 2, O); |
10115 | 644 | return; |
10116 | 0 | break; |
10117 | 104 | case 42: |
10118 | | // MVE_VLD20_16_wb, MVE_VLD20_32_wb, MVE_VLD20_8_wb, MVE_VLD21_16_wb, MVE... |
10119 | 104 | printAddrMode7Operand(MI, 3, O); |
10120 | 104 | SStream_concat1(O, '!'); |
10121 | 104 | return; |
10122 | 0 | break; |
10123 | 1.31k | case 43: |
10124 | | // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq... |
10125 | 1.31k | SStream_concat0(O, ".u64\t"); |
10126 | 1.31k | ARM_add_vector_data(MI, ARM_VECTORDATA_U64); |
10127 | 1.31k | break; |
10128 | 1.12k | case 44: |
10129 | | // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i... |
10130 | 1.12k | SStream_concat0(O, ".i64\t"); |
10131 | 1.12k | ARM_add_vector_data(MI, ARM_VECTORDATA_I64); |
10132 | 1.12k | printOperand(MI, 0, O); |
10133 | 1.12k | SStream_concat0(O, ", "); |
10134 | 1.12k | break; |
10135 | 100 | case 45: |
10136 | | // MVE_VMULLBp16, MVE_VMULLTp16 |
10137 | 100 | SStream_concat0(O, ".p16\t"); |
10138 | 100 | ARM_add_vector_data(MI, ARM_VECTORDATA_P16); |
10139 | 100 | printOperand(MI, 0, O); |
10140 | 100 | SStream_concat0(O, ", "); |
10141 | 100 | printOperand(MI, 1, O); |
10142 | 100 | SStream_concat0(O, ", "); |
10143 | 100 | printOperand(MI, 2, O); |
10144 | 100 | return; |
10145 | 0 | break; |
10146 | 104 | case 46: |
10147 | | // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq |
10148 | 104 | SStream_concat0(O, ".p8\t"); |
10149 | 104 | ARM_add_vector_data(MI, ARM_VECTORDATA_P8); |
10150 | 104 | printOperand(MI, 0, O); |
10151 | 104 | SStream_concat0(O, ", "); |
10152 | 104 | printOperand(MI, 1, O); |
10153 | 104 | SStream_concat0(O, ", "); |
10154 | 104 | printOperand(MI, 2, O); |
10155 | 104 | return; |
10156 | 0 | break; |
10157 | 754 | case 47: |
10158 | | // MVE_VST20_16, MVE_VST20_32, MVE_VST20_8, MVE_VST21_16, MVE_VST21_32, M... |
10159 | 754 | printAddrMode7Operand(MI, 1, O); |
10160 | 754 | return; |
10161 | 0 | break; |
10162 | 609 | case 48: |
10163 | | // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD |
10164 | 609 | SStream_concat1(O, '!'); |
10165 | 609 | return; |
10166 | 0 | break; |
10167 | 154 | case 49: |
10168 | | // VCVTBDH, VCVTTDH |
10169 | 154 | SStream_concat0(O, ".f16.f64\t"); |
10170 | 154 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16F64); |
10171 | 154 | printOperand(MI, 0, O); |
10172 | 154 | SStream_concat0(O, ", "); |
10173 | 154 | printOperand(MI, 2, O); |
10174 | 154 | return; |
10175 | 0 | break; |
10176 | 47 | case 50: |
10177 | | // VCVTBHD, VCVTTHD |
10178 | 47 | SStream_concat0(O, ".f64.f16\t"); |
10179 | 47 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64F16); |
10180 | 47 | printOperand(MI, 0, O); |
10181 | 47 | SStream_concat0(O, ", "); |
10182 | 47 | printOperand(MI, 1, O); |
10183 | 47 | return; |
10184 | 0 | break; |
10185 | 362 | case 51: |
10186 | | // VCVTDS |
10187 | 362 | SStream_concat0(O, ".f64.f32\t"); |
10188 | 362 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64F32); |
10189 | 362 | printOperand(MI, 0, O); |
10190 | 362 | SStream_concat0(O, ", "); |
10191 | 362 | printOperand(MI, 1, O); |
10192 | 362 | return; |
10193 | 0 | break; |
10194 | 13 | case 52: |
10195 | | // VCVTSD |
10196 | 13 | SStream_concat0(O, ".f32.f64\t"); |
10197 | 13 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32F64); |
10198 | 13 | printOperand(MI, 0, O); |
10199 | 13 | SStream_concat0(O, ", "); |
10200 | 13 | printOperand(MI, 1, O); |
10201 | 13 | return; |
10202 | 0 | break; |
10203 | 104 | case 53: |
10204 | | // VJCVT, VTOSIRD, VTOSIZD, VTOSLD |
10205 | 104 | SStream_concat0(O, ".s32.f64\t"); |
10206 | 104 | ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64); |
10207 | 104 | printOperand(MI, 0, O); |
10208 | 104 | SStream_concat0(O, ", "); |
10209 | 104 | printOperand(MI, 1, O); |
10210 | 104 | break; |
10211 | 11.3k | case 54: |
10212 | | // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... |
10213 | 11.3k | SStream_concat0(O, ".16\t{"); |
10214 | 11.3k | ARM_add_vector_size(MI, 16); |
10215 | 11.3k | break; |
10216 | 8.12k | case 55: |
10217 | | // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... |
10218 | 8.12k | SStream_concat0(O, ".32\t{"); |
10219 | 8.12k | ARM_add_vector_size(MI, 32); |
10220 | 8.12k | break; |
10221 | 9.50k | case 56: |
10222 | | // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... |
10223 | 9.50k | SStream_concat0(O, ".8\t{"); |
10224 | 9.50k | ARM_add_vector_size(MI, 8); |
10225 | 9.50k | break; |
10226 | 270 | case 57: |
10227 | | // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V... |
10228 | 270 | SStream_concat0(O, "\tfpcxtns, "); |
10229 | 270 | break; |
10230 | 271 | case 58: |
10231 | | // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_... |
10232 | 271 | SStream_concat0(O, "\tfpcxts, "); |
10233 | 271 | break; |
10234 | 670 | case 59: |
10235 | | // VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_NZCVQC_post, VLDR_FPSCR_NZCVQC_pre, ... |
10236 | 670 | SStream_concat0(O, "\tfpscr_nzcvqc, "); |
10237 | 670 | break; |
10238 | 1.12k | case 60: |
10239 | | // VLDR_FPSCR_off, VLDR_FPSCR_post, VLDR_FPSCR_pre, VMSR, VSTR_FPSCR_off,... |
10240 | 1.12k | SStream_concat0(O, "\tfpscr, "); |
10241 | 1.12k | break; |
10242 | 0 | case 61: |
10243 | | // VLDR_P0_off, VLDR_P0_post, VLDR_P0_pre, VMSR_P0, VSTR_P0_off, VSTR_P0_... |
10244 | 0 | SStream_concat0(O, "\tp0, "); |
10245 | 0 | break; |
10246 | 0 | case 62: |
10247 | | // VLDR_VPR_off, VLDR_VPR_post, VLDR_VPR_pre, VMSR_VPR, VSTR_VPR_off, VST... |
10248 | 0 | SStream_concat0(O, "\tvpr, "); |
10249 | 0 | break; |
10250 | 35 | case 63: |
10251 | | // VMSR_FPEXC |
10252 | 35 | SStream_concat0(O, "\tfpexc, "); |
10253 | 35 | printOperand(MI, 0, O); |
10254 | 35 | return; |
10255 | 0 | break; |
10256 | 221 | case 64: |
10257 | | // VMSR_FPINST |
10258 | 221 | SStream_concat0(O, "\tfpinst, "); |
10259 | 221 | printOperand(MI, 0, O); |
10260 | 221 | return; |
10261 | 0 | break; |
10262 | 35 | case 65: |
10263 | | // VMSR_FPINST2 |
10264 | 35 | SStream_concat0(O, "\tfpinst2, "); |
10265 | 35 | printOperand(MI, 0, O); |
10266 | 35 | return; |
10267 | 0 | break; |
10268 | 39 | case 66: |
10269 | | // VMSR_FPSID |
10270 | 39 | SStream_concat0(O, "\tfpsid, "); |
10271 | 39 | printOperand(MI, 0, O); |
10272 | 39 | return; |
10273 | 0 | break; |
10274 | 406 | case 67: |
10275 | | // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... |
10276 | 406 | SStream_concat0(O, ".s64\t"); |
10277 | 406 | ARM_add_vector_data(MI, ARM_VECTORDATA_S64); |
10278 | 406 | printOperand(MI, 0, O); |
10279 | 406 | SStream_concat0(O, ", "); |
10280 | 406 | break; |
10281 | 75 | case 68: |
10282 | | // VSHTOD |
10283 | 75 | SStream_concat0(O, ".f64.s16\t"); |
10284 | 75 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64S16); |
10285 | 75 | printOperand(MI, 0, O); |
10286 | 75 | SStream_concat0(O, ", "); |
10287 | 75 | printOperand(MI, 1, O); |
10288 | 75 | SStream_concat0(O, ", "); |
10289 | 75 | printFBits16(MI, 2, O); |
10290 | 75 | return; |
10291 | 0 | break; |
10292 | 70 | case 69: |
10293 | | // VSHTOS |
10294 | 70 | SStream_concat0(O, ".f32.s16\t"); |
10295 | 70 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32S16); |
10296 | 70 | printOperand(MI, 0, O); |
10297 | 70 | SStream_concat0(O, ", "); |
10298 | 70 | printOperand(MI, 1, O); |
10299 | 70 | SStream_concat0(O, ", "); |
10300 | 70 | printFBits16(MI, 2, O); |
10301 | 70 | return; |
10302 | 0 | break; |
10303 | 200 | case 70: |
10304 | | // VSITOD, VSLTOD |
10305 | 200 | SStream_concat0(O, ".f64.s32\t"); |
10306 | 200 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64S32); |
10307 | 200 | printOperand(MI, 0, O); |
10308 | 200 | SStream_concat0(O, ", "); |
10309 | 200 | printOperand(MI, 1, O); |
10310 | 200 | break; |
10311 | 49 | case 71: |
10312 | | // VSITOH, VSLTOH |
10313 | 49 | SStream_concat0(O, ".f16.s32\t"); |
10314 | 49 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16S32); |
10315 | 49 | printOperand(MI, 0, O); |
10316 | 49 | SStream_concat0(O, ", "); |
10317 | 49 | printOperand(MI, 1, O); |
10318 | 49 | break; |
10319 | 46 | case 72: |
10320 | | // VTOSHD |
10321 | 46 | SStream_concat0(O, ".s16.f64\t"); |
10322 | 46 | ARM_add_vector_data(MI, ARM_VECTORDATA_S16F64); |
10323 | 46 | printOperand(MI, 0, O); |
10324 | 46 | SStream_concat0(O, ", "); |
10325 | 46 | printOperand(MI, 1, O); |
10326 | 46 | SStream_concat0(O, ", "); |
10327 | 46 | printFBits16(MI, 2, O); |
10328 | 46 | return; |
10329 | 0 | break; |
10330 | 91 | case 73: |
10331 | | // VTOSHS |
10332 | 91 | SStream_concat0(O, ".s16.f32\t"); |
10333 | 91 | ARM_add_vector_data(MI, ARM_VECTORDATA_S16F32); |
10334 | 91 | printOperand(MI, 0, O); |
10335 | 91 | SStream_concat0(O, ", "); |
10336 | 91 | printOperand(MI, 1, O); |
10337 | 91 | SStream_concat0(O, ", "); |
10338 | 91 | printFBits16(MI, 2, O); |
10339 | 91 | return; |
10340 | 0 | break; |
10341 | 80 | case 74: |
10342 | | // VTOSIRH, VTOSIZH, VTOSLH |
10343 | 80 | SStream_concat0(O, ".s32.f16\t"); |
10344 | 80 | ARM_add_vector_data(MI, ARM_VECTORDATA_S32F16); |
10345 | 80 | printOperand(MI, 0, O); |
10346 | 80 | SStream_concat0(O, ", "); |
10347 | 80 | printOperand(MI, 1, O); |
10348 | 80 | break; |
10349 | 24 | case 75: |
10350 | | // VTOUHD |
10351 | 24 | SStream_concat0(O, ".u16.f64\t"); |
10352 | 24 | ARM_add_vector_data(MI, ARM_VECTORDATA_U16F64); |
10353 | 24 | printOperand(MI, 0, O); |
10354 | 24 | SStream_concat0(O, ", "); |
10355 | 24 | printOperand(MI, 1, O); |
10356 | 24 | SStream_concat0(O, ", "); |
10357 | 24 | printFBits16(MI, 2, O); |
10358 | 24 | return; |
10359 | 0 | break; |
10360 | 24 | case 76: |
10361 | | // VTOUHS |
10362 | 24 | SStream_concat0(O, ".u16.f32\t"); |
10363 | 24 | ARM_add_vector_data(MI, ARM_VECTORDATA_U16F32); |
10364 | 24 | printOperand(MI, 0, O); |
10365 | 24 | SStream_concat0(O, ", "); |
10366 | 24 | printOperand(MI, 1, O); |
10367 | 24 | SStream_concat0(O, ", "); |
10368 | 24 | printFBits16(MI, 2, O); |
10369 | 24 | return; |
10370 | 0 | break; |
10371 | 877 | case 77: |
10372 | | // VTOUIRD, VTOUIZD, VTOULD |
10373 | 877 | SStream_concat0(O, ".u32.f64\t"); |
10374 | 877 | ARM_add_vector_data(MI, ARM_VECTORDATA_U32F64); |
10375 | 877 | printOperand(MI, 0, O); |
10376 | 877 | SStream_concat0(O, ", "); |
10377 | 877 | printOperand(MI, 1, O); |
10378 | 877 | break; |
10379 | 170 | case 78: |
10380 | | // VTOUIRH, VTOUIZH, VTOULH |
10381 | 170 | SStream_concat0(O, ".u32.f16\t"); |
10382 | 170 | ARM_add_vector_data(MI, ARM_VECTORDATA_U32F16); |
10383 | 170 | printOperand(MI, 0, O); |
10384 | 170 | SStream_concat0(O, ", "); |
10385 | 170 | printOperand(MI, 1, O); |
10386 | 170 | break; |
10387 | 68 | case 79: |
10388 | | // VUHTOD |
10389 | 68 | SStream_concat0(O, ".f64.u16\t"); |
10390 | 68 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64U16); |
10391 | 68 | printOperand(MI, 0, O); |
10392 | 68 | SStream_concat0(O, ", "); |
10393 | 68 | printOperand(MI, 1, O); |
10394 | 68 | SStream_concat0(O, ", "); |
10395 | 68 | printFBits16(MI, 2, O); |
10396 | 68 | return; |
10397 | 0 | break; |
10398 | 286 | case 80: |
10399 | | // VUHTOS |
10400 | 286 | SStream_concat0(O, ".f32.u16\t"); |
10401 | 286 | ARM_add_vector_data(MI, ARM_VECTORDATA_F32U16); |
10402 | 286 | printOperand(MI, 0, O); |
10403 | 286 | SStream_concat0(O, ", "); |
10404 | 286 | printOperand(MI, 1, O); |
10405 | 286 | SStream_concat0(O, ", "); |
10406 | 286 | printFBits16(MI, 2, O); |
10407 | 286 | return; |
10408 | 0 | break; |
10409 | 38 | case 81: |
10410 | | // VUITOD, VULTOD |
10411 | 38 | SStream_concat0(O, ".f64.u32\t"); |
10412 | 38 | ARM_add_vector_data(MI, ARM_VECTORDATA_F64U32); |
10413 | 38 | printOperand(MI, 0, O); |
10414 | 38 | SStream_concat0(O, ", "); |
10415 | 38 | printOperand(MI, 1, O); |
10416 | 38 | break; |
10417 | 26 | case 82: |
10418 | | // VUITOH, VULTOH |
10419 | 26 | SStream_concat0(O, ".f16.u32\t"); |
10420 | 26 | ARM_add_vector_data(MI, ARM_VECTORDATA_F16U32); |
10421 | 26 | printOperand(MI, 0, O); |
10422 | 26 | SStream_concat0(O, ", "); |
10423 | 26 | printOperand(MI, 1, O); |
10424 | 26 | break; |
10425 | 25.8k | case 83: |
10426 | | // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADDspImm, t2ADR, t2ANDr... |
10427 | 25.8k | SStream_concat0(O, ".w\t"); |
10428 | 25.8k | break; |
10429 | 78 | case 84: |
10430 | | // t2SRSDB, t2SRSIA |
10431 | 78 | SStream_concat0(O, "\tsp, "); |
10432 | 78 | printOperand(MI, 0, O); |
10433 | 78 | return; |
10434 | 0 | break; |
10435 | 84 | case 85: |
10436 | | // t2SRSDB_UPD, t2SRSIA_UPD |
10437 | 84 | SStream_concat0(O, "\tsp!, "); |
10438 | 84 | printOperand(MI, 0, O); |
10439 | 84 | return; |
10440 | 0 | break; |
10441 | 34 | case 86: |
10442 | | // t2SUBS_PC_LR |
10443 | 34 | SStream_concat0(O, "\tpc, lr, "); |
10444 | 34 | printOperand(MI, 0, O); |
10445 | 34 | return; |
10446 | 0 | break; |
10447 | 304k | case 87: |
10448 | | // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... |
10449 | 304k | printPredicateOperand(MI, 4, O); |
10450 | 304k | SStream_concat0(O, "\t"); |
10451 | 304k | printOperand(MI, 0, O); |
10452 | 304k | SStream_concat0(O, ", "); |
10453 | 304k | break; |
10454 | 45.3k | case 88: |
10455 | | // tMOVi8, tMVN, tRSB |
10456 | 45.3k | printPredicateOperand(MI, 3, O); |
10457 | 45.3k | SStream_concat0(O, "\t"); |
10458 | 45.3k | printOperand(MI, 0, O); |
10459 | 45.3k | SStream_concat0(O, ", "); |
10460 | 45.3k | printOperand(MI, 2, O); |
10461 | 45.3k | break; |
10462 | 1.44M | } |
10463 | | |
10464 | | // Fragment 2 encoded into 7 bits for 69 unique commands. |
10465 | 1.43M | switch ((uint32_t)((Bits >> 26) & 127)) { |
10466 | 0 | default: |
10467 | 0 | assert(0 && "Invalid command number."); |
10468 | 623k | case 0: |
10469 | | // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... |
10470 | 623k | printOperand(MI, 0, O); |
10471 | 623k | break; |
10472 | 18.3k | case 1: |
10473 | | // ITasm, t2IT |
10474 | 18.3k | printMandatoryPredicateOperand(MI, 0, O); |
10475 | 18.3k | return; |
10476 | 0 | break; |
10477 | 0 | case 2: |
10478 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... |
10479 | 0 | printVectorListThreeAllLanes(MI, 0, O); |
10480 | 0 | SStream_concat0(O, ", "); |
10481 | 0 | printAddrMode6Operand(MI, 1, O); |
10482 | 0 | break; |
10483 | 0 | case 3: |
10484 | | // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... |
10485 | 0 | printVectorListThreeSpacedAllLanes(MI, 0, O); |
10486 | 0 | SStream_concat0(O, ", "); |
10487 | 0 | printAddrMode6Operand(MI, 1, O); |
10488 | 0 | break; |
10489 | 1.39k | case 4: |
10490 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... |
10491 | 1.39k | printVectorListThree(MI, 0, O); |
10492 | 1.39k | SStream_concat0(O, ", "); |
10493 | 1.39k | break; |
10494 | 0 | case 5: |
10495 | | // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... |
10496 | 0 | printVectorListThreeSpaced(MI, 0, O); |
10497 | 0 | SStream_concat0(O, ", "); |
10498 | 0 | printAddrMode6Operand(MI, 1, O); |
10499 | 0 | break; |
10500 | 0 | case 6: |
10501 | | // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... |
10502 | 0 | printVectorListFourAllLanes(MI, 0, O); |
10503 | 0 | SStream_concat0(O, ", "); |
10504 | 0 | printAddrMode6Operand(MI, 1, O); |
10505 | 0 | break; |
10506 | 0 | case 7: |
10507 | | // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... |
10508 | 0 | printVectorListFourSpacedAllLanes(MI, 0, O); |
10509 | 0 | SStream_concat0(O, ", "); |
10510 | 0 | printAddrMode6Operand(MI, 1, O); |
10511 | 0 | break; |
10512 | 2.39k | case 8: |
10513 | | // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... |
10514 | 2.39k | printVectorListFour(MI, 0, O); |
10515 | 2.39k | SStream_concat0(O, ", "); |
10516 | 2.39k | break; |
10517 | 0 | case 9: |
10518 | | // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... |
10519 | 0 | printVectorListFourSpaced(MI, 0, O); |
10520 | 0 | SStream_concat0(O, ", "); |
10521 | 0 | printAddrMode6Operand(MI, 1, O); |
10522 | 0 | break; |
10523 | 465 | case 10: |
10524 | | // t2LDR_POST_imm, t2STR_POST_imm, VLDR_FPCXTNS_post, VLDR_FPCXTS_post, V... |
10525 | 465 | printAddrMode7Operand(MI, 1, O); |
10526 | 465 | break; |
10527 | 0 | case 11: |
10528 | | // t2LDR_PRE_imm, t2STR_PRE_imm |
10529 | 0 | printT2AddrModeImm8Operand_1(MI, 1, O); |
10530 | 0 | SStream_concat1(O, '!'); |
10531 | 0 | return; |
10532 | 0 | break; |
10533 | 215k | case 12: |
10534 | | // AESD, AESE, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDO... |
10535 | 215k | printOperand(MI, 2, O); |
10536 | 215k | break; |
10537 | 202k | case 13: |
10538 | | // AESIMC, AESMC, BF16_VCVT, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, C... |
10539 | 202k | printOperand(MI, 1, O); |
10540 | 202k | break; |
10541 | 53.6k | case 14: |
10542 | | // BL_pred, Bcc, t2B, t2BFLi, t2BFLr, t2BFi, t2BFr, t2Bcc, tB, tBcc |
10543 | 53.6k | printOperandAddr(MI, Address, 0, O); |
10544 | 53.6k | break; |
10545 | 18.3k | case 15: |
10546 | | // CDE_CX1A, CDE_CX1DA, CDE_CX2A, CDE_CX2DA, CDE_CX3A, CDE_CX3DA, CDE_VCX... |
10547 | 18.3k | printPImmediate(MI, 1, O); |
10548 | 18.3k | SStream_concat0(O, ", "); |
10549 | 18.3k | break; |
10550 | 45.4k | case 16: |
10551 | | // CDE_CX1D, MVE_LCTP, MVE_VCVTf16s16n, MVE_VCVTf16u16n, MVE_VCVTf32s32n,... |
10552 | 45.4k | return; |
10553 | 0 | break; |
10554 | 6.30k | case 17: |
10555 | | // CDE_CX2D, CDE_CX3D, FCONSTD, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, M... |
10556 | 6.30k | SStream_concat0(O, ", "); |
10557 | 6.30k | break; |
10558 | 97.0k | case 18: |
10559 | | // CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VC... |
10560 | 97.0k | printOperand(MI, 3, O); |
10561 | 97.0k | break; |
10562 | 53.5k | case 19: |
10563 | | // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_... |
10564 | 53.5k | printPImmediate(MI, 0, O); |
10565 | 53.5k | SStream_concat0(O, ", "); |
10566 | 53.5k | break; |
10567 | 1.39k | case 20: |
10568 | | // CDP2 |
10569 | 1.39k | printCImmediate(MI, 2, O); |
10570 | 1.39k | SStream_concat0(O, ", "); |
10571 | 1.39k | printCImmediate(MI, 3, O); |
10572 | 1.39k | SStream_concat0(O, ", "); |
10573 | 1.39k | printCImmediate(MI, 4, O); |
10574 | 1.39k | SStream_concat0(O, ", "); |
10575 | 1.39k | printOperand(MI, 5, O); |
10576 | 1.39k | return; |
10577 | 0 | break; |
10578 | 1.59k | case 21: |
10579 | | // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS |
10580 | 1.59k | printCPSIFlag(MI, 1, O); |
10581 | 1.59k | break; |
10582 | 301 | case 22: |
10583 | | // LDAEXD, LDREXD |
10584 | 301 | printGPRPairOperand(MI, 0, O); |
10585 | 301 | SStream_concat0(O, ", "); |
10586 | 301 | printAddrMode7Operand(MI, 1, O); |
10587 | 301 | return; |
10588 | 0 | break; |
10589 | 1.14k | case 23: |
10590 | | // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET |
10591 | 1.14k | printAddrMode5Operand_0(MI, 2, O); |
10592 | 1.14k | return; |
10593 | 0 | break; |
10594 | 1.80k | case 24: |
10595 | | // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... |
10596 | 1.80k | printAddrMode7Operand(MI, 2, O); |
10597 | 1.80k | break; |
10598 | 894 | case 25: |
10599 | | // MRRC, t2MRRC, t2MRRC2 |
10600 | 894 | printPImmediate(MI, 2, O); |
10601 | 894 | SStream_concat0(O, ", "); |
10602 | 894 | printOperand(MI, 3, O); |
10603 | 894 | SStream_concat0(O, ", "); |
10604 | 894 | printOperand(MI, 0, O); |
10605 | 894 | SStream_concat0(O, ", "); |
10606 | 894 | printOperand(MI, 1, O); |
10607 | 894 | SStream_concat0(O, ", "); |
10608 | 894 | printCImmediate(MI, 4, O); |
10609 | 894 | return; |
10610 | 0 | break; |
10611 | 11.4k | case 26: |
10612 | | // MSR, MSRi, t2MSR_AR, t2MSR_M |
10613 | 11.4k | printMSRMaskOperand(MI, 0, O); |
10614 | 11.4k | SStream_concat0(O, ", "); |
10615 | 11.4k | break; |
10616 | 162 | case 27: |
10617 | | // MSRbanked, t2MSRbanked |
10618 | 162 | printBankedRegOperand(MI, 0, O); |
10619 | 162 | SStream_concat0(O, ", "); |
10620 | 162 | printOperand(MI, 1, O); |
10621 | 162 | return; |
10622 | 0 | break; |
10623 | 4.49k | case 28: |
10624 | | // MVE_LETP, t2LEUpdate, tBL, tBLXi |
10625 | 4.49k | printOperandAddr(MI, Address, 2, O); |
10626 | 4.49k | return; |
10627 | 0 | break; |
10628 | 12.6k | case 29: |
10629 | | // MVE_VCMPf16, MVE_VCMPf16r, MVE_VCMPf32, MVE_VCMPf32r, MVE_VCMPi16, MVE... |
10630 | 12.6k | printMandatoryRestrictedPredicateOperand(MI, 3, O); |
10631 | 12.6k | SStream_concat0(O, ", "); |
10632 | 12.6k | printOperand(MI, 1, O); |
10633 | 12.6k | SStream_concat0(O, ", "); |
10634 | 12.6k | printOperand(MI, 2, O); |
10635 | 12.6k | return; |
10636 | 0 | break; |
10637 | 839 | case 30: |
10638 | | // MVE_VMOVimmi64, VMOVv1i64, VMOVv2i64 |
10639 | 839 | printVMOVModImmOperand(MI, 1, O); |
10640 | 839 | return; |
10641 | 0 | break; |
10642 | 1.25k | case 31: |
10643 | | // VCMPEZD, VCMPZD, tRSB |
10644 | 1.25k | SStream_concat0(O, ", #0"); |
10645 | 1.25k | return; |
10646 | 0 | break; |
10647 | 344 | case 32: |
10648 | | // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... |
10649 | 344 | printVectorListOneAllLanes(MI, 0, O); |
10650 | 344 | SStream_concat0(O, ", "); |
10651 | 344 | break; |
10652 | 1.01k | case 33: |
10653 | | // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... |
10654 | 1.01k | printVectorListTwoAllLanes(MI, 0, O); |
10655 | 1.01k | SStream_concat0(O, ", "); |
10656 | 1.01k | break; |
10657 | 714 | case 34: |
10658 | | // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... |
10659 | 714 | printVectorListOne(MI, 0, O); |
10660 | 714 | SStream_concat0(O, ", "); |
10661 | 714 | break; |
10662 | 3.62k | case 35: |
10663 | | // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... |
10664 | 3.62k | printVectorListTwo(MI, 0, O); |
10665 | 3.62k | SStream_concat0(O, ", "); |
10666 | 3.62k | break; |
10667 | 1.78k | case 36: |
10668 | | // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... |
10669 | 1.78k | printVectorListTwoSpacedAllLanes(MI, 0, O); |
10670 | 1.78k | SStream_concat0(O, ", "); |
10671 | 1.78k | break; |
10672 | 2.47k | case 37: |
10673 | | // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... |
10674 | 2.47k | printVectorListTwoSpaced(MI, 0, O); |
10675 | 2.47k | SStream_concat0(O, ", "); |
10676 | 2.47k | break; |
10677 | 602 | case 38: |
10678 | | // VLDR_FPCXTNS_off, VLDR_FPCXTS_off, VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_o... |
10679 | 602 | printT2AddrModeImm8s4Operand_0(MI, 0, O); |
10680 | 602 | return; |
10681 | 0 | break; |
10682 | 1.14k | case 39: |
10683 | | // VLDR_FPCXTNS_pre, VLDR_FPCXTS_pre, VLDR_FPSCR_NZCVQC_pre, VLDR_FPSCR_p... |
10684 | 1.14k | printT2AddrModeImm8s4Operand_1(MI, 1, O); |
10685 | 1.14k | SStream_concat1(O, '!'); |
10686 | 1.14k | return; |
10687 | 0 | break; |
10688 | 0 | case 40: |
10689 | | // VLDR_P0_off, VSTR_P0_off |
10690 | 0 | printT2AddrModeImm8s4Operand_0(MI, 1, O); |
10691 | 0 | return; |
10692 | 0 | break; |
10693 | 0 | case 41: |
10694 | | // VLDR_P0_pre, VSTR_P0_pre |
10695 | 0 | printT2AddrModeImm8s4Operand_1(MI, 2, O); |
10696 | 0 | SStream_concat1(O, '!'); |
10697 | 0 | return; |
10698 | 0 | break; |
10699 | 11.9k | case 42: |
10700 | | // VSCCLRMD, VSCCLRMS, t2CLRM, tPOP, tPUSH |
10701 | 11.9k | printRegisterList(MI, 2, O); |
10702 | 11.9k | return; |
10703 | 0 | break; |
10704 | 7.53k | case 43: |
10705 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... |
10706 | 7.53k | printOperand(MI, 4, O); |
10707 | 7.53k | break; |
10708 | 57 | case 44: |
10709 | | // VST1d16, VST1d32, VST1d64, VST1d8 |
10710 | 57 | printVectorListOne(MI, 2, O); |
10711 | 57 | SStream_concat0(O, ", "); |
10712 | 57 | printAddrMode6Operand(MI, 0, O); |
10713 | 57 | return; |
10714 | 0 | break; |
10715 | 218 | case 45: |
10716 | | // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 |
10717 | 218 | printVectorListFour(MI, 2, O); |
10718 | 218 | SStream_concat0(O, ", "); |
10719 | 218 | printAddrMode6Operand(MI, 0, O); |
10720 | 218 | return; |
10721 | 0 | break; |
10722 | 663 | case 46: |
10723 | | // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... |
10724 | 663 | printVectorListFour(MI, 3, O); |
10725 | 663 | SStream_concat0(O, ", "); |
10726 | 663 | printAddrMode6Operand(MI, 1, O); |
10727 | 663 | SStream_concat1(O, '!'); |
10728 | 663 | return; |
10729 | 0 | break; |
10730 | 1.36k | case 47: |
10731 | | // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... |
10732 | 1.36k | printVectorListFour(MI, 4, O); |
10733 | 1.36k | SStream_concat0(O, ", "); |
10734 | 1.36k | printAddrMode6Operand(MI, 1, O); |
10735 | 1.36k | SStream_concat0(O, ", "); |
10736 | 1.36k | printOperand(MI, 3, O); |
10737 | 1.36k | return; |
10738 | 0 | break; |
10739 | 239 | case 48: |
10740 | | // VST1d16T, VST1d32T, VST1d64T, VST1d8T |
10741 | 239 | printVectorListThree(MI, 2, O); |
10742 | 239 | SStream_concat0(O, ", "); |
10743 | 239 | printAddrMode6Operand(MI, 0, O); |
10744 | 239 | return; |
10745 | 0 | break; |
10746 | 1.04k | case 49: |
10747 | | // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed |
10748 | 1.04k | printVectorListThree(MI, 3, O); |
10749 | 1.04k | SStream_concat0(O, ", "); |
10750 | 1.04k | printAddrMode6Operand(MI, 1, O); |
10751 | 1.04k | SStream_concat1(O, '!'); |
10752 | 1.04k | return; |
10753 | 0 | break; |
10754 | 291 | case 50: |
10755 | | // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... |
10756 | 291 | printVectorListThree(MI, 4, O); |
10757 | 291 | SStream_concat0(O, ", "); |
10758 | 291 | printAddrMode6Operand(MI, 1, O); |
10759 | 291 | SStream_concat0(O, ", "); |
10760 | 291 | printOperand(MI, 3, O); |
10761 | 291 | return; |
10762 | 0 | break; |
10763 | 545 | case 51: |
10764 | | // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed |
10765 | 545 | printVectorListOne(MI, 3, O); |
10766 | 545 | SStream_concat0(O, ", "); |
10767 | 545 | printAddrMode6Operand(MI, 1, O); |
10768 | 545 | SStream_concat1(O, '!'); |
10769 | 545 | return; |
10770 | 0 | break; |
10771 | 556 | case 52: |
10772 | | // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... |
10773 | 556 | printVectorListOne(MI, 4, O); |
10774 | 556 | SStream_concat0(O, ", "); |
10775 | 556 | printAddrMode6Operand(MI, 1, O); |
10776 | 556 | SStream_concat0(O, ", "); |
10777 | 556 | printOperand(MI, 3, O); |
10778 | 556 | return; |
10779 | 0 | break; |
10780 | 629 | case 53: |
10781 | | // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 |
10782 | 629 | printVectorListTwo(MI, 2, O); |
10783 | 629 | SStream_concat0(O, ", "); |
10784 | 629 | printAddrMode6Operand(MI, 0, O); |
10785 | 629 | return; |
10786 | 0 | break; |
10787 | 1.04k | case 54: |
10788 | | // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... |
10789 | 1.04k | printVectorListTwo(MI, 3, O); |
10790 | 1.04k | SStream_concat0(O, ", "); |
10791 | 1.04k | printAddrMode6Operand(MI, 1, O); |
10792 | 1.04k | SStream_concat1(O, '!'); |
10793 | 1.04k | return; |
10794 | 0 | break; |
10795 | 946 | case 55: |
10796 | | // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... |
10797 | 946 | printVectorListTwo(MI, 4, O); |
10798 | 946 | SStream_concat0(O, ", "); |
10799 | 946 | printAddrMode6Operand(MI, 1, O); |
10800 | 946 | SStream_concat0(O, ", "); |
10801 | 946 | printOperand(MI, 3, O); |
10802 | 946 | return; |
10803 | 0 | break; |
10804 | 562 | case 56: |
10805 | | // VST2b16, VST2b32, VST2b8 |
10806 | 562 | printVectorListTwoSpaced(MI, 2, O); |
10807 | 562 | SStream_concat0(O, ", "); |
10808 | 562 | printAddrMode6Operand(MI, 0, O); |
10809 | 562 | return; |
10810 | 0 | break; |
10811 | 411 | case 57: |
10812 | | // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed |
10813 | 411 | printVectorListTwoSpaced(MI, 3, O); |
10814 | 411 | SStream_concat0(O, ", "); |
10815 | 411 | printAddrMode6Operand(MI, 1, O); |
10816 | 411 | SStream_concat1(O, '!'); |
10817 | 411 | return; |
10818 | 0 | break; |
10819 | 685 | case 58: |
10820 | | // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register |
10821 | 685 | printVectorListTwoSpaced(MI, 4, O); |
10822 | 685 | SStream_concat0(O, ", "); |
10823 | 685 | printAddrMode6Operand(MI, 1, O); |
10824 | 685 | SStream_concat0(O, ", "); |
10825 | 685 | printOperand(MI, 3, O); |
10826 | 685 | return; |
10827 | 0 | break; |
10828 | 9.53k | case 59: |
10829 | | // t2BFic, tCBNZ, tCBZ |
10830 | 9.53k | printOperandAddr(MI, Address, 1, O); |
10831 | 9.53k | break; |
10832 | 1.58k | case 60: |
10833 | | // t2DMB, t2DSB |
10834 | 1.58k | printMemBOption(MI, 0, O); |
10835 | 1.58k | return; |
10836 | 0 | break; |
10837 | 93 | case 61: |
10838 | | // t2ISB |
10839 | 93 | printInstSyncBOption(MI, 0, O); |
10840 | 93 | return; |
10841 | 0 | break; |
10842 | 887 | case 62: |
10843 | | // t2PLDWi12, t2PLDi12, t2PLIi12 |
10844 | 887 | printAddrModeImm12Operand_0(MI, 0, O); |
10845 | 887 | return; |
10846 | 0 | break; |
10847 | 161 | case 63: |
10848 | | // t2PLDWi8, t2PLDi8, t2PLIi8 |
10849 | 161 | printT2AddrModeImm8Operand_0(MI, 0, O); |
10850 | 161 | return; |
10851 | 0 | break; |
10852 | 391 | case 64: |
10853 | | // t2PLDWs, t2PLDs, t2PLIs |
10854 | 391 | printT2AddrModeSoRegOperand(MI, 0, O); |
10855 | 391 | return; |
10856 | 0 | break; |
10857 | 1.38k | case 65: |
10858 | | // t2PLDpci, t2PLIpci |
10859 | 1.38k | printThumbLdrLabelOperand(MI, 0, O); |
10860 | 1.38k | return; |
10861 | 0 | break; |
10862 | 77 | case 66: |
10863 | | // t2TBB |
10864 | 77 | printAddrModeTBB(MI, 0, O); |
10865 | 77 | return; |
10866 | 0 | break; |
10867 | 446 | case 67: |
10868 | | // t2TBH |
10869 | 446 | printAddrModeTBH(MI, 0, O); |
10870 | 446 | return; |
10871 | 0 | break; |
10872 | 0 | case 68: |
10873 | | // t2TSB |
10874 | 0 | printTraceSyncBOption(MI, 0, O); |
10875 | 0 | return; |
10876 | 0 | break; |
10877 | 1.43M | } |
10878 | | |
10879 | | // Fragment 3 encoded into 6 bits for 39 unique commands. |
10880 | 1.31M | switch ((uint32_t)((Bits >> 33) & 63)) { |
10881 | 0 | default: |
10882 | 0 | assert(0 && "Invalid command number."); |
10883 | 846k | case 0: |
10884 | | // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... |
10885 | 846k | SStream_concat0(O, ", "); |
10886 | 846k | break; |
10887 | 322k | case 1: |
10888 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... |
10889 | 322k | return; |
10890 | 0 | break; |
10891 | 20 | case 2: |
10892 | | // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... |
10893 | 20 | SStream_concat1(O, '!'); |
10894 | 20 | return; |
10895 | 0 | break; |
10896 | 2.22k | case 3: |
10897 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... |
10898 | 2.22k | printAddrMode6Operand(MI, 1, O); |
10899 | 2.22k | break; |
10900 | 0 | case 4: |
10901 | | // CDE_CX1A, CDE_CX2A, CDE_CX3A, CDE_VCX1A_vec, CDE_VCX1_vec, CDE_VCX2A_v... |
10902 | 0 | printOperand(MI, 0, O); |
10903 | 0 | SStream_concat0(O, ", "); |
10904 | 0 | break; |
10905 | 0 | case 5: |
10906 | | // CDE_CX1DA, CDE_CX2DA, CDE_CX3DA |
10907 | 0 | printGPRPairOperand(MI, 0, O); |
10908 | 0 | SStream_concat0(O, ", "); |
10909 | 0 | printOperand(MI, 3, O); |
10910 | 0 | break; |
10911 | 0 | case 6: |
10912 | | // CDE_CX2D, CDE_CX3D |
10913 | 0 | printOperand(MI, 3, O); |
10914 | 0 | break; |
10915 | 41.3k | case 7: |
10916 | | // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,... |
10917 | 41.3k | printOperand(MI, 1, O); |
10918 | 41.3k | break; |
10919 | 242 | case 8: |
10920 | | // FCONSTD |
10921 | 242 | printFPImmOperand(MI, 1, O); |
10922 | 242 | return; |
10923 | 0 | break; |
10924 | 23.4k | case 9: |
10925 | | // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... |
10926 | 23.4k | SStream_concat0(O, "!, "); |
10927 | 23.4k | printRegisterList(MI, 4, O); |
10928 | 23.4k | break; |
10929 | 22.8k | case 10: |
10930 | | // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_POST,... |
10931 | 22.8k | printCImmediate(MI, 1, O); |
10932 | 22.8k | SStream_concat0(O, ", "); |
10933 | 22.8k | break; |
10934 | 12.1k | case 11: |
10935 | | // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... |
10936 | 12.1k | printCImmediate(MI, 2, O); |
10937 | 12.1k | SStream_concat0(O, ", "); |
10938 | 12.1k | printAddrMode5Operand_1(MI, 3, O); |
10939 | 12.1k | SStream_concat1(O, '!'); |
10940 | 12.1k | return; |
10941 | 0 | break; |
10942 | 10.6k | case 12: |
10943 | | // MRC, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, MVE_VCVTf32s32_fix, MVE_V... |
10944 | 10.6k | printOperand(MI, 2, O); |
10945 | 10.6k | break; |
10946 | 418 | case 13: |
10947 | | // MRS, t2MRS_AR |
10948 | 418 | SStream_concat0(O, ", apsr"); |
10949 | 418 | return; |
10950 | 0 | break; |
10951 | 99 | case 14: |
10952 | | // MRSsys, t2MRSsys_AR |
10953 | 99 | SStream_concat0(O, ", spsr"); |
10954 | 99 | return; |
10955 | 0 | break; |
10956 | 1.07k | case 15: |
10957 | | // MSRi |
10958 | 1.07k | printModImmOperand(MI, 1, O); |
10959 | 1.07k | return; |
10960 | 0 | break; |
10961 | 0 | case 16: |
10962 | | // MVE_VMOV_q_rr |
10963 | 0 | printVectorIndex(MI, 4, O); |
10964 | 0 | SStream_concat0(O, ", "); |
10965 | 0 | printOperand(MI, 1, O); |
10966 | 0 | printVectorIndex(MI, 5, O); |
10967 | 0 | SStream_concat0(O, ", "); |
10968 | 0 | printOperand(MI, 2, O); |
10969 | 0 | SStream_concat0(O, ", "); |
10970 | 0 | printOperand(MI, 3, O); |
10971 | 0 | return; |
10972 | 0 | break; |
10973 | 709 | case 17: |
10974 | | // MVE_VMOV_to_lane_16, MVE_VMOV_to_lane_32, MVE_VMOV_to_lane_8, VSETLNi1... |
10975 | 709 | printVectorIndex(MI, 3, O); |
10976 | 709 | SStream_concat0(O, ", "); |
10977 | 709 | printOperand(MI, 2, O); |
10978 | 709 | return; |
10979 | 0 | break; |
10980 | 831 | case 18: |
10981 | | // VCMPEZH, VCMPEZS, VCMPZH, VCMPZS |
10982 | 831 | SStream_concat0(O, ", #0"); |
10983 | 831 | return; |
10984 | 0 | break; |
10985 | 11.5k | case 19: |
10986 | | // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... |
10987 | 11.5k | printAddrMode6Operand(MI, 2, O); |
10988 | 11.5k | break; |
10989 | 14.8k | case 20: |
10990 | | // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... |
10991 | 14.8k | SStream_concat1(O, '['); |
10992 | 14.8k | break; |
10993 | 1.91k | case 21: |
10994 | | // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... |
10995 | 1.91k | SStream_concat0(O, "[], "); |
10996 | 1.91k | printOperand(MI, 1, O); |
10997 | 1.91k | SStream_concat0(O, "[], "); |
10998 | 1.91k | printOperand(MI, 2, O); |
10999 | 1.91k | break; |
11000 | 465 | case 22: |
11001 | | // VLDR_FPCXTNS_post, VLDR_FPCXTS_post, VLDR_FPSCR_NZCVQC_post, VLDR_FPSC... |
11002 | 465 | printT2AddrModeImm8s4OffsetOperand(MI, 2, O); |
11003 | 465 | return; |
11004 | 0 | break; |
11005 | 0 | case 23: |
11006 | | // VLDR_P0_post, VSTR_P0_post |
11007 | 0 | printT2AddrModeImm8s4OffsetOperand(MI, 3, O); |
11008 | 0 | return; |
11009 | 0 | break; |
11010 | 43 | case 24: |
11011 | | // VMRS |
11012 | 43 | SStream_concat0(O, ", fpscr"); |
11013 | 43 | return; |
11014 | 0 | break; |
11015 | 47 | case 25: |
11016 | | // VMRS_FPCXTNS |
11017 | 47 | SStream_concat0(O, ", fpcxtns"); |
11018 | 47 | return; |
11019 | 0 | break; |
11020 | 19 | case 26: |
11021 | | // VMRS_FPCXTS |
11022 | 19 | SStream_concat0(O, ", fpcxts"); |
11023 | 19 | return; |
11024 | 0 | break; |
11025 | 116 | case 27: |
11026 | | // VMRS_FPEXC |
11027 | 116 | SStream_concat0(O, ", fpexc"); |
11028 | 116 | return; |
11029 | 0 | break; |
11030 | 346 | case 28: |
11031 | | // VMRS_FPINST |
11032 | 346 | SStream_concat0(O, ", fpinst"); |
11033 | 346 | return; |
11034 | 0 | break; |
11035 | 62 | case 29: |
11036 | | // VMRS_FPINST2 |
11037 | 62 | SStream_concat0(O, ", fpinst2"); |
11038 | 62 | return; |
11039 | 0 | break; |
11040 | 100 | case 30: |
11041 | | // VMRS_FPSCR_NZCVQC |
11042 | 100 | SStream_concat0(O, ", fpscr_nzcvqc"); |
11043 | 100 | return; |
11044 | 0 | break; |
11045 | 57 | case 31: |
11046 | | // VMRS_FPSID |
11047 | 57 | SStream_concat0(O, ", fpsid"); |
11048 | 57 | return; |
11049 | 0 | break; |
11050 | 188 | case 32: |
11051 | | // VMRS_MVFR0 |
11052 | 188 | SStream_concat0(O, ", mvfr0"); |
11053 | 188 | return; |
11054 | 0 | break; |
11055 | 3 | case 33: |
11056 | | // VMRS_MVFR1 |
11057 | 3 | SStream_concat0(O, ", mvfr1"); |
11058 | 3 | return; |
11059 | 0 | break; |
11060 | 10 | case 34: |
11061 | | // VMRS_MVFR2 |
11062 | 10 | SStream_concat0(O, ", mvfr2"); |
11063 | 10 | return; |
11064 | 0 | break; |
11065 | 0 | case 35: |
11066 | | // VMRS_P0 |
11067 | 0 | SStream_concat0(O, ", p0"); |
11068 | 0 | return; |
11069 | 0 | break; |
11070 | 0 | case 36: |
11071 | | // VMRS_VPR |
11072 | 0 | SStream_concat0(O, ", vpr"); |
11073 | 0 | return; |
11074 | 0 | break; |
11075 | 72 | case 37: |
11076 | | // VSHTOH, VTOSHH, VTOUHH, VUHTOH |
11077 | 72 | printFBits16(MI, 2, O); |
11078 | 72 | return; |
11079 | 0 | break; |
11080 | 1.23k | case 38: |
11081 | | // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... |
11082 | 1.23k | printFBits32(MI, 2, O); |
11083 | 1.23k | return; |
11084 | 0 | break; |
11085 | 1.31M | } |
11086 | | |
11087 | | // Fragment 4 encoded into 7 bits for 77 unique commands. |
11088 | 975k | switch ((uint32_t)((Bits >> 39) & 127)) { |
11089 | 0 | default: |
11090 | 0 | assert(0 && "Invalid command number."); |
11091 | 196k | case 0: |
11092 | | // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... |
11093 | 196k | printOperand(MI, 1, O); |
11094 | 196k | break; |
11095 | 84 | case 1: |
11096 | | // LDRBT_POST, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRBT_POST, STRT_P... |
11097 | 84 | printAddrMode7Operand(MI, 1, O); |
11098 | 84 | return; |
11099 | 0 | break; |
11100 | 0 | case 2: |
11101 | | // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... |
11102 | 0 | printAddrMode6Operand(MI, 2, O); |
11103 | 0 | break; |
11104 | 142k | case 3: |
11105 | | // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... |
11106 | 142k | printOperand(MI, 3, O); |
11107 | 142k | break; |
11108 | 37.1k | case 4: |
11109 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... |
11110 | 37.1k | return; |
11111 | 0 | break; |
11112 | 5.66k | case 5: |
11113 | | // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... |
11114 | 5.66k | SStream_concat1(O, '!'); |
11115 | 5.66k | return; |
11116 | 0 | break; |
11117 | 43.8k | case 6: |
11118 | | // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... |
11119 | 43.8k | SStream_concat0(O, ", "); |
11120 | 43.8k | break; |
11121 | 0 | case 7: |
11122 | | // t2LDR_POST_imm, t2STR_POST_imm |
11123 | 0 | printT2AddrModeImm8OffsetOperand(MI, 2, O); |
11124 | 0 | return; |
11125 | 0 | break; |
11126 | 559 | case 8: |
11127 | | // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs |
11128 | 559 | printT2SOOperand(MI, 1, O); |
11129 | 559 | return; |
11130 | 0 | break; |
11131 | 1.55k | case 9: |
11132 | | // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr |
11133 | 1.55k | printSORegRegOperand(MI, 1, O); |
11134 | 1.55k | return; |
11135 | 0 | break; |
11136 | 1.10k | case 10: |
11137 | | // ADR, t2ADR |
11138 | 1.10k | printAdrLabelOperand_0(MI, 1, O); |
11139 | 1.10k | return; |
11140 | 0 | break; |
11141 | 138 | case 11: |
11142 | | // BFC, t2BFC |
11143 | 138 | printBitfieldInvMaskImmOperand(MI, 2, O); |
11144 | 138 | return; |
11145 | 0 | break; |
11146 | 27.7k | case 12: |
11147 | | // BFI, CDE_VCX1_vec, CDE_VCX2_vec, CDE_VCX3_vec, CPS3p, CRC32B, CRC32CB,... |
11148 | 27.7k | printOperand(MI, 2, O); |
11149 | 27.7k | break; |
11150 | 0 | case 13: |
11151 | | // CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VCX3A_fpdp, CDE_VCX3A_fpsp |
11152 | 0 | printOperand(MI, 4, O); |
11153 | 0 | break; |
11154 | 1.63k | case 14: |
11155 | | // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri |
11156 | 1.63k | printModImmOperand(MI, 1, O); |
11157 | 1.63k | return; |
11158 | 0 | break; |
11159 | 1.43k | case 15: |
11160 | | // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi |
11161 | 1.43k | printSORegImmOperand(MI, 1, O); |
11162 | 1.43k | return; |
11163 | 0 | break; |
11164 | 849 | case 16: |
11165 | | // FCONSTH, FCONSTS, MVE_VMOVimmf32, VMOVv2f32, VMOVv4f32 |
11166 | 849 | printFPImmOperand(MI, 1, O); |
11167 | 849 | return; |
11168 | 0 | break; |
11169 | 5.33k | case 17: |
11170 | | // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... |
11171 | 5.33k | printRegisterList(MI, 3, O); |
11172 | 5.33k | break; |
11173 | 437 | case 18: |
11174 | | // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION |
11175 | 437 | printCoprocOptionImm(MI, 3, O); |
11176 | 437 | return; |
11177 | 0 | break; |
11178 | 1.36k | case 19: |
11179 | | // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST |
11180 | 1.36k | printPostIdxImm8s4Operand(MI, 3, O); |
11181 | 1.36k | return; |
11182 | 0 | break; |
11183 | 9.17k | case 20: |
11184 | | // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... |
11185 | 9.17k | printAddrMode5Operand_0(MI, 2, O); |
11186 | 9.17k | return; |
11187 | 0 | break; |
11188 | 32.1k | case 21: |
11189 | | // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... |
11190 | 32.1k | printAddrMode7Operand(MI, 2, O); |
11191 | 32.1k | break; |
11192 | 3.81k | case 22: |
11193 | | // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM |
11194 | 3.81k | printAddrModeImm12Operand_1(MI, 2, O); |
11195 | 3.81k | SStream_concat1(O, '!'); |
11196 | 3.81k | return; |
11197 | 0 | break; |
11198 | 3.79k | case 23: |
11199 | | // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG |
11200 | 3.79k | printAddrMode2Operand(MI, 2, O); |
11201 | 3.79k | SStream_concat1(O, '!'); |
11202 | 3.79k | return; |
11203 | 0 | break; |
11204 | 4.52k | case 24: |
11205 | | // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... |
11206 | 4.52k | printAddrModeImm12Operand_0(MI, 1, O); |
11207 | 4.52k | return; |
11208 | 0 | break; |
11209 | 1.15k | case 25: |
11210 | | // LDRBrs, LDRrs, STRBrs, STRrs |
11211 | 1.15k | printAddrMode2Operand(MI, 1, O); |
11212 | 1.15k | return; |
11213 | 0 | break; |
11214 | 2.02k | case 26: |
11215 | | // LDRH, LDRSB, LDRSH, STRH |
11216 | 2.02k | printAddrMode3Operand_0(MI, 1, O); |
11217 | 2.02k | return; |
11218 | 0 | break; |
11219 | 1.67k | case 27: |
11220 | | // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE |
11221 | 1.67k | printAddrMode3Operand_1(MI, 2, O); |
11222 | 1.67k | SStream_concat1(O, '!'); |
11223 | 1.67k | return; |
11224 | 0 | break; |
11225 | 284 | case 28: |
11226 | | // MCR2 |
11227 | 284 | printCImmediate(MI, 3, O); |
11228 | 284 | SStream_concat0(O, ", "); |
11229 | 284 | printCImmediate(MI, 4, O); |
11230 | 284 | SStream_concat0(O, ", "); |
11231 | 284 | printOperand(MI, 5, O); |
11232 | 284 | return; |
11233 | 0 | break; |
11234 | 82 | case 29: |
11235 | | // MRSbanked, t2MRSbanked |
11236 | 82 | printBankedRegOperand(MI, 1, O); |
11237 | 82 | return; |
11238 | 0 | break; |
11239 | 674 | case 30: |
11240 | | // MVE_VBICimmi16, MVE_VBICimmi32, MVE_VORRimmi16, MVE_VORRimmi32 |
11241 | 674 | printVMOVModImmOperand(MI, 2, O); |
11242 | 674 | return; |
11243 | 0 | break; |
11244 | 7.34k | case 31: |
11245 | | // MVE_VLDRBS16, MVE_VLDRBS32, MVE_VLDRBU16, MVE_VLDRBU32, MVE_VLDRBU8, M... |
11246 | 7.34k | printT2AddrModeImm8Operand_0(MI, 1, O); |
11247 | 7.34k | return; |
11248 | 0 | break; |
11249 | 1.87k | case 32: |
11250 | | // MVE_VLDRBS16_pre, MVE_VLDRBS32_pre, MVE_VLDRBU16_pre, MVE_VLDRBU32_pre... |
11251 | 1.87k | printT2AddrModeImm8Operand_0(MI, 2, O); |
11252 | 1.87k | SStream_concat1(O, '!'); |
11253 | 1.87k | return; |
11254 | 0 | break; |
11255 | 96 | case 33: |
11256 | | // MVE_VLDRBS16_rq, MVE_VLDRBS32_rq, MVE_VLDRBU16_rq, MVE_VLDRBU32_rq, MV... |
11257 | 96 | printMveAddrModeRQOperand_0(MI, 1, O); |
11258 | 96 | return; |
11259 | 0 | break; |
11260 | 3.49k | case 34: |
11261 | | // MVE_VLDRBU8_pre, MVE_VLDRHU16_pre, MVE_VLDRWU32_pre, MVE_VSTRBU8_pre, ... |
11262 | 3.49k | printT2AddrModeImm8Operand_1(MI, 2, O); |
11263 | 3.49k | SStream_concat1(O, '!'); |
11264 | 3.49k | return; |
11265 | 0 | break; |
11266 | 73 | case 35: |
11267 | | // MVE_VLDRDU64_rq, MVE_VSTRD64_rq |
11268 | 73 | printMveAddrModeRQOperand_3(MI, 1, O); |
11269 | 73 | return; |
11270 | 0 | break; |
11271 | 137 | case 36: |
11272 | | // MVE_VLDRHS32_rq, MVE_VLDRHU16_rq, MVE_VLDRHU32_rq, MVE_VSTRH16_rq, MVE... |
11273 | 137 | printMveAddrModeRQOperand_1(MI, 1, O); |
11274 | 137 | return; |
11275 | 0 | break; |
11276 | 193 | case 37: |
11277 | | // MVE_VLDRWU32_rq, MVE_VSTRW32_rq |
11278 | 193 | printMveAddrModeRQOperand_2(MI, 1, O); |
11279 | 193 | return; |
11280 | 0 | break; |
11281 | 3.74k | case 38: |
11282 | | // MVE_VMOVimmi16, MVE_VMOVimmi32, MVE_VMOVimmi8, MVE_VMVNimmi16, MVE_VMV... |
11283 | 3.74k | printVMOVModImmOperand(MI, 1, O); |
11284 | 3.74k | return; |
11285 | 0 | break; |
11286 | 696 | case 39: |
11287 | | // MVE_WLSTP_16, MVE_WLSTP_32, MVE_WLSTP_64, MVE_WLSTP_8, t2BFic, t2WLS |
11288 | 696 | printOperandAddr(MI, Address, 2, O); |
11289 | 696 | break; |
11290 | 1.01k | case 40: |
11291 | | // SSAT, SSAT16, t2SSAT, t2SSAT16 |
11292 | 1.01k | printImmPlusOneOperand(MI, 1, O); |
11293 | 1.01k | SStream_concat0(O, ", "); |
11294 | 1.01k | printOperand(MI, 2, O); |
11295 | 1.01k | break; |
11296 | 689 | case 41: |
11297 | | // STLEXD, STREXD |
11298 | 689 | printGPRPairOperand(MI, 1, O); |
11299 | 689 | SStream_concat0(O, ", "); |
11300 | 689 | printAddrMode7Operand(MI, 2, O); |
11301 | 689 | return; |
11302 | 0 | break; |
11303 | 1.32k | case 42: |
11304 | | // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... |
11305 | 1.32k | printNoHashImmediate(MI, 4, O); |
11306 | 1.32k | break; |
11307 | 4.13k | case 43: |
11308 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... |
11309 | 4.13k | printNoHashImmediate(MI, 6, O); |
11310 | 4.13k | break; |
11311 | 3.09k | case 44: |
11312 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
11313 | 3.09k | printNoHashImmediate(MI, 8, O); |
11314 | 3.09k | SStream_concat0(O, "], "); |
11315 | 3.09k | break; |
11316 | 471 | case 45: |
11317 | | // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... |
11318 | 471 | SStream_concat0(O, "[]}, "); |
11319 | 471 | break; |
11320 | 2.18k | case 46: |
11321 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
11322 | 2.18k | printNoHashImmediate(MI, 10, O); |
11323 | 2.18k | SStream_concat0(O, "], "); |
11324 | 2.18k | printOperand(MI, 1, O); |
11325 | 2.18k | SStream_concat1(O, '['); |
11326 | 2.18k | printNoHashImmediate(MI, 10, O); |
11327 | 2.18k | SStream_concat0(O, "], "); |
11328 | 2.18k | printOperand(MI, 2, O); |
11329 | 2.18k | SStream_concat1(O, '['); |
11330 | 2.18k | printNoHashImmediate(MI, 10, O); |
11331 | 2.18k | break; |
11332 | 1.44k | case 47: |
11333 | | // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... |
11334 | 1.44k | SStream_concat0(O, "[], "); |
11335 | 1.44k | printOperand(MI, 3, O); |
11336 | 1.44k | SStream_concat0(O, "[]}, "); |
11337 | 1.44k | break; |
11338 | 1.22k | case 48: |
11339 | | // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... |
11340 | 1.22k | printNoHashImmediate(MI, 12, O); |
11341 | 1.22k | SStream_concat0(O, "], "); |
11342 | 1.22k | printOperand(MI, 1, O); |
11343 | 1.22k | SStream_concat1(O, '['); |
11344 | 1.22k | printNoHashImmediate(MI, 12, O); |
11345 | 1.22k | SStream_concat0(O, "], "); |
11346 | 1.22k | printOperand(MI, 2, O); |
11347 | 1.22k | SStream_concat1(O, '['); |
11348 | 1.22k | printNoHashImmediate(MI, 12, O); |
11349 | 1.22k | SStream_concat0(O, "], "); |
11350 | 1.22k | printOperand(MI, 3, O); |
11351 | 1.22k | SStream_concat1(O, '['); |
11352 | 1.22k | printNoHashImmediate(MI, 12, O); |
11353 | 1.22k | SStream_concat0(O, "]}, "); |
11354 | 1.22k | printAddrMode6Operand(MI, 5, O); |
11355 | 1.22k | printAddrMode6OffsetOperand(MI, 7, O); |
11356 | 1.22k | return; |
11357 | 0 | break; |
11358 | 941 | case 49: |
11359 | | // VLDRD, VLDRS, VSTRD, VSTRS |
11360 | 941 | printAddrMode5Operand_0(MI, 1, O); |
11361 | 941 | return; |
11362 | 0 | break; |
11363 | 339 | case 50: |
11364 | | // VLDRH, VSTRH |
11365 | 339 | printAddrMode5FP16Operand_0(MI, 1, O); |
11366 | 339 | return; |
11367 | 0 | break; |
11368 | 159 | case 51: |
11369 | | // VST1LNd16, VST1LNd32, VST1LNd8 |
11370 | 159 | printNoHashImmediate(MI, 3, O); |
11371 | 159 | SStream_concat0(O, "]}, "); |
11372 | 159 | printAddrMode6Operand(MI, 0, O); |
11373 | 159 | return; |
11374 | 0 | break; |
11375 | 1.86k | case 52: |
11376 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... |
11377 | 1.86k | printNoHashImmediate(MI, 5, O); |
11378 | 1.86k | break; |
11379 | 846 | case 53: |
11380 | | // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... |
11381 | 846 | printNoHashImmediate(MI, 7, O); |
11382 | 846 | SStream_concat0(O, "], "); |
11383 | 846 | printOperand(MI, 5, O); |
11384 | 846 | SStream_concat1(O, '['); |
11385 | 846 | printNoHashImmediate(MI, 7, O); |
11386 | 846 | SStream_concat0(O, "], "); |
11387 | 846 | printOperand(MI, 6, O); |
11388 | 846 | SStream_concat1(O, '['); |
11389 | 846 | printNoHashImmediate(MI, 7, O); |
11390 | 846 | SStream_concat0(O, "]}, "); |
11391 | 846 | printAddrMode6Operand(MI, 1, O); |
11392 | 846 | printAddrMode6OffsetOperand(MI, 3, O); |
11393 | 846 | return; |
11394 | 0 | break; |
11395 | 3.93k | case 54: |
11396 | | // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... |
11397 | 3.93k | printOperand(MI, 5, O); |
11398 | 3.93k | SStream_concat0(O, ", "); |
11399 | 3.93k | printOperand(MI, 6, O); |
11400 | 3.93k | break; |
11401 | 135 | case 55: |
11402 | | // VTBL1 |
11403 | 135 | printVectorListOne(MI, 1, O); |
11404 | 135 | SStream_concat0(O, ", "); |
11405 | 135 | printOperand(MI, 2, O); |
11406 | 135 | return; |
11407 | 0 | break; |
11408 | 184 | case 56: |
11409 | | // VTBL2 |
11410 | 184 | printVectorListTwo(MI, 1, O); |
11411 | 184 | SStream_concat0(O, ", "); |
11412 | 184 | printOperand(MI, 2, O); |
11413 | 184 | return; |
11414 | 0 | break; |
11415 | 94 | case 57: |
11416 | | // VTBL3 |
11417 | 94 | printVectorListThree(MI, 1, O); |
11418 | 94 | SStream_concat0(O, ", "); |
11419 | 94 | printOperand(MI, 2, O); |
11420 | 94 | return; |
11421 | 0 | break; |
11422 | 85 | case 58: |
11423 | | // VTBL4 |
11424 | 85 | printVectorListFour(MI, 1, O); |
11425 | 85 | SStream_concat0(O, ", "); |
11426 | 85 | printOperand(MI, 2, O); |
11427 | 85 | return; |
11428 | 0 | break; |
11429 | 126 | case 59: |
11430 | | // VTBX1 |
11431 | 126 | printVectorListOne(MI, 2, O); |
11432 | 126 | SStream_concat0(O, ", "); |
11433 | 126 | printOperand(MI, 3, O); |
11434 | 126 | return; |
11435 | 0 | break; |
11436 | 106 | case 60: |
11437 | | // VTBX2 |
11438 | 106 | printVectorListTwo(MI, 2, O); |
11439 | 106 | SStream_concat0(O, ", "); |
11440 | 106 | printOperand(MI, 3, O); |
11441 | 106 | return; |
11442 | 0 | break; |
11443 | 271 | case 61: |
11444 | | // VTBX3 |
11445 | 271 | printVectorListThree(MI, 2, O); |
11446 | 271 | SStream_concat0(O, ", "); |
11447 | 271 | printOperand(MI, 3, O); |
11448 | 271 | return; |
11449 | 0 | break; |
11450 | 156 | case 62: |
11451 | | // VTBX4 |
11452 | 156 | printVectorListFour(MI, 2, O); |
11453 | 156 | SStream_concat0(O, ", "); |
11454 | 156 | printOperand(MI, 3, O); |
11455 | 156 | return; |
11456 | 0 | break; |
11457 | 2.55k | case 63: |
11458 | | // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... |
11459 | 2.55k | SStream_concat0(O, " ^"); |
11460 | 2.55k | return; |
11461 | 0 | break; |
11462 | 390 | case 64: |
11463 | | // t2BFLi, t2BFi |
11464 | 390 | printOperandAddr(MI, Address, 1, O); |
11465 | 390 | return; |
11466 | 0 | break; |
11467 | 30.0k | case 65: |
11468 | | // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci |
11469 | 30.0k | printThumbLdrLabelOperand(MI, 1, O); |
11470 | 30.0k | return; |
11471 | 0 | break; |
11472 | 1.63k | case 66: |
11473 | | // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs |
11474 | 1.63k | printT2AddrModeSoRegOperand(MI, 1, O); |
11475 | 1.63k | return; |
11476 | 0 | break; |
11477 | 42 | case 67: |
11478 | | // t2LDREX |
11479 | 42 | printT2AddrModeImm0_1020s4Operand(MI, 1, O); |
11480 | 42 | return; |
11481 | 0 | break; |
11482 | 1.11k | case 68: |
11483 | | // t2MRS_M |
11484 | 1.11k | printMSRMaskOperand(MI, 1, O); |
11485 | 1.11k | return; |
11486 | 0 | break; |
11487 | 2.42k | case 69: |
11488 | | // tADDspi, tSUBspi |
11489 | 2.42k | printThumbS4ImmOperand(MI, 2, O); |
11490 | 2.42k | return; |
11491 | 0 | break; |
11492 | 25.1k | case 70: |
11493 | | // tADR |
11494 | 25.1k | printAdrLabelOperandAddr_2(MI, Address, 1, O); |
11495 | 25.1k | return; |
11496 | 0 | break; |
11497 | 67.8k | case 71: |
11498 | | // tASRri, tLSRri |
11499 | 67.8k | printThumbSRImm(MI, 3, O); |
11500 | 67.8k | return; |
11501 | 0 | break; |
11502 | 57.0k | case 72: |
11503 | | // tLDRBi, tSTRBi |
11504 | 57.0k | printThumbAddrModeImm5S1Operand(MI, 1, O); |
11505 | 57.0k | return; |
11506 | 0 | break; |
11507 | 38.7k | case 73: |
11508 | | // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr |
11509 | 38.7k | printThumbAddrModeRROperand(MI, 1, O); |
11510 | 38.7k | return; |
11511 | 0 | break; |
11512 | 64.2k | case 74: |
11513 | | // tLDRHi, tSTRHi |
11514 | 64.2k | printThumbAddrModeImm5S2Operand(MI, 1, O); |
11515 | 64.2k | return; |
11516 | 0 | break; |
11517 | 77.2k | case 75: |
11518 | | // tLDRi, tSTRi |
11519 | 77.2k | printThumbAddrModeImm5S4Operand(MI, 1, O); |
11520 | 77.2k | return; |
11521 | 0 | break; |
11522 | 36.7k | case 76: |
11523 | | // tLDRspi, tSTRspi |
11524 | 36.7k | printThumbAddrModeSPOperand(MI, 1, O); |
11525 | 36.7k | return; |
11526 | 0 | break; |
11527 | 975k | } |
11528 | | |
11529 | | // Fragment 5 encoded into 5 bits for 27 unique commands. |
11530 | 468k | switch ((uint32_t)((Bits >> 46) & 31)) { |
11531 | 0 | default: |
11532 | 0 | assert(0 && "Invalid command number."); |
11533 | 180k | case 0: |
11534 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... |
11535 | 180k | SStream_concat0(O, ", "); |
11536 | 180k | break; |
11537 | 211k | case 1: |
11538 | | // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... |
11539 | 211k | return; |
11540 | 0 | break; |
11541 | 0 | case 2: |
11542 | | // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... |
11543 | 0 | SStream_concat1(O, '!'); |
11544 | 0 | return; |
11545 | 0 | break; |
11546 | 966 | case 3: |
11547 | | // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... |
11548 | 966 | printOperand(MI, 3, O); |
11549 | 966 | return; |
11550 | 0 | break; |
11551 | 415 | case 4: |
11552 | | // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, VBF16MALBQI, VBF16MALTQI, VCMLAv2f32... |
11553 | 415 | printVectorIndex(MI, 4, O); |
11554 | 415 | break; |
11555 | 5.85k | case 5: |
11556 | | // CDE_CX2DA, CDE_CX3D, CDE_CX3DA, VLD1DUPd16wb_register, VLD1DUPd32wb_re... |
11557 | 5.85k | printOperand(MI, 4, O); |
11558 | 5.85k | break; |
11559 | 24.6k | case 6: |
11560 | | // CDP, t2CDP, t2CDP2 |
11561 | 24.6k | printCImmediate(MI, 2, O); |
11562 | 24.6k | SStream_concat0(O, ", "); |
11563 | 24.6k | printCImmediate(MI, 3, O); |
11564 | 24.6k | SStream_concat0(O, ", "); |
11565 | 24.6k | printCImmediate(MI, 4, O); |
11566 | 24.6k | SStream_concat0(O, ", "); |
11567 | 24.6k | printOperand(MI, 5, O); |
11568 | 24.6k | return; |
11569 | 0 | break; |
11570 | 6.19k | case 7: |
11571 | | // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ... |
11572 | 6.19k | printOperand(MI, 2, O); |
11573 | 6.19k | break; |
11574 | 6.23k | case 8: |
11575 | | // MRC, t2MRC, t2MRC2 |
11576 | 6.23k | printOperand(MI, 0, O); |
11577 | 6.23k | SStream_concat0(O, ", "); |
11578 | 6.23k | printCImmediate(MI, 3, O); |
11579 | 6.23k | SStream_concat0(O, ", "); |
11580 | 6.23k | printCImmediate(MI, 4, O); |
11581 | 6.23k | SStream_concat0(O, ", "); |
11582 | 6.23k | printOperand(MI, 5, O); |
11583 | 6.23k | return; |
11584 | 0 | break; |
11585 | 3.52k | case 9: |
11586 | | // MVE_VLDRBS16_post, MVE_VLDRBS32_post, MVE_VLDRBU16_post, MVE_VLDRBU32_... |
11587 | 3.52k | printT2AddrModeImm8OffsetOperand(MI, 3, O); |
11588 | 3.52k | return; |
11589 | 0 | break; |
11590 | 1.61k | case 10: |
11591 | | // MVE_VMOV_from_lane_32, MVE_VMOV_from_lane_s16, MVE_VMOV_from_lane_s8, ... |
11592 | 1.61k | printVectorIndex(MI, 2, O); |
11593 | 1.61k | return; |
11594 | 0 | break; |
11595 | 539 | case 11: |
11596 | | // MVE_VSHLL_lws16bh, MVE_VSHLL_lws16th, MVE_VSHLL_lwu16bh, MVE_VSHLL_lwu... |
11597 | 539 | SStream_concat0(O, ", #16"); |
11598 | 539 | return; |
11599 | 0 | break; |
11600 | 1.11k | case 12: |
11601 | | // MVE_VSHLL_lws8bh, MVE_VSHLL_lws8th, MVE_VSHLL_lwu8bh, MVE_VSHLL_lwu8th |
11602 | 1.11k | SStream_concat0(O, ", #8"); |
11603 | 1.11k | return; |
11604 | 0 | break; |
11605 | 984 | case 13: |
11606 | | // SSAT, t2SSAT |
11607 | 984 | printShiftImmOperand(MI, 3, O); |
11608 | 984 | return; |
11609 | 0 | break; |
11610 | 390 | case 14: |
11611 | | // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... |
11612 | 390 | printRotImmOperand(MI, 2, O); |
11613 | 390 | return; |
11614 | 0 | break; |
11615 | 6.80k | case 15: |
11616 | | // VCEQzv16i8, VCEQzv2f32, VCEQzv2i32, VCEQzv4f16, VCEQzv4f32, VCEQzv4i16... |
11617 | 6.80k | SStream_concat0(O, ", #0"); |
11618 | 6.80k | return; |
11619 | 0 | break; |
11620 | 326 | case 16: |
11621 | | // VFMALDI, VFMALQI, VFMSLDI, VFMSLQI |
11622 | 326 | printVectorIndex(MI, 3, O); |
11623 | 326 | return; |
11624 | 0 | break; |
11625 | 4.90k | case 17: |
11626 | | // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... |
11627 | 4.90k | SStream_concat0(O, "]}, "); |
11628 | 4.90k | break; |
11629 | 4.60k | case 18: |
11630 | | // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... |
11631 | 4.60k | SStream_concat0(O, "], "); |
11632 | 4.60k | break; |
11633 | 2.39k | case 19: |
11634 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
11635 | 2.39k | printOperand(MI, 1, O); |
11636 | 2.39k | SStream_concat1(O, '['); |
11637 | 2.39k | printNoHashImmediate(MI, 8, O); |
11638 | 2.39k | break; |
11639 | 57 | case 20: |
11640 | | // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 |
11641 | 57 | printAddrMode6Operand(MI, 3, O); |
11642 | 57 | return; |
11643 | 0 | break; |
11644 | 819 | case 21: |
11645 | | // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... |
11646 | 819 | printAddrMode6Operand(MI, 4, O); |
11647 | 819 | break; |
11648 | 1.03k | case 22: |
11649 | | // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... |
11650 | 1.03k | printAddrMode6Operand(MI, 5, O); |
11651 | 1.03k | printAddrMode6OffsetOperand(MI, 7, O); |
11652 | 1.03k | return; |
11653 | 0 | break; |
11654 | 1.40k | case 23: |
11655 | | // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... |
11656 | 1.40k | SStream_concat0(O, "}, "); |
11657 | 1.40k | printAddrMode6Operand(MI, 1, O); |
11658 | 1.40k | printAddrMode6OffsetOperand(MI, 3, O); |
11659 | 1.40k | return; |
11660 | 0 | break; |
11661 | 694 | case 24: |
11662 | | // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... |
11663 | 694 | printOperand(MI, 5, O); |
11664 | 694 | SStream_concat1(O, '['); |
11665 | 694 | printNoHashImmediate(MI, 8, O); |
11666 | 694 | SStream_concat0(O, "], "); |
11667 | 694 | printOperand(MI, 6, O); |
11668 | 694 | SStream_concat1(O, '['); |
11669 | 694 | printNoHashImmediate(MI, 8, O); |
11670 | 694 | SStream_concat0(O, "], "); |
11671 | 694 | printOperand(MI, 7, O); |
11672 | 694 | SStream_concat1(O, '['); |
11673 | 694 | printNoHashImmediate(MI, 8, O); |
11674 | 694 | SStream_concat0(O, "]}, "); |
11675 | 694 | printAddrMode6Operand(MI, 1, O); |
11676 | 694 | printAddrMode6OffsetOperand(MI, 3, O); |
11677 | 694 | return; |
11678 | 0 | break; |
11679 | 1.70k | case 25: |
11680 | | // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... |
11681 | 1.70k | SStream_concat0(O, " ^"); |
11682 | 1.70k | return; |
11683 | 0 | break; |
11684 | 0 | case 26: |
11685 | | // t2MOVsra_flag, t2MOVsrl_flag |
11686 | 0 | SStream_concat0(O, ", #1"); |
11687 | 0 | return; |
11688 | 0 | break; |
11689 | 468k | } |
11690 | | |
11691 | | // Fragment 6 encoded into 6 bits for 38 unique commands. |
11692 | 205k | switch ((uint32_t)((Bits >> 51) & 63)) { |
11693 | 0 | default: |
11694 | 0 | assert(0 && "Invalid command number."); |
11695 | 64.2k | case 0: |
11696 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... |
11697 | 64.2k | printOperand(MI, 2, O); |
11698 | 64.2k | break; |
11699 | 3.60k | case 1: |
11700 | | // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... |
11701 | 3.60k | printOperand(MI, 4, O); |
11702 | 3.60k | break; |
11703 | 5.98k | case 2: |
11704 | | // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri |
11705 | 5.98k | printModImmOperand(MI, 2, O); |
11706 | 5.98k | return; |
11707 | 0 | break; |
11708 | 11.1k | case 3: |
11709 | | // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... |
11710 | 11.1k | printSORegImmOperand(MI, 2, O); |
11711 | 11.1k | return; |
11712 | 0 | break; |
11713 | 6.58k | case 4: |
11714 | | // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, CDE_CX2DA, CDE_CX3D, VADDD, VBF16MAL... |
11715 | 6.58k | return; |
11716 | 0 | break; |
11717 | 497 | case 5: |
11718 | | // BFI, t2BFI |
11719 | 497 | printBitfieldInvMaskImmOperand(MI, 3, O); |
11720 | 497 | return; |
11721 | 0 | break; |
11722 | 6.28k | case 6: |
11723 | | // CDE_CX3DA, MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f... |
11724 | 6.28k | SStream_concat0(O, ", "); |
11725 | 6.28k | break; |
11726 | 16.0k | case 7: |
11727 | | // CDE_VCX2_vec, CDE_VCX3_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, M... |
11728 | 16.0k | printOperand(MI, 3, O); |
11729 | 16.0k | break; |
11730 | 846 | case 8: |
11731 | | // CDE_VCX3A_fpdp, CDE_VCX3A_fpsp, VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8... |
11732 | 846 | printOperand(MI, 5, O); |
11733 | 846 | break; |
11734 | 4.53k | case 9: |
11735 | | // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... |
11736 | 4.53k | printCoprocOptionImm(MI, 3, O); |
11737 | 4.53k | return; |
11738 | 0 | break; |
11739 | 9.15k | case 10: |
11740 | | // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... |
11741 | 9.15k | printPostIdxImm8s4Operand(MI, 3, O); |
11742 | 9.15k | return; |
11743 | 0 | break; |
11744 | 10.0k | case 11: |
11745 | | // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... |
11746 | 10.0k | printAddrMode2OffsetOperand(MI, 3, O); |
11747 | 10.0k | return; |
11748 | 0 | break; |
11749 | 580 | case 12: |
11750 | | // LDRD, STRD |
11751 | 580 | printAddrMode3Operand_0(MI, 2, O); |
11752 | 580 | return; |
11753 | 0 | break; |
11754 | 6.01k | case 13: |
11755 | | // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST |
11756 | 6.01k | printAddrMode7Operand(MI, 3, O); |
11757 | 6.01k | break; |
11758 | 915 | case 14: |
11759 | | // LDRD_PRE, STRD_PRE |
11760 | 915 | printAddrMode3Operand_1(MI, 3, O); |
11761 | 915 | SStream_concat1(O, '!'); |
11762 | 915 | return; |
11763 | 0 | break; |
11764 | 670 | case 15: |
11765 | | // LDRHTi, LDRSBTi, LDRSHTi, STRHTi |
11766 | 670 | printPostIdxImm8Operand(MI, 3, O); |
11767 | 670 | return; |
11768 | 0 | break; |
11769 | 1.46k | case 16: |
11770 | | // LDRHTr, LDRSBTr, LDRSHTr, STRHTr |
11771 | 1.46k | printPostIdxRegOperand(MI, 3, O); |
11772 | 1.46k | return; |
11773 | 0 | break; |
11774 | 2.74k | case 17: |
11775 | | // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST |
11776 | 2.74k | printAddrMode3OffsetOperand(MI, 3, O); |
11777 | 2.74k | return; |
11778 | 0 | break; |
11779 | 506 | case 18: |
11780 | | // MCRR2 |
11781 | 506 | printCImmediate(MI, 4, O); |
11782 | 506 | return; |
11783 | 0 | break; |
11784 | 0 | case 19: |
11785 | | // MVE_SQRSHRL, MVE_UQRSHLL |
11786 | 0 | printMveSaturateOp(MI, 5, O); |
11787 | 0 | SStream_concat0(O, ", "); |
11788 | 0 | printOperand(MI, 4, O); |
11789 | 0 | return; |
11790 | 0 | break; |
11791 | 723 | case 20: |
11792 | | // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... |
11793 | 723 | printAddrMode7Operand(MI, 2, O); |
11794 | 723 | return; |
11795 | 0 | break; |
11796 | 290 | case 21: |
11797 | | // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 |
11798 | 290 | printComplexRotationOp_180_90(MI, 3, O); |
11799 | 290 | return; |
11800 | 0 | break; |
11801 | 253 | case 22: |
11802 | | // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 |
11803 | 253 | printComplexRotationOp_90_0(MI, 4, O); |
11804 | 253 | return; |
11805 | 0 | break; |
11806 | 1.75k | case 23: |
11807 | | // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... |
11808 | 1.75k | printAddrMode6Operand(MI, 1, O); |
11809 | 1.75k | break; |
11810 | 2.12k | case 24: |
11811 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD |
11812 | 2.12k | printAddrMode6Operand(MI, 2, O); |
11813 | 2.12k | printAddrMode6OffsetOperand(MI, 4, O); |
11814 | 2.12k | return; |
11815 | 0 | break; |
11816 | 187 | case 25: |
11817 | | // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 |
11818 | 187 | printOperand(MI, 1, O); |
11819 | 187 | SStream_concat1(O, '['); |
11820 | 187 | printNoHashImmediate(MI, 6, O); |
11821 | 187 | SStream_concat0(O, "]}, "); |
11822 | 187 | printAddrMode6Operand(MI, 2, O); |
11823 | 187 | return; |
11824 | 0 | break; |
11825 | 1.81k | case 26: |
11826 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
11827 | 1.81k | SStream_concat0(O, "]}, "); |
11828 | 1.81k | printAddrMode6Operand(MI, 3, O); |
11829 | 1.81k | printAddrMode6OffsetOperand(MI, 5, O); |
11830 | 1.81k | return; |
11831 | 0 | break; |
11832 | 414 | case 27: |
11833 | | // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... |
11834 | 414 | printAddrMode6OffsetOperand(MI, 6, O); |
11835 | 414 | return; |
11836 | 0 | break; |
11837 | 586 | case 28: |
11838 | | // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 |
11839 | 586 | SStream_concat0(O, "], "); |
11840 | 586 | printOperand(MI, 2, O); |
11841 | 586 | SStream_concat1(O, '['); |
11842 | 586 | printNoHashImmediate(MI, 8, O); |
11843 | 586 | SStream_concat0(O, "]}, "); |
11844 | 586 | printAddrMode6Operand(MI, 3, O); |
11845 | 586 | return; |
11846 | 0 | break; |
11847 | 1.02k | case 29: |
11848 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
11849 | 1.02k | printAddrMode6Operand(MI, 4, O); |
11850 | 1.02k | printAddrMode6OffsetOperand(MI, 6, O); |
11851 | 1.02k | return; |
11852 | 0 | break; |
11853 | 2.53k | case 30: |
11854 | | // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... |
11855 | 2.53k | printOperand(MI, 7, O); |
11856 | 2.53k | SStream_concat0(O, "}, "); |
11857 | 2.53k | printAddrMode6Operand(MI, 1, O); |
11858 | 2.53k | printAddrMode6OffsetOperand(MI, 3, O); |
11859 | 2.53k | return; |
11860 | 0 | break; |
11861 | 2.92k | case 31: |
11862 | | // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... |
11863 | 2.92k | printT2SOOperand(MI, 2, O); |
11864 | 2.92k | return; |
11865 | 0 | break; |
11866 | 397 | case 32: |
11867 | | // t2ASRri, t2LSRri |
11868 | 397 | printThumbSRImm(MI, 2, O); |
11869 | 397 | return; |
11870 | 0 | break; |
11871 | 418 | case 33: |
11872 | | // t2BFic, t2CSEL, t2CSINC, t2CSINV, t2CSNEG |
11873 | 418 | printMandatoryPredicateOperand(MI, 3, O); |
11874 | 418 | return; |
11875 | 0 | break; |
11876 | 7.24k | case 34: |
11877 | | // t2LDRD_PRE, t2STRD_PRE |
11878 | 7.24k | printT2AddrModeImm8s4Operand_1(MI, 3, O); |
11879 | 7.24k | SStream_concat1(O, '!'); |
11880 | 7.24k | return; |
11881 | 0 | break; |
11882 | 662 | case 35: |
11883 | | // t2LDRDi8, t2STRDi8 |
11884 | 662 | printT2AddrModeImm8s4Operand_0(MI, 2, O); |
11885 | 662 | return; |
11886 | 0 | break; |
11887 | 721 | case 36: |
11888 | | // t2STREX |
11889 | 721 | printT2AddrModeImm0_1020s4Operand(MI, 2, O); |
11890 | 721 | return; |
11891 | 0 | break; |
11892 | 29.2k | case 37: |
11893 | | // tADDrSPi |
11894 | 29.2k | printThumbS4ImmOperand(MI, 2, O); |
11895 | 29.2k | return; |
11896 | 0 | break; |
11897 | 205k | } |
11898 | | |
11899 | | // Fragment 7 encoded into 4 bits for 16 unique commands. |
11900 | 98.8k | switch ((uint32_t)((Bits >> 57) & 15)) { |
11901 | 0 | default: |
11902 | 0 | assert(0 && "Invalid command number."); |
11903 | 45.1k | case 0: |
11904 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... |
11905 | 45.1k | return; |
11906 | 0 | break; |
11907 | 28.9k | case 1: |
11908 | | // CDE_CX3A, CDE_VCX3A_vec, CDE_VCX3_vec, LDRD_POST, MLA, MLS, MVE_VCADDf... |
11909 | 28.9k | SStream_concat0(O, ", "); |
11910 | 28.9k | break; |
11911 | 0 | case 2: |
11912 | | // CDE_CX3DA |
11913 | 0 | printOperand(MI, 5, O); |
11914 | 0 | return; |
11915 | 0 | break; |
11916 | 4.69k | case 3: |
11917 | | // MCR, t2MCR, t2MCR2 |
11918 | 4.69k | printCImmediate(MI, 3, O); |
11919 | 4.69k | SStream_concat0(O, ", "); |
11920 | 4.69k | printCImmediate(MI, 4, O); |
11921 | 4.69k | SStream_concat0(O, ", "); |
11922 | 4.69k | printOperand(MI, 5, O); |
11923 | 4.69k | return; |
11924 | 0 | break; |
11925 | 1.36k | case 4: |
11926 | | // MCRR, t2MCRR, t2MCRR2 |
11927 | 1.36k | printOperand(MI, 3, O); |
11928 | 1.36k | SStream_concat0(O, ", "); |
11929 | 1.36k | printCImmediate(MI, 4, O); |
11930 | 1.36k | return; |
11931 | 0 | break; |
11932 | 2.57k | case 5: |
11933 | | // MVE_VMOV_rr_q, VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4... |
11934 | 2.57k | printVectorIndex(MI, 3, O); |
11935 | 2.57k | break; |
11936 | 187 | case 6: |
11937 | | // PKHBT, t2PKHBT |
11938 | 187 | printPKHLSLShiftImm(MI, 3, O); |
11939 | 187 | return; |
11940 | 0 | break; |
11941 | 292 | case 7: |
11942 | | // PKHTB, t2PKHTB |
11943 | 292 | printPKHASRShiftImm(MI, 3, O); |
11944 | 292 | return; |
11945 | 0 | break; |
11946 | 615 | case 8: |
11947 | | // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... |
11948 | 615 | printRotImmOperand(MI, 3, O); |
11949 | 615 | return; |
11950 | 0 | break; |
11951 | 1.31k | case 9: |
11952 | | // USAT, t2USAT |
11953 | 1.31k | printShiftImmOperand(MI, 3, O); |
11954 | 1.31k | return; |
11955 | 0 | break; |
11956 | 231 | case 10: |
11957 | | // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... |
11958 | 231 | printComplexRotationOp_90_0(MI, 5, O); |
11959 | 231 | return; |
11960 | 0 | break; |
11961 | 2.73k | case 11: |
11962 | | // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... |
11963 | 2.73k | SStream_concat0(O, "}, "); |
11964 | 2.73k | break; |
11965 | 4.42k | case 12: |
11966 | | // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... |
11967 | 4.42k | SStream_concat1(O, '['); |
11968 | 4.42k | break; |
11969 | 994 | case 13: |
11970 | | // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslfd, ... |
11971 | 994 | printVectorIndex(MI, 4, O); |
11972 | 994 | return; |
11973 | 0 | break; |
11974 | 1.21k | case 14: |
11975 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD |
11976 | 1.21k | printAddrMode6OffsetOperand(MI, 3, O); |
11977 | 1.21k | return; |
11978 | 0 | break; |
11979 | 4.10k | case 15: |
11980 | | // t2LDRD_POST, t2STRD_POST |
11981 | 4.10k | printT2AddrModeImm8s4OffsetOperand(MI, 4, O); |
11982 | 4.10k | return; |
11983 | 0 | break; |
11984 | 98.8k | } |
11985 | | |
11986 | 38.6k | switch (MCInst_getOpcode(MI)) { |
11987 | 0 | default: |
11988 | 0 | assert(0 && "Unexpected opcode."); |
11989 | 0 | case ARM_CDE_CX3A: |
11990 | 0 | case ARM_CDE_VCX3A_vec: |
11991 | 0 | case ARM_CDE_VCX3_vec: |
11992 | 815 | case ARM_LDRD_POST: |
11993 | 1.31k | case ARM_MLA: |
11994 | 1.47k | case ARM_MLS: |
11995 | 1.98k | case ARM_MVE_VCADDf16: |
11996 | 2.10k | case ARM_MVE_VCADDf32: |
11997 | 2.27k | case ARM_MVE_VCADDi16: |
11998 | 2.57k | case ARM_MVE_VCADDi32: |
11999 | 2.77k | case ARM_MVE_VCADDi8: |
12000 | 3.15k | case ARM_MVE_VCMLAf16: |
12001 | 3.28k | case ARM_MVE_VCMLAf32: |
12002 | 3.49k | case ARM_MVE_VCMULf16: |
12003 | 3.66k | case ARM_MVE_VCMULf32: |
12004 | 4.42k | case ARM_MVE_VDWDUPu16: |
12005 | 4.44k | case ARM_MVE_VDWDUPu32: |
12006 | 5.20k | case ARM_MVE_VDWDUPu8: |
12007 | 5.81k | case ARM_MVE_VHCADDs16: |
12008 | 5.93k | case ARM_MVE_VHCADDs32: |
12009 | 6.16k | case ARM_MVE_VHCADDs8: |
12010 | 6.24k | case ARM_MVE_VIWDUPu16: |
12011 | 6.31k | case ARM_MVE_VIWDUPu32: |
12012 | 6.92k | case ARM_MVE_VIWDUPu8: |
12013 | 6.92k | case ARM_MVE_VMLALDAVas16: |
12014 | 6.92k | case ARM_MVE_VMLALDAVas32: |
12015 | 6.92k | case ARM_MVE_VMLALDAVau16: |
12016 | 6.92k | case ARM_MVE_VMLALDAVau32: |
12017 | 6.98k | case ARM_MVE_VMLALDAVaxs16: |
12018 | 7.21k | case ARM_MVE_VMLALDAVaxs32: |
12019 | 7.21k | case ARM_MVE_VMLALDAVs16: |
12020 | 7.21k | case ARM_MVE_VMLALDAVs32: |
12021 | 7.21k | case ARM_MVE_VMLALDAVu16: |
12022 | 7.21k | case ARM_MVE_VMLALDAVu32: |
12023 | 7.26k | case ARM_MVE_VMLALDAVxs16: |
12024 | 7.34k | case ARM_MVE_VMLALDAVxs32: |
12025 | 7.45k | case ARM_MVE_VMLSLDAVas16: |
12026 | 7.56k | case ARM_MVE_VMLSLDAVas32: |
12027 | 7.61k | case ARM_MVE_VMLSLDAVaxs16: |
12028 | 8.17k | case ARM_MVE_VMLSLDAVaxs32: |
12029 | 8.38k | case ARM_MVE_VMLSLDAVs16: |
12030 | 8.51k | case ARM_MVE_VMLSLDAVs32: |
12031 | 8.60k | case ARM_MVE_VMLSLDAVxs16: |
12032 | 8.73k | case ARM_MVE_VMLSLDAVxs32: |
12033 | 8.73k | case ARM_MVE_VRMLALDAVHas32: |
12034 | 8.73k | case ARM_MVE_VRMLALDAVHau32: |
12035 | 8.88k | case ARM_MVE_VRMLALDAVHaxs32: |
12036 | 8.88k | case ARM_MVE_VRMLALDAVHs32: |
12037 | 8.88k | case ARM_MVE_VRMLALDAVHu32: |
12038 | 8.92k | case ARM_MVE_VRMLALDAVHxs32: |
12039 | 8.99k | case ARM_MVE_VRMLSLDAVHas32: |
12040 | 9.15k | case ARM_MVE_VRMLSLDAVHaxs32: |
12041 | 9.23k | case ARM_MVE_VRMLSLDAVHs32: |
12042 | 9.42k | case ARM_MVE_VRMLSLDAVHxs32: |
12043 | 9.53k | case ARM_SBFX: |
12044 | 9.99k | case ARM_SMLABB: |
12045 | 10.1k | case ARM_SMLABT: |
12046 | 10.2k | case ARM_SMLAD: |
12047 | 10.3k | case ARM_SMLADX: |
12048 | 10.4k | case ARM_SMLALBB: |
12049 | 10.8k | case ARM_SMLALBT: |
12050 | 10.9k | case ARM_SMLALD: |
12051 | 11.1k | case ARM_SMLALDX: |
12052 | 11.1k | case ARM_SMLALTB: |
12053 | 11.4k | case ARM_SMLALTT: |
12054 | 11.4k | case ARM_SMLATB: |
12055 | 11.8k | case ARM_SMLATT: |
12056 | 11.9k | case ARM_SMLAWB: |
12057 | 12.0k | case ARM_SMLAWT: |
12058 | 12.0k | case ARM_SMLSD: |
12059 | 12.1k | case ARM_SMLSDX: |
12060 | 12.2k | case ARM_SMLSLD: |
12061 | 12.3k | case ARM_SMLSLDX: |
12062 | 12.3k | case ARM_SMMLA: |
12063 | 12.5k | case ARM_SMMLAR: |
12064 | 12.6k | case ARM_SMMLS: |
12065 | 12.6k | case ARM_SMMLSR: |
12066 | 12.7k | case ARM_SMULL: |
12067 | 13.8k | case ARM_STRD_POST: |
12068 | 13.8k | case ARM_UBFX: |
12069 | 14.3k | case ARM_UMAAL: |
12070 | 14.9k | case ARM_UMULL: |
12071 | 15.0k | case ARM_USADA8: |
12072 | 15.5k | case ARM_VEXTd16: |
12073 | 15.7k | case ARM_VEXTd32: |
12074 | 16.0k | case ARM_VEXTd8: |
12075 | 16.1k | case ARM_VEXTq16: |
12076 | 16.1k | case ARM_VEXTq32: |
12077 | 16.3k | case ARM_VEXTq64: |
12078 | 16.4k | case ARM_VEXTq8: |
12079 | 16.6k | case ARM_VLD3d16: |
12080 | 16.8k | case ARM_VLD3d32: |
12081 | 16.9k | case ARM_VLD3d8: |
12082 | 17.6k | case ARM_VLD3q16: |
12083 | 17.7k | case ARM_VLD3q32: |
12084 | 17.8k | case ARM_VLD3q8: |
12085 | 18.0k | case ARM_VMOVRRS: |
12086 | 18.7k | case ARM_VMOVSRR: |
12087 | 18.8k | case ARM_VST3d16: |
12088 | 18.9k | case ARM_VST3d32: |
12089 | 18.9k | case ARM_VST3d8: |
12090 | 19.0k | case ARM_VST3q16: |
12091 | 19.1k | case ARM_VST3q32: |
12092 | 19.1k | case ARM_VST3q8: |
12093 | 19.5k | case ARM_t2MLA: |
12094 | 19.6k | case ARM_t2MLS: |
12095 | 19.9k | case ARM_t2SBFX: |
12096 | 20.0k | case ARM_t2SMLABB: |
12097 | 20.1k | case ARM_t2SMLABT: |
12098 | 20.2k | case ARM_t2SMLAD: |
12099 | 20.2k | case ARM_t2SMLADX: |
12100 | 20.7k | case ARM_t2SMLAL: |
12101 | 20.7k | case ARM_t2SMLALBB: |
12102 | 20.8k | case ARM_t2SMLALBT: |
12103 | 20.9k | case ARM_t2SMLALD: |
12104 | 21.0k | case ARM_t2SMLALDX: |
12105 | 21.0k | case ARM_t2SMLALTB: |
12106 | 21.1k | case ARM_t2SMLALTT: |
12107 | 21.2k | case ARM_t2SMLATB: |
12108 | 21.3k | case ARM_t2SMLATT: |
12109 | 21.6k | case ARM_t2SMLAWB: |
12110 | 21.7k | case ARM_t2SMLAWT: |
12111 | 22.7k | case ARM_t2SMLSD: |
12112 | 22.7k | case ARM_t2SMLSDX: |
12113 | 22.8k | case ARM_t2SMLSLD: |
12114 | 22.9k | case ARM_t2SMLSLDX: |
12115 | 23.1k | case ARM_t2SMMLA: |
12116 | 23.2k | case ARM_t2SMMLAR: |
12117 | 23.5k | case ARM_t2SMMLS: |
12118 | 23.5k | case ARM_t2SMMLSR: |
12119 | 23.8k | case ARM_t2SMULL: |
12120 | 24.2k | case ARM_t2STLEXD: |
12121 | 24.3k | case ARM_t2STREXD: |
12122 | 24.4k | case ARM_t2UBFX: |
12123 | 24.4k | case ARM_t2UMAAL: |
12124 | 24.9k | case ARM_t2UMLAL: |
12125 | 25.0k | case ARM_t2UMULL: |
12126 | 25.2k | case ARM_t2USADA8: |
12127 | 25.2k | switch (MCInst_getOpcode(MI)) { |
12128 | 0 | default: |
12129 | 0 | assert(0 && "Unexpected opcode."); |
12130 | 0 | case ARM_CDE_CX3A: |
12131 | 0 | case ARM_CDE_VCX3A_vec: |
12132 | 0 | case ARM_MVE_VMLALDAVas16: |
12133 | 0 | case ARM_MVE_VMLALDAVas32: |
12134 | 0 | case ARM_MVE_VMLALDAVau16: |
12135 | 0 | case ARM_MVE_VMLALDAVau32: |
12136 | 68 | case ARM_MVE_VMLALDAVaxs16: |
12137 | 294 | case ARM_MVE_VMLALDAVaxs32: |
12138 | 404 | case ARM_MVE_VMLSLDAVas16: |
12139 | 508 | case ARM_MVE_VMLSLDAVas32: |
12140 | 562 | case ARM_MVE_VMLSLDAVaxs16: |
12141 | 1.12k | case ARM_MVE_VMLSLDAVaxs32: |
12142 | 1.12k | case ARM_MVE_VRMLALDAVHas32: |
12143 | 1.12k | case ARM_MVE_VRMLALDAVHau32: |
12144 | 1.27k | case ARM_MVE_VRMLALDAVHaxs32: |
12145 | 1.34k | case ARM_MVE_VRMLSLDAVHas32: |
12146 | 1.49k | case ARM_MVE_VRMLSLDAVHaxs32: |
12147 | 1.49k | printOperand(MI, 5, O); |
12148 | 1.49k | break; |
12149 | 0 | case ARM_CDE_VCX3_vec: |
12150 | 764 | case ARM_MVE_VDWDUPu16: |
12151 | 787 | case ARM_MVE_VDWDUPu32: |
12152 | 1.54k | case ARM_MVE_VDWDUPu8: |
12153 | 1.62k | case ARM_MVE_VIWDUPu16: |
12154 | 1.70k | case ARM_MVE_VIWDUPu32: |
12155 | 2.30k | case ARM_MVE_VIWDUPu8: |
12156 | 2.30k | printOperand(MI, 4, O); |
12157 | 2.30k | break; |
12158 | 815 | case ARM_LDRD_POST: |
12159 | 1.90k | case ARM_STRD_POST: |
12160 | 1.90k | printAddrMode3OffsetOperand(MI, 4, O); |
12161 | 1.90k | break; |
12162 | 502 | case ARM_MLA: |
12163 | 657 | case ARM_MLS: |
12164 | 657 | case ARM_MVE_VMLALDAVs16: |
12165 | 657 | case ARM_MVE_VMLALDAVs32: |
12166 | 657 | case ARM_MVE_VMLALDAVu16: |
12167 | 657 | case ARM_MVE_VMLALDAVu32: |
12168 | 704 | case ARM_MVE_VMLALDAVxs16: |
12169 | 789 | case ARM_MVE_VMLALDAVxs32: |
12170 | 998 | case ARM_MVE_VMLSLDAVs16: |
12171 | 1.12k | case ARM_MVE_VMLSLDAVs32: |
12172 | 1.21k | case ARM_MVE_VMLSLDAVxs16: |
12173 | 1.34k | case ARM_MVE_VMLSLDAVxs32: |
12174 | 1.34k | case ARM_MVE_VRMLALDAVHs32: |
12175 | 1.34k | case ARM_MVE_VRMLALDAVHu32: |
12176 | 1.39k | case ARM_MVE_VRMLALDAVHxs32: |
12177 | 1.47k | case ARM_MVE_VRMLSLDAVHs32: |
12178 | 1.66k | case ARM_MVE_VRMLSLDAVHxs32: |
12179 | 2.12k | case ARM_SMLABB: |
12180 | 2.26k | case ARM_SMLABT: |
12181 | 2.34k | case ARM_SMLAD: |
12182 | 2.45k | case ARM_SMLADX: |
12183 | 2.53k | case ARM_SMLALBB: |
12184 | 2.98k | case ARM_SMLALBT: |
12185 | 3.06k | case ARM_SMLALD: |
12186 | 3.26k | case ARM_SMLALDX: |
12187 | 3.31k | case ARM_SMLALTB: |
12188 | 3.56k | case ARM_SMLALTT: |
12189 | 3.62k | case ARM_SMLATB: |
12190 | 3.94k | case ARM_SMLATT: |
12191 | 4.04k | case ARM_SMLAWB: |
12192 | 4.13k | case ARM_SMLAWT: |
12193 | 4.17k | case ARM_SMLSD: |
12194 | 4.30k | case ARM_SMLSDX: |
12195 | 4.39k | case ARM_SMLSLD: |
12196 | 4.47k | case ARM_SMLSLDX: |
12197 | 4.52k | case ARM_SMMLA: |
12198 | 4.63k | case ARM_SMMLAR: |
12199 | 4.73k | case ARM_SMMLS: |
12200 | 4.77k | case ARM_SMMLSR: |
12201 | 4.85k | case ARM_SMULL: |
12202 | 5.28k | case ARM_UMAAL: |
12203 | 5.91k | case ARM_UMULL: |
12204 | 5.98k | case ARM_USADA8: |
12205 | 6.52k | case ARM_VEXTd16: |
12206 | 6.71k | case ARM_VEXTd32: |
12207 | 6.96k | case ARM_VEXTd8: |
12208 | 7.12k | case ARM_VEXTq16: |
12209 | 7.14k | case ARM_VEXTq32: |
12210 | 7.28k | case ARM_VEXTq64: |
12211 | 7.36k | case ARM_VEXTq8: |
12212 | 7.50k | case ARM_VMOVRRS: |
12213 | 8.24k | case ARM_VMOVSRR: |
12214 | 8.61k | case ARM_t2MLA: |
12215 | 8.70k | case ARM_t2MLS: |
12216 | 8.79k | case ARM_t2SMLABB: |
12217 | 8.91k | case ARM_t2SMLABT: |
12218 | 9.00k | case ARM_t2SMLAD: |
12219 | 9.04k | case ARM_t2SMLADX: |
12220 | 9.50k | case ARM_t2SMLAL: |
12221 | 9.54k | case ARM_t2SMLALBB: |
12222 | 9.58k | case ARM_t2SMLALBT: |
12223 | 9.74k | case ARM_t2SMLALD: |
12224 | 9.78k | case ARM_t2SMLALDX: |
12225 | 9.82k | case ARM_t2SMLALTB: |
12226 | 9.89k | case ARM_t2SMLALTT: |
12227 | 10.0k | case ARM_t2SMLATB: |
12228 | 10.1k | case ARM_t2SMLATT: |
12229 | 10.4k | case ARM_t2SMLAWB: |
12230 | 10.4k | case ARM_t2SMLAWT: |
12231 | 11.4k | case ARM_t2SMLSD: |
12232 | 11.5k | case ARM_t2SMLSDX: |
12233 | 11.6k | case ARM_t2SMLSLD: |
12234 | 11.6k | case ARM_t2SMLSLDX: |
12235 | 11.8k | case ARM_t2SMMLA: |
12236 | 11.9k | case ARM_t2SMMLAR: |
12237 | 12.2k | case ARM_t2SMMLS: |
12238 | 12.2k | case ARM_t2SMMLSR: |
12239 | 12.6k | case ARM_t2SMULL: |
12240 | 12.6k | case ARM_t2UMAAL: |
12241 | 13.1k | case ARM_t2UMLAL: |
12242 | 13.1k | case ARM_t2UMULL: |
12243 | 13.3k | case ARM_t2USADA8: |
12244 | 13.3k | printOperand(MI, 3, O); |
12245 | 13.3k | break; |
12246 | 515 | case ARM_MVE_VCADDf16: |
12247 | 630 | case ARM_MVE_VCADDf32: |
12248 | 802 | case ARM_MVE_VCADDi16: |
12249 | 1.10k | case ARM_MVE_VCADDi32: |
12250 | 1.30k | case ARM_MVE_VCADDi8: |
12251 | 1.91k | case ARM_MVE_VHCADDs16: |
12252 | 2.03k | case ARM_MVE_VHCADDs32: |
12253 | 2.26k | case ARM_MVE_VHCADDs8: |
12254 | 2.26k | printComplexRotationOp_180_90(MI, 3, O); |
12255 | 2.26k | break; |
12256 | 377 | case ARM_MVE_VCMLAf16: |
12257 | 510 | case ARM_MVE_VCMLAf32: |
12258 | 510 | printComplexRotationOp_90_0(MI, 4, O); |
12259 | 510 | break; |
12260 | 214 | case ARM_MVE_VCMULf16: |
12261 | 375 | case ARM_MVE_VCMULf32: |
12262 | 375 | printComplexRotationOp_90_0(MI, 3, O); |
12263 | 375 | break; |
12264 | 112 | case ARM_SBFX: |
12265 | 191 | case ARM_UBFX: |
12266 | 520 | case ARM_t2SBFX: |
12267 | 653 | case ARM_t2UBFX: |
12268 | 653 | printImmPlusOneOperand(MI, 3, O); |
12269 | 653 | break; |
12270 | 226 | case ARM_VLD3d16: |
12271 | 466 | case ARM_VLD3d32: |
12272 | 557 | case ARM_VLD3d8: |
12273 | 1.27k | case ARM_VLD3q16: |
12274 | 1.34k | case ARM_VLD3q32: |
12275 | 1.45k | case ARM_VLD3q8: |
12276 | 1.45k | printAddrMode6Operand(MI, 3, O); |
12277 | 1.45k | break; |
12278 | 79 | case ARM_VST3d16: |
12279 | 171 | case ARM_VST3d32: |
12280 | 241 | case ARM_VST3d8: |
12281 | 293 | case ARM_VST3q16: |
12282 | 374 | case ARM_VST3q32: |
12283 | 410 | case ARM_VST3q8: |
12284 | 410 | printAddrMode6Operand(MI, 0, O); |
12285 | 410 | break; |
12286 | 368 | case ARM_t2STLEXD: |
12287 | 498 | case ARM_t2STREXD: |
12288 | 498 | printAddrMode7Operand(MI, 3, O); |
12289 | 498 | break; |
12290 | 25.2k | } |
12291 | 25.2k | return; |
12292 | 25.2k | break; |
12293 | 25.2k | case ARM_MVE_VMOV_rr_q: |
12294 | 0 | SStream_concat0(O, ", "); |
12295 | 0 | printOperand(MI, 2, O); |
12296 | 0 | printVectorIndex(MI, 4, O); |
12297 | 0 | return; |
12298 | 0 | break; |
12299 | 232 | case ARM_VLD3d16_UPD: |
12300 | 314 | case ARM_VLD3d32_UPD: |
12301 | 571 | case ARM_VLD3d8_UPD: |
12302 | 658 | case ARM_VLD3q16_UPD: |
12303 | 717 | case ARM_VLD3q32_UPD: |
12304 | 871 | case ARM_VLD3q8_UPD: |
12305 | 871 | printAddrMode6Operand(MI, 4, O); |
12306 | 871 | printAddrMode6OffsetOperand(MI, 6, O); |
12307 | 871 | return; |
12308 | 0 | break; |
12309 | 626 | case ARM_VLD4LNd16: |
12310 | 711 | case ARM_VLD4LNd32: |
12311 | 941 | case ARM_VLD4LNd8: |
12312 | 1.02k | case ARM_VLD4LNq16: |
12313 | 1.16k | case ARM_VLD4LNq32: |
12314 | 1.16k | printNoHashImmediate(MI, 10, O); |
12315 | 1.16k | SStream_concat0(O, "]}, "); |
12316 | 1.16k | printAddrMode6Operand(MI, 4, O); |
12317 | 1.16k | return; |
12318 | 0 | break; |
12319 | 112 | case ARM_VLD4d16: |
12320 | 252 | case ARM_VLD4d32: |
12321 | 704 | case ARM_VLD4d8: |
12322 | 1.27k | case ARM_VLD4q16: |
12323 | 1.32k | case ARM_VLD4q32: |
12324 | 1.55k | case ARM_VLD4q8: |
12325 | 1.55k | printOperand(MI, 3, O); |
12326 | 1.55k | SStream_concat0(O, "}, "); |
12327 | 1.55k | printAddrMode6Operand(MI, 4, O); |
12328 | 1.55k | return; |
12329 | 0 | break; |
12330 | 494 | case ARM_VLD4d16_UPD: |
12331 | 1.31k | case ARM_VLD4d32_UPD: |
12332 | 1.89k | case ARM_VLD4d8_UPD: |
12333 | 2.27k | case ARM_VLD4q16_UPD: |
12334 | 2.46k | case ARM_VLD4q32_UPD: |
12335 | 2.80k | case ARM_VLD4q8_UPD: |
12336 | 2.80k | printOperand(MI, 3, O); |
12337 | 2.80k | SStream_concat0(O, "}, "); |
12338 | 2.80k | printAddrMode6Operand(MI, 5, O); |
12339 | 2.80k | printAddrMode6OffsetOperand(MI, 7, O); |
12340 | 2.80k | return; |
12341 | 0 | break; |
12342 | 86 | case ARM_VMULLslsv2i32: |
12343 | 182 | case ARM_VMULLslsv4i16: |
12344 | 247 | case ARM_VMULLsluv2i32: |
12345 | 282 | case ARM_VMULLsluv4i16: |
12346 | 394 | case ARM_VMULslfd: |
12347 | 577 | case ARM_VMULslfq: |
12348 | 708 | case ARM_VMULslhd: |
12349 | 805 | case ARM_VMULslhq: |
12350 | 1.15k | case ARM_VMULslv2i32: |
12351 | 1.33k | case ARM_VMULslv4i16: |
12352 | 1.44k | case ARM_VMULslv4i32: |
12353 | 1.66k | case ARM_VMULslv8i16: |
12354 | 1.78k | case ARM_VQDMULHslv2i32: |
12355 | 1.92k | case ARM_VQDMULHslv4i16: |
12356 | 1.95k | case ARM_VQDMULHslv4i32: |
12357 | 2.04k | case ARM_VQDMULHslv8i16: |
12358 | 2.08k | case ARM_VQDMULLslv2i32: |
12359 | 2.19k | case ARM_VQDMULLslv4i16: |
12360 | 2.27k | case ARM_VQRDMULHslv2i32: |
12361 | 2.31k | case ARM_VQRDMULHslv4i16: |
12362 | 2.51k | case ARM_VQRDMULHslv4i32: |
12363 | 2.57k | case ARM_VQRDMULHslv8i16: |
12364 | 2.57k | return; |
12365 | 0 | break; |
12366 | 199 | case ARM_VST2LNd16: |
12367 | 307 | case ARM_VST2LNd32: |
12368 | 439 | case ARM_VST2LNd8: |
12369 | 659 | case ARM_VST2LNq16: |
12370 | 781 | case ARM_VST2LNq32: |
12371 | 781 | printNoHashImmediate(MI, 4, O); |
12372 | 781 | SStream_concat0(O, "]}, "); |
12373 | 781 | printAddrMode6Operand(MI, 0, O); |
12374 | 781 | return; |
12375 | 0 | break; |
12376 | 121 | case ARM_VST2LNd16_UPD: |
12377 | 294 | case ARM_VST2LNd32_UPD: |
12378 | 619 | case ARM_VST2LNd8_UPD: |
12379 | 777 | case ARM_VST2LNq16_UPD: |
12380 | 846 | case ARM_VST2LNq32_UPD: |
12381 | 846 | printNoHashImmediate(MI, 6, O); |
12382 | 846 | SStream_concat0(O, "]}, "); |
12383 | 846 | printAddrMode6Operand(MI, 1, O); |
12384 | 846 | printAddrMode6OffsetOperand(MI, 3, O); |
12385 | 846 | return; |
12386 | 0 | break; |
12387 | 185 | case ARM_VST3LNd16: |
12388 | 393 | case ARM_VST3LNd32: |
12389 | 534 | case ARM_VST3LNd8: |
12390 | 570 | case ARM_VST3LNq16: |
12391 | 648 | case ARM_VST3LNq32: |
12392 | 648 | printNoHashImmediate(MI, 5, O); |
12393 | 648 | SStream_concat0(O, "], "); |
12394 | 648 | printOperand(MI, 4, O); |
12395 | 648 | SStream_concat1(O, '['); |
12396 | 648 | printNoHashImmediate(MI, 5, O); |
12397 | 648 | SStream_concat0(O, "]}, "); |
12398 | 648 | printAddrMode6Operand(MI, 0, O); |
12399 | 648 | return; |
12400 | 0 | break; |
12401 | 499 | case ARM_VST4LNd16: |
12402 | 546 | case ARM_VST4LNd32: |
12403 | 696 | case ARM_VST4LNd8: |
12404 | 950 | case ARM_VST4LNq16: |
12405 | 984 | case ARM_VST4LNq32: |
12406 | 984 | printNoHashImmediate(MI, 6, O); |
12407 | 984 | SStream_concat0(O, "], "); |
12408 | 984 | printOperand(MI, 4, O); |
12409 | 984 | SStream_concat1(O, '['); |
12410 | 984 | printNoHashImmediate(MI, 6, O); |
12411 | 984 | SStream_concat0(O, "], "); |
12412 | 984 | printOperand(MI, 5, O); |
12413 | 984 | SStream_concat1(O, '['); |
12414 | 984 | printNoHashImmediate(MI, 6, O); |
12415 | 984 | SStream_concat0(O, "]}, "); |
12416 | 984 | printAddrMode6Operand(MI, 0, O); |
12417 | 984 | return; |
12418 | 0 | break; |
12419 | 85 | case ARM_VST4d16: |
12420 | 180 | case ARM_VST4d32: |
12421 | 383 | case ARM_VST4d8: |
12422 | 958 | case ARM_VST4q16: |
12423 | 1.04k | case ARM_VST4q32: |
12424 | 1.20k | case ARM_VST4q8: |
12425 | 1.20k | printOperand(MI, 5, O); |
12426 | 1.20k | SStream_concat0(O, "}, "); |
12427 | 1.20k | printAddrMode6Operand(MI, 0, O); |
12428 | 1.20k | return; |
12429 | 0 | break; |
12430 | 38.6k | } |
12431 | 38.6k | } |
12432 | | |
12433 | | /// getRegisterName - This method is automatically generated by tblgen |
12434 | | /// from the register set description. This returns the assembler name |
12435 | | /// for the specified register. |
12436 | | const char *getRegisterName(unsigned RegNo, unsigned AltIdx) |
12437 | 4.72M | { |
12438 | 4.72M | #ifndef CAPSTONE_DIET |
12439 | 4.72M | assert(RegNo && RegNo < 296 && "Invalid register number!"); |
12440 | | |
12441 | 4.72M | static const char AsmStrsNoRegAltName[] = { |
12442 | 4.72M | /* 0 */ "D4_D6_D8_D10\0" |
12443 | 4.72M | /* 13 */ "D7_D8_D9_D10\0" |
12444 | 4.72M | /* 26 */ "Q7_Q8_Q9_Q10\0" |
12445 | 4.72M | /* 39 */ "d10\0" |
12446 | 4.72M | /* 43 */ "q10\0" |
12447 | 4.72M | /* 47 */ "r10\0" |
12448 | 4.72M | /* 51 */ "s10\0" |
12449 | 4.72M | /* 55 */ "D14_D16_D18_D20\0" |
12450 | 4.72M | /* 71 */ "D17_D18_D19_D20\0" |
12451 | 4.72M | /* 87 */ "d20\0" |
12452 | 4.72M | /* 91 */ "s20\0" |
12453 | 4.72M | /* 95 */ "D24_D26_D28_D30\0" |
12454 | 4.72M | /* 111 */ "D27_D28_D29_D30\0" |
12455 | 4.72M | /* 127 */ "d30\0" |
12456 | 4.72M | /* 131 */ "s30\0" |
12457 | 4.72M | /* 135 */ "d0\0" |
12458 | 4.72M | /* 138 */ "p0\0" |
12459 | 4.72M | /* 141 */ "q0\0" |
12460 | 4.72M | /* 144 */ "mvfr0\0" |
12461 | 4.72M | /* 150 */ "s0\0" |
12462 | 4.72M | /* 153 */ "D9_D10_D11\0" |
12463 | 4.72M | /* 164 */ "D5_D7_D9_D11\0" |
12464 | 4.72M | /* 177 */ "Q8_Q9_Q10_Q11\0" |
12465 | 4.72M | /* 191 */ "R10_R11\0" |
12466 | 4.72M | /* 199 */ "d11\0" |
12467 | 4.72M | /* 203 */ "q11\0" |
12468 | 4.72M | /* 207 */ "r11\0" |
12469 | 4.72M | /* 211 */ "s11\0" |
12470 | 4.72M | /* 215 */ "D19_D20_D21\0" |
12471 | 4.72M | /* 227 */ "D15_D17_D19_D21\0" |
12472 | 4.72M | /* 243 */ "d21\0" |
12473 | 4.72M | /* 247 */ "s21\0" |
12474 | 4.72M | /* 251 */ "D29_D30_D31\0" |
12475 | 4.72M | /* 263 */ "D25_D27_D29_D31\0" |
12476 | 4.72M | /* 279 */ "d31\0" |
12477 | 4.72M | /* 283 */ "s31\0" |
12478 | 4.72M | /* 287 */ "Q0_Q1\0" |
12479 | 4.72M | /* 293 */ "R0_R1\0" |
12480 | 4.72M | /* 299 */ "d1\0" |
12481 | 4.72M | /* 302 */ "q1\0" |
12482 | 4.72M | /* 305 */ "mvfr1\0" |
12483 | 4.72M | /* 311 */ "s1\0" |
12484 | 4.72M | /* 314 */ "D6_D8_D10_D12\0" |
12485 | 4.72M | /* 328 */ "D9_D10_D11_D12\0" |
12486 | 4.72M | /* 343 */ "Q9_Q10_Q11_Q12\0" |
12487 | 4.72M | /* 358 */ "d12\0" |
12488 | 4.72M | /* 362 */ "q12\0" |
12489 | 4.72M | /* 366 */ "r12\0" |
12490 | 4.72M | /* 370 */ "s12\0" |
12491 | 4.72M | /* 374 */ "D16_D18_D20_D22\0" |
12492 | 4.72M | /* 390 */ "D19_D20_D21_D22\0" |
12493 | 4.72M | /* 406 */ "d22\0" |
12494 | 4.72M | /* 410 */ "s22\0" |
12495 | 4.72M | /* 414 */ "D0_D2\0" |
12496 | 4.72M | /* 420 */ "D0_D1_D2\0" |
12497 | 4.72M | /* 429 */ "Q1_Q2\0" |
12498 | 4.72M | /* 435 */ "d2\0" |
12499 | 4.72M | /* 438 */ "q2\0" |
12500 | 4.72M | /* 441 */ "mvfr2\0" |
12501 | 4.72M | /* 447 */ "s2\0" |
12502 | 4.72M | /* 450 */ "fpinst2\0" |
12503 | 4.72M | /* 458 */ "D7_D9_D11_D13\0" |
12504 | 4.72M | /* 472 */ "D11_D12_D13\0" |
12505 | 4.72M | /* 484 */ "Q10_Q11_Q12_Q13\0" |
12506 | 4.72M | /* 500 */ "d13\0" |
12507 | 4.72M | /* 504 */ "q13\0" |
12508 | 4.72M | /* 508 */ "s13\0" |
12509 | 4.72M | /* 512 */ "D17_D19_D21_D23\0" |
12510 | 4.72M | /* 528 */ "D21_D22_D23\0" |
12511 | 4.72M | /* 540 */ "d23\0" |
12512 | 4.72M | /* 544 */ "s23\0" |
12513 | 4.72M | /* 548 */ "D1_D3\0" |
12514 | 4.72M | /* 554 */ "D1_D2_D3\0" |
12515 | 4.72M | /* 563 */ "Q0_Q1_Q2_Q3\0" |
12516 | 4.72M | /* 575 */ "R2_R3\0" |
12517 | 4.72M | /* 581 */ "d3\0" |
12518 | 4.72M | /* 584 */ "q3\0" |
12519 | 4.72M | /* 587 */ "r3\0" |
12520 | 4.72M | /* 590 */ "s3\0" |
12521 | 4.72M | /* 593 */ "D8_D10_D12_D14\0" |
12522 | 4.72M | /* 608 */ "D11_D12_D13_D14\0" |
12523 | 4.72M | /* 624 */ "Q11_Q12_Q13_Q14\0" |
12524 | 4.72M | /* 640 */ "d14\0" |
12525 | 4.72M | /* 644 */ "q14\0" |
12526 | 4.72M | /* 648 */ "s14\0" |
12527 | 4.72M | /* 652 */ "D18_D20_D22_D24\0" |
12528 | 4.72M | /* 668 */ "D21_D22_D23_D24\0" |
12529 | 4.72M | /* 684 */ "d24\0" |
12530 | 4.72M | /* 688 */ "s24\0" |
12531 | 4.72M | /* 692 */ "D0_D2_D4\0" |
12532 | 4.72M | /* 701 */ "D1_D2_D3_D4\0" |
12533 | 4.72M | /* 713 */ "Q1_Q2_Q3_Q4\0" |
12534 | 4.72M | /* 725 */ "d4\0" |
12535 | 4.72M | /* 728 */ "q4\0" |
12536 | 4.72M | /* 731 */ "r4\0" |
12537 | 4.72M | /* 734 */ "s4\0" |
12538 | 4.72M | /* 737 */ "D9_D11_D13_D15\0" |
12539 | 4.72M | /* 752 */ "D13_D14_D15\0" |
12540 | 4.72M | /* 764 */ "Q12_Q13_Q14_Q15\0" |
12541 | 4.72M | /* 780 */ "d15\0" |
12542 | 4.72M | /* 784 */ "q15\0" |
12543 | 4.72M | /* 788 */ "s15\0" |
12544 | 4.72M | /* 792 */ "D19_D21_D23_D25\0" |
12545 | 4.72M | /* 808 */ "D23_D24_D25\0" |
12546 | 4.72M | /* 820 */ "d25\0" |
12547 | 4.72M | /* 824 */ "s25\0" |
12548 | 4.72M | /* 828 */ "D1_D3_D5\0" |
12549 | 4.72M | /* 837 */ "D3_D4_D5\0" |
12550 | 4.72M | /* 846 */ "Q2_Q3_Q4_Q5\0" |
12551 | 4.72M | /* 858 */ "R4_R5\0" |
12552 | 4.72M | /* 864 */ "d5\0" |
12553 | 4.72M | /* 867 */ "q5\0" |
12554 | 4.72M | /* 870 */ "r5\0" |
12555 | 4.72M | /* 873 */ "s5\0" |
12556 | 4.72M | /* 876 */ "D10_D12_D14_D16\0" |
12557 | 4.72M | /* 892 */ "D13_D14_D15_D16\0" |
12558 | 4.72M | /* 908 */ "d16\0" |
12559 | 4.72M | /* 912 */ "s16\0" |
12560 | 4.72M | /* 916 */ "D20_D22_D24_D26\0" |
12561 | 4.72M | /* 932 */ "D23_D24_D25_D26\0" |
12562 | 4.72M | /* 948 */ "d26\0" |
12563 | 4.72M | /* 952 */ "s26\0" |
12564 | 4.72M | /* 956 */ "D0_D2_D4_D6\0" |
12565 | 4.72M | /* 968 */ "D3_D4_D5_D6\0" |
12566 | 4.72M | /* 980 */ "Q3_Q4_Q5_Q6\0" |
12567 | 4.72M | /* 992 */ "d6\0" |
12568 | 4.72M | /* 995 */ "q6\0" |
12569 | 4.72M | /* 998 */ "r6\0" |
12570 | 4.72M | /* 1001 */ "s6\0" |
12571 | 4.72M | /* 1004 */ "D11_D13_D15_D17\0" |
12572 | 4.72M | /* 1020 */ "D15_D16_D17\0" |
12573 | 4.72M | /* 1032 */ "d17\0" |
12574 | 4.72M | /* 1036 */ "s17\0" |
12575 | 4.72M | /* 1040 */ "D21_D23_D25_D27\0" |
12576 | 4.72M | /* 1056 */ "D25_D26_D27\0" |
12577 | 4.72M | /* 1068 */ "d27\0" |
12578 | 4.72M | /* 1072 */ "s27\0" |
12579 | 4.72M | /* 1076 */ "D1_D3_D5_D7\0" |
12580 | 4.72M | /* 1088 */ "D5_D6_D7\0" |
12581 | 4.72M | /* 1097 */ "Q4_Q5_Q6_Q7\0" |
12582 | 4.72M | /* 1109 */ "R6_R7\0" |
12583 | 4.72M | /* 1115 */ "d7\0" |
12584 | 4.72M | /* 1118 */ "q7\0" |
12585 | 4.72M | /* 1121 */ "r7\0" |
12586 | 4.72M | /* 1124 */ "s7\0" |
12587 | 4.72M | /* 1127 */ "D12_D14_D16_D18\0" |
12588 | 4.72M | /* 1143 */ "D15_D16_D17_D18\0" |
12589 | 4.72M | /* 1159 */ "d18\0" |
12590 | 4.72M | /* 1163 */ "s18\0" |
12591 | 4.72M | /* 1167 */ "D22_D24_D26_D28\0" |
12592 | 4.72M | /* 1183 */ "D25_D26_D27_D28\0" |
12593 | 4.72M | /* 1199 */ "d28\0" |
12594 | 4.72M | /* 1203 */ "s28\0" |
12595 | 4.72M | /* 1207 */ "D2_D4_D6_D8\0" |
12596 | 4.72M | /* 1219 */ "D5_D6_D7_D8\0" |
12597 | 4.72M | /* 1231 */ "Q5_Q6_Q7_Q8\0" |
12598 | 4.72M | /* 1243 */ "d8\0" |
12599 | 4.72M | /* 1246 */ "q8\0" |
12600 | 4.72M | /* 1249 */ "r8\0" |
12601 | 4.72M | /* 1252 */ "s8\0" |
12602 | 4.72M | /* 1255 */ "D13_D15_D17_D19\0" |
12603 | 4.72M | /* 1271 */ "D17_D18_D19\0" |
12604 | 4.72M | /* 1283 */ "d19\0" |
12605 | 4.72M | /* 1287 */ "s19\0" |
12606 | 4.72M | /* 1291 */ "D23_D25_D27_D29\0" |
12607 | 4.72M | /* 1307 */ "D27_D28_D29\0" |
12608 | 4.72M | /* 1319 */ "d29\0" |
12609 | 4.72M | /* 1323 */ "s29\0" |
12610 | 4.72M | /* 1327 */ "D3_D5_D7_D9\0" |
12611 | 4.72M | /* 1339 */ "D7_D8_D9\0" |
12612 | 4.72M | /* 1348 */ "Q6_Q7_Q8_Q9\0" |
12613 | 4.72M | /* 1360 */ "R8_R9\0" |
12614 | 4.72M | /* 1366 */ "d9\0" |
12615 | 4.72M | /* 1369 */ "q9\0" |
12616 | 4.72M | /* 1372 */ "r9\0" |
12617 | 4.72M | /* 1375 */ "s9\0" |
12618 | 4.72M | /* 1378 */ "R12_SP\0" |
12619 | 4.72M | /* 1385 */ "pc\0" |
12620 | 4.72M | /* 1388 */ "fpscr_nzcvqc\0" |
12621 | 4.72M | /* 1401 */ "fpexc\0" |
12622 | 4.72M | /* 1407 */ "fpsid\0" |
12623 | 4.72M | /* 1413 */ "ra_auth_code\0" |
12624 | 4.72M | /* 1426 */ "itstate\0" |
12625 | 4.72M | /* 1434 */ "sp\0" |
12626 | 4.72M | /* 1437 */ "fpscr\0" |
12627 | 4.72M | /* 1443 */ "lr\0" |
12628 | 4.72M | /* 1446 */ "vpr\0" |
12629 | 4.72M | /* 1450 */ "apsr\0" |
12630 | 4.72M | /* 1455 */ "cpsr\0" |
12631 | 4.72M | /* 1460 */ "spsr\0" |
12632 | 4.72M | /* 1465 */ "zr\0" |
12633 | 4.72M | /* 1468 */ "fpcxtns\0" |
12634 | 4.72M | /* 1476 */ "fpcxts\0" |
12635 | 4.72M | /* 1483 */ "fpinst\0" |
12636 | 4.72M | /* 1490 */ "fpscr_nzcv\0" |
12637 | 4.72M | /* 1501 */ "apsr_nzcv\0" |
12638 | 4.72M | }; |
12639 | 4.72M | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
12640 | 4.72M | 1450, 1501, 1455, 1468, 1476, 1401, 1483, 1437, 1490, 1388, |
12641 | 4.72M | 1407, 1426, 1443, 1385, 1413, 1434, 1460, 1446, 1465, 135, |
12642 | 4.72M | 299, 435, 581, 725, 864, 992, 1115, 1243, 1366, 39, |
12643 | 4.72M | 199, 358, 500, 640, 780, 908, 1032, 1159, 1283, 87, |
12644 | 4.72M | 243, 406, 540, 684, 820, 948, 1068, 1199, 1319, 127, |
12645 | 4.72M | 279, 450, 144, 305, 441, 138, 141, 302, 438, 584, |
12646 | 4.72M | 728, 867, 995, 1118, 1246, 1369, 43, 203, 362, 504, |
12647 | 4.72M | 644, 784, 147, 308, 444, 587, 731, 870, 998, 1121, |
12648 | 4.72M | 1249, 1372, 47, 207, 366, 150, 311, 447, 590, 734, |
12649 | 4.72M | 873, 1001, 1124, 1252, 1375, 51, 211, 370, 508, 648, |
12650 | 4.72M | 788, 912, 1036, 1163, 1287, 91, 247, 410, 544, 688, |
12651 | 4.72M | 824, 952, 1072, 1203, 1323, 131, 283, 414, 548, 695, |
12652 | 4.72M | 831, 962, 1082, 1213, 1333, 6, 170, 320, 464, 600, |
12653 | 4.72M | 744, 884, 1012, 1135, 1263, 63, 235, 382, 520, 660, |
12654 | 4.72M | 800, 924, 1048, 1175, 1299, 103, 271, 287, 429, 569, |
12655 | 4.72M | 719, 852, 986, 1103, 1237, 1354, 32, 183, 350, 492, |
12656 | 4.72M | 632, 772, 563, 713, 846, 980, 1097, 1231, 1348, 26, |
12657 | 4.72M | 177, 343, 484, 624, 764, 293, 575, 858, 1109, 1360, |
12658 | 4.72M | 191, 1378, 420, 554, 704, 837, 971, 1088, 1222, 1339, |
12659 | 4.72M | 16, 153, 331, 472, 612, 752, 896, 1020, 1147, 1271, |
12660 | 4.72M | 75, 215, 394, 528, 672, 808, 936, 1056, 1187, 1307, |
12661 | 4.72M | 115, 251, 692, 828, 959, 1079, 1210, 1330, 3, 167, |
12662 | 4.72M | 317, 461, 596, 740, 880, 1008, 1131, 1259, 59, 231, |
12663 | 4.72M | 378, 516, 656, 796, 920, 1044, 1171, 1295, 99, 267, |
12664 | 4.72M | 956, 1076, 1207, 1327, 0, 164, 314, 458, 593, 737, |
12665 | 4.72M | 876, 1004, 1127, 1255, 55, 227, 374, 512, 652, 792, |
12666 | 4.72M | 916, 1040, 1167, 1291, 95, 263, 423, 707, 974, 1225, |
12667 | 4.72M | 19, 335, 616, 900, 1151, 79, 398, 676, 940, 1191, |
12668 | 4.72M | 119, 701, 968, 1219, 13, 328, 608, 892, 1143, 71, |
12669 | 4.72M | 390, 668, 932, 1183, 111, |
12670 | 4.72M | }; |
12671 | | |
12672 | 4.72M | static const char AsmStrsRegNamesRaw[] = { /* 0 */ "r13\0" |
12673 | 4.72M | /* 4 */ "r14\0" |
12674 | 4.72M | /* 8 */ "r15\0" }; |
12675 | 4.72M | static const uint8_t RegAsmOffsetRegNamesRaw[] = { |
12676 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 8, 3, 0, 3, 3, 3, 3, |
12677 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12678 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12679 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12680 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12681 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12682 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12683 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12684 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12685 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12686 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12687 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12688 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12689 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12690 | 4.72M | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
12691 | 4.72M | }; |
12692 | | |
12693 | 4.72M | switch (AltIdx) { |
12694 | 0 | default: |
12695 | 0 | assert(0 && "Invalid register alt name index!"); |
12696 | 3.77M | case ARM_NoRegAltName: |
12697 | 3.77M | assert(*(AsmStrsNoRegAltName + |
12698 | 3.77M | RegAsmOffsetNoRegAltName[RegNo - 1]) && |
12699 | 3.77M | "Invalid alt name index for register!"); |
12700 | 3.77M | return AsmStrsNoRegAltName + |
12701 | 3.77M | RegAsmOffsetNoRegAltName[RegNo - 1]; |
12702 | 952k | case ARM_RegNamesRaw: |
12703 | 952k | if (!*(AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1])) |
12704 | 872k | return getRegisterName(RegNo, ARM_NoRegAltName); |
12705 | 80.2k | return AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1]; |
12706 | 4.72M | } |
12707 | | #else |
12708 | | return NULL; |
12709 | | #endif // CAPSTONE_DIET |
12710 | 4.72M | } |
12711 | | #ifdef PRINT_ALIAS_INSTR |
12712 | | #undef PRINT_ALIAS_INSTR |
12713 | | |
12714 | | static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) |
12715 | 1.45M | { |
12716 | 1.45M | #ifndef CAPSTONE_DIET |
12717 | 1.45M | static const PatternsForOpcode OpToPatterns[] = { |
12718 | 1.45M | { ARM_DSB, 0, 3 }, |
12719 | 1.45M | { ARM_HINT, 3, 9 }, |
12720 | 1.45M | { ARM_MVE_VMLADAVas16, 12, 1 }, |
12721 | 1.45M | { ARM_MVE_VMLADAVas32, 13, 1 }, |
12722 | 1.45M | { ARM_MVE_VMLADAVas8, 14, 1 }, |
12723 | 1.45M | { ARM_MVE_VMLADAVau16, 15, 1 }, |
12724 | 1.45M | { ARM_MVE_VMLADAVau32, 16, 1 }, |
12725 | 1.45M | { ARM_MVE_VMLADAVau8, 17, 1 }, |
12726 | 1.45M | { ARM_MVE_VMLADAVs16, 18, 1 }, |
12727 | 1.45M | { ARM_MVE_VMLADAVs32, 19, 1 }, |
12728 | 1.45M | { ARM_MVE_VMLADAVs8, 20, 1 }, |
12729 | 1.45M | { ARM_MVE_VMLADAVu16, 21, 1 }, |
12730 | 1.45M | { ARM_MVE_VMLADAVu32, 22, 1 }, |
12731 | 1.45M | { ARM_MVE_VMLADAVu8, 23, 1 }, |
12732 | 1.45M | { ARM_MVE_VMLALDAVas16, 24, 1 }, |
12733 | 1.45M | { ARM_MVE_VMLALDAVas32, 25, 1 }, |
12734 | 1.45M | { ARM_MVE_VMLALDAVau16, 26, 1 }, |
12735 | 1.45M | { ARM_MVE_VMLALDAVau32, 27, 1 }, |
12736 | 1.45M | { ARM_MVE_VMLALDAVs16, 28, 1 }, |
12737 | 1.45M | { ARM_MVE_VMLALDAVs32, 29, 1 }, |
12738 | 1.45M | { ARM_MVE_VMLALDAVu16, 30, 1 }, |
12739 | 1.45M | { ARM_MVE_VMLALDAVu32, 31, 1 }, |
12740 | 1.45M | { ARM_MVE_VORR, 32, 1 }, |
12741 | 1.45M | { ARM_MVE_VRMLALDAVHas32, 33, 1 }, |
12742 | 1.45M | { ARM_MVE_VRMLALDAVHau32, 34, 1 }, |
12743 | 1.45M | { ARM_MVE_VRMLALDAVHs32, 35, 1 }, |
12744 | 1.45M | { ARM_MVE_VRMLALDAVHu32, 36, 1 }, |
12745 | 1.45M | { ARM_t2CSINC, 37, 2 }, |
12746 | 1.45M | { ARM_t2CSINV, 39, 2 }, |
12747 | 1.45M | { ARM_t2CSNEG, 41, 1 }, |
12748 | 1.45M | { ARM_t2DSB, 42, 3 }, |
12749 | 1.45M | { ARM_t2HINT, 45, 13 }, |
12750 | 1.45M | { ARM_t2SUBS_PC_LR, 58, 1 }, |
12751 | 1.45M | { ARM_tHINT, 59, 6 }, |
12752 | 1.45M | { 0 }, |
12753 | 1.45M | }; |
12754 | | |
12755 | 1.45M | static const AliasPattern Patterns[] = { |
12756 | | // ARM_DSB - 0 |
12757 | 1.45M | { 0, 0, 1, 3 }, |
12758 | 1.45M | { 5, 3, 1, 3 }, |
12759 | 1.45M | { 11, 6, 1, 3 }, |
12760 | | // ARM_HINT - 3 |
12761 | 1.45M | { 15, 9, 3, 3 }, |
12762 | 1.45M | { 23, 12, 3, 3 }, |
12763 | 1.45M | { 33, 15, 3, 3 }, |
12764 | 1.45M | { 41, 18, 3, 3 }, |
12765 | 1.45M | { 49, 21, 3, 3 }, |
12766 | 1.45M | { 57, 24, 3, 3 }, |
12767 | 1.45M | { 66, 27, 3, 3 }, |
12768 | 1.45M | { 74, 30, 3, 3 }, |
12769 | 1.45M | { 83, 33, 3, 4 }, |
12770 | | // ARM_MVE_VMLADAVas16 - 12 |
12771 | 1.45M | { 94, 37, 7, 6 }, |
12772 | | // ARM_MVE_VMLADAVas32 - 13 |
12773 | 1.45M | { 120, 43, 7, 6 }, |
12774 | | // ARM_MVE_VMLADAVas8 - 14 |
12775 | 1.45M | { 146, 49, 7, 6 }, |
12776 | | // ARM_MVE_VMLADAVau16 - 15 |
12777 | 1.45M | { 171, 55, 7, 6 }, |
12778 | | // ARM_MVE_VMLADAVau32 - 16 |
12779 | 1.45M | { 197, 61, 7, 6 }, |
12780 | | // ARM_MVE_VMLADAVau8 - 17 |
12781 | 1.45M | { 223, 67, 7, 6 }, |
12782 | | // ARM_MVE_VMLADAVs16 - 18 |
12783 | 1.45M | { 248, 73, 6, 5 }, |
12784 | | // ARM_MVE_VMLADAVs32 - 19 |
12785 | 1.45M | { 273, 78, 6, 5 }, |
12786 | | // ARM_MVE_VMLADAVs8 - 20 |
12787 | 1.45M | { 298, 83, 6, 5 }, |
12788 | | // ARM_MVE_VMLADAVu16 - 21 |
12789 | 1.45M | { 322, 88, 6, 5 }, |
12790 | | // ARM_MVE_VMLADAVu32 - 22 |
12791 | 1.45M | { 347, 93, 6, 5 }, |
12792 | | // ARM_MVE_VMLADAVu8 - 23 |
12793 | 1.45M | { 372, 98, 6, 5 }, |
12794 | | // ARM_MVE_VMLALDAVas16 - 24 |
12795 | 1.45M | { 396, 103, 9, 8 }, |
12796 | | // ARM_MVE_VMLALDAVas32 - 25 |
12797 | 1.45M | { 427, 111, 9, 8 }, |
12798 | | // ARM_MVE_VMLALDAVau16 - 26 |
12799 | 1.45M | { 458, 119, 9, 8 }, |
12800 | | // ARM_MVE_VMLALDAVau32 - 27 |
12801 | 1.45M | { 489, 127, 9, 8 }, |
12802 | | // ARM_MVE_VMLALDAVs16 - 28 |
12803 | 1.45M | { 520, 135, 7, 6 }, |
12804 | | // ARM_MVE_VMLALDAVs32 - 29 |
12805 | 1.45M | { 550, 141, 7, 6 }, |
12806 | | // ARM_MVE_VMLALDAVu16 - 30 |
12807 | 1.45M | { 580, 147, 7, 6 }, |
12808 | | // ARM_MVE_VMLALDAVu32 - 31 |
12809 | 1.45M | { 610, 153, 7, 6 }, |
12810 | | // ARM_MVE_VORR - 32 |
12811 | 1.45M | { 640, 159, 7, 5 }, |
12812 | | // ARM_MVE_VRMLALDAVHas32 - 33 |
12813 | 1.45M | { 656, 164, 9, 8 }, |
12814 | | // ARM_MVE_VRMLALDAVHau32 - 34 |
12815 | 1.45M | { 689, 172, 9, 8 }, |
12816 | | // ARM_MVE_VRMLALDAVHs32 - 35 |
12817 | 1.45M | { 722, 180, 7, 6 }, |
12818 | | // ARM_MVE_VRMLALDAVHu32 - 36 |
12819 | 1.45M | { 754, 186, 7, 6 }, |
12820 | | // ARM_t2CSINC - 37 |
12821 | 1.45M | { 786, 192, 4, 4 }, |
12822 | 1.45M | { 800, 196, 4, 4 }, |
12823 | | // ARM_t2CSINV - 39 |
12824 | 1.45M | { 818, 200, 4, 4 }, |
12825 | 1.45M | { 833, 204, 4, 4 }, |
12826 | | // ARM_t2CSNEG - 41 |
12827 | 1.45M | { 851, 208, 4, 4 }, |
12828 | | // ARM_t2DSB - 42 |
12829 | 1.45M | { 0, 212, 3, 6 }, |
12830 | 1.45M | { 5, 218, 3, 6 }, |
12831 | 1.45M | { 869, 224, 3, 2 }, |
12832 | | // ARM_t2HINT - 45 |
12833 | 1.45M | { 877, 226, 3, 3 }, |
12834 | 1.45M | { 887, 229, 3, 3 }, |
12835 | 1.45M | { 899, 232, 3, 3 }, |
12836 | 1.45M | { 909, 235, 3, 3 }, |
12837 | 1.45M | { 919, 238, 3, 3 }, |
12838 | 1.45M | { 929, 241, 3, 4 }, |
12839 | 1.45M | { 940, 245, 3, 4 }, |
12840 | 1.45M | { 74, 249, 3, 3 }, |
12841 | 1.45M | { 950, 252, 3, 3 }, |
12842 | 1.45M | { 971, 255, 3, 3 }, |
12843 | 1.45M | { 979, 258, 3, 3 }, |
12844 | 1.45M | { 997, 261, 3, 3 }, |
12845 | 1.45M | { 83, 264, 3, 5 }, |
12846 | | // ARM_t2SUBS_PC_LR - 58 |
12847 | 1.45M | { 1015, 269, 3, 4 }, |
12848 | | // ARM_tHINT - 59 |
12849 | 1.45M | { 15, 273, 3, 3 }, |
12850 | 1.45M | { 23, 276, 3, 3 }, |
12851 | 1.45M | { 33, 279, 3, 3 }, |
12852 | 1.45M | { 41, 282, 3, 3 }, |
12853 | 1.45M | { 49, 285, 3, 3 }, |
12854 | 1.45M | { 57, 288, 3, 4 }, |
12855 | 1.45M | { 0 }, |
12856 | 1.45M | }; |
12857 | | |
12858 | 1.45M | static const AliasPatternCond Conds[] = { |
12859 | | // (DSB 0) - 0 |
12860 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
12861 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12862 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDB }, |
12863 | | // (DSB 4) - 3 |
12864 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)4 }, |
12865 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12866 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDB }, |
12867 | | // (DSB 12) - 6 |
12868 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)12 }, |
12869 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12870 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDFB }, |
12871 | | // (HINT 0, pred:$p) - 9 |
12872 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
12873 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12874 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12875 | | // (HINT 1, pred:$p) - 12 |
12876 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)1 }, |
12877 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12878 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12879 | | // (HINT 2, pred:$p) - 15 |
12880 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)2 }, |
12881 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12882 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12883 | | // (HINT 3, pred:$p) - 18 |
12884 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)3 }, |
12885 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12886 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12887 | | // (HINT 4, pred:$p) - 21 |
12888 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)4 }, |
12889 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12890 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12891 | | // (HINT 5, pred:$p) - 24 |
12892 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)5 }, |
12893 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12894 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8Ops }, |
12895 | | // (HINT 16, pred:$p) - 27 |
12896 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)16 }, |
12897 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12898 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureRAS }, |
12899 | | // (HINT 20, pred:$p) - 30 |
12900 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)20 }, |
12901 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12902 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6KOps }, |
12903 | | // (HINT 22, pred:$p) - 33 |
12904 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)22 }, |
12905 | 1.45M | { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, |
12906 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8Ops }, |
12907 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureCLRBHB }, |
12908 | | // (MVE_VMLADAVas16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 37 |
12909 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12910 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12911 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12912 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12913 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12914 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12915 | | // (MVE_VMLADAVas32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 43 |
12916 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12917 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12918 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12919 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12920 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12921 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12922 | | // (MVE_VMLADAVas8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 49 |
12923 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12924 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12925 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12926 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12927 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12928 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12929 | | // (MVE_VMLADAVau16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 55 |
12930 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12931 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12932 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12933 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12934 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12935 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12936 | | // (MVE_VMLADAVau32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 61 |
12937 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12938 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12939 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12940 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12941 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12942 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12943 | | // (MVE_VMLADAVau8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 67 |
12944 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12945 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12946 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12947 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12948 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12949 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12950 | | // (MVE_VMLADAVs16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 73 |
12951 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12952 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12953 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12954 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12955 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12956 | | // (MVE_VMLADAVs32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 78 |
12957 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12958 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12959 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12960 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12961 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12962 | | // (MVE_VMLADAVs8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 83 |
12963 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12964 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12965 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12966 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12967 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12968 | | // (MVE_VMLADAVu16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 88 |
12969 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12970 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12971 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12972 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12973 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12974 | | // (MVE_VMLADAVu32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 93 |
12975 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12976 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12977 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12978 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12979 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12980 | | // (MVE_VMLADAVu8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 98 |
12981 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12982 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12983 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12984 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12985 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12986 | | // (MVE_VMLALDAVas16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 103 |
12987 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12988 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
12989 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12990 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12991 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12992 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
12993 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
12994 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
12995 | | // (MVE_VMLALDAVas32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 111 |
12996 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
12997 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
12998 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
12999 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13000 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13001 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13002 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13003 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13004 | | // (MVE_VMLALDAVau16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 119 |
13005 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13006 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13007 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13008 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13009 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13010 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13011 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13012 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13013 | | // (MVE_VMLALDAVau32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 127 |
13014 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13015 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13016 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13017 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13018 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13019 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13020 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13021 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13022 | | // (MVE_VMLALDAVs16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 135 |
13023 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13024 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13025 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13026 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13027 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13028 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13029 | | // (MVE_VMLALDAVs32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 141 |
13030 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13031 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13032 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13033 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13034 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13035 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13036 | | // (MVE_VMLALDAVu16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 147 |
13037 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13038 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13039 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13040 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13041 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13042 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13043 | | // (MVE_VMLALDAVu32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 153 |
13044 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13045 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13046 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13047 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13048 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13049 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13050 | | // (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp) - 159 |
13051 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13052 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13053 | 1.45M | { AliasPatternCond_K_TiedReg, 1 }, |
13054 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13055 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13056 | | // (MVE_VRMLALDAVHas32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 164 |
13057 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13058 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13059 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13060 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13061 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13062 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13063 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13064 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13065 | | // (MVE_VRMLALDAVHau32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 172 |
13066 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13067 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13068 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13069 | 1.45M | { AliasPatternCond_K_Ignore, 0 }, |
13070 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13071 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13072 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13073 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13074 | | // (MVE_VRMLALDAVHs32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 180 |
13075 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13076 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13077 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13078 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13079 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13080 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13081 | | // (MVE_VRMLALDAVHu32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 186 |
13082 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, |
13083 | 1.45M | { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, |
13084 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13085 | 1.45M | { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, |
13086 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, |
13087 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13088 | | // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 192 |
13089 | 1.45M | { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, |
13090 | 1.45M | { AliasPatternCond_K_Reg, ARM_ZR }, |
13091 | 1.45M | { AliasPatternCond_K_Reg, ARM_ZR }, |
13092 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, |
13093 | | // (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 196 |
13094 | 1.45M | { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, |
13095 | 1.45M | { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, |
13096 | 1.45M | { AliasPatternCond_K_TiedReg, 1 }, |
13097 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, |
13098 | | // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 200 |
13099 | 1.45M | { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, |
13100 | 1.45M | { AliasPatternCond_K_Reg, ARM_ZR }, |
13101 | 1.45M | { AliasPatternCond_K_Reg, ARM_ZR }, |
13102 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, |
13103 | | // (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 204 |
13104 | 1.45M | { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, |
13105 | 1.45M | { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, |
13106 | 1.45M | { AliasPatternCond_K_TiedReg, 1 }, |
13107 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, |
13108 | | // (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 208 |
13109 | 1.45M | { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, |
13110 | 1.45M | { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, |
13111 | 1.45M | { AliasPatternCond_K_TiedReg, 1 }, |
13112 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, |
13113 | | // (t2DSB 0, 14, 0) - 212 |
13114 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13115 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)14 }, |
13116 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13117 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDB }, |
13118 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13119 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13120 | | // (t2DSB 4, 14, 0) - 218 |
13121 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)4 }, |
13122 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)14 }, |
13123 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13124 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDB }, |
13125 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13126 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13127 | | // (t2DSB 12, pred:$p) - 224 |
13128 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)12 }, |
13129 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureDFB }, |
13130 | | // (t2HINT 0, pred:$p) - 226 |
13131 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13132 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13133 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13134 | | // (t2HINT 1, pred:$p) - 229 |
13135 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)1 }, |
13136 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13137 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13138 | | // (t2HINT 2, pred:$p) - 232 |
13139 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)2 }, |
13140 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13141 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13142 | | // (t2HINT 3, pred:$p) - 235 |
13143 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)3 }, |
13144 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13145 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13146 | | // (t2HINT 4, pred:$p) - 238 |
13147 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)4 }, |
13148 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13149 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13150 | | // (t2HINT 5, pred:$p) - 241 |
13151 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)5 }, |
13152 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13153 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13154 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8Ops }, |
13155 | | // (t2HINT 16, pred:$p) - 245 |
13156 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)16 }, |
13157 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13158 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13159 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureRAS }, |
13160 | | // (t2HINT 20, pred:$p) - 249 |
13161 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)20 }, |
13162 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13163 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13164 | | // (t2HINT 13, pred:$p) - 252 |
13165 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)13 }, |
13166 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13167 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13168 | | // (t2HINT 15, pred:$p) - 255 |
13169 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)15 }, |
13170 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13171 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13172 | | // (t2HINT 29, pred:$p) - 258 |
13173 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)29 }, |
13174 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13175 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13176 | | // (t2HINT 45, pred:$p) - 261 |
13177 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)45 }, |
13178 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13179 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13180 | | // (t2HINT 22, pred:$p) - 264 |
13181 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)22 }, |
13182 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13183 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13184 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8Ops }, |
13185 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureCLRBHB }, |
13186 | | // (t2SUBS_PC_LR 0, pred:$p) - 269 |
13187 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13188 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13189 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13190 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureVirtualization }, |
13191 | | // (tHINT 0, pred:$p) - 273 |
13192 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)0 }, |
13193 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13194 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6MOps }, |
13195 | | // (tHINT 1, pred:$p) - 276 |
13196 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)1 }, |
13197 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13198 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6MOps }, |
13199 | | // (tHINT 2, pred:$p) - 279 |
13200 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)2 }, |
13201 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13202 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6MOps }, |
13203 | | // (tHINT 3, pred:$p) - 282 |
13204 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)3 }, |
13205 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13206 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6MOps }, |
13207 | | // (tHINT 4, pred:$p) - 285 |
13208 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)4 }, |
13209 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13210 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV6MOps }, |
13211 | | // (tHINT 5, pred:$p) - 288 |
13212 | 1.45M | { AliasPatternCond_K_Imm, (uint32_t)5 }, |
13213 | 1.45M | { AliasPatternCond_K_Feature, ARM_ModeThumb }, |
13214 | 1.45M | { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, |
13215 | 1.45M | { AliasPatternCond_K_Feature, ARM_HasV8Ops }, |
13216 | 1.45M | { 0 }, |
13217 | 1.45M | }; |
13218 | | |
13219 | 1.45M | static const char AsmStrings[] = |
13220 | | /* 0 */ |
13221 | 1.45M | "ssbb\0" |
13222 | 1.45M | /* 5 */ "pssbb\0" |
13223 | 1.45M | /* 11 */ "dfb\0" |
13224 | 1.45M | /* 15 */ "nop$\xFF\x02\x01\0" |
13225 | 1.45M | /* 23 */ "yield$\xFF\x02\x01\0" |
13226 | 1.45M | /* 33 */ "wfe$\xFF\x02\x01\0" |
13227 | 1.45M | /* 41 */ "wfi$\xFF\x02\x01\0" |
13228 | 1.45M | /* 49 */ "sev$\xFF\x02\x01\0" |
13229 | 1.45M | /* 57 */ "sevl$\xFF\x02\x01\0" |
13230 | 1.45M | /* 66 */ "esb$\xFF\x02\x01\0" |
13231 | 1.45M | /* 74 */ "csdb$\xFF\x02\x01\0" |
13232 | 1.45M | /* 83 */ "clrbhb$\xFF\x02\x01\0" |
13233 | 1.45M | /* 94 */ "vmlava$\xFF\x05\x02.s16 $\x01, $\x03, $\x04\0" |
13234 | 1.45M | /* 120 */ "vmlava$\xFF\x05\x02.s32 $\x01, $\x03, $\x04\0" |
13235 | 1.45M | /* 146 */ "vmlava$\xFF\x05\x02.s8 $\x01, $\x03, $\x04\0" |
13236 | 1.45M | /* 171 */ "vmlava$\xFF\x05\x02.u16 $\x01, $\x03, $\x04\0" |
13237 | 1.45M | /* 197 */ "vmlava$\xFF\x05\x02.u32 $\x01, $\x03, $\x04\0" |
13238 | 1.45M | /* 223 */ "vmlava$\xFF\x05\x02.u8 $\x01, $\x03, $\x04\0" |
13239 | 1.45M | /* 248 */ "vmlav$\xFF\x04\x02.s16 $\x01, $\x02, $\x03\0" |
13240 | 1.45M | /* 273 */ "vmlav$\xFF\x04\x02.s32 $\x01, $\x02, $\x03\0" |
13241 | 1.45M | /* 298 */ "vmlav$\xFF\x04\x02.s8 $\x01, $\x02, $\x03\0" |
13242 | 1.45M | /* 322 */ "vmlav$\xFF\x04\x02.u16 $\x01, $\x02, $\x03\0" |
13243 | 1.45M | /* 347 */ "vmlav$\xFF\x04\x02.u32 $\x01, $\x02, $\x03\0" |
13244 | 1.45M | /* 372 */ "vmlav$\xFF\x04\x02.u8 $\x01, $\x02, $\x03\0" |
13245 | 1.45M | /* 396 */ "vmlalva$\xFF\x07\x02.s16 $\x01, $\x02, $\x05, $\x06\0" |
13246 | 1.45M | /* 427 */ "vmlalva$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" |
13247 | 1.45M | /* 458 */ "vmlalva$\xFF\x07\x02.u16 $\x01, $\x02, $\x05, $\x06\0" |
13248 | 1.45M | /* 489 */ "vmlalva$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" |
13249 | 1.45M | /* 520 */ "vmlalv$\xFF\x05\x02.s16 $\x01, $\x02, $\x03, $\x04\0" |
13250 | 1.45M | /* 550 */ "vmlalv$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" |
13251 | 1.45M | /* 580 */ "vmlalv$\xFF\x05\x02.u16 $\x01, $\x02, $\x03, $\x04\0" |
13252 | 1.45M | /* 610 */ "vmlalv$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" |
13253 | 1.45M | /* 640 */ "vmov$\xFF\x04\x02 $\x01, $\x02\0" |
13254 | 1.45M | /* 656 */ "vrmlalvha$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" |
13255 | 1.45M | /* 689 */ "vrmlalvha$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" |
13256 | 1.45M | /* 722 */ "vrmlalvh$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" |
13257 | 1.45M | /* 754 */ "vrmlalvh$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" |
13258 | 1.45M | /* 786 */ "cset $\x01, $\xFF\x04\x03\0" |
13259 | 1.45M | /* 800 */ "cinc $\x01, $\x02, $\xFF\x04\x03\0" |
13260 | 1.45M | /* 818 */ "csetm $\x01, $\xFF\x04\x03\0" |
13261 | 1.45M | /* 833 */ "cinv $\x01, $\x02, $\xFF\x04\x03\0" |
13262 | 1.45M | /* 851 */ "cneg $\x01, $\x02, $\xFF\x04\x03\0" |
13263 | 1.45M | /* 869 */ "dfb$\xFF\x02\x01\0" |
13264 | 1.45M | /* 877 */ "nop$\xFF\x02\x01.w\0" |
13265 | 1.45M | /* 887 */ "yield$\xFF\x02\x01.w\0" |
13266 | 1.45M | /* 899 */ "wfe$\xFF\x02\x01.w\0" |
13267 | 1.45M | /* 909 */ "wfi$\xFF\x02\x01.w\0" |
13268 | 1.45M | /* 919 */ "sev$\xFF\x02\x01.w\0" |
13269 | 1.45M | /* 929 */ "sevl$\xFF\x02\x01.w\0" |
13270 | 1.45M | /* 940 */ "esb$\xFF\x02\x01.w\0" |
13271 | 1.45M | /* 950 */ "pacbti$\xFF\x02\x01 r12,lr,sp\0" |
13272 | 1.45M | /* 971 */ "bti$\xFF\x02\x01\0" |
13273 | 1.45M | /* 979 */ "pac$\xFF\x02\x01 r12,lr,sp\0" |
13274 | 1.45M | /* 997 */ "aut$\xFF\x02\x01 r12,lr,sp\0" |
13275 | 1.45M | /* 1015 */ "eret$\xFF\x02\x01\0"; |
13276 | | |
13277 | 1.45M | #ifndef NDEBUG |
13278 | | //static struct SortCheck { |
13279 | | // SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
13280 | | // assert(std::is_sorted( |
13281 | | // OpToPatterns.begin(), OpToPatterns.end(), |
13282 | | // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { |
13283 | | // return L.Opcode < R.Opcode; |
13284 | | // }) && |
13285 | | // "tablegen failed to sort opcode patterns"); |
13286 | | // } |
13287 | | //} sortCheckVar(OpToPatterns); |
13288 | 1.45M | #endif |
13289 | | |
13290 | 1.45M | AliasMatchingData M = { |
13291 | 1.45M | OpToPatterns, Patterns, Conds, AsmStrings, NULL, |
13292 | 1.45M | }; |
13293 | 1.45M | const char *AsmString = matchAliasPatterns(MI, &M); |
13294 | 1.45M | if (!AsmString) |
13295 | 1.45M | return false; |
13296 | | |
13297 | 2.58k | unsigned I = 0; |
13298 | 17.5k | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
13299 | 17.5k | AsmString[I] != '$' && AsmString[I] != '\0') |
13300 | 14.9k | ++I; |
13301 | 2.58k | char *substr = cs_mem_malloc(I + 1); |
13302 | 2.58k | memcpy(substr, AsmString, I); |
13303 | 2.58k | substr[I] = '\0'; |
13304 | 2.58k | SStream_concat0(OS, substr); |
13305 | 2.58k | cs_mem_free(substr); |
13306 | 2.58k | if (AsmString[I] != '\0') { |
13307 | 2.53k | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
13308 | 462 | SStream_concat1(OS, ' '); |
13309 | 462 | ++I; |
13310 | 462 | } |
13311 | 22.5k | do { |
13312 | 22.5k | if (AsmString[I] == '$') { |
13313 | 7.97k | ++I; |
13314 | 7.97k | if (AsmString[I] == (char)0xff) { |
13315 | 2.53k | ++I; |
13316 | 2.53k | int OpIdx = AsmString[I++] - 1; |
13317 | 2.53k | int PrintMethodIdx = AsmString[I++] - 1; |
13318 | 2.53k | printCustomAliasOperand(MI, Address, |
13319 | 2.53k | OpIdx, |
13320 | 2.53k | PrintMethodIdx, |
13321 | 2.53k | OS); |
13322 | 2.53k | } else |
13323 | 5.43k | printOperand( |
13324 | 5.43k | MI, |
13325 | 5.43k | ((unsigned)AsmString[I++]) - 1, |
13326 | 5.43k | OS); |
13327 | 14.6k | } else { |
13328 | 14.6k | SStream_concat1(OS, AsmString[I++]); |
13329 | 14.6k | } |
13330 | 22.5k | } while (AsmString[I] != '\0'); |
13331 | 2.53k | } |
13332 | | |
13333 | 2.58k | return true; |
13334 | | #else |
13335 | | return false; |
13336 | | #endif // CAPSTONE_DIET |
13337 | 1.45M | } |
13338 | | |
13339 | | #ifndef CAPSTONE_DIET |
13340 | | void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx, |
13341 | | unsigned PrintMethodIdx, SStream *OS) |
13342 | 2.53k | { |
13343 | 2.53k | switch (PrintMethodIdx) { |
13344 | 0 | default: |
13345 | 0 | assert(0 && "Unknown PrintMethod kind"); |
13346 | 0 | break; |
13347 | 762 | case 0: |
13348 | 762 | printPredicateOperand(MI, OpIdx, OS); |
13349 | 762 | break; |
13350 | 1.31k | case 1: |
13351 | 1.31k | printVPTPredicateOperand(MI, OpIdx, OS); |
13352 | 1.31k | break; |
13353 | 462 | case 2: |
13354 | 462 | printMandatoryInvertedPredicateOperand(MI, OpIdx, OS); |
13355 | 462 | break; |
13356 | 2.53k | } |
13357 | 2.53k | } |
13358 | | #endif // CAPSTONE_DIET |
13359 | | |
13360 | | #endif // PRINT_ALIAS_INSTR |