/src/capstonenext/arch/Alpha/AlphaDisassembler.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_ALPHA |
5 | | |
6 | | #include <stdio.h> // DEBUG |
7 | | #include <stdlib.h> |
8 | | #include <string.h> |
9 | | |
10 | | #include "../../utils.h" |
11 | | |
12 | | #include "../../MCFixedLenDisassembler.h" |
13 | | #include "../../Mapping.h" |
14 | | |
15 | | #include "AlphaDisassembler.h" |
16 | | #include "AlphaLinkage.h" |
17 | | |
18 | | static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo, |
19 | | uint64_t Address, |
20 | | const void *Decoder); |
21 | | |
22 | | static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo, |
23 | | uint64_t Address, |
24 | | const void *Decoder); |
25 | | |
26 | | static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo, |
27 | | uint64_t Address, |
28 | | const void *Decoder); |
29 | | |
30 | | #include "AlphaGenDisassemblerTables.inc" |
31 | | |
32 | | #define GET_REGINFO_ENUM |
33 | | #define GET_REGINFO_MC_DESC |
34 | | |
35 | | #include "AlphaGenRegisterInfo.inc" |
36 | | |
37 | | static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo, |
38 | | uint64_t Address, |
39 | | const void *Decoder) |
40 | 0 | { |
41 | 0 | if (RegNo > 31) |
42 | 0 | return MCDisassembler_Fail; |
43 | | |
44 | 0 | unsigned Register = GPRC[RegNo]; |
45 | 0 | MCOperand_CreateReg0(Inst, (Register)); |
46 | 0 | return MCDisassembler_Success; |
47 | 0 | } |
48 | | |
49 | | static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo, |
50 | | uint64_t Address, |
51 | | const void *Decoder) |
52 | 0 | { |
53 | 0 | if (RegNo > 31) |
54 | 0 | return MCDisassembler_Fail; |
55 | | |
56 | 0 | unsigned Register = F4RC[RegNo]; |
57 | 0 | MCOperand_CreateReg0(Inst, (Register)); |
58 | 0 | return MCDisassembler_Success; |
59 | 0 | } |
60 | | |
61 | | static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo, |
62 | | uint64_t Address, |
63 | | const void *Decoder) |
64 | 0 | { |
65 | 0 | if (RegNo > 31) |
66 | 0 | return MCDisassembler_Fail; |
67 | | |
68 | 0 | unsigned Register = F8RC[RegNo]; |
69 | 0 | MCOperand_CreateReg0(Inst, (Register)); |
70 | 0 | return MCDisassembler_Success; |
71 | 0 | } |
72 | | |
73 | | #define GET_SUBTARGETINFO_ENUM |
74 | | |
75 | | #include "AlphaGenInstrInfo.inc" |
76 | | |
77 | | DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes, |
78 | | size_t ByteLen, MCInst *MI, |
79 | | uint16_t *Size, uint64_t Address, |
80 | | void *Info) |
81 | 0 | { |
82 | 0 | if (!handle) { |
83 | 0 | return MCDisassembler_Fail; |
84 | 0 | } |
85 | | |
86 | 0 | if (ByteLen < 4) { |
87 | 0 | *Size = 0; |
88 | 0 | return MCDisassembler_Fail; |
89 | 0 | } |
90 | | |
91 | 0 | uint32_t Insn = readBytes32(MI, Bytes); |
92 | | // Calling the auto-generated decoder function. |
93 | 0 | DecodeStatus Result = |
94 | 0 | decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL); |
95 | |
|
96 | 0 | if (Result != MCDisassembler_Fail) { |
97 | 0 | *Size = 4; |
98 | 0 | return Result; |
99 | 0 | } |
100 | | |
101 | 0 | *Size = 4; |
102 | 0 | return MCDisassembler_Fail; |
103 | 0 | } |
104 | | |
105 | | void Alpha_init(MCRegisterInfo *MRI) |
106 | 0 | { |
107 | 0 | MCRegisterInfo_InitMCRegisterInfo( |
108 | 0 | MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0, AlphaMCRegisterClasses, |
109 | 0 | ARR_SIZE(AlphaMCRegisterClasses), 0, 0, AlphaRegDiffLists, 0, |
110 | 0 | AlphaSubRegIdxLists, 1, 0); |
111 | 0 | } |
112 | | |
113 | | #endif |