/src/capstonenext/arch/Mips/MipsDisassembler.c
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1 | | //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file is part of the Mips Disassembler. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | /* Capstone Disassembly Engine */ |
15 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
16 | | |
17 | | #ifdef CAPSTONE_HAS_MIPS |
18 | | |
19 | | #include <stdio.h> |
20 | | #include <string.h> |
21 | | |
22 | | #include "capstone/platform.h" |
23 | | |
24 | | #include "MipsDisassembler.h" |
25 | | |
26 | | #include "../../utils.h" |
27 | | |
28 | | #include "../../MCRegisterInfo.h" |
29 | | #include "../../SStream.h" |
30 | | |
31 | | #include "../../MathExtras.h" |
32 | | |
33 | | //#include "Mips.h" |
34 | | //#include "MipsRegisterInfo.h" |
35 | | //#include "MipsSubtarget.h" |
36 | | #include "../../MCFixedLenDisassembler.h" |
37 | | #include "../../MCInst.h" |
38 | | //#include "llvm/MC/MCSubtargetInfo.h" |
39 | | #include "../../MCRegisterInfo.h" |
40 | | #include "../../MCDisassembler.h" |
41 | | |
42 | | // Forward declare these because the autogenerated code will reference them. |
43 | | // Definitions are further down. |
44 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, |
45 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
46 | | |
47 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, |
48 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
49 | | |
50 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, |
51 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
52 | | |
53 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, |
54 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
55 | | |
56 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, |
57 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
58 | | |
59 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, |
60 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
61 | | |
62 | | static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, |
63 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
64 | | |
65 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, |
66 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
67 | | |
68 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, |
69 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
70 | | |
71 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, |
72 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
73 | | |
74 | | static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, |
75 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
76 | | |
77 | | static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, |
78 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
79 | | |
80 | | static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, |
81 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
82 | | |
83 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, |
84 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
85 | | |
86 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, |
87 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
88 | | |
89 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, |
90 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
91 | | |
92 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, |
93 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
94 | | |
95 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, |
96 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
97 | | |
98 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, |
99 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
100 | | |
101 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, |
102 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
103 | | |
104 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, |
105 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
106 | | |
107 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, |
108 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
109 | | |
110 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, |
111 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
112 | | |
113 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, |
114 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
115 | | |
116 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, |
117 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); |
118 | | |
119 | | static DecodeStatus DecodeBranchTarget(MCInst *Inst, |
120 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); |
121 | | |
122 | | static DecodeStatus DecodeJumpTarget(MCInst *Inst, |
123 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
124 | | |
125 | | static DecodeStatus DecodeBranchTarget21(MCInst *Inst, |
126 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); |
127 | | |
128 | | static DecodeStatus DecodeBranchTarget26(MCInst *Inst, |
129 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); |
130 | | |
131 | | // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is |
132 | | // shifted left by 1 bit. |
133 | | static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, |
134 | | unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); |
135 | | |
136 | | // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is |
137 | | // shifted left by 1 bit. |
138 | | static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, |
139 | | unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); |
140 | | |
141 | | // DecodeBranchTargetMM - Decode microMIPS branch offset, which is |
142 | | // shifted left by 1 bit. |
143 | | static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, |
144 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); |
145 | | |
146 | | // DecodeJumpTargetMM - Decode microMIPS jump target, which is |
147 | | // shifted left by 1 bit. |
148 | | static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, |
149 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
150 | | |
151 | | static DecodeStatus DecodeMem(MCInst *Inst, |
152 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
153 | | |
154 | | static DecodeStatus DecodeCacheOp(MCInst *Inst, |
155 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
156 | | |
157 | | static DecodeStatus DecodeCacheOpR6(MCInst *Inst, |
158 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
159 | | |
160 | | static DecodeStatus DecodeCacheOpMM(MCInst *Inst, |
161 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
162 | | |
163 | | static DecodeStatus DecodeSyncI(MCInst *Inst, |
164 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
165 | | |
166 | | static DecodeStatus DecodeMSA128Mem(MCInst *Inst, |
167 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
168 | | |
169 | | static DecodeStatus DecodeMemMMImm4(MCInst *Inst, |
170 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
171 | | |
172 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, |
173 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
174 | | |
175 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, |
176 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
177 | | |
178 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, |
179 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
180 | | |
181 | | static DecodeStatus DecodeMemMMImm12(MCInst *Inst, |
182 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
183 | | |
184 | | static DecodeStatus DecodeMemMMImm16(MCInst *Inst, |
185 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
186 | | |
187 | | static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, |
188 | | uint64_t Address, const MCRegisterInfo *Decoder); |
189 | | |
190 | | static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, |
191 | | uint64_t Address, MCRegisterInfo *Decoder); |
192 | | |
193 | | static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, |
194 | | uint64_t Address, MCRegisterInfo *Decoder); |
195 | | |
196 | | static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, |
197 | | uint64_t Address, MCRegisterInfo *Decoder); |
198 | | |
199 | | static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, |
200 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
201 | | |
202 | | static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, |
203 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); |
204 | | |
205 | | static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, |
206 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); |
207 | | |
208 | | static DecodeStatus DecodeLiSimm7(MCInst *Inst, |
209 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); |
210 | | |
211 | | static DecodeStatus DecodeSimm4(MCInst *Inst, |
212 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); |
213 | | |
214 | | static DecodeStatus DecodeSimm16(MCInst *Inst, |
215 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
216 | | |
217 | | // Decode the immediate field of an LSA instruction which |
218 | | // is off by one. |
219 | | static DecodeStatus DecodeLSAImm(MCInst *Inst, |
220 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
221 | | |
222 | | static DecodeStatus DecodeInsSize(MCInst *Inst, |
223 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
224 | | |
225 | | static DecodeStatus DecodeExtSize(MCInst *Inst, |
226 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
227 | | |
228 | | static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, |
229 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
230 | | |
231 | | static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, |
232 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); |
233 | | |
234 | | static DecodeStatus DecodeSimm9SP(MCInst *Inst, |
235 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
236 | | |
237 | | static DecodeStatus DecodeANDI16Imm(MCInst *Inst, |
238 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
239 | | |
240 | | static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, |
241 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
242 | | |
243 | | static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, |
244 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
245 | | |
246 | | /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't |
247 | | /// handle. |
248 | | static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, |
249 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
250 | | |
251 | | static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, |
252 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
253 | | |
254 | | static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, |
255 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
256 | | |
257 | | static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, |
258 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
259 | | |
260 | | static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, |
261 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
262 | | |
263 | | static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, |
264 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
265 | | |
266 | | static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, |
267 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
268 | | |
269 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, |
270 | | uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); |
271 | | |
272 | | static DecodeStatus DecodeRegListOperand16(MCInst *Inst, |
273 | | uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); |
274 | | |
275 | | static DecodeStatus DecodeMovePRegPair(MCInst *Inst, |
276 | | uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); |
277 | | |
278 | | #define GET_SUBTARGETINFO_ENUM |
279 | | #include "MipsGenSubtargetInfo.inc" |
280 | | |
281 | | // Hacky: enable all features for disassembler |
282 | | static uint64_t getFeatureBits(int mode) |
283 | 236k | { |
284 | 236k | uint64_t Bits = (uint64_t)-1; // include every features at first |
285 | | |
286 | | // By default we do not support Mips1 |
287 | 236k | Bits &= ~Mips_FeatureMips1; |
288 | | |
289 | | // No MicroMips |
290 | 236k | Bits &= ~Mips_FeatureMicroMips; |
291 | | |
292 | | // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() |
293 | | // some features are mutually execlusive |
294 | 236k | if (mode & CS_MODE_16) { |
295 | | //Bits &= ~Mips_FeatureMips32r2; |
296 | | //Bits &= ~Mips_FeatureMips32; |
297 | | //Bits &= ~Mips_FeatureFPIdx; |
298 | | //Bits &= ~Mips_FeatureBitCount; |
299 | | //Bits &= ~Mips_FeatureSwap; |
300 | | //Bits &= ~Mips_FeatureSEInReg; |
301 | | //Bits &= ~Mips_FeatureMips64r2; |
302 | | //Bits &= ~Mips_FeatureFP64Bit; |
303 | 236k | } else if (mode & CS_MODE_32) { |
304 | 41.9k | Bits &= ~Mips_FeatureMips16; |
305 | 41.9k | Bits &= ~Mips_FeatureFP64Bit; |
306 | 41.9k | Bits &= ~Mips_FeatureMips64r2; |
307 | 41.9k | Bits &= ~Mips_FeatureMips32r6; |
308 | 41.9k | Bits &= ~Mips_FeatureMips64r6; |
309 | 194k | } else if (mode & CS_MODE_64) { |
310 | 123k | Bits &= ~Mips_FeatureMips16; |
311 | 123k | Bits &= ~Mips_FeatureMips64r6; |
312 | 123k | Bits &= ~Mips_FeatureMips32r6; |
313 | 123k | } else if (mode & CS_MODE_MIPS32R6) { |
314 | 70.5k | Bits |= Mips_FeatureMips32r6; |
315 | 70.5k | Bits &= ~Mips_FeatureMips16; |
316 | 70.5k | Bits &= ~Mips_FeatureFP64Bit; |
317 | 70.5k | Bits &= ~Mips_FeatureMips64r6; |
318 | 70.5k | Bits &= ~Mips_FeatureMips64r2; |
319 | 70.5k | } |
320 | | |
321 | 236k | if (mode & CS_MODE_MICRO) { |
322 | 66.8k | Bits |= Mips_FeatureMicroMips; |
323 | 66.8k | Bits &= ~Mips_FeatureMips4_32r2; |
324 | 66.8k | Bits &= ~Mips_FeatureMips2; |
325 | 66.8k | } |
326 | | |
327 | 236k | return Bits; |
328 | 236k | } |
329 | | |
330 | | #include "MipsGenDisassemblerTables.inc" |
331 | | |
332 | | #define GET_REGINFO_ENUM |
333 | | #include "MipsGenRegisterInfo.inc" |
334 | | |
335 | | #define GET_REGINFO_MC_DESC |
336 | | #include "MipsGenRegisterInfo.inc" |
337 | | |
338 | | #define GET_INSTRINFO_ENUM |
339 | | #include "MipsGenInstrInfo.inc" |
340 | | |
341 | | void Mips_init(MCRegisterInfo *MRI) |
342 | 4.47k | { |
343 | | // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, |
344 | | // MipsMCRegisterClasses, 62, |
345 | | // MipsRegUnitRoots, |
346 | | // 273, |
347 | | // MipsRegDiffLists, |
348 | | // MipsLaneMaskLists, |
349 | | // MipsRegStrings, |
350 | | // MipsRegClassStrings, |
351 | | // MipsSubRegIdxLists, |
352 | | // 12, |
353 | | // MipsSubRegIdxRanges, |
354 | | // MipsRegEncodingTable); |
355 | | |
356 | | |
357 | 4.47k | MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, |
358 | 4.47k | 0, 0, |
359 | 4.47k | MipsMCRegisterClasses, 62, |
360 | 4.47k | 0, 0, |
361 | 4.47k | MipsRegDiffLists, |
362 | 4.47k | 0, |
363 | 4.47k | MipsSubRegIdxLists, 12, |
364 | 4.47k | 0); |
365 | 4.47k | } |
366 | | |
367 | | /// Read two bytes from the ArrayRef and return 16 bit halfword sorted |
368 | | /// according to the given endianness. |
369 | | static void readInstruction16(unsigned char *code, uint32_t *insn, |
370 | | bool isBigEndian) |
371 | 46.9k | { |
372 | | // We want to read exactly 2 Bytes of data. |
373 | 46.9k | if (isBigEndian) |
374 | 20.0k | *insn = (code[0] << 8) | code[1]; |
375 | 26.9k | else |
376 | 26.9k | *insn = (code[1] << 8) | code[0]; |
377 | 46.9k | } |
378 | | |
379 | | /// readInstruction - read four bytes from the MemoryObject |
380 | | /// and return 32 bit word sorted according to the given endianness |
381 | | static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) |
382 | 123k | { |
383 | | // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) |
384 | | // always precede the low 16 bits in the instruction stream (that is, they |
385 | | // are placed at lower addresses in the instruction stream). |
386 | | // |
387 | | // microMIPS byte ordering: |
388 | | // Big-endian: 0 | 1 | 2 | 3 |
389 | | // Little-endian: 1 | 0 | 3 | 2 |
390 | | |
391 | | // We want to read exactly 4 Bytes of data. |
392 | 123k | if (isBigEndian) { |
393 | | // Encoded as a big-endian 32-bit word in the stream. |
394 | 65.5k | *insn = |
395 | 65.5k | (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); |
396 | 65.5k | } else { |
397 | 58.2k | if (isMicroMips) { |
398 | 11.4k | *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | |
399 | 11.4k | ((uint32_t) code[1] << 24); |
400 | 46.8k | } else { |
401 | 46.8k | *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | |
402 | 46.8k | ((uint32_t) code[3] << 24); |
403 | 46.8k | } |
404 | 58.2k | } |
405 | 123k | } |
406 | | |
407 | | static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, |
408 | | const uint8_t *code, size_t code_len, |
409 | | uint16_t *Size, |
410 | | uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) |
411 | 152k | { |
412 | 152k | uint32_t Insn; |
413 | 152k | DecodeStatus Result; |
414 | | |
415 | 152k | if (instr->flat_insn->detail) { |
416 | 152k | memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); |
417 | 152k | } |
418 | | |
419 | 152k | if (mode & CS_MODE_MICRO) { |
420 | 47.1k | if (code_len < 2) |
421 | | // not enough data |
422 | 185 | return MCDisassembler_Fail; |
423 | | |
424 | 46.9k | readInstruction16((unsigned char*)code, &Insn, isBigEndian); |
425 | | |
426 | | // Calling the auto-generated decoder function. |
427 | 46.9k | Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); |
428 | 46.9k | if (Result != MCDisassembler_Fail) { |
429 | 26.9k | *Size = 2; |
430 | 26.9k | return Result; |
431 | 26.9k | } |
432 | | |
433 | 20.0k | if (code_len < 4) |
434 | | // not enough data |
435 | 141 | return MCDisassembler_Fail; |
436 | | |
437 | 19.8k | readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); |
438 | | |
439 | | //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); |
440 | | // Calling the auto-generated decoder function. |
441 | 19.8k | Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); |
442 | 19.8k | if (Result != MCDisassembler_Fail) { |
443 | 19.6k | *Size = 4; |
444 | 19.6k | return Result; |
445 | 19.6k | } |
446 | 248 | return MCDisassembler_Fail; |
447 | 19.8k | } |
448 | | |
449 | 105k | if (code_len < 4) |
450 | | // not enough data |
451 | 1.18k | return MCDisassembler_Fail; |
452 | | |
453 | 103k | readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); |
454 | | |
455 | 103k | if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { |
456 | | // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); |
457 | 0 | Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); |
458 | 0 | if (Result != MCDisassembler_Fail) { |
459 | 0 | *Size = 4; |
460 | 0 | return Result; |
461 | 0 | } |
462 | 0 | } |
463 | | |
464 | 103k | if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { |
465 | | // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); |
466 | 0 | Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, |
467 | 0 | Address, MRI, mode); |
468 | 0 | if (Result != MCDisassembler_Fail) { |
469 | 0 | *Size = 4; |
470 | 0 | return Result; |
471 | 0 | } |
472 | 0 | } |
473 | | |
474 | 103k | if (mode & CS_MODE_MIPS32R6) { |
475 | | // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); |
476 | 24.8k | Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, |
477 | 24.8k | Address, MRI, mode); |
478 | 24.8k | if (Result != MCDisassembler_Fail) { |
479 | 12.3k | *Size = 4; |
480 | 12.3k | return Result; |
481 | 12.3k | } |
482 | 24.8k | } |
483 | | |
484 | 91.5k | if (mode & CS_MODE_MIPS64) { |
485 | | // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); |
486 | 70.7k | Result = decodeInstruction(DecoderTableMips6432, instr, Insn, |
487 | 70.7k | Address, MRI, mode); |
488 | 70.7k | if (Result != MCDisassembler_Fail) { |
489 | 17.9k | *Size = 4; |
490 | 17.9k | return Result; |
491 | 17.9k | } |
492 | 70.7k | } |
493 | | |
494 | | // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); |
495 | | // Calling the auto-generated decoder function. |
496 | 73.6k | Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); |
497 | 73.6k | if (Result != MCDisassembler_Fail) { |
498 | 72.5k | *Size = 4; |
499 | 72.5k | return Result; |
500 | 72.5k | } |
501 | | |
502 | 1.13k | return MCDisassembler_Fail; |
503 | 73.6k | } |
504 | | |
505 | | bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, |
506 | | uint16_t *size, uint64_t address, void *info) |
507 | 152k | { |
508 | 152k | cs_struct *handle = (cs_struct *)(uintptr_t)ud; |
509 | | |
510 | 152k | DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, |
511 | 152k | code, code_len, |
512 | 152k | size, |
513 | 152k | address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); |
514 | | |
515 | 152k | return status == MCDisassembler_Success; |
516 | 152k | } |
517 | | |
518 | | static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) |
519 | 266k | { |
520 | 266k | const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); |
521 | 266k | return rc->RegsBegin[RegNo]; |
522 | 266k | } |
523 | | |
524 | | static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, |
525 | | uint64_t Address, const MCRegisterInfo *Decoder) |
526 | 128 | { |
527 | 128 | typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); |
528 | | // The size of the n field depends on the element size |
529 | | // The register class also depends on this. |
530 | 128 | uint32_t tmp = fieldFromInstruction(insn, 17, 5); |
531 | 128 | unsigned NSize = 0; |
532 | 128 | DecodeFN RegDecoder = NULL; |
533 | | |
534 | 128 | if ((tmp & 0x18) == 0x00) { // INSVE_B |
535 | 22 | NSize = 4; |
536 | 22 | RegDecoder = DecodeMSA128BRegisterClass; |
537 | 106 | } else if ((tmp & 0x1c) == 0x10) { // INSVE_H |
538 | 28 | NSize = 3; |
539 | 28 | RegDecoder = DecodeMSA128HRegisterClass; |
540 | 78 | } else if ((tmp & 0x1e) == 0x18) { // INSVE_W |
541 | 49 | NSize = 2; |
542 | 49 | RegDecoder = DecodeMSA128WRegisterClass; |
543 | 49 | } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D |
544 | 29 | NSize = 1; |
545 | 29 | RegDecoder = DecodeMSA128DRegisterClass; |
546 | 29 | } //else llvm_unreachable("Invalid encoding"); |
547 | | |
548 | | //assert(NSize != 0 && RegDecoder != nullptr); |
549 | 128 | if (NSize == 0 || RegDecoder == NULL) |
550 | 0 | return MCDisassembler_Fail; |
551 | | |
552 | | // $wd |
553 | 128 | tmp = fieldFromInstruction(insn, 6, 5); |
554 | 128 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
555 | 0 | return MCDisassembler_Fail; |
556 | | |
557 | | // $wd_in |
558 | 128 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
559 | 0 | return MCDisassembler_Fail; |
560 | | |
561 | | // $n |
562 | 128 | tmp = fieldFromInstruction(insn, 16, NSize); |
563 | 128 | MCOperand_CreateImm0(MI, tmp); |
564 | | |
565 | | // $ws |
566 | 128 | tmp = fieldFromInstruction(insn, 11, 5); |
567 | 128 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
568 | 0 | return MCDisassembler_Fail; |
569 | | |
570 | | // $n2 |
571 | 128 | MCOperand_CreateImm0(MI, 0); |
572 | | |
573 | 128 | return MCDisassembler_Success; |
574 | 128 | } |
575 | | |
576 | | static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, |
577 | | uint64_t Address, const MCRegisterInfo *Decoder) |
578 | 1.52k | { |
579 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
580 | | // (otherwise we would have matched the ADDI instruction from the earlier |
581 | | // ISA's instead). |
582 | | // |
583 | | // We have: |
584 | | // 0b001000 sssss ttttt iiiiiiiiiiiiiiii |
585 | | // BOVC if rs >= rt |
586 | | // BEQZALC if rs == 0 && rt != 0 |
587 | | // BEQC if rs < rt && rs != 0 |
588 | | |
589 | 1.52k | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
590 | 1.52k | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
591 | 1.52k | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
592 | 1.52k | bool HasRs = false; |
593 | | |
594 | 1.52k | if (Rs >= Rt) { |
595 | 816 | MCInst_setOpcode(MI, Mips_BOVC); |
596 | 816 | HasRs = true; |
597 | 816 | } else if (Rs != 0 && Rs < Rt) { |
598 | 307 | MCInst_setOpcode(MI, Mips_BEQC); |
599 | 307 | HasRs = true; |
600 | 307 | } else |
601 | 399 | MCInst_setOpcode(MI, Mips_BEQZALC); |
602 | | |
603 | 1.52k | if (HasRs) |
604 | 1.12k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
605 | | |
606 | 1.52k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
607 | 1.52k | MCOperand_CreateImm0(MI, Imm); |
608 | | |
609 | 1.52k | return MCDisassembler_Success; |
610 | 1.52k | } |
611 | | |
612 | | static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, |
613 | | uint64_t Address, const MCRegisterInfo *Decoder) |
614 | 804 | { |
615 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
616 | | // (otherwise we would have matched the ADDI instruction from the earlier |
617 | | // ISA's instead). |
618 | | // |
619 | | // We have: |
620 | | // 0b011000 sssss ttttt iiiiiiiiiiiiiiii |
621 | | // BNVC if rs >= rt |
622 | | // BNEZALC if rs == 0 && rt != 0 |
623 | | // BNEC if rs < rt && rs != 0 |
624 | | |
625 | 804 | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
626 | 804 | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
627 | 804 | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
628 | 804 | bool HasRs = false; |
629 | | |
630 | 804 | if (Rs >= Rt) { |
631 | 586 | MCInst_setOpcode(MI, Mips_BNVC); |
632 | 586 | HasRs = true; |
633 | 586 | } else if (Rs != 0 && Rs < Rt) { |
634 | 128 | MCInst_setOpcode(MI, Mips_BNEC); |
635 | 128 | HasRs = true; |
636 | 128 | } else |
637 | 90 | MCInst_setOpcode(MI, Mips_BNEZALC); |
638 | | |
639 | 804 | if (HasRs) |
640 | 714 | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
641 | | |
642 | 804 | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
643 | 804 | MCOperand_CreateImm0(MI, Imm); |
644 | | |
645 | 804 | return MCDisassembler_Success; |
646 | 804 | } |
647 | | |
648 | | static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, |
649 | | uint64_t Address, const MCRegisterInfo *Decoder) |
650 | 1.20k | { |
651 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
652 | | // (otherwise we would have matched the BLEZL instruction from the earlier |
653 | | // ISA's instead). |
654 | | // |
655 | | // We have: |
656 | | // 0b010110 sssss ttttt iiiiiiiiiiiiiiii |
657 | | // Invalid if rs == 0 |
658 | | // BLEZC if rs == 0 && rt != 0 |
659 | | // BGEZC if rs == rt && rt != 0 |
660 | | // BGEC if rs != rt && rs != 0 && rt != 0 |
661 | | |
662 | 1.20k | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
663 | 1.20k | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
664 | 1.20k | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
665 | 1.20k | bool HasRs = false; |
666 | | |
667 | 1.20k | if (Rt == 0) |
668 | 5 | return MCDisassembler_Fail; |
669 | 1.20k | else if (Rs == 0) |
670 | 154 | MCInst_setOpcode(MI, Mips_BLEZC); |
671 | 1.04k | else if (Rs == Rt) |
672 | 234 | MCInst_setOpcode(MI, Mips_BGEZC); |
673 | 815 | else { |
674 | 815 | HasRs = true; |
675 | 815 | MCInst_setOpcode(MI, Mips_BGEC); |
676 | 815 | } |
677 | | |
678 | 1.20k | if (HasRs) |
679 | 815 | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
680 | | |
681 | 1.20k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
682 | | |
683 | 1.20k | MCOperand_CreateImm0(MI, Imm); |
684 | | |
685 | 1.20k | return MCDisassembler_Success; |
686 | 1.20k | } |
687 | | |
688 | | static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, |
689 | | uint64_t Address, const MCRegisterInfo *Decoder) |
690 | 1.06k | { |
691 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
692 | | // (otherwise we would have matched the BGTZL instruction from the earlier |
693 | | // ISA's instead). |
694 | | // |
695 | | // We have: |
696 | | // 0b010111 sssss ttttt iiiiiiiiiiiiiiii |
697 | | // Invalid if rs == 0 |
698 | | // BGTZC if rs == 0 && rt != 0 |
699 | | // BLTZC if rs == rt && rt != 0 |
700 | | // BLTC if rs != rt && rs != 0 && rt != 0 |
701 | | |
702 | 1.06k | bool HasRs = false; |
703 | | |
704 | 1.06k | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
705 | 1.06k | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
706 | 1.06k | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
707 | | |
708 | 1.06k | if (Rt == 0) |
709 | 5 | return MCDisassembler_Fail; |
710 | 1.05k | else if (Rs == 0) |
711 | 96 | MCInst_setOpcode(MI, Mips_BGTZC); |
712 | 960 | else if (Rs == Rt) |
713 | 71 | MCInst_setOpcode(MI, Mips_BLTZC); |
714 | 889 | else { |
715 | 889 | MCInst_setOpcode(MI, Mips_BLTC); |
716 | 889 | HasRs = true; |
717 | 889 | } |
718 | | |
719 | 1.05k | if (HasRs) |
720 | 889 | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
721 | | |
722 | 1.05k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
723 | 1.05k | MCOperand_CreateImm0(MI, Imm); |
724 | | |
725 | 1.05k | return MCDisassembler_Success; |
726 | 1.06k | } |
727 | | |
728 | | static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, |
729 | | uint64_t Address, const MCRegisterInfo *Decoder) |
730 | 2.15k | { |
731 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
732 | | // (otherwise we would have matched the BGTZ instruction from the earlier |
733 | | // ISA's instead). |
734 | | // |
735 | | // We have: |
736 | | // 0b000111 sssss ttttt iiiiiiiiiiiiiiii |
737 | | // BGTZ if rt == 0 |
738 | | // BGTZALC if rs == 0 && rt != 0 |
739 | | // BLTZALC if rs != 0 && rs == rt |
740 | | // BLTUC if rs != 0 && rs != rt |
741 | | |
742 | 2.15k | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
743 | 2.15k | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
744 | 2.15k | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
745 | 2.15k | bool HasRs = false; |
746 | 2.15k | bool HasRt = false; |
747 | | |
748 | 2.15k | if (Rt == 0) { |
749 | 94 | MCInst_setOpcode(MI, Mips_BGTZ); |
750 | 94 | HasRs = true; |
751 | 2.05k | } else if (Rs == 0) { |
752 | 466 | MCInst_setOpcode(MI, Mips_BGTZALC); |
753 | 466 | HasRt = true; |
754 | 1.59k | } else if (Rs == Rt) { |
755 | 155 | MCInst_setOpcode(MI, Mips_BLTZALC); |
756 | 155 | HasRs = true; |
757 | 1.43k | } else { |
758 | 1.43k | MCInst_setOpcode(MI, Mips_BLTUC); |
759 | 1.43k | HasRs = true; |
760 | 1.43k | HasRt = true; |
761 | 1.43k | } |
762 | | |
763 | 2.15k | if (HasRs) |
764 | 1.68k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
765 | | |
766 | 2.15k | if (HasRt) |
767 | 1.90k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
768 | | |
769 | 2.15k | MCOperand_CreateImm0(MI, Imm); |
770 | | |
771 | 2.15k | return MCDisassembler_Success; |
772 | 2.15k | } |
773 | | |
774 | | static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, |
775 | | uint64_t Address, const MCRegisterInfo *Decoder) |
776 | 1.45k | { |
777 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
778 | | // (otherwise we would have matched the BLEZL instruction from the earlier |
779 | | // ISA's instead). |
780 | | // |
781 | | // We have: |
782 | | // 0b000110 sssss ttttt iiiiiiiiiiiiiiii |
783 | | // Invalid if rs == 0 |
784 | | // BLEZALC if rs == 0 && rt != 0 |
785 | | // BGEZALC if rs == rt && rt != 0 |
786 | | // BGEUC if rs != rt && rs != 0 && rt != 0 |
787 | | |
788 | 1.45k | uint32_t Rs = fieldFromInstruction(insn, 21, 5); |
789 | 1.45k | uint32_t Rt = fieldFromInstruction(insn, 16, 5); |
790 | 1.45k | uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; |
791 | 1.45k | bool HasRs = false; |
792 | | |
793 | 1.45k | if (Rt == 0) |
794 | 261 | return MCDisassembler_Fail; |
795 | 1.19k | else if (Rs == 0) |
796 | 306 | MCInst_setOpcode(MI, Mips_BLEZALC); |
797 | 887 | else if (Rs == Rt) |
798 | 99 | MCInst_setOpcode(MI, Mips_BGEZALC); |
799 | 788 | else { |
800 | 788 | HasRs = true; |
801 | 788 | MCInst_setOpcode(MI, Mips_BGEUC); |
802 | 788 | } |
803 | | |
804 | 1.19k | if (HasRs) |
805 | 788 | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); |
806 | | |
807 | 1.19k | MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); |
808 | | |
809 | 1.19k | MCOperand_CreateImm0(MI, Imm); |
810 | | |
811 | 1.19k | return MCDisassembler_Success; |
812 | 1.45k | } |
813 | | |
814 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, |
815 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
816 | 0 | { |
817 | 0 | return MCDisassembler_Fail; |
818 | 0 | } |
819 | | |
820 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, |
821 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
822 | 14.2k | { |
823 | 14.2k | unsigned Reg; |
824 | | |
825 | 14.2k | if (RegNo > 31) |
826 | 0 | return MCDisassembler_Fail; |
827 | | |
828 | 14.2k | Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); |
829 | 14.2k | MCOperand_CreateReg0(Inst, Reg); |
830 | 14.2k | return MCDisassembler_Success; |
831 | 14.2k | } |
832 | | |
833 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, |
834 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
835 | 29.3k | { |
836 | 29.3k | unsigned Reg; |
837 | | |
838 | 29.3k | if (RegNo > 7) |
839 | 0 | return MCDisassembler_Fail; |
840 | | |
841 | 29.3k | Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); |
842 | 29.3k | MCOperand_CreateReg0(Inst, Reg); |
843 | 29.3k | return MCDisassembler_Success; |
844 | 29.3k | } |
845 | | |
846 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, |
847 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
848 | 2.61k | { |
849 | 2.61k | unsigned Reg; |
850 | | |
851 | 2.61k | if (RegNo > 7) |
852 | 0 | return MCDisassembler_Fail; |
853 | | |
854 | 2.61k | Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); |
855 | 2.61k | MCOperand_CreateReg0(Inst, Reg); |
856 | 2.61k | return MCDisassembler_Success; |
857 | 2.61k | } |
858 | | |
859 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, |
860 | | unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
861 | 1.07k | { |
862 | 1.07k | unsigned Reg; |
863 | | |
864 | 1.07k | if (RegNo > 7) |
865 | 0 | return MCDisassembler_Fail; |
866 | | |
867 | 1.07k | Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); |
868 | 1.07k | MCOperand_CreateReg0(Inst, Reg); |
869 | 1.07k | return MCDisassembler_Success; |
870 | 1.07k | } |
871 | | |
872 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, |
873 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
874 | 103k | { |
875 | 103k | unsigned Reg; |
876 | | |
877 | 103k | if (RegNo > 31) |
878 | 0 | return MCDisassembler_Fail; |
879 | | |
880 | 103k | Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); |
881 | 103k | MCOperand_CreateReg0(Inst, Reg); |
882 | 103k | return MCDisassembler_Success; |
883 | 103k | } |
884 | | |
885 | | static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, |
886 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
887 | 3.69k | { |
888 | | // if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) |
889 | 3.69k | if (Inst->csh->mode & CS_MODE_MIPS64) |
890 | 2.67k | return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); |
891 | | |
892 | 1.02k | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
893 | 3.69k | } |
894 | | |
895 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, |
896 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
897 | 1.09k | { |
898 | 1.09k | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
899 | 1.09k | } |
900 | | |
901 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, |
902 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
903 | 8.20k | { |
904 | 8.20k | unsigned Reg; |
905 | | |
906 | 8.20k | if (RegNo > 31) |
907 | 0 | return MCDisassembler_Fail; |
908 | | |
909 | 8.20k | Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); |
910 | 8.20k | MCOperand_CreateReg0(Inst, Reg); |
911 | 8.20k | return MCDisassembler_Success; |
912 | 8.20k | } |
913 | | |
914 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, |
915 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
916 | 4.54k | { |
917 | 4.54k | unsigned Reg; |
918 | | |
919 | 4.54k | if (RegNo > 31) |
920 | 0 | return MCDisassembler_Fail; |
921 | | |
922 | 4.54k | Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); |
923 | 4.54k | MCOperand_CreateReg0(Inst, Reg); |
924 | 4.54k | return MCDisassembler_Success; |
925 | 4.54k | } |
926 | | |
927 | | static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, |
928 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
929 | 109 | { |
930 | 109 | unsigned Reg; |
931 | | |
932 | 109 | if (RegNo > 31) |
933 | 0 | return MCDisassembler_Fail; |
934 | | |
935 | 109 | Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); |
936 | 109 | MCOperand_CreateReg0(Inst, Reg); |
937 | 109 | return MCDisassembler_Success; |
938 | 109 | } |
939 | | |
940 | | static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, |
941 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
942 | 2.80k | { |
943 | 2.80k | unsigned Reg; |
944 | | |
945 | 2.80k | if (RegNo > 7) |
946 | 0 | return MCDisassembler_Fail; |
947 | | |
948 | 2.80k | Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); |
949 | 2.80k | MCOperand_CreateReg0(Inst, Reg); |
950 | 2.80k | return MCDisassembler_Success; |
951 | 2.80k | } |
952 | | |
953 | | static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, |
954 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
955 | 2.95k | { |
956 | 2.95k | unsigned Reg; |
957 | | |
958 | 2.95k | if (RegNo > 7) |
959 | 0 | return MCDisassembler_Fail; |
960 | | |
961 | 2.95k | Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); |
962 | 2.95k | MCOperand_CreateReg0(Inst, Reg); |
963 | 2.95k | return MCDisassembler_Success; |
964 | 2.95k | } |
965 | | |
966 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, |
967 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
968 | 305 | { |
969 | 305 | unsigned Reg; |
970 | | |
971 | 305 | if (RegNo > 31) |
972 | 0 | return MCDisassembler_Fail; |
973 | | |
974 | 305 | Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); |
975 | 305 | MCOperand_CreateReg0(Inst, Reg); |
976 | 305 | return MCDisassembler_Success; |
977 | 305 | } |
978 | | |
979 | | static DecodeStatus DecodeMem(MCInst *Inst, |
980 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
981 | 15.8k | { |
982 | 15.8k | int Offset = SignExtend32(Insn & 0xffff, 16); |
983 | 15.8k | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
984 | 15.8k | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
985 | 15.8k | int opcode = MCInst_getOpcode(Inst); |
986 | | |
987 | 15.8k | Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
988 | 15.8k | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
989 | | |
990 | 15.8k | if (opcode == Mips_SC || opcode == Mips_SCD) { |
991 | 1.76k | MCOperand_CreateReg0(Inst, Reg); |
992 | 1.76k | } |
993 | | |
994 | 15.8k | MCOperand_CreateReg0(Inst, Reg); |
995 | 15.8k | MCOperand_CreateReg0(Inst, Base); |
996 | 15.8k | MCOperand_CreateImm0(Inst, Offset); |
997 | | |
998 | 15.8k | return MCDisassembler_Success; |
999 | 15.8k | } |
1000 | | |
1001 | | static DecodeStatus DecodeCacheOp(MCInst *Inst, |
1002 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1003 | 959 | { |
1004 | 959 | int Offset = SignExtend32(Insn & 0xffff, 16); |
1005 | 959 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); |
1006 | 959 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1007 | | |
1008 | 959 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1009 | | |
1010 | 959 | MCOperand_CreateReg0(Inst, Base); |
1011 | 959 | MCOperand_CreateImm0(Inst, Offset); |
1012 | 959 | MCOperand_CreateImm0(Inst, Hint); |
1013 | | |
1014 | 959 | return MCDisassembler_Success; |
1015 | 959 | } |
1016 | | |
1017 | | static DecodeStatus DecodeCacheOpMM(MCInst *Inst, |
1018 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1019 | 126 | { |
1020 | 126 | int Offset = SignExtend32(Insn & 0xfff, 12); |
1021 | 126 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1022 | 126 | unsigned Hint = fieldFromInstruction(Insn, 21, 5); |
1023 | | |
1024 | 126 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1025 | | |
1026 | 126 | MCOperand_CreateReg0(Inst, Base); |
1027 | 126 | MCOperand_CreateImm0(Inst, Offset); |
1028 | 126 | MCOperand_CreateImm0(Inst, Hint); |
1029 | | |
1030 | 126 | return MCDisassembler_Success; |
1031 | 126 | } |
1032 | | |
1033 | | static DecodeStatus DecodeCacheOpR6(MCInst *Inst, |
1034 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1035 | 48 | { |
1036 | 48 | int Offset = fieldFromInstruction(Insn, 7, 9); |
1037 | 48 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); |
1038 | 48 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1039 | | |
1040 | 48 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1041 | | |
1042 | 48 | MCOperand_CreateReg0(Inst, Base); |
1043 | 48 | MCOperand_CreateImm0(Inst, Offset); |
1044 | 48 | MCOperand_CreateImm0(Inst, Hint); |
1045 | | |
1046 | 48 | return MCDisassembler_Success; |
1047 | 48 | } |
1048 | | |
1049 | | static DecodeStatus DecodeSyncI(MCInst *Inst, |
1050 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1051 | 295 | { |
1052 | 295 | int Offset = SignExtend32(Insn & 0xffff, 16); |
1053 | 295 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1054 | | |
1055 | 295 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1056 | | |
1057 | 295 | MCOperand_CreateReg0(Inst, Base); |
1058 | 295 | MCOperand_CreateImm0(Inst, Offset); |
1059 | | |
1060 | 295 | return MCDisassembler_Success; |
1061 | 295 | } |
1062 | | |
1063 | | static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, |
1064 | | uint64_t Address, const MCRegisterInfo *Decoder) |
1065 | 1.33k | { |
1066 | 1.33k | int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); |
1067 | 1.33k | unsigned Reg = fieldFromInstruction(Insn, 6, 5); |
1068 | 1.33k | unsigned Base = fieldFromInstruction(Insn, 11, 5); |
1069 | | |
1070 | 1.33k | Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); |
1071 | 1.33k | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1072 | | |
1073 | 1.33k | MCOperand_CreateReg0(Inst, Reg); |
1074 | 1.33k | MCOperand_CreateReg0(Inst, Base); |
1075 | | // MCOperand_CreateImm0(Inst, Offset); |
1076 | | |
1077 | | // The immediate field of an LD/ST instruction is scaled which means it must |
1078 | | // be multiplied (when decoding) by the size (in bytes) of the instructions' |
1079 | | // data format. |
1080 | | // .b - 1 byte |
1081 | | // .h - 2 bytes |
1082 | | // .w - 4 bytes |
1083 | | // .d - 8 bytes |
1084 | 1.33k | switch(MCInst_getOpcode(Inst)) { |
1085 | 0 | default: |
1086 | | //assert (0 && "Unexpected instruction"); |
1087 | 0 | return MCDisassembler_Fail; |
1088 | 0 | break; |
1089 | 136 | case Mips_LD_B: |
1090 | 368 | case Mips_ST_B: |
1091 | 368 | MCOperand_CreateImm0(Inst, Offset); |
1092 | 368 | break; |
1093 | 88 | case Mips_LD_H: |
1094 | 249 | case Mips_ST_H: |
1095 | 249 | MCOperand_CreateImm0(Inst, Offset * 2); |
1096 | 249 | break; |
1097 | 96 | case Mips_LD_W: |
1098 | 296 | case Mips_ST_W: |
1099 | 296 | MCOperand_CreateImm0(Inst, Offset * 4); |
1100 | 296 | break; |
1101 | 172 | case Mips_LD_D: |
1102 | 425 | case Mips_ST_D: |
1103 | 425 | MCOperand_CreateImm0(Inst, Offset * 8); |
1104 | 425 | break; |
1105 | 1.33k | } |
1106 | | |
1107 | 1.33k | return MCDisassembler_Success; |
1108 | 1.33k | } |
1109 | | |
1110 | | static DecodeStatus DecodeMemMMImm4(MCInst *Inst, |
1111 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1112 | 7.38k | { |
1113 | 7.38k | unsigned Offset = Insn & 0xf; |
1114 | 7.38k | unsigned Reg = fieldFromInstruction(Insn, 7, 3); |
1115 | 7.38k | unsigned Base = fieldFromInstruction(Insn, 4, 3); |
1116 | | |
1117 | 7.38k | switch (MCInst_getOpcode(Inst)) { |
1118 | 2.43k | case Mips_LBU16_MM: |
1119 | 3.82k | case Mips_LHU16_MM: |
1120 | 4.76k | case Mips_LW16_MM: |
1121 | 4.76k | if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) |
1122 | 4.76k | == MCDisassembler_Fail) |
1123 | 0 | return MCDisassembler_Fail; |
1124 | 4.76k | break; |
1125 | 4.76k | case Mips_SB16_MM: |
1126 | 1.85k | case Mips_SH16_MM: |
1127 | 2.61k | case Mips_SW16_MM: |
1128 | 2.61k | if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) |
1129 | 2.61k | == MCDisassembler_Fail) |
1130 | 0 | return MCDisassembler_Fail; |
1131 | 2.61k | break; |
1132 | 7.38k | } |
1133 | | |
1134 | 7.38k | if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) |
1135 | 7.38k | == MCDisassembler_Fail) |
1136 | 0 | return MCDisassembler_Fail; |
1137 | | |
1138 | 7.38k | switch (MCInst_getOpcode(Inst)) { |
1139 | 2.43k | case Mips_LBU16_MM: |
1140 | 2.43k | if (Offset == 0xf) |
1141 | 444 | MCOperand_CreateImm0(Inst, -1); |
1142 | 1.99k | else |
1143 | 1.99k | MCOperand_CreateImm0(Inst, Offset); |
1144 | 2.43k | break; |
1145 | 1.22k | case Mips_SB16_MM: |
1146 | 1.22k | MCOperand_CreateImm0(Inst, Offset); |
1147 | 1.22k | break; |
1148 | 1.39k | case Mips_LHU16_MM: |
1149 | 2.02k | case Mips_SH16_MM: |
1150 | 2.02k | MCOperand_CreateImm0(Inst, Offset << 1); |
1151 | 2.02k | break; |
1152 | 935 | case Mips_LW16_MM: |
1153 | 1.69k | case Mips_SW16_MM: |
1154 | 1.69k | MCOperand_CreateImm0(Inst, Offset << 2); |
1155 | 1.69k | break; |
1156 | 7.38k | } |
1157 | | |
1158 | 7.38k | return MCDisassembler_Success; |
1159 | 7.38k | } |
1160 | | |
1161 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, |
1162 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1163 | 895 | { |
1164 | 895 | unsigned Offset = Insn & 0x1F; |
1165 | 895 | unsigned Reg = fieldFromInstruction(Insn, 5, 5); |
1166 | | |
1167 | 895 | Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
1168 | | |
1169 | 895 | MCOperand_CreateReg0(Inst, Reg); |
1170 | 895 | MCOperand_CreateReg0(Inst, Mips_SP); |
1171 | 895 | MCOperand_CreateImm0(Inst, Offset << 2); |
1172 | | |
1173 | 895 | return MCDisassembler_Success; |
1174 | 895 | } |
1175 | | |
1176 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, |
1177 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1178 | 653 | { |
1179 | 653 | unsigned Offset = Insn & 0x7F; |
1180 | 653 | unsigned Reg = fieldFromInstruction(Insn, 7, 3); |
1181 | | |
1182 | 653 | Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
1183 | | |
1184 | 653 | MCOperand_CreateReg0(Inst, Reg); |
1185 | 653 | MCOperand_CreateReg0(Inst, Mips_GP); |
1186 | 653 | MCOperand_CreateImm0(Inst, Offset << 2); |
1187 | | |
1188 | 653 | return MCDisassembler_Success; |
1189 | 653 | } |
1190 | | |
1191 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, |
1192 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1193 | 1.28k | { |
1194 | 1.28k | int Offset = SignExtend32(Insn & 0xf, 4); |
1195 | | |
1196 | 1.28k | if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) |
1197 | 0 | return MCDisassembler_Fail; |
1198 | | |
1199 | 1.28k | MCOperand_CreateReg0(Inst, Mips_SP); |
1200 | 1.28k | MCOperand_CreateImm0(Inst, Offset * 4); |
1201 | | |
1202 | 1.28k | return MCDisassembler_Success; |
1203 | 1.28k | } |
1204 | | |
1205 | | static DecodeStatus DecodeMemMMImm12(MCInst *Inst, |
1206 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1207 | 1.30k | { |
1208 | 1.30k | int Offset = SignExtend32(Insn & 0x0fff, 12); |
1209 | 1.30k | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1210 | 1.30k | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1211 | | |
1212 | 1.30k | Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
1213 | 1.30k | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1214 | | |
1215 | 1.30k | switch (MCInst_getOpcode(Inst)) { |
1216 | 129 | case Mips_SWM32_MM: |
1217 | 504 | case Mips_LWM32_MM: |
1218 | 504 | if (DecodeRegListOperand(Inst, Insn, Address, Decoder) |
1219 | 504 | == MCDisassembler_Fail) |
1220 | 4 | return MCDisassembler_Fail; |
1221 | 500 | MCOperand_CreateReg0(Inst, Base); |
1222 | 500 | MCOperand_CreateImm0(Inst, Offset); |
1223 | 500 | break; |
1224 | 54 | case Mips_SC_MM: |
1225 | 54 | MCOperand_CreateReg0(Inst, Reg); |
1226 | | // fallthrough |
1227 | 799 | default: |
1228 | 799 | MCOperand_CreateReg0(Inst, Reg); |
1229 | 799 | if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) |
1230 | 499 | MCOperand_CreateReg0(Inst, Reg + 1); |
1231 | | |
1232 | 799 | MCOperand_CreateReg0(Inst, Base); |
1233 | 799 | MCOperand_CreateImm0(Inst, Offset); |
1234 | 1.30k | } |
1235 | | |
1236 | 1.29k | return MCDisassembler_Success; |
1237 | 1.30k | } |
1238 | | |
1239 | | static DecodeStatus DecodeMemMMImm16(MCInst *Inst, |
1240 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1241 | 4.69k | { |
1242 | 4.69k | int Offset = SignExtend32(Insn & 0xffff, 16); |
1243 | 4.69k | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1244 | 4.69k | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1245 | | |
1246 | 4.69k | Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
1247 | 4.69k | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1248 | | |
1249 | 4.69k | MCOperand_CreateReg0(Inst, Reg); |
1250 | 4.69k | MCOperand_CreateReg0(Inst, Base); |
1251 | 4.69k | MCOperand_CreateImm0(Inst, Offset); |
1252 | | |
1253 | 4.69k | return MCDisassembler_Success; |
1254 | 4.69k | } |
1255 | | |
1256 | | static DecodeStatus DecodeFMem(MCInst *Inst, |
1257 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1258 | 1.96k | { |
1259 | 1.96k | int Offset = SignExtend32(Insn & 0xffff, 16); |
1260 | 1.96k | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1261 | 1.96k | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1262 | | |
1263 | 1.96k | Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); |
1264 | 1.96k | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1265 | | |
1266 | 1.96k | MCOperand_CreateReg0(Inst, Reg); |
1267 | 1.96k | MCOperand_CreateReg0(Inst, Base); |
1268 | 1.96k | MCOperand_CreateImm0(Inst, Offset); |
1269 | | |
1270 | 1.96k | return MCDisassembler_Success; |
1271 | 1.96k | } |
1272 | | |
1273 | | static DecodeStatus DecodeFMem2(MCInst *Inst, |
1274 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1275 | 833 | { |
1276 | 833 | int Offset = SignExtend32(Insn & 0xffff, 16); |
1277 | 833 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1278 | 833 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1279 | | |
1280 | 833 | Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); |
1281 | 833 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1282 | | |
1283 | 833 | MCOperand_CreateReg0(Inst, Reg); |
1284 | 833 | MCOperand_CreateReg0(Inst, Base); |
1285 | 833 | MCOperand_CreateImm0(Inst, Offset); |
1286 | | |
1287 | 833 | return MCDisassembler_Success; |
1288 | 833 | } |
1289 | | |
1290 | | static DecodeStatus DecodeFMem3(MCInst *Inst, |
1291 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1292 | 0 | { |
1293 | 0 | int Offset = SignExtend32(Insn & 0xffff, 16); |
1294 | 0 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1295 | 0 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1296 | |
|
1297 | 0 | Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); |
1298 | 0 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1299 | |
|
1300 | 0 | MCOperand_CreateReg0(Inst, Reg); |
1301 | 0 | MCOperand_CreateReg0(Inst, Base); |
1302 | 0 | MCOperand_CreateImm0(Inst, Offset); |
1303 | |
|
1304 | 0 | return MCDisassembler_Success; |
1305 | 0 | } |
1306 | | |
1307 | | static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, |
1308 | | unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
1309 | 469 | { |
1310 | 469 | int Offset = SignExtend32(Insn & 0x07ff, 11); |
1311 | 469 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1312 | 469 | unsigned Base = fieldFromInstruction(Insn, 11, 5); |
1313 | | |
1314 | 469 | Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); |
1315 | 469 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1316 | | |
1317 | 469 | MCOperand_CreateReg0(Inst, Reg); |
1318 | 469 | MCOperand_CreateReg0(Inst, Base); |
1319 | 469 | MCOperand_CreateImm0(Inst, Offset); |
1320 | | |
1321 | 469 | return MCDisassembler_Success; |
1322 | 469 | } |
1323 | | |
1324 | | static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, |
1325 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1326 | 252 | { |
1327 | 252 | int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); |
1328 | 252 | unsigned Rt = fieldFromInstruction(Insn, 16, 5); |
1329 | 252 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1330 | | |
1331 | 252 | Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); |
1332 | 252 | Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
1333 | | |
1334 | 252 | if (MCInst_getOpcode(Inst) == Mips_SC_R6 || |
1335 | 252 | MCInst_getOpcode(Inst) == Mips_SCD_R6) { |
1336 | 189 | MCOperand_CreateReg0(Inst, Rt); |
1337 | 189 | } |
1338 | | |
1339 | 252 | MCOperand_CreateReg0(Inst, Rt); |
1340 | 252 | MCOperand_CreateReg0(Inst, Base); |
1341 | 252 | MCOperand_CreateImm0(Inst, Offset); |
1342 | | |
1343 | 252 | return MCDisassembler_Success; |
1344 | 252 | } |
1345 | | |
1346 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, |
1347 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1348 | 82 | { |
1349 | | // Currently only hardware register 29 is supported. |
1350 | 82 | if (RegNo != 29) |
1351 | 9 | return MCDisassembler_Fail; |
1352 | | |
1353 | 73 | MCOperand_CreateReg0(Inst, Mips_HWR29); |
1354 | | |
1355 | 73 | return MCDisassembler_Success; |
1356 | 82 | } |
1357 | | |
1358 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, |
1359 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1360 | 2.44k | { |
1361 | 2.44k | unsigned Reg; |
1362 | | |
1363 | 2.44k | if (RegNo > 30 || RegNo % 2) |
1364 | 49 | return MCDisassembler_Fail; |
1365 | | |
1366 | 2.39k | Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); |
1367 | 2.39k | MCOperand_CreateReg0(Inst, Reg); |
1368 | | |
1369 | 2.39k | return MCDisassembler_Success; |
1370 | 2.44k | } |
1371 | | |
1372 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, |
1373 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1374 | 1.09k | { |
1375 | 1.09k | unsigned Reg; |
1376 | | |
1377 | 1.09k | if (RegNo >= 4) |
1378 | 0 | return MCDisassembler_Fail; |
1379 | | |
1380 | 1.09k | Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); |
1381 | 1.09k | MCOperand_CreateReg0(Inst, Reg); |
1382 | 1.09k | return MCDisassembler_Success; |
1383 | 1.09k | } |
1384 | | |
1385 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, |
1386 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1387 | 50 | { |
1388 | 50 | unsigned Reg; |
1389 | | |
1390 | 50 | if (RegNo >= 4) |
1391 | 0 | return MCDisassembler_Fail; |
1392 | | |
1393 | 50 | Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); |
1394 | 50 | MCOperand_CreateReg0(Inst, Reg); |
1395 | | |
1396 | 50 | return MCDisassembler_Success; |
1397 | 50 | } |
1398 | | |
1399 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, |
1400 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1401 | 31 | { |
1402 | 31 | unsigned Reg; |
1403 | | |
1404 | 31 | if (RegNo >= 4) |
1405 | 0 | return MCDisassembler_Fail; |
1406 | | |
1407 | 31 | Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); |
1408 | 31 | MCOperand_CreateReg0(Inst, Reg); |
1409 | | |
1410 | 31 | return MCDisassembler_Success; |
1411 | 31 | } |
1412 | | |
1413 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, |
1414 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1415 | 6.80k | { |
1416 | 6.80k | unsigned Reg; |
1417 | | |
1418 | 6.80k | if (RegNo > 31) |
1419 | 0 | return MCDisassembler_Fail; |
1420 | | |
1421 | 6.80k | Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); |
1422 | 6.80k | MCOperand_CreateReg0(Inst, Reg); |
1423 | | |
1424 | 6.80k | return MCDisassembler_Success; |
1425 | 6.80k | } |
1426 | | |
1427 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, |
1428 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1429 | 7.01k | { |
1430 | 7.01k | unsigned Reg; |
1431 | | |
1432 | 7.01k | if (RegNo > 31) |
1433 | 0 | return MCDisassembler_Fail; |
1434 | | |
1435 | 7.01k | Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); |
1436 | 7.01k | MCOperand_CreateReg0(Inst, Reg); |
1437 | | |
1438 | 7.01k | return MCDisassembler_Success; |
1439 | 7.01k | } |
1440 | | |
1441 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, |
1442 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1443 | 5.55k | { |
1444 | 5.55k | unsigned Reg; |
1445 | | |
1446 | 5.55k | if (RegNo > 31) |
1447 | 0 | return MCDisassembler_Fail; |
1448 | | |
1449 | 5.55k | Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); |
1450 | 5.55k | MCOperand_CreateReg0(Inst, Reg); |
1451 | | |
1452 | 5.55k | return MCDisassembler_Success; |
1453 | 5.55k | } |
1454 | | |
1455 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, |
1456 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1457 | 3.74k | { |
1458 | 3.74k | unsigned Reg; |
1459 | | |
1460 | 3.74k | if (RegNo > 31) |
1461 | 0 | return MCDisassembler_Fail; |
1462 | | |
1463 | 3.74k | Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); |
1464 | 3.74k | MCOperand_CreateReg0(Inst, Reg); |
1465 | | |
1466 | 3.74k | return MCDisassembler_Success; |
1467 | 3.74k | } |
1468 | | |
1469 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, |
1470 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1471 | 157 | { |
1472 | 157 | unsigned Reg; |
1473 | | |
1474 | 157 | if (RegNo > 7) |
1475 | 3 | return MCDisassembler_Fail; |
1476 | | |
1477 | 154 | Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); |
1478 | 154 | MCOperand_CreateReg0(Inst, Reg); |
1479 | | |
1480 | 154 | return MCDisassembler_Success; |
1481 | 157 | } |
1482 | | |
1483 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, |
1484 | | unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) |
1485 | 95 | { |
1486 | 95 | unsigned Reg; |
1487 | | |
1488 | 95 | if (RegNo > 31) |
1489 | 0 | return MCDisassembler_Fail; |
1490 | | |
1491 | 95 | Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); |
1492 | 95 | MCOperand_CreateReg0(Inst, Reg); |
1493 | | |
1494 | 95 | return MCDisassembler_Success; |
1495 | 95 | } |
1496 | | |
1497 | | static DecodeStatus DecodeBranchTarget(MCInst *Inst, |
1498 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) |
1499 | 17.2k | { |
1500 | 17.2k | uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; |
1501 | 17.2k | MCOperand_CreateImm0(Inst, TargetAddress); |
1502 | | |
1503 | 17.2k | return MCDisassembler_Success; |
1504 | 17.2k | } |
1505 | | |
1506 | | static DecodeStatus DecodeJumpTarget(MCInst *Inst, |
1507 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1508 | 4.53k | { |
1509 | 4.53k | uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); |
1510 | 4.53k | MCOperand_CreateImm0(Inst, TargetAddress); |
1511 | | |
1512 | 4.53k | return MCDisassembler_Success; |
1513 | 4.53k | } |
1514 | | |
1515 | | static DecodeStatus DecodeBranchTarget21(MCInst *Inst, |
1516 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) |
1517 | 1.04k | { |
1518 | 1.04k | int32_t BranchOffset = SignExtend32(Offset, 21) * 4; |
1519 | | |
1520 | 1.04k | MCOperand_CreateImm0(Inst, BranchOffset); |
1521 | | |
1522 | 1.04k | return MCDisassembler_Success; |
1523 | 1.04k | } |
1524 | | |
1525 | | static DecodeStatus DecodeBranchTarget26(MCInst *Inst, |
1526 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) |
1527 | 535 | { |
1528 | 535 | int32_t BranchOffset = SignExtend32(Offset, 26) * 4; |
1529 | | |
1530 | 535 | MCOperand_CreateImm0(Inst, BranchOffset); |
1531 | 535 | return MCDisassembler_Success; |
1532 | 535 | } |
1533 | | |
1534 | | static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, |
1535 | | unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) |
1536 | 1.48k | { |
1537 | 1.48k | int32_t BranchOffset = SignExtend32(Offset, 7) * 2; |
1538 | 1.48k | MCOperand_CreateImm0(Inst, BranchOffset); |
1539 | 1.48k | return MCDisassembler_Success; |
1540 | 1.48k | } |
1541 | | |
1542 | | static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, |
1543 | | unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) |
1544 | 432 | { |
1545 | 432 | int32_t BranchOffset = SignExtend32(Offset, 10) * 2; |
1546 | 432 | MCOperand_CreateImm0(Inst, BranchOffset); |
1547 | 432 | return MCDisassembler_Success; |
1548 | 432 | } |
1549 | | |
1550 | | static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, |
1551 | | unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) |
1552 | 2.42k | { |
1553 | 2.42k | int32_t BranchOffset = SignExtend32(Offset, 16) * 2; |
1554 | 2.42k | MCOperand_CreateImm0(Inst, BranchOffset); |
1555 | | |
1556 | 2.42k | return MCDisassembler_Success; |
1557 | 2.42k | } |
1558 | | |
1559 | | static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, |
1560 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1561 | 1.61k | { |
1562 | 1.61k | unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; |
1563 | 1.61k | MCOperand_CreateImm0(Inst, JumpOffset); |
1564 | | |
1565 | 1.61k | return MCDisassembler_Success; |
1566 | 1.61k | } |
1567 | | |
1568 | | static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, |
1569 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) |
1570 | 1.41k | { |
1571 | 1.41k | if (Value == 0) |
1572 | 306 | MCOperand_CreateImm0(Inst, 1); |
1573 | 1.10k | else if (Value == 0x7) |
1574 | 475 | MCOperand_CreateImm0(Inst, -1); |
1575 | 633 | else |
1576 | 633 | MCOperand_CreateImm0(Inst, Value << 2); |
1577 | | |
1578 | 1.41k | return MCDisassembler_Success; |
1579 | 1.41k | } |
1580 | | |
1581 | | static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, |
1582 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) |
1583 | 385 | { |
1584 | 385 | MCOperand_CreateImm0(Inst, Value << 2); |
1585 | | |
1586 | 385 | return MCDisassembler_Success; |
1587 | 385 | } |
1588 | | |
1589 | | static DecodeStatus DecodeLiSimm7(MCInst *Inst, |
1590 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) |
1591 | 1.19k | { |
1592 | 1.19k | if (Value == 0x7F) |
1593 | 252 | MCOperand_CreateImm0(Inst, -1); |
1594 | 942 | else |
1595 | 942 | MCOperand_CreateImm0(Inst, Value); |
1596 | | |
1597 | 1.19k | return MCDisassembler_Success; |
1598 | 1.19k | } |
1599 | | |
1600 | | static DecodeStatus DecodeSimm4(MCInst *Inst, |
1601 | | unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) |
1602 | 712 | { |
1603 | 712 | MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); |
1604 | | |
1605 | 712 | return MCDisassembler_Success; |
1606 | 712 | } |
1607 | | |
1608 | | static DecodeStatus DecodeSimm16(MCInst *Inst, |
1609 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1610 | 9.61k | { |
1611 | 9.61k | MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); |
1612 | | |
1613 | 9.61k | return MCDisassembler_Success; |
1614 | 9.61k | } |
1615 | | |
1616 | | static DecodeStatus DecodeLSAImm(MCInst *Inst, |
1617 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1618 | 426 | { |
1619 | | // We add one to the immediate field as it was encoded as 'imm - 1'. |
1620 | 426 | MCOperand_CreateImm0(Inst, Insn + 1); |
1621 | | |
1622 | 426 | return MCDisassembler_Success; |
1623 | 426 | } |
1624 | | |
1625 | | static DecodeStatus DecodeInsSize(MCInst *Inst, |
1626 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1627 | 666 | { |
1628 | | // First we need to grab the pos(lsb) from MCInst. |
1629 | 666 | int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); |
1630 | 666 | int Size = (int) Insn - Pos + 1; |
1631 | 666 | MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); |
1632 | | |
1633 | 666 | return MCDisassembler_Success; |
1634 | 666 | } |
1635 | | |
1636 | | static DecodeStatus DecodeExtSize(MCInst *Inst, |
1637 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1638 | 730 | { |
1639 | 730 | int Size = (int)Insn + 1; |
1640 | | |
1641 | 730 | MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); |
1642 | | |
1643 | 730 | return MCDisassembler_Success; |
1644 | 730 | } |
1645 | | |
1646 | | static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, |
1647 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1648 | 438 | { |
1649 | 438 | MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); |
1650 | | |
1651 | 438 | return MCDisassembler_Success; |
1652 | 438 | } |
1653 | | |
1654 | | static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, |
1655 | | unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) |
1656 | 0 | { |
1657 | 0 | MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); |
1658 | |
|
1659 | 0 | return MCDisassembler_Success; |
1660 | 0 | } |
1661 | | |
1662 | | static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, |
1663 | | uint64_t Address, MCRegisterInfo *Decoder) |
1664 | 1.36k | { |
1665 | 1.36k | int32_t DecodedValue; |
1666 | | |
1667 | 1.36k | switch (Insn) { |
1668 | 90 | case 0: DecodedValue = 256; break; |
1669 | 61 | case 1: DecodedValue = 257; break; |
1670 | 233 | case 510: DecodedValue = -258; break; |
1671 | 61 | case 511: DecodedValue = -257; break; |
1672 | 916 | default: DecodedValue = SignExtend32(Insn, 9); break; |
1673 | 1.36k | } |
1674 | 1.36k | MCOperand_CreateImm0(Inst, DecodedValue * 4); |
1675 | | |
1676 | 1.36k | return MCDisassembler_Success; |
1677 | 1.36k | } |
1678 | | |
1679 | | static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, |
1680 | | uint64_t Address, MCRegisterInfo *Decoder) |
1681 | 1.07k | { |
1682 | | // Insn must be >= 0, since it is unsigned that condition is always true. |
1683 | | // assert(Insn < 16); |
1684 | 1.07k | int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, |
1685 | 1.07k | 255, 32768, 65535}; |
1686 | | |
1687 | 1.07k | if (Insn >= 16) |
1688 | 0 | return MCDisassembler_Fail; |
1689 | | |
1690 | 1.07k | MCOperand_CreateImm0(Inst, DecodedValues[Insn]); |
1691 | | |
1692 | 1.07k | return MCDisassembler_Success; |
1693 | 1.07k | } |
1694 | | |
1695 | | static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, |
1696 | | uint64_t Address, MCRegisterInfo *Decoder) |
1697 | 144 | { |
1698 | 144 | MCOperand_CreateImm0(Inst, Insn << 2); |
1699 | | |
1700 | 144 | return MCDisassembler_Success; |
1701 | 144 | } |
1702 | | |
1703 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, |
1704 | | uint64_t Address, const MCRegisterInfo *Decoder) |
1705 | 504 | { |
1706 | 504 | unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, |
1707 | 504 | Mips_S6, Mips_FP}; |
1708 | 504 | unsigned RegNum; |
1709 | 504 | unsigned int i; |
1710 | | |
1711 | 504 | unsigned RegLst = fieldFromInstruction(Insn, 21, 5); |
1712 | | // Empty register lists are not allowed. |
1713 | 504 | if (RegLst == 0) |
1714 | 4 | return MCDisassembler_Fail; |
1715 | | |
1716 | 500 | RegNum = RegLst & 0xf; |
1717 | 1.63k | for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) |
1718 | 1.13k | MCOperand_CreateReg0(Inst, Regs[i]); |
1719 | | |
1720 | 500 | if (RegLst & 0x10) |
1721 | 381 | MCOperand_CreateReg0(Inst, Mips_RA); |
1722 | | |
1723 | 500 | return MCDisassembler_Success; |
1724 | 504 | } |
1725 | | |
1726 | | static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, |
1727 | | uint64_t Address, MCRegisterInfo *Decoder) |
1728 | 1.28k | { |
1729 | 1.28k | unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; |
1730 | 1.28k | unsigned RegLst = fieldFromInstruction(Insn, 4, 2); |
1731 | 1.28k | unsigned RegNum = RegLst & 0x3; |
1732 | 1.28k | unsigned int i; |
1733 | | |
1734 | 3.74k | for (i = 0; i <= RegNum; i++) |
1735 | 2.46k | MCOperand_CreateReg0(Inst, Regs[i]); |
1736 | | |
1737 | 1.28k | MCOperand_CreateReg0(Inst, Mips_RA); |
1738 | | |
1739 | 1.28k | return MCDisassembler_Success; |
1740 | 1.28k | } |
1741 | | |
1742 | | static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, |
1743 | | uint64_t Address, MCRegisterInfo *Decoder) |
1744 | 535 | { |
1745 | 535 | unsigned RegPair = fieldFromInstruction(Insn, 7, 3); |
1746 | | |
1747 | 535 | switch (RegPair) { |
1748 | 0 | default: |
1749 | 0 | return MCDisassembler_Fail; |
1750 | 535 | case 0: |
1751 | 535 | MCOperand_CreateReg0(Inst, Mips_A1); |
1752 | 535 | MCOperand_CreateReg0(Inst, Mips_A2); |
1753 | 535 | break; |
1754 | 0 | case 1: |
1755 | 0 | MCOperand_CreateReg0(Inst, Mips_A1); |
1756 | 0 | MCOperand_CreateReg0(Inst, Mips_A3); |
1757 | 0 | break; |
1758 | 0 | case 2: |
1759 | 0 | MCOperand_CreateReg0(Inst, Mips_A2); |
1760 | 0 | MCOperand_CreateReg0(Inst, Mips_A3); |
1761 | 0 | break; |
1762 | 0 | case 3: |
1763 | 0 | MCOperand_CreateReg0(Inst, Mips_A0); |
1764 | 0 | MCOperand_CreateReg0(Inst, Mips_S5); |
1765 | 0 | break; |
1766 | 0 | case 4: |
1767 | 0 | MCOperand_CreateReg0(Inst, Mips_A0); |
1768 | 0 | MCOperand_CreateReg0(Inst, Mips_S6); |
1769 | 0 | break; |
1770 | 0 | case 5: |
1771 | 0 | MCOperand_CreateReg0(Inst, Mips_A0); |
1772 | 0 | MCOperand_CreateReg0(Inst, Mips_A1); |
1773 | 0 | break; |
1774 | 0 | case 6: |
1775 | 0 | MCOperand_CreateReg0(Inst, Mips_A0); |
1776 | 0 | MCOperand_CreateReg0(Inst, Mips_A2); |
1777 | 0 | break; |
1778 | 0 | case 7: |
1779 | 0 | MCOperand_CreateReg0(Inst, Mips_A0); |
1780 | 0 | MCOperand_CreateReg0(Inst, Mips_A3); |
1781 | 0 | break; |
1782 | 535 | } |
1783 | | |
1784 | 535 | return MCDisassembler_Success; |
1785 | 535 | } |
1786 | | |
1787 | | static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, |
1788 | | uint64_t Address, MCRegisterInfo *Decoder) |
1789 | 696 | { |
1790 | 696 | MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); |
1791 | 696 | return MCDisassembler_Success; |
1792 | 696 | } |
1793 | | |
1794 | | #endif |