/src/capstonenext/arch/Sparc/SparcDisassembler.c
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1 | | //===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | /* Capstone Disassembly Engine */ |
11 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
12 | | |
13 | | #ifdef CAPSTONE_HAS_SPARC |
14 | | |
15 | | #include <stdio.h> // DEBUG |
16 | | #include <stdlib.h> |
17 | | #include <string.h> |
18 | | |
19 | | #include "../../cs_priv.h" |
20 | | #include "../../utils.h" |
21 | | |
22 | | #include "SparcDisassembler.h" |
23 | | |
24 | | #include "../../MCInst.h" |
25 | | #include "../../MCInstrDesc.h" |
26 | | #include "../../MCFixedLenDisassembler.h" |
27 | | #include "../../MCRegisterInfo.h" |
28 | | #include "../../MCDisassembler.h" |
29 | | #include "../../MathExtras.h" |
30 | | |
31 | | |
32 | | #define GET_REGINFO_MC_DESC |
33 | | #define GET_REGINFO_ENUM |
34 | | #include "SparcGenRegisterInfo.inc" |
35 | | static const unsigned IntRegDecoderTable[] = { |
36 | | SP_G0, SP_G1, SP_G2, SP_G3, |
37 | | SP_G4, SP_G5, SP_G6, SP_G7, |
38 | | SP_O0, SP_O1, SP_O2, SP_O3, |
39 | | SP_O4, SP_O5, SP_O6, SP_O7, |
40 | | SP_L0, SP_L1, SP_L2, SP_L3, |
41 | | SP_L4, SP_L5, SP_L6, SP_L7, |
42 | | SP_I0, SP_I1, SP_I2, SP_I3, |
43 | | SP_I4, SP_I5, SP_I6, SP_I7 |
44 | | }; |
45 | | |
46 | | static const unsigned FPRegDecoderTable[] = { |
47 | | SP_F0, SP_F1, SP_F2, SP_F3, |
48 | | SP_F4, SP_F5, SP_F6, SP_F7, |
49 | | SP_F8, SP_F9, SP_F10, SP_F11, |
50 | | SP_F12, SP_F13, SP_F14, SP_F15, |
51 | | SP_F16, SP_F17, SP_F18, SP_F19, |
52 | | SP_F20, SP_F21, SP_F22, SP_F23, |
53 | | SP_F24, SP_F25, SP_F26, SP_F27, |
54 | | SP_F28, SP_F29, SP_F30, SP_F31 |
55 | | }; |
56 | | |
57 | | static const unsigned DFPRegDecoderTable[] = { |
58 | | SP_D0, SP_D16, SP_D1, SP_D17, |
59 | | SP_D2, SP_D18, SP_D3, SP_D19, |
60 | | SP_D4, SP_D20, SP_D5, SP_D21, |
61 | | SP_D6, SP_D22, SP_D7, SP_D23, |
62 | | SP_D8, SP_D24, SP_D9, SP_D25, |
63 | | SP_D10, SP_D26, SP_D11, SP_D27, |
64 | | SP_D12, SP_D28, SP_D13, SP_D29, |
65 | | SP_D14, SP_D30, SP_D15, SP_D31 |
66 | | }; |
67 | | |
68 | | static const unsigned QFPRegDecoderTable[] = { |
69 | | SP_Q0, SP_Q8, ~0U, ~0U, |
70 | | SP_Q1, SP_Q9, ~0U, ~0U, |
71 | | SP_Q2, SP_Q10, ~0U, ~0U, |
72 | | SP_Q3, SP_Q11, ~0U, ~0U, |
73 | | SP_Q4, SP_Q12, ~0U, ~0U, |
74 | | SP_Q5, SP_Q13, ~0U, ~0U, |
75 | | SP_Q6, SP_Q14, ~0U, ~0U, |
76 | | SP_Q7, SP_Q15, ~0U, ~0U |
77 | | }; |
78 | | |
79 | | static const unsigned FCCRegDecoderTable[] = { |
80 | | SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3 |
81 | | }; |
82 | | |
83 | | static uint64_t getFeatureBits(int mode) |
84 | 122k | { |
85 | | // support everything |
86 | 122k | return (uint64_t)-1; |
87 | 122k | } |
88 | | |
89 | | static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
90 | | uint64_t Address, const void *Decoder) |
91 | 50.1k | { |
92 | 50.1k | unsigned Reg; |
93 | | |
94 | 50.1k | if (RegNo > 31) |
95 | 0 | return MCDisassembler_Fail; |
96 | | |
97 | 50.1k | Reg = IntRegDecoderTable[RegNo]; |
98 | 50.1k | MCOperand_CreateReg0(Inst, Reg); |
99 | | |
100 | 50.1k | return MCDisassembler_Success; |
101 | 50.1k | } |
102 | | |
103 | | static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, |
104 | | uint64_t Address, const void *Decoder) |
105 | 7.51k | { |
106 | 7.51k | unsigned Reg; |
107 | | |
108 | 7.51k | if (RegNo > 31) |
109 | 0 | return MCDisassembler_Fail; |
110 | | |
111 | 7.51k | Reg = IntRegDecoderTable[RegNo]; |
112 | 7.51k | MCOperand_CreateReg0(Inst, Reg); |
113 | | |
114 | 7.51k | return MCDisassembler_Success; |
115 | 7.51k | } |
116 | | |
117 | | static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
118 | | uint64_t Address, const void *Decoder) |
119 | 6.39k | { |
120 | 6.39k | unsigned Reg; |
121 | | |
122 | 6.39k | if (RegNo > 31) |
123 | 0 | return MCDisassembler_Fail; |
124 | | |
125 | 6.39k | Reg = FPRegDecoderTable[RegNo]; |
126 | 6.39k | MCOperand_CreateReg0(Inst, Reg); |
127 | | |
128 | 6.39k | return MCDisassembler_Success; |
129 | 6.39k | } |
130 | | |
131 | | static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
132 | | uint64_t Address, const void *Decoder) |
133 | 9.96k | { |
134 | 9.96k | unsigned Reg; |
135 | | |
136 | 9.96k | if (RegNo > 31) |
137 | 0 | return MCDisassembler_Fail; |
138 | | |
139 | 9.96k | Reg = DFPRegDecoderTable[RegNo]; |
140 | 9.96k | MCOperand_CreateReg0(Inst, Reg); |
141 | | |
142 | 9.96k | return MCDisassembler_Success; |
143 | 9.96k | } |
144 | | |
145 | | static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
146 | | uint64_t Address, const void *Decoder) |
147 | 3.26k | { |
148 | 3.26k | unsigned Reg; |
149 | | |
150 | 3.26k | if (RegNo > 31) |
151 | 0 | return MCDisassembler_Fail; |
152 | | |
153 | 3.26k | Reg = QFPRegDecoderTable[RegNo]; |
154 | 3.26k | if (Reg == ~0U) |
155 | 36 | return MCDisassembler_Fail; |
156 | | |
157 | 3.22k | MCOperand_CreateReg0(Inst, Reg); |
158 | | |
159 | 3.22k | return MCDisassembler_Success; |
160 | 3.26k | } |
161 | | |
162 | | static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
163 | | uint64_t Address, const void *Decoder) |
164 | 11.5k | { |
165 | 11.5k | if (RegNo > 3) |
166 | 6 | return MCDisassembler_Fail; |
167 | | |
168 | 11.5k | MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]); |
169 | | |
170 | 11.5k | return MCDisassembler_Success; |
171 | 11.5k | } |
172 | | |
173 | | |
174 | | static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, |
175 | | const void *Decoder); |
176 | | static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, |
177 | | const void *Decoder); |
178 | | static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, |
179 | | const void *Decoder); |
180 | | static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, |
181 | | const void *Decoder); |
182 | | static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, |
183 | | uint64_t Address, const void *Decoder); |
184 | | static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, |
185 | | uint64_t Address, const void *Decoder); |
186 | | static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, |
187 | | uint64_t Address, const void *Decoder); |
188 | | static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, |
189 | | uint64_t Address, const void *Decoder); |
190 | | static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, |
191 | | uint64_t Address, const void *Decoder); |
192 | | static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, |
193 | | uint64_t Address, const void *Decoder); |
194 | | static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, |
195 | | const void *Decoder); |
196 | | static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, |
197 | | const void *Decoder); |
198 | | static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address, |
199 | | const void *Decoder); |
200 | | |
201 | | |
202 | | #define GET_SUBTARGETINFO_ENUM |
203 | | #include "SparcGenSubtargetInfo.inc" |
204 | | #include "SparcGenDisassemblerTables.inc" |
205 | | |
206 | | /// readInstruction - read four bytes and return 32 bit word. |
207 | | static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn) |
208 | 123k | { |
209 | 123k | if (len < 4) |
210 | | // not enough data |
211 | 1.01k | return MCDisassembler_Fail; |
212 | | |
213 | | // Encoded as a big-endian 32-bit word in the stream. |
214 | 122k | *Insn = (code[3] << 0) | |
215 | 122k | (code[2] << 8) | |
216 | 122k | (code[1] << 16) | |
217 | 122k | ((uint32_t) code[0] << 24); |
218 | | |
219 | 122k | return MCDisassembler_Success; |
220 | 123k | } |
221 | | |
222 | | bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, |
223 | | uint16_t *size, uint64_t address, void *info) |
224 | 123k | { |
225 | 123k | uint32_t Insn; |
226 | 123k | DecodeStatus Result; |
227 | | |
228 | 123k | Result = readInstruction32(code, code_len, &Insn); |
229 | 123k | if (Result == MCDisassembler_Fail) |
230 | 1.01k | return false; |
231 | | |
232 | 122k | if (MI->flat_insn->detail) { |
233 | 122k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc)); |
234 | 122k | } |
235 | | |
236 | 122k | Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, |
237 | 122k | (MCRegisterInfo *)info, 0); |
238 | 122k | if (Result != MCDisassembler_Fail) { |
239 | 121k | *size = 4; |
240 | 121k | return true; |
241 | 121k | } |
242 | | |
243 | 1.04k | return false; |
244 | 122k | } |
245 | | |
246 | | typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, |
247 | | const void *Decoder); |
248 | | |
249 | | static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, |
250 | | const void *Decoder, |
251 | | bool isLoad, DecodeFunc DecodeRD) |
252 | 3.79k | { |
253 | 3.79k | DecodeStatus status; |
254 | 3.79k | unsigned rd = fieldFromInstruction_4(insn, 25, 5); |
255 | 3.79k | unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); |
256 | 3.79k | bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0; |
257 | 3.79k | unsigned rs2 = 0; |
258 | 3.79k | unsigned simm13 = 0; |
259 | | |
260 | 3.79k | if (isImm) |
261 | 2.64k | simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); |
262 | 1.14k | else |
263 | 1.14k | rs2 = fieldFromInstruction_4(insn, 0, 5); |
264 | | |
265 | 3.79k | if (isLoad) { |
266 | 1.91k | status = DecodeRD(MI, rd, Address, Decoder); |
267 | 1.91k | if (status != MCDisassembler_Success) |
268 | 2 | return status; |
269 | 1.91k | } |
270 | | |
271 | | // Decode rs1. |
272 | 3.79k | status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); |
273 | 3.79k | if (status != MCDisassembler_Success) |
274 | 0 | return status; |
275 | | |
276 | | // Decode imm|rs2. |
277 | 3.79k | if (isImm) |
278 | 2.64k | MCOperand_CreateImm0(MI, simm13); |
279 | 1.14k | else { |
280 | 1.14k | status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); |
281 | 1.14k | if (status != MCDisassembler_Success) |
282 | 0 | return status; |
283 | 1.14k | } |
284 | | |
285 | 3.79k | if (!isLoad) { |
286 | 1.87k | status = DecodeRD(MI, rd, Address, Decoder); |
287 | 1.87k | if (status != MCDisassembler_Success) |
288 | 2 | return status; |
289 | 1.87k | } |
290 | | |
291 | 3.78k | return MCDisassembler_Success; |
292 | 3.79k | } |
293 | | |
294 | | static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, |
295 | | const void *Decoder) |
296 | 401 | { |
297 | 401 | return DecodeMem(Inst, insn, Address, Decoder, true, |
298 | 401 | DecodeIntRegsRegisterClass); |
299 | 401 | } |
300 | | |
301 | | static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, |
302 | | const void *Decoder) |
303 | 1.11k | { |
304 | 1.11k | return DecodeMem(Inst, insn, Address, Decoder, true, |
305 | 1.11k | DecodeFPRegsRegisterClass); |
306 | 1.11k | } |
307 | | |
308 | | static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, |
309 | | const void *Decoder) |
310 | 247 | { |
311 | 247 | return DecodeMem(Inst, insn, Address, Decoder, true, |
312 | 247 | DecodeDFPRegsRegisterClass); |
313 | 247 | } |
314 | | |
315 | | static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, |
316 | | const void *Decoder) |
317 | 149 | { |
318 | 149 | return DecodeMem(Inst, insn, Address, Decoder, true, |
319 | 149 | DecodeQFPRegsRegisterClass); |
320 | 149 | } |
321 | | |
322 | | static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, |
323 | | uint64_t Address, const void *Decoder) |
324 | 340 | { |
325 | 340 | return DecodeMem(Inst, insn, Address, Decoder, false, |
326 | 340 | DecodeIntRegsRegisterClass); |
327 | 340 | } |
328 | | |
329 | | static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, |
330 | | const void *Decoder) |
331 | 442 | { |
332 | 442 | return DecodeMem(Inst, insn, Address, Decoder, false, |
333 | 442 | DecodeFPRegsRegisterClass); |
334 | 442 | } |
335 | | |
336 | | static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, |
337 | | uint64_t Address, const void *Decoder) |
338 | 260 | { |
339 | 260 | return DecodeMem(Inst, insn, Address, Decoder, false, |
340 | 260 | DecodeDFPRegsRegisterClass); |
341 | 260 | } |
342 | | |
343 | | static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, |
344 | | uint64_t Address, const void *Decoder) |
345 | 835 | { |
346 | 835 | return DecodeMem(Inst, insn, Address, Decoder, false, |
347 | 835 | DecodeQFPRegsRegisterClass); |
348 | 835 | } |
349 | | |
350 | | static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, |
351 | | uint64_t Address, const void *Decoder) |
352 | 32.6k | { |
353 | 32.6k | unsigned tgt = fieldFromInstruction_4(insn, 0, 30); |
354 | 32.6k | tgt <<= 2; |
355 | | |
356 | 32.6k | MCOperand_CreateImm0(MI, tgt); |
357 | | |
358 | 32.6k | return MCDisassembler_Success; |
359 | 32.6k | } |
360 | | |
361 | | static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, |
362 | | uint64_t Address, const void *Decoder) |
363 | 3.97k | { |
364 | 3.97k | unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); |
365 | | |
366 | 3.97k | MCOperand_CreateImm0(MI, tgt); |
367 | | |
368 | 3.97k | return MCDisassembler_Success; |
369 | 3.97k | } |
370 | | |
371 | | static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, |
372 | | const void *Decoder) |
373 | 779 | { |
374 | 779 | DecodeStatus status; |
375 | 779 | unsigned rd = fieldFromInstruction_4(insn, 25, 5); |
376 | 779 | unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); |
377 | 779 | unsigned isImm = fieldFromInstruction_4(insn, 13, 1); |
378 | 779 | unsigned rs2 = 0; |
379 | 779 | unsigned simm13 = 0; |
380 | | |
381 | 779 | if (isImm) |
382 | 468 | simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); |
383 | 311 | else |
384 | 311 | rs2 = fieldFromInstruction_4(insn, 0, 5); |
385 | | |
386 | | // Decode RD. |
387 | 779 | status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); |
388 | 779 | if (status != MCDisassembler_Success) |
389 | 0 | return status; |
390 | | |
391 | | // Decode RS1. |
392 | 779 | status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); |
393 | 779 | if (status != MCDisassembler_Success) |
394 | 0 | return status; |
395 | | |
396 | | // Decode RS1 | SIMM13. |
397 | 779 | if (isImm) |
398 | 468 | MCOperand_CreateImm0(MI, simm13); |
399 | 311 | else { |
400 | 311 | status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); |
401 | 311 | if (status != MCDisassembler_Success) |
402 | 0 | return status; |
403 | 311 | } |
404 | | |
405 | 779 | return MCDisassembler_Success; |
406 | 779 | } |
407 | | |
408 | | static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, |
409 | | const void *Decoder) |
410 | 766 | { |
411 | 766 | DecodeStatus status; |
412 | 766 | unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); |
413 | 766 | unsigned isImm = fieldFromInstruction_4(insn, 13, 1); |
414 | 766 | unsigned rs2 = 0; |
415 | 766 | unsigned simm13 = 0; |
416 | 766 | if (isImm) |
417 | 215 | simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); |
418 | 551 | else |
419 | 551 | rs2 = fieldFromInstruction_4(insn, 0, 5); |
420 | | |
421 | | // Decode RS1. |
422 | 766 | status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); |
423 | 766 | if (status != MCDisassembler_Success) |
424 | 0 | return status; |
425 | | |
426 | | // Decode RS2 | SIMM13. |
427 | 766 | if (isImm) |
428 | 215 | MCOperand_CreateImm0(MI, simm13); |
429 | 551 | else { |
430 | 551 | status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); |
431 | 551 | if (status != MCDisassembler_Success) |
432 | 0 | return status; |
433 | 551 | } |
434 | | |
435 | 766 | return MCDisassembler_Success; |
436 | 766 | } |
437 | | |
438 | | static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address, |
439 | | const void *Decoder) |
440 | 826 | { |
441 | 826 | DecodeStatus status; |
442 | 826 | unsigned rd = fieldFromInstruction_4(insn, 25, 5); |
443 | 826 | unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); |
444 | 826 | unsigned isImm = fieldFromInstruction_4(insn, 13, 1); |
445 | 826 | unsigned rs2 = 0; |
446 | 826 | unsigned simm13 = 0; |
447 | | |
448 | 826 | if (isImm) |
449 | 771 | simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); |
450 | 55 | else |
451 | 55 | rs2 = fieldFromInstruction_4(insn, 0, 5); |
452 | | |
453 | | // Decode RD. |
454 | 826 | status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); |
455 | 826 | if (status != MCDisassembler_Success) |
456 | 0 | return status; |
457 | | |
458 | | // Decode RS1. |
459 | 826 | status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); |
460 | 826 | if (status != MCDisassembler_Success) |
461 | 0 | return status; |
462 | | |
463 | | // Decode RS1 | SIMM13. |
464 | 826 | if (isImm) |
465 | 771 | MCOperand_CreateImm0(MI, simm13); |
466 | 55 | else { |
467 | 55 | status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); |
468 | 55 | if (status != MCDisassembler_Success) |
469 | 0 | return status; |
470 | 55 | } |
471 | | |
472 | 826 | return MCDisassembler_Success; |
473 | 826 | } |
474 | | |
475 | | void Sparc_init(MCRegisterInfo *MRI) |
476 | 3.04k | { |
477 | | /* |
478 | | InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, |
479 | | SparcMCRegisterClasses, 8, |
480 | | SparcRegUnitRoots, |
481 | | 86, |
482 | | SparcRegDiffLists, |
483 | | SparcRegStrings, |
484 | | SparcSubRegIdxLists, |
485 | | 7, |
486 | | SparcSubRegIdxRanges, |
487 | | SparcRegEncodingTable); |
488 | | */ |
489 | | |
490 | 3.04k | MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119, |
491 | 3.04k | 0, 0, |
492 | 3.04k | SparcMCRegisterClasses, 8, |
493 | 3.04k | 0, 0, |
494 | 3.04k | SparcRegDiffLists, |
495 | 3.04k | 0, |
496 | 3.04k | SparcSubRegIdxLists, 7, |
497 | 3.04k | 0); |
498 | 3.04k | } |
499 | | |
500 | | #endif |