/src/capstonenext/arch/Sparc/SparcInstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This class prints an Sparc MCInst to a .s file. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | /* Capstone Disassembly Engine */ |
15 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
16 | | |
17 | | #ifdef CAPSTONE_HAS_SPARC |
18 | | |
19 | | #ifdef _MSC_VER |
20 | | #define _CRT_SECURE_NO_WARNINGS |
21 | | #endif |
22 | | |
23 | | #include <stdio.h> |
24 | | #include <stdlib.h> |
25 | | #include <string.h> |
26 | | #include <limits.h> |
27 | | |
28 | | #include "SparcInstPrinter.h" |
29 | | #include "../../MCInst.h" |
30 | | #include "../../utils.h" |
31 | | #include "../../SStream.h" |
32 | | #include "../../MCRegisterInfo.h" |
33 | | #include "../../MathExtras.h" |
34 | | #include "SparcMapping.h" |
35 | | |
36 | | #include "Sparc.h" |
37 | | |
38 | | static const char *getRegisterName(unsigned RegNo); |
39 | | static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); |
40 | | static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier); |
41 | | static void printOperand(MCInst *MI, int opNum, SStream *O); |
42 | | |
43 | | static void Sparc_add_hint(MCInst *MI, unsigned int hint) |
44 | 2.44k | { |
45 | 2.44k | if (MI->csh->detail_opt) { |
46 | 2.44k | MI->flat_insn->detail->sparc.hint = hint; |
47 | 2.44k | } |
48 | 2.44k | } |
49 | | |
50 | | static void Sparc_add_reg(MCInst *MI, unsigned int reg) |
51 | 8.71k | { |
52 | 8.71k | if (MI->csh->detail_opt) { |
53 | 8.71k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; |
54 | 8.71k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; |
55 | 8.71k | MI->flat_insn->detail->sparc.op_count++; |
56 | 8.71k | } |
57 | 8.71k | } |
58 | | |
59 | | static void set_mem_access(MCInst *MI, bool status) |
60 | 12.2k | { |
61 | 12.2k | if (MI->csh->detail_opt != CS_OPT_ON) |
62 | 0 | return; |
63 | | |
64 | 12.2k | MI->csh->doing_mem = status; |
65 | | |
66 | 12.2k | if (status) { |
67 | 6.12k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM; |
68 | 6.12k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID; |
69 | 6.12k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0; |
70 | 6.12k | } else { |
71 | | // done, create the next operand slot |
72 | 6.12k | MI->flat_insn->detail->sparc.op_count++; |
73 | 6.12k | } |
74 | 12.2k | } |
75 | | |
76 | | void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) |
77 | 121k | { |
78 | 121k | if (((cs_struct *)ud)->detail_opt != CS_OPT_ON) |
79 | 0 | return; |
80 | | |
81 | | // fix up some instructions |
82 | 121k | if (insn->id == SPARC_INS_CASX) { |
83 | | // first op is actually a memop, not regop |
84 | 17 | insn->detail->sparc.operands[0].type = SPARC_OP_MEM; |
85 | 17 | insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg; |
86 | 17 | insn->detail->sparc.operands[0].mem.disp = 0; |
87 | 17 | } |
88 | 121k | } |
89 | | |
90 | | static void printRegName(SStream *OS, unsigned RegNo) |
91 | 79.8k | { |
92 | 79.8k | SStream_concat0(OS, "%"); |
93 | 79.8k | SStream_concat0(OS, getRegisterName(RegNo)); |
94 | 79.8k | } |
95 | | |
96 | | #define GET_INSTRINFO_ENUM |
97 | | #include "SparcGenInstrInfo.inc" |
98 | | |
99 | | #define GET_REGINFO_ENUM |
100 | | #include "SparcGenRegisterInfo.inc" |
101 | | |
102 | | static bool printSparcAliasInstr(MCInst *MI, SStream *O) |
103 | 84.0k | { |
104 | 84.0k | switch (MCInst_getOpcode(MI)) { |
105 | 82.2k | default: return false; |
106 | 311 | case SP_JMPLrr: |
107 | 779 | case SP_JMPLri: |
108 | 779 | if (MCInst_getNumOperands(MI) != 3) |
109 | 0 | return false; |
110 | 779 | if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) |
111 | 0 | return false; |
112 | | |
113 | 779 | switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { |
114 | 174 | default: return false; |
115 | 585 | case SP_G0: // jmp $addr | ret | retl |
116 | 585 | if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
117 | 585 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { |
118 | 92 | switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
119 | 61 | default: break; |
120 | 61 | case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true; |
121 | 13 | case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true; |
122 | 92 | } |
123 | 92 | } |
124 | | |
125 | 554 | SStream_concat0(O, "jmp\t"); |
126 | 554 | MCInst_setOpcodePub(MI, SPARC_INS_JMP); |
127 | 554 | printMemOperand(MI, 1, O, NULL); |
128 | 554 | return true; |
129 | 20 | case SP_O7: // call $addr |
130 | 20 | SStream_concat0(O, "call "); |
131 | 20 | MCInst_setOpcodePub(MI, SPARC_INS_CALL); |
132 | 20 | printMemOperand(MI, 1, O, NULL); |
133 | 20 | return true; |
134 | 779 | } |
135 | 45 | case SP_V9FCMPS: |
136 | 235 | case SP_V9FCMPD: |
137 | 399 | case SP_V9FCMPQ: |
138 | 972 | case SP_V9FCMPES: |
139 | 1.00k | case SP_V9FCMPED: |
140 | 1.04k | case SP_V9FCMPEQ: |
141 | 1.04k | if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || |
142 | 1.04k | (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || |
143 | 1.04k | (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) |
144 | 1.04k | return false; |
145 | | // if V8, skip printing %fcc0. |
146 | 0 | switch(MCInst_getOpcode(MI)) { |
147 | 0 | default: |
148 | 0 | case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break; |
149 | 0 | case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break; |
150 | 0 | case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break; |
151 | 0 | case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break; |
152 | 0 | case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break; |
153 | 0 | case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break; |
154 | 0 | } |
155 | 0 | printOperand(MI, 1, O); |
156 | 0 | SStream_concat0(O, ", "); |
157 | 0 | printOperand(MI, 2, O); |
158 | 0 | return true; |
159 | 84.0k | } |
160 | 84.0k | } |
161 | | |
162 | | static void printOperand(MCInst *MI, int opNum, SStream *O) |
163 | 183k | { |
164 | 183k | int64_t Imm; |
165 | 183k | unsigned reg; |
166 | 183k | MCOperand *MO = MCInst_getOperand(MI, opNum); |
167 | | |
168 | 183k | if (MCOperand_isReg(MO)) { |
169 | 79.8k | reg = MCOperand_getReg(MO); |
170 | 79.8k | printRegName(O, reg); |
171 | 79.8k | reg = Sparc_map_register(reg); |
172 | | |
173 | 79.8k | if (MI->csh->detail_opt) { |
174 | 79.8k | if (MI->csh->doing_mem) { |
175 | 7.63k | if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base) |
176 | 1.50k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg; |
177 | 6.12k | else |
178 | 6.12k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg; |
179 | 72.1k | } else { |
180 | 72.1k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; |
181 | 72.1k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; |
182 | 72.1k | MI->flat_insn->detail->sparc.op_count++; |
183 | 72.1k | } |
184 | 79.8k | } |
185 | | |
186 | 79.8k | return; |
187 | 79.8k | } |
188 | | |
189 | 103k | if (MCOperand_isImm(MO)) { |
190 | 103k | Imm = (int)MCOperand_getImm(MO); |
191 | | |
192 | | // Conditional branches displacements needs to be signextended to be |
193 | | // able to jump backwards. |
194 | | // |
195 | | // Displacements are measured as the number of instructions forward or |
196 | | // backward, so they need to be multiplied by 4 |
197 | 103k | switch (MI->Opcode) { |
198 | 32.6k | case SP_CALL: |
199 | | // Imm = SignExtend32(Imm, 30); |
200 | 32.6k | Imm += MI->address; |
201 | 32.6k | break; |
202 | | |
203 | | // Branch on integer condition with prediction (BPcc) |
204 | | // Branch on floating point condition with prediction (FBPfcc) |
205 | 541 | case SP_BPICC: |
206 | 831 | case SP_BPICCA: |
207 | 4.28k | case SP_BPICCANT: |
208 | 8.17k | case SP_BPICCNT: |
209 | 8.91k | case SP_BPXCC: |
210 | 9.38k | case SP_BPXCCA: |
211 | 12.1k | case SP_BPXCCANT: |
212 | 15.8k | case SP_BPXCCNT: |
213 | 16.4k | case SP_BPFCC: |
214 | 17.3k | case SP_BPFCCA: |
215 | 20.7k | case SP_BPFCCANT: |
216 | 24.8k | case SP_BPFCCNT: |
217 | 24.8k | Imm = SignExtend32(Imm, 19); |
218 | 24.8k | Imm = MI->address + Imm * 4; |
219 | 24.8k | break; |
220 | | |
221 | | // Branch on integer condition (Bicc) |
222 | | // Branch on floating point condition (FBfcc) |
223 | 756 | case SP_BA: |
224 | 6.06k | case SP_BCOND: |
225 | 9.60k | case SP_BCONDA: |
226 | 10.8k | case SP_FBCOND: |
227 | 11.6k | case SP_FBCONDA: |
228 | 11.6k | Imm = SignExtend32(Imm, 22); |
229 | 11.6k | Imm = MI->address + Imm * 4; |
230 | 11.6k | break; |
231 | | |
232 | | // Branch on integer register with prediction (BPr) |
233 | 121 | case SP_BPGEZapn: |
234 | 166 | case SP_BPGEZapt: |
235 | 625 | case SP_BPGEZnapn: |
236 | 687 | case SP_BPGEZnapt: |
237 | 725 | case SP_BPGZapn: |
238 | 815 | case SP_BPGZapt: |
239 | 930 | case SP_BPGZnapn: |
240 | 1.18k | case SP_BPGZnapt: |
241 | 1.23k | case SP_BPLEZapn: |
242 | 1.32k | case SP_BPLEZapt: |
243 | 1.44k | case SP_BPLEZnapn: |
244 | 1.59k | case SP_BPLEZnapt: |
245 | 1.64k | case SP_BPLZapn: |
246 | 2.20k | case SP_BPLZapt: |
247 | 2.47k | case SP_BPLZnapn: |
248 | 2.51k | case SP_BPLZnapt: |
249 | 2.63k | case SP_BPNZapn: |
250 | 2.71k | case SP_BPNZapt: |
251 | 2.90k | case SP_BPNZnapn: |
252 | 3.15k | case SP_BPNZnapt: |
253 | 3.19k | case SP_BPZapn: |
254 | 3.32k | case SP_BPZapt: |
255 | 3.38k | case SP_BPZnapn: |
256 | 3.61k | case SP_BPZnapt: |
257 | 3.61k | Imm = SignExtend32(Imm, 16); |
258 | 3.61k | Imm = MI->address + Imm * 4; |
259 | 3.61k | break; |
260 | 103k | } |
261 | | |
262 | 103k | printInt64(O, Imm); |
263 | | |
264 | 103k | if (MI->csh->detail_opt) { |
265 | 103k | if (MI->csh->doing_mem) { |
266 | 4.00k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm; |
267 | 99.8k | } else { |
268 | 99.8k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM; |
269 | 99.8k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm; |
270 | 99.8k | MI->flat_insn->detail->sparc.op_count++; |
271 | 99.8k | } |
272 | 103k | } |
273 | 103k | } |
274 | | |
275 | 103k | return; |
276 | 103k | } |
277 | | |
278 | | static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier) |
279 | 6.12k | { |
280 | 6.12k | MCOperand *MO; |
281 | | |
282 | 6.12k | set_mem_access(MI, true); |
283 | 6.12k | printOperand(MI, opNum, O); |
284 | | |
285 | | // If this is an ADD operand, emit it like normal operands. |
286 | 6.12k | if (Modifier && !strcmp(Modifier, "arith")) { |
287 | 0 | SStream_concat0(O, ", "); |
288 | 0 | printOperand(MI, opNum + 1, O); |
289 | 0 | set_mem_access(MI, false); |
290 | 0 | return; |
291 | 0 | } |
292 | | |
293 | 6.12k | MO = MCInst_getOperand(MI, opNum + 1); |
294 | | |
295 | 6.12k | if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { |
296 | 554 | set_mem_access(MI, false); |
297 | 554 | return; // don't print "+%g0" |
298 | 554 | } |
299 | | |
300 | 5.57k | if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { |
301 | 63 | set_mem_access(MI, false); |
302 | 63 | return; // don't print "+0" |
303 | 63 | } |
304 | | |
305 | 5.51k | SStream_concat0(O, "+"); // qq |
306 | | |
307 | 5.51k | printOperand(MI, opNum + 1, O); |
308 | 5.51k | set_mem_access(MI, false); |
309 | 5.51k | } |
310 | | |
311 | | static void printCCOperand(MCInst *MI, int opNum, SStream *O) |
312 | 12.6k | { |
313 | 12.6k | int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256; |
314 | | |
315 | 12.6k | switch (MCInst_getOpcode(MI)) { |
316 | 6.84k | default: break; |
317 | 6.84k | case SP_FBCOND: |
318 | 2.01k | case SP_FBCONDA: |
319 | 2.64k | case SP_BPFCC: |
320 | 3.52k | case SP_BPFCCA: |
321 | 3.52k | case SP_BPFCCNT: |
322 | 3.52k | case SP_BPFCCANT: |
323 | 4.01k | case SP_MOVFCCrr: case SP_V9MOVFCCrr: |
324 | 4.86k | case SP_MOVFCCri: case SP_V9MOVFCCri: |
325 | 5.17k | case SP_FMOVS_FCC: case SP_V9FMOVS_FCC: |
326 | 5.67k | case SP_FMOVD_FCC: case SP_V9FMOVD_FCC: |
327 | 5.81k | case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC: |
328 | | // Make sure CC is a fp conditional flag. |
329 | 5.81k | CC = (CC < 16+256) ? (CC + 16) : CC; |
330 | 5.81k | break; |
331 | 12.6k | } |
332 | | |
333 | 12.6k | SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); |
334 | | |
335 | 12.6k | if (MI->csh->detail_opt) |
336 | 12.6k | MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; |
337 | 12.6k | } |
338 | | |
339 | | |
340 | | static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) |
341 | 0 | { |
342 | 0 | return true; |
343 | 0 | } |
344 | | |
345 | | |
346 | | #define PRINT_ALIAS_INSTR |
347 | | #include "SparcGenAsmWriter.inc" |
348 | | |
349 | | void Sparc_printInst(MCInst *MI, SStream *O, void *Info) |
350 | 121k | { |
351 | 121k | char *mnem, *p; |
352 | 121k | char instr[64]; // Sparc has no instruction this long |
353 | | |
354 | 121k | mnem = printAliasInstr(MI, O, Info); |
355 | 121k | if (mnem) { |
356 | | // fixup instruction id due to the change in alias instruction |
357 | 37.0k | unsigned cpy_len = sizeof(instr) - 1 < strlen(mnem) ? sizeof(instr) - 1 : strlen(mnem); |
358 | 37.0k | memcpy(instr, mnem, cpy_len); |
359 | 37.0k | instr[cpy_len] = '\0'; |
360 | | // does this contains hint with a coma? |
361 | 37.0k | p = strchr(instr, ','); |
362 | 37.0k | if (p) |
363 | 24.8k | *p = '\0'; // now instr only has instruction mnemonic |
364 | 37.0k | MCInst_setOpcodePub(MI, Sparc_map_insn(instr)); |
365 | 37.0k | switch(MCInst_getOpcode(MI)) { |
366 | 5.30k | case SP_BCOND: |
367 | 8.84k | case SP_BCONDA: |
368 | 12.3k | case SP_BPICCANT: |
369 | 16.1k | case SP_BPICCNT: |
370 | 18.9k | case SP_BPXCCANT: |
371 | 22.6k | case SP_BPXCCNT: |
372 | 24.3k | case SP_TXCCri: |
373 | 28.8k | case SP_TXCCrr: |
374 | 28.8k | if (MI->csh->detail_opt) { |
375 | | // skip 'b', 't' |
376 | 28.8k | MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1); |
377 | 28.8k | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
378 | 28.8k | } |
379 | 28.8k | break; |
380 | 3.45k | case SP_BPFCCANT: |
381 | 7.51k | case SP_BPFCCNT: |
382 | 7.51k | if (MI->csh->detail_opt) { |
383 | | // skip 'fb' |
384 | 7.51k | MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2); |
385 | 7.51k | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
386 | 7.51k | } |
387 | 7.51k | break; |
388 | 0 | case SP_FMOVD_ICC: |
389 | 0 | case SP_FMOVD_XCC: |
390 | 0 | case SP_FMOVQ_ICC: |
391 | 0 | case SP_FMOVQ_XCC: |
392 | 0 | case SP_FMOVS_ICC: |
393 | 0 | case SP_FMOVS_XCC: |
394 | 0 | if (MI->csh->detail_opt) { |
395 | | // skip 'fmovd', 'fmovq', 'fmovs' |
396 | 0 | MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5); |
397 | 0 | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
398 | 0 | } |
399 | 0 | break; |
400 | 0 | case SP_MOVICCri: |
401 | 0 | case SP_MOVICCrr: |
402 | 0 | case SP_MOVXCCri: |
403 | 0 | case SP_MOVXCCrr: |
404 | 0 | if (MI->csh->detail_opt) { |
405 | | // skip 'mov' |
406 | 0 | MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3); |
407 | 0 | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
408 | 0 | } |
409 | 0 | break; |
410 | 0 | case SP_V9FMOVD_FCC: |
411 | 0 | case SP_V9FMOVQ_FCC: |
412 | 0 | case SP_V9FMOVS_FCC: |
413 | 0 | if (MI->csh->detail_opt) { |
414 | | // skip 'fmovd', 'fmovq', 'fmovs' |
415 | 0 | MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5); |
416 | 0 | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
417 | 0 | } |
418 | 0 | break; |
419 | 0 | case SP_V9MOVFCCri: |
420 | 0 | case SP_V9MOVFCCrr: |
421 | 0 | if (MI->csh->detail_opt) { |
422 | | // skip 'mov' |
423 | 0 | MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3); |
424 | 0 | MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); |
425 | 0 | } |
426 | 0 | break; |
427 | 705 | default: |
428 | 705 | break; |
429 | 37.0k | } |
430 | 37.0k | cs_mem_free(mnem); |
431 | 84.0k | } else { |
432 | 84.0k | if (!printSparcAliasInstr(MI, O)) |
433 | 83.4k | printInstruction(MI, O, NULL); |
434 | 84.0k | } |
435 | 121k | } |
436 | | |
437 | | void Sparc_addReg(MCInst *MI, int reg) |
438 | 19.9k | { |
439 | 19.9k | if (MI->csh->detail_opt) { |
440 | 19.9k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; |
441 | 19.9k | MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; |
442 | 19.9k | MI->flat_insn->detail->sparc.op_count++; |
443 | 19.9k | } |
444 | 19.9k | } |
445 | | |
446 | | #endif |