/src/capstonenext/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |*Assembly Writer Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #include <stdio.h> |
10 | | |
11 | | /// printInstruction - This method is automatically generated by tablegen |
12 | | /// from the instruction set description. |
13 | 67.2k | static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { |
14 | 67.2k | static const uint32_t OpInfo[] = { |
15 | 67.2k | 0U, // PHI |
16 | 67.2k | 0U, // INLINEASM |
17 | 67.2k | 0U, // CFI_INSTRUCTION |
18 | 67.2k | 0U, // EH_LABEL |
19 | 67.2k | 0U, // GC_LABEL |
20 | 67.2k | 0U, // KILL |
21 | 67.2k | 0U, // EXTRACT_SUBREG |
22 | 67.2k | 0U, // INSERT_SUBREG |
23 | 67.2k | 0U, // IMPLICIT_DEF |
24 | 67.2k | 0U, // SUBREG_TO_REG |
25 | 67.2k | 0U, // COPY_TO_REGCLASS |
26 | 67.2k | 882U, // DBG_VALUE |
27 | 67.2k | 0U, // REG_SEQUENCE |
28 | 67.2k | 0U, // COPY |
29 | 67.2k | 875U, // BUNDLE |
30 | 67.2k | 904U, // LIFETIME_START |
31 | 67.2k | 862U, // LIFETIME_END |
32 | 67.2k | 0U, // STACKMAP |
33 | 67.2k | 0U, // PATCHPOINT |
34 | 67.2k | 0U, // LOAD_STACK_GUARD |
35 | 67.2k | 0U, // STATEPOINT |
36 | 67.2k | 0U, // FRAME_ALLOC |
37 | 67.2k | 1126U, // ABS2_l2_rr |
38 | 67.2k | 10847U, // ABS_l1_pp |
39 | 67.2k | 1631U, // ABS_l1_rr |
40 | 67.2k | 85006U, // ADD2_d2_rrr |
41 | 67.2k | 85006U, // ADD2_l1_rrr_x2 |
42 | 67.2k | 85006U, // ADD2_s1_rrr |
43 | 67.2k | 85171U, // ADD4_l1_rrr_x2 |
44 | 67.2k | 91479U, // ADDAB_d1_rir |
45 | 67.2k | 91479U, // ADDAB_d1_rrr |
46 | 67.2k | 91541U, // ADDAD_d1_rir |
47 | 67.2k | 91541U, // ADDAD_d1_rrr |
48 | 67.2k | 91577U, // ADDAH_d1_rir |
49 | 67.2k | 91577U, // ADDAH_d1_rrr |
50 | 67.2k | 91937U, // ADDAW_d1_rir |
51 | 67.2k | 91937U, // ADDAW_d1_rrr |
52 | 67.2k | 132488U, // ADDKPC_s3_iir |
53 | 67.2k | 1518U, // ADDK_s2_ir |
54 | 67.2k | 233140U, // ADDU_l1_rpp |
55 | 67.2k | 216756U, // ADDU_l1_rrp_x2 |
56 | 67.2k | 91555U, // ADD_d1_rir |
57 | 67.2k | 91555U, // ADD_d1_rrr |
58 | 67.2k | 91555U, // ADD_d2_rir |
59 | 67.2k | 85411U, // ADD_d2_rrr |
60 | 67.2k | 232867U, // ADD_l1_ipp |
61 | 67.2k | 85411U, // ADD_l1_irr |
62 | 67.2k | 232867U, // ADD_l1_rpp |
63 | 67.2k | 216483U, // ADD_l1_rrp_x2 |
64 | 67.2k | 85411U, // ADD_l1_rrr_x2 |
65 | 67.2k | 85411U, // ADD_s1_irr |
66 | 67.2k | 85411U, // ADD_s1_rrr |
67 | 67.2k | 85542U, // ANDN_d2_rrr |
68 | 67.2k | 85542U, // ANDN_l1_rrr_x2 |
69 | 67.2k | 85542U, // ANDN_s4_rrr |
70 | 67.2k | 85416U, // AND_d2_rir |
71 | 67.2k | 85416U, // AND_d2_rrr |
72 | 67.2k | 85416U, // AND_l1_irr |
73 | 67.2k | 85416U, // AND_l1_rrr_x2 |
74 | 67.2k | 85416U, // AND_s1_irr |
75 | 67.2k | 85416U, // AND_s1_rrr |
76 | 67.2k | 85019U, // AVG2_m1_rrr |
77 | 67.2k | 85232U, // AVGU4_m1_rrr |
78 | 67.2k | 1410U, // BDEC_s8_ir |
79 | 67.2k | 1196U, // BITC4_m2_rr |
80 | 67.2k | 307756U, // BNOP_s10_ri |
81 | 67.2k | 307756U, // BNOP_s9_ii |
82 | 67.2k | 1654U, // BPOS_s8_ir |
83 | 67.2k | 53588U, // B_s5_i |
84 | 67.2k | 53588U, // B_s6_r |
85 | 67.2k | 892U, // B_s7_irp |
86 | 67.2k | 898U, // B_s7_nrp |
87 | 67.2k | 353870U, // CLR_s15_riir |
88 | 67.2k | 91726U, // CLR_s1_rrr |
89 | 67.2k | 85080U, // CMPEQ2_s1_rrr |
90 | 67.2k | 85207U, // CMPEQ4_s1_rrr |
91 | 67.2k | 101938U, // CMPEQ_l1_ipr |
92 | 67.2k | 85554U, // CMPEQ_l1_irr |
93 | 67.2k | 101938U, // CMPEQ_l1_rpr |
94 | 67.2k | 85554U, // CMPEQ_l1_rrr_x2 |
95 | 67.2k | 85109U, // CMPGT2_s1_rrr |
96 | 67.2k | 85298U, // CMPGTU4_s1_rrr |
97 | 67.2k | 102037U, // CMPGT_l1_ipr |
98 | 67.2k | 85653U, // CMPGT_l1_irr |
99 | 67.2k | 102037U, // CMPGT_l1_rpr |
100 | 67.2k | 85653U, // CMPGT_l1_rrr_x2 |
101 | 67.2k | 102150U, // CMPLTU_l1_ipr |
102 | 67.2k | 85766U, // CMPLTU_l1_irr |
103 | 67.2k | 102150U, // CMPLTU_l1_rpr |
104 | 67.2k | 85766U, // CMPLTU_l1_rrr_x2 |
105 | 67.2k | 102044U, // CMPLT_l1_ipr |
106 | 67.2k | 85660U, // CMPLT_l1_irr |
107 | 67.2k | 102044U, // CMPLT_l1_rpr |
108 | 67.2k | 85660U, // CMPLT_l1_rrr_x2 |
109 | 67.2k | 1529U, // DEAL_m2_rr |
110 | 67.2k | 216145U, // DOTP2_m1_rrp |
111 | 67.2k | 85073U, // DOTP2_m1_rrr |
112 | 67.2k | 85065U, // DOTPN2_m1_rrr |
113 | 67.2k | 85124U, // DOTPNRSU2_m1_rrr |
114 | 67.2k | 85135U, // DOTPRSU2_m1_rrr |
115 | 67.2k | 85281U, // DOTPSU4_m1_rrr |
116 | 67.2k | 85273U, // DOTPU4_m1_rrr |
117 | 67.2k | 354062U, // EXTU_s15_riir |
118 | 67.2k | 91918U, // EXTU_s1_rrr |
119 | 67.2k | 353955U, // EXT_s15_riir |
120 | 67.2k | 91811U, // EXT_s1_rrr |
121 | 67.2k | 102142U, // GMPGTU_l1_ipr |
122 | 67.2k | 85758U, // GMPGTU_l1_irr |
123 | 67.2k | 102142U, // GMPGTU_l1_rpr |
124 | 67.2k | 85758U, // GMPGTU_l1_rrr_x2 |
125 | 67.2k | 85321U, // GMPY4_m1_rrr |
126 | 67.2k | 5800U, // LDBU_d5_mr |
127 | 67.2k | 6824U, // LDBU_d6_mr |
128 | 67.2k | 5470U, // LDB_d5_mr |
129 | 67.2k | 6494U, // LDB_d6_mr |
130 | 67.2k | 14120U, // LDDW_d7_mp |
131 | 67.2k | 5818U, // LDHU_d5_mr |
132 | 67.2k | 6842U, // LDHU_d6_mr |
133 | 67.2k | 5568U, // LDH_d5_mr |
134 | 67.2k | 6592U, // LDH_d6_mr |
135 | 67.2k | 14131U, // LDNDW_d8_mp |
136 | 67.2k | 5959U, // LDNW_d5_mr |
137 | 67.2k | 5934U, // LDW_d5_mr |
138 | 67.2k | 6958U, // LDW_d6_mr |
139 | 67.2k | 85404U, // LMBD_l1_irr |
140 | 67.2k | 85404U, // LMBD_l1_rrr_x2 |
141 | 67.2k | 85145U, // MAX2_l1_rrr_x2 |
142 | 67.2k | 85307U, // MAXU4_l1_rrr_x2 |
143 | 67.2k | 85059U, // MIN2_l1_rrr_x2 |
144 | 67.2k | 85266U, // MINU4_l1_rrr_x2 |
145 | 67.2k | 216224U, // MPY2_m1_rrp |
146 | 67.2k | 85566U, // MPYHIR_m1_rrr |
147 | 67.2k | 216544U, // MPYHI_m1_rrp |
148 | 67.2k | 85720U, // MPYHLU_m4_rrr |
149 | 67.2k | 85516U, // MPYHL_m4_rrr |
150 | 67.2k | 85728U, // MPYHSLU_m4_rrr |
151 | 67.2k | 85743U, // MPYHSU_m4_rrr |
152 | 67.2k | 85613U, // MPYHULS_m4_rrr |
153 | 67.2k | 85628U, // MPYHUS_m4_rrr |
154 | 67.2k | 85713U, // MPYHU_m4_rrr |
155 | 67.2k | 85466U, // MPYH_m4_rrr |
156 | 67.2k | 85696U, // MPYLHU_m4_rrr |
157 | 67.2k | 85453U, // MPYLH_m4_rrr |
158 | 67.2k | 85574U, // MPYLIR_m1_rrr |
159 | 67.2k | 216551U, // MPYLI_m1_rrp |
160 | 67.2k | 85704U, // MPYLSHU_m4_rrr |
161 | 67.2k | 85604U, // MPYLUHS_m4_rrr |
162 | 67.2k | 216362U, // MPYSU4_m1_rrp |
163 | 67.2k | 85751U, // MPYSU_m4_irr |
164 | 67.2k | 85751U, // MPYSU_m4_rrr |
165 | 67.2k | 216386U, // MPYU4_m1_rrp |
166 | 67.2k | 85636U, // MPYUS_m4_rrr |
167 | 67.2k | 85780U, // MPYU_m4_rrr |
168 | 67.2k | 85849U, // MPY_m4_irr |
169 | 67.2k | 85849U, // MPY_m4_rrr |
170 | 67.2k | 1424U, // MVC_s1_rr |
171 | 67.2k | 1424U, // MVC_s1_rr2 |
172 | 67.2k | 1453U, // MVD_m2_rr |
173 | 67.2k | 1477U, // MVKLH_s12_ir |
174 | 67.2k | 1524U, // MVKL_s12_ir |
175 | 67.2k | 1524U, // MVK_d1_rr |
176 | 67.2k | 1524U, // MVK_l2_ir |
177 | 67.2k | 53249U, // NOP_n |
178 | 67.2k | 2592U, // NORM_l1_pr |
179 | 67.2k | 1568U, // NORM_l1_rr |
180 | 67.2k | 85588U, // OR_d2_rir |
181 | 67.2k | 85588U, // OR_d2_rrr |
182 | 67.2k | 85588U, // OR_l1_irr |
183 | 67.2k | 85588U, // OR_l1_rrr_x2 |
184 | 67.2k | 85588U, // OR_s1_irr |
185 | 67.2k | 85588U, // OR_s1_rrr |
186 | 67.2k | 85043U, // PACK2_l1_rrr_x2 |
187 | 67.2k | 85043U, // PACK2_s4_rrr |
188 | 67.2k | 85025U, // PACKH2_l1_rrr_x2 |
189 | 67.2k | 85025U, // PACKH2_s1_rrr |
190 | 67.2k | 85184U, // PACKH4_l1_rrr_x2 |
191 | 67.2k | 85050U, // PACKHL2_l1_rrr_x2 |
192 | 67.2k | 85050U, // PACKHL2_s1_rrr |
193 | 67.2k | 85192U, // PACKL4_l1_rrr_x2 |
194 | 67.2k | 85033U, // PACKLH2_l1_rrr_x2 |
195 | 67.2k | 85033U, // PACKLH2_s1_rrr |
196 | 67.2k | 91667U, // ROTL_m1_rir |
197 | 67.2k | 91667U, // ROTL_m1_rrr |
198 | 67.2k | 85005U, // SADD2_s4_rrr |
199 | 67.2k | 85224U, // SADDU4_s4_rrr |
200 | 67.2k | 85100U, // SADDUS2_s4_rrr |
201 | 67.2k | 232866U, // SADD_l1_ipp |
202 | 67.2k | 85410U, // SADD_l1_irr |
203 | 67.2k | 232866U, // SADD_l1_rpp |
204 | 67.2k | 85410U, // SADD_l1_rrr_x2 |
205 | 67.2k | 85410U, // SADD_s1_rrr |
206 | 67.2k | 2699U, // SAT_l1_pr |
207 | 67.2k | 353936U, // SET_s15_riir |
208 | 67.2k | 91792U, // SET_s1_rrr |
209 | 67.2k | 1535U, // SHFL_m2_rr |
210 | 67.2k | 85347U, // SHLMB_l1_rrr_x2 |
211 | 67.2k | 85347U, // SHLMB_s4_rrr |
212 | 67.2k | 223750U, // SHL_s1_pip |
213 | 67.2k | 223750U, // SHL_s1_prp |
214 | 67.2k | 222726U, // SHL_s1_rip |
215 | 67.2k | 91654U, // SHL_s1_rir |
216 | 67.2k | 222726U, // SHL_s1_rrp |
217 | 67.2k | 91654U, // SHL_s1_rrr |
218 | 67.2k | 91232U, // SHR2_s1_rir |
219 | 67.2k | 91232U, // SHR2_s4_rrr |
220 | 67.2k | 85354U, // SHRMB_l1_rrr_x2 |
221 | 67.2k | 85354U, // SHRMB_s4_rrr |
222 | 67.2k | 91261U, // SHRU2_s1_rir |
223 | 67.2k | 91261U, // SHRU2_s4_rrr |
224 | 67.2k | 223977U, // SHRU_s1_pip |
225 | 67.2k | 223977U, // SHRU_s1_prp |
226 | 67.2k | 91881U, // SHRU_s1_rir |
227 | 67.2k | 91881U, // SHRU_s1_rrr |
228 | 67.2k | 223801U, // SHR_s1_pip |
229 | 67.2k | 223801U, // SHR_s1_prp |
230 | 67.2k | 91705U, // SHR_s1_rir |
231 | 67.2k | 91705U, // SHR_s1_rrr |
232 | 67.2k | 216223U, // SMPY2_m1_rrp |
233 | 67.2k | 85515U, // SMPYHL_m4_rrr |
234 | 67.2k | 85465U, // SMPYH_m4_rrr |
235 | 67.2k | 85452U, // SMPYLH_m4_rrr |
236 | 67.2k | 85848U, // SMPY_m4_rrr |
237 | 67.2k | 85042U, // SPACK2_s4_rrr |
238 | 67.2k | 85248U, // SPACKU4_s4_rrr |
239 | 67.2k | 91653U, // SSHL_s1_rir |
240 | 67.2k | 91653U, // SSHL_s1_rrr |
241 | 67.2k | 85529U, // SSHVL_m1_rrr |
242 | 67.2k | 85592U, // SSHVR_m1_rrr |
243 | 67.2k | 232822U, // SSUB_l1_ipp |
244 | 67.2k | 85366U, // SSUB_l1_irr |
245 | 67.2k | 85366U, // SSUB_l1_rrr_x1 |
246 | 67.2k | 85366U, // SSUB_l1_rrr_x2 |
247 | 67.2k | 438641U, // STB_d5_rm |
248 | 67.2k | 504177U, // STB_d6_rm |
249 | 67.2k | 8001U, // STDW_d7_pm |
250 | 67.2k | 438740U, // STH_d5_rm |
251 | 67.2k | 504276U, // STH_d6_rm |
252 | 67.2k | 7994U, // STNDW_d8_pm |
253 | 67.2k | 439117U, // STNW_d5_rm |
254 | 67.2k | 439123U, // STW_d5_rm |
255 | 67.2k | 504659U, // STW_d6_rm |
256 | 67.2k | 84999U, // SUB2_d2_rrr |
257 | 67.2k | 84999U, // SUB2_l1_rrr_x2 |
258 | 67.2k | 84999U, // SUB2_s1_rrr |
259 | 67.2k | 85158U, // SUB4_l1_rrr_x2 |
260 | 67.2k | 85215U, // SUBABS4_l1_rrr_x2 |
261 | 67.2k | 91472U, // SUBAB_d1_rir |
262 | 67.2k | 91472U, // SUBAB_d1_rrr |
263 | 67.2k | 91472U, // SUBAH_d1_rir |
264 | 67.2k | 91570U, // SUBAH_d1_rrr |
265 | 67.2k | 91472U, // SUBAW_d1_rir |
266 | 67.2k | 91930U, // SUBAW_d1_rrr |
267 | 67.2k | 85372U, // SUBC_l1_rrr_x2 |
268 | 67.2k | 216750U, // SUBU_l1_rrp_x1 |
269 | 67.2k | 216750U, // SUBU_l1_rrp_x2 |
270 | 67.2k | 91511U, // SUB_d1_rir |
271 | 67.2k | 91511U, // SUB_d1_rrr |
272 | 67.2k | 85367U, // SUB_d2_rrr |
273 | 67.2k | 232823U, // SUB_l1_ipp |
274 | 67.2k | 85367U, // SUB_l1_irr |
275 | 67.2k | 216439U, // SUB_l1_rrp_x1 |
276 | 67.2k | 216439U, // SUB_l1_rrp_x2 |
277 | 67.2k | 85367U, // SUB_l1_rrr_x1 |
278 | 67.2k | 85367U, // SUB_l1_rrr_x2 |
279 | 67.2k | 85367U, // SUB_s1_irr |
280 | 67.2k | 85367U, // SUB_s1_rrr |
281 | 67.2k | 91511U, // SUB_s4_rrr |
282 | 67.2k | 1232U, // SWAP4_l2_rr |
283 | 67.2k | 1271U, // UNPKHU4_l2_rr |
284 | 67.2k | 1271U, // UNPKHU4_s14_rr |
285 | 67.2k | 1289U, // UNPKLU4_l2_rr |
286 | 67.2k | 1289U, // UNPKLU4_s14_rr |
287 | 67.2k | 85587U, // XOR_d2_rir |
288 | 67.2k | 85587U, // XOR_d2_rrr |
289 | 67.2k | 85587U, // XOR_l1_irr |
290 | 67.2k | 85587U, // XOR_l1_rrr_x2 |
291 | 67.2k | 85587U, // XOR_s1_irr |
292 | 67.2k | 85587U, // XOR_s1_rrr |
293 | 67.2k | 1044U, // XPND2_m2_rr |
294 | 67.2k | 1209U, // XPND4_m2_rr |
295 | 67.2k | 0U |
296 | 67.2k | }; |
297 | | |
298 | 67.2k | #ifndef CAPSTONE_DIET |
299 | 67.2k | static const char AsmStrs[] = { |
300 | 67.2k | /* 0 */ 'n', 'o', 'p', 9, 9, 0, |
301 | 67.2k | /* 6 */ 's', 'u', 'b', '2', 9, 0, |
302 | 67.2k | /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0, |
303 | 67.2k | /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0, |
304 | 67.2k | /* 26 */ 'a', 'v', 'g', '2', 9, 0, |
305 | 67.2k | /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0, |
306 | 67.2k | /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0, |
307 | 67.2k | /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0, |
308 | 67.2k | /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0, |
309 | 67.2k | /* 66 */ 'm', 'i', 'n', '2', 9, 0, |
310 | 67.2k | /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0, |
311 | 67.2k | /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0, |
312 | 67.2k | /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0, |
313 | 67.2k | /* 95 */ 's', 'h', 'r', '2', 9, 0, |
314 | 67.2k | /* 101 */ 'a', 'b', 's', '2', 9, 0, |
315 | 67.2k | /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0, |
316 | 67.2k | /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0, |
317 | 67.2k | /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0, |
318 | 67.2k | /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0, |
319 | 67.2k | /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0, |
320 | 67.2k | /* 152 */ 'm', 'a', 'x', '2', 9, 0, |
321 | 67.2k | /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0, |
322 | 67.2k | /* 165 */ 's', 'u', 'b', '4', 9, 0, |
323 | 67.2k | /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0, |
324 | 67.2k | /* 178 */ 'a', 'd', 'd', '4', 9, 0, |
325 | 67.2k | /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0, |
326 | 67.2k | /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0, |
327 | 67.2k | /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0, |
328 | 67.2k | /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0, |
329 | 67.2k | /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0, |
330 | 67.2k | /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0, |
331 | 67.2k | /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0, |
332 | 67.2k | /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0, |
333 | 67.2k | /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0, |
334 | 67.2k | /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0, |
335 | 67.2k | /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0, |
336 | 67.2k | /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0, |
337 | 67.2k | /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0, |
338 | 67.2k | /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0, |
339 | 67.2k | /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0, |
340 | 67.2k | /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0, |
341 | 67.2k | /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0, |
342 | 67.2k | /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0, |
343 | 67.2k | /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0, |
344 | 67.2k | /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0, |
345 | 67.2k | /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0, |
346 | 67.2k | /* 349 */ 'l', 'd', 'b', 9, 0, |
347 | 67.2k | /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0, |
348 | 67.2k | /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0, |
349 | 67.2k | /* 368 */ 's', 't', 'b', 9, 0, |
350 | 67.2k | /* 373 */ 's', 's', 'u', 'b', 9, 0, |
351 | 67.2k | /* 379 */ 's', 'u', 'b', 'c', 9, 0, |
352 | 67.2k | /* 385 */ 'b', 'd', 'e', 'c', 9, 0, |
353 | 67.2k | /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0, |
354 | 67.2k | /* 399 */ 'm', 'v', 'c', 9, 0, |
355 | 67.2k | /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0, |
356 | 67.2k | /* 411 */ 'l', 'm', 'b', 'd', 9, 0, |
357 | 67.2k | /* 417 */ 's', 'a', 'd', 'd', 9, 0, |
358 | 67.2k | /* 423 */ 'a', 'n', 'd', 9, 0, |
359 | 67.2k | /* 428 */ 'm', 'v', 'd', 9, 0, |
360 | 67.2k | /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0, |
361 | 67.2k | /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0, |
362 | 67.2k | /* 447 */ 'l', 'd', 'h', 9, 0, |
363 | 67.2k | /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0, |
364 | 67.2k | /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0, |
365 | 67.2k | /* 467 */ 's', 't', 'h', 9, 0, |
366 | 67.2k | /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0, |
367 | 67.2k | /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0, |
368 | 67.2k | /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0, |
369 | 67.2k | /* 493 */ 'a', 'd', 'd', 'k', 9, 0, |
370 | 67.2k | /* 499 */ 'm', 'v', 'k', 9, 0, |
371 | 67.2k | /* 504 */ 'd', 'e', 'a', 'l', 9, 0, |
372 | 67.2k | /* 510 */ 's', 'h', 'f', 'l', 9, 0, |
373 | 67.2k | /* 516 */ 's', 's', 'h', 'l', 9, 0, |
374 | 67.2k | /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0, |
375 | 67.2k | /* 530 */ 'r', 'o', 't', 'l', 9, 0, |
376 | 67.2k | /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0, |
377 | 67.2k | /* 543 */ 'n', 'o', 'r', 'm', 9, 0, |
378 | 67.2k | /* 549 */ 'a', 'n', 'd', 'n', 9, 0, |
379 | 67.2k | /* 555 */ 'b', 'n', 'o', 'p', 9, 0, |
380 | 67.2k | /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0, |
381 | 67.2k | /* 568 */ 's', 'h', 'r', 9, 0, |
382 | 67.2k | /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0, |
383 | 67.2k | /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0, |
384 | 67.2k | /* 589 */ 'c', 'l', 'r', 9, 0, |
385 | 67.2k | /* 594 */ 'x', 'o', 'r', 9, 0, |
386 | 67.2k | /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0, |
387 | 67.2k | /* 606 */ 'a', 'b', 's', 9, 0, |
388 | 67.2k | /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0, |
389 | 67.2k | /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0, |
390 | 67.2k | /* 629 */ 'b', 'p', 'o', 's', 9, 0, |
391 | 67.2k | /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0, |
392 | 67.2k | /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0, |
393 | 67.2k | /* 650 */ 's', 'a', 't', 9, 0, |
394 | 67.2k | /* 655 */ 's', 'e', 't', 9, 0, |
395 | 67.2k | /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0, |
396 | 67.2k | /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0, |
397 | 67.2k | /* 674 */ 'e', 'x', 't', 9, 0, |
398 | 67.2k | /* 679 */ 'l', 'd', 'b', 'u', 9, 0, |
399 | 67.2k | /* 685 */ 's', 'u', 'b', 'u', 9, 0, |
400 | 67.2k | /* 691 */ 'a', 'd', 'd', 'u', 9, 0, |
401 | 67.2k | /* 697 */ 'l', 'd', 'h', 'u', 9, 0, |
402 | 67.2k | /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0, |
403 | 67.2k | /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0, |
404 | 67.2k | /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0, |
405 | 67.2k | /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0, |
406 | 67.2k | /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0, |
407 | 67.2k | /* 744 */ 's', 'h', 'r', 'u', 9, 0, |
408 | 67.2k | /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0, |
409 | 67.2k | /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0, |
410 | 67.2k | /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0, |
411 | 67.2k | /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0, |
412 | 67.2k | /* 781 */ 'e', 'x', 't', 'u', 9, 0, |
413 | 67.2k | /* 787 */ 'm', 'p', 'y', 'u', 9, 0, |
414 | 67.2k | /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0, |
415 | 67.2k | /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0, |
416 | 67.2k | /* 807 */ 'l', 'd', 'd', 'w', 9, 0, |
417 | 67.2k | /* 813 */ 'l', 'd', 'w', 9, 0, |
418 | 67.2k | /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0, |
419 | 67.2k | /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0, |
420 | 67.2k | /* 832 */ 's', 't', 'd', 'w', 9, 0, |
421 | 67.2k | /* 838 */ 'l', 'd', 'n', 'w', 9, 0, |
422 | 67.2k | /* 844 */ 's', 't', 'n', 'w', 9, 0, |
423 | 67.2k | /* 850 */ 's', 't', 'w', 9, 0, |
424 | 67.2k | /* 855 */ 's', 'm', 'p', 'y', 9, 0, |
425 | 67.2k | /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0, |
426 | 67.2k | /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0, |
427 | 67.2k | /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0, |
428 | 67.2k | /* 891 */ 'b', 9, 'i', 'r', 'p', 0, |
429 | 67.2k | /* 897 */ 'b', 9, 'n', 'r', 'p', 0, |
430 | 67.2k | /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0, |
431 | 67.2k | }; |
432 | 67.2k | #endif |
433 | | |
434 | | // Emit the opcode for the instruction. |
435 | 67.2k | uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; |
436 | | // assert(Bits != 0 && "Cannot print this instruction."); |
437 | 67.2k | #ifndef CAPSTONE_DIET |
438 | 67.2k | SStream_concat0(O, AsmStrs+(Bits & 1023)-1); |
439 | 67.2k | #endif |
440 | | |
441 | | |
442 | | // Fragment 0 encoded into 3 bits for 8 unique commands. |
443 | 67.2k | switch ((uint32_t)((Bits >> 10) & 7)) { |
444 | 0 | default: |
445 | 180 | case 0: |
446 | | // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, B_s7_irp, B_s7_nrp |
447 | 180 | return; |
448 | 0 | break; |
449 | 17.9k | case 1: |
450 | | // ABS2_l2_rr, ABS_l1_rr, ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD... |
451 | 17.9k | printOperand(MI, 1, O); |
452 | 17.9k | SStream_concat0(O, ", "); |
453 | 17.9k | break; |
454 | 6.62k | case 2: |
455 | | // ABS_l1_pp, NORM_l1_pr, SAT_l1_pr, SHL_s1_pip, SHL_s1_prp, SHRU_s1_pip,... |
456 | 6.62k | printRegPair(MI, 1, O); |
457 | 6.62k | SStream_concat0(O, ", "); |
458 | 6.62k | break; |
459 | 18.8k | case 3: |
460 | | // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rpp,... |
461 | 18.8k | printOperand(MI, 2, O); |
462 | 18.8k | SStream_concat0(O, ", "); |
463 | 18.8k | break; |
464 | 14.1k | case 4: |
465 | | // BNOP_s10_ri, BNOP_s9_ii, B_s5_i, B_s6_r, NOP_n, STB_d5_rm, STB_d6_rm, ... |
466 | 14.1k | printOperand(MI, 0, O); |
467 | 14.1k | break; |
468 | 4.73k | case 5: |
469 | | // LDBU_d5_mr, LDB_d5_mr, LDDW_d7_mp, LDHU_d5_mr, LDH_d5_mr, LDNDW_d8_mp,... |
470 | 4.73k | printMemOperand(MI, 1, O); |
471 | 4.73k | SStream_concat0(O, ", "); |
472 | 4.73k | break; |
473 | 4.21k | case 6: |
474 | | // LDBU_d6_mr, LDB_d6_mr, LDHU_d6_mr, LDH_d6_mr, LDW_d6_mr |
475 | 4.21k | printMemOperand2(MI, 1, O); |
476 | 4.21k | SStream_concat0(O, ", "); |
477 | 4.21k | printOperand(MI, 0, O); |
478 | 4.21k | return; |
479 | 0 | break; |
480 | 548 | case 7: |
481 | | // STDW_d7_pm, STNDW_d8_pm |
482 | 548 | printRegPair(MI, 0, O); |
483 | 548 | SStream_concat0(O, ", "); |
484 | 548 | printMemOperand(MI, 1, O); |
485 | 548 | return; |
486 | 0 | break; |
487 | 67.2k | } |
488 | | |
489 | | |
490 | | // Fragment 1 encoded into 3 bits for 7 unique commands. |
491 | 62.3k | switch ((uint32_t)((Bits >> 13) & 7)) { |
492 | 0 | default: |
493 | 16.9k | case 0: |
494 | | // ABS2_l2_rr, ABS_l1_rr, ADDKPC_s3_iir, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2... |
495 | 16.9k | printOperand(MI, 0, O); |
496 | 16.9k | break; |
497 | 2.28k | case 1: |
498 | | // ABS_l1_pp, LDDW_d7_mp, LDNDW_d8_mp |
499 | 2.28k | printRegPair(MI, 0, O); |
500 | 2.28k | return; |
501 | 0 | break; |
502 | 15.0k | case 2: |
503 | | // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rrp_... |
504 | 15.0k | printOperand(MI, 1, O); |
505 | 15.0k | SStream_concat0(O, ", "); |
506 | 15.0k | break; |
507 | 10.0k | case 3: |
508 | | // ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD_d1_rrr, ADDAH_d1_rir, ... |
509 | 10.0k | printOperand(MI, 2, O); |
510 | 10.0k | SStream_concat0(O, ", "); |
511 | 10.0k | break; |
512 | 3.82k | case 4: |
513 | | // ADDU_l1_rpp, ADD_l1_ipp, ADD_l1_rpp, CMPEQ_l1_ipr, CMPEQ_l1_rpr, CMPGT... |
514 | 3.82k | printRegPair(MI, 1, O); |
515 | 3.82k | SStream_concat0(O, ", "); |
516 | 3.82k | break; |
517 | 9.72k | case 5: |
518 | | // BNOP_s10_ri, BNOP_s9_ii, STB_d5_rm, STB_d6_rm, STH_d5_rm, STH_d6_rm, S... |
519 | 9.72k | SStream_concat0(O, ", "); |
520 | 9.72k | break; |
521 | 4.44k | case 6: |
522 | | // B_s5_i, B_s6_r, NOP_n |
523 | 4.44k | return; |
524 | 0 | break; |
525 | 62.3k | } |
526 | | |
527 | | |
528 | | // Fragment 2 encoded into 3 bits for 8 unique commands. |
529 | 55.5k | switch ((uint32_t)((Bits >> 16) & 7)) { |
530 | 0 | default: |
531 | 16.1k | case 0: |
532 | | // ABS2_l2_rr, ABS_l1_rr, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2_rr, BPOS_s8_ir... |
533 | 16.1k | return; |
534 | 0 | break; |
535 | 19.4k | case 1: |
536 | | // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDAB_d1_rir... |
537 | 19.4k | printOperand(MI, 0, O); |
538 | 19.4k | return; |
539 | 0 | break; |
540 | 764 | case 2: |
541 | | // ADDKPC_s3_iir |
542 | 764 | SStream_concat0(O, ", "); |
543 | 764 | printOperand(MI, 2, O); |
544 | 764 | return; |
545 | 0 | break; |
546 | 5.81k | case 3: |
547 | | // ADDU_l1_rpp, ADDU_l1_rrp_x2, ADD_l1_ipp, ADD_l1_rpp, ADD_l1_rrp_x2, DO... |
548 | 5.81k | printRegPair(MI, 0, O); |
549 | 5.81k | return; |
550 | 0 | break; |
551 | 1.24k | case 4: |
552 | | // BNOP_s10_ri, BNOP_s9_ii |
553 | 1.24k | printOperand(MI, 1, O); |
554 | 1.24k | return; |
555 | 0 | break; |
556 | 3.67k | case 5: |
557 | | // CLR_s15_riir, EXTU_s15_riir, EXT_s15_riir, SET_s15_riir |
558 | 3.67k | printOperand(MI, 3, O); |
559 | 3.67k | SStream_concat0(O, ", "); |
560 | 3.67k | printOperand(MI, 0, O); |
561 | 3.67k | return; |
562 | 0 | break; |
563 | 2.13k | case 6: |
564 | | // STB_d5_rm, STH_d5_rm, STNW_d5_rm, STW_d5_rm |
565 | 2.13k | printMemOperand(MI, 1, O); |
566 | 2.13k | return; |
567 | 0 | break; |
568 | 6.34k | case 7: |
569 | | // STB_d6_rm, STH_d6_rm, STW_d6_rm |
570 | 6.34k | printMemOperand2(MI, 1, O); |
571 | 6.34k | return; |
572 | 0 | break; |
573 | 55.5k | } |
574 | | |
575 | 55.5k | } |
576 | | |
577 | | |
578 | | /// getRegisterName - This method is automatically generated by tblgen |
579 | | /// from the register set description. This returns the assembler name |
580 | | /// for the specified register. |
581 | 152k | static const char *getRegisterName(unsigned RegNo) { |
582 | 152k | #ifndef CAPSTONE_DIET |
583 | 152k | static const char AsmStrs[] = { |
584 | 152k | /* 0 */ 'a', '1', '0', 0, |
585 | 152k | /* 4 */ 'b', '1', '0', 0, |
586 | 152k | /* 8 */ 'a', '2', '0', 0, |
587 | 152k | /* 12 */ 'b', '2', '0', 0, |
588 | 152k | /* 16 */ 'a', '3', '0', 0, |
589 | 152k | /* 20 */ 'b', '3', '0', 0, |
590 | 152k | /* 24 */ 'a', '0', 0, |
591 | 152k | /* 27 */ 'b', '0', 0, |
592 | 152k | /* 30 */ 'a', '1', '1', 0, |
593 | 152k | /* 34 */ 'b', '1', '1', 0, |
594 | 152k | /* 38 */ 'a', '2', '1', 0, |
595 | 152k | /* 42 */ 'b', '2', '1', 0, |
596 | 152k | /* 46 */ 'a', '3', '1', 0, |
597 | 152k | /* 50 */ 'b', '3', '1', 0, |
598 | 152k | /* 54 */ 'a', '1', 0, |
599 | 152k | /* 57 */ 'b', '1', 0, |
600 | 152k | /* 60 */ 'p', 'c', 'e', '1', 0, |
601 | 152k | /* 65 */ 'a', '1', '2', 0, |
602 | 152k | /* 69 */ 'b', '1', '2', 0, |
603 | 152k | /* 73 */ 'a', '2', '2', 0, |
604 | 152k | /* 77 */ 'b', '2', '2', 0, |
605 | 152k | /* 81 */ 'a', '2', 0, |
606 | 152k | /* 84 */ 'b', '2', 0, |
607 | 152k | /* 87 */ 'a', '1', '3', 0, |
608 | 152k | /* 91 */ 'b', '1', '3', 0, |
609 | 152k | /* 95 */ 'a', '2', '3', 0, |
610 | 152k | /* 99 */ 'b', '2', '3', 0, |
611 | 152k | /* 103 */ 'a', '3', 0, |
612 | 152k | /* 106 */ 'b', '3', 0, |
613 | 152k | /* 109 */ 'a', '1', '4', 0, |
614 | 152k | /* 113 */ 'b', '1', '4', 0, |
615 | 152k | /* 117 */ 'a', '2', '4', 0, |
616 | 152k | /* 121 */ 'b', '2', '4', 0, |
617 | 152k | /* 125 */ 'a', '4', 0, |
618 | 152k | /* 128 */ 'b', '4', 0, |
619 | 152k | /* 131 */ 'a', '1', '5', 0, |
620 | 152k | /* 135 */ 'b', '1', '5', 0, |
621 | 152k | /* 139 */ 'a', '2', '5', 0, |
622 | 152k | /* 143 */ 'b', '2', '5', 0, |
623 | 152k | /* 147 */ 'a', '5', 0, |
624 | 152k | /* 150 */ 'b', '5', 0, |
625 | 152k | /* 153 */ 'a', '1', '6', 0, |
626 | 152k | /* 157 */ 'b', '1', '6', 0, |
627 | 152k | /* 161 */ 'a', '2', '6', 0, |
628 | 152k | /* 165 */ 'b', '2', '6', 0, |
629 | 152k | /* 169 */ 'a', '6', 0, |
630 | 152k | /* 172 */ 'b', '6', 0, |
631 | 152k | /* 175 */ 'a', '1', '7', 0, |
632 | 152k | /* 179 */ 'b', '1', '7', 0, |
633 | 152k | /* 183 */ 'a', '2', '7', 0, |
634 | 152k | /* 187 */ 'b', '2', '7', 0, |
635 | 152k | /* 191 */ 'a', '7', 0, |
636 | 152k | /* 194 */ 'b', '7', 0, |
637 | 152k | /* 197 */ 'a', '1', '8', 0, |
638 | 152k | /* 201 */ 'b', '1', '8', 0, |
639 | 152k | /* 205 */ 'a', '2', '8', 0, |
640 | 152k | /* 209 */ 'b', '2', '8', 0, |
641 | 152k | /* 213 */ 'a', '8', 0, |
642 | 152k | /* 216 */ 'b', '8', 0, |
643 | 152k | /* 219 */ 'a', '1', '9', 0, |
644 | 152k | /* 223 */ 'b', '1', '9', 0, |
645 | 152k | /* 227 */ 'a', '2', '9', 0, |
646 | 152k | /* 231 */ 'b', '2', '9', 0, |
647 | 152k | /* 235 */ 'a', '9', 0, |
648 | 152k | /* 238 */ 'b', '9', 0, |
649 | 152k | /* 241 */ 'g', 'p', 'l', 'y', 'a', 0, |
650 | 152k | /* 247 */ 'g', 'p', 'l', 'y', 'b', 0, |
651 | 152k | /* 253 */ 'r', 'i', 'l', 'c', 0, |
652 | 152k | /* 258 */ 't', 's', 'c', 'h', 0, |
653 | 152k | /* 263 */ 't', 's', 'c', 'l', 0, |
654 | 152k | /* 268 */ 'd', 'n', 'u', 'm', 0, |
655 | 152k | /* 273 */ 'r', 'e', 'p', 0, |
656 | 152k | /* 277 */ 'i', 'r', 'p', 0, |
657 | 152k | /* 281 */ 'n', 'r', 'p', 0, |
658 | 152k | /* 285 */ 'i', 's', 't', 'p', 0, |
659 | 152k | /* 290 */ 'e', 'c', 'r', 0, |
660 | 152k | /* 294 */ 'i', 'c', 'r', 0, |
661 | 152k | /* 298 */ 'd', 'i', 'e', 'r', 0, |
662 | 152k | /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0, |
663 | 152k | /* 310 */ 'a', 'm', 'r', 0, |
664 | 152k | /* 314 */ 'i', 'e', 'r', 'r', 0, |
665 | 152k | /* 319 */ 'c', 's', 'r', 0, |
666 | 152k | /* 323 */ 'i', 's', 'r', 0, |
667 | 152k | /* 327 */ 's', 's', 'r', 0, |
668 | 152k | /* 331 */ 'i', 't', 's', 'r', 0, |
669 | 152k | /* 336 */ 'n', 't', 's', 'r', 0, |
670 | 152k | }; |
671 | | |
672 | 152k | static const uint16_t RegAsmOffset[] = { |
673 | 152k | 310, 319, 298, 268, 290, 303, 241, 247, 294, 299, 314, 254, 277, 323, |
674 | 152k | 285, 331, 281, 336, 273, 253, 327, 258, 263, 332, 24, 54, 81, 103, |
675 | 152k | 125, 147, 169, 191, 213, 235, 0, 30, 65, 87, 109, 131, 153, 175, |
676 | 152k | 197, 219, 8, 38, 73, 95, 117, 139, 161, 183, 205, 227, 16, 46, |
677 | 152k | 27, 57, 84, 106, 128, 150, 172, 194, 216, 238, 4, 34, 69, 91, |
678 | 152k | 113, 135, 157, 179, 201, 223, 12, 42, 77, 99, 121, 143, 165, 187, |
679 | 152k | 209, 231, 20, 50, 60, |
680 | 152k | }; |
681 | | |
682 | 152k | return AsmStrs+RegAsmOffset[RegNo-1]; |
683 | | #else |
684 | | return NULL; |
685 | | #endif |
686 | 152k | } |