/src/capstonenext/arch/TriCore/TriCoreMapping.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_TRICORE |
5 | | |
6 | | #include <stdio.h> // debug |
7 | | #include <string.h> |
8 | | #include <assert.h> |
9 | | |
10 | | #include "../../Mapping.h" |
11 | | #include "../../utils.h" |
12 | | #include "../../cs_simple_types.h" |
13 | | |
14 | | #include "TriCoreMapping.h" |
15 | | #include "TriCoreLinkage.h" |
16 | | |
17 | | #define GET_INSTRINFO_ENUM |
18 | | |
19 | | #include "TriCoreGenInstrInfo.inc" |
20 | | |
21 | | static const insn_map insns[] = { |
22 | | // dummy item |
23 | | { 0, |
24 | | 0, |
25 | | #ifndef CAPSTONE_DIET |
26 | | { 0 }, |
27 | | { 0 }, |
28 | | { 0 }, |
29 | | 0, |
30 | | 0 |
31 | | #endif |
32 | | }, |
33 | | |
34 | | #include "TriCoreGenCSMappingInsn.inc" |
35 | | }; |
36 | | |
37 | | void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
38 | 0 | { |
39 | | // Not used. Information is set after disassembly. |
40 | 0 | } |
41 | | |
42 | | #ifndef CAPSTONE_DIET |
43 | | static const tricore_reg flag_regs[] = { TRICORE_REG_PSW }; |
44 | | #endif // CAPSTONE_DIET |
45 | | |
46 | | static inline void check_updates_flags(MCInst *MI) |
47 | 0 | { |
48 | 0 | #ifndef CAPSTONE_DIET |
49 | 0 | if (!MI->flat_insn->detail) |
50 | 0 | return; |
51 | 0 | cs_detail *detail = MI->flat_insn->detail; |
52 | 0 | for (int i = 0; i < detail->regs_write_count; ++i) { |
53 | 0 | if (detail->regs_write[i] == 0) |
54 | 0 | return; |
55 | 0 | for (int j = 0; j < ARR_SIZE(flag_regs); ++j) { |
56 | 0 | if (detail->regs_write[i] == flag_regs[j]) { |
57 | 0 | detail->tricore.update_flags = true; |
58 | 0 | return; |
59 | 0 | } |
60 | 0 | } |
61 | 0 | } |
62 | 0 | #endif // CAPSTONE_DIET |
63 | 0 | } |
64 | | |
65 | | void TriCore_set_instr_map_data(MCInst *MI) |
66 | 0 | { |
67 | 0 | map_cs_id(MI, insns, ARR_SIZE(insns)); |
68 | 0 | map_implicit_reads(MI, insns); |
69 | 0 | map_implicit_writes(MI, insns); |
70 | 0 | check_updates_flags(MI); |
71 | 0 | map_groups(MI, insns); |
72 | 0 | } |
73 | | |
74 | | #ifndef CAPSTONE_DIET |
75 | | |
76 | | static const char * const insn_names[] = { |
77 | | NULL, |
78 | | |
79 | | #include "TriCoreGenCSMappingInsnName.inc" |
80 | | }; |
81 | | |
82 | | // special alias insn |
83 | | static const name_map alias_insn_names[] = { { 0, NULL } }; |
84 | | #endif |
85 | | |
86 | | const char *TriCore_insn_name(csh handle, unsigned int id) |
87 | 0 | { |
88 | 0 | #ifndef CAPSTONE_DIET |
89 | 0 | unsigned int i; |
90 | |
|
91 | 0 | if (id >= TRICORE_INS_ENDING) |
92 | 0 | return NULL; |
93 | | |
94 | | // handle special alias first |
95 | 0 | for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { |
96 | 0 | if (alias_insn_names[i].id == id) |
97 | 0 | return alias_insn_names[i].name; |
98 | 0 | } |
99 | | |
100 | 0 | return insn_names[id]; |
101 | | #else |
102 | | return NULL; |
103 | | #endif |
104 | 0 | } |
105 | | |
106 | | #ifndef CAPSTONE_DIET |
107 | | static const name_map group_name_maps[] = { |
108 | | { TRICORE_GRP_INVALID, NULL }, |
109 | | { TRICORE_GRP_CALL, "call" }, |
110 | | { TRICORE_GRP_JUMP, "jump" }, |
111 | | }; |
112 | | #endif |
113 | | |
114 | | const char *TriCore_group_name(csh handle, unsigned int id) |
115 | 0 | { |
116 | 0 | #ifndef CAPSTONE_DIET |
117 | 0 | if (id >= TRICORE_GRP_ENDING) |
118 | 0 | return NULL; |
119 | | |
120 | 0 | return group_name_maps[id].name; |
121 | | #else |
122 | | return NULL; |
123 | | #endif |
124 | 0 | } |
125 | | |
126 | | #ifndef CAPSTONE_DIET |
127 | | static const map_insn_ops insn_operands[] = { |
128 | | #include "TriCoreGenCSMappingInsnOp.inc" |
129 | | }; |
130 | | #endif |
131 | | |
132 | | void TriCore_set_access(MCInst *MI) |
133 | 0 | { |
134 | 0 | #ifndef CAPSTONE_DIET |
135 | 0 | if (!(MI->csh->detail_opt == CS_OPT_ON && MI->flat_insn->detail)) |
136 | 0 | return; |
137 | | |
138 | 0 | assert(MI->Opcode < ARR_SIZE(insn_operands)); |
139 | | |
140 | 0 | cs_detail *detail = MI->flat_insn->detail; |
141 | 0 | cs_tricore *tc = &(detail->tricore); |
142 | 0 | for (int i = 0; i < tc->op_count; ++i) { |
143 | 0 | cs_ac_type ac = map_get_op_access(MI, i); |
144 | 0 | cs_tricore_op *op = &tc->operands[i]; |
145 | 0 | op->access = ac; |
146 | 0 | cs_op_type op_type = map_get_op_type(MI, i); |
147 | 0 | if (op_type != CS_OP_REG) { |
148 | 0 | continue; |
149 | 0 | } |
150 | 0 | if (ac & CS_AC_READ) { |
151 | 0 | detail->regs_read[detail->regs_read_count++] = op->reg; |
152 | 0 | } |
153 | 0 | if (ac & CS_AC_WRITE) { |
154 | 0 | detail->regs_write[detail->regs_write_count++] = |
155 | 0 | op->reg; |
156 | 0 | } |
157 | 0 | } |
158 | 0 | #endif |
159 | 0 | } |
160 | | |
161 | | void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read, |
162 | | uint8_t *regs_read_count, cs_regs regs_write, |
163 | | uint8_t *regs_write_count) |
164 | 0 | { |
165 | 0 | #ifndef CAPSTONE_DIET |
166 | 0 | uint8_t read_count, write_count; |
167 | 0 | cs_detail *detail = insn->detail; |
168 | 0 | read_count = detail->regs_read_count; |
169 | 0 | write_count = detail->regs_write_count; |
170 | | |
171 | | // implicit registers |
172 | 0 | memcpy(regs_read, detail->regs_read, |
173 | 0 | read_count * sizeof(detail->regs_read[0])); |
174 | 0 | memcpy(regs_write, detail->regs_write, |
175 | 0 | write_count * sizeof(detail->regs_write[0])); |
176 | | |
177 | | // explicit registers |
178 | 0 | cs_tricore *tc = &detail->tricore; |
179 | 0 | for (uint8_t i = 0; i < tc->op_count; i++) { |
180 | 0 | cs_tricore_op *op = &(tc->operands[i]); |
181 | 0 | switch ((int)op->type) { |
182 | 0 | case TRICORE_OP_REG: |
183 | 0 | if ((op->access & CS_AC_READ) && |
184 | 0 | !arr_exist(regs_read, read_count, op->reg)) { |
185 | 0 | regs_read[read_count] = (uint16_t)op->reg; |
186 | 0 | read_count++; |
187 | 0 | } |
188 | 0 | if ((op->access & CS_AC_WRITE) && |
189 | 0 | !arr_exist(regs_write, write_count, op->reg)) { |
190 | 0 | regs_write[write_count] = (uint16_t)op->reg; |
191 | 0 | write_count++; |
192 | 0 | } |
193 | 0 | break; |
194 | 0 | case TRICORE_OP_MEM: |
195 | | // registers appeared in memory references always being read |
196 | 0 | if ((op->mem.base != ARM_REG_INVALID) && |
197 | 0 | !arr_exist(regs_read, read_count, op->mem.base)) { |
198 | 0 | regs_read[read_count] = (uint16_t)op->mem.base; |
199 | 0 | read_count++; |
200 | 0 | } |
201 | 0 | default: |
202 | 0 | break; |
203 | 0 | } |
204 | 0 | } |
205 | | |
206 | 0 | *regs_read_count = read_count; |
207 | 0 | *regs_write_count = write_count; |
208 | 0 | #endif |
209 | 0 | } |
210 | | |
211 | | bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen, |
212 | | MCInst *MI, uint16_t *Size, uint64_t Address, |
213 | | void *Info) |
214 | 0 | { |
215 | 0 | return TriCore_LLVM_getInstruction(handle, Bytes, ByteLen, MI, Size, |
216 | 0 | Address, Info); |
217 | 0 | } |
218 | | |
219 | | void TriCore_printInst(MCInst *MI, SStream *O, void *Info) |
220 | 0 | { |
221 | 0 | TriCore_LLVM_printInst(MI, MI->address, O); |
222 | 0 | } |
223 | | |
224 | | const char *TriCore_getRegisterName(csh handle, unsigned int RegNo) |
225 | 0 | { |
226 | 0 | return TriCore_LLVM_getRegisterName(RegNo); |
227 | 0 | } |
228 | | |
229 | | #endif // CAPSTONE_HAS_TRICORE |