/src/capstonenext/arch/X86/X86Disassembler.c
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1 | | //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file is part of the X86 Disassembler. |
11 | | // It contains code to translate the data produced by the decoder into |
12 | | // MCInsts. |
13 | | // |
14 | | // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and |
15 | | // 64-bit X86 instruction sets. The main decode sequence for an assembly |
16 | | // instruction in this disassembler is: |
17 | | // |
18 | | // 1. Read the prefix bytes and determine the attributes of the instruction. |
19 | | // These attributes, recorded in enum attributeBits |
20 | | // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM |
21 | | // provides a mapping from bitmasks to contexts, which are represented by |
22 | | // enum InstructionContext (ibid.). |
23 | | // |
24 | | // 2. Read the opcode, and determine what kind of opcode it is. The |
25 | | // disassembler distinguishes four kinds of opcodes, which are enumerated in |
26 | | // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte |
27 | | // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a |
28 | | // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. |
29 | | // |
30 | | // 3. Depending on the opcode type, look in one of four ClassDecision structures |
31 | | // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which |
32 | | // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get |
33 | | // a ModRMDecision (ibid.). |
34 | | // |
35 | | // 4. Some instructions, such as escape opcodes or extended opcodes, or even |
36 | | // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the |
37 | | // ModR/M byte to complete decode. The ModRMDecision's type is an entry from |
38 | | // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the |
39 | | // ModR/M byte is required and how to interpret it. |
40 | | // |
41 | | // 5. After resolving the ModRMDecision, the disassembler has a unique ID |
42 | | // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in |
43 | | // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and |
44 | | // meanings of its operands. |
45 | | // |
46 | | // 6. For each operand, its encoding is an entry from OperandEncoding |
47 | | // (X86DisassemblerDecoderCommon.h) and its type is an entry from |
48 | | // OperandType (ibid.). The encoding indicates how to read it from the |
49 | | // instruction; the type indicates how to interpret the value once it has |
50 | | // been read. For example, a register operand could be stored in the R/M |
51 | | // field of the ModR/M byte, the REG field of the ModR/M byte, or added to |
52 | | // the main opcode. This is orthogonal from its meaning (an GPR or an XMM |
53 | | // register, for instance). Given this information, the operands can be |
54 | | // extracted and interpreted. |
55 | | // |
56 | | // 7. As the last step, the disassembler translates the instruction information |
57 | | // and operands into a format understandable by the client - in this case, an |
58 | | // MCInst for use by the MC infrastructure. |
59 | | // |
60 | | // The disassembler is broken broadly into two parts: the table emitter that |
61 | | // emits the instruction decode tables discussed above during compilation, and |
62 | | // the disassembler itself. The table emitter is documented in more detail in |
63 | | // utils/TableGen/X86DisassemblerEmitter.h. |
64 | | // |
65 | | // X86Disassembler.cpp contains the code responsible for step 7, and for |
66 | | // invoking the decoder to execute steps 1-6. |
67 | | // X86DisassemblerDecoderCommon.h contains the definitions needed by both the |
68 | | // table emitter and the disassembler. |
69 | | // X86DisassemblerDecoder.h contains the public interface of the decoder, |
70 | | // factored out into C for possible use by other projects. |
71 | | // X86DisassemblerDecoder.c contains the source code of the decoder, which is |
72 | | // responsible for steps 1-6. |
73 | | // |
74 | | //===----------------------------------------------------------------------===// |
75 | | |
76 | | /* Capstone Disassembly Engine */ |
77 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
78 | | |
79 | | #ifdef CAPSTONE_HAS_X86 |
80 | | |
81 | | #ifdef _MSC_VER |
82 | | #pragma warning(disable:4996) // disable MSVC's warning on strncpy() |
83 | | #pragma warning(disable:28719) // disable MSVC's warning on strncpy() |
84 | | #endif |
85 | | |
86 | | #include <capstone/platform.h> |
87 | | |
88 | | #if defined(CAPSTONE_HAS_OSXKERNEL) |
89 | | #include <Availability.h> |
90 | | #endif |
91 | | |
92 | | #include <string.h> |
93 | | |
94 | | #include "../../cs_priv.h" |
95 | | |
96 | | #include "X86BaseInfo.h" |
97 | | #include "X86Disassembler.h" |
98 | | #include "X86DisassemblerDecoderCommon.h" |
99 | | #include "X86DisassemblerDecoder.h" |
100 | | #include "../../MCInst.h" |
101 | | #include "../../utils.h" |
102 | | #include "X86Mapping.h" |
103 | | |
104 | | #define GET_REGINFO_ENUM |
105 | | #define GET_REGINFO_MC_DESC |
106 | | #include "X86GenRegisterInfo.inc" |
107 | | |
108 | | #define GET_INSTRINFO_ENUM |
109 | | #ifdef CAPSTONE_X86_REDUCE |
110 | | #include "X86GenInstrInfo_reduce.inc" |
111 | | #else |
112 | | #include "X86GenInstrInfo.inc" |
113 | | #endif |
114 | | |
115 | | // Fill-ins to make the compiler happy. These constants are never actually |
116 | | // assigned; they are just filler to make an automatically-generated switch |
117 | | // statement work. |
118 | | enum { |
119 | | X86_BX_SI = 500, |
120 | | X86_BX_DI = 501, |
121 | | X86_BP_SI = 502, |
122 | | X86_BP_DI = 503, |
123 | | X86_sib = 504, |
124 | | X86_sib64 = 505 |
125 | | }; |
126 | | |
127 | | // |
128 | | // Private code that translates from struct InternalInstructions to MCInsts. |
129 | | // |
130 | | |
131 | | /// translateRegister - Translates an internal register to the appropriate LLVM |
132 | | /// register, and appends it as an operand to an MCInst. |
133 | | /// |
134 | | /// @param mcInst - The MCInst to append to. |
135 | | /// @param reg - The Reg to append. |
136 | | static void translateRegister(MCInst *mcInst, Reg reg) |
137 | 1.44M | { |
138 | 322M | #define ENTRY(x) X86_##x, |
139 | 1.44M | static const uint16_t llvmRegnums[] = { |
140 | 1.44M | ALL_REGS |
141 | 1.44M | 0 |
142 | 1.44M | }; |
143 | 1.44M | #undef ENTRY |
144 | | |
145 | 1.44M | uint16_t llvmRegnum = llvmRegnums[reg]; |
146 | 1.44M | MCOperand_CreateReg0(mcInst, llvmRegnum); |
147 | 1.44M | } |
148 | | |
149 | | static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { |
150 | | 0, // SEG_OVERRIDE_NONE |
151 | | X86_CS, |
152 | | X86_SS, |
153 | | X86_DS, |
154 | | X86_ES, |
155 | | X86_FS, |
156 | | X86_GS |
157 | | }; |
158 | | |
159 | | /// translateSrcIndex - Appends a source index operand to an MCInst. |
160 | | /// |
161 | | /// @param mcInst - The MCInst to append to. |
162 | | /// @param insn - The internal instruction. |
163 | | static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) |
164 | 102k | { |
165 | 102k | unsigned baseRegNo; |
166 | | |
167 | 102k | if (insn->mode == MODE_64BIT) |
168 | 40.3k | baseRegNo = insn->hasAdSize ? X86_ESI : X86_RSI; |
169 | 62.3k | else if (insn->mode == MODE_32BIT) |
170 | 27.0k | baseRegNo = insn->hasAdSize ? X86_SI : X86_ESI; |
171 | 35.2k | else { |
172 | | // assert(insn->mode == MODE_16BIT); |
173 | 35.2k | baseRegNo = insn->hasAdSize ? X86_ESI : X86_SI; |
174 | 35.2k | } |
175 | | |
176 | 102k | MCOperand_CreateReg0(mcInst, baseRegNo); |
177 | | |
178 | 102k | MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); |
179 | | |
180 | 102k | return false; |
181 | 102k | } |
182 | | |
183 | | /// translateDstIndex - Appends a destination index operand to an MCInst. |
184 | | /// |
185 | | /// @param mcInst - The MCInst to append to. |
186 | | /// @param insn - The internal instruction. |
187 | | static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) |
188 | 116k | { |
189 | 116k | unsigned baseRegNo; |
190 | | |
191 | 116k | if (insn->mode == MODE_64BIT) |
192 | 40.2k | baseRegNo = insn->hasAdSize ? X86_EDI : X86_RDI; |
193 | 76.1k | else if (insn->mode == MODE_32BIT) |
194 | 34.2k | baseRegNo = insn->hasAdSize ? X86_DI : X86_EDI; |
195 | 41.9k | else { |
196 | | // assert(insn->mode == MODE_16BIT); |
197 | 41.9k | baseRegNo = insn->hasAdSize ? X86_EDI : X86_DI; |
198 | 41.9k | } |
199 | | |
200 | 116k | MCOperand_CreateReg0(mcInst, baseRegNo); |
201 | | |
202 | 116k | return false; |
203 | 116k | } |
204 | | |
205 | | /// translateImmediate - Appends an immediate operand to an MCInst. |
206 | | /// |
207 | | /// @param mcInst - The MCInst to append to. |
208 | | /// @param immediate - The immediate value to append. |
209 | | /// @param operand - The operand, as stored in the descriptor table. |
210 | | /// @param insn - The internal instruction. |
211 | | static void translateImmediate(MCInst *mcInst, uint64_t immediate, |
212 | | const OperandSpecifier *operand, InternalInstruction *insn) |
213 | 522k | { |
214 | 522k | OperandType type; |
215 | | |
216 | 522k | type = (OperandType)operand->type; |
217 | 522k | if (type == TYPE_REL) { |
218 | | //isBranch = true; |
219 | | //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize; |
220 | 141k | switch (operand->encoding) { |
221 | 0 | default: |
222 | 0 | break; |
223 | 7.72k | case ENCODING_Iv: |
224 | 7.72k | switch (insn->displacementSize) { |
225 | 0 | default: |
226 | 0 | break; |
227 | 0 | case 1: |
228 | 0 | if(immediate & 0x80) |
229 | 0 | immediate |= ~(0xffull); |
230 | 0 | break; |
231 | 2.93k | case 2: |
232 | 2.93k | if(immediate & 0x8000) |
233 | 1.55k | immediate |= ~(0xffffull); |
234 | 2.93k | break; |
235 | 4.79k | case 4: |
236 | 4.79k | if(immediate & 0x80000000) |
237 | 2.65k | immediate |= ~(0xffffffffull); |
238 | 4.79k | break; |
239 | 0 | case 8: |
240 | 0 | break; |
241 | 7.72k | } |
242 | 7.72k | break; |
243 | 128k | case ENCODING_IB: |
244 | 128k | if (immediate & 0x80) |
245 | 40.9k | immediate |= ~(0xffull); |
246 | 128k | break; |
247 | 2.39k | case ENCODING_IW: |
248 | 2.39k | if (immediate & 0x8000) |
249 | 1.65k | immediate |= ~(0xffffull); |
250 | 2.39k | break; |
251 | 3.37k | case ENCODING_ID: |
252 | 3.37k | if (immediate & 0x80000000) |
253 | 2.06k | immediate |= ~(0xffffffffull); |
254 | 3.37k | break; |
255 | 141k | } |
256 | 141k | } // By default sign-extend all X86 immediates based on their encoding. |
257 | 381k | else if (type == TYPE_IMM) { |
258 | 244k | switch (operand->encoding) { |
259 | 81.7k | default: |
260 | 81.7k | break; |
261 | 134k | case ENCODING_IB: |
262 | 134k | if(immediate & 0x80) |
263 | 48.8k | immediate |= ~(0xffull); |
264 | 134k | break; |
265 | 22.7k | case ENCODING_IW: |
266 | 22.7k | if(immediate & 0x8000) |
267 | 11.8k | immediate |= ~(0xffffull); |
268 | 22.7k | break; |
269 | 5.26k | case ENCODING_ID: |
270 | 5.26k | if(immediate & 0x80000000) |
271 | 1.81k | immediate |= ~(0xffffffffull); |
272 | 5.26k | break; |
273 | 730 | case ENCODING_IO: |
274 | 730 | break; |
275 | 244k | } |
276 | 244k | } else if (type == TYPE_IMM3) { |
277 | 17.2k | #ifndef CAPSTONE_X86_REDUCE |
278 | | // Check for immediates that printSSECC can't handle. |
279 | 17.2k | if (immediate >= 8) { |
280 | 10.0k | unsigned NewOpc = 0; |
281 | | |
282 | 10.0k | switch (MCInst_getOpcode(mcInst)) { |
283 | 0 | default: break; // never reach |
284 | 139 | case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; |
285 | 382 | case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; |
286 | 913 | case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; |
287 | 1.22k | case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; |
288 | 977 | case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; |
289 | 1.20k | case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; |
290 | 546 | case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; |
291 | 825 | case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; |
292 | 353 | case X86_VPCOMBri: NewOpc = X86_VPCOMBri_alt; break; |
293 | 150 | case X86_VPCOMBmi: NewOpc = X86_VPCOMBmi_alt; break; |
294 | 220 | case X86_VPCOMWri: NewOpc = X86_VPCOMWri_alt; break; |
295 | 719 | case X86_VPCOMWmi: NewOpc = X86_VPCOMWmi_alt; break; |
296 | 226 | case X86_VPCOMDri: NewOpc = X86_VPCOMDri_alt; break; |
297 | 183 | case X86_VPCOMDmi: NewOpc = X86_VPCOMDmi_alt; break; |
298 | 172 | case X86_VPCOMQri: NewOpc = X86_VPCOMQri_alt; break; |
299 | 183 | case X86_VPCOMQmi: NewOpc = X86_VPCOMQmi_alt; break; |
300 | 114 | case X86_VPCOMUBri: NewOpc = X86_VPCOMUBri_alt; break; |
301 | 155 | case X86_VPCOMUBmi: NewOpc = X86_VPCOMUBmi_alt; break; |
302 | 318 | case X86_VPCOMUWri: NewOpc = X86_VPCOMUWri_alt; break; |
303 | 239 | case X86_VPCOMUWmi: NewOpc = X86_VPCOMUWmi_alt; break; |
304 | 159 | case X86_VPCOMUDri: NewOpc = X86_VPCOMUDri_alt; break; |
305 | 211 | case X86_VPCOMUDmi: NewOpc = X86_VPCOMUDmi_alt; break; |
306 | 190 | case X86_VPCOMUQri: NewOpc = X86_VPCOMUQri_alt; break; |
307 | 260 | case X86_VPCOMUQmi: NewOpc = X86_VPCOMUQmi_alt; break; |
308 | 10.0k | } |
309 | | |
310 | | // Switch opcode to the one that doesn't get special printing. |
311 | 10.0k | if (NewOpc != 0) { |
312 | 10.0k | MCInst_setOpcode(mcInst, NewOpc); |
313 | 10.0k | } |
314 | 10.0k | } |
315 | 17.2k | #endif |
316 | 119k | } else if (type == TYPE_IMM5) { |
317 | 23.4k | #ifndef CAPSTONE_X86_REDUCE |
318 | | // Check for immediates that printAVXCC can't handle. |
319 | 23.4k | if (immediate >= 32) { |
320 | 19.7k | unsigned NewOpc = 0; |
321 | | |
322 | 19.7k | switch (MCInst_getOpcode(mcInst)) { |
323 | 6.63k | default: break; // unexpected opcode |
324 | 6.63k | case X86_VCMPPDrmi: NewOpc = X86_VCMPPDrmi_alt; break; |
325 | 241 | case X86_VCMPPDrri: NewOpc = X86_VCMPPDrri_alt; break; |
326 | 474 | case X86_VCMPPSrmi: NewOpc = X86_VCMPPSrmi_alt; break; |
327 | 384 | case X86_VCMPPSrri: NewOpc = X86_VCMPPSrri_alt; break; |
328 | 473 | case X86_VCMPSDrm: NewOpc = X86_VCMPSDrm_alt; break; |
329 | 1.12k | case X86_VCMPSDrr: NewOpc = X86_VCMPSDrr_alt; break; |
330 | 266 | case X86_VCMPSSrm: NewOpc = X86_VCMPSSrm_alt; break; |
331 | 344 | case X86_VCMPSSrr: NewOpc = X86_VCMPSSrr_alt; break; |
332 | 225 | case X86_VCMPPDYrmi: NewOpc = X86_VCMPPDYrmi_alt; break; |
333 | 706 | case X86_VCMPPDYrri: NewOpc = X86_VCMPPDYrri_alt; break; |
334 | 422 | case X86_VCMPPSYrmi: NewOpc = X86_VCMPPSYrmi_alt; break; |
335 | 889 | case X86_VCMPPSYrri: NewOpc = X86_VCMPPSYrri_alt; break; |
336 | 243 | case X86_VCMPPDZrmi: NewOpc = X86_VCMPPDZrmi_alt; break; |
337 | 926 | case X86_VCMPPDZrri: NewOpc = X86_VCMPPDZrri_alt; break; |
338 | 837 | case X86_VCMPPDZrrib: NewOpc = X86_VCMPPDZrrib_alt; break; |
339 | 760 | case X86_VCMPPSZrmi: NewOpc = X86_VCMPPSZrmi_alt; break; |
340 | 645 | case X86_VCMPPSZrri: NewOpc = X86_VCMPPSZrri_alt; break; |
341 | 172 | case X86_VCMPPSZrrib: NewOpc = X86_VCMPPSZrrib_alt; break; |
342 | 312 | case X86_VCMPPDZ128rmi: NewOpc = X86_VCMPPDZ128rmi_alt; break; |
343 | 275 | case X86_VCMPPDZ128rri: NewOpc = X86_VCMPPDZ128rri_alt; break; |
344 | 331 | case X86_VCMPPSZ128rmi: NewOpc = X86_VCMPPSZ128rmi_alt; break; |
345 | 118 | case X86_VCMPPSZ128rri: NewOpc = X86_VCMPPSZ128rri_alt; break; |
346 | 121 | case X86_VCMPPDZ256rmi: NewOpc = X86_VCMPPDZ256rmi_alt; break; |
347 | 140 | case X86_VCMPPDZ256rri: NewOpc = X86_VCMPPDZ256rri_alt; break; |
348 | 133 | case X86_VCMPPSZ256rmi: NewOpc = X86_VCMPPSZ256rmi_alt; break; |
349 | 241 | case X86_VCMPPSZ256rri: NewOpc = X86_VCMPPSZ256rri_alt; break; |
350 | 275 | case X86_VCMPSDZrm_Int: NewOpc = X86_VCMPSDZrmi_alt; break; |
351 | 179 | case X86_VCMPSDZrr_Int: NewOpc = X86_VCMPSDZrri_alt; break; |
352 | 170 | case X86_VCMPSDZrrb_Int: NewOpc = X86_VCMPSDZrrb_alt; break; |
353 | 439 | case X86_VCMPSSZrm_Int: NewOpc = X86_VCMPSSZrmi_alt; break; |
354 | 374 | case X86_VCMPSSZrr_Int: NewOpc = X86_VCMPSSZrri_alt; break; |
355 | 245 | case X86_VCMPSSZrrb_Int: NewOpc = X86_VCMPSSZrrb_alt; break; |
356 | 19.7k | } |
357 | | |
358 | | // Switch opcode to the one that doesn't get special printing. |
359 | 19.7k | if (NewOpc != 0) { |
360 | 13.1k | MCInst_setOpcode(mcInst, NewOpc); |
361 | 13.1k | } |
362 | 19.7k | } |
363 | 23.4k | #endif |
364 | 95.9k | } else if (type == TYPE_AVX512ICC) { |
365 | 14.4k | #ifndef CAPSTONE_X86_REDUCE |
366 | 14.4k | if (immediate >= 8 || ((immediate & 0x3) == 3)) { |
367 | 6.83k | unsigned NewOpc = 0; |
368 | 6.83k | switch (MCInst_getOpcode(mcInst)) { |
369 | 0 | default: // llvm_unreachable("unexpected opcode"); |
370 | 131 | case X86_VPCMPBZ128rmi: NewOpc = X86_VPCMPBZ128rmi_alt; break; |
371 | 142 | case X86_VPCMPBZ128rmik: NewOpc = X86_VPCMPBZ128rmik_alt; break; |
372 | 28 | case X86_VPCMPBZ128rri: NewOpc = X86_VPCMPBZ128rri_alt; break; |
373 | 10 | case X86_VPCMPBZ128rrik: NewOpc = X86_VPCMPBZ128rrik_alt; break; |
374 | 23 | case X86_VPCMPBZ256rmi: NewOpc = X86_VPCMPBZ256rmi_alt; break; |
375 | 2 | case X86_VPCMPBZ256rmik: NewOpc = X86_VPCMPBZ256rmik_alt; break; |
376 | 21 | case X86_VPCMPBZ256rri: NewOpc = X86_VPCMPBZ256rri_alt; break; |
377 | 15 | case X86_VPCMPBZ256rrik: NewOpc = X86_VPCMPBZ256rrik_alt; break; |
378 | 24 | case X86_VPCMPBZrmi: NewOpc = X86_VPCMPBZrmi_alt; break; |
379 | 83 | case X86_VPCMPBZrmik: NewOpc = X86_VPCMPBZrmik_alt; break; |
380 | 18 | case X86_VPCMPBZrri: NewOpc = X86_VPCMPBZrri_alt; break; |
381 | 17 | case X86_VPCMPBZrrik: NewOpc = X86_VPCMPBZrrik_alt; break; |
382 | 28 | case X86_VPCMPDZ128rmi: NewOpc = X86_VPCMPDZ128rmi_alt; break; |
383 | 305 | case X86_VPCMPDZ128rmib: NewOpc = X86_VPCMPDZ128rmib_alt; break; |
384 | 304 | case X86_VPCMPDZ128rmibk: NewOpc = X86_VPCMPDZ128rmibk_alt; break; |
385 | 12 | case X86_VPCMPDZ128rmik: NewOpc = X86_VPCMPDZ128rmik_alt; break; |
386 | 20 | case X86_VPCMPDZ128rri: NewOpc = X86_VPCMPDZ128rri_alt; break; |
387 | 15 | case X86_VPCMPDZ128rrik: NewOpc = X86_VPCMPDZ128rrik_alt; break; |
388 | 6 | case X86_VPCMPDZ256rmi: NewOpc = X86_VPCMPDZ256rmi_alt; break; |
389 | 232 | case X86_VPCMPDZ256rmib: NewOpc = X86_VPCMPDZ256rmib_alt; break; |
390 | 22 | case X86_VPCMPDZ256rmibk: NewOpc = X86_VPCMPDZ256rmibk_alt; break; |
391 | 15 | case X86_VPCMPDZ256rmik: NewOpc = X86_VPCMPDZ256rmik_alt; break; |
392 | 17 | case X86_VPCMPDZ256rri: NewOpc = X86_VPCMPDZ256rri_alt; break; |
393 | 3 | case X86_VPCMPDZ256rrik: NewOpc = X86_VPCMPDZ256rrik_alt; break; |
394 | 11 | case X86_VPCMPDZrmi: NewOpc = X86_VPCMPDZrmi_alt; break; |
395 | 15 | case X86_VPCMPDZrmib: NewOpc = X86_VPCMPDZrmib_alt; break; |
396 | 23 | case X86_VPCMPDZrmibk: NewOpc = X86_VPCMPDZrmibk_alt; break; |
397 | 21 | case X86_VPCMPDZrmik: NewOpc = X86_VPCMPDZrmik_alt; break; |
398 | 27 | case X86_VPCMPDZrri: NewOpc = X86_VPCMPDZrri_alt; break; |
399 | 13 | case X86_VPCMPDZrrik: NewOpc = X86_VPCMPDZrrik_alt; break; |
400 | 7 | case X86_VPCMPQZ128rmi: NewOpc = X86_VPCMPQZ128rmi_alt; break; |
401 | 714 | case X86_VPCMPQZ128rmib: NewOpc = X86_VPCMPQZ128rmib_alt; break; |
402 | 1.20k | case X86_VPCMPQZ128rmibk: NewOpc = X86_VPCMPQZ128rmibk_alt; break; |
403 | 53 | case X86_VPCMPQZ128rmik: NewOpc = X86_VPCMPQZ128rmik_alt; break; |
404 | 8 | case X86_VPCMPQZ128rri: NewOpc = X86_VPCMPQZ128rri_alt; break; |
405 | 9 | case X86_VPCMPQZ128rrik: NewOpc = X86_VPCMPQZ128rrik_alt; break; |
406 | 164 | case X86_VPCMPQZ256rmi: NewOpc = X86_VPCMPQZ256rmi_alt; break; |
407 | 27 | case X86_VPCMPQZ256rmib: NewOpc = X86_VPCMPQZ256rmib_alt; break; |
408 | 52 | case X86_VPCMPQZ256rmibk: NewOpc = X86_VPCMPQZ256rmibk_alt; break; |
409 | 56 | case X86_VPCMPQZ256rmik: NewOpc = X86_VPCMPQZ256rmik_alt; break; |
410 | 16 | case X86_VPCMPQZ256rri: NewOpc = X86_VPCMPQZ256rri_alt; break; |
411 | 34 | case X86_VPCMPQZ256rrik: NewOpc = X86_VPCMPQZ256rrik_alt; break; |
412 | 6 | case X86_VPCMPQZrmi: NewOpc = X86_VPCMPQZrmi_alt; break; |
413 | 1 | case X86_VPCMPQZrmib: NewOpc = X86_VPCMPQZrmib_alt; break; |
414 | 10 | case X86_VPCMPQZrmibk: NewOpc = X86_VPCMPQZrmibk_alt; break; |
415 | 12 | case X86_VPCMPQZrmik: NewOpc = X86_VPCMPQZrmik_alt; break; |
416 | 11 | case X86_VPCMPQZrri: NewOpc = X86_VPCMPQZrri_alt; break; |
417 | 19 | case X86_VPCMPQZrrik: NewOpc = X86_VPCMPQZrrik_alt; break; |
418 | 20 | case X86_VPCMPUBZ128rmi: NewOpc = X86_VPCMPUBZ128rmi_alt; break; |
419 | 1 | case X86_VPCMPUBZ128rmik: NewOpc = X86_VPCMPUBZ128rmik_alt; break; |
420 | 19 | case X86_VPCMPUBZ128rri: NewOpc = X86_VPCMPUBZ128rri_alt; break; |
421 | 28 | case X86_VPCMPUBZ128rrik: NewOpc = X86_VPCMPUBZ128rrik_alt; break; |
422 | 8 | case X86_VPCMPUBZ256rmi: NewOpc = X86_VPCMPUBZ256rmi_alt; break; |
423 | 260 | case X86_VPCMPUBZ256rmik: NewOpc = X86_VPCMPUBZ256rmik_alt; break; |
424 | 7 | case X86_VPCMPUBZ256rri: NewOpc = X86_VPCMPUBZ256rri_alt; break; |
425 | 14 | case X86_VPCMPUBZ256rrik: NewOpc = X86_VPCMPUBZ256rrik_alt; break; |
426 | 8 | case X86_VPCMPUBZrmi: NewOpc = X86_VPCMPUBZrmi_alt; break; |
427 | 22 | case X86_VPCMPUBZrmik: NewOpc = X86_VPCMPUBZrmik_alt; break; |
428 | 22 | case X86_VPCMPUBZrri: NewOpc = X86_VPCMPUBZrri_alt; break; |
429 | 65 | case X86_VPCMPUBZrrik: NewOpc = X86_VPCMPUBZrrik_alt; break; |
430 | 2 | case X86_VPCMPUDZ128rmi: NewOpc = X86_VPCMPUDZ128rmi_alt; break; |
431 | 22 | case X86_VPCMPUDZ128rmib: NewOpc = X86_VPCMPUDZ128rmib_alt; break; |
432 | 57 | case X86_VPCMPUDZ128rmibk: NewOpc = X86_VPCMPUDZ128rmibk_alt; break; |
433 | 207 | case X86_VPCMPUDZ128rmik: NewOpc = X86_VPCMPUDZ128rmik_alt; break; |
434 | 6 | case X86_VPCMPUDZ128rri: NewOpc = X86_VPCMPUDZ128rri_alt; break; |
435 | 23 | case X86_VPCMPUDZ128rrik: NewOpc = X86_VPCMPUDZ128rrik_alt; break; |
436 | 19 | case X86_VPCMPUDZ256rmi: NewOpc = X86_VPCMPUDZ256rmi_alt; break; |
437 | 99 | case X86_VPCMPUDZ256rmib: NewOpc = X86_VPCMPUDZ256rmib_alt; break; |
438 | 68 | case X86_VPCMPUDZ256rmibk: NewOpc = X86_VPCMPUDZ256rmibk_alt; break; |
439 | 10 | case X86_VPCMPUDZ256rmik: NewOpc = X86_VPCMPUDZ256rmik_alt; break; |
440 | 26 | case X86_VPCMPUDZ256rri: NewOpc = X86_VPCMPUDZ256rri_alt; break; |
441 | 12 | case X86_VPCMPUDZ256rrik: NewOpc = X86_VPCMPUDZ256rrik_alt; break; |
442 | 11 | case X86_VPCMPUDZrmi: NewOpc = X86_VPCMPUDZrmi_alt; break; |
443 | 7 | case X86_VPCMPUDZrmib: NewOpc = X86_VPCMPUDZrmib_alt; break; |
444 | 143 | case X86_VPCMPUDZrmibk: NewOpc = X86_VPCMPUDZrmibk_alt; break; |
445 | 22 | case X86_VPCMPUDZrmik: NewOpc = X86_VPCMPUDZrmik_alt; break; |
446 | 3 | case X86_VPCMPUDZrri: NewOpc = X86_VPCMPUDZrri_alt; break; |
447 | 10 | case X86_VPCMPUDZrrik: NewOpc = X86_VPCMPUDZrrik_alt; break; |
448 | 11 | case X86_VPCMPUQZ128rmi: NewOpc = X86_VPCMPUQZ128rmi_alt; break; |
449 | 47 | case X86_VPCMPUQZ128rmib: NewOpc = X86_VPCMPUQZ128rmib_alt; break; |
450 | 20 | case X86_VPCMPUQZ128rmibk: NewOpc = X86_VPCMPUQZ128rmibk_alt; break; |
451 | 6 | case X86_VPCMPUQZ128rmik: NewOpc = X86_VPCMPUQZ128rmik_alt; break; |
452 | 41 | case X86_VPCMPUQZ128rri: NewOpc = X86_VPCMPUQZ128rri_alt; break; |
453 | 7 | case X86_VPCMPUQZ128rrik: NewOpc = X86_VPCMPUQZ128rrik_alt; break; |
454 | 36 | case X86_VPCMPUQZ256rmi: NewOpc = X86_VPCMPUQZ256rmi_alt; break; |
455 | 86 | case X86_VPCMPUQZ256rmib: NewOpc = X86_VPCMPUQZ256rmib_alt; break; |
456 | 59 | case X86_VPCMPUQZ256rmibk: NewOpc = X86_VPCMPUQZ256rmibk_alt; break; |
457 | 9 | case X86_VPCMPUQZ256rmik: NewOpc = X86_VPCMPUQZ256rmik_alt; break; |
458 | 7 | case X86_VPCMPUQZ256rri: NewOpc = X86_VPCMPUQZ256rri_alt; break; |
459 | 70 | case X86_VPCMPUQZ256rrik: NewOpc = X86_VPCMPUQZ256rrik_alt; break; |
460 | 22 | case X86_VPCMPUQZrmi: NewOpc = X86_VPCMPUQZrmi_alt; break; |
461 | 9 | case X86_VPCMPUQZrmib: NewOpc = X86_VPCMPUQZrmib_alt; break; |
462 | 133 | case X86_VPCMPUQZrmibk: NewOpc = X86_VPCMPUQZrmibk_alt; break; |
463 | 23 | case X86_VPCMPUQZrmik: NewOpc = X86_VPCMPUQZrmik_alt; break; |
464 | 39 | case X86_VPCMPUQZrri: NewOpc = X86_VPCMPUQZrri_alt; break; |
465 | 18 | case X86_VPCMPUQZrrik: NewOpc = X86_VPCMPUQZrrik_alt; break; |
466 | 5 | case X86_VPCMPUWZ128rmi: NewOpc = X86_VPCMPUWZ128rmi_alt; break; |
467 | 13 | case X86_VPCMPUWZ128rmik: NewOpc = X86_VPCMPUWZ128rmik_alt; break; |
468 | 5 | case X86_VPCMPUWZ128rri: NewOpc = X86_VPCMPUWZ128rri_alt; break; |
469 | 12 | case X86_VPCMPUWZ128rrik: NewOpc = X86_VPCMPUWZ128rrik_alt; break; |
470 | 17 | case X86_VPCMPUWZ256rmi: NewOpc = X86_VPCMPUWZ256rmi_alt; break; |
471 | 18 | case X86_VPCMPUWZ256rmik: NewOpc = X86_VPCMPUWZ256rmik_alt; break; |
472 | 12 | case X86_VPCMPUWZ256rri: NewOpc = X86_VPCMPUWZ256rri_alt; break; |
473 | 28 | case X86_VPCMPUWZ256rrik: NewOpc = X86_VPCMPUWZ256rrik_alt; break; |
474 | 47 | case X86_VPCMPUWZrmi: NewOpc = X86_VPCMPUWZrmi_alt; break; |
475 | 47 | case X86_VPCMPUWZrmik: NewOpc = X86_VPCMPUWZrmik_alt; break; |
476 | 35 | case X86_VPCMPUWZrri: NewOpc = X86_VPCMPUWZrri_alt; break; |
477 | 13 | case X86_VPCMPUWZrrik: NewOpc = X86_VPCMPUWZrrik_alt; break; |
478 | 13 | case X86_VPCMPWZ128rmi: NewOpc = X86_VPCMPWZ128rmi_alt; break; |
479 | 36 | case X86_VPCMPWZ128rmik: NewOpc = X86_VPCMPWZ128rmik_alt; break; |
480 | 5 | case X86_VPCMPWZ128rri: NewOpc = X86_VPCMPWZ128rri_alt; break; |
481 | 15 | case X86_VPCMPWZ128rrik: NewOpc = X86_VPCMPWZ128rrik_alt; break; |
482 | 13 | case X86_VPCMPWZ256rmi: NewOpc = X86_VPCMPWZ256rmi_alt; break; |
483 | 18 | case X86_VPCMPWZ256rmik: NewOpc = X86_VPCMPWZ256rmik_alt; break; |
484 | 35 | case X86_VPCMPWZ256rri: NewOpc = X86_VPCMPWZ256rri_alt; break; |
485 | 12 | case X86_VPCMPWZ256rrik: NewOpc = X86_VPCMPWZ256rrik_alt; break; |
486 | 160 | case X86_VPCMPWZrmi: NewOpc = X86_VPCMPWZrmi_alt; break; |
487 | 175 | case X86_VPCMPWZrmik: NewOpc = X86_VPCMPWZrmik_alt; break; |
488 | 49 | case X86_VPCMPWZrri: NewOpc = X86_VPCMPWZrri_alt; break; |
489 | 180 | case X86_VPCMPWZrrik: NewOpc = X86_VPCMPWZrrik_alt; break; |
490 | 6.83k | } |
491 | | |
492 | | // Switch opcode to the one that doesn't get special printing. |
493 | 6.83k | if (NewOpc != 0) { |
494 | 6.83k | MCInst_setOpcode(mcInst, NewOpc); |
495 | 6.83k | } |
496 | 6.83k | } |
497 | 14.4k | #endif |
498 | 14.4k | } |
499 | | |
500 | 522k | switch (type) { |
501 | 773 | case TYPE_XMM: |
502 | 773 | MCOperand_CreateReg0(mcInst, X86_XMM0 + ((uint32_t)immediate >> 4)); |
503 | 773 | return; |
504 | 3.13k | case TYPE_YMM: |
505 | 3.13k | MCOperand_CreateReg0(mcInst, X86_YMM0 + ((uint32_t)immediate >> 4)); |
506 | 3.13k | return; |
507 | 0 | case TYPE_ZMM: |
508 | 0 | MCOperand_CreateReg0(mcInst, X86_ZMM0 + ((uint32_t)immediate >> 4)); |
509 | 0 | return; |
510 | 518k | default: |
511 | | // operand is 64 bits wide. Do nothing. |
512 | 518k | break; |
513 | 522k | } |
514 | | |
515 | 518k | MCOperand_CreateImm0(mcInst, immediate); |
516 | | |
517 | 518k | if (type == TYPE_MOFFS) { |
518 | 21.0k | MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); |
519 | 21.0k | } |
520 | 518k | } |
521 | | |
522 | | /// translateRMRegister - Translates a register stored in the R/M field of the |
523 | | /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. |
524 | | /// @param mcInst - The MCInst to append to. |
525 | | /// @param insn - The internal instruction to extract the R/M field |
526 | | /// from. |
527 | | /// @return - 0 on success; -1 otherwise |
528 | | static bool translateRMRegister(MCInst *mcInst, InternalInstruction *insn) |
529 | 337k | { |
530 | 337k | if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { |
531 | | //debug("A R/M register operand may not have a SIB byte"); |
532 | 0 | return true; |
533 | 0 | } |
534 | | |
535 | 337k | switch (insn->eaBase) { |
536 | 0 | case EA_BASE_NONE: |
537 | | //debug("EA_BASE_NONE for ModR/M base"); |
538 | 0 | return true; |
539 | 0 | #define ENTRY(x) case EA_BASE_##x: |
540 | 0 | ALL_EA_BASES |
541 | 0 | #undef ENTRY |
542 | | //debug("A R/M register operand may not have a base; " |
543 | | // "the operand must be a register."); |
544 | 0 | return true; |
545 | 0 | #define ENTRY(x) \ |
546 | 337k | case EA_REG_##x: \ |
547 | 337k | MCOperand_CreateReg0(mcInst, X86_##x); break; |
548 | 0 | ALL_REGS |
549 | 0 | #undef ENTRY |
550 | 0 | default: |
551 | | //debug("Unexpected EA base register"); |
552 | 0 | return true; |
553 | 337k | } |
554 | | |
555 | 337k | return false; |
556 | 337k | } |
557 | | |
558 | | /// translateRMMemory - Translates a memory operand stored in the Mod and R/M |
559 | | /// fields of an internal instruction (and possibly its SIB byte) to a memory |
560 | | /// operand in LLVM's format, and appends it to an MCInst. |
561 | | /// |
562 | | /// @param mcInst - The MCInst to append to. |
563 | | /// @param insn - The instruction to extract Mod, R/M, and SIB fields |
564 | | /// from. |
565 | | /// @return - 0 on success; nonzero otherwise |
566 | | static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn) |
567 | 814k | { |
568 | | // Addresses in an MCInst are represented as five operands: |
569 | | // 1. basereg (register) The R/M base, or (if there is a SIB) the |
570 | | // SIB base |
571 | | // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified |
572 | | // scale amount |
573 | | // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) |
574 | | // the index (which is multiplied by the |
575 | | // scale amount) |
576 | | // 4. displacement (immediate) 0, or the displacement if there is one |
577 | | // 5. segmentreg (register) x86_registerNONE for now, but could be set |
578 | | // if we have segment overrides |
579 | 814k | int scaleAmount, indexReg; |
580 | | |
581 | 814k | if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { |
582 | 44.8k | if (insn->sibBase != SIB_BASE_NONE) { |
583 | 41.9k | switch (insn->sibBase) { |
584 | 0 | #define ENTRY(x) \ |
585 | 41.9k | case SIB_BASE_##x: \ |
586 | 41.9k | MCOperand_CreateReg0(mcInst, X86_##x); break; |
587 | 0 | ALL_SIB_BASES |
588 | 0 | #undef ENTRY |
589 | 0 | default: |
590 | | //debug("Unexpected sibBase"); |
591 | 0 | return true; |
592 | 41.9k | } |
593 | 41.9k | } else { |
594 | 2.86k | MCOperand_CreateReg0(mcInst, 0); |
595 | 2.86k | } |
596 | | |
597 | 44.8k | if (insn->sibIndex != SIB_INDEX_NONE) { |
598 | 34.9k | switch (insn->sibIndex) { |
599 | 0 | default: |
600 | | //debug("Unexpected sibIndex"); |
601 | 0 | return true; |
602 | 0 | #define ENTRY(x) \ |
603 | 34.9k | case SIB_INDEX_##x: \ |
604 | 34.9k | indexReg = X86_##x; break; |
605 | 0 | EA_BASES_32BIT |
606 | 13 | EA_BASES_64BIT |
607 | 272 | REGS_XMM |
608 | 44 | REGS_YMM |
609 | 34.9k | REGS_ZMM |
610 | 34.9k | #undef ENTRY |
611 | 34.9k | } |
612 | 34.9k | } else { |
613 | | // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present, |
614 | | // but no index is used and modrm alone should have been enough. |
615 | | // -No base register in 32-bit mode. In 64-bit mode this is used to |
616 | | // avoid rip-relative addressing. |
617 | | // -Any base register used other than ESP/RSP/R12D/R12. Using these as a |
618 | | // base always requires a SIB byte. |
619 | | // -A scale other than 1 is used. |
620 | 9.82k | if (insn->sibScale != 1 || |
621 | 9.82k | (insn->sibBase == SIB_BASE_NONE && insn->mode != MODE_64BIT) || |
622 | 9.82k | (insn->sibBase != SIB_BASE_NONE && |
623 | 5.35k | insn->sibBase != SIB_BASE_ESP && insn->sibBase != SIB_BASE_RSP && |
624 | 5.98k | insn->sibBase != SIB_BASE_R12D && insn->sibBase != SIB_BASE_R12)) { |
625 | 5.98k | indexReg = insn->addressSize == 4? X86_EIZ : X86_RIZ; |
626 | 5.98k | } else |
627 | 3.84k | indexReg = 0; |
628 | 9.82k | } |
629 | | |
630 | 44.8k | scaleAmount = insn->sibScale; |
631 | 769k | } else { |
632 | 769k | switch (insn->eaBase) { |
633 | 20.6k | case EA_BASE_NONE: |
634 | 20.6k | if (insn->eaDisplacement == EA_DISP_NONE) { |
635 | | //debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); |
636 | 0 | return true; |
637 | 0 | } |
638 | 20.6k | if (insn->mode == MODE_64BIT) { |
639 | 5.08k | if (insn->prefix3 == 0x67) // address-size prefix overrides RIP relative addressing |
640 | 794 | MCOperand_CreateReg0(mcInst, X86_EIP); |
641 | 4.29k | else |
642 | | // Section 2.2.1.6 |
643 | 4.29k | MCOperand_CreateReg0(mcInst, insn->addressSize == 4 ? X86_EIP : X86_RIP); |
644 | 15.5k | } else { |
645 | 15.5k | MCOperand_CreateReg0(mcInst, 0); |
646 | 15.5k | } |
647 | | |
648 | 20.6k | indexReg = 0; |
649 | 20.6k | break; |
650 | 115k | case EA_BASE_BX_SI: |
651 | 115k | MCOperand_CreateReg0(mcInst, X86_BX); |
652 | 115k | indexReg = X86_SI; |
653 | 115k | break; |
654 | 34.6k | case EA_BASE_BX_DI: |
655 | 34.6k | MCOperand_CreateReg0(mcInst, X86_BX); |
656 | 34.6k | indexReg = X86_DI; |
657 | 34.6k | break; |
658 | 26.1k | case EA_BASE_BP_SI: |
659 | 26.1k | MCOperand_CreateReg0(mcInst, X86_BP); |
660 | 26.1k | indexReg = X86_SI; |
661 | 26.1k | break; |
662 | 24.7k | case EA_BASE_BP_DI: |
663 | 24.7k | MCOperand_CreateReg0(mcInst, X86_BP); |
664 | 24.7k | indexReg = X86_DI; |
665 | 24.7k | break; |
666 | 547k | default: |
667 | 547k | indexReg = 0; |
668 | 547k | switch (insn->eaBase) { |
669 | 0 | default: |
670 | | //debug("Unexpected eaBase"); |
671 | 0 | return true; |
672 | | // Here, we will use the fill-ins defined above. However, |
673 | | // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and |
674 | | // sib and sib64 were handled in the top-level if, so they're only |
675 | | // placeholders to keep the compiler happy. |
676 | 0 | #define ENTRY(x) \ |
677 | 547k | case EA_BASE_##x: \ |
678 | 547k | MCOperand_CreateReg0(mcInst, X86_##x); break; |
679 | 0 | ALL_EA_BASES |
680 | 0 | #undef ENTRY |
681 | 0 | #define ENTRY(x) case EA_REG_##x: |
682 | 2.24k | ALL_REGS |
683 | 0 | #undef ENTRY |
684 | | //debug("A R/M memory operand may not be a register; " |
685 | | // "the base field must be a base."); |
686 | 0 | return true; |
687 | 547k | } |
688 | 769k | } |
689 | | |
690 | 769k | scaleAmount = 1; |
691 | 769k | } |
692 | | |
693 | 814k | MCOperand_CreateImm0(mcInst, scaleAmount); |
694 | 814k | MCOperand_CreateReg0(mcInst, indexReg); |
695 | 814k | MCOperand_CreateImm0(mcInst, insn->displacement); |
696 | | |
697 | 814k | MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); |
698 | | |
699 | 814k | return false; |
700 | 814k | } |
701 | | |
702 | | /// translateRM - Translates an operand stored in the R/M (and possibly SIB) |
703 | | /// byte of an instruction to LLVM form, and appends it to an MCInst. |
704 | | /// |
705 | | /// @param mcInst - The MCInst to append to. |
706 | | /// @param operand - The operand, as stored in the descriptor table. |
707 | | /// @param insn - The instruction to extract Mod, R/M, and SIB fields |
708 | | /// from. |
709 | | /// @return - 0 on success; nonzero otherwise |
710 | | static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand, |
711 | | InternalInstruction *insn) |
712 | 1.15M | { |
713 | 1.15M | switch (operand->type) { |
714 | 0 | default: |
715 | | //debug("Unexpected type for a R/M operand"); |
716 | 0 | return true; |
717 | 130k | case TYPE_R8: |
718 | 132k | case TYPE_R16: |
719 | 134k | case TYPE_R32: |
720 | 152k | case TYPE_R64: |
721 | 272k | case TYPE_Rv: |
722 | 278k | case TYPE_MM64: |
723 | 304k | case TYPE_XMM: |
724 | 318k | case TYPE_YMM: |
725 | 333k | case TYPE_ZMM: |
726 | 335k | case TYPE_VK: |
727 | 335k | case TYPE_DEBUGREG: |
728 | 335k | case TYPE_CONTROLREG: |
729 | 337k | case TYPE_BNDR: |
730 | 337k | return translateRMRegister(mcInst, insn); |
731 | 806k | case TYPE_M: |
732 | 809k | case TYPE_MVSIBX: |
733 | 812k | case TYPE_MVSIBY: |
734 | 814k | case TYPE_MVSIBZ: |
735 | 814k | return translateRMMemory(mcInst, insn); |
736 | 1.15M | } |
737 | 1.15M | } |
738 | | |
739 | | /// translateFPRegister - Translates a stack position on the FPU stack to its |
740 | | /// LLVM form, and appends it to an MCInst. |
741 | | /// |
742 | | /// @param mcInst - The MCInst to append to. |
743 | | /// @param stackPos - The stack position to translate. |
744 | | static void translateFPRegister(MCInst *mcInst, uint8_t stackPos) |
745 | 9.79k | { |
746 | 9.79k | MCOperand_CreateReg0(mcInst, X86_ST0 + stackPos); |
747 | 9.79k | } |
748 | | |
749 | | /// translateMaskRegister - Translates a 3-bit mask register number to |
750 | | /// LLVM form, and appends it to an MCInst. |
751 | | /// |
752 | | /// @param mcInst - The MCInst to append to. |
753 | | /// @param maskRegNum - Number of mask register from 0 to 7. |
754 | | /// @return - false on success; true otherwise. |
755 | | static bool translateMaskRegister(MCInst *mcInst, uint8_t maskRegNum) |
756 | 67.4k | { |
757 | 67.4k | if (maskRegNum >= 8) { |
758 | | // debug("Invalid mask register number"); |
759 | 0 | return true; |
760 | 0 | } |
761 | | |
762 | 67.4k | MCOperand_CreateReg0(mcInst, X86_K0 + maskRegNum); |
763 | | |
764 | 67.4k | return false; |
765 | 67.4k | } |
766 | | |
767 | | /// translateOperand - Translates an operand stored in an internal instruction |
768 | | /// to LLVM's format and appends it to an MCInst. |
769 | | /// |
770 | | /// @param mcInst - The MCInst to append to. |
771 | | /// @param operand - The operand, as stored in the descriptor table. |
772 | | /// @param insn - The internal instruction. |
773 | | /// @return - false on success; true otherwise. |
774 | | static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, InternalInstruction *insn) |
775 | 3.84M | { |
776 | 3.84M | switch (operand->encoding) { |
777 | 995k | case ENCODING_REG: |
778 | 995k | translateRegister(mcInst, insn->reg); |
779 | 995k | return false; |
780 | 67.4k | case ENCODING_WRITEMASK: |
781 | 67.4k | return translateMaskRegister(mcInst, insn->writemask); |
782 | 7.66M | CASE_ENCODING_RM: |
783 | 7.66M | CASE_ENCODING_VSIB: |
784 | 1.15M | return translateRM(mcInst, operand, insn); |
785 | 377k | case ENCODING_IB: |
786 | 402k | case ENCODING_IW: |
787 | 411k | case ENCODING_ID: |
788 | 412k | case ENCODING_IO: |
789 | 501k | case ENCODING_Iv: |
790 | 522k | case ENCODING_Ia: |
791 | 522k | translateImmediate(mcInst, insn->immediates[insn->numImmediatesTranslated++], operand, insn); |
792 | 522k | return false; |
793 | 4.41k | case ENCODING_IRC: |
794 | 4.41k | MCOperand_CreateImm0(mcInst, insn->RC); |
795 | 4.41k | return false; |
796 | 102k | case ENCODING_SI: |
797 | 102k | return translateSrcIndex(mcInst, insn); |
798 | 116k | case ENCODING_DI: |
799 | 116k | return translateDstIndex(mcInst, insn); |
800 | 24.4k | case ENCODING_RB: |
801 | 24.4k | case ENCODING_RW: |
802 | 24.4k | case ENCODING_RD: |
803 | 58.5k | case ENCODING_RO: |
804 | 364k | case ENCODING_Rv: |
805 | 364k | translateRegister(mcInst, insn->opcodeRegister); |
806 | 364k | return false; |
807 | 9.79k | case ENCODING_FP: |
808 | 9.79k | translateFPRegister(mcInst, insn->modRM & 7); |
809 | 9.79k | return false; |
810 | 84.3k | case ENCODING_VVVV: |
811 | 84.3k | translateRegister(mcInst, insn->vvvv); |
812 | 84.3k | return false; |
813 | 424k | case ENCODING_DUP: |
814 | 424k | return translateOperand(mcInst, &insn->operands[operand->type - TYPE_DUP0], insn); |
815 | 0 | default: |
816 | | //debug("Unhandled operand encoding during translation"); |
817 | 0 | return true; |
818 | 3.84M | } |
819 | 3.84M | } |
820 | | |
821 | | static bool translateInstruction(MCInst *mcInst, InternalInstruction *insn) |
822 | 2.02M | { |
823 | 2.02M | int index; |
824 | | |
825 | 2.02M | if (!insn->spec) { |
826 | | //debug("Instruction has no specification"); |
827 | 0 | return true; |
828 | 0 | } |
829 | | |
830 | 2.02M | MCInst_clear(mcInst); |
831 | 2.02M | MCInst_setOpcode(mcInst, insn->instructionID); |
832 | | |
833 | | // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 |
834 | | // prefix bytes should be disassembled as xrelease and xacquire then set the |
835 | | // opcode to those instead of the rep and repne opcodes. |
836 | 2.02M | #ifndef CAPSTONE_X86_REDUCE |
837 | 2.02M | if (insn->xAcquireRelease) { |
838 | 5.86k | if (MCInst_getOpcode(mcInst) == X86_REP_PREFIX) |
839 | 0 | MCInst_setOpcode(mcInst, X86_XRELEASE_PREFIX); |
840 | 5.86k | else if (MCInst_getOpcode(mcInst) == X86_REPNE_PREFIX) |
841 | 0 | MCInst_setOpcode(mcInst, X86_XACQUIRE_PREFIX); |
842 | 5.86k | } |
843 | 2.02M | #endif |
844 | | |
845 | 2.02M | insn->numImmediatesTranslated = 0; |
846 | | |
847 | 14.1M | for (index = 0; index < X86_MAX_OPERANDS; ++index) { |
848 | 12.1M | if (insn->operands[index].encoding != ENCODING_NONE) { |
849 | 3.41M | if (translateOperand(mcInst, &insn->operands[index], insn)) { |
850 | 0 | return true; |
851 | 0 | } |
852 | 3.41M | } |
853 | 12.1M | } |
854 | | |
855 | 2.02M | return false; |
856 | 2.02M | } |
857 | | |
858 | | static int reader(const struct reader_info *info, uint8_t *byte, uint64_t address) |
859 | 8.55M | { |
860 | 8.55M | if (address - info->offset >= info->size) |
861 | | // out of buffer range |
862 | 6.17k | return -1; |
863 | | |
864 | 8.55M | *byte = info->code[address - info->offset]; |
865 | | |
866 | 8.55M | return 0; |
867 | 8.55M | } |
868 | | |
869 | | // copy x86 detail information from internal structure to public structure |
870 | | static void update_pub_insn(cs_insn *pub, InternalInstruction *inter) |
871 | 2.02M | { |
872 | 2.02M | if (inter->vectorExtensionType != 0) { |
873 | 115k | memcpy(pub->detail->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->detail->x86.opcode)); |
874 | 1.91M | } else { |
875 | 1.91M | if (inter->twoByteEscape) { |
876 | 79.8k | if (inter->threeByteEscape) { |
877 | 0 | pub->detail->x86.opcode[0] = inter->twoByteEscape; |
878 | 0 | pub->detail->x86.opcode[1] = inter->threeByteEscape; |
879 | 0 | pub->detail->x86.opcode[2] = inter->opcode; |
880 | 79.8k | } else { |
881 | 79.8k | pub->detail->x86.opcode[0] = inter->twoByteEscape; |
882 | 79.8k | pub->detail->x86.opcode[1] = inter->opcode; |
883 | 79.8k | } |
884 | 1.83M | } else { |
885 | 1.83M | pub->detail->x86.opcode[0] = inter->opcode; |
886 | 1.83M | } |
887 | 1.91M | } |
888 | | |
889 | 2.02M | pub->detail->x86.rex = inter->rexPrefix; |
890 | | |
891 | 2.02M | pub->detail->x86.addr_size = inter->addressSize; |
892 | | |
893 | 2.02M | pub->detail->x86.modrm = inter->orgModRM; |
894 | 2.02M | pub->detail->x86.encoding.modrm_offset = inter->modRMOffset; |
895 | | |
896 | 2.02M | pub->detail->x86.sib = inter->sib; |
897 | 2.02M | pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex); |
898 | 2.02M | pub->detail->x86.sib_scale = inter->sibScale; |
899 | 2.02M | pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase); |
900 | | |
901 | 2.02M | pub->detail->x86.disp = inter->displacement; |
902 | 2.02M | if (inter->consumedDisplacement) { |
903 | 276k | pub->detail->x86.encoding.disp_offset = inter->displacementOffset; |
904 | 276k | pub->detail->x86.encoding.disp_size = inter->displacementSize; |
905 | 276k | } |
906 | | |
907 | 2.02M | pub->detail->x86.encoding.imm_offset = inter->immediateOffset; |
908 | 2.02M | if (pub->detail->x86.encoding.imm_size == 0 && inter->immediateOffset != 0) |
909 | 490k | pub->detail->x86.encoding.imm_size = inter->immediateSize; |
910 | 2.02M | } |
911 | | |
912 | | void X86_init(MCRegisterInfo *MRI) |
913 | 15.7k | { |
914 | | // InitMCRegisterInfo(), X86GenRegisterInfo.inc |
915 | | // RI->InitMCRegisterInfo(X86RegDesc, 277, |
916 | | // RA, PC, |
917 | | // X86MCRegisterClasses, 86, |
918 | | // X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, |
919 | | // X86RegClassStrings, |
920 | | // X86SubRegIdxLists, 9, |
921 | | // X86SubRegIdxRanges, X86RegEncodingTable); |
922 | | /* |
923 | | InitMCRegisterInfo(X86RegDesc, 234, |
924 | | RA, PC, |
925 | | X86MCRegisterClasses, 79, |
926 | | X86RegUnitRoots, 119, X86RegDiffLists, X86RegStrings, |
927 | | X86SubRegIdxLists, 7, |
928 | | X86SubRegIdxRanges, X86RegEncodingTable); |
929 | | */ |
930 | | |
931 | 15.7k | MCRegisterInfo_InitMCRegisterInfo(MRI, X86RegDesc, 277, |
932 | 15.7k | 0, 0, |
933 | 15.7k | X86MCRegisterClasses, 86, |
934 | 15.7k | 0, 0, X86RegDiffLists, 0, |
935 | 15.7k | X86SubRegIdxLists, 9, |
936 | 15.7k | 0); |
937 | 15.7k | } |
938 | | |
939 | | // Public interface for the disassembler |
940 | | bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, |
941 | | MCInst *instr, uint16_t *size, uint64_t address, void *_info) |
942 | 2.03M | { |
943 | 2.03M | cs_struct *handle = (cs_struct *)(uintptr_t)ud; |
944 | 2.03M | InternalInstruction insn = { 0 }; |
945 | 2.03M | struct reader_info info; |
946 | 2.03M | int ret; |
947 | 2.03M | bool result; |
948 | | |
949 | 2.03M | info.code = code; |
950 | 2.03M | info.size = code_len; |
951 | 2.03M | info.offset = address; |
952 | | |
953 | 2.03M | if (instr->flat_insn->detail) { |
954 | | // instr->flat_insn->detail initialization: 3 alternatives |
955 | | |
956 | | // 1. The whole structure, this is how it's done in other arch disassemblers |
957 | | // Probably overkill since cs_detail is huge because of the 36 operands of ARM |
958 | | |
959 | | //memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); |
960 | | |
961 | | // 2. Only the part relevant to x86 |
962 | 2.03M | memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86) + sizeof(cs_x86)); |
963 | | |
964 | | // 3. The relevant part except for x86.operands |
965 | | // sizeof(cs_x86) is 0x1c0, sizeof(x86.operands) is 0x180 |
966 | | // marginally faster, should be okay since x86.op_count is set to 0 |
967 | | |
968 | | //memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86)+offsetof(cs_x86, operands)); |
969 | 2.03M | } |
970 | | |
971 | 2.03M | if (handle->mode & CS_MODE_16) |
972 | 695k | ret = decodeInstruction(&insn, |
973 | 695k | reader, &info, |
974 | 695k | address, |
975 | 695k | MODE_16BIT); |
976 | 1.34M | else if (handle->mode & CS_MODE_32) |
977 | 710k | ret = decodeInstruction(&insn, |
978 | 710k | reader, &info, |
979 | 710k | address, |
980 | 710k | MODE_32BIT); |
981 | 630k | else |
982 | 630k | ret = decodeInstruction(&insn, |
983 | 630k | reader, &info, |
984 | 630k | address, |
985 | 630k | MODE_64BIT); |
986 | | |
987 | 2.03M | if (ret) { |
988 | | // *size = (uint16_t)(insn.readerCursor - address); |
989 | 9.52k | return false; |
990 | 2.02M | } else { |
991 | 2.02M | *size = (uint16_t)insn.length; |
992 | | |
993 | 2.02M | result = (!translateInstruction(instr, &insn)) ? true : false; |
994 | 2.02M | if (result) { |
995 | 2.02M | unsigned Flags = X86_IP_NO_PREFIX; |
996 | 2.02M | instr->imm_size = insn.immSize; |
997 | | |
998 | | // copy all prefixes |
999 | 2.02M | instr->x86_prefix[0] = insn.prefix0; |
1000 | 2.02M | instr->x86_prefix[1] = insn.prefix1; |
1001 | 2.02M | instr->x86_prefix[2] = insn.prefix2; |
1002 | 2.02M | instr->x86_prefix[3] = insn.prefix3; |
1003 | 2.02M | instr->xAcquireRelease = insn.xAcquireRelease; |
1004 | | |
1005 | 2.02M | if (handle->detail_opt) { |
1006 | 2.02M | update_pub_insn(instr->flat_insn, &insn); |
1007 | 2.02M | } |
1008 | | |
1009 | 2.02M | if (insn.hasAdSize) |
1010 | 14.3k | Flags |= X86_IP_HAS_AD_SIZE; |
1011 | | |
1012 | 2.02M | if (!insn.mandatoryPrefix) { |
1013 | 2.00M | if (insn.hasOpSize) |
1014 | 31.9k | Flags |= X86_IP_HAS_OP_SIZE; |
1015 | | |
1016 | 2.00M | if (insn.repeatPrefix == 0xf2) |
1017 | 45.8k | Flags |= X86_IP_HAS_REPEAT_NE; |
1018 | 1.95M | else if (insn.repeatPrefix == 0xf3 && |
1019 | | // It should not be 'pause' f3 90 |
1020 | 1.95M | insn.opcode != 0x90) |
1021 | 39.6k | Flags |= X86_IP_HAS_REPEAT; |
1022 | 2.00M | if (insn.hasLockPrefix) |
1023 | 50.9k | Flags |= X86_IP_HAS_LOCK; |
1024 | 2.00M | } |
1025 | | |
1026 | 2.02M | instr->flags = Flags; |
1027 | 2.02M | } |
1028 | | |
1029 | 2.02M | return result; |
1030 | 2.02M | } |
1031 | 2.03M | } |
1032 | | |
1033 | | #endif |