/src/capstonenext/arch/X86/X86Mapping.c
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1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_X86 |
5 | | |
6 | | #if defined(CAPSTONE_HAS_OSXKERNEL) |
7 | | #include <Availability.h> |
8 | | #endif |
9 | | |
10 | | #include <string.h> |
11 | | #ifndef CAPSTONE_HAS_OSXKERNEL |
12 | | #include <stdlib.h> |
13 | | #endif |
14 | | |
15 | | #include "../../Mapping.h" |
16 | | #include "../../MCInstPrinter.h" |
17 | | #include "X86Mapping.h" |
18 | | #include "X86DisassemblerDecoder.h" |
19 | | |
20 | | #include "../../utils.h" |
21 | | |
22 | | |
23 | | const uint64_t arch_masks[9] = { |
24 | | 0, 0xff, |
25 | | 0xffff, // 16bit |
26 | | 0, |
27 | | 0xffffffff, // 32bit |
28 | | 0, 0, 0, |
29 | | 0xffffffffffffffffLL // 64bit |
30 | | }; |
31 | | |
32 | | static const x86_reg sib_base_map[] = { |
33 | | X86_REG_INVALID, |
34 | | #define ENTRY(x) X86_REG_##x, |
35 | | ALL_SIB_BASES |
36 | | #undef ENTRY |
37 | | }; |
38 | | |
39 | | // Fill-ins to make the compiler happy. These constants are never actually |
40 | | // assigned; they are just filler to make an automatically-generated switch |
41 | | // statement work. |
42 | | enum { |
43 | | X86_REG_BX_SI = 500, |
44 | | X86_REG_BX_DI = 501, |
45 | | X86_REG_BP_SI = 502, |
46 | | X86_REG_BP_DI = 503, |
47 | | X86_REG_sib = 504, |
48 | | X86_REG_sib64 = 505 |
49 | | }; |
50 | | |
51 | | static const x86_reg sib_index_map[] = { |
52 | | X86_REG_INVALID, |
53 | | #define ENTRY(x) X86_REG_##x, |
54 | | ALL_EA_BASES |
55 | | REGS_XMM |
56 | | REGS_YMM |
57 | | REGS_ZMM |
58 | | #undef ENTRY |
59 | | }; |
60 | | |
61 | | static const x86_reg segment_map[] = { |
62 | | X86_REG_INVALID, |
63 | | X86_REG_CS, |
64 | | X86_REG_SS, |
65 | | X86_REG_DS, |
66 | | X86_REG_ES, |
67 | | X86_REG_FS, |
68 | | X86_REG_GS, |
69 | | }; |
70 | | |
71 | | x86_reg x86_map_sib_base(int r) |
72 | 2.02M | { |
73 | 2.02M | return sib_base_map[r]; |
74 | 2.02M | } |
75 | | |
76 | | x86_reg x86_map_sib_index(int r) |
77 | 2.02M | { |
78 | 2.02M | return sib_index_map[r]; |
79 | 2.02M | } |
80 | | |
81 | | x86_reg x86_map_segment(int r) |
82 | 0 | { |
83 | 0 | return segment_map[r]; |
84 | 0 | } |
85 | | |
86 | | #ifndef CAPSTONE_DIET |
87 | | static const name_map reg_name_maps[] = { |
88 | | { X86_REG_INVALID, NULL }, |
89 | | |
90 | | { X86_REG_AH, "ah" }, |
91 | | { X86_REG_AL, "al" }, |
92 | | { X86_REG_AX, "ax" }, |
93 | | { X86_REG_BH, "bh" }, |
94 | | { X86_REG_BL, "bl" }, |
95 | | { X86_REG_BP, "bp" }, |
96 | | { X86_REG_BPL, "bpl" }, |
97 | | { X86_REG_BX, "bx" }, |
98 | | { X86_REG_CH, "ch" }, |
99 | | { X86_REG_CL, "cl" }, |
100 | | { X86_REG_CS, "cs" }, |
101 | | { X86_REG_CX, "cx" }, |
102 | | { X86_REG_DH, "dh" }, |
103 | | { X86_REG_DI, "di" }, |
104 | | { X86_REG_DIL, "dil" }, |
105 | | { X86_REG_DL, "dl" }, |
106 | | { X86_REG_DS, "ds" }, |
107 | | { X86_REG_DX, "dx" }, |
108 | | { X86_REG_EAX, "eax" }, |
109 | | { X86_REG_EBP, "ebp" }, |
110 | | { X86_REG_EBX, "ebx" }, |
111 | | { X86_REG_ECX, "ecx" }, |
112 | | { X86_REG_EDI, "edi" }, |
113 | | { X86_REG_EDX, "edx" }, |
114 | | { X86_REG_EFLAGS, "flags" }, |
115 | | { X86_REG_EIP, "eip" }, |
116 | | { X86_REG_EIZ, "eiz" }, |
117 | | { X86_REG_ES, "es" }, |
118 | | { X86_REG_ESI, "esi" }, |
119 | | { X86_REG_ESP, "esp" }, |
120 | | { X86_REG_FPSW, "fpsw" }, |
121 | | { X86_REG_FS, "fs" }, |
122 | | { X86_REG_GS, "gs" }, |
123 | | { X86_REG_IP, "ip" }, |
124 | | { X86_REG_RAX, "rax" }, |
125 | | { X86_REG_RBP, "rbp" }, |
126 | | { X86_REG_RBX, "rbx" }, |
127 | | { X86_REG_RCX, "rcx" }, |
128 | | { X86_REG_RDI, "rdi" }, |
129 | | { X86_REG_RDX, "rdx" }, |
130 | | { X86_REG_RIP, "rip" }, |
131 | | { X86_REG_RIZ, "riz" }, |
132 | | { X86_REG_RSI, "rsi" }, |
133 | | { X86_REG_RSP, "rsp" }, |
134 | | { X86_REG_SI, "si" }, |
135 | | { X86_REG_SIL, "sil" }, |
136 | | { X86_REG_SP, "sp" }, |
137 | | { X86_REG_SPL, "spl" }, |
138 | | { X86_REG_SS, "ss" }, |
139 | | { X86_REG_CR0, "cr0" }, |
140 | | { X86_REG_CR1, "cr1" }, |
141 | | { X86_REG_CR2, "cr2" }, |
142 | | { X86_REG_CR3, "cr3" }, |
143 | | { X86_REG_CR4, "cr4" }, |
144 | | { X86_REG_CR5, "cr5" }, |
145 | | { X86_REG_CR6, "cr6" }, |
146 | | { X86_REG_CR7, "cr7" }, |
147 | | { X86_REG_CR8, "cr8" }, |
148 | | { X86_REG_CR9, "cr9" }, |
149 | | { X86_REG_CR10, "cr10" }, |
150 | | { X86_REG_CR11, "cr11" }, |
151 | | { X86_REG_CR12, "cr12" }, |
152 | | { X86_REG_CR13, "cr13" }, |
153 | | { X86_REG_CR14, "cr14" }, |
154 | | { X86_REG_CR15, "cr15" }, |
155 | | { X86_REG_DR0, "dr0" }, |
156 | | { X86_REG_DR1, "dr1" }, |
157 | | { X86_REG_DR2, "dr2" }, |
158 | | { X86_REG_DR3, "dr3" }, |
159 | | { X86_REG_DR4, "dr4" }, |
160 | | { X86_REG_DR5, "dr5" }, |
161 | | { X86_REG_DR6, "dr6" }, |
162 | | { X86_REG_DR7, "dr7" }, |
163 | | { X86_REG_DR8, "dr8" }, |
164 | | { X86_REG_DR9, "dr9" }, |
165 | | { X86_REG_DR10, "dr10" }, |
166 | | { X86_REG_DR11, "dr11" }, |
167 | | { X86_REG_DR12, "dr12" }, |
168 | | { X86_REG_DR13, "dr13" }, |
169 | | { X86_REG_DR14, "dr14" }, |
170 | | { X86_REG_DR15, "dr15" }, |
171 | | { X86_REG_FP0, "fp0" }, |
172 | | { X86_REG_FP1, "fp1" }, |
173 | | { X86_REG_FP2, "fp2" }, |
174 | | { X86_REG_FP3, "fp3" }, |
175 | | { X86_REG_FP4, "fp4" }, |
176 | | { X86_REG_FP5, "fp5" }, |
177 | | { X86_REG_FP6, "fp6" }, |
178 | | { X86_REG_FP7, "fp7" }, |
179 | | { X86_REG_K0, "k0" }, |
180 | | { X86_REG_K1, "k1" }, |
181 | | { X86_REG_K2, "k2" }, |
182 | | { X86_REG_K3, "k3" }, |
183 | | { X86_REG_K4, "k4" }, |
184 | | { X86_REG_K5, "k5" }, |
185 | | { X86_REG_K6, "k6" }, |
186 | | { X86_REG_K7, "k7" }, |
187 | | { X86_REG_MM0, "mm0" }, |
188 | | { X86_REG_MM1, "mm1" }, |
189 | | { X86_REG_MM2, "mm2" }, |
190 | | { X86_REG_MM3, "mm3" }, |
191 | | { X86_REG_MM4, "mm4" }, |
192 | | { X86_REG_MM5, "mm5" }, |
193 | | { X86_REG_MM6, "mm6" }, |
194 | | { X86_REG_MM7, "mm7" }, |
195 | | { X86_REG_R8, "r8" }, |
196 | | { X86_REG_R9, "r9" }, |
197 | | { X86_REG_R10, "r10" }, |
198 | | { X86_REG_R11, "r11" }, |
199 | | { X86_REG_R12, "r12" }, |
200 | | { X86_REG_R13, "r13" }, |
201 | | { X86_REG_R14, "r14" }, |
202 | | { X86_REG_R15, "r15" }, |
203 | | { X86_REG_ST0, "st(0)" }, |
204 | | { X86_REG_ST1, "st(1)" }, |
205 | | { X86_REG_ST2, "st(2)" }, |
206 | | { X86_REG_ST3, "st(3)" }, |
207 | | { X86_REG_ST4, "st(4)" }, |
208 | | { X86_REG_ST5, "st(5)" }, |
209 | | { X86_REG_ST6, "st(6)" }, |
210 | | { X86_REG_ST7, "st(7)" }, |
211 | | { X86_REG_XMM0, "xmm0" }, |
212 | | { X86_REG_XMM1, "xmm1" }, |
213 | | { X86_REG_XMM2, "xmm2" }, |
214 | | { X86_REG_XMM3, "xmm3" }, |
215 | | { X86_REG_XMM4, "xmm4" }, |
216 | | { X86_REG_XMM5, "xmm5" }, |
217 | | { X86_REG_XMM6, "xmm6" }, |
218 | | { X86_REG_XMM7, "xmm7" }, |
219 | | { X86_REG_XMM8, "xmm8" }, |
220 | | { X86_REG_XMM9, "xmm9" }, |
221 | | { X86_REG_XMM10, "xmm10" }, |
222 | | { X86_REG_XMM11, "xmm11" }, |
223 | | { X86_REG_XMM12, "xmm12" }, |
224 | | { X86_REG_XMM13, "xmm13" }, |
225 | | { X86_REG_XMM14, "xmm14" }, |
226 | | { X86_REG_XMM15, "xmm15" }, |
227 | | { X86_REG_XMM16, "xmm16" }, |
228 | | { X86_REG_XMM17, "xmm17" }, |
229 | | { X86_REG_XMM18, "xmm18" }, |
230 | | { X86_REG_XMM19, "xmm19" }, |
231 | | { X86_REG_XMM20, "xmm20" }, |
232 | | { X86_REG_XMM21, "xmm21" }, |
233 | | { X86_REG_XMM22, "xmm22" }, |
234 | | { X86_REG_XMM23, "xmm23" }, |
235 | | { X86_REG_XMM24, "xmm24" }, |
236 | | { X86_REG_XMM25, "xmm25" }, |
237 | | { X86_REG_XMM26, "xmm26" }, |
238 | | { X86_REG_XMM27, "xmm27" }, |
239 | | { X86_REG_XMM28, "xmm28" }, |
240 | | { X86_REG_XMM29, "xmm29" }, |
241 | | { X86_REG_XMM30, "xmm30" }, |
242 | | { X86_REG_XMM31, "xmm31" }, |
243 | | { X86_REG_YMM0, "ymm0" }, |
244 | | { X86_REG_YMM1, "ymm1" }, |
245 | | { X86_REG_YMM2, "ymm2" }, |
246 | | { X86_REG_YMM3, "ymm3" }, |
247 | | { X86_REG_YMM4, "ymm4" }, |
248 | | { X86_REG_YMM5, "ymm5" }, |
249 | | { X86_REG_YMM6, "ymm6" }, |
250 | | { X86_REG_YMM7, "ymm7" }, |
251 | | { X86_REG_YMM8, "ymm8" }, |
252 | | { X86_REG_YMM9, "ymm9" }, |
253 | | { X86_REG_YMM10, "ymm10" }, |
254 | | { X86_REG_YMM11, "ymm11" }, |
255 | | { X86_REG_YMM12, "ymm12" }, |
256 | | { X86_REG_YMM13, "ymm13" }, |
257 | | { X86_REG_YMM14, "ymm14" }, |
258 | | { X86_REG_YMM15, "ymm15" }, |
259 | | { X86_REG_YMM16, "ymm16" }, |
260 | | { X86_REG_YMM17, "ymm17" }, |
261 | | { X86_REG_YMM18, "ymm18" }, |
262 | | { X86_REG_YMM19, "ymm19" }, |
263 | | { X86_REG_YMM20, "ymm20" }, |
264 | | { X86_REG_YMM21, "ymm21" }, |
265 | | { X86_REG_YMM22, "ymm22" }, |
266 | | { X86_REG_YMM23, "ymm23" }, |
267 | | { X86_REG_YMM24, "ymm24" }, |
268 | | { X86_REG_YMM25, "ymm25" }, |
269 | | { X86_REG_YMM26, "ymm26" }, |
270 | | { X86_REG_YMM27, "ymm27" }, |
271 | | { X86_REG_YMM28, "ymm28" }, |
272 | | { X86_REG_YMM29, "ymm29" }, |
273 | | { X86_REG_YMM30, "ymm30" }, |
274 | | { X86_REG_YMM31, "ymm31" }, |
275 | | { X86_REG_ZMM0, "zmm0" }, |
276 | | { X86_REG_ZMM1, "zmm1" }, |
277 | | { X86_REG_ZMM2, "zmm2" }, |
278 | | { X86_REG_ZMM3, "zmm3" }, |
279 | | { X86_REG_ZMM4, "zmm4" }, |
280 | | { X86_REG_ZMM5, "zmm5" }, |
281 | | { X86_REG_ZMM6, "zmm6" }, |
282 | | { X86_REG_ZMM7, "zmm7" }, |
283 | | { X86_REG_ZMM8, "zmm8" }, |
284 | | { X86_REG_ZMM9, "zmm9" }, |
285 | | { X86_REG_ZMM10, "zmm10" }, |
286 | | { X86_REG_ZMM11, "zmm11" }, |
287 | | { X86_REG_ZMM12, "zmm12" }, |
288 | | { X86_REG_ZMM13, "zmm13" }, |
289 | | { X86_REG_ZMM14, "zmm14" }, |
290 | | { X86_REG_ZMM15, "zmm15" }, |
291 | | { X86_REG_ZMM16, "zmm16" }, |
292 | | { X86_REG_ZMM17, "zmm17" }, |
293 | | { X86_REG_ZMM18, "zmm18" }, |
294 | | { X86_REG_ZMM19, "zmm19" }, |
295 | | { X86_REG_ZMM20, "zmm20" }, |
296 | | { X86_REG_ZMM21, "zmm21" }, |
297 | | { X86_REG_ZMM22, "zmm22" }, |
298 | | { X86_REG_ZMM23, "zmm23" }, |
299 | | { X86_REG_ZMM24, "zmm24" }, |
300 | | { X86_REG_ZMM25, "zmm25" }, |
301 | | { X86_REG_ZMM26, "zmm26" }, |
302 | | { X86_REG_ZMM27, "zmm27" }, |
303 | | { X86_REG_ZMM28, "zmm28" }, |
304 | | { X86_REG_ZMM29, "zmm29" }, |
305 | | { X86_REG_ZMM30, "zmm30" }, |
306 | | { X86_REG_ZMM31, "zmm31" }, |
307 | | { X86_REG_R8B, "r8b" }, |
308 | | { X86_REG_R9B, "r9b" }, |
309 | | { X86_REG_R10B, "r10b" }, |
310 | | { X86_REG_R11B, "r11b" }, |
311 | | { X86_REG_R12B, "r12b" }, |
312 | | { X86_REG_R13B, "r13b" }, |
313 | | { X86_REG_R14B, "r14b" }, |
314 | | { X86_REG_R15B, "r15b" }, |
315 | | { X86_REG_R8D, "r8d" }, |
316 | | { X86_REG_R9D, "r9d" }, |
317 | | { X86_REG_R10D, "r10d" }, |
318 | | { X86_REG_R11D, "r11d" }, |
319 | | { X86_REG_R12D, "r12d" }, |
320 | | { X86_REG_R13D, "r13d" }, |
321 | | { X86_REG_R14D, "r14d" }, |
322 | | { X86_REG_R15D, "r15d" }, |
323 | | { X86_REG_R8W, "r8w" }, |
324 | | { X86_REG_R9W, "r9w" }, |
325 | | { X86_REG_R10W, "r10w" }, |
326 | | { X86_REG_R11W, "r11w" }, |
327 | | { X86_REG_R12W, "r12w" }, |
328 | | { X86_REG_R13W, "r13w" }, |
329 | | { X86_REG_R14W, "r14w" }, |
330 | | { X86_REG_R15W, "r15w" }, |
331 | | |
332 | | { X86_REG_BND0, "bnd0" }, |
333 | | { X86_REG_BND1, "bnd1" }, |
334 | | { X86_REG_BND2, "bnd2" }, |
335 | | { X86_REG_BND3, "bnd3" }, |
336 | | }; |
337 | | #endif |
338 | | |
339 | | // register size in non-64bit mode |
340 | | const uint8_t regsize_map_32 [] = { |
341 | | 0, // { X86_REG_INVALID, NULL }, |
342 | | 1, // { X86_REG_AH, "ah" }, |
343 | | 1, // { X86_REG_AL, "al" }, |
344 | | 2, // { X86_REG_AX, "ax" }, |
345 | | 1, // { X86_REG_BH, "bh" }, |
346 | | 1, // { X86_REG_BL, "bl" }, |
347 | | 2, // { X86_REG_BP, "bp" }, |
348 | | 1, // { X86_REG_BPL, "bpl" }, |
349 | | 2, // { X86_REG_BX, "bx" }, |
350 | | 1, // { X86_REG_CH, "ch" }, |
351 | | 1, // { X86_REG_CL, "cl" }, |
352 | | 2, // { X86_REG_CS, "cs" }, |
353 | | 2, // { X86_REG_CX, "cx" }, |
354 | | 1, // { X86_REG_DH, "dh" }, |
355 | | 2, // { X86_REG_DI, "di" }, |
356 | | 1, // { X86_REG_DIL, "dil" }, |
357 | | 1, // { X86_REG_DL, "dl" }, |
358 | | 2, // { X86_REG_DS, "ds" }, |
359 | | 2, // { X86_REG_DX, "dx" }, |
360 | | 4, // { X86_REG_EAX, "eax" }, |
361 | | 4, // { X86_REG_EBP, "ebp" }, |
362 | | 4, // { X86_REG_EBX, "ebx" }, |
363 | | 4, // { X86_REG_ECX, "ecx" }, |
364 | | 4, // { X86_REG_EDI, "edi" }, |
365 | | 4, // { X86_REG_EDX, "edx" }, |
366 | | 4, // { X86_REG_EFLAGS, "flags" }, |
367 | | 4, // { X86_REG_EIP, "eip" }, |
368 | | 4, // { X86_REG_EIZ, "eiz" }, |
369 | | 2, // { X86_REG_ES, "es" }, |
370 | | 4, // { X86_REG_ESI, "esi" }, |
371 | | 4, // { X86_REG_ESP, "esp" }, |
372 | | 10, // { X86_REG_FPSW, "fpsw" }, |
373 | | 2, // { X86_REG_FS, "fs" }, |
374 | | 2, // { X86_REG_GS, "gs" }, |
375 | | 2, // { X86_REG_IP, "ip" }, |
376 | | 8, // { X86_REG_RAX, "rax" }, |
377 | | 8, // { X86_REG_RBP, "rbp" }, |
378 | | 8, // { X86_REG_RBX, "rbx" }, |
379 | | 8, // { X86_REG_RCX, "rcx" }, |
380 | | 8, // { X86_REG_RDI, "rdi" }, |
381 | | 8, // { X86_REG_RDX, "rdx" }, |
382 | | 8, // { X86_REG_RIP, "rip" }, |
383 | | 8, // { X86_REG_RIZ, "riz" }, |
384 | | 8, // { X86_REG_RSI, "rsi" }, |
385 | | 8, // { X86_REG_RSP, "rsp" }, |
386 | | 2, // { X86_REG_SI, "si" }, |
387 | | 1, // { X86_REG_SIL, "sil" }, |
388 | | 2, // { X86_REG_SP, "sp" }, |
389 | | 1, // { X86_REG_SPL, "spl" }, |
390 | | 2, // { X86_REG_SS, "ss" }, |
391 | | 4, // { X86_REG_CR0, "cr0" }, |
392 | | 4, // { X86_REG_CR1, "cr1" }, |
393 | | 4, // { X86_REG_CR2, "cr2" }, |
394 | | 4, // { X86_REG_CR3, "cr3" }, |
395 | | 4, // { X86_REG_CR4, "cr4" }, |
396 | | 8, // { X86_REG_CR5, "cr5" }, |
397 | | 8, // { X86_REG_CR6, "cr6" }, |
398 | | 8, // { X86_REG_CR7, "cr7" }, |
399 | | 8, // { X86_REG_CR8, "cr8" }, |
400 | | 8, // { X86_REG_CR9, "cr9" }, |
401 | | 8, // { X86_REG_CR10, "cr10" }, |
402 | | 8, // { X86_REG_CR11, "cr11" }, |
403 | | 8, // { X86_REG_CR12, "cr12" }, |
404 | | 8, // { X86_REG_CR13, "cr13" }, |
405 | | 8, // { X86_REG_CR14, "cr14" }, |
406 | | 8, // { X86_REG_CR15, "cr15" }, |
407 | | 4, // { X86_REG_DR0, "dr0" }, |
408 | | 4, // { X86_REG_DR1, "dr1" }, |
409 | | 4, // { X86_REG_DR2, "dr2" }, |
410 | | 4, // { X86_REG_DR3, "dr3" }, |
411 | | 4, // { X86_REG_DR4, "dr4" }, |
412 | | 4, // { X86_REG_DR5, "dr5" }, |
413 | | 4, // { X86_REG_DR6, "dr6" }, |
414 | | 4, // { X86_REG_DR7, "dr7" }, |
415 | | 4, // { X86_REG_DR8, "dr8" }, |
416 | | 4, // { X86_REG_DR9, "dr9" }, |
417 | | 4, // { X86_REG_DR10, "dr10" }, |
418 | | 4, // { X86_REG_DR11, "dr11" }, |
419 | | 4, // { X86_REG_DR12, "dr12" }, |
420 | | 4, // { X86_REG_DR13, "dr13" }, |
421 | | 4, // { X86_REG_DR14, "dr14" }, |
422 | | 4, // { X86_REG_DR15, "dr15" }, |
423 | | 10, // { X86_REG_FP0, "fp0" }, |
424 | | 10, // { X86_REG_FP1, "fp1" }, |
425 | | 10, // { X86_REG_FP2, "fp2" }, |
426 | | 10, // { X86_REG_FP3, "fp3" }, |
427 | | 10, // { X86_REG_FP4, "fp4" }, |
428 | | 10, // { X86_REG_FP5, "fp5" }, |
429 | | 10, // { X86_REG_FP6, "fp6" }, |
430 | | 10, // { X86_REG_FP7, "fp7" }, |
431 | | 2, // { X86_REG_K0, "k0" }, |
432 | | 2, // { X86_REG_K1, "k1" }, |
433 | | 2, // { X86_REG_K2, "k2" }, |
434 | | 2, // { X86_REG_K3, "k3" }, |
435 | | 2, // { X86_REG_K4, "k4" }, |
436 | | 2, // { X86_REG_K5, "k5" }, |
437 | | 2, // { X86_REG_K6, "k6" }, |
438 | | 2, // { X86_REG_K7, "k7" }, |
439 | | 8, // { X86_REG_MM0, "mm0" }, |
440 | | 8, // { X86_REG_MM1, "mm1" }, |
441 | | 8, // { X86_REG_MM2, "mm2" }, |
442 | | 8, // { X86_REG_MM3, "mm3" }, |
443 | | 8, // { X86_REG_MM4, "mm4" }, |
444 | | 8, // { X86_REG_MM5, "mm5" }, |
445 | | 8, // { X86_REG_MM6, "mm6" }, |
446 | | 8, // { X86_REG_MM7, "mm7" }, |
447 | | 8, // { X86_REG_R8, "r8" }, |
448 | | 8, // { X86_REG_R9, "r9" }, |
449 | | 8, // { X86_REG_R10, "r10" }, |
450 | | 8, // { X86_REG_R11, "r11" }, |
451 | | 8, // { X86_REG_R12, "r12" }, |
452 | | 8, // { X86_REG_R13, "r13" }, |
453 | | 8, // { X86_REG_R14, "r14" }, |
454 | | 8, // { X86_REG_R15, "r15" }, |
455 | | 10, // { X86_REG_ST0, "st0" }, |
456 | | 10, // { X86_REG_ST1, "st1" }, |
457 | | 10, // { X86_REG_ST2, "st2" }, |
458 | | 10, // { X86_REG_ST3, "st3" }, |
459 | | 10, // { X86_REG_ST4, "st4" }, |
460 | | 10, // { X86_REG_ST5, "st5" }, |
461 | | 10, // { X86_REG_ST6, "st6" }, |
462 | | 10, // { X86_REG_ST7, "st7" }, |
463 | | 16, // { X86_REG_XMM0, "xmm0" }, |
464 | | 16, // { X86_REG_XMM1, "xmm1" }, |
465 | | 16, // { X86_REG_XMM2, "xmm2" }, |
466 | | 16, // { X86_REG_XMM3, "xmm3" }, |
467 | | 16, // { X86_REG_XMM4, "xmm4" }, |
468 | | 16, // { X86_REG_XMM5, "xmm5" }, |
469 | | 16, // { X86_REG_XMM6, "xmm6" }, |
470 | | 16, // { X86_REG_XMM7, "xmm7" }, |
471 | | 16, // { X86_REG_XMM8, "xmm8" }, |
472 | | 16, // { X86_REG_XMM9, "xmm9" }, |
473 | | 16, // { X86_REG_XMM10, "xmm10" }, |
474 | | 16, // { X86_REG_XMM11, "xmm11" }, |
475 | | 16, // { X86_REG_XMM12, "xmm12" }, |
476 | | 16, // { X86_REG_XMM13, "xmm13" }, |
477 | | 16, // { X86_REG_XMM14, "xmm14" }, |
478 | | 16, // { X86_REG_XMM15, "xmm15" }, |
479 | | 16, // { X86_REG_XMM16, "xmm16" }, |
480 | | 16, // { X86_REG_XMM17, "xmm17" }, |
481 | | 16, // { X86_REG_XMM18, "xmm18" }, |
482 | | 16, // { X86_REG_XMM19, "xmm19" }, |
483 | | 16, // { X86_REG_XMM20, "xmm20" }, |
484 | | 16, // { X86_REG_XMM21, "xmm21" }, |
485 | | 16, // { X86_REG_XMM22, "xmm22" }, |
486 | | 16, // { X86_REG_XMM23, "xmm23" }, |
487 | | 16, // { X86_REG_XMM24, "xmm24" }, |
488 | | 16, // { X86_REG_XMM25, "xmm25" }, |
489 | | 16, // { X86_REG_XMM26, "xmm26" }, |
490 | | 16, // { X86_REG_XMM27, "xmm27" }, |
491 | | 16, // { X86_REG_XMM28, "xmm28" }, |
492 | | 16, // { X86_REG_XMM29, "xmm29" }, |
493 | | 16, // { X86_REG_XMM30, "xmm30" }, |
494 | | 16, // { X86_REG_XMM31, "xmm31" }, |
495 | | 32, // { X86_REG_YMM0, "ymm0" }, |
496 | | 32, // { X86_REG_YMM1, "ymm1" }, |
497 | | 32, // { X86_REG_YMM2, "ymm2" }, |
498 | | 32, // { X86_REG_YMM3, "ymm3" }, |
499 | | 32, // { X86_REG_YMM4, "ymm4" }, |
500 | | 32, // { X86_REG_YMM5, "ymm5" }, |
501 | | 32, // { X86_REG_YMM6, "ymm6" }, |
502 | | 32, // { X86_REG_YMM7, "ymm7" }, |
503 | | 32, // { X86_REG_YMM8, "ymm8" }, |
504 | | 32, // { X86_REG_YMM9, "ymm9" }, |
505 | | 32, // { X86_REG_YMM10, "ymm10" }, |
506 | | 32, // { X86_REG_YMM11, "ymm11" }, |
507 | | 32, // { X86_REG_YMM12, "ymm12" }, |
508 | | 32, // { X86_REG_YMM13, "ymm13" }, |
509 | | 32, // { X86_REG_YMM14, "ymm14" }, |
510 | | 32, // { X86_REG_YMM15, "ymm15" }, |
511 | | 32, // { X86_REG_YMM16, "ymm16" }, |
512 | | 32, // { X86_REG_YMM17, "ymm17" }, |
513 | | 32, // { X86_REG_YMM18, "ymm18" }, |
514 | | 32, // { X86_REG_YMM19, "ymm19" }, |
515 | | 32, // { X86_REG_YMM20, "ymm20" }, |
516 | | 32, // { X86_REG_YMM21, "ymm21" }, |
517 | | 32, // { X86_REG_YMM22, "ymm22" }, |
518 | | 32, // { X86_REG_YMM23, "ymm23" }, |
519 | | 32, // { X86_REG_YMM24, "ymm24" }, |
520 | | 32, // { X86_REG_YMM25, "ymm25" }, |
521 | | 32, // { X86_REG_YMM26, "ymm26" }, |
522 | | 32, // { X86_REG_YMM27, "ymm27" }, |
523 | | 32, // { X86_REG_YMM28, "ymm28" }, |
524 | | 32, // { X86_REG_YMM29, "ymm29" }, |
525 | | 32, // { X86_REG_YMM30, "ymm30" }, |
526 | | 32, // { X86_REG_YMM31, "ymm31" }, |
527 | | 64, // { X86_REG_ZMM0, "zmm0" }, |
528 | | 64, // { X86_REG_ZMM1, "zmm1" }, |
529 | | 64, // { X86_REG_ZMM2, "zmm2" }, |
530 | | 64, // { X86_REG_ZMM3, "zmm3" }, |
531 | | 64, // { X86_REG_ZMM4, "zmm4" }, |
532 | | 64, // { X86_REG_ZMM5, "zmm5" }, |
533 | | 64, // { X86_REG_ZMM6, "zmm6" }, |
534 | | 64, // { X86_REG_ZMM7, "zmm7" }, |
535 | | 64, // { X86_REG_ZMM8, "zmm8" }, |
536 | | 64, // { X86_REG_ZMM9, "zmm9" }, |
537 | | 64, // { X86_REG_ZMM10, "zmm10" }, |
538 | | 64, // { X86_REG_ZMM11, "zmm11" }, |
539 | | 64, // { X86_REG_ZMM12, "zmm12" }, |
540 | | 64, // { X86_REG_ZMM13, "zmm13" }, |
541 | | 64, // { X86_REG_ZMM14, "zmm14" }, |
542 | | 64, // { X86_REG_ZMM15, "zmm15" }, |
543 | | 64, // { X86_REG_ZMM16, "zmm16" }, |
544 | | 64, // { X86_REG_ZMM17, "zmm17" }, |
545 | | 64, // { X86_REG_ZMM18, "zmm18" }, |
546 | | 64, // { X86_REG_ZMM19, "zmm19" }, |
547 | | 64, // { X86_REG_ZMM20, "zmm20" }, |
548 | | 64, // { X86_REG_ZMM21, "zmm21" }, |
549 | | 64, // { X86_REG_ZMM22, "zmm22" }, |
550 | | 64, // { X86_REG_ZMM23, "zmm23" }, |
551 | | 64, // { X86_REG_ZMM24, "zmm24" }, |
552 | | 64, // { X86_REG_ZMM25, "zmm25" }, |
553 | | 64, // { X86_REG_ZMM26, "zmm26" }, |
554 | | 64, // { X86_REG_ZMM27, "zmm27" }, |
555 | | 64, // { X86_REG_ZMM28, "zmm28" }, |
556 | | 64, // { X86_REG_ZMM29, "zmm29" }, |
557 | | 64, // { X86_REG_ZMM30, "zmm30" }, |
558 | | 64, // { X86_REG_ZMM31, "zmm31" }, |
559 | | 1, // { X86_REG_R8B, "r8b" }, |
560 | | 1, // { X86_REG_R9B, "r9b" }, |
561 | | 1, // { X86_REG_R10B, "r10b" }, |
562 | | 1, // { X86_REG_R11B, "r11b" }, |
563 | | 1, // { X86_REG_R12B, "r12b" }, |
564 | | 1, // { X86_REG_R13B, "r13b" }, |
565 | | 1, // { X86_REG_R14B, "r14b" }, |
566 | | 1, // { X86_REG_R15B, "r15b" }, |
567 | | 4, // { X86_REG_R8D, "r8d" }, |
568 | | 4, // { X86_REG_R9D, "r9d" }, |
569 | | 4, // { X86_REG_R10D, "r10d" }, |
570 | | 4, // { X86_REG_R11D, "r11d" }, |
571 | | 4, // { X86_REG_R12D, "r12d" }, |
572 | | 4, // { X86_REG_R13D, "r13d" }, |
573 | | 4, // { X86_REG_R14D, "r14d" }, |
574 | | 4, // { X86_REG_R15D, "r15d" }, |
575 | | 2, // { X86_REG_R8W, "r8w" }, |
576 | | 2, // { X86_REG_R9W, "r9w" }, |
577 | | 2, // { X86_REG_R10W, "r10w" }, |
578 | | 2, // { X86_REG_R11W, "r11w" }, |
579 | | 2, // { X86_REG_R12W, "r12w" }, |
580 | | 2, // { X86_REG_R13W, "r13w" }, |
581 | | 2, // { X86_REG_R14W, "r14w" }, |
582 | | 2, // { X86_REG_R15W, "r15w" }, |
583 | | 16, // { X86_REG_BND0, "bnd0" }, |
584 | | 16, // { X86_REG_BND1, "bnd0" }, |
585 | | 16, // { X86_REG_BND2, "bnd0" }, |
586 | | 16, // { X86_REG_BND3, "bnd0" }, |
587 | | }; |
588 | | |
589 | | // register size in 64bit mode |
590 | | const uint8_t regsize_map_64 [] = { |
591 | | 0, // { X86_REG_INVALID, NULL }, |
592 | | 1, // { X86_REG_AH, "ah" }, |
593 | | 1, // { X86_REG_AL, "al" }, |
594 | | 2, // { X86_REG_AX, "ax" }, |
595 | | 1, // { X86_REG_BH, "bh" }, |
596 | | 1, // { X86_REG_BL, "bl" }, |
597 | | 2, // { X86_REG_BP, "bp" }, |
598 | | 1, // { X86_REG_BPL, "bpl" }, |
599 | | 2, // { X86_REG_BX, "bx" }, |
600 | | 1, // { X86_REG_CH, "ch" }, |
601 | | 1, // { X86_REG_CL, "cl" }, |
602 | | 2, // { X86_REG_CS, "cs" }, |
603 | | 2, // { X86_REG_CX, "cx" }, |
604 | | 1, // { X86_REG_DH, "dh" }, |
605 | | 2, // { X86_REG_DI, "di" }, |
606 | | 1, // { X86_REG_DIL, "dil" }, |
607 | | 1, // { X86_REG_DL, "dl" }, |
608 | | 2, // { X86_REG_DS, "ds" }, |
609 | | 2, // { X86_REG_DX, "dx" }, |
610 | | 4, // { X86_REG_EAX, "eax" }, |
611 | | 4, // { X86_REG_EBP, "ebp" }, |
612 | | 4, // { X86_REG_EBX, "ebx" }, |
613 | | 4, // { X86_REG_ECX, "ecx" }, |
614 | | 4, // { X86_REG_EDI, "edi" }, |
615 | | 4, // { X86_REG_EDX, "edx" }, |
616 | | 8, // { X86_REG_EFLAGS, "flags" }, |
617 | | 4, // { X86_REG_EIP, "eip" }, |
618 | | 4, // { X86_REG_EIZ, "eiz" }, |
619 | | 2, // { X86_REG_ES, "es" }, |
620 | | 4, // { X86_REG_ESI, "esi" }, |
621 | | 4, // { X86_REG_ESP, "esp" }, |
622 | | 10, // { X86_REG_FPSW, "fpsw" }, |
623 | | 2, // { X86_REG_FS, "fs" }, |
624 | | 2, // { X86_REG_GS, "gs" }, |
625 | | 2, // { X86_REG_IP, "ip" }, |
626 | | 8, // { X86_REG_RAX, "rax" }, |
627 | | 8, // { X86_REG_RBP, "rbp" }, |
628 | | 8, // { X86_REG_RBX, "rbx" }, |
629 | | 8, // { X86_REG_RCX, "rcx" }, |
630 | | 8, // { X86_REG_RDI, "rdi" }, |
631 | | 8, // { X86_REG_RDX, "rdx" }, |
632 | | 8, // { X86_REG_RIP, "rip" }, |
633 | | 8, // { X86_REG_RIZ, "riz" }, |
634 | | 8, // { X86_REG_RSI, "rsi" }, |
635 | | 8, // { X86_REG_RSP, "rsp" }, |
636 | | 2, // { X86_REG_SI, "si" }, |
637 | | 1, // { X86_REG_SIL, "sil" }, |
638 | | 2, // { X86_REG_SP, "sp" }, |
639 | | 1, // { X86_REG_SPL, "spl" }, |
640 | | 2, // { X86_REG_SS, "ss" }, |
641 | | 8, // { X86_REG_CR0, "cr0" }, |
642 | | 8, // { X86_REG_CR1, "cr1" }, |
643 | | 8, // { X86_REG_CR2, "cr2" }, |
644 | | 8, // { X86_REG_CR3, "cr3" }, |
645 | | 8, // { X86_REG_CR4, "cr4" }, |
646 | | 8, // { X86_REG_CR5, "cr5" }, |
647 | | 8, // { X86_REG_CR6, "cr6" }, |
648 | | 8, // { X86_REG_CR7, "cr7" }, |
649 | | 8, // { X86_REG_CR8, "cr8" }, |
650 | | 8, // { X86_REG_CR9, "cr9" }, |
651 | | 8, // { X86_REG_CR10, "cr10" }, |
652 | | 8, // { X86_REG_CR11, "cr11" }, |
653 | | 8, // { X86_REG_CR12, "cr12" }, |
654 | | 8, // { X86_REG_CR13, "cr13" }, |
655 | | 8, // { X86_REG_CR14, "cr14" }, |
656 | | 8, // { X86_REG_CR15, "cr15" }, |
657 | | 8, // { X86_REG_DR0, "dr0" }, |
658 | | 8, // { X86_REG_DR1, "dr1" }, |
659 | | 8, // { X86_REG_DR2, "dr2" }, |
660 | | 8, // { X86_REG_DR3, "dr3" }, |
661 | | 8, // { X86_REG_DR4, "dr4" }, |
662 | | 8, // { X86_REG_DR5, "dr5" }, |
663 | | 8, // { X86_REG_DR6, "dr6" }, |
664 | | 8, // { X86_REG_DR7, "dr7" }, |
665 | | 8, // { X86_REG_DR8, "dr8" }, |
666 | | 8, // { X86_REG_DR9, "dr9" }, |
667 | | 8, // { X86_REG_DR10, "dr10" }, |
668 | | 8, // { X86_REG_DR11, "dr11" }, |
669 | | 8, // { X86_REG_DR12, "dr12" }, |
670 | | 8, // { X86_REG_DR13, "dr13" }, |
671 | | 8, // { X86_REG_DR14, "dr14" }, |
672 | | 8, // { X86_REG_DR15, "dr15" }, |
673 | | 10, // { X86_REG_FP0, "fp0" }, |
674 | | 10, // { X86_REG_FP1, "fp1" }, |
675 | | 10, // { X86_REG_FP2, "fp2" }, |
676 | | 10, // { X86_REG_FP3, "fp3" }, |
677 | | 10, // { X86_REG_FP4, "fp4" }, |
678 | | 10, // { X86_REG_FP5, "fp5" }, |
679 | | 10, // { X86_REG_FP6, "fp6" }, |
680 | | 10, // { X86_REG_FP7, "fp7" }, |
681 | | 2, // { X86_REG_K0, "k0" }, |
682 | | 2, // { X86_REG_K1, "k1" }, |
683 | | 2, // { X86_REG_K2, "k2" }, |
684 | | 2, // { X86_REG_K3, "k3" }, |
685 | | 2, // { X86_REG_K4, "k4" }, |
686 | | 2, // { X86_REG_K5, "k5" }, |
687 | | 2, // { X86_REG_K6, "k6" }, |
688 | | 2, // { X86_REG_K7, "k7" }, |
689 | | 8, // { X86_REG_MM0, "mm0" }, |
690 | | 8, // { X86_REG_MM1, "mm1" }, |
691 | | 8, // { X86_REG_MM2, "mm2" }, |
692 | | 8, // { X86_REG_MM3, "mm3" }, |
693 | | 8, // { X86_REG_MM4, "mm4" }, |
694 | | 8, // { X86_REG_MM5, "mm5" }, |
695 | | 8, // { X86_REG_MM6, "mm6" }, |
696 | | 8, // { X86_REG_MM7, "mm7" }, |
697 | | 8, // { X86_REG_R8, "r8" }, |
698 | | 8, // { X86_REG_R9, "r9" }, |
699 | | 8, // { X86_REG_R10, "r10" }, |
700 | | 8, // { X86_REG_R11, "r11" }, |
701 | | 8, // { X86_REG_R12, "r12" }, |
702 | | 8, // { X86_REG_R13, "r13" }, |
703 | | 8, // { X86_REG_R14, "r14" }, |
704 | | 8, // { X86_REG_R15, "r15" }, |
705 | | 10, // { X86_REG_ST0, "st0" }, |
706 | | 10, // { X86_REG_ST1, "st1" }, |
707 | | 10, // { X86_REG_ST2, "st2" }, |
708 | | 10, // { X86_REG_ST3, "st3" }, |
709 | | 10, // { X86_REG_ST4, "st4" }, |
710 | | 10, // { X86_REG_ST5, "st5" }, |
711 | | 10, // { X86_REG_ST6, "st6" }, |
712 | | 10, // { X86_REG_ST7, "st7" }, |
713 | | 16, // { X86_REG_XMM0, "xmm0" }, |
714 | | 16, // { X86_REG_XMM1, "xmm1" }, |
715 | | 16, // { X86_REG_XMM2, "xmm2" }, |
716 | | 16, // { X86_REG_XMM3, "xmm3" }, |
717 | | 16, // { X86_REG_XMM4, "xmm4" }, |
718 | | 16, // { X86_REG_XMM5, "xmm5" }, |
719 | | 16, // { X86_REG_XMM6, "xmm6" }, |
720 | | 16, // { X86_REG_XMM7, "xmm7" }, |
721 | | 16, // { X86_REG_XMM8, "xmm8" }, |
722 | | 16, // { X86_REG_XMM9, "xmm9" }, |
723 | | 16, // { X86_REG_XMM10, "xmm10" }, |
724 | | 16, // { X86_REG_XMM11, "xmm11" }, |
725 | | 16, // { X86_REG_XMM12, "xmm12" }, |
726 | | 16, // { X86_REG_XMM13, "xmm13" }, |
727 | | 16, // { X86_REG_XMM14, "xmm14" }, |
728 | | 16, // { X86_REG_XMM15, "xmm15" }, |
729 | | 16, // { X86_REG_XMM16, "xmm16" }, |
730 | | 16, // { X86_REG_XMM17, "xmm17" }, |
731 | | 16, // { X86_REG_XMM18, "xmm18" }, |
732 | | 16, // { X86_REG_XMM19, "xmm19" }, |
733 | | 16, // { X86_REG_XMM20, "xmm20" }, |
734 | | 16, // { X86_REG_XMM21, "xmm21" }, |
735 | | 16, // { X86_REG_XMM22, "xmm22" }, |
736 | | 16, // { X86_REG_XMM23, "xmm23" }, |
737 | | 16, // { X86_REG_XMM24, "xmm24" }, |
738 | | 16, // { X86_REG_XMM25, "xmm25" }, |
739 | | 16, // { X86_REG_XMM26, "xmm26" }, |
740 | | 16, // { X86_REG_XMM27, "xmm27" }, |
741 | | 16, // { X86_REG_XMM28, "xmm28" }, |
742 | | 16, // { X86_REG_XMM29, "xmm29" }, |
743 | | 16, // { X86_REG_XMM30, "xmm30" }, |
744 | | 16, // { X86_REG_XMM31, "xmm31" }, |
745 | | 32, // { X86_REG_YMM0, "ymm0" }, |
746 | | 32, // { X86_REG_YMM1, "ymm1" }, |
747 | | 32, // { X86_REG_YMM2, "ymm2" }, |
748 | | 32, // { X86_REG_YMM3, "ymm3" }, |
749 | | 32, // { X86_REG_YMM4, "ymm4" }, |
750 | | 32, // { X86_REG_YMM5, "ymm5" }, |
751 | | 32, // { X86_REG_YMM6, "ymm6" }, |
752 | | 32, // { X86_REG_YMM7, "ymm7" }, |
753 | | 32, // { X86_REG_YMM8, "ymm8" }, |
754 | | 32, // { X86_REG_YMM9, "ymm9" }, |
755 | | 32, // { X86_REG_YMM10, "ymm10" }, |
756 | | 32, // { X86_REG_YMM11, "ymm11" }, |
757 | | 32, // { X86_REG_YMM12, "ymm12" }, |
758 | | 32, // { X86_REG_YMM13, "ymm13" }, |
759 | | 32, // { X86_REG_YMM14, "ymm14" }, |
760 | | 32, // { X86_REG_YMM15, "ymm15" }, |
761 | | 32, // { X86_REG_YMM16, "ymm16" }, |
762 | | 32, // { X86_REG_YMM17, "ymm17" }, |
763 | | 32, // { X86_REG_YMM18, "ymm18" }, |
764 | | 32, // { X86_REG_YMM19, "ymm19" }, |
765 | | 32, // { X86_REG_YMM20, "ymm20" }, |
766 | | 32, // { X86_REG_YMM21, "ymm21" }, |
767 | | 32, // { X86_REG_YMM22, "ymm22" }, |
768 | | 32, // { X86_REG_YMM23, "ymm23" }, |
769 | | 32, // { X86_REG_YMM24, "ymm24" }, |
770 | | 32, // { X86_REG_YMM25, "ymm25" }, |
771 | | 32, // { X86_REG_YMM26, "ymm26" }, |
772 | | 32, // { X86_REG_YMM27, "ymm27" }, |
773 | | 32, // { X86_REG_YMM28, "ymm28" }, |
774 | | 32, // { X86_REG_YMM29, "ymm29" }, |
775 | | 32, // { X86_REG_YMM30, "ymm30" }, |
776 | | 32, // { X86_REG_YMM31, "ymm31" }, |
777 | | 64, // { X86_REG_ZMM0, "zmm0" }, |
778 | | 64, // { X86_REG_ZMM1, "zmm1" }, |
779 | | 64, // { X86_REG_ZMM2, "zmm2" }, |
780 | | 64, // { X86_REG_ZMM3, "zmm3" }, |
781 | | 64, // { X86_REG_ZMM4, "zmm4" }, |
782 | | 64, // { X86_REG_ZMM5, "zmm5" }, |
783 | | 64, // { X86_REG_ZMM6, "zmm6" }, |
784 | | 64, // { X86_REG_ZMM7, "zmm7" }, |
785 | | 64, // { X86_REG_ZMM8, "zmm8" }, |
786 | | 64, // { X86_REG_ZMM9, "zmm9" }, |
787 | | 64, // { X86_REG_ZMM10, "zmm10" }, |
788 | | 64, // { X86_REG_ZMM11, "zmm11" }, |
789 | | 64, // { X86_REG_ZMM12, "zmm12" }, |
790 | | 64, // { X86_REG_ZMM13, "zmm13" }, |
791 | | 64, // { X86_REG_ZMM14, "zmm14" }, |
792 | | 64, // { X86_REG_ZMM15, "zmm15" }, |
793 | | 64, // { X86_REG_ZMM16, "zmm16" }, |
794 | | 64, // { X86_REG_ZMM17, "zmm17" }, |
795 | | 64, // { X86_REG_ZMM18, "zmm18" }, |
796 | | 64, // { X86_REG_ZMM19, "zmm19" }, |
797 | | 64, // { X86_REG_ZMM20, "zmm20" }, |
798 | | 64, // { X86_REG_ZMM21, "zmm21" }, |
799 | | 64, // { X86_REG_ZMM22, "zmm22" }, |
800 | | 64, // { X86_REG_ZMM23, "zmm23" }, |
801 | | 64, // { X86_REG_ZMM24, "zmm24" }, |
802 | | 64, // { X86_REG_ZMM25, "zmm25" }, |
803 | | 64, // { X86_REG_ZMM26, "zmm26" }, |
804 | | 64, // { X86_REG_ZMM27, "zmm27" }, |
805 | | 64, // { X86_REG_ZMM28, "zmm28" }, |
806 | | 64, // { X86_REG_ZMM29, "zmm29" }, |
807 | | 64, // { X86_REG_ZMM30, "zmm30" }, |
808 | | 64, // { X86_REG_ZMM31, "zmm31" }, |
809 | | 1, // { X86_REG_R8B, "r8b" }, |
810 | | 1, // { X86_REG_R9B, "r9b" }, |
811 | | 1, // { X86_REG_R10B, "r10b" }, |
812 | | 1, // { X86_REG_R11B, "r11b" }, |
813 | | 1, // { X86_REG_R12B, "r12b" }, |
814 | | 1, // { X86_REG_R13B, "r13b" }, |
815 | | 1, // { X86_REG_R14B, "r14b" }, |
816 | | 1, // { X86_REG_R15B, "r15b" }, |
817 | | 4, // { X86_REG_R8D, "r8d" }, |
818 | | 4, // { X86_REG_R9D, "r9d" }, |
819 | | 4, // { X86_REG_R10D, "r10d" }, |
820 | | 4, // { X86_REG_R11D, "r11d" }, |
821 | | 4, // { X86_REG_R12D, "r12d" }, |
822 | | 4, // { X86_REG_R13D, "r13d" }, |
823 | | 4, // { X86_REG_R14D, "r14d" }, |
824 | | 4, // { X86_REG_R15D, "r15d" }, |
825 | | 2, // { X86_REG_R8W, "r8w" }, |
826 | | 2, // { X86_REG_R9W, "r9w" }, |
827 | | 2, // { X86_REG_R10W, "r10w" }, |
828 | | 2, // { X86_REG_R11W, "r11w" }, |
829 | | 2, // { X86_REG_R12W, "r12w" }, |
830 | | 2, // { X86_REG_R13W, "r13w" }, |
831 | | 2, // { X86_REG_R14W, "r14w" }, |
832 | | 2, // { X86_REG_R15W, "r15w" }, |
833 | | 16, // { X86_REG_BND0, "bnd0" }, |
834 | | 16, // { X86_REG_BND1, "bnd0" }, |
835 | | 16, // { X86_REG_BND2, "bnd0" }, |
836 | | 16, // { X86_REG_BND3, "bnd0" }, |
837 | | }; |
838 | | |
839 | | const char *X86_reg_name(csh handle, unsigned int reg) |
840 | 2.66M | { |
841 | 2.66M | #ifndef CAPSTONE_DIET |
842 | 2.66M | cs_struct *ud = (cs_struct *)handle; |
843 | | |
844 | 2.66M | if (reg >= ARR_SIZE(reg_name_maps)) |
845 | 0 | return NULL; |
846 | | |
847 | 2.66M | if (reg == X86_REG_EFLAGS) { |
848 | 1.39M | if (ud->mode & CS_MODE_32) |
849 | 468k | return "eflags"; |
850 | 929k | if (ud->mode & CS_MODE_64) |
851 | 439k | return "rflags"; |
852 | 929k | } |
853 | | |
854 | 1.75M | return reg_name_maps[reg].name; |
855 | | #else |
856 | | return NULL; |
857 | | #endif |
858 | 2.66M | } |
859 | | |
860 | | #ifndef CAPSTONE_DIET |
861 | | static const char * const insn_name_maps[] = { |
862 | | NULL, // X86_INS_INVALID |
863 | | #ifndef CAPSTONE_X86_REDUCE |
864 | | #include "X86MappingInsnName.inc" |
865 | | #else |
866 | | #include "X86MappingInsnName_reduce.inc" |
867 | | #endif |
868 | | }; |
869 | | #endif |
870 | | |
871 | | // NOTE: insn_name_maps[] is sorted in order |
872 | | const char *X86_insn_name(csh handle, unsigned int id) |
873 | 2.02M | { |
874 | 2.02M | #ifndef CAPSTONE_DIET |
875 | 2.02M | if (id >= ARR_SIZE(insn_name_maps)) |
876 | 0 | return NULL; |
877 | | |
878 | 2.02M | return insn_name_maps[id]; |
879 | | #else |
880 | | return NULL; |
881 | | #endif |
882 | 2.02M | } |
883 | | |
884 | | #ifndef CAPSTONE_DIET |
885 | | static const name_map group_name_maps[] = { |
886 | | // generic groups |
887 | | { X86_GRP_INVALID, NULL }, |
888 | | { X86_GRP_JUMP, "jump" }, |
889 | | { X86_GRP_CALL, "call" }, |
890 | | { X86_GRP_RET, "ret" }, |
891 | | { X86_GRP_INT, "int" }, |
892 | | { X86_GRP_IRET, "iret" }, |
893 | | { X86_GRP_PRIVILEGE, "privilege" }, |
894 | | { X86_GRP_BRANCH_RELATIVE, "branch_relative" }, |
895 | | |
896 | | // architecture-specific groups |
897 | | { X86_GRP_VM, "vm" }, |
898 | | { X86_GRP_3DNOW, "3dnow" }, |
899 | | { X86_GRP_AES, "aes" }, |
900 | | { X86_GRP_ADX, "adx" }, |
901 | | { X86_GRP_AVX, "avx" }, |
902 | | { X86_GRP_AVX2, "avx2" }, |
903 | | { X86_GRP_AVX512, "avx512" }, |
904 | | { X86_GRP_BMI, "bmi" }, |
905 | | { X86_GRP_BMI2, "bmi2" }, |
906 | | { X86_GRP_CMOV, "cmov" }, |
907 | | { X86_GRP_F16C, "fc16" }, |
908 | | { X86_GRP_FMA, "fma" }, |
909 | | { X86_GRP_FMA4, "fma4" }, |
910 | | { X86_GRP_FSGSBASE, "fsgsbase" }, |
911 | | { X86_GRP_HLE, "hle" }, |
912 | | { X86_GRP_MMX, "mmx" }, |
913 | | { X86_GRP_MODE32, "mode32" }, |
914 | | { X86_GRP_MODE64, "mode64" }, |
915 | | { X86_GRP_RTM, "rtm" }, |
916 | | { X86_GRP_SHA, "sha" }, |
917 | | { X86_GRP_SSE1, "sse1" }, |
918 | | { X86_GRP_SSE2, "sse2" }, |
919 | | { X86_GRP_SSE3, "sse3" }, |
920 | | { X86_GRP_SSE41, "sse41" }, |
921 | | { X86_GRP_SSE42, "sse42" }, |
922 | | { X86_GRP_SSE4A, "sse4a" }, |
923 | | { X86_GRP_SSSE3, "ssse3" }, |
924 | | { X86_GRP_PCLMUL, "pclmul" }, |
925 | | { X86_GRP_XOP, "xop" }, |
926 | | { X86_GRP_CDI, "cdi" }, |
927 | | { X86_GRP_ERI, "eri" }, |
928 | | { X86_GRP_TBM, "tbm" }, |
929 | | { X86_GRP_16BITMODE, "16bitmode" }, |
930 | | { X86_GRP_NOT64BITMODE, "not64bitmode" }, |
931 | | { X86_GRP_SGX, "sgx" }, |
932 | | { X86_GRP_DQI, "dqi" }, |
933 | | { X86_GRP_BWI, "bwi" }, |
934 | | { X86_GRP_PFI, "pfi" }, |
935 | | { X86_GRP_VLX, "vlx" }, |
936 | | { X86_GRP_SMAP, "smap" }, |
937 | | { X86_GRP_NOVLX, "novlx" }, |
938 | | { X86_GRP_FPU, "fpu" }, |
939 | | }; |
940 | | #endif |
941 | | |
942 | | const char *X86_group_name(csh handle, unsigned int id) |
943 | 878k | { |
944 | 878k | #ifndef CAPSTONE_DIET |
945 | 878k | return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); |
946 | | #else |
947 | | return NULL; |
948 | | #endif |
949 | 878k | } |
950 | | |
951 | | #define GET_INSTRINFO_ENUM |
952 | | #ifdef CAPSTONE_X86_REDUCE |
953 | | #include "X86GenInstrInfo_reduce.inc" |
954 | | |
955 | | const insn_map_x86 insns[] = { // reduce x86 instructions |
956 | | #include "X86MappingInsn_reduce.inc" |
957 | | }; |
958 | | #else |
959 | | #include "X86GenInstrInfo.inc" |
960 | | |
961 | | const insn_map_x86 insns[] = { // full x86 instructions |
962 | | #include "X86MappingInsn.inc" |
963 | | }; |
964 | | #endif |
965 | | |
966 | | #ifndef CAPSTONE_DIET |
967 | | // in arr, replace r1 = r2 |
968 | | static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) |
969 | 255k | { |
970 | 255k | uint8_t i; |
971 | | |
972 | 386k | for(i = 0; i < max; i++) { |
973 | 369k | if (arr[i] == r1) { |
974 | 238k | arr[i] = r2; |
975 | 238k | break; |
976 | 238k | } |
977 | 369k | } |
978 | 255k | } |
979 | | #endif |
980 | | |
981 | | // look for @id in @insns |
982 | | // return -1 if not found |
983 | | unsigned int find_insn(unsigned int id) |
984 | 7.00M | { |
985 | | // binary searching since the IDs are sorted in order |
986 | 7.00M | unsigned int left, right, m; |
987 | 7.00M | unsigned int max = ARR_SIZE(insns); |
988 | | |
989 | 7.00M | right = max - 1; |
990 | | |
991 | 7.00M | if (id < insns[0].id || id > insns[right].id) |
992 | | // not found |
993 | 189 | return -1; |
994 | | |
995 | 7.00M | left = 0; |
996 | | |
997 | 91.6M | while(left <= right) { |
998 | 91.6M | m = (left + right) / 2; |
999 | 91.6M | if (id == insns[m].id) { |
1000 | 7.00M | return m; |
1001 | 7.00M | } |
1002 | | |
1003 | 84.6M | if (id < insns[m].id) |
1004 | 50.6M | right = m - 1; |
1005 | 33.9M | else |
1006 | 33.9M | left = m + 1; |
1007 | 84.6M | } |
1008 | | |
1009 | | // not found |
1010 | | // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); |
1011 | 0 | return -1; |
1012 | 7.00M | } |
1013 | | |
1014 | | // given internal insn id, return public instruction info |
1015 | | void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
1016 | 2.02M | { |
1017 | 2.02M | unsigned int i = find_insn(id); |
1018 | 2.02M | if (i != -1) { |
1019 | 2.02M | insn->id = insns[i].mapid; |
1020 | | |
1021 | 2.02M | if (h->detail_opt) { |
1022 | 2.02M | #ifndef CAPSTONE_DIET |
1023 | 2.02M | memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); |
1024 | 2.02M | insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); |
1025 | | |
1026 | | // special cases when regs_write[] depends on arch |
1027 | 2.02M | switch(id) { |
1028 | 2.02M | default: |
1029 | 2.02M | memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
1030 | 2.02M | insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
1031 | 2.02M | break; |
1032 | 498 | case X86_RDTSC: |
1033 | 498 | if (h->mode == CS_MODE_64) { |
1034 | 198 | memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
1035 | 198 | insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
1036 | 300 | } else { |
1037 | 300 | insn->detail->regs_write[0] = X86_REG_EAX; |
1038 | 300 | insn->detail->regs_write[1] = X86_REG_EDX; |
1039 | 300 | insn->detail->regs_write_count = 2; |
1040 | 300 | } |
1041 | 498 | break; |
1042 | 1.15k | case X86_RDTSCP: |
1043 | 1.15k | if (h->mode == CS_MODE_64) { |
1044 | 491 | memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
1045 | 491 | insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
1046 | 667 | } else { |
1047 | 667 | insn->detail->regs_write[0] = X86_REG_EAX; |
1048 | 667 | insn->detail->regs_write[1] = X86_REG_ECX; |
1049 | 667 | insn->detail->regs_write[2] = X86_REG_EDX; |
1050 | 667 | insn->detail->regs_write_count = 3; |
1051 | 667 | } |
1052 | 1.15k | break; |
1053 | 2.02M | } |
1054 | | |
1055 | 2.02M | switch(insn->id) { |
1056 | 1.86M | default: |
1057 | 1.86M | break; |
1058 | | |
1059 | 1.86M | case X86_INS_LOOP: |
1060 | 7.89k | case X86_INS_LOOPE: |
1061 | 12.2k | case X86_INS_LOOPNE: |
1062 | 12.2k | switch(h->mode) { |
1063 | 0 | default: break; |
1064 | 3.84k | case CS_MODE_16: |
1065 | 3.84k | insn->detail->regs_read[0] = X86_REG_CX; |
1066 | 3.84k | insn->detail->regs_read_count = 1; |
1067 | 3.84k | insn->detail->regs_write[0] = X86_REG_CX; |
1068 | 3.84k | insn->detail->regs_write_count = 1; |
1069 | 3.84k | break; |
1070 | 4.00k | case CS_MODE_32: |
1071 | 4.00k | insn->detail->regs_read[0] = X86_REG_ECX; |
1072 | 4.00k | insn->detail->regs_read_count = 1; |
1073 | 4.00k | insn->detail->regs_write[0] = X86_REG_ECX; |
1074 | 4.00k | insn->detail->regs_write_count = 1; |
1075 | 4.00k | break; |
1076 | 4.42k | case CS_MODE_64: |
1077 | 4.42k | insn->detail->regs_read[0] = X86_REG_RCX; |
1078 | 4.42k | insn->detail->regs_read_count = 1; |
1079 | 4.42k | insn->detail->regs_write[0] = X86_REG_RCX; |
1080 | 4.42k | insn->detail->regs_write_count = 1; |
1081 | 4.42k | break; |
1082 | 12.2k | } |
1083 | | |
1084 | | // LOOPE & LOOPNE also read EFLAGS |
1085 | 12.2k | if (insn->id != X86_INS_LOOP) { |
1086 | 6.96k | insn->detail->regs_read[1] = X86_REG_EFLAGS; |
1087 | 6.96k | insn->detail->regs_read_count = 2; |
1088 | 6.96k | } |
1089 | | |
1090 | 12.2k | break; |
1091 | | |
1092 | 7.17k | case X86_INS_LODSB: |
1093 | 16.2k | case X86_INS_LODSD: |
1094 | 18.4k | case X86_INS_LODSQ: |
1095 | 23.7k | case X86_INS_LODSW: |
1096 | 23.7k | switch(h->mode) { |
1097 | 6.80k | default: |
1098 | 6.80k | break; |
1099 | 7.12k | case CS_MODE_16: |
1100 | 7.12k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); |
1101 | 7.12k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); |
1102 | 7.12k | break; |
1103 | 9.84k | case CS_MODE_64: |
1104 | 9.84k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); |
1105 | 9.84k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); |
1106 | 9.84k | break; |
1107 | 23.7k | } |
1108 | 23.7k | break; |
1109 | | |
1110 | 23.7k | case X86_INS_SCASB: |
1111 | 12.3k | case X86_INS_SCASW: |
1112 | 13.9k | case X86_INS_SCASQ: |
1113 | 20.1k | case X86_INS_STOSB: |
1114 | 24.9k | case X86_INS_STOSD: |
1115 | 26.7k | case X86_INS_STOSQ: |
1116 | 29.7k | case X86_INS_STOSW: |
1117 | 29.7k | switch(h->mode) { |
1118 | 6.26k | default: |
1119 | 6.26k | break; |
1120 | 14.9k | case CS_MODE_16: |
1121 | 14.9k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); |
1122 | 14.9k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); |
1123 | 14.9k | break; |
1124 | 8.51k | case CS_MODE_64: |
1125 | 8.51k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); |
1126 | 8.51k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); |
1127 | 8.51k | break; |
1128 | 29.7k | } |
1129 | 29.7k | break; |
1130 | | |
1131 | 29.7k | case X86_INS_CMPSB: |
1132 | 21.7k | case X86_INS_CMPSD: |
1133 | 24.0k | case X86_INS_CMPSQ: |
1134 | 29.2k | case X86_INS_CMPSW: |
1135 | 38.5k | case X86_INS_MOVSB: |
1136 | 45.3k | case X86_INS_MOVSW: |
1137 | 55.4k | case X86_INS_MOVSD: |
1138 | 57.3k | case X86_INS_MOVSQ: |
1139 | 57.3k | switch(h->mode) { |
1140 | 13.7k | default: |
1141 | 13.7k | break; |
1142 | 19.4k | case CS_MODE_16: |
1143 | 19.4k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); |
1144 | 19.4k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); |
1145 | 19.4k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); |
1146 | 19.4k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); |
1147 | 19.4k | break; |
1148 | 24.2k | case CS_MODE_64: |
1149 | 24.2k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); |
1150 | 24.2k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); |
1151 | 24.2k | arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); |
1152 | 24.2k | arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); |
1153 | 24.2k | break; |
1154 | 57.3k | } |
1155 | 57.3k | break; |
1156 | | |
1157 | 57.3k | case X86_INS_RET: |
1158 | 35.2k | switch(h->mode) { |
1159 | 10.4k | case CS_MODE_16: |
1160 | 10.4k | insn->detail->regs_write[0] = X86_REG_SP; |
1161 | 10.4k | insn->detail->regs_read[0] = X86_REG_SP; |
1162 | 10.4k | break; |
1163 | 12.7k | case CS_MODE_32: |
1164 | 12.7k | insn->detail->regs_write[0] = X86_REG_ESP; |
1165 | 12.7k | insn->detail->regs_read[0] = X86_REG_ESP; |
1166 | 12.7k | break; |
1167 | 12.0k | default: // 64-bit |
1168 | 12.0k | insn->detail->regs_write[0] = X86_REG_RSP; |
1169 | 12.0k | insn->detail->regs_read[0] = X86_REG_RSP; |
1170 | 12.0k | break; |
1171 | 35.2k | } |
1172 | 35.2k | insn->detail->regs_write_count = 1; |
1173 | 35.2k | insn->detail->regs_read_count = 1; |
1174 | 35.2k | break; |
1175 | 2.02M | } |
1176 | | |
1177 | 2.02M | memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); |
1178 | 2.02M | insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); |
1179 | | |
1180 | 2.02M | if (insns[i].branch || insns[i].indirect_branch) { |
1181 | | // this insn also belongs to JUMP group. add JUMP group |
1182 | 136k | insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP; |
1183 | 136k | insn->detail->groups_count++; |
1184 | 136k | } |
1185 | | |
1186 | 2.02M | switch (insns[i].id) { |
1187 | 3.36k | case X86_OUT8ir: |
1188 | 4.86k | case X86_OUT16ir: |
1189 | 7.70k | case X86_OUT32ir: |
1190 | 7.70k | if (insn->detail->x86.operands[0].imm == -78) { |
1191 | | // Writing to port 0xb2 causes an SMI on most platforms |
1192 | | // See: http://cs.gmu.edu/~tr-admin/papers/GMU-CS-TR-2011-8.pdf |
1193 | 0 | insn->detail->groups[insn->detail->groups_count] = X86_GRP_INT; |
1194 | 0 | insn->detail->groups_count++; |
1195 | 0 | } |
1196 | 7.70k | break; |
1197 | | |
1198 | 2.01M | default: |
1199 | 2.01M | break; |
1200 | 2.02M | } |
1201 | 2.02M | #endif |
1202 | 2.02M | } |
1203 | 2.02M | } |
1204 | 2.02M | } |
1205 | | |
1206 | | // map special instructions with accumulate registers. |
1207 | | // this is needed because LLVM embeds these register names into AsmStrs[], |
1208 | | // but not separately in operands |
1209 | | struct insn_reg { |
1210 | | uint16_t insn; |
1211 | | x86_reg reg; |
1212 | | enum cs_ac_type access; |
1213 | | }; |
1214 | | |
1215 | | struct insn_reg2 { |
1216 | | uint16_t insn; |
1217 | | x86_reg reg1, reg2; |
1218 | | enum cs_ac_type access1, access2; |
1219 | | }; |
1220 | | |
1221 | | static const struct insn_reg insn_regs_att[] = { |
1222 | | { X86_INSB, X86_REG_DX, CS_AC_READ }, |
1223 | | { X86_INSL, X86_REG_DX, CS_AC_READ }, |
1224 | | { X86_INSW, X86_REG_DX, CS_AC_READ }, |
1225 | | { X86_MOV16o16a, X86_REG_AX, CS_AC_READ }, |
1226 | | { X86_MOV16o32a, X86_REG_AX, CS_AC_READ }, |
1227 | | { X86_MOV16o64a, X86_REG_AX, CS_AC_READ }, |
1228 | | { X86_MOV32o16a, X86_REG_EAX, CS_AC_READ }, |
1229 | | { X86_MOV32o32a, X86_REG_EAX, CS_AC_READ }, |
1230 | | { X86_MOV32o64a, X86_REG_EAX, CS_AC_READ }, |
1231 | | { X86_MOV64o32a, X86_REG_RAX, CS_AC_READ }, |
1232 | | { X86_MOV64o64a, X86_REG_RAX, CS_AC_READ }, |
1233 | | { X86_MOV8o16a, X86_REG_AL, CS_AC_READ }, |
1234 | | { X86_MOV8o32a, X86_REG_AL, CS_AC_READ }, |
1235 | | { X86_MOV8o64a, X86_REG_AL, CS_AC_READ }, |
1236 | | { X86_OUT16ir, X86_REG_AX, CS_AC_READ }, |
1237 | | { X86_OUT32ir, X86_REG_EAX, CS_AC_READ }, |
1238 | | { X86_OUT8ir, X86_REG_AL, CS_AC_READ }, |
1239 | | { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, |
1240 | | { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, |
1241 | | { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, |
1242 | | { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, |
1243 | | { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, |
1244 | | { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, |
1245 | | { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, |
1246 | | { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, |
1247 | | { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, |
1248 | | { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, |
1249 | | { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, |
1250 | | { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, |
1251 | | { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, |
1252 | | { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, |
1253 | | { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, |
1254 | | { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, |
1255 | | { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, |
1256 | | { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, |
1257 | | { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, |
1258 | | { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, |
1259 | | { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, |
1260 | | { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, |
1261 | | { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, |
1262 | | { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, |
1263 | | { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, |
1264 | | { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, |
1265 | | { X86_RCL16rCL, X86_REG_CL, CS_AC_READ }, |
1266 | | { X86_RCL32rCL, X86_REG_CL, CS_AC_READ }, |
1267 | | { X86_RCL64rCL, X86_REG_CL, CS_AC_READ }, |
1268 | | { X86_RCL8rCL, X86_REG_CL, CS_AC_READ }, |
1269 | | { X86_RCR16rCL, X86_REG_CL, CS_AC_READ }, |
1270 | | { X86_RCR32rCL, X86_REG_CL, CS_AC_READ }, |
1271 | | { X86_RCR64rCL, X86_REG_CL, CS_AC_READ }, |
1272 | | { X86_RCR8rCL, X86_REG_CL, CS_AC_READ }, |
1273 | | { X86_ROL16rCL, X86_REG_CL, CS_AC_READ }, |
1274 | | { X86_ROL32rCL, X86_REG_CL, CS_AC_READ }, |
1275 | | { X86_ROL64rCL, X86_REG_CL, CS_AC_READ }, |
1276 | | { X86_ROL8rCL, X86_REG_CL, CS_AC_READ }, |
1277 | | { X86_ROR16rCL, X86_REG_CL, CS_AC_READ }, |
1278 | | { X86_ROR32rCL, X86_REG_CL, CS_AC_READ }, |
1279 | | { X86_ROR64rCL, X86_REG_CL, CS_AC_READ }, |
1280 | | { X86_ROR8rCL, X86_REG_CL, CS_AC_READ }, |
1281 | | { X86_SAL16rCL, X86_REG_CL, CS_AC_READ }, |
1282 | | { X86_SAL32rCL, X86_REG_CL, CS_AC_READ }, |
1283 | | { X86_SAL64rCL, X86_REG_CL, CS_AC_READ }, |
1284 | | { X86_SAL8rCL, X86_REG_CL, CS_AC_READ }, |
1285 | | { X86_SAR16rCL, X86_REG_CL, CS_AC_READ }, |
1286 | | { X86_SAR32rCL, X86_REG_CL, CS_AC_READ }, |
1287 | | { X86_SAR64rCL, X86_REG_CL, CS_AC_READ }, |
1288 | | { X86_SAR8rCL, X86_REG_CL, CS_AC_READ }, |
1289 | | { X86_SHL16rCL, X86_REG_CL, CS_AC_READ }, |
1290 | | { X86_SHL32rCL, X86_REG_CL, CS_AC_READ }, |
1291 | | { X86_SHL64rCL, X86_REG_CL, CS_AC_READ }, |
1292 | | { X86_SHL8rCL, X86_REG_CL, CS_AC_READ }, |
1293 | | { X86_SHLD16mrCL, X86_REG_CL, CS_AC_READ }, |
1294 | | { X86_SHLD16rrCL, X86_REG_CL, CS_AC_READ }, |
1295 | | { X86_SHLD32mrCL, X86_REG_CL, CS_AC_READ }, |
1296 | | { X86_SHLD32rrCL, X86_REG_CL, CS_AC_READ }, |
1297 | | { X86_SHLD64mrCL, X86_REG_CL, CS_AC_READ }, |
1298 | | { X86_SHLD64rrCL, X86_REG_CL, CS_AC_READ }, |
1299 | | { X86_SHR16rCL, X86_REG_CL, CS_AC_READ }, |
1300 | | { X86_SHR32rCL, X86_REG_CL, CS_AC_READ }, |
1301 | | { X86_SHR64rCL, X86_REG_CL, CS_AC_READ }, |
1302 | | { X86_SHR8rCL, X86_REG_CL, CS_AC_READ }, |
1303 | | { X86_SHRD16mrCL, X86_REG_CL, CS_AC_READ }, |
1304 | | { X86_SHRD16rrCL, X86_REG_CL, CS_AC_READ }, |
1305 | | { X86_SHRD32mrCL, X86_REG_CL, CS_AC_READ }, |
1306 | | { X86_SHRD32rrCL, X86_REG_CL, CS_AC_READ }, |
1307 | | { X86_SHRD64mrCL, X86_REG_CL, CS_AC_READ }, |
1308 | | { X86_SHRD64rrCL, X86_REG_CL, CS_AC_READ }, |
1309 | | { X86_XCHG16ar, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1310 | | { X86_XCHG32ar, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1311 | | { X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1312 | | }; |
1313 | | |
1314 | | static const struct insn_reg insn_regs_att_extra[] = { |
1315 | | // dummy entry, to avoid empty array |
1316 | | { 0, 0 }, |
1317 | | #ifndef CAPSTONE_X86_REDUCE |
1318 | | { X86_ADD_FrST0, X86_REG_ST0, CS_AC_READ }, |
1319 | | { X86_DIVR_FrST0, X86_REG_ST0, CS_AC_READ }, |
1320 | | { X86_DIV_FrST0, X86_REG_ST0, CS_AC_READ }, |
1321 | | { X86_FNSTSW16r, X86_REG_AX, CS_AC_READ }, |
1322 | | { X86_MUL_FrST0, X86_REG_ST0, CS_AC_READ }, |
1323 | | { X86_SKINIT, X86_REG_EAX, CS_AC_READ }, |
1324 | | { X86_SUBR_FrST0, X86_REG_ST0, CS_AC_READ }, |
1325 | | { X86_SUB_FrST0, X86_REG_ST0, CS_AC_READ }, |
1326 | | { X86_VMLOAD32, X86_REG_EAX, CS_AC_READ }, |
1327 | | { X86_VMLOAD64, X86_REG_RAX, CS_AC_READ }, |
1328 | | { X86_VMRUN32, X86_REG_EAX, CS_AC_READ }, |
1329 | | { X86_VMRUN64, X86_REG_RAX, CS_AC_READ }, |
1330 | | { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, |
1331 | | { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, |
1332 | | #endif |
1333 | | }; |
1334 | | |
1335 | | static const struct insn_reg insn_regs_intel[] = { |
1336 | | { X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1337 | | { X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1338 | | { X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1339 | | { X86_ADC8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1340 | | { X86_ADD16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1341 | | { X86_ADD32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1342 | | { X86_ADD64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1343 | | { X86_ADD8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1344 | | { X86_AND16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1345 | | { X86_AND32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1346 | | { X86_AND64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1347 | | { X86_AND8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1348 | | { X86_CMP16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1349 | | { X86_CMP32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1350 | | { X86_CMP64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1351 | | { X86_CMP8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1352 | | { X86_IN16ri, X86_REG_AX, CS_AC_WRITE }, |
1353 | | { X86_IN32ri, X86_REG_EAX, CS_AC_WRITE }, |
1354 | | { X86_IN8ri, X86_REG_AL, CS_AC_WRITE }, |
1355 | | { X86_LODSB, X86_REG_AL, CS_AC_WRITE }, |
1356 | | { X86_LODSL, X86_REG_EAX, CS_AC_WRITE }, |
1357 | | { X86_LODSQ, X86_REG_RAX, CS_AC_WRITE }, |
1358 | | { X86_LODSW, X86_REG_AX, CS_AC_WRITE }, |
1359 | | { X86_MOV16ao16, X86_REG_AX, CS_AC_WRITE }, // 16-bit A1 1020 // mov ax, word ptr [0x2010] |
1360 | | { X86_MOV16ao32, X86_REG_AX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov ax, word ptr [0x40302010] |
1361 | | { X86_MOV16ao64, X86_REG_AX, CS_AC_WRITE }, // 64-bit 66 A1 1020304050607080 // movabs ax, word ptr [0x8070605040302010] |
1362 | | { X86_MOV32ao16, X86_REG_EAX, CS_AC_WRITE }, // 32-bit 67 A1 1020 // mov eax, dword ptr [0x2010] |
1363 | | { X86_MOV32ao32, X86_REG_EAX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov eax, dword ptr [0x40302010] |
1364 | | { X86_MOV32ao64, X86_REG_EAX, CS_AC_WRITE }, // 64-bit A1 1020304050607080 // movabs eax, dword ptr [0x8070605040302010] |
1365 | | { X86_MOV64ao32, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 8B04 10203040 // mov rax, qword ptr [0x40302010] |
1366 | | { X86_MOV64ao64, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 A1 1020304050607080 // movabs rax, qword ptr [0x8070605040302010] |
1367 | | { X86_MOV8ao16, X86_REG_AL, CS_AC_WRITE }, // 16-bit A0 1020 // mov al, byte ptr [0x2010] |
1368 | | { X86_MOV8ao32, X86_REG_AL, CS_AC_WRITE }, // 32-bit A0 10203040 // mov al, byte ptr [0x40302010] |
1369 | | { X86_MOV8ao64, X86_REG_AL, CS_AC_WRITE }, // 64-bit 66 A0 1020304050607080 // movabs al, byte ptr [0x8070605040302010] |
1370 | | { X86_OR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1371 | | { X86_OR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1372 | | { X86_OR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1373 | | { X86_OR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1374 | | { X86_OUTSB, X86_REG_DX, CS_AC_WRITE }, |
1375 | | { X86_OUTSL, X86_REG_DX, CS_AC_WRITE }, |
1376 | | { X86_OUTSW, X86_REG_DX, CS_AC_WRITE }, |
1377 | | { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, |
1378 | | { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, |
1379 | | { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, |
1380 | | { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, |
1381 | | { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, |
1382 | | { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, |
1383 | | { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, |
1384 | | { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, |
1385 | | { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, |
1386 | | { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, |
1387 | | { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, |
1388 | | { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, |
1389 | | { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, |
1390 | | { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, |
1391 | | { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, |
1392 | | { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, |
1393 | | { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, |
1394 | | { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, |
1395 | | { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, |
1396 | | { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, |
1397 | | { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, |
1398 | | { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, |
1399 | | { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, |
1400 | | { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, |
1401 | | { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, |
1402 | | { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, |
1403 | | { X86_SBB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1404 | | { X86_SBB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1405 | | { X86_SBB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1406 | | { X86_SBB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1407 | | { X86_SCASB, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1408 | | { X86_SCASL, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1409 | | { X86_SCASQ, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1410 | | { X86_SCASW, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1411 | | { X86_SUB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1412 | | { X86_SUB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1413 | | { X86_SUB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1414 | | { X86_SUB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1415 | | { X86_TEST16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1416 | | { X86_TEST32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1417 | | { X86_TEST64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1418 | | { X86_TEST8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1419 | | { X86_XOR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, |
1420 | | { X86_XOR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, |
1421 | | { X86_XOR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, |
1422 | | { X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, |
1423 | | }; |
1424 | | |
1425 | | static const struct insn_reg insn_regs_intel_extra[] = { |
1426 | | // dummy entry, to avoid empty array |
1427 | | { 0, 0, 0 }, |
1428 | | #ifndef CAPSTONE_X86_REDUCE |
1429 | | { X86_CMOVBE_F, X86_REG_ST0, CS_AC_WRITE }, |
1430 | | { X86_CMOVB_F, X86_REG_ST0, CS_AC_WRITE }, |
1431 | | { X86_CMOVE_F, X86_REG_ST0, CS_AC_WRITE }, |
1432 | | { X86_CMOVNBE_F, X86_REG_ST0, CS_AC_WRITE }, |
1433 | | { X86_CMOVNB_F, X86_REG_ST0, CS_AC_WRITE }, |
1434 | | { X86_CMOVNE_F, X86_REG_ST0, CS_AC_WRITE }, |
1435 | | { X86_CMOVNP_F, X86_REG_ST0, CS_AC_WRITE }, |
1436 | | { X86_CMOVP_F, X86_REG_ST0, CS_AC_WRITE }, |
1437 | | // { X86_COMP_FST0r, X86_REG_ST0, CS_AC_WRITE }, |
1438 | | // { X86_COM_FST0r, X86_REG_ST0, CS_AC_WRITE }, |
1439 | | { X86_FNSTSW16r, X86_REG_AX, CS_AC_WRITE }, |
1440 | | { X86_SKINIT, X86_REG_EAX, CS_AC_WRITE }, |
1441 | | { X86_VMLOAD32, X86_REG_EAX, CS_AC_WRITE }, |
1442 | | { X86_VMLOAD64, X86_REG_RAX, CS_AC_WRITE }, |
1443 | | { X86_VMRUN32, X86_REG_EAX, CS_AC_WRITE }, |
1444 | | { X86_VMRUN64, X86_REG_RAX, CS_AC_WRITE }, |
1445 | | { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, |
1446 | | { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, |
1447 | | { X86_XCH_F, X86_REG_ST0, CS_AC_WRITE }, |
1448 | | #endif |
1449 | | }; |
1450 | | |
1451 | | static const struct insn_reg2 insn_regs_intel2[] = { |
1452 | | { X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, |
1453 | | { X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, |
1454 | | { X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, |
1455 | | { X86_INVLPGA32, X86_REG_EAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, |
1456 | | { X86_INVLPGA64, X86_REG_RAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, |
1457 | | { X86_OUT16rr, X86_REG_DX, X86_REG_AX, CS_AC_READ, CS_AC_READ }, |
1458 | | { X86_OUT32rr, X86_REG_DX, X86_REG_EAX, CS_AC_READ, CS_AC_READ }, |
1459 | | { X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ }, |
1460 | | }; |
1461 | | |
1462 | | static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id) |
1463 | 3.89M | { |
1464 | 3.89M | unsigned int first, last, mid; |
1465 | | |
1466 | 3.89M | first = 0; |
1467 | 3.89M | last = max -1; |
1468 | | |
1469 | 3.89M | if (insns[0].insn > id || insns[last].insn < id) { |
1470 | | // not found |
1471 | 584k | return -1; |
1472 | 584k | } |
1473 | | |
1474 | 20.2M | while (first <= last) { |
1475 | 17.0M | mid = (first + last) / 2; |
1476 | 17.0M | if (insns[mid].insn < id) { |
1477 | 8.09M | first = mid + 1; |
1478 | 8.99M | } else if (insns[mid].insn == id) { |
1479 | 161k | return mid; |
1480 | 8.83M | } else { |
1481 | 8.83M | if (mid == 0) |
1482 | 0 | break; |
1483 | 8.83M | last = mid - 1; |
1484 | 8.83M | } |
1485 | 17.0M | } |
1486 | | |
1487 | | // not found |
1488 | 3.14M | return -1; |
1489 | 3.30M | } |
1490 | | |
1491 | | static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id) |
1492 | 1.86M | { |
1493 | 1.86M | unsigned int first, last, mid; |
1494 | | |
1495 | 1.86M | first = 0; |
1496 | 1.86M | last = max -1; |
1497 | | |
1498 | 1.86M | if (insns[0].insn > id || insns[last].insn < id) { |
1499 | | // not found |
1500 | 1.38M | return -1; |
1501 | 1.38M | } |
1502 | | |
1503 | 1.88M | while (first <= last) { |
1504 | 1.44M | mid = (first + last) / 2; |
1505 | 1.44M | if (insns[mid].insn < id) { |
1506 | 940k | first = mid + 1; |
1507 | 940k | } else if (insns[mid].insn == id) { |
1508 | 34.6k | return mid; |
1509 | 468k | } else { |
1510 | 468k | if (mid == 0) |
1511 | 0 | break; |
1512 | 468k | last = mid - 1; |
1513 | 468k | } |
1514 | 1.44M | } |
1515 | | |
1516 | | // not found |
1517 | 445k | return -1; |
1518 | 480k | } |
1519 | | |
1520 | | // return register of given instruction id |
1521 | | // return 0 if not found |
1522 | | // this is to handle instructions embedding accumulate registers into AsmStrs[] |
1523 | | x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access) |
1524 | 922k | { |
1525 | 922k | int i; |
1526 | | |
1527 | 922k | i = binary_search1(insn_regs_intel, ARR_SIZE(insn_regs_intel), id); |
1528 | 922k | if (i != -1) { |
1529 | 98.9k | if (access) { |
1530 | 98.9k | *access = insn_regs_intel[i].access; |
1531 | 98.9k | } |
1532 | 98.9k | return insn_regs_intel[i].reg; |
1533 | 98.9k | } |
1534 | | |
1535 | 824k | i = binary_search1(insn_regs_intel_extra, ARR_SIZE(insn_regs_intel_extra), id); |
1536 | 824k | if (i != -1) { |
1537 | 1.31k | if (access) { |
1538 | 1.31k | *access = insn_regs_intel_extra[i].access; |
1539 | 1.31k | } |
1540 | 1.31k | return insn_regs_intel_extra[i].reg; |
1541 | 1.31k | } |
1542 | | |
1543 | | // not found |
1544 | 822k | return 0; |
1545 | 824k | } |
1546 | | |
1547 | | bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) |
1548 | 822k | { |
1549 | 822k | int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); |
1550 | 822k | if (i != -1) { |
1551 | 15.2k | *reg1 = insn_regs_intel2[i].reg1; |
1552 | 15.2k | *reg2 = insn_regs_intel2[i].reg2; |
1553 | 15.2k | if (access1) |
1554 | 15.2k | *access1 = insn_regs_intel2[i].access1; |
1555 | 15.2k | if (access2) |
1556 | 15.2k | *access2 = insn_regs_intel2[i].access2; |
1557 | 15.2k | return true; |
1558 | 15.2k | } |
1559 | | |
1560 | | // not found |
1561 | 807k | return false; |
1562 | 822k | } |
1563 | | |
1564 | | x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access) |
1565 | 1.10M | { |
1566 | 1.10M | int i; |
1567 | | |
1568 | 1.10M | i = binary_search1(insn_regs_att, ARR_SIZE(insn_regs_att), id); |
1569 | 1.10M | if (i != -1) { |
1570 | 60.3k | if (access) |
1571 | 60.3k | *access = insn_regs_att[i].access; |
1572 | 60.3k | return insn_regs_att[i].reg; |
1573 | 60.3k | } |
1574 | | |
1575 | 1.04M | i = binary_search1(insn_regs_att_extra, ARR_SIZE(insn_regs_att_extra), id); |
1576 | 1.04M | if (i != -1) { |
1577 | 740 | if (access) |
1578 | 740 | *access = insn_regs_att_extra[i].access; |
1579 | 740 | return insn_regs_att_extra[i].reg; |
1580 | 740 | } |
1581 | | |
1582 | | // not found |
1583 | 1.04M | return 0; |
1584 | 1.04M | } |
1585 | | |
1586 | | // ATT just reuses Intel data, but with the order of registers reversed |
1587 | | bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) |
1588 | 1.04M | { |
1589 | 1.04M | int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); |
1590 | 1.04M | if (i != -1) { |
1591 | 19.4k | *reg1 = insn_regs_intel2[i].reg2; |
1592 | 19.4k | *reg2 = insn_regs_intel2[i].reg1; |
1593 | 19.4k | if (access1) |
1594 | 19.4k | *access1 = insn_regs_intel2[i].access2; |
1595 | 19.4k | if (access2) |
1596 | 19.4k | *access2 = insn_regs_intel2[i].access1; |
1597 | 19.4k | return true; |
1598 | 19.4k | } |
1599 | | |
1600 | | // not found |
1601 | 1.02M | return false; |
1602 | 1.04M | } |
1603 | | |
1604 | | // given MCInst's id, find out if this insn is valid for REPNE prefix |
1605 | | static bool valid_repne(cs_struct *h, unsigned int opcode) |
1606 | 54.0k | { |
1607 | 54.0k | unsigned int id; |
1608 | 54.0k | unsigned int i = find_insn(opcode); |
1609 | 54.0k | if (i != -1) { |
1610 | 54.0k | id = insns[i].mapid; |
1611 | 54.0k | switch(id) { |
1612 | 34.7k | default: |
1613 | 34.7k | return false; |
1614 | | |
1615 | 672 | case X86_INS_CMPSB: |
1616 | 1.23k | case X86_INS_CMPSS: |
1617 | 2.00k | case X86_INS_CMPSW: |
1618 | 2.76k | case X86_INS_CMPSQ: |
1619 | | |
1620 | 3.23k | case X86_INS_SCASB: |
1621 | 3.76k | case X86_INS_SCASW: |
1622 | 4.33k | case X86_INS_SCASQ: |
1623 | | |
1624 | 4.57k | case X86_INS_MOVSB: |
1625 | 4.88k | case X86_INS_MOVSS: |
1626 | 5.23k | case X86_INS_MOVSW: |
1627 | 5.99k | case X86_INS_MOVSQ: |
1628 | | |
1629 | 7.00k | case X86_INS_LODSB: |
1630 | 7.34k | case X86_INS_LODSW: |
1631 | 7.89k | case X86_INS_LODSD: |
1632 | 8.69k | case X86_INS_LODSQ: |
1633 | | |
1634 | 8.94k | case X86_INS_STOSB: |
1635 | 9.33k | case X86_INS_STOSW: |
1636 | 9.75k | case X86_INS_STOSD: |
1637 | 10.0k | case X86_INS_STOSQ: |
1638 | | |
1639 | 10.8k | case X86_INS_INSB: |
1640 | 11.5k | case X86_INS_INSW: |
1641 | 12.0k | case X86_INS_INSD: |
1642 | | |
1643 | 12.2k | case X86_INS_OUTSB: |
1644 | 13.1k | case X86_INS_OUTSW: |
1645 | 14.1k | case X86_INS_OUTSD: |
1646 | | |
1647 | 14.1k | return true; |
1648 | | |
1649 | 1.90k | case X86_INS_MOVSD: |
1650 | 1.90k | if (opcode == X86_MOVSW) // REP MOVSB |
1651 | 0 | return true; |
1652 | 1.90k | return false; |
1653 | | |
1654 | 2.68k | case X86_INS_CMPSD: |
1655 | 2.68k | if (opcode == X86_CMPSL) // REP CMPSD |
1656 | 847 | return true; |
1657 | 1.84k | return false; |
1658 | | |
1659 | 678 | case X86_INS_SCASD: |
1660 | 678 | if (opcode == X86_SCASL) // REP SCASD |
1661 | 678 | return true; |
1662 | 0 | return false; |
1663 | 54.0k | } |
1664 | 54.0k | } |
1665 | | |
1666 | | // not found |
1667 | 0 | return false; |
1668 | 54.0k | } |
1669 | | |
1670 | | // given MCInst's id, find out if this insn is valid for BND prefix |
1671 | | // BND prefix is valid for CALL/JMP/RET |
1672 | | #ifndef CAPSTONE_DIET |
1673 | | static bool valid_bnd(cs_struct *h, unsigned int opcode) |
1674 | 38.4k | { |
1675 | 38.4k | unsigned int id; |
1676 | 38.4k | unsigned int i = find_insn(opcode); |
1677 | 38.4k | if (i != -1) { |
1678 | 38.4k | id = insns[i].mapid; |
1679 | 38.4k | switch(id) { |
1680 | 27.4k | default: |
1681 | 27.4k | return false; |
1682 | | |
1683 | 353 | case X86_INS_JAE: |
1684 | 570 | case X86_INS_JA: |
1685 | 732 | case X86_INS_JBE: |
1686 | 1.15k | case X86_INS_JB: |
1687 | 1.44k | case X86_INS_JCXZ: |
1688 | 1.83k | case X86_INS_JECXZ: |
1689 | 2.00k | case X86_INS_JE: |
1690 | 2.97k | case X86_INS_JGE: |
1691 | 3.25k | case X86_INS_JG: |
1692 | 3.75k | case X86_INS_JLE: |
1693 | 4.82k | case X86_INS_JL: |
1694 | 5.55k | case X86_INS_JMP: |
1695 | 6.08k | case X86_INS_JNE: |
1696 | 6.34k | case X86_INS_JNO: |
1697 | 6.71k | case X86_INS_JNP: |
1698 | 7.22k | case X86_INS_JNS: |
1699 | 7.66k | case X86_INS_JO: |
1700 | 8.08k | case X86_INS_JP: |
1701 | 8.40k | case X86_INS_JRCXZ: |
1702 | 9.00k | case X86_INS_JS: |
1703 | | |
1704 | 9.30k | case X86_INS_CALL: |
1705 | 10.5k | case X86_INS_RET: |
1706 | 10.6k | case X86_INS_RETF: |
1707 | 11.0k | case X86_INS_RETFQ: |
1708 | 11.0k | return true; |
1709 | 38.4k | } |
1710 | 38.4k | } |
1711 | | |
1712 | | // not found |
1713 | 0 | return false; |
1714 | 38.4k | } |
1715 | | |
1716 | | // return true if the opcode is XCHG [mem] |
1717 | | static bool xchg_mem(unsigned int opcode) |
1718 | 101k | { |
1719 | 101k | switch(opcode) { |
1720 | 98.8k | default: |
1721 | 98.8k | return false; |
1722 | 783 | case X86_XCHG8rm: |
1723 | 1.13k | case X86_XCHG16rm: |
1724 | 1.51k | case X86_XCHG32rm: |
1725 | 2.41k | case X86_XCHG64rm: |
1726 | 2.41k | return true; |
1727 | 101k | } |
1728 | 101k | } |
1729 | | #endif |
1730 | | |
1731 | | // given MCInst's id, find out if this insn is valid for REP prefix |
1732 | | static bool valid_rep(cs_struct *h, unsigned int opcode) |
1733 | 45.9k | { |
1734 | 45.9k | unsigned int id; |
1735 | 45.9k | unsigned int i = find_insn(opcode); |
1736 | 45.9k | if (i != -1) { |
1737 | 45.9k | id = insns[i].mapid; |
1738 | 45.9k | switch(id) { |
1739 | 36.0k | default: |
1740 | 36.0k | return false; |
1741 | | |
1742 | 244 | case X86_INS_MOVSB: |
1743 | 643 | case X86_INS_MOVSW: |
1744 | 1.02k | case X86_INS_MOVSQ: |
1745 | | |
1746 | 1.73k | case X86_INS_LODSB: |
1747 | 2.34k | case X86_INS_LODSW: |
1748 | 2.79k | case X86_INS_LODSQ: |
1749 | | |
1750 | 3.68k | case X86_INS_STOSB: |
1751 | 4.00k | case X86_INS_STOSW: |
1752 | 5.32k | case X86_INS_STOSQ: |
1753 | | |
1754 | 5.58k | case X86_INS_INSB: |
1755 | 6.02k | case X86_INS_INSW: |
1756 | 6.55k | case X86_INS_INSD: |
1757 | | |
1758 | 6.94k | case X86_INS_OUTSB: |
1759 | 7.32k | case X86_INS_OUTSW: |
1760 | 7.68k | case X86_INS_OUTSD: |
1761 | 7.68k | return true; |
1762 | | |
1763 | | // following are some confused instructions, which have the same |
1764 | | // mnemonics in 128bit media instructions. Intel is horribly crazy! |
1765 | 677 | case X86_INS_MOVSD: |
1766 | 677 | if (opcode == X86_MOVSL) // REP MOVSD |
1767 | 490 | return true; |
1768 | 187 | return false; |
1769 | | |
1770 | 661 | case X86_INS_LODSD: |
1771 | 661 | if (opcode == X86_LODSL) // REP LODSD |
1772 | 661 | return true; |
1773 | 0 | return false; |
1774 | | |
1775 | 828 | case X86_INS_STOSD: |
1776 | 828 | if (opcode == X86_STOSL) // REP STOSD |
1777 | 828 | return true; |
1778 | 0 | return false; |
1779 | 45.9k | } |
1780 | 45.9k | } |
1781 | | |
1782 | | // not found |
1783 | 0 | return false; |
1784 | 45.9k | } |
1785 | | |
1786 | | #ifndef CAPSTONE_DIET |
1787 | | // given MCInst's id, find if this is a "repz ret" instruction |
1788 | | // gcc generates "repz ret" (f3 c3) instructions in some cases as an |
1789 | | // optimization for AMD platforms, see: |
1790 | | // https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg02117.html |
1791 | | static bool valid_ret_repz(cs_struct *h, unsigned int opcode) |
1792 | 31.1k | { |
1793 | 31.1k | unsigned int id; |
1794 | 31.1k | unsigned int i = find_insn(opcode); |
1795 | | |
1796 | 31.1k | if (i != -1) { |
1797 | 31.1k | id = insns[i].mapid; |
1798 | 31.1k | return id == X86_INS_RET; |
1799 | 31.1k | } |
1800 | | |
1801 | | // not found |
1802 | 0 | return false; |
1803 | 31.1k | } |
1804 | | #endif |
1805 | | |
1806 | | // given MCInst's id, find out if this insn is valid for REPE prefix |
1807 | | static bool valid_repe(cs_struct *h, unsigned int opcode) |
1808 | 36.2k | { |
1809 | 36.2k | unsigned int id; |
1810 | 36.2k | unsigned int i = find_insn(opcode); |
1811 | 36.2k | if (i != -1) { |
1812 | 36.2k | id = insns[i].mapid; |
1813 | 36.2k | switch(id) { |
1814 | 30.7k | default: |
1815 | 30.7k | return false; |
1816 | | |
1817 | 503 | case X86_INS_CMPSB: |
1818 | 928 | case X86_INS_CMPSW: |
1819 | 1.82k | case X86_INS_CMPSQ: |
1820 | | |
1821 | 2.12k | case X86_INS_SCASB: |
1822 | 3.16k | case X86_INS_SCASW: |
1823 | 3.62k | case X86_INS_SCASQ: |
1824 | 3.62k | return true; |
1825 | | |
1826 | | // following are some confused instructions, which have the same |
1827 | | // mnemonics in 128bit media instructions. Intel is horribly crazy! |
1828 | 913 | case X86_INS_CMPSD: |
1829 | 913 | if (opcode == X86_CMPSL) // REP CMPSD |
1830 | 573 | return true; |
1831 | 340 | return false; |
1832 | | |
1833 | 978 | case X86_INS_SCASD: |
1834 | 978 | if (opcode == X86_SCASL) // REP SCASD |
1835 | 978 | return true; |
1836 | 0 | return false; |
1837 | 36.2k | } |
1838 | 36.2k | } |
1839 | | |
1840 | | // not found |
1841 | 0 | return false; |
1842 | 36.2k | } |
1843 | | |
1844 | | // Given MCInst's id, find out if this insn is valid for NOTRACK prefix. |
1845 | | // NOTRACK prefix is valid for CALL/JMP. |
1846 | | static bool valid_notrack(cs_struct *h, unsigned int opcode) |
1847 | 5.87k | { |
1848 | 5.87k | unsigned int id; |
1849 | 5.87k | unsigned int i = find_insn(opcode); |
1850 | 5.87k | if (i != -1) { |
1851 | 5.87k | id = insns[i].mapid; |
1852 | 5.87k | switch(id) { |
1853 | 5.07k | default: |
1854 | 5.07k | return false; |
1855 | 362 | case X86_INS_CALL: |
1856 | 799 | case X86_INS_JMP: |
1857 | 799 | return true; |
1858 | 5.87k | } |
1859 | 5.87k | } |
1860 | | |
1861 | | // not found |
1862 | 0 | return false; |
1863 | 5.87k | } |
1864 | | |
1865 | | #ifndef CAPSTONE_DIET |
1866 | | // add *CX register to regs_read[] & regs_write[] |
1867 | | static void add_cx(MCInst *MI) |
1868 | 30.4k | { |
1869 | 30.4k | if (MI->csh->detail_opt) { |
1870 | 30.4k | x86_reg cx; |
1871 | | |
1872 | 30.4k | if (MI->csh->mode & CS_MODE_16) |
1873 | 9.96k | cx = X86_REG_CX; |
1874 | 20.5k | else if (MI->csh->mode & CS_MODE_32) |
1875 | 9.03k | cx = X86_REG_ECX; |
1876 | 11.4k | else // 64-bit |
1877 | 11.4k | cx = X86_REG_RCX; |
1878 | | |
1879 | 30.4k | MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx; |
1880 | 30.4k | MI->flat_insn->detail->regs_read_count++; |
1881 | | |
1882 | 30.4k | MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = cx; |
1883 | 30.4k | MI->flat_insn->detail->regs_write_count++; |
1884 | 30.4k | } |
1885 | 30.4k | } |
1886 | | #endif |
1887 | | |
1888 | | // return true if we patch the mnemonic |
1889 | | bool X86_lockrep(MCInst *MI, SStream *O) |
1890 | 2.02M | { |
1891 | 2.02M | unsigned int opcode; |
1892 | 2.02M | bool res = false; |
1893 | | |
1894 | 2.02M | switch(MI->x86_prefix[0]) { |
1895 | 1.87M | default: |
1896 | 1.87M | break; |
1897 | 1.87M | case 0xf0: |
1898 | 50.9k | #ifndef CAPSTONE_DIET |
1899 | 50.9k | if (MI->xAcquireRelease == 0xf2) |
1900 | 1.20k | SStream_concat(O, "xacquire|lock|"); |
1901 | 49.7k | else if (MI->xAcquireRelease == 0xf3) |
1902 | 503 | SStream_concat(O, "xrelease|lock|"); |
1903 | 49.2k | else |
1904 | 49.2k | SStream_concat(O, "lock|"); |
1905 | 50.9k | #endif |
1906 | 50.9k | break; |
1907 | 54.7k | case 0xf2: // repne |
1908 | 54.7k | opcode = MCInst_getOpcode(MI); |
1909 | | |
1910 | 54.7k | #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode |
1911 | 54.7k | if (xchg_mem(opcode) && MI->xAcquireRelease) { |
1912 | 662 | SStream_concat(O, "xacquire|"); |
1913 | 54.0k | } else if (valid_repne(MI->csh, opcode)) { |
1914 | 15.6k | SStream_concat(O, "repne|"); |
1915 | 15.6k | add_cx(MI); |
1916 | 38.4k | } else if (valid_bnd(MI->csh, opcode)) { |
1917 | 11.0k | SStream_concat(O, "bnd|"); |
1918 | 27.4k | } else { |
1919 | | // invalid prefix |
1920 | 27.4k | MI->x86_prefix[0] = 0; |
1921 | | |
1922 | | // handle special cases |
1923 | 27.4k | #ifndef CAPSTONE_X86_REDUCE |
1924 | | #if 0 |
1925 | | if (opcode == X86_MULPDrr) { |
1926 | | MCInst_setOpcode(MI, X86_MULSDrr); |
1927 | | SStream_concat0(O, "mulsd\t"); |
1928 | | res = true; |
1929 | | } |
1930 | | #endif |
1931 | 27.4k | #endif |
1932 | 27.4k | } |
1933 | | #else // diet mode -> only patch opcode in special cases |
1934 | | if (!valid_repne(MI->csh, opcode)) { |
1935 | | MI->x86_prefix[0] = 0; |
1936 | | } |
1937 | | #ifndef CAPSTONE_X86_REDUCE |
1938 | | #if 0 |
1939 | | // handle special cases |
1940 | | if (opcode == X86_MULPDrr) { |
1941 | | MCInst_setOpcode(MI, X86_MULSDrr); |
1942 | | } |
1943 | | #endif |
1944 | | #endif |
1945 | | #endif |
1946 | 54.7k | break; |
1947 | | |
1948 | 46.5k | case 0xf3: |
1949 | 46.5k | opcode = MCInst_getOpcode(MI); |
1950 | | |
1951 | 46.5k | #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode |
1952 | 46.5k | if (xchg_mem(opcode) && MI->xAcquireRelease) { |
1953 | 563 | SStream_concat(O, "xrelease|"); |
1954 | 45.9k | } else if (valid_rep(MI->csh, opcode)) { |
1955 | 9.66k | SStream_concat(O, "rep|"); |
1956 | 9.66k | add_cx(MI); |
1957 | 36.2k | } else if (valid_repe(MI->csh, opcode)) { |
1958 | 5.17k | SStream_concat(O, "repe|"); |
1959 | 5.17k | add_cx(MI); |
1960 | 31.1k | } else if (valid_ret_repz(MI->csh, opcode)) { |
1961 | 1.14k | SStream_concat(O, "repz|"); |
1962 | 29.9k | } else { |
1963 | | // invalid prefix |
1964 | 29.9k | MI->x86_prefix[0] = 0; |
1965 | | |
1966 | | // handle special cases |
1967 | 29.9k | #ifndef CAPSTONE_X86_REDUCE |
1968 | | #if 0 |
1969 | | // FIXME: remove this special case? |
1970 | | if (opcode == X86_MULPDrr) { |
1971 | | MCInst_setOpcode(MI, X86_MULSSrr); |
1972 | | SStream_concat0(O, "mulss\t"); |
1973 | | res = true; |
1974 | | } |
1975 | | #endif |
1976 | 29.9k | #endif |
1977 | 29.9k | } |
1978 | | #else // diet mode -> only patch opcode in special cases |
1979 | | if (!valid_rep(MI->csh, opcode) && !valid_repe(MI->csh, opcode)) { |
1980 | | MI->x86_prefix[0] = 0; |
1981 | | } |
1982 | | #ifndef CAPSTONE_X86_REDUCE |
1983 | | #if 0 |
1984 | | // handle special cases |
1985 | | // FIXME: remove this special case? |
1986 | | if (opcode == X86_MULPDrr) { |
1987 | | MCInst_setOpcode(MI, X86_MULSSrr); |
1988 | | } |
1989 | | #endif |
1990 | | #endif |
1991 | | #endif |
1992 | 46.5k | break; |
1993 | 2.02M | } |
1994 | | |
1995 | 2.02M | switch(MI->x86_prefix[1]) { |
1996 | 2.02M | default: |
1997 | 2.02M | break; |
1998 | 2.02M | case 0x3e: |
1999 | 5.87k | opcode = MCInst_getOpcode(MI); |
2000 | 5.87k | if (valid_notrack(MI->csh, opcode)) { |
2001 | 799 | SStream_concat(O, "notrack|"); |
2002 | 799 | } |
2003 | 5.87k | break; |
2004 | 2.02M | } |
2005 | | |
2006 | | // copy normalized prefix[] back to x86.prefix[] |
2007 | 2.02M | if (MI->csh->detail_opt) |
2008 | 2.02M | memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix)); |
2009 | | |
2010 | 2.02M | return res; |
2011 | 2.02M | } |
2012 | | |
2013 | | void op_addReg(MCInst *MI, int reg) |
2014 | 158k | { |
2015 | 158k | if (MI->csh->detail_opt) { |
2016 | 158k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; |
2017 | 158k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; |
2018 | 158k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg]; |
2019 | 158k | MI->flat_insn->detail->x86.op_count++; |
2020 | 158k | } |
2021 | | |
2022 | 158k | if (MI->op1_size == 0) |
2023 | 109k | MI->op1_size = MI->csh->regsize_map[reg]; |
2024 | 158k | } |
2025 | | |
2026 | | void op_addImm(MCInst *MI, int v) |
2027 | 9.74k | { |
2028 | 9.74k | if (MI->csh->detail_opt) { |
2029 | 9.74k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
2030 | 9.74k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v; |
2031 | | // if op_count > 0, then this operand's size is taken from the destination op |
2032 | 9.74k | if (MI->csh->syntax != CS_OPT_SYNTAX_ATT) { |
2033 | 9.74k | if (MI->flat_insn->detail->x86.op_count > 0) |
2034 | 9.74k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; |
2035 | 0 | else |
2036 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
2037 | 9.74k | } else |
2038 | 0 | MI->has_imm = true; |
2039 | 9.74k | MI->flat_insn->detail->x86.op_count++; |
2040 | 9.74k | } |
2041 | | |
2042 | 9.74k | if (MI->op1_size == 0) |
2043 | 0 | MI->op1_size = MI->imm_size; |
2044 | 9.74k | } |
2045 | | |
2046 | | void op_addXopCC(MCInst *MI, int v) |
2047 | 2.87k | { |
2048 | 2.87k | if (MI->csh->detail_opt) { |
2049 | 2.87k | MI->flat_insn->detail->x86.xop_cc = v; |
2050 | 2.87k | } |
2051 | 2.87k | } |
2052 | | |
2053 | | void op_addSseCC(MCInst *MI, int v) |
2054 | 0 | { |
2055 | 0 | if (MI->csh->detail_opt) { |
2056 | 0 | MI->flat_insn->detail->x86.sse_cc = v; |
2057 | 0 | } |
2058 | 0 | } |
2059 | | |
2060 | | void op_addAvxCC(MCInst *MI, int v) |
2061 | 22.2k | { |
2062 | 22.2k | if (MI->csh->detail_opt) { |
2063 | 22.2k | MI->flat_insn->detail->x86.avx_cc = v; |
2064 | 22.2k | } |
2065 | 22.2k | } |
2066 | | |
2067 | | void op_addAvxRoundingMode(MCInst *MI, int v) |
2068 | 4.41k | { |
2069 | 4.41k | if (MI->csh->detail_opt) { |
2070 | 4.41k | MI->flat_insn->detail->x86.avx_rm = v; |
2071 | 4.41k | } |
2072 | 4.41k | } |
2073 | | |
2074 | | // below functions supply details to X86GenAsmWriter*.inc |
2075 | | void op_addAvxZeroOpmask(MCInst *MI) |
2076 | 11.1k | { |
2077 | 11.1k | if (MI->csh->detail_opt) { |
2078 | | // link with the previous operand |
2079 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_zero_opmask = true; |
2080 | 11.1k | } |
2081 | 11.1k | } |
2082 | | |
2083 | | void op_addAvxSae(MCInst *MI) |
2084 | 9.37k | { |
2085 | 9.37k | if (MI->csh->detail_opt) { |
2086 | 9.37k | MI->flat_insn->detail->x86.avx_sae = true; |
2087 | 9.37k | } |
2088 | 9.37k | } |
2089 | | |
2090 | | void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v) |
2091 | 14.0k | { |
2092 | 14.0k | if (MI->csh->detail_opt) { |
2093 | | // link with the previous operand |
2094 | 14.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_bcast = v; |
2095 | 14.0k | } |
2096 | 14.0k | } |
2097 | | |
2098 | | #ifndef CAPSTONE_DIET |
2099 | | // map instruction to its characteristics |
2100 | | typedef struct insn_op { |
2101 | | uint64_t flags; // how this instruction update EFLAGS(arithmetic instructions) of FPU FLAGS(for FPU instructions) |
2102 | | uint8_t access[6]; |
2103 | | } insn_op; |
2104 | | |
2105 | | static const insn_op insn_ops[] = { |
2106 | | #ifdef CAPSTONE_X86_REDUCE |
2107 | | #include "X86MappingInsnOp_reduce.inc" |
2108 | | #else |
2109 | | #include "X86MappingInsnOp.inc" |
2110 | | #endif |
2111 | | }; |
2112 | | |
2113 | | // given internal insn id, return operand access info |
2114 | | const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags) |
2115 | 4.73M | { |
2116 | 4.73M | unsigned int i = find_insn(id); |
2117 | 4.73M | if (i != -1) { |
2118 | 4.73M | *eflags = insn_ops[i].flags; |
2119 | 4.73M | return insn_ops[i].access; |
2120 | 4.73M | } |
2121 | | |
2122 | 0 | return NULL; |
2123 | 4.73M | } |
2124 | | |
2125 | | void X86_reg_access(const cs_insn *insn, |
2126 | | cs_regs regs_read, uint8_t *regs_read_count, |
2127 | | cs_regs regs_write, uint8_t *regs_write_count) |
2128 | 0 | { |
2129 | 0 | uint8_t i; |
2130 | 0 | uint8_t read_count, write_count; |
2131 | 0 | cs_x86 *x86 = &(insn->detail->x86); |
2132 | |
|
2133 | 0 | read_count = insn->detail->regs_read_count; |
2134 | 0 | write_count = insn->detail->regs_write_count; |
2135 | | |
2136 | | // implicit registers |
2137 | 0 | memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); |
2138 | 0 | memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); |
2139 | | |
2140 | | // explicit registers |
2141 | 0 | for (i = 0; i < x86->op_count; i++) { |
2142 | 0 | cs_x86_op *op = &(x86->operands[i]); |
2143 | 0 | switch((int)op->type) { |
2144 | 0 | case X86_OP_REG: |
2145 | 0 | if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { |
2146 | 0 | regs_read[read_count] = op->reg; |
2147 | 0 | read_count++; |
2148 | 0 | } |
2149 | 0 | if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { |
2150 | 0 | regs_write[write_count] = op->reg; |
2151 | 0 | write_count++; |
2152 | 0 | } |
2153 | 0 | break; |
2154 | 0 | case X86_OP_MEM: |
2155 | | // registers appeared in memory references always being read |
2156 | 0 | if ((op->mem.segment != X86_REG_INVALID)) { |
2157 | 0 | regs_read[read_count] = op->mem.segment; |
2158 | 0 | read_count++; |
2159 | 0 | } |
2160 | 0 | if ((op->mem.base != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { |
2161 | 0 | regs_read[read_count] = op->mem.base; |
2162 | 0 | read_count++; |
2163 | 0 | } |
2164 | 0 | if ((op->mem.index != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { |
2165 | 0 | regs_read[read_count] = op->mem.index; |
2166 | 0 | read_count++; |
2167 | 0 | } |
2168 | 0 | default: |
2169 | 0 | break; |
2170 | 0 | } |
2171 | 0 | } |
2172 | | |
2173 | 0 | *regs_read_count = read_count; |
2174 | 0 | *regs_write_count = write_count; |
2175 | 0 | } |
2176 | | #endif |
2177 | | |
2178 | | // map immediate size to instruction id |
2179 | | // this array is sorted for binary searching |
2180 | | static const struct size_id { |
2181 | | uint8_t enc_size; |
2182 | | uint8_t size; |
2183 | | uint16_t id; |
2184 | | } x86_imm_size[] = { |
2185 | | #include "X86ImmSize.inc" |
2186 | | }; |
2187 | | |
2188 | | // given the instruction name, return the size of its immediate operand (or 0) |
2189 | | uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size) |
2190 | 308k | { |
2191 | | // binary searching since the IDs are sorted in order |
2192 | 308k | unsigned int left, right, m; |
2193 | | |
2194 | 308k | right = ARR_SIZE(x86_imm_size) - 1; |
2195 | | |
2196 | 308k | if (id < x86_imm_size[0].id || id > x86_imm_size[right].id) |
2197 | | // not found |
2198 | 0 | return 0; |
2199 | | |
2200 | 308k | left = 0; |
2201 | | |
2202 | 2.40M | while (left <= right) { |
2203 | 2.28M | m = (left + right) / 2; |
2204 | 2.28M | if (id == x86_imm_size[m].id) { |
2205 | 197k | if (enc_size != NULL) |
2206 | 195k | *enc_size = x86_imm_size[m].enc_size; |
2207 | | |
2208 | 197k | return x86_imm_size[m].size; |
2209 | 197k | } |
2210 | | |
2211 | 2.09M | if (id > x86_imm_size[m].id) |
2212 | 1.00M | left = m + 1; |
2213 | 1.08M | else { |
2214 | 1.08M | if (m == 0) |
2215 | 0 | break; |
2216 | 1.08M | right = m - 1; |
2217 | 1.08M | } |
2218 | 2.09M | } |
2219 | | |
2220 | | // not found |
2221 | 110k | return 0; |
2222 | 308k | } |
2223 | | |
2224 | | #define GET_REGINFO_ENUM |
2225 | | #include "X86GenRegisterInfo.inc" |
2226 | | |
2227 | | // map internal register id to public register id |
2228 | | static const struct register_map { |
2229 | | unsigned short id; |
2230 | | unsigned short pub_id; |
2231 | | } reg_map [] = { |
2232 | | // first dummy map |
2233 | | { 0, 0 }, |
2234 | | #include "X86MappingReg.inc" |
2235 | | }; |
2236 | | |
2237 | | // return 0 on invalid input, or public register ID otherwise |
2238 | | // NOTE: reg_map is sorted in order of internal register |
2239 | | unsigned short X86_register_map(unsigned short id) |
2240 | 5.13M | { |
2241 | 5.13M | if (id < ARR_SIZE(reg_map)) |
2242 | 5.13M | return reg_map[id].pub_id; |
2243 | | |
2244 | 0 | return 0; |
2245 | 5.13M | } |
2246 | | |
2247 | | /// The post-printer function. Used to fixup flaws in the disassembly information |
2248 | | /// of certain instructions. |
2249 | 2.02M | void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci) { |
2250 | 2.02M | if (!insn || !insn->detail) { |
2251 | 0 | return; |
2252 | 0 | } |
2253 | 2.02M | switch (insn->id) { |
2254 | 2.01M | default: |
2255 | 2.01M | break; |
2256 | 2.01M | case X86_INS_RCL: |
2257 | | // Addmissing 1 immediate |
2258 | 16.0k | if (insn->detail->x86.op_count > 1) { |
2259 | 15.2k | return; |
2260 | 15.2k | } |
2261 | 788 | insn->detail->x86.operands[1].imm = 1; |
2262 | 788 | insn->detail->x86.operands[1].type = X86_OP_IMM; |
2263 | 788 | insn->detail->x86.operands[1].access = CS_AC_READ; |
2264 | 788 | insn->detail->x86.op_count++; |
2265 | 788 | break; |
2266 | 2.02M | } |
2267 | 2.02M | } |
2268 | | |
2269 | | |
2270 | | #endif |