Coverage Report

Created: 2024-08-21 06:24

/src/capstonenext/arch/XCore/XCoreGenDisassemblerTables.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* * XCore Disassembler                                                         *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#include "../../MCInst.h"
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#include "../../LEB128.h"
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// Helper function for extracting fields from encoded instructions.
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#define FieldFromInstruction(fname, InsnType) \
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628k
static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType)*8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XCoreDisassembler.c:fieldFromInstruction_2
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257k
static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType)*8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XCoreDisassembler.c:fieldFromInstruction_4
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static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType)*8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
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static const uint8_t DecoderTable16[] = {
28
/* 0 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
29
/* 3 */       MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115
30
/* 7 */       MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
31
/* 10 */      MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19
32
/* 15 */      MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R
33
/* 19 */      MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27
34
/* 24 */      MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R
35
/* 27 */      MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36
36
/* 32 */      MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r
37
/* 36 */      MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44
38
/* 41 */      MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R
39
/* 44 */      MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52
40
/* 49 */      MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R
41
/* 52 */      MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60
42
/* 57 */      MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R
43
/* 60 */      MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68
44
/* 65 */      MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R
45
/* 68 */      MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77
46
/* 73 */      MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R
47
/* 77 */      MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
48
/* 80 */      MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87
49
/* 84 */      MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r
50
/* 87 */      MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94
51
/* 91 */      MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r
52
/* 94 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
53
/* 97 */      MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104
54
/* 101 */     MCD_OPC_Decode, 111, 2, // Opcode: INITPC_2r
55
/* 104 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111
56
/* 108 */     MCD_OPC_Decode, 105, 2, // Opcode: GETST_2r
57
/* 111 */     MCD_OPC_Decode, 230, 1, 3, // Opcode: STW_2rus
58
/* 115 */     MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233
59
/* 119 */     MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
60
/* 122 */     MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131
61
/* 127 */     MCD_OPC_Decode, 152, 1, 0, // Opcode: LDSPC_0R
62
/* 131 */     MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140
63
/* 136 */     MCD_OPC_Decode, 223, 1, 0, // Opcode: STSPC_0R
64
/* 140 */     MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149
65
/* 145 */     MCD_OPC_Decode, 153, 1, 0, // Opcode: LDSSR_0R
66
/* 149 */     MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158
67
/* 154 */     MCD_OPC_Decode, 224, 1, 0, // Opcode: STSSR_0R
68
/* 158 */     MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167
69
/* 163 */     MCD_OPC_Decode, 222, 1, 0, // Opcode: STSED_0R
70
/* 167 */     MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176
71
/* 172 */     MCD_OPC_Decode, 221, 1, 0, // Opcode: STET_0R
72
/* 176 */     MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184
73
/* 181 */     MCD_OPC_Decode, 95, 0, // Opcode: GETED_0R
74
/* 184 */     MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192
75
/* 189 */     MCD_OPC_Decode, 96, 0, // Opcode: GETET_0R
76
/* 192 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
77
/* 195 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203
78
/* 199 */     MCD_OPC_Decode, 242, 1, 1, // Opcode: WAITET_1R
79
/* 203 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211
80
/* 207 */     MCD_OPC_Decode, 241, 1, 1, // Opcode: WAITEF_1R
81
/* 211 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
82
/* 214 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221
83
/* 218 */     MCD_OPC_Decode, 109, 2, // Opcode: INITDP_2r
84
/* 221 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229
85
/* 225 */     MCD_OPC_Decode, 183, 1, 4, // Opcode: OUTT_2r
86
/* 229 */     MCD_OPC_Decode, 163, 1, 3, // Opcode: LDW_2rus
87
/* 233 */     MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337
88
/* 237 */     MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
89
/* 240 */     MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248
90
/* 245 */     MCD_OPC_Decode, 69, 0, // Opcode: DENTSP_0R
91
/* 248 */     MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256
92
/* 253 */     MCD_OPC_Decode, 73, 0, // Opcode: DRESTSP_0R
93
/* 256 */     MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264
94
/* 261 */     MCD_OPC_Decode, 97, 0, // Opcode: GETID_0R
95
/* 264 */     MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272
96
/* 269 */     MCD_OPC_Decode, 98, 0, // Opcode: GETKEP_0R
97
/* 272 */     MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280
98
/* 277 */     MCD_OPC_Decode, 99, 0, // Opcode: GETKSP_0R
99
/* 280 */     MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289
100
/* 285 */     MCD_OPC_Decode, 151, 1, 0, // Opcode: LDSED_0R
101
/* 289 */     MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298
102
/* 294 */     MCD_OPC_Decode, 149, 1, 0, // Opcode: LDET_0R
103
/* 298 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
104
/* 301 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308
105
/* 305 */     MCD_OPC_Decode, 92, 1, // Opcode: FREER_1r
106
/* 308 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316
107
/* 312 */     MCD_OPC_Decode, 171, 1, 1, // Opcode: MJOIN_1r
108
/* 316 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
109
/* 319 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326
110
/* 323 */     MCD_OPC_Decode, 112, 2, // Opcode: INITSP_2r
111
/* 326 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334
112
/* 330 */     MCD_OPC_Decode, 197, 1, 4, // Opcode: SETD_2r
113
/* 334 */     MCD_OPC_Decode, 23, 5, // Opcode: ADD_3r
114
/* 337 */     MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382
115
/* 341 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
116
/* 344 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352
117
/* 348 */     MCD_OPC_Decode, 240, 1, 1, // Opcode: TSTART_1R
118
/* 352 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360
119
/* 356 */     MCD_OPC_Decode, 174, 1, 1, // Opcode: MSYNC_1r
120
/* 360 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
121
/* 363 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370
122
/* 367 */     MCD_OPC_Decode, 108, 2, // Opcode: INITCP_2r
123
/* 370 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378
124
/* 374 */     MCD_OPC_Decode, 238, 1, 6, // Opcode: TSETMR_2r
125
/* 378 */     MCD_OPC_Decode, 233, 1, 5, // Opcode: SUB_3r
126
/* 382 */     MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416
127
/* 386 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
128
/* 389 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396
129
/* 393 */     MCD_OPC_Decode, 36, 1, // Opcode: BLA_1r
130
/* 396 */     MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403
131
/* 400 */     MCD_OPC_Decode, 30, 1, // Opcode: BAU_1r
132
/* 403 */     MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412
133
/* 409 */     MCD_OPC_Decode, 79, 2, // Opcode: EET_2r
134
/* 412 */     MCD_OPC_Decode, 215, 1, 5, // Opcode: SHL_3r
135
/* 416 */     MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459
136
/* 420 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
137
/* 423 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430
138
/* 427 */     MCD_OPC_Decode, 53, 1, // Opcode: BRU_1r
139
/* 430 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438
140
/* 434 */     MCD_OPC_Decode, 205, 1, 1, // Opcode: SETSP_1r
141
/* 438 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
142
/* 441 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448
143
/* 445 */     MCD_OPC_Decode, 26, 7, // Opcode: ANDNOT_2r
144
/* 448 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455
145
/* 452 */     MCD_OPC_Decode, 78, 2, // Opcode: EEF_2r
146
/* 455 */     MCD_OPC_Decode, 217, 1, 5, // Opcode: SHR_3r
147
/* 459 */     MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504
148
/* 463 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
149
/* 466 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474
150
/* 470 */     MCD_OPC_Decode, 196, 1, 1, // Opcode: SETDP_1r
151
/* 474 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482
152
/* 478 */     MCD_OPC_Decode, 192, 1, 1, // Opcode: SETCP_1r
153
/* 482 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
154
/* 485 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493
155
/* 489 */     MCD_OPC_Decode, 212, 1, 7, // Opcode: SEXT_2r
156
/* 493 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501
157
/* 497 */     MCD_OPC_Decode, 213, 1, 8, // Opcode: SEXT_rus
158
/* 501 */     MCD_OPC_Decode, 86, 5, // Opcode: EQ_3r
159
/* 504 */     MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547
160
/* 508 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
161
/* 511 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518
162
/* 515 */     MCD_OPC_Decode, 70, 1, // Opcode: DGETREG_1r
163
/* 518 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526
164
/* 522 */     MCD_OPC_Decode, 198, 1, 1, // Opcode: SETEV_1r
165
/* 526 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
166
/* 529 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536
167
/* 533 */     MCD_OPC_Decode, 106, 2, // Opcode: GETTS_2r
168
/* 536 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544
169
/* 540 */     MCD_OPC_Decode, 203, 1, 4, // Opcode: SETPT_2r
170
/* 544 */     MCD_OPC_Decode, 27, 5, // Opcode: AND_3r
171
/* 547 */     MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592
172
/* 551 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
173
/* 554 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561
174
/* 558 */     MCD_OPC_Decode, 118, 1, // Opcode: KCALL_1r
175
/* 561 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569
176
/* 565 */     MCD_OPC_Decode, 211, 1, 1, // Opcode: SETV_1r
177
/* 569 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
178
/* 572 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580
179
/* 576 */     MCD_OPC_Decode, 245, 1, 7, // Opcode: ZEXT_2r
180
/* 580 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588
181
/* 584 */     MCD_OPC_Decode, 246, 1, 8, // Opcode: ZEXT_rus
182
/* 588 */     MCD_OPC_Decode, 178, 1, 5, // Opcode: OR_3r
183
/* 592 */     MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636
184
/* 596 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
185
/* 599 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606
186
/* 603 */     MCD_OPC_Decode, 75, 1, // Opcode: ECALLF_1r
187
/* 606 */     MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613
188
/* 610 */     MCD_OPC_Decode, 76, 1, // Opcode: ECALLT_1r
189
/* 613 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
190
/* 616 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624
191
/* 620 */     MCD_OPC_Decode, 179, 1, 2, // Opcode: OUTCT_2r
192
/* 624 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632
193
/* 628 */     MCD_OPC_Decode, 180, 1, 9, // Opcode: OUTCT_rus
194
/* 632 */     MCD_OPC_Decode, 164, 1, 5, // Opcode: LDW_3r
195
/* 636 */     MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659
196
/* 640 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
197
/* 643 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651
198
/* 647 */     MCD_OPC_Decode, 226, 1, 10, // Opcode: STWDP_ru6
199
/* 651 */     MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 1221
200
/* 655 */     MCD_OPC_Decode, 229, 1, 10, // Opcode: STWSP_ru6
201
/* 659 */     MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682
202
/* 663 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
203
/* 666 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674
204
/* 670 */     MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWDP_ru6
205
/* 674 */     MCD_OPC_FilterValue, 1, 31, 2, // Skip to: 1221
206
/* 678 */     MCD_OPC_Decode, 162, 1, 10, // Opcode: LDWSP_ru6
207
/* 682 */     MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705
208
/* 686 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
209
/* 689 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697
210
/* 693 */     MCD_OPC_Decode, 141, 1, 10, // Opcode: LDAWDP_ru6
211
/* 697 */     MCD_OPC_FilterValue, 1, 8, 2, // Skip to: 1221
212
/* 701 */     MCD_OPC_Decode, 146, 1, 10, // Opcode: LDAWSP_ru6
213
/* 705 */     MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728
214
/* 709 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
215
/* 712 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720
216
/* 716 */     MCD_OPC_Decode, 148, 1, 10, // Opcode: LDC_ru6
217
/* 720 */     MCD_OPC_FilterValue, 1, 241, 1, // Skip to: 1221
218
/* 724 */     MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWCP_ru6
219
/* 728 */     MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812
220
/* 732 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
221
/* 735 */     MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773
222
/* 739 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
223
/* 742 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749
224
/* 746 */     MCD_OPC_Decode, 52, 11, // Opcode: BRFU_u6
225
/* 749 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756
226
/* 753 */     MCD_OPC_Decode, 35, 11, // Opcode: BLAT_u6
227
/* 756 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763
228
/* 760 */     MCD_OPC_Decode, 88, 11, // Opcode: EXTDP_u6
229
/* 763 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770
230
/* 767 */     MCD_OPC_Decode, 120, 11, // Opcode: KCALL_u6
231
/* 770 */     MCD_OPC_Decode, 50, 12, // Opcode: BRFT_ru6
232
/* 773 */     MCD_OPC_FilterValue, 1, 188, 1, // Skip to: 1221
233
/* 777 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
234
/* 780 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787
235
/* 784 */     MCD_OPC_Decode, 46, 13, // Opcode: BRBU_u6
236
/* 787 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794
237
/* 791 */     MCD_OPC_Decode, 84, 11, // Opcode: ENTSP_u6
238
/* 794 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801
239
/* 798 */     MCD_OPC_Decode, 90, 11, // Opcode: EXTSP_u6
240
/* 801 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809
241
/* 805 */     MCD_OPC_Decode, 189, 1, 11, // Opcode: RETSP_u6
242
/* 809 */     MCD_OPC_Decode, 44, 14, // Opcode: BRBT_ru6
243
/* 812 */     MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883
244
/* 816 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
245
/* 819 */     MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858
246
/* 823 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
247
/* 826 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833
248
/* 830 */     MCD_OPC_Decode, 64, 11, // Opcode: CLRSR_u6
249
/* 833 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841
250
/* 837 */     MCD_OPC_Decode, 209, 1, 11, // Opcode: SETSR_u6
251
/* 841 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848
252
/* 845 */     MCD_OPC_Decode, 122, 11, // Opcode: KENTSP_u6
253
/* 848 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855
254
/* 852 */     MCD_OPC_Decode, 124, 11, // Opcode: KRESTSP_u6
255
/* 855 */     MCD_OPC_Decode, 48, 12, // Opcode: BRFF_ru6
256
/* 858 */     MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 1221
257
/* 862 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
258
/* 865 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872
259
/* 869 */     MCD_OPC_Decode, 104, 11, // Opcode: GETSR_u6
260
/* 872 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880
261
/* 876 */     MCD_OPC_Decode, 139, 1, 11, // Opcode: LDAWCP_u6
262
/* 880 */     MCD_OPC_Decode, 42, 14, // Opcode: BRBF_ru6
263
/* 883 */     MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925
264
/* 887 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
265
/* 890 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897
266
/* 894 */     MCD_OPC_Decode, 60, 1, // Opcode: CLRPT_1R
267
/* 897 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905
268
/* 901 */     MCD_OPC_Decode, 234, 1, 1, // Opcode: SYNCR_1r
269
/* 905 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
270
/* 908 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915
271
/* 912 */     MCD_OPC_Decode, 102, 9, // Opcode: GETR_rus
272
/* 915 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922
273
/* 919 */     MCD_OPC_Decode, 107, 2, // Opcode: INCT_2r
274
/* 922 */     MCD_OPC_Decode, 127, 5, // Opcode: LD16S_3r
275
/* 925 */     MCD_OPC_FilterValue, 17, 22, 0, // Skip to: 951
276
/* 929 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
277
/* 932 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940
278
/* 936 */     MCD_OPC_Decode, 177, 1, 2, // Opcode: NOT
279
/* 940 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947
280
/* 944 */     MCD_OPC_Decode, 115, 2, // Opcode: INT_2r
281
/* 947 */     MCD_OPC_Decode, 128, 1, 5, // Opcode: LD8U_3r
282
/* 951 */     MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 976
283
/* 955 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
284
/* 958 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 966
285
/* 962 */     MCD_OPC_Decode, 176, 1, 2, // Opcode: NEG
286
/* 966 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 973
287
/* 970 */     MCD_OPC_Decode, 82, 2, // Opcode: ENDIN_2r
288
/* 973 */     MCD_OPC_Decode, 22, 3, // Opcode: ADD_2rus
289
/* 976 */     MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 984
290
/* 980 */     MCD_OPC_Decode, 232, 1, 3, // Opcode: SUB_2rus
291
/* 984 */     MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1011
292
/* 988 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
293
/* 991 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 999
294
/* 995 */     MCD_OPC_Decode, 172, 1, 2, // Opcode: MKMSK_2r
295
/* 999 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1007
296
/* 1003 */    MCD_OPC_Decode, 173, 1, 15, // Opcode: MKMSK_rus
297
/* 1007 */    MCD_OPC_Decode, 214, 1, 16, // Opcode: SHL_2rus
298
/* 1011 */    MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1038
299
/* 1015 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
300
/* 1018 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1026
301
/* 1022 */    MCD_OPC_Decode, 184, 1, 4, // Opcode: OUT_2r
302
/* 1026 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1034
303
/* 1030 */    MCD_OPC_Decode, 182, 1, 7, // Opcode: OUTSHR_2r
304
/* 1034 */    MCD_OPC_Decode, 216, 1, 16, // Opcode: SHR_2rus
305
/* 1038 */    MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1062
306
/* 1042 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
307
/* 1045 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1052
308
/* 1049 */    MCD_OPC_Decode, 116, 2, // Opcode: IN_2r
309
/* 1052 */    MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1059
310
/* 1056 */    MCD_OPC_Decode, 114, 7, // Opcode: INSHR_2r
311
/* 1059 */    MCD_OPC_Decode, 85, 3, // Opcode: EQ_2rus
312
/* 1062 */    MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1089
313
/* 1066 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
314
/* 1069 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1077
315
/* 1073 */    MCD_OPC_Decode, 185, 1, 2, // Opcode: PEEK_2r
316
/* 1077 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1085
317
/* 1081 */    MCD_OPC_Decode, 235, 1, 2, // Opcode: TESTCT_2r
318
/* 1085 */    MCD_OPC_Decode, 239, 1, 17, // Opcode: TSETR_3r
319
/* 1089 */    MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1116
320
/* 1093 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
321
/* 1096 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1104
322
/* 1100 */    MCD_OPC_Decode, 201, 1, 4, // Opcode: SETPSC_2r
323
/* 1104 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1112
324
/* 1108 */    MCD_OPC_Decode, 237, 1, 2, // Opcode: TESTWCT_2r
325
/* 1112 */    MCD_OPC_Decode, 166, 1, 5, // Opcode: LSS_3r
326
/* 1116 */    MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1141
327
/* 1120 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
328
/* 1123 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1130
329
/* 1127 */    MCD_OPC_Decode, 57, 2, // Opcode: CHKCT_2r
330
/* 1130 */    MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1137
331
/* 1134 */    MCD_OPC_Decode, 58, 15, // Opcode: CHKCT_rus
332
/* 1137 */    MCD_OPC_Decode, 168, 1, 5, // Opcode: LSU_3r
333
/* 1141 */    MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1162
334
/* 1145 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
335
/* 1148 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1155
336
/* 1152 */    MCD_OPC_Decode, 40, 18, // Opcode: BLRF_u10
337
/* 1155 */    MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1221
338
/* 1159 */    MCD_OPC_Decode, 38, 19, // Opcode: BLRB_u10
339
/* 1162 */    MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1185
340
/* 1166 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
341
/* 1169 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1177
342
/* 1173 */    MCD_OPC_Decode, 135, 1, 18, // Opcode: LDAPF_u10
343
/* 1177 */    MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1221
344
/* 1181 */    MCD_OPC_Decode, 132, 1, 19, // Opcode: LDAPB_u10
345
/* 1185 */    MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1207
346
/* 1189 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
347
/* 1192 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1199
348
/* 1196 */    MCD_OPC_Decode, 33, 18, // Opcode: BLACP_u10
349
/* 1199 */    MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1221
350
/* 1203 */    MCD_OPC_Decode, 157, 1, 18, // Opcode: LDWCP_u10
351
/* 1207 */    MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1221
352
/* 1211 */    MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1221
353
/* 1217 */    MCD_OPC_Decode, 195, 1, 12, // Opcode: SETC_ru6
354
/* 1221 */    MCD_OPC_Fail,
355
  0
356
};
357
358
static const uint8_t DecoderTable32[] = {
359
/* 0 */       MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
360
/* 3 */       MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96
361
/* 7 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
362
/* 10 */      MCD_OPC_FilterValue, 31, 216, 3, // Skip to: 998
363
/* 14 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
364
/* 17 */      MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31
365
/* 21 */      MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45
366
/* 28 */      MCD_OPC_Decode, 31, 20, // Opcode: BITREV_l2r
367
/* 31 */      MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45
368
/* 35 */      MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45
369
/* 42 */      MCD_OPC_Decode, 56, 20, // Opcode: BYTEREV_l2r
370
/* 45 */      MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56
371
/* 52 */      MCD_OPC_Decode, 231, 1, 21, // Opcode: STW_l3r
372
/* 56 */      MCD_OPC_ExtractField, 20, 7,  // Inst{26-20} ...
373
/* 59 */      MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66
374
/* 63 */      MCD_OPC_Decode, 66, 22, // Opcode: CRC8_l4r
375
/* 66 */      MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74
376
/* 70 */      MCD_OPC_Decode, 170, 1, 23, // Opcode: MACCU_l4r
377
/* 74 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
378
/* 77 */      MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85
379
/* 81 */      MCD_OPC_Decode, 150, 1, 24, // Opcode: LDIVU_l5r
380
/* 85 */      MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92
381
/* 89 */      MCD_OPC_Decode, 126, 24, // Opcode: LADD_l5r
382
/* 92 */      MCD_OPC_Decode, 165, 1, 25, // Opcode: LMUL_l6r
383
/* 96 */      MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186
384
/* 100 */     MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
385
/* 103 */     MCD_OPC_FilterValue, 31, 123, 3, // Skip to: 998
386
/* 107 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
387
/* 110 */     MCD_OPC_FilterValue, 0, 116, 3, // Skip to: 998
388
/* 114 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
389
/* 117 */     MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136
390
/* 121 */     MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156
391
/* 127 */     MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156
392
/* 133 */     MCD_OPC_Decode, 65, 20, // Opcode: CLZ_l2r
393
/* 136 */     MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156
394
/* 140 */     MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156
395
/* 146 */     MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156
396
/* 152 */     MCD_OPC_Decode, 191, 1, 26, // Opcode: SETCLK_l2r
397
/* 156 */     MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172
398
/* 162 */     MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172
399
/* 168 */     MCD_OPC_Decode, 244, 1, 21, // Opcode: XOR_l3r
400
/* 172 */     MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182
401
/* 178 */     MCD_OPC_Decode, 169, 1, 23, // Opcode: MACCS_l4r
402
/* 182 */     MCD_OPC_Decode, 167, 1, 24, // Opcode: LSUB_l5r
403
/* 186 */     MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219
404
/* 190 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
405
/* 193 */     MCD_OPC_FilterValue, 159, 251, 3, 31, 3, // Skip to: 998
406
/* 199 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
407
/* 202 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209
408
/* 206 */     MCD_OPC_Decode, 110, 20, // Opcode: INITLR_l2r
409
/* 209 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216
410
/* 213 */     MCD_OPC_Decode, 101, 20, // Opcode: GETPS_l2r
411
/* 216 */     MCD_OPC_Decode, 29, 21, // Opcode: ASHR_l3r
412
/* 219 */     MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254
413
/* 223 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
414
/* 226 */     MCD_OPC_FilterValue, 159, 251, 3, 254, 2, // Skip to: 998
415
/* 232 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
416
/* 235 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243
417
/* 239 */     MCD_OPC_Decode, 202, 1, 26, // Opcode: SETPS_l2r
418
/* 243 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250
419
/* 247 */     MCD_OPC_Decode, 94, 20, // Opcode: GETD_l2r
420
/* 250 */     MCD_OPC_Decode, 144, 1, 21, // Opcode: LDAWF_l3r
421
/* 254 */     MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290
422
/* 258 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
423
/* 261 */     MCD_OPC_FilterValue, 159, 251, 3, 219, 2, // Skip to: 998
424
/* 267 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
425
/* 270 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278
426
/* 274 */     MCD_OPC_Decode, 236, 1, 20, // Opcode: TESTLCL_l2r
427
/* 278 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286
428
/* 282 */     MCD_OPC_Decode, 210, 1, 26, // Opcode: SETTW_l2r
429
/* 286 */     MCD_OPC_Decode, 137, 1, 21, // Opcode: LDAWB_l3r
430
/* 290 */     MCD_OPC_FilterValue, 5, 32, 0, // Skip to: 326
431
/* 294 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
432
/* 297 */     MCD_OPC_FilterValue, 159, 251, 3, 183, 2, // Skip to: 998
433
/* 303 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
434
/* 306 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314
435
/* 310 */     MCD_OPC_Decode, 204, 1, 26, // Opcode: SETRDY_l2r
436
/* 314 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322
437
/* 318 */     MCD_OPC_Decode, 193, 1, 20, // Opcode: SETC_l2r
438
/* 322 */     MCD_OPC_Decode, 130, 1, 21, // Opcode: LDA16F_l3r
439
/* 326 */     MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 361
440
/* 330 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
441
/* 333 */     MCD_OPC_FilterValue, 159, 251, 3, 147, 2, // Skip to: 998
442
/* 339 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
443
/* 342 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 350
444
/* 346 */     MCD_OPC_Decode, 200, 1, 26, // Opcode: SETN_l2r
445
/* 350 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 357
446
/* 354 */     MCD_OPC_Decode, 100, 20, // Opcode: GETN_l2r
447
/* 357 */     MCD_OPC_Decode, 129, 1, 21, // Opcode: LDA16B_l3r
448
/* 361 */     MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 377
449
/* 365 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 998
450
/* 373 */     MCD_OPC_Decode, 175, 1, 21, // Opcode: MUL_l3r
451
/* 377 */     MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 392
452
/* 381 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 998
453
/* 389 */     MCD_OPC_Decode, 71, 21, // Opcode: DIVS_l3r
454
/* 392 */     MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 407
455
/* 396 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 998
456
/* 404 */     MCD_OPC_Decode, 72, 21, // Opcode: DIVU_l3r
457
/* 407 */     MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 442
458
/* 411 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
459
/* 414 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 428
460
/* 418 */     MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 998
461
/* 424 */     MCD_OPC_Decode, 225, 1, 27, // Opcode: STWDP_lru6
462
/* 428 */     MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 998
463
/* 432 */     MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 998
464
/* 438 */     MCD_OPC_Decode, 228, 1, 27, // Opcode: STWSP_lru6
465
/* 442 */     MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 477
466
/* 446 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
467
/* 449 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 463
468
/* 453 */     MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 998
469
/* 459 */     MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWDP_lru6
470
/* 463 */     MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 998
471
/* 467 */     MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 998
472
/* 473 */     MCD_OPC_Decode, 161, 1, 27, // Opcode: LDWSP_lru6
473
/* 477 */     MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 512
474
/* 481 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
475
/* 484 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 498
476
/* 488 */     MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 998
477
/* 494 */     MCD_OPC_Decode, 140, 1, 27, // Opcode: LDAWDP_lru6
478
/* 498 */     MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 998
479
/* 502 */     MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 998
480
/* 508 */     MCD_OPC_Decode, 145, 1, 27, // Opcode: LDAWSP_lru6
481
/* 512 */     MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 547
482
/* 516 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
483
/* 519 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 533
484
/* 523 */     MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 998
485
/* 529 */     MCD_OPC_Decode, 147, 1, 27, // Opcode: LDC_lru6
486
/* 533 */     MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 998
487
/* 537 */     MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 998
488
/* 543 */     MCD_OPC_Decode, 154, 1, 27, // Opcode: LDWCP_lru6
489
/* 547 */     MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 645
490
/* 551 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
491
/* 554 */     MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 599
492
/* 558 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
493
/* 561 */     MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 998
494
/* 565 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
495
/* 568 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 575
496
/* 572 */     MCD_OPC_Decode, 51, 28, // Opcode: BRFU_lu6
497
/* 575 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 582
498
/* 579 */     MCD_OPC_Decode, 34, 28, // Opcode: BLAT_lu6
499
/* 582 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 589
500
/* 586 */     MCD_OPC_Decode, 87, 28, // Opcode: EXTDP_lu6
501
/* 589 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 596
502
/* 593 */     MCD_OPC_Decode, 119, 28, // Opcode: KCALL_lu6
503
/* 596 */     MCD_OPC_Decode, 49, 29, // Opcode: BRFT_lru6
504
/* 599 */     MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 998
505
/* 603 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
506
/* 606 */     MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 998
507
/* 610 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
508
/* 613 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 620
509
/* 617 */     MCD_OPC_Decode, 45, 30, // Opcode: BRBU_lu6
510
/* 620 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 627
511
/* 624 */     MCD_OPC_Decode, 83, 28, // Opcode: ENTSP_lu6
512
/* 627 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 634
513
/* 631 */     MCD_OPC_Decode, 89, 28, // Opcode: EXTSP_lu6
514
/* 634 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 642
515
/* 638 */     MCD_OPC_Decode, 188, 1, 28, // Opcode: RETSP_lu6
516
/* 642 */     MCD_OPC_Decode, 43, 31, // Opcode: BRBT_lru6
517
/* 645 */     MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 730
518
/* 649 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
519
/* 652 */     MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 698
520
/* 656 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
521
/* 659 */     MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 998
522
/* 663 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
523
/* 666 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 673
524
/* 670 */     MCD_OPC_Decode, 63, 28, // Opcode: CLRSR_lu6
525
/* 673 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 681
526
/* 677 */     MCD_OPC_Decode, 208, 1, 28, // Opcode: SETSR_lu6
527
/* 681 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 688
528
/* 685 */     MCD_OPC_Decode, 121, 28, // Opcode: KENTSP_lu6
529
/* 688 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 695
530
/* 692 */     MCD_OPC_Decode, 123, 28, // Opcode: KRESTSP_lu6
531
/* 695 */     MCD_OPC_Decode, 47, 29, // Opcode: BRFF_lru6
532
/* 698 */     MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 998
533
/* 702 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
534
/* 705 */     MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 998
535
/* 709 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
536
/* 712 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 719
537
/* 716 */     MCD_OPC_Decode, 103, 28, // Opcode: GETSR_lu6
538
/* 719 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 727
539
/* 723 */     MCD_OPC_Decode, 138, 1, 28, // Opcode: LDAWCP_lu6
540
/* 727 */     MCD_OPC_Decode, 41, 31, // Opcode: BRBF_lru6
541
/* 730 */     MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 746
542
/* 734 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 998
543
/* 742 */     MCD_OPC_Decode, 219, 1, 21, // Opcode: ST16_l3r
544
/* 746 */     MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 762
545
/* 750 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 998
546
/* 758 */     MCD_OPC_Decode, 220, 1, 21, // Opcode: ST8_l3r
547
/* 762 */     MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 797
548
/* 766 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
549
/* 769 */     MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 778
550
/* 775 */     MCD_OPC_Decode, 28, 32, // Opcode: ASHR_l2rus
551
/* 778 */     MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 788
552
/* 784 */     MCD_OPC_Decode, 181, 1, 32, // Opcode: OUTPW_l2rus
553
/* 788 */     MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 998
554
/* 794 */     MCD_OPC_Decode, 113, 32, // Opcode: INPW_l2rus
555
/* 797 */     MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 813
556
/* 801 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 998
557
/* 809 */     MCD_OPC_Decode, 143, 1, 33, // Opcode: LDAWF_l2rus
558
/* 813 */     MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 829
559
/* 817 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 998
560
/* 825 */     MCD_OPC_Decode, 136, 1, 33, // Opcode: LDAWB_l2rus
561
/* 829 */     MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 844
562
/* 833 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 998
563
/* 841 */     MCD_OPC_Decode, 67, 34, // Opcode: CRC_l3r
564
/* 844 */     MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 860
565
/* 848 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 998
566
/* 856 */     MCD_OPC_Decode, 186, 1, 21, // Opcode: REMS_l3r
567
/* 860 */     MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 876
568
/* 864 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 998
569
/* 872 */     MCD_OPC_Decode, 187, 1, 21, // Opcode: REMU_l3r
570
/* 876 */     MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 909
571
/* 880 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
572
/* 883 */     MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 896
573
/* 887 */     MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 998
574
/* 893 */     MCD_OPC_Decode, 39, 35, // Opcode: BLRF_lu10
575
/* 896 */     MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 998
576
/* 900 */     MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 998
577
/* 906 */     MCD_OPC_Decode, 37, 36, // Opcode: BLRB_lu10
578
/* 909 */     MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 944
579
/* 913 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
580
/* 916 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 930
581
/* 920 */     MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 998
582
/* 926 */     MCD_OPC_Decode, 133, 1, 35, // Opcode: LDAPF_lu10
583
/* 930 */     MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 998
584
/* 934 */     MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 998
585
/* 940 */     MCD_OPC_Decode, 131, 1, 36, // Opcode: LDAPB_lu10
586
/* 944 */     MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 978
587
/* 948 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
588
/* 951 */     MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 964
589
/* 955 */     MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 998
590
/* 961 */     MCD_OPC_Decode, 32, 35, // Opcode: BLACP_lu10
591
/* 964 */     MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 998
592
/* 968 */     MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 998
593
/* 974 */     MCD_OPC_Decode, 155, 1, 35, // Opcode: LDWCP_lu10
594
/* 978 */     MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 998
595
/* 982 */     MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 998
596
/* 988 */     MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 998
597
/* 994 */     MCD_OPC_Decode, 194, 1, 29, // Opcode: SETC_lru6
598
/* 998 */     MCD_OPC_Fail,
599
  0
600
};
601
602
static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
603
0
{
604
0
  return true;  //llvm_unreachable("Invalid index!");
605
0
}
606
607
#define DecodeToMCInst(fname,fieldname, InsnType) \
608
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
609
84.1k
                uint64_t Address, const void *Decoder) \
610
84.1k
{ \
611
84.1k
  InsnType tmp; \
612
84.1k
  switch (Idx) { \
613
0
  default: \
614
3.16k
  case 0: \
615
3.16k
    return S; \
616
893
  case 1: \
617
893
    tmp = fieldname(insn, 0, 4); \
618
893
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
619
893
    return S; \
620
27.4k
  case 2: \
621
27.4k
    if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
622
27.4k
    return S; \
623
27.4k
  case 3: \
624
1.14k
    if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
625
1.14k
    return S; \
626
5.87k
  case 4: \
627
5.87k
    if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
628
5.87k
    return S; \
629
5.87k
  case 5: \
630
1.67k
    if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
631
1.67k
    return S; \
632
2.41k
  case 6: \
633
2.41k
    if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
634
2.41k
    return S; \
635
7.15k
  case 7: \
636
7.15k
    if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
637
7.15k
    return S; \
638
7.15k
  case 8: \
639
3.84k
    if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
640
3.84k
    return S; \
641
3.84k
  case 9: \
642
2.42k
    if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
643
2.42k
    return S; \
644
8.49k
  case 10: \
645
8.49k
    tmp = fieldname(insn, 6, 4); \
646
8.49k
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
647
8.49k
    tmp = fieldname(insn, 0, 6); \
648
8.49k
    MCOperand_CreateImm0(MI, tmp); \
649
8.49k
    return S; \
650
8.49k
  case 11: \
651
1.77k
    tmp = fieldname(insn, 0, 6); \
652
1.77k
    MCOperand_CreateImm0(MI, tmp); \
653
1.77k
    return S; \
654
8.49k
  case 12: \
655
2.49k
    tmp = fieldname(insn, 6, 4); \
656
2.49k
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
657
2.49k
    tmp = fieldname(insn, 0, 6); \
658
2.49k
    MCOperand_CreateImm0(MI, tmp); \
659
2.49k
    return S; \
660
2.49k
  case 13: \
661
284
    tmp = fieldname(insn, 0, 6); \
662
284
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
663
284
    return S; \
664
1.88k
  case 14: \
665
1.88k
    tmp = fieldname(insn, 6, 4); \
666
1.88k
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
667
1.88k
    tmp = fieldname(insn, 0, 6); \
668
1.88k
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
669
1.88k
    return S; \
670
1.88k
  case 15: \
671
1.46k
    if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
672
1.46k
    return S; \
673
1.46k
  case 16: \
674
0
    if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
675
0
    return S; \
676
0
  case 17: \
677
0
    if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
678
0
    return S; \
679
3.14k
  case 18: \
680
3.14k
    tmp = fieldname(insn, 0, 10); \
681
3.14k
    MCOperand_CreateImm0(MI, tmp); \
682
3.14k
    return S; \
683
1.62k
  case 19: \
684
1.62k
    tmp = fieldname(insn, 0, 10); \
685
1.62k
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
686
1.62k
    return S; \
687
1.62k
  case 20: \
688
1.23k
    if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
689
1.23k
    return S; \
690
1.23k
  case 21: \
691
106
    if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
692
106
    return S; \
693
376
  case 22: \
694
376
    if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
695
376
    return S; \
696
376
  case 23: \
697
353
    if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
698
353
    return S; \
699
1.45k
  case 24: \
700
1.45k
    if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
701
1.45k
    return S; \
702
1.45k
  case 25: \
703
0
    if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
704
0
    return S; \
705
1.41k
  case 26: \
706
1.41k
    if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
707
1.41k
    return S; \
708
1.41k
  case 27: \
709
184
    tmp = fieldname(insn, 22, 4); \
710
184
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
711
184
    tmp = 0; \
712
184
    tmp |= (fieldname(insn, 0, 10) << 6); \
713
184
    tmp |= (fieldname(insn, 16, 6) << 0); \
714
184
    MCOperand_CreateImm0(MI, tmp); \
715
184
    return S; \
716
295
  case 28: \
717
295
    tmp = 0; \
718
295
    tmp |= (fieldname(insn, 0, 10) << 6); \
719
295
    tmp |= (fieldname(insn, 16, 6) << 0); \
720
295
    MCOperand_CreateImm0(MI, tmp); \
721
295
    return S; \
722
184
  case 29: \
723
94
    tmp = fieldname(insn, 22, 4); \
724
94
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
725
94
    tmp = 0; \
726
92
    tmp |= (fieldname(insn, 0, 10) << 6); \
727
92
    tmp |= (fieldname(insn, 16, 6) << 0); \
728
92
    MCOperand_CreateImm0(MI, tmp); \
729
92
    return S; \
730
94
  case 30: \
731
75
    tmp = 0; \
732
75
    tmp |= (fieldname(insn, 0, 10) << 6); \
733
75
    tmp |= (fieldname(insn, 16, 6) << 0); \
734
75
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
735
75
    return S; \
736
468
  case 31: \
737
468
    tmp = fieldname(insn, 22, 4); \
738
468
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
739
468
    tmp = 0; \
740
465
    tmp |= (fieldname(insn, 0, 10) << 6); \
741
465
    tmp |= (fieldname(insn, 16, 6) << 0); \
742
465
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
743
465
    return S; \
744
465
  case 32: \
745
243
    if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
746
243
    return S; \
747
243
  case 33: \
748
90
    if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
749
90
    return S; \
750
90
  case 34: \
751
86
    if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
752
86
    return S; \
753
129
  case 35: \
754
129
    tmp = 0; \
755
129
    tmp |= (fieldname(insn, 0, 10) << 10); \
756
129
    tmp |= (fieldname(insn, 16, 10) << 0); \
757
129
    MCOperand_CreateImm0(MI, tmp); \
758
129
    return S; \
759
340
  case 36: \
760
340
    tmp = 0; \
761
340
    tmp |= (fieldname(insn, 0, 10) << 10); \
762
340
    tmp |= (fieldname(insn, 16, 10) << 0); \
763
340
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
764
340
    return S; \
765
84.1k
  } \
766
84.1k
} 
XCoreDisassembler.c:decodeToMCInst_2
Line
Count
Source
609
77.2k
                uint64_t Address, const void *Decoder) \
610
77.2k
{ \
611
77.2k
  InsnType tmp; \
612
77.2k
  switch (Idx) { \
613
0
  default: \
614
3.16k
  case 0: \
615
3.16k
    return S; \
616
893
  case 1: \
617
893
    tmp = fieldname(insn, 0, 4); \
618
893
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
619
893
    return S; \
620
27.4k
  case 2: \
621
27.4k
    if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
622
27.4k
    return S; \
623
27.4k
  case 3: \
624
1.14k
    if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
625
1.14k
    return S; \
626
5.87k
  case 4: \
627
5.87k
    if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
628
5.87k
    return S; \
629
5.87k
  case 5: \
630
1.67k
    if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
631
1.67k
    return S; \
632
2.41k
  case 6: \
633
2.41k
    if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
634
2.41k
    return S; \
635
7.15k
  case 7: \
636
7.15k
    if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
637
7.15k
    return S; \
638
7.15k
  case 8: \
639
3.84k
    if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
640
3.84k
    return S; \
641
3.84k
  case 9: \
642
2.42k
    if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
643
2.42k
    return S; \
644
8.49k
  case 10: \
645
8.49k
    tmp = fieldname(insn, 6, 4); \
646
8.49k
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
647
8.49k
    tmp = fieldname(insn, 0, 6); \
648
8.49k
    MCOperand_CreateImm0(MI, tmp); \
649
8.49k
    return S; \
650
8.49k
  case 11: \
651
1.77k
    tmp = fieldname(insn, 0, 6); \
652
1.77k
    MCOperand_CreateImm0(MI, tmp); \
653
1.77k
    return S; \
654
8.49k
  case 12: \
655
2.49k
    tmp = fieldname(insn, 6, 4); \
656
2.49k
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
657
2.49k
    tmp = fieldname(insn, 0, 6); \
658
2.49k
    MCOperand_CreateImm0(MI, tmp); \
659
2.49k
    return S; \
660
2.49k
  case 13: \
661
284
    tmp = fieldname(insn, 0, 6); \
662
284
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
663
284
    return S; \
664
1.88k
  case 14: \
665
1.88k
    tmp = fieldname(insn, 6, 4); \
666
1.88k
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
667
1.88k
    tmp = fieldname(insn, 0, 6); \
668
1.88k
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
669
1.88k
    return S; \
670
1.88k
  case 15: \
671
1.46k
    if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
672
1.46k
    return S; \
673
1.46k
  case 16: \
674
0
    if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
675
0
    return S; \
676
0
  case 17: \
677
0
    if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
678
0
    return S; \
679
3.14k
  case 18: \
680
3.14k
    tmp = fieldname(insn, 0, 10); \
681
3.14k
    MCOperand_CreateImm0(MI, tmp); \
682
3.14k
    return S; \
683
1.62k
  case 19: \
684
1.62k
    tmp = fieldname(insn, 0, 10); \
685
1.62k
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
686
1.62k
    return S; \
687
1.62k
  case 20: \
688
0
    if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
689
0
    return S; \
690
0
  case 21: \
691
0
    if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
692
0
    return S; \
693
0
  case 22: \
694
0
    if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
695
0
    return S; \
696
0
  case 23: \
697
0
    if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
698
0
    return S; \
699
0
  case 24: \
700
0
    if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
701
0
    return S; \
702
0
  case 25: \
703
0
    if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
704
0
    return S; \
705
0
  case 26: \
706
0
    if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
707
0
    return S; \
708
0
  case 27: \
709
0
    tmp = fieldname(insn, 22, 4); \
710
0
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
711
0
    tmp = 0; \
712
0
    tmp |= (fieldname(insn, 0, 10) << 6); \
713
0
    tmp |= (fieldname(insn, 16, 6) << 0); \
714
0
    MCOperand_CreateImm0(MI, tmp); \
715
0
    return S; \
716
0
  case 28: \
717
0
    tmp = 0; \
718
0
    tmp |= (fieldname(insn, 0, 10) << 6); \
719
0
    tmp |= (fieldname(insn, 16, 6) << 0); \
720
0
    MCOperand_CreateImm0(MI, tmp); \
721
0
    return S; \
722
0
  case 29: \
723
0
    tmp = fieldname(insn, 22, 4); \
724
0
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
725
0
    tmp = 0; \
726
0
    tmp |= (fieldname(insn, 0, 10) << 6); \
727
0
    tmp |= (fieldname(insn, 16, 6) << 0); \
728
0
    MCOperand_CreateImm0(MI, tmp); \
729
0
    return S; \
730
0
  case 30: \
731
0
    tmp = 0; \
732
0
    tmp |= (fieldname(insn, 0, 10) << 6); \
733
0
    tmp |= (fieldname(insn, 16, 6) << 0); \
734
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
735
0
    return S; \
736
0
  case 31: \
737
0
    tmp = fieldname(insn, 22, 4); \
738
0
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
739
0
    tmp = 0; \
740
0
    tmp |= (fieldname(insn, 0, 10) << 6); \
741
0
    tmp |= (fieldname(insn, 16, 6) << 0); \
742
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
743
0
    return S; \
744
0
  case 32: \
745
0
    if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
746
0
    return S; \
747
0
  case 33: \
748
0
    if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
749
0
    return S; \
750
0
  case 34: \
751
0
    if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
752
0
    return S; \
753
0
  case 35: \
754
0
    tmp = 0; \
755
0
    tmp |= (fieldname(insn, 0, 10) << 10); \
756
0
    tmp |= (fieldname(insn, 16, 10) << 0); \
757
0
    MCOperand_CreateImm0(MI, tmp); \
758
0
    return S; \
759
0
  case 36: \
760
0
    tmp = 0; \
761
0
    tmp |= (fieldname(insn, 0, 10) << 10); \
762
0
    tmp |= (fieldname(insn, 16, 10) << 0); \
763
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
764
0
    return S; \
765
77.2k
  } \
766
77.2k
} 
XCoreDisassembler.c:decodeToMCInst_4
Line
Count
Source
609
6.93k
                uint64_t Address, const void *Decoder) \
610
6.93k
{ \
611
6.93k
  InsnType tmp; \
612
6.93k
  switch (Idx) { \
613
0
  default: \
614
0
  case 0: \
615
0
    return S; \
616
0
  case 1: \
617
0
    tmp = fieldname(insn, 0, 4); \
618
0
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
619
0
    return S; \
620
0
  case 2: \
621
0
    if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
622
0
    return S; \
623
0
  case 3: \
624
0
    if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
625
0
    return S; \
626
0
  case 4: \
627
0
    if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
628
0
    return S; \
629
0
  case 5: \
630
0
    if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
631
0
    return S; \
632
0
  case 6: \
633
0
    if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
634
0
    return S; \
635
0
  case 7: \
636
0
    if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
637
0
    return S; \
638
0
  case 8: \
639
0
    if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
640
0
    return S; \
641
0
  case 9: \
642
0
    if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
643
0
    return S; \
644
0
  case 10: \
645
0
    tmp = fieldname(insn, 6, 4); \
646
0
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
647
0
    tmp = fieldname(insn, 0, 6); \
648
0
    MCOperand_CreateImm0(MI, tmp); \
649
0
    return S; \
650
0
  case 11: \
651
0
    tmp = fieldname(insn, 0, 6); \
652
0
    MCOperand_CreateImm0(MI, tmp); \
653
0
    return S; \
654
0
  case 12: \
655
0
    tmp = fieldname(insn, 6, 4); \
656
0
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
657
0
    tmp = fieldname(insn, 0, 6); \
658
0
    MCOperand_CreateImm0(MI, tmp); \
659
0
    return S; \
660
0
  case 13: \
661
0
    tmp = fieldname(insn, 0, 6); \
662
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
663
0
    return S; \
664
0
  case 14: \
665
0
    tmp = fieldname(insn, 6, 4); \
666
0
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
667
0
    tmp = fieldname(insn, 0, 6); \
668
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
669
0
    return S; \
670
0
  case 15: \
671
0
    if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
672
0
    return S; \
673
0
  case 16: \
674
0
    if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
675
0
    return S; \
676
0
  case 17: \
677
0
    if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
678
0
    return S; \
679
0
  case 18: \
680
0
    tmp = fieldname(insn, 0, 10); \
681
0
    MCOperand_CreateImm0(MI, tmp); \
682
0
    return S; \
683
0
  case 19: \
684
0
    tmp = fieldname(insn, 0, 10); \
685
0
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
686
0
    return S; \
687
1.23k
  case 20: \
688
1.23k
    if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
689
1.23k
    return S; \
690
1.23k
  case 21: \
691
106
    if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
692
106
    return S; \
693
376
  case 22: \
694
376
    if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
695
376
    return S; \
696
376
  case 23: \
697
353
    if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
698
353
    return S; \
699
1.45k
  case 24: \
700
1.45k
    if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
701
1.45k
    return S; \
702
1.45k
  case 25: \
703
0
    if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
704
0
    return S; \
705
1.41k
  case 26: \
706
1.41k
    if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
707
1.41k
    return S; \
708
1.41k
  case 27: \
709
184
    tmp = fieldname(insn, 22, 4); \
710
184
    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
711
184
    tmp = 0; \
712
184
    tmp |= (fieldname(insn, 0, 10) << 6); \
713
184
    tmp |= (fieldname(insn, 16, 6) << 0); \
714
184
    MCOperand_CreateImm0(MI, tmp); \
715
184
    return S; \
716
295
  case 28: \
717
295
    tmp = 0; \
718
295
    tmp |= (fieldname(insn, 0, 10) << 6); \
719
295
    tmp |= (fieldname(insn, 16, 6) << 0); \
720
295
    MCOperand_CreateImm0(MI, tmp); \
721
295
    return S; \
722
184
  case 29: \
723
94
    tmp = fieldname(insn, 22, 4); \
724
94
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
725
94
    tmp = 0; \
726
92
    tmp |= (fieldname(insn, 0, 10) << 6); \
727
92
    tmp |= (fieldname(insn, 16, 6) << 0); \
728
92
    MCOperand_CreateImm0(MI, tmp); \
729
92
    return S; \
730
94
  case 30: \
731
75
    tmp = 0; \
732
75
    tmp |= (fieldname(insn, 0, 10) << 6); \
733
75
    tmp |= (fieldname(insn, 16, 6) << 0); \
734
75
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
735
75
    return S; \
736
468
  case 31: \
737
468
    tmp = fieldname(insn, 22, 4); \
738
468
    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
739
468
    tmp = 0; \
740
465
    tmp |= (fieldname(insn, 0, 10) << 6); \
741
465
    tmp |= (fieldname(insn, 16, 6) << 0); \
742
465
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
743
465
    return S; \
744
465
  case 32: \
745
243
    if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
746
243
    return S; \
747
243
  case 33: \
748
90
    if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
749
90
    return S; \
750
90
  case 34: \
751
86
    if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
752
86
    return S; \
753
129
  case 35: \
754
129
    tmp = 0; \
755
129
    tmp |= (fieldname(insn, 0, 10) << 10); \
756
129
    tmp |= (fieldname(insn, 16, 10) << 0); \
757
129
    MCOperand_CreateImm0(MI, tmp); \
758
129
    return S; \
759
340
  case 36: \
760
340
    tmp = 0; \
761
340
    tmp |= (fieldname(insn, 0, 10) << 10); \
762
340
    tmp |= (fieldname(insn, 16, 10) << 0); \
763
340
    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
764
340
    return S; \
765
6.93k
  } \
766
6.93k
} 
767
768
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
769
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
770
91.6k
           InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
771
91.6k
{ \
772
91.6k
  uint64_t Bits = getFeatureBits(feature); \
773
91.6k
  const uint8_t *Ptr = DecodeTable; \
774
91.6k
  uint32_t CurFieldValue = 0, ExpectedValue; \
775
91.6k
  DecodeStatus S = MCDisassembler_Success; \
776
91.6k
  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
777
91.6k
  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
778
91.6k
  bool Pred, Fail; \
779
1.88M
  for (;;) { \
780
1.88M
    switch (*Ptr) { \
781
0
    default: \
782
0
      return MCDisassembler_Fail; \
783
244k
    case MCD_OPC_ExtractField: { \
784
244k
      Start = *++Ptr; \
785
244k
      Len = *++Ptr; \
786
244k
      ++Ptr; \
787
244k
      CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
788
244k
      break; \
789
0
    } \
790
1.53M
    case MCD_OPC_FilterValue: { \
791
1.53M
      Val = (InsnType)decodeULEB128(++Ptr, &Len); \
792
1.53M
      Ptr += Len; \
793
1.53M
      NumToSkip = *Ptr++; \
794
1.53M
      NumToSkip |= (*Ptr++) << 8; \
795
1.53M
      if (Val != CurFieldValue) \
796
1.53M
        Ptr += NumToSkip; \
797
1.53M
      break; \
798
0
    } \
799
11.1k
    case MCD_OPC_CheckField: { \
800
11.1k
      Start = *++Ptr; \
801
11.1k
      Len = *++Ptr; \
802
11.1k
      FieldValue = fieldname(insn, Start, Len); \
803
11.1k
      ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
804
11.1k
      Ptr += Len; \
805
11.1k
      NumToSkip = *Ptr++; \
806
11.1k
      NumToSkip |= (*Ptr++) << 8; \
807
11.1k
      if (ExpectedValue != FieldValue) \
808
11.1k
        Ptr += NumToSkip; \
809
11.1k
      break; \
810
0
    } \
811
0
    case MCD_OPC_CheckPredicate: { \
812
0
      PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
813
0
      Ptr += Len; \
814
0
      NumToSkip = *Ptr++; \
815
0
      NumToSkip |= (*Ptr++) << 8; \
816
0
      Pred = checkDecoderPredicate(PIdx, Bits); \
817
0
      if (!Pred) \
818
0
        Ptr += NumToSkip; \
819
0
      (void)Pred; \
820
0
      break; \
821
0
    } \
822
84.1k
    case MCD_OPC_Decode: { \
823
84.1k
      Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
824
84.1k
      Ptr += Len; \
825
84.1k
      DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
826
84.1k
      Ptr += Len; \
827
84.1k
      MCInst_setOpcode(MI, Opc); \
828
84.1k
      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
829
0
    } \
830
0
    case MCD_OPC_SoftFail: { \
831
0
      PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
832
0
      Ptr += Len; \
833
0
      NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
834
0
      Ptr += Len; \
835
0
      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
836
0
      if (Fail) \
837
0
        S = MCDisassembler_SoftFail; \
838
0
      break; \
839
0
    } \
840
7.47k
    case MCD_OPC_Fail: { \
841
7.47k
      return MCDisassembler_Fail; \
842
0
    } \
843
1.88M
    } \
844
1.88M
  } \
845
91.6k
}
XCoreDisassembler.c:decodeInstruction_2
Line
Count
Source
770
84.4k
           InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
771
84.4k
{ \
772
84.4k
  uint64_t Bits = getFeatureBits(feature); \
773
84.4k
  const uint8_t *Ptr = DecodeTable; \
774
84.4k
  uint32_t CurFieldValue = 0, ExpectedValue; \
775
84.4k
  DecodeStatus S = MCDisassembler_Success; \
776
84.4k
  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
777
84.4k
  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
778
84.4k
  bool Pred, Fail; \
779
1.76M
  for (;;) { \
780
1.76M
    switch (*Ptr) { \
781
0
    default: \
782
0
      return MCDisassembler_Fail; \
783
220k
    case MCD_OPC_ExtractField: { \
784
220k
      Start = *++Ptr; \
785
220k
      Len = *++Ptr; \
786
220k
      ++Ptr; \
787
220k
      CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
788
220k
      break; \
789
0
    } \
790
1.45M
    case MCD_OPC_FilterValue: { \
791
1.45M
      Val = (InsnType)decodeULEB128(++Ptr, &Len); \
792
1.45M
      Ptr += Len; \
793
1.45M
      NumToSkip = *Ptr++; \
794
1.45M
      NumToSkip |= (*Ptr++) << 8; \
795
1.45M
      if (Val != CurFieldValue) \
796
1.45M
        Ptr += NumToSkip; \
797
1.45M
      break; \
798
0
    } \
799
3.54k
    case MCD_OPC_CheckField: { \
800
3.54k
      Start = *++Ptr; \
801
3.54k
      Len = *++Ptr; \
802
3.54k
      FieldValue = fieldname(insn, Start, Len); \
803
3.54k
      ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
804
3.54k
      Ptr += Len; \
805
3.54k
      NumToSkip = *Ptr++; \
806
3.54k
      NumToSkip |= (*Ptr++) << 8; \
807
3.54k
      if (ExpectedValue != FieldValue) \
808
3.54k
        Ptr += NumToSkip; \
809
3.54k
      break; \
810
0
    } \
811
0
    case MCD_OPC_CheckPredicate: { \
812
0
      PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
813
0
      Ptr += Len; \
814
0
      NumToSkip = *Ptr++; \
815
0
      NumToSkip |= (*Ptr++) << 8; \
816
0
      Pred = checkDecoderPredicate(PIdx, Bits); \
817
0
      if (!Pred) \
818
0
        Ptr += NumToSkip; \
819
0
      (void)Pred; \
820
0
      break; \
821
0
    } \
822
77.2k
    case MCD_OPC_Decode: { \
823
77.2k
      Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
824
77.2k
      Ptr += Len; \
825
77.2k
      DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
826
77.2k
      Ptr += Len; \
827
77.2k
      MCInst_setOpcode(MI, Opc); \
828
77.2k
      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
829
0
    } \
830
0
    case MCD_OPC_SoftFail: { \
831
0
      PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
832
0
      Ptr += Len; \
833
0
      NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
834
0
      Ptr += Len; \
835
0
      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
836
0
      if (Fail) \
837
0
        S = MCDisassembler_SoftFail; \
838
0
      break; \
839
0
    } \
840
7.20k
    case MCD_OPC_Fail: { \
841
7.20k
      return MCDisassembler_Fail; \
842
0
    } \
843
1.76M
    } \
844
1.76M
  } \
845
84.4k
}
XCoreDisassembler.c:decodeInstruction_4
Line
Count
Source
770
7.20k
           InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
771
7.20k
{ \
772
7.20k
  uint64_t Bits = getFeatureBits(feature); \
773
7.20k
  const uint8_t *Ptr = DecodeTable; \
774
7.20k
  uint32_t CurFieldValue = 0, ExpectedValue; \
775
7.20k
  DecodeStatus S = MCDisassembler_Success; \
776
7.20k
  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
777
7.20k
  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
778
7.20k
  bool Pred, Fail; \
779
119k
  for (;;) { \
780
119k
    switch (*Ptr) { \
781
0
    default: \
782
0
      return MCDisassembler_Fail; \
783
24.2k
    case MCD_OPC_ExtractField: { \
784
24.2k
      Start = *++Ptr; \
785
24.2k
      Len = *++Ptr; \
786
24.2k
      ++Ptr; \
787
24.2k
      CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
788
24.2k
      break; \
789
0
    } \
790
80.7k
    case MCD_OPC_FilterValue: { \
791
80.7k
      Val = (InsnType)decodeULEB128(++Ptr, &Len); \
792
80.7k
      Ptr += Len; \
793
80.7k
      NumToSkip = *Ptr++; \
794
80.7k
      NumToSkip |= (*Ptr++) << 8; \
795
80.7k
      if (Val != CurFieldValue) \
796
80.7k
        Ptr += NumToSkip; \
797
80.7k
      break; \
798
0
    } \
799
7.59k
    case MCD_OPC_CheckField: { \
800
7.59k
      Start = *++Ptr; \
801
7.59k
      Len = *++Ptr; \
802
7.59k
      FieldValue = fieldname(insn, Start, Len); \
803
7.59k
      ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
804
7.59k
      Ptr += Len; \
805
7.59k
      NumToSkip = *Ptr++; \
806
7.59k
      NumToSkip |= (*Ptr++) << 8; \
807
7.59k
      if (ExpectedValue != FieldValue) \
808
7.59k
        Ptr += NumToSkip; \
809
7.59k
      break; \
810
0
    } \
811
0
    case MCD_OPC_CheckPredicate: { \
812
0
      PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
813
0
      Ptr += Len; \
814
0
      NumToSkip = *Ptr++; \
815
0
      NumToSkip |= (*Ptr++) << 8; \
816
0
      Pred = checkDecoderPredicate(PIdx, Bits); \
817
0
      if (!Pred) \
818
0
        Ptr += NumToSkip; \
819
0
      (void)Pred; \
820
0
      break; \
821
0
    } \
822
6.93k
    case MCD_OPC_Decode: { \
823
6.93k
      Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
824
6.93k
      Ptr += Len; \
825
6.93k
      DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
826
6.93k
      Ptr += Len; \
827
6.93k
      MCInst_setOpcode(MI, Opc); \
828
6.93k
      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
829
0
    } \
830
0
    case MCD_OPC_SoftFail: { \
831
0
      PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
832
0
      Ptr += Len; \
833
0
      NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
834
0
      Ptr += Len; \
835
0
      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
836
0
      if (Fail) \
837
0
        S = MCDisassembler_SoftFail; \
838
0
      break; \
839
0
    } \
840
268
    case MCD_OPC_Fail: { \
841
268
      return MCDisassembler_Fail; \
842
0
    } \
843
119k
    } \
844
119k
  } \
845
7.20k
}
846
847
848
FieldFromInstruction(fieldFromInstruction_2, uint16_t)
849
DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
850
DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
851
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
852
DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
853
DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)