/src/capstonev5/arch/ARM/ARMBaseInfo.h
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1 | | //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains small standalone helper functions and enum definitions for |
11 | | // the ARM target useful for the compiler back-end and the MC libraries. |
12 | | // As such, it deliberately does not include references to LLVM core |
13 | | // code gen types, passes, etc.. |
14 | | // |
15 | | //===----------------------------------------------------------------------===// |
16 | | |
17 | | /* Capstone Disassembly Engine */ |
18 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
19 | | |
20 | | #ifndef CS_ARMBASEINFO_H |
21 | | #define CS_ARMBASEINFO_H |
22 | | |
23 | | #include "capstone/arm.h" |
24 | | |
25 | | // Defines symbolic names for ARM registers. This defines a mapping from |
26 | | // register name to register number. |
27 | | // |
28 | | #define GET_REGINFO_ENUM |
29 | | #include "ARMGenRegisterInfo.inc" |
30 | | |
31 | | // Enums corresponding to ARM condition codes |
32 | | // The CondCodes constants map directly to the 4-bit encoding of the |
33 | | // condition field for predicated instructions. |
34 | | typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) |
35 | | ARMCC_EQ, // Equal Equal |
36 | | ARMCC_NE, // Not equal Not equal, or unordered |
37 | | ARMCC_HS, // Carry set >, ==, or unordered |
38 | | ARMCC_LO, // Carry clear Less than |
39 | | ARMCC_MI, // Minus, negative Less than |
40 | | ARMCC_PL, // Plus, positive or zero >, ==, or unordered |
41 | | ARMCC_VS, // Overflow Unordered |
42 | | ARMCC_VC, // No overflow Not unordered |
43 | | ARMCC_HI, // Unsigned higher Greater than, or unordered |
44 | | ARMCC_LS, // Unsigned lower or same Less than or equal |
45 | | ARMCC_GE, // Greater than or equal Greater than or equal |
46 | | ARMCC_LT, // Less than Less than, or unordered |
47 | | ARMCC_GT, // Greater than Greater than |
48 | | ARMCC_LE, // Less than or equal <, ==, or unordered |
49 | | ARMCC_AL // Always (unconditional) Always (unconditional) |
50 | | } ARMCC_CondCodes; |
51 | | |
52 | | inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) |
53 | 0 | { |
54 | 0 | switch (CC) { |
55 | 0 | case ARMCC_EQ: return ARMCC_NE; |
56 | 0 | case ARMCC_NE: return ARMCC_EQ; |
57 | 0 | case ARMCC_HS: return ARMCC_LO; |
58 | 0 | case ARMCC_LO: return ARMCC_HS; |
59 | 0 | case ARMCC_MI: return ARMCC_PL; |
60 | 0 | case ARMCC_PL: return ARMCC_MI; |
61 | 0 | case ARMCC_VS: return ARMCC_VC; |
62 | 0 | case ARMCC_VC: return ARMCC_VS; |
63 | 0 | case ARMCC_HI: return ARMCC_LS; |
64 | 0 | case ARMCC_LS: return ARMCC_HI; |
65 | 0 | case ARMCC_GE: return ARMCC_LT; |
66 | 0 | case ARMCC_LT: return ARMCC_GE; |
67 | 0 | case ARMCC_GT: return ARMCC_LE; |
68 | 0 | case ARMCC_LE: return ARMCC_GT; |
69 | 0 | default: return ARMCC_AL; |
70 | 0 | } |
71 | 0 | } Unexecuted instantiation: ARMDisassembler.c:ARMCC_getOppositeCondition Unexecuted instantiation: ARMInstPrinter.c:ARMCC_getOppositeCondition |
72 | | |
73 | | inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) |
74 | 170k | { |
75 | 170k | switch (CC) { |
76 | 31.0k | case ARMCC_EQ: return "eq"; |
77 | 13.5k | case ARMCC_NE: return "ne"; |
78 | 9.83k | case ARMCC_HS: return "hs"; |
79 | 10.4k | case ARMCC_LO: return "lo"; |
80 | 12.0k | case ARMCC_MI: return "mi"; |
81 | 6.81k | case ARMCC_PL: return "pl"; |
82 | 9.70k | case ARMCC_VS: return "vs"; |
83 | 8.67k | case ARMCC_VC: return "vc"; |
84 | 13.1k | case ARMCC_HI: return "hi"; |
85 | 6.78k | case ARMCC_LS: return "ls"; |
86 | 6.98k | case ARMCC_GE: return "ge"; |
87 | 18.0k | case ARMCC_LT: return "lt"; |
88 | 8.06k | case ARMCC_GT: return "gt"; |
89 | 14.1k | case ARMCC_LE: return "le"; |
90 | 1.04k | case ARMCC_AL: return "al"; |
91 | 0 | default: return ""; |
92 | 170k | } |
93 | 170k | } Unexecuted instantiation: ARMDisassembler.c:ARMCC_ARMCondCodeToString ARMInstPrinter.c:ARMCC_ARMCondCodeToString Line | Count | Source | 74 | 170k | { | 75 | 170k | switch (CC) { | 76 | 31.0k | case ARMCC_EQ: return "eq"; | 77 | 13.5k | case ARMCC_NE: return "ne"; | 78 | 9.83k | case ARMCC_HS: return "hs"; | 79 | 10.4k | case ARMCC_LO: return "lo"; | 80 | 12.0k | case ARMCC_MI: return "mi"; | 81 | 6.81k | case ARMCC_PL: return "pl"; | 82 | 9.70k | case ARMCC_VS: return "vs"; | 83 | 8.67k | case ARMCC_VC: return "vc"; | 84 | 13.1k | case ARMCC_HI: return "hi"; | 85 | 6.78k | case ARMCC_LS: return "ls"; | 86 | 6.98k | case ARMCC_GE: return "ge"; | 87 | 18.0k | case ARMCC_LT: return "lt"; | 88 | 8.06k | case ARMCC_GT: return "gt"; | 89 | 14.1k | case ARMCC_LE: return "le"; | 90 | 1.04k | case ARMCC_AL: return "al"; | 91 | 0 | default: return ""; | 92 | 170k | } | 93 | 170k | } |
|
94 | | |
95 | | inline static const char *ARM_PROC_IFlagsToString(unsigned val) |
96 | 434 | { |
97 | 434 | switch (val) { |
98 | 130 | case ARM_CPSFLAG_F: return "f"; |
99 | 133 | case ARM_CPSFLAG_I: return "i"; |
100 | 171 | case ARM_CPSFLAG_A: return "a"; |
101 | 0 | default: return ""; |
102 | 434 | } |
103 | 434 | } Unexecuted instantiation: ARMDisassembler.c:ARM_PROC_IFlagsToString ARMInstPrinter.c:ARM_PROC_IFlagsToString Line | Count | Source | 96 | 434 | { | 97 | 434 | switch (val) { | 98 | 130 | case ARM_CPSFLAG_F: return "f"; | 99 | 133 | case ARM_CPSFLAG_I: return "i"; | 100 | 171 | case ARM_CPSFLAG_A: return "a"; | 101 | 0 | default: return ""; | 102 | 434 | } | 103 | 434 | } |
|
104 | | |
105 | | inline static const char *ARM_PROC_IModToString(unsigned val) |
106 | 470 | { |
107 | 470 | switch (val) { |
108 | 366 | case ARM_CPSMODE_IE: return "ie"; |
109 | 104 | case ARM_CPSMODE_ID: return "id"; |
110 | 0 | default: return ""; |
111 | 470 | } |
112 | 470 | } Unexecuted instantiation: ARMDisassembler.c:ARM_PROC_IModToString ARMInstPrinter.c:ARM_PROC_IModToString Line | Count | Source | 106 | 470 | { | 107 | 470 | switch (val) { | 108 | 366 | case ARM_CPSMODE_IE: return "ie"; | 109 | 104 | case ARM_CPSMODE_ID: return "id"; | 110 | 0 | default: return ""; | 111 | 470 | } | 112 | 470 | } |
|
113 | | |
114 | | inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) |
115 | 1.35k | { |
116 | | // TODO: add details |
117 | 1.35k | switch (val + 1) { |
118 | 0 | default: return "BUGBUG"; |
119 | 26 | case ARM_MB_SY: return "sy"; |
120 | 179 | case ARM_MB_ST: return "st"; |
121 | 444 | case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; |
122 | 76 | case ARM_MB_RESERVED_12: return "#0xc"; |
123 | 27 | case ARM_MB_ISH: return "ish"; |
124 | 11 | case ARM_MB_ISHST: return "ishst"; |
125 | 32 | case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9"; |
126 | 53 | case ARM_MB_RESERVED_8: return "#8"; |
127 | 49 | case ARM_MB_NSH: return "nsh"; |
128 | 120 | case ARM_MB_NSHST: return "nshst"; |
129 | 87 | case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5"; |
130 | 84 | case ARM_MB_RESERVED_4: return "#4"; |
131 | 62 | case ARM_MB_OSH: return "osh"; |
132 | 35 | case ARM_MB_OSHST: return "oshst"; |
133 | 46 | case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1"; |
134 | 19 | case ARM_MB_RESERVED_0: return "#0"; |
135 | 1.35k | } |
136 | 1.35k | } Unexecuted instantiation: ARMDisassembler.c:ARM_MB_MemBOptToString ARMInstPrinter.c:ARM_MB_MemBOptToString Line | Count | Source | 115 | 1.35k | { | 116 | | // TODO: add details | 117 | 1.35k | switch (val + 1) { | 118 | 0 | default: return "BUGBUG"; | 119 | 26 | case ARM_MB_SY: return "sy"; | 120 | 179 | case ARM_MB_ST: return "st"; | 121 | 444 | case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; | 122 | 76 | case ARM_MB_RESERVED_12: return "#0xc"; | 123 | 27 | case ARM_MB_ISH: return "ish"; | 124 | 11 | case ARM_MB_ISHST: return "ishst"; | 125 | 32 | case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9"; | 126 | 53 | case ARM_MB_RESERVED_8: return "#8"; | 127 | 49 | case ARM_MB_NSH: return "nsh"; | 128 | 120 | case ARM_MB_NSHST: return "nshst"; | 129 | 87 | case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5"; | 130 | 84 | case ARM_MB_RESERVED_4: return "#4"; | 131 | 62 | case ARM_MB_OSH: return "osh"; | 132 | 35 | case ARM_MB_OSHST: return "oshst"; | 133 | 46 | case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1"; | 134 | 19 | case ARM_MB_RESERVED_0: return "#0"; | 135 | 1.35k | } | 136 | 1.35k | } |
|
137 | | |
138 | | enum ARM_ISB_InstSyncBOpt { |
139 | | ARM_ISB_RESERVED_0 = 0, |
140 | | ARM_ISB_RESERVED_1 = 1, |
141 | | ARM_ISB_RESERVED_2 = 2, |
142 | | ARM_ISB_RESERVED_3 = 3, |
143 | | ARM_ISB_RESERVED_4 = 4, |
144 | | ARM_ISB_RESERVED_5 = 5, |
145 | | ARM_ISB_RESERVED_6 = 6, |
146 | | ARM_ISB_RESERVED_7 = 7, |
147 | | ARM_ISB_RESERVED_8 = 8, |
148 | | ARM_ISB_RESERVED_9 = 9, |
149 | | ARM_ISB_RESERVED_10 = 10, |
150 | | ARM_ISB_RESERVED_11 = 11, |
151 | | ARM_ISB_RESERVED_12 = 12, |
152 | | ARM_ISB_RESERVED_13 = 13, |
153 | | ARM_ISB_RESERVED_14 = 14, |
154 | | ARM_ISB_SY = 15 |
155 | | }; |
156 | | |
157 | | inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) |
158 | 1.02k | { |
159 | 1.02k | switch (val) { |
160 | 0 | default: // never reach |
161 | 575 | case ARM_ISB_RESERVED_0: return "#0x0"; |
162 | 40 | case ARM_ISB_RESERVED_1: return "#0x1"; |
163 | 72 | case ARM_ISB_RESERVED_2: return "#0x2"; |
164 | 7 | case ARM_ISB_RESERVED_3: return "#0x3"; |
165 | 17 | case ARM_ISB_RESERVED_4: return "#0x4"; |
166 | 75 | case ARM_ISB_RESERVED_5: return "#0x5"; |
167 | 23 | case ARM_ISB_RESERVED_6: return "#0x6"; |
168 | 127 | case ARM_ISB_RESERVED_7: return "#0x7"; |
169 | 11 | case ARM_ISB_RESERVED_8: return "#0x8"; |
170 | 22 | case ARM_ISB_RESERVED_9: return "#0x9"; |
171 | 3 | case ARM_ISB_RESERVED_10: return "#0xa"; |
172 | 10 | case ARM_ISB_RESERVED_11: return "#0xb"; |
173 | 8 | case ARM_ISB_RESERVED_12: return "#0xc"; |
174 | 18 | case ARM_ISB_RESERVED_13: return "#0xd"; |
175 | 10 | case ARM_ISB_RESERVED_14: return "#0xe"; |
176 | 10 | case ARM_ISB_SY: return "sy"; |
177 | 1.02k | } |
178 | 1.02k | } Unexecuted instantiation: ARMDisassembler.c:ARM_ISB_InstSyncBOptToString ARMInstPrinter.c:ARM_ISB_InstSyncBOptToString Line | Count | Source | 158 | 1.02k | { | 159 | 1.02k | switch (val) { | 160 | 0 | default: // never reach | 161 | 575 | case ARM_ISB_RESERVED_0: return "#0x0"; | 162 | 40 | case ARM_ISB_RESERVED_1: return "#0x1"; | 163 | 72 | case ARM_ISB_RESERVED_2: return "#0x2"; | 164 | 7 | case ARM_ISB_RESERVED_3: return "#0x3"; | 165 | 17 | case ARM_ISB_RESERVED_4: return "#0x4"; | 166 | 75 | case ARM_ISB_RESERVED_5: return "#0x5"; | 167 | 23 | case ARM_ISB_RESERVED_6: return "#0x6"; | 168 | 127 | case ARM_ISB_RESERVED_7: return "#0x7"; | 169 | 11 | case ARM_ISB_RESERVED_8: return "#0x8"; | 170 | 22 | case ARM_ISB_RESERVED_9: return "#0x9"; | 171 | 3 | case ARM_ISB_RESERVED_10: return "#0xa"; | 172 | 10 | case ARM_ISB_RESERVED_11: return "#0xb"; | 173 | 8 | case ARM_ISB_RESERVED_12: return "#0xc"; | 174 | 18 | case ARM_ISB_RESERVED_13: return "#0xd"; | 175 | 10 | case ARM_ISB_RESERVED_14: return "#0xe"; | 176 | 10 | case ARM_ISB_SY: return "sy"; | 177 | 1.02k | } | 178 | 1.02k | } |
|
179 | | |
180 | | /// isARMLowRegister - Returns true if the register is a low register (r0-r7). |
181 | | /// |
182 | | static inline bool isARMLowRegister(unsigned Reg) |
183 | 0 | { |
184 | 0 | //using namespace ARM; |
185 | 0 | switch (Reg) { |
186 | 0 | case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: |
187 | 0 | case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: |
188 | 0 | return true; |
189 | 0 | default: |
190 | 0 | return false; |
191 | 0 | } |
192 | 0 | } Unexecuted instantiation: ARMDisassembler.c:isARMLowRegister Unexecuted instantiation: ARMInstPrinter.c:isARMLowRegister |
193 | | |
194 | | /// ARMII - This namespace holds all of the target specific flags that |
195 | | /// instruction info tracks. |
196 | | /// |
197 | | /// ARM Index Modes |
198 | | enum ARMII_IndexMode { |
199 | | ARMII_IndexModeNone = 0, |
200 | | ARMII_IndexModePre = 1, |
201 | | ARMII_IndexModePost = 2, |
202 | | ARMII_IndexModeUpd = 3 |
203 | | }; |
204 | | |
205 | | /// ARM Addressing Modes |
206 | | typedef enum ARMII_AddrMode { |
207 | | ARMII_AddrModeNone = 0, |
208 | | ARMII_AddrMode1 = 1, |
209 | | ARMII_AddrMode2 = 2, |
210 | | ARMII_AddrMode3 = 3, |
211 | | ARMII_AddrMode4 = 4, |
212 | | ARMII_AddrMode5 = 5, |
213 | | ARMII_AddrMode6 = 6, |
214 | | ARMII_AddrModeT1_1 = 7, |
215 | | ARMII_AddrModeT1_2 = 8, |
216 | | ARMII_AddrModeT1_4 = 9, |
217 | | ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data |
218 | | ARMII_AddrModeT2_i12 = 11, |
219 | | ARMII_AddrModeT2_i8 = 12, |
220 | | ARMII_AddrModeT2_so = 13, |
221 | | ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data |
222 | | ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 |
223 | | ARMII_AddrMode_i12 = 16 |
224 | | } ARMII_AddrMode; |
225 | | |
226 | | inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) |
227 | 0 | { |
228 | 0 | switch (addrmode) { |
229 | 0 | case ARMII_AddrModeNone: return "AddrModeNone"; |
230 | 0 | case ARMII_AddrMode1: return "AddrMode1"; |
231 | 0 | case ARMII_AddrMode2: return "AddrMode2"; |
232 | 0 | case ARMII_AddrMode3: return "AddrMode3"; |
233 | 0 | case ARMII_AddrMode4: return "AddrMode4"; |
234 | 0 | case ARMII_AddrMode5: return "AddrMode5"; |
235 | 0 | case ARMII_AddrMode6: return "AddrMode6"; |
236 | 0 | case ARMII_AddrModeT1_1: return "AddrModeT1_1"; |
237 | 0 | case ARMII_AddrModeT1_2: return "AddrModeT1_2"; |
238 | 0 | case ARMII_AddrModeT1_4: return "AddrModeT1_4"; |
239 | 0 | case ARMII_AddrModeT1_s: return "AddrModeT1_s"; |
240 | 0 | case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; |
241 | 0 | case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; |
242 | 0 | case ARMII_AddrModeT2_so: return "AddrModeT2_so"; |
243 | 0 | case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; |
244 | 0 | case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; |
245 | 0 | case ARMII_AddrMode_i12: return "AddrMode_i12"; |
246 | 0 | } |
247 | 0 | } Unexecuted instantiation: ARMDisassembler.c:ARMII_AddrModeToString Unexecuted instantiation: ARMInstPrinter.c:ARMII_AddrModeToString |
248 | | |
249 | | /// Target Operand Flag enum. |
250 | | enum ARMII_TOF { |
251 | | //===------------------------------------------------------------------===// |
252 | | // ARM Specific MachineOperand flags. |
253 | | |
254 | | ARMII_MO_NO_FLAG, |
255 | | |
256 | | /// MO_LO16 - On a symbol operand, this represents a relocation containing |
257 | | /// lower 16 bit of the address. Used only via movw instruction. |
258 | | ARMII_MO_LO16, |
259 | | |
260 | | /// MO_HI16 - On a symbol operand, this represents a relocation containing |
261 | | /// higher 16 bit of the address. Used only via movt instruction. |
262 | | ARMII_MO_HI16, |
263 | | |
264 | | /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a |
265 | | /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, |
266 | | /// i.e. "FOO$non_lazy_ptr". |
267 | | /// Used only via movw instruction. |
268 | | ARMII_MO_LO16_NONLAZY, |
269 | | |
270 | | /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a |
271 | | /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, |
272 | | /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. |
273 | | ARMII_MO_HI16_NONLAZY, |
274 | | |
275 | | /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a |
276 | | /// relocation containing lower 16 bit of the PC relative address of the |
277 | | /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". |
278 | | /// Used only via movw instruction. |
279 | | ARMII_MO_LO16_NONLAZY_PIC, |
280 | | |
281 | | /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a |
282 | | /// relocation containing lower 16 bit of the PC relative address of the |
283 | | /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". |
284 | | /// Used only via movt instruction. |
285 | | ARMII_MO_HI16_NONLAZY_PIC, |
286 | | |
287 | | /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a |
288 | | /// call operand. |
289 | | ARMII_MO_PLT |
290 | | }; |
291 | | |
292 | | enum { |
293 | | //===------------------------------------------------------------------===// |
294 | | // Instruction Flags. |
295 | | |
296 | | //===------------------------------------------------------------------===// |
297 | | // This four-bit field describes the addressing mode used. |
298 | | ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h |
299 | | |
300 | | // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load |
301 | | // and store ops only. Generic "updating" flag is used for ld/st multiple. |
302 | | // The index mode enums are declared in ARMBaseInfo.h |
303 | | ARMII_IndexModeShift = 5, |
304 | | ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, |
305 | | |
306 | | //===------------------------------------------------------------------===// |
307 | | // Instruction encoding formats. |
308 | | // |
309 | | ARMII_FormShift = 7, |
310 | | ARMII_FormMask = 0x3f << ARMII_FormShift, |
311 | | |
312 | | // Pseudo instructions |
313 | | ARMII_Pseudo = 0 << ARMII_FormShift, |
314 | | |
315 | | // Multiply instructions |
316 | | ARMII_MulFrm = 1 << ARMII_FormShift, |
317 | | |
318 | | // Branch instructions |
319 | | ARMII_BrFrm = 2 << ARMII_FormShift, |
320 | | ARMII_BrMiscFrm = 3 << ARMII_FormShift, |
321 | | |
322 | | // Data Processing instructions |
323 | | ARMII_DPFrm = 4 << ARMII_FormShift, |
324 | | ARMII_DPSoRegFrm = 5 << ARMII_FormShift, |
325 | | |
326 | | // Load and Store |
327 | | ARMII_LdFrm = 6 << ARMII_FormShift, |
328 | | ARMII_StFrm = 7 << ARMII_FormShift, |
329 | | ARMII_LdMiscFrm = 8 << ARMII_FormShift, |
330 | | ARMII_StMiscFrm = 9 << ARMII_FormShift, |
331 | | ARMII_LdStMulFrm = 10 << ARMII_FormShift, |
332 | | |
333 | | ARMII_LdStExFrm = 11 << ARMII_FormShift, |
334 | | |
335 | | // Miscellaneous arithmetic instructions |
336 | | ARMII_ArithMiscFrm = 12 << ARMII_FormShift, |
337 | | ARMII_SatFrm = 13 << ARMII_FormShift, |
338 | | |
339 | | // Extend instructions |
340 | | ARMII_ExtFrm = 14 << ARMII_FormShift, |
341 | | |
342 | | // VFP formats |
343 | | ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, |
344 | | ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, |
345 | | ARMII_VFPConv1Frm = 17 << ARMII_FormShift, |
346 | | ARMII_VFPConv2Frm = 18 << ARMII_FormShift, |
347 | | ARMII_VFPConv3Frm = 19 << ARMII_FormShift, |
348 | | ARMII_VFPConv4Frm = 20 << ARMII_FormShift, |
349 | | ARMII_VFPConv5Frm = 21 << ARMII_FormShift, |
350 | | ARMII_VFPLdStFrm = 22 << ARMII_FormShift, |
351 | | ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, |
352 | | ARMII_VFPMiscFrm = 24 << ARMII_FormShift, |
353 | | |
354 | | // Thumb format |
355 | | ARMII_ThumbFrm = 25 << ARMII_FormShift, |
356 | | |
357 | | // Miscelleaneous format |
358 | | ARMII_MiscFrm = 26 << ARMII_FormShift, |
359 | | |
360 | | // NEON formats |
361 | | ARMII_NGetLnFrm = 27 << ARMII_FormShift, |
362 | | ARMII_NSetLnFrm = 28 << ARMII_FormShift, |
363 | | ARMII_NDupFrm = 29 << ARMII_FormShift, |
364 | | ARMII_NLdStFrm = 30 << ARMII_FormShift, |
365 | | ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, |
366 | | ARMII_N2RegFrm = 32 << ARMII_FormShift, |
367 | | ARMII_NVCVTFrm = 33 << ARMII_FormShift, |
368 | | ARMII_NVDupLnFrm = 34 << ARMII_FormShift, |
369 | | ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, |
370 | | ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, |
371 | | ARMII_N3RegFrm = 37 << ARMII_FormShift, |
372 | | ARMII_N3RegVShFrm = 38 << ARMII_FormShift, |
373 | | ARMII_NVExtFrm = 39 << ARMII_FormShift, |
374 | | ARMII_NVMulSLFrm = 40 << ARMII_FormShift, |
375 | | ARMII_NVTBLFrm = 41 << ARMII_FormShift, |
376 | | |
377 | | //===------------------------------------------------------------------===// |
378 | | // Misc flags. |
379 | | |
380 | | // UnaryDP - Indicates this is a unary data processing instruction, i.e. |
381 | | // it doesn't have a Rn operand. |
382 | | ARMII_UnaryDP = 1 << 13, |
383 | | |
384 | | // Xform16Bit - Indicates this Thumb2 instruction may be transformed into |
385 | | // a 16-bit Thumb instruction if certain conditions are met. |
386 | | ARMII_Xform16Bit = 1 << 14, |
387 | | |
388 | | // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb |
389 | | // instruction. Used by the parser to determine whether to require the 'S' |
390 | | // suffix on the mnemonic (when not in an IT block) or preclude it (when |
391 | | // in an IT block). |
392 | | ARMII_ThumbArithFlagSetting = 1 << 18, |
393 | | |
394 | | //===------------------------------------------------------------------===// |
395 | | // Code domain. |
396 | | ARMII_DomainShift = 15, |
397 | | ARMII_DomainMask = 7 << ARMII_DomainShift, |
398 | | ARMII_DomainGeneral = 0 << ARMII_DomainShift, |
399 | | ARMII_DomainVFP = 1 << ARMII_DomainShift, |
400 | | ARMII_DomainNEON = 2 << ARMII_DomainShift, |
401 | | ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, |
402 | | |
403 | | //===------------------------------------------------------------------===// |
404 | | // Field shifts - such shifts are used to set field while generating |
405 | | // machine instructions. |
406 | | // |
407 | | // FIXME: This list will need adjusting/fixing as the MC code emitter |
408 | | // takes shape and the ARMCodeEmitter.cpp bits go away. |
409 | | ARMII_ShiftTypeShift = 4, |
410 | | |
411 | | ARMII_M_BitShift = 5, |
412 | | ARMII_ShiftImmShift = 5, |
413 | | ARMII_ShiftShift = 7, |
414 | | ARMII_N_BitShift = 7, |
415 | | ARMII_ImmHiShift = 8, |
416 | | ARMII_SoRotImmShift = 8, |
417 | | ARMII_RegRsShift = 8, |
418 | | ARMII_ExtRotImmShift = 10, |
419 | | ARMII_RegRdLoShift = 12, |
420 | | ARMII_RegRdShift = 12, |
421 | | ARMII_RegRdHiShift = 16, |
422 | | ARMII_RegRnShift = 16, |
423 | | ARMII_S_BitShift = 20, |
424 | | ARMII_W_BitShift = 21, |
425 | | ARMII_AM3_I_BitShift = 22, |
426 | | ARMII_D_BitShift = 22, |
427 | | ARMII_U_BitShift = 23, |
428 | | ARMII_P_BitShift = 24, |
429 | | ARMII_I_BitShift = 25, |
430 | | ARMII_CondShift = 28 |
431 | | }; |
432 | | |
433 | | typedef struct MClassSysReg { |
434 | | const char *Name; |
435 | | arm_sysreg sysreg; |
436 | | uint16_t M1Encoding12; |
437 | | uint16_t M2M3Encoding8; |
438 | | uint16_t Encoding; |
439 | | int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList |
440 | | } MClassSysReg; |
441 | | |
442 | | enum TraceSyncBOpt { |
443 | | CSYNC = 0 |
444 | | }; |
445 | | |
446 | | const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); |
447 | | const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); |
448 | | |
449 | | // returns APSR with _<bits> qualifier. |
450 | | // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier |
451 | | static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) |
452 | 1.76k | { |
453 | 1.76k | return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); |
454 | 1.76k | } Unexecuted instantiation: ARMDisassembler.c:lookupMClassSysRegAPSRNonDeprecated ARMInstPrinter.c:lookupMClassSysRegAPSRNonDeprecated Line | Count | Source | 452 | 1.76k | { | 453 | 1.76k | return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); | 454 | 1.76k | } |
|
455 | | |
456 | | static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) |
457 | 2.44k | { |
458 | 2.44k | return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); |
459 | 2.44k | } Unexecuted instantiation: ARMDisassembler.c:lookupMClassSysRegBy8bitSYSmValue ARMInstPrinter.c:lookupMClassSysRegBy8bitSYSmValue Line | Count | Source | 457 | 2.44k | { | 458 | 2.44k | return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); | 459 | 2.44k | } |
|
460 | | |
461 | | // returns true if TestFeatures are all present in FeaturesRequired |
462 | | static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures) |
463 | 3.98k | { |
464 | 3.98k | return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); |
465 | 3.98k | } Unexecuted instantiation: ARMDisassembler.c:MClassSysReg_isInRequiredFeatures ARMInstPrinter.c:MClassSysReg_isInRequiredFeatures Line | Count | Source | 463 | 3.98k | { | 464 | 3.98k | return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); | 465 | 3.98k | } |
|
466 | | |
467 | | // lookup system register using 12-bit SYSm value. |
468 | | // Note: the search is uniqued using M1 mask |
469 | | static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) |
470 | 2.00k | { |
471 | 2.00k | return lookupMClassSysRegByM1Encoding12(SYSm); |
472 | 2.00k | } Unexecuted instantiation: ARMDisassembler.c:lookupMClassSysRegBy12bitSYSmValue ARMInstPrinter.c:lookupMClassSysRegBy12bitSYSmValue Line | Count | Source | 470 | 2.00k | { | 471 | 2.00k | return lookupMClassSysRegByM1Encoding12(SYSm); | 472 | 2.00k | } |
|
473 | | |
474 | | static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val) |
475 | 0 | { |
476 | 0 | switch (val) { |
477 | 0 | default: |
478 | | // llvm_unreachable("Unknown trace synchronization barrier operation"); |
479 | 0 | return NULL; |
480 | | |
481 | 0 | case CSYNC: |
482 | 0 | return "csync"; |
483 | 0 | } |
484 | 0 | } Unexecuted instantiation: ARMDisassembler.c:ARM_TSB_TraceSyncBOptToString Unexecuted instantiation: ARMInstPrinter.c:ARM_TSB_TraceSyncBOptToString |
485 | | |
486 | | #endif |