/src/capstonev5/arch/SystemZ/SystemZDisassembler.c
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1 | | //===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | /* Capstone Disassembly Engine */ |
11 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
12 | | |
13 | | #ifdef CAPSTONE_HAS_SYSZ |
14 | | |
15 | | #include <stdio.h> // DEBUG |
16 | | #include <stdlib.h> |
17 | | #include <string.h> |
18 | | |
19 | | #include "../../cs_priv.h" |
20 | | #include "../../utils.h" |
21 | | |
22 | | #include "SystemZDisassembler.h" |
23 | | |
24 | | #include "../../MCInst.h" |
25 | | #include "../../MCInstrDesc.h" |
26 | | #include "../../MCFixedLenDisassembler.h" |
27 | | #include "../../MCRegisterInfo.h" |
28 | | #include "../../MCDisassembler.h" |
29 | | #include "../../MathExtras.h" |
30 | | |
31 | | #include "SystemZMCTargetDesc.h" |
32 | | |
33 | | static uint64_t getFeatureBits(int mode) |
34 | 137k | { |
35 | | // support everything |
36 | 137k | return (uint64_t)-1; |
37 | 137k | } |
38 | | |
39 | | static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) |
40 | 213k | { |
41 | | //assert(RegNo < 16 && "Invalid register"); |
42 | 213k | RegNo = Regs[RegNo]; |
43 | 213k | if (RegNo == 0) |
44 | 288 | return MCDisassembler_Fail; |
45 | | |
46 | 213k | MCOperand_CreateReg0(Inst, (unsigned)RegNo); |
47 | 213k | return MCDisassembler_Success; |
48 | 213k | } |
49 | | |
50 | | static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
51 | | uint64_t Address, const void *Decoder) |
52 | 54.1k | { |
53 | 54.1k | return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); |
54 | 54.1k | } |
55 | | |
56 | | static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
57 | | uint64_t Address, const void *Decoder) |
58 | 6.52k | { |
59 | 6.52k | return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); |
60 | 6.52k | } |
61 | | |
62 | | static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
63 | | uint64_t Address, const void *Decoder) |
64 | 40.4k | { |
65 | 40.4k | return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); |
66 | 40.4k | } |
67 | | |
68 | | static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
69 | | uint64_t Address, const void *Decoder) |
70 | 12.5k | { |
71 | 12.5k | return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); |
72 | 12.5k | } |
73 | | |
74 | | static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
75 | | uint64_t Address, const void *Decoder) |
76 | 4.30k | { |
77 | 4.30k | return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); |
78 | 4.30k | } |
79 | | |
80 | | static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
81 | | uint64_t Address, const void *Decoder) |
82 | 29.9k | { |
83 | 29.9k | return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs); |
84 | 29.9k | } |
85 | | |
86 | | static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
87 | | uint64_t Address, const void *Decoder) |
88 | 40.7k | { |
89 | 40.7k | return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs); |
90 | 40.7k | } |
91 | | |
92 | | static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
93 | | uint64_t Address, const void *Decoder) |
94 | 5.71k | { |
95 | 5.71k | return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs); |
96 | 5.71k | } |
97 | | |
98 | | static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
99 | | uint64_t Address, const void *Decoder) |
100 | 2.26k | { |
101 | 2.26k | return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs); |
102 | 2.26k | } |
103 | | |
104 | | static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
105 | | uint64_t Address, const void *Decoder) |
106 | 1.12k | { |
107 | 1.12k | return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs); |
108 | 1.12k | } |
109 | | |
110 | | static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
111 | | uint64_t Address, const void *Decoder) |
112 | 14.0k | { |
113 | 14.0k | return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs); |
114 | 14.0k | } |
115 | | |
116 | | static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
117 | | uint64_t Address, const void *Decoder) |
118 | 1.16k | { |
119 | 1.16k | return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs); |
120 | 1.16k | } |
121 | | |
122 | | static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, |
123 | | uint64_t Address, const void *Decoder) |
124 | 1.20k | { |
125 | 1.20k | return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs); |
126 | 1.20k | } |
127 | | |
128 | | static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) |
129 | 44.4k | { |
130 | | //assert(isUInt<N>(Imm) && "Invalid immediate"); |
131 | 44.4k | MCOperand_CreateImm0(Inst, Imm); |
132 | 44.4k | return MCDisassembler_Success; |
133 | 44.4k | } |
134 | | |
135 | | static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) |
136 | 6.70k | { |
137 | | //assert(isUInt<N>(Imm) && "Invalid immediate"); |
138 | 6.70k | MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); |
139 | 6.70k | return MCDisassembler_Success; |
140 | 6.70k | } |
141 | | |
142 | | static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, |
143 | | uint64_t Address, const void *Decoder) |
144 | 552 | { |
145 | 552 | return decodeUImmOperand(Inst, Imm); |
146 | 552 | } |
147 | | |
148 | | static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, |
149 | | uint64_t Address, const void *Decoder) |
150 | 874 | { |
151 | 874 | return decodeUImmOperand(Inst, Imm); |
152 | 874 | } |
153 | | |
154 | | static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, |
155 | | uint64_t Address, const void *Decoder) |
156 | 401 | { |
157 | 401 | return decodeUImmOperand(Inst, Imm); |
158 | 401 | } |
159 | | |
160 | | static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, |
161 | | uint64_t Address, const void *Decoder) |
162 | 27.6k | { |
163 | 27.6k | return decodeUImmOperand(Inst, Imm); |
164 | 27.6k | } |
165 | | |
166 | | static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, |
167 | | uint64_t Address, const void *Decoder) |
168 | 121 | { |
169 | 121 | return decodeUImmOperand(Inst, Imm); |
170 | 121 | } |
171 | | |
172 | | static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, |
173 | | uint64_t Address, const void *Decoder) |
174 | 10.2k | { |
175 | 10.2k | return decodeUImmOperand(Inst, Imm); |
176 | 10.2k | } |
177 | | |
178 | | static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, |
179 | | uint64_t Address, const void *Decoder) |
180 | 171 | { |
181 | 171 | return decodeUImmOperand(Inst, Imm); |
182 | 171 | } |
183 | | |
184 | | static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, |
185 | | uint64_t Address, const void *Decoder) |
186 | 2.91k | { |
187 | 2.91k | return decodeUImmOperand(Inst, Imm); |
188 | 2.91k | } |
189 | | |
190 | | static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, |
191 | | uint64_t Address, const void *Decoder) |
192 | 1.56k | { |
193 | 1.56k | return decodeUImmOperand(Inst, Imm); |
194 | 1.56k | } |
195 | | |
196 | | static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, |
197 | | uint64_t Address, const void *Decoder) |
198 | 2.93k | { |
199 | 2.93k | return decodeSImmOperand(Inst, Imm, 8); |
200 | 2.93k | } |
201 | | |
202 | | static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, |
203 | | uint64_t Address, const void *Decoder) |
204 | 2.44k | { |
205 | 2.44k | return decodeSImmOperand(Inst, Imm, 16); |
206 | 2.44k | } |
207 | | |
208 | | static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, |
209 | | uint64_t Address, const void *Decoder) |
210 | 1.33k | { |
211 | 1.33k | return decodeSImmOperand(Inst, Imm, 32); |
212 | 1.33k | } |
213 | | |
214 | | static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, |
215 | | uint64_t Address, unsigned N) |
216 | 9.40k | { |
217 | | //assert(isUInt<N>(Imm) && "Invalid PC-relative offset"); |
218 | 9.40k | MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address); |
219 | 9.40k | return MCDisassembler_Success; |
220 | 9.40k | } |
221 | | |
222 | | static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, |
223 | | uint64_t Address, |
224 | | const void *Decoder) |
225 | 819 | { |
226 | 819 | return decodePCDBLOperand(Inst, Imm, Address, 12); |
227 | 819 | } |
228 | | |
229 | | static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, |
230 | | uint64_t Address, |
231 | | const void *Decoder) |
232 | 4.97k | { |
233 | 4.97k | return decodePCDBLOperand(Inst, Imm, Address, 16); |
234 | 4.97k | } |
235 | | |
236 | | static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, |
237 | | uint64_t Address, |
238 | | const void *Decoder) |
239 | 819 | { |
240 | 819 | return decodePCDBLOperand(Inst, Imm, Address, 24); |
241 | 819 | } |
242 | | |
243 | | static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, |
244 | | uint64_t Address, |
245 | | const void *Decoder) |
246 | 558 | { |
247 | 558 | return decodePCDBLOperand(Inst, Imm, Address, 32); |
248 | 558 | } |
249 | | |
250 | | static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, |
251 | | uint64_t Address, |
252 | | const void *Decoder) |
253 | 2.23k | { |
254 | 2.23k | return decodePCDBLOperand(Inst, Imm, Address, 32); |
255 | 2.23k | } |
256 | | |
257 | | static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, |
258 | | const unsigned *Regs) |
259 | 25.9k | { |
260 | 25.9k | uint64_t Base = Field >> 12; |
261 | 25.9k | uint64_t Disp = Field & 0xfff; |
262 | | //assert(Base < 16 && "Invalid BDAddr12"); |
263 | | |
264 | 25.9k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
265 | 25.9k | MCOperand_CreateImm0(Inst, Disp); |
266 | | |
267 | 25.9k | return MCDisassembler_Success; |
268 | 25.9k | } |
269 | | |
270 | | static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, |
271 | | const unsigned *Regs) |
272 | 4.42k | { |
273 | 4.42k | uint64_t Base = Field >> 20; |
274 | 4.42k | uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); |
275 | | //assert(Base < 16 && "Invalid BDAddr20"); |
276 | | |
277 | 4.42k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
278 | 4.42k | MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); |
279 | 4.42k | return MCDisassembler_Success; |
280 | 4.42k | } |
281 | | |
282 | | static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, |
283 | | const unsigned *Regs) |
284 | 30.3k | { |
285 | 30.3k | uint64_t Index = Field >> 16; |
286 | 30.3k | uint64_t Base = (Field >> 12) & 0xf; |
287 | 30.3k | uint64_t Disp = Field & 0xfff; |
288 | | |
289 | | //assert(Index < 16 && "Invalid BDXAddr12"); |
290 | 30.3k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
291 | 30.3k | MCOperand_CreateImm0(Inst, Disp); |
292 | 30.3k | MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); |
293 | | |
294 | 30.3k | return MCDisassembler_Success; |
295 | 30.3k | } |
296 | | |
297 | | static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, |
298 | | const unsigned *Regs) |
299 | 2.06k | { |
300 | 2.06k | uint64_t Index = Field >> 24; |
301 | 2.06k | uint64_t Base = (Field >> 20) & 0xf; |
302 | 2.06k | uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); |
303 | | |
304 | | //assert(Index < 16 && "Invalid BDXAddr20"); |
305 | 2.06k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
306 | 2.06k | MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); |
307 | 2.06k | MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); |
308 | | |
309 | 2.06k | return MCDisassembler_Success; |
310 | 2.06k | } |
311 | | |
312 | | static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, |
313 | | const unsigned *Regs) |
314 | 12.0k | { |
315 | 12.0k | uint64_t Length = Field >> 16; |
316 | 12.0k | uint64_t Base = (Field >> 12) & 0xf; |
317 | 12.0k | uint64_t Disp = Field & 0xfff; |
318 | | //assert(Length < 256 && "Invalid BDLAddr12Len8"); |
319 | | |
320 | 12.0k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
321 | 12.0k | MCOperand_CreateImm0(Inst, Disp); |
322 | 12.0k | MCOperand_CreateImm0(Inst, Length + 1); |
323 | | |
324 | 12.0k | return MCDisassembler_Success; |
325 | 12.0k | } |
326 | | |
327 | | static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, |
328 | | const unsigned *Regs) |
329 | 1.08k | { |
330 | 1.08k | uint64_t Length = Field >> 16; |
331 | 1.08k | uint64_t Base = (Field >> 12) & 0xf; |
332 | 1.08k | uint64_t Disp = Field & 0xfff; |
333 | | //assert(Length < 16 && "Invalid BDRAddr12"); |
334 | | |
335 | 1.08k | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
336 | 1.08k | MCOperand_CreateImm0(Inst, Disp); |
337 | 1.08k | MCOperand_CreateReg0(Inst, Regs[Length]); |
338 | | |
339 | 1.08k | return MCDisassembler_Success; |
340 | 1.08k | } |
341 | | |
342 | | static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, |
343 | | const unsigned *Regs) |
344 | 937 | { |
345 | 937 | uint64_t Index = Field >> 16; |
346 | 937 | uint64_t Base = (Field >> 12) & 0xf; |
347 | 937 | uint64_t Disp = Field & 0xfff; |
348 | | //assert(Index < 32 && "Invalid BDVAddr12"); |
349 | | |
350 | 937 | MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); |
351 | 937 | MCOperand_CreateImm0(Inst, Disp); |
352 | 937 | MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); |
353 | | |
354 | 937 | return MCDisassembler_Success; |
355 | 937 | } |
356 | | |
357 | | static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, |
358 | | uint64_t Address, const void *Decoder) |
359 | 3.73k | { |
360 | 3.73k | return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); |
361 | 3.73k | } |
362 | | |
363 | | static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, |
364 | | uint64_t Address, const void *Decoder) |
365 | 919 | { |
366 | 919 | return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); |
367 | 919 | } |
368 | | |
369 | | static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, |
370 | | uint64_t Address, const void *Decoder) |
371 | 22.2k | { |
372 | 22.2k | return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); |
373 | 22.2k | } |
374 | | |
375 | | static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, |
376 | | uint64_t Address, const void *Decoder) |
377 | 3.50k | { |
378 | 3.50k | return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); |
379 | 3.50k | } |
380 | | |
381 | | static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, |
382 | | uint64_t Address, const void *Decoder) |
383 | 30.3k | { |
384 | 30.3k | return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); |
385 | 30.3k | } |
386 | | |
387 | | static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, |
388 | | uint64_t Address, const void *Decoder) |
389 | 2.06k | { |
390 | 2.06k | return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); |
391 | 2.06k | } |
392 | | |
393 | | static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field, |
394 | | uint64_t Address, const void *Decoder) |
395 | 7.64k | { |
396 | 7.64k | return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); |
397 | 7.64k | } |
398 | | |
399 | | static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, |
400 | | uint64_t Address, const void *Decoder) |
401 | 4.40k | { |
402 | 4.40k | return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); |
403 | 4.40k | } |
404 | | |
405 | | static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, |
406 | | uint64_t Address, const void *Decoder) |
407 | 1.08k | { |
408 | 1.08k | return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); |
409 | 1.08k | } |
410 | | |
411 | | static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, |
412 | | uint64_t Address, const void *Decoder) |
413 | 937 | { |
414 | 937 | return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); |
415 | 937 | } |
416 | | |
417 | | |
418 | | #define GET_SUBTARGETINFO_ENUM |
419 | | #include "SystemZGenSubtargetInfo.inc" |
420 | | #include "SystemZGenDisassemblerTables.inc" |
421 | | bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, |
422 | | uint16_t *size, uint64_t address, void *info) |
423 | 139k | { |
424 | 139k | uint64_t Inst; |
425 | 139k | const uint8_t *Table; |
426 | 139k | uint16_t I; |
427 | | |
428 | | // The top 2 bits of the first byte specify the size. |
429 | 139k | if (*code < 0x40) { |
430 | 41.1k | *size = 2; |
431 | 41.1k | Table = DecoderTable16; |
432 | 97.8k | } else if (*code < 0xc0) { |
433 | 53.9k | *size = 4; |
434 | 53.9k | Table = DecoderTable32; |
435 | 53.9k | } else { |
436 | 43.8k | *size = 6; |
437 | 43.8k | Table = DecoderTable48; |
438 | 43.8k | } |
439 | | |
440 | 139k | if (code_len < *size) |
441 | | // short of input data |
442 | 1.20k | return false; |
443 | | |
444 | 137k | if (MI->flat_insn->detail) { |
445 | 137k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz)); |
446 | 137k | } |
447 | | |
448 | | // Construct the instruction. |
449 | 137k | Inst = 0; |
450 | 694k | for (I = 0; I < *size; ++I) |
451 | 556k | Inst = (Inst << 8) | code[I]; |
452 | | |
453 | 137k | return decodeInstruction(Table, MI, Inst, address, info, 0); |
454 | 139k | } |
455 | | |
456 | | #define GET_REGINFO_ENUM |
457 | | #define GET_REGINFO_MC_DESC |
458 | | #include "SystemZGenRegisterInfo.inc" |
459 | | void SystemZ_init(MCRegisterInfo *MRI) |
460 | 3.92k | { |
461 | | /* |
462 | | InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, |
463 | | SystemZMCRegisterClasses, 12, |
464 | | SystemZRegUnitRoots, |
465 | | 49, |
466 | | SystemZRegDiffLists, |
467 | | SystemZRegStrings, |
468 | | SystemZSubRegIdxLists, |
469 | | 7, |
470 | | SystemZSubRegIdxRanges, |
471 | | SystemZRegEncodingTable); |
472 | | */ |
473 | | |
474 | 3.92k | MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194, |
475 | 3.92k | 0, 0, |
476 | 3.92k | SystemZMCRegisterClasses, 21, |
477 | 3.92k | 0, 0, |
478 | 3.92k | SystemZRegDiffLists, |
479 | 3.92k | 0, |
480 | 3.92k | SystemZSubRegIdxLists, 7, |
481 | 3.92k | 0); |
482 | 3.92k | } |
483 | | |
484 | | #endif |