/src/capstonev5/arch/TMS320C64x/TMS320C64xDisassembler.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_TMS320C64X |
5 | | |
6 | | #include <string.h> |
7 | | |
8 | | #include "../../cs_priv.h" |
9 | | #include "../../utils.h" |
10 | | |
11 | | #include "TMS320C64xDisassembler.h" |
12 | | |
13 | | #include "../../MCInst.h" |
14 | | #include "../../MCInstrDesc.h" |
15 | | #include "../../MCFixedLenDisassembler.h" |
16 | | #include "../../MCRegisterInfo.h" |
17 | | #include "../../MCDisassembler.h" |
18 | | #include "../../MathExtras.h" |
19 | | |
20 | | static uint64_t getFeatureBits(int mode); |
21 | | |
22 | | static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
23 | | uint64_t Address, void *Decoder); |
24 | | |
25 | | static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
26 | | uint64_t Address, void *Decoder); |
27 | | |
28 | | static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, |
29 | | uint64_t Address, void *Decoder); |
30 | | |
31 | | static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, |
32 | | uint64_t Address, void *Decoder); |
33 | | |
34 | | static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, |
35 | | uint64_t Address, void *Decoder); |
36 | | |
37 | | static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, |
38 | | uint64_t Address, void *Decoder); |
39 | | |
40 | | static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, |
41 | | uint64_t Address, void *Decoder); |
42 | | |
43 | | static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, |
44 | | uint64_t Address, void *Decoder); |
45 | | |
46 | | static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, |
47 | | uint64_t Address, void *Decoder); |
48 | | |
49 | | static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, |
50 | | uint64_t Address, void *Decoder); |
51 | | |
52 | | static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, |
53 | | uint64_t Address, void *Decoder); |
54 | | |
55 | | static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, |
56 | | uint64_t Address, void *Decoder); |
57 | | |
58 | | static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, |
59 | | uint64_t Address, void *Decoder); |
60 | | |
61 | | static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, |
62 | | uint64_t Address, void *Decoder); |
63 | | |
64 | | static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, |
65 | | uint64_t Address, void *Decoder); |
66 | | |
67 | | static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, |
68 | | uint64_t Address, void *Decoder); |
69 | | |
70 | | static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, |
71 | | uint64_t Address, void *Decoder); |
72 | | |
73 | | static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, |
74 | | uint64_t Address, void *Decoder); |
75 | | |
76 | | static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, |
77 | | uint64_t Address, void *Decoder); |
78 | | |
79 | | static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, |
80 | | uint64_t Address, void *Decoder); |
81 | | |
82 | | static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, |
83 | | uint64_t Address, void *Decoder); |
84 | | |
85 | | #include "TMS320C64xGenDisassemblerTables.inc" |
86 | | |
87 | | #define GET_REGINFO_ENUM |
88 | | #define GET_REGINFO_MC_DESC |
89 | | #include "TMS320C64xGenRegisterInfo.inc" |
90 | | |
91 | | static const unsigned GPRegsDecoderTable[] = { |
92 | | TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, |
93 | | TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, |
94 | | TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, |
95 | | TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, |
96 | | TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, |
97 | | TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, |
98 | | TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, |
99 | | TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31 |
100 | | }; |
101 | | |
102 | | static const unsigned ControlRegsDecoderTable[] = { |
103 | | TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_ISR, TMS320C64x_ICR, |
104 | | TMS320C64x_IER, TMS320C64x_ISTP, TMS320C64x_IRP, TMS320C64x_NRP, |
105 | | ~0U, ~0U, TMS320C64x_TSCL, TMS320C64x_TSCH, |
106 | | ~0U, TMS320C64x_ILC, TMS320C64x_RILC, TMS320C64x_REP, |
107 | | TMS320C64x_PCE1, TMS320C64x_DNUM, ~0U, ~0U, |
108 | | ~0U, TMS320C64x_SSR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, |
109 | | TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR, TMS320C64x_ITSR, |
110 | | TMS320C64x_NTSR, TMS320C64x_ECR, ~0U, TMS320C64x_IERR |
111 | | }; |
112 | | |
113 | | static uint64_t getFeatureBits(int mode) |
114 | 70.5k | { |
115 | | // support everything |
116 | 70.5k | return (uint64_t)-1; |
117 | 70.5k | } |
118 | | |
119 | | static unsigned getReg(const unsigned *RegTable, unsigned RegNo) |
120 | 125k | { |
121 | 125k | if(RegNo > 31) |
122 | 98 | return ~0U; |
123 | 125k | return RegTable[RegNo]; |
124 | 125k | } |
125 | | |
126 | | static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
127 | | uint64_t Address, void *Decoder) |
128 | 93.2k | { |
129 | 93.2k | unsigned Reg; |
130 | | |
131 | 93.2k | if(RegNo > 31) |
132 | 0 | return MCDisassembler_Fail; |
133 | | |
134 | 93.2k | Reg = getReg(GPRegsDecoderTable, RegNo); |
135 | 93.2k | if(Reg == ~0U) |
136 | 0 | return MCDisassembler_Fail; |
137 | 93.2k | MCOperand_CreateReg0(Inst, Reg); |
138 | | |
139 | 93.2k | return MCDisassembler_Success; |
140 | 93.2k | } |
141 | | |
142 | | static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
143 | | uint64_t Address, void *Decoder) |
144 | 2.57k | { |
145 | 2.57k | unsigned Reg; |
146 | | |
147 | 2.57k | if(RegNo > 31) |
148 | 0 | return MCDisassembler_Fail; |
149 | | |
150 | 2.57k | Reg = getReg(ControlRegsDecoderTable, RegNo); |
151 | 2.57k | if(Reg == ~0U) |
152 | 4 | return MCDisassembler_Fail; |
153 | 2.57k | MCOperand_CreateReg0(Inst, Reg); |
154 | | |
155 | 2.57k | return MCDisassembler_Success; |
156 | 2.57k | } |
157 | | |
158 | | static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, |
159 | | uint64_t Address, void *Decoder) |
160 | 7.05k | { |
161 | 7.05k | int32_t imm; |
162 | | |
163 | 7.05k | imm = Val; |
164 | | /* Sign extend 5 bit value */ |
165 | 7.05k | if(imm & (1 << (5 - 1))) |
166 | 2.59k | imm |= ~((1 << 5) - 1); |
167 | | |
168 | 7.05k | MCOperand_CreateImm0(Inst, imm); |
169 | | |
170 | 7.05k | return MCDisassembler_Success; |
171 | 7.05k | } |
172 | | |
173 | | static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, |
174 | | uint64_t Address, void *Decoder) |
175 | 4.06k | { |
176 | 4.06k | int32_t imm; |
177 | | |
178 | 4.06k | imm = Val; |
179 | | /* Sign extend 16 bit value */ |
180 | 4.06k | if(imm & (1 << (16 - 1))) |
181 | 2.18k | imm |= ~((1 << 16) - 1); |
182 | | |
183 | 4.06k | MCOperand_CreateImm0(Inst, imm); |
184 | | |
185 | 4.06k | return MCDisassembler_Success; |
186 | 4.06k | } |
187 | | |
188 | | static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, |
189 | | uint64_t Address, void *Decoder) |
190 | 764 | { |
191 | 764 | int32_t imm; |
192 | | |
193 | 764 | imm = Val; |
194 | | /* Sign extend 7 bit value */ |
195 | 764 | if(imm & (1 << (7 - 1))) |
196 | 631 | imm |= ~((1 << 7) - 1); |
197 | | |
198 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
199 | 764 | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
200 | | |
201 | 764 | return MCDisassembler_Success; |
202 | 764 | } |
203 | | |
204 | | static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, |
205 | | uint64_t Address, void *Decoder) |
206 | 1.24k | { |
207 | 1.24k | int32_t imm; |
208 | | |
209 | 1.24k | imm = Val; |
210 | | /* Sign extend 10 bit value */ |
211 | 1.24k | if(imm & (1 << (10 - 1))) |
212 | 502 | imm |= ~((1 << 10) - 1); |
213 | | |
214 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
215 | 1.24k | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
216 | | |
217 | 1.24k | return MCDisassembler_Success; |
218 | 1.24k | } |
219 | | |
220 | | static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, |
221 | | uint64_t Address, void *Decoder) |
222 | 1.01k | { |
223 | 1.01k | int32_t imm; |
224 | | |
225 | 1.01k | imm = Val; |
226 | | /* Sign extend 12 bit value */ |
227 | 1.01k | if(imm & (1 << (12 - 1))) |
228 | 176 | imm |= ~((1 << 12) - 1); |
229 | | |
230 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
231 | 1.01k | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
232 | | |
233 | 1.01k | return MCDisassembler_Success; |
234 | 1.01k | } |
235 | | |
236 | | static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, |
237 | | uint64_t Address, void *Decoder) |
238 | 3.62k | { |
239 | 3.62k | int32_t imm; |
240 | | |
241 | 3.62k | imm = Val; |
242 | | /* Sign extend 21 bit value */ |
243 | 3.62k | if(imm & (1 << (21 - 1))) |
244 | 1.08k | imm |= ~((1 << 21) - 1); |
245 | | |
246 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
247 | 3.62k | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
248 | | |
249 | 3.62k | return MCDisassembler_Success; |
250 | 3.62k | } |
251 | | |
252 | | static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, |
253 | | uint64_t Address, void *Decoder) |
254 | 6.47k | { |
255 | 6.47k | return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder); |
256 | 6.47k | } |
257 | | |
258 | | static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, |
259 | | uint64_t Address, void *Decoder) |
260 | 7.57k | { |
261 | 7.57k | uint8_t scaled, base, offset, mode, unit; |
262 | 7.57k | unsigned basereg, offsetreg; |
263 | | |
264 | 7.57k | scaled = (Val >> 15) & 1; |
265 | 7.57k | base = (Val >> 10) & 0x1f; |
266 | 7.57k | offset = (Val >> 5) & 0x1f; |
267 | 7.57k | mode = (Val >> 1) & 0xf; |
268 | 7.57k | unit = Val & 1; |
269 | | |
270 | 7.57k | if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31)) |
271 | 81 | base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
272 | 7.49k | else if((base >= TMS320C64X_REG_B0) && (base <= TMS320C64X_REG_B31)) |
273 | 0 | base = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
274 | 7.57k | basereg = getReg(GPRegsDecoderTable, base); |
275 | 7.57k | if (basereg == ~0U) |
276 | 81 | return MCDisassembler_Fail; |
277 | | |
278 | 7.49k | switch(mode) { |
279 | 836 | case 0: |
280 | 1.38k | case 1: |
281 | 1.75k | case 8: |
282 | 2.37k | case 9: |
283 | 3.53k | case 10: |
284 | 4.82k | case 11: |
285 | 4.82k | MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit); |
286 | 4.82k | break; |
287 | 395 | case 4: |
288 | 1.04k | case 5: |
289 | 1.67k | case 12: |
290 | 1.98k | case 13: |
291 | 2.35k | case 14: |
292 | 2.61k | case 15: |
293 | 2.61k | if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31)) |
294 | 17 | offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
295 | 2.60k | else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31)) |
296 | 0 | offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
297 | 2.61k | offsetreg = getReg(GPRegsDecoderTable, offset); |
298 | 2.61k | if (offsetreg == ~0U) |
299 | 17 | return MCDisassembler_Fail; |
300 | 2.60k | MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit); |
301 | 2.60k | break; |
302 | 56 | default: |
303 | 56 | return MCDisassembler_Fail; |
304 | 7.49k | } |
305 | | |
306 | 7.42k | return MCDisassembler_Success; |
307 | 7.49k | } |
308 | | |
309 | | static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, |
310 | | uint64_t Address, void *Decoder) |
311 | 10.5k | { |
312 | 10.5k | uint16_t offset; |
313 | 10.5k | unsigned basereg; |
314 | | |
315 | 10.5k | if(Val & 1) |
316 | 5.66k | basereg = TMS320C64X_REG_B15; |
317 | 4.90k | else |
318 | 4.90k | basereg = TMS320C64X_REG_B14; |
319 | | |
320 | 10.5k | offset = (Val >> 1) & 0x7fff; |
321 | 10.5k | MCOperand_CreateImm0(Inst, (offset << 7) | basereg); |
322 | | |
323 | 10.5k | return MCDisassembler_Success; |
324 | 10.5k | } |
325 | | |
326 | | static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, |
327 | | uint64_t Address, void *Decoder) |
328 | 18.2k | { |
329 | 18.2k | unsigned Reg; |
330 | | |
331 | 18.2k | if(RegNo > 31) |
332 | 0 | return MCDisassembler_Fail; |
333 | | |
334 | 18.2k | Reg = getReg(GPRegsDecoderTable, RegNo); |
335 | 18.2k | MCOperand_CreateReg0(Inst, Reg); |
336 | | |
337 | 18.2k | return MCDisassembler_Success; |
338 | 18.2k | } |
339 | | |
340 | | static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, |
341 | | uint64_t Address, void *Decoder) |
342 | 1.09k | { |
343 | 1.09k | unsigned Reg; |
344 | | |
345 | 1.09k | if(RegNo > 15) |
346 | 0 | return MCDisassembler_Fail; |
347 | | |
348 | 1.09k | Reg = getReg(GPRegsDecoderTable, RegNo << 1); |
349 | 1.09k | MCOperand_CreateReg0(Inst, Reg); |
350 | | |
351 | 1.09k | return MCDisassembler_Success; |
352 | 1.09k | } |
353 | | |
354 | | static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, |
355 | | uint64_t Address, void *Decoder) |
356 | 69.9k | { |
357 | 69.9k | DecodeStatus ret = MCDisassembler_Success; |
358 | | |
359 | 69.9k | if(!Inst->flat_insn->detail) |
360 | 0 | return MCDisassembler_Success; |
361 | | |
362 | 69.9k | switch(Val) { |
363 | 16.7k | case 0: |
364 | 25.0k | case 7: |
365 | 25.0k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; |
366 | 25.0k | break; |
367 | 10.4k | case 1: |
368 | 10.4k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0; |
369 | 10.4k | break; |
370 | 6.41k | case 2: |
371 | 6.41k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1; |
372 | 6.41k | break; |
373 | 6.84k | case 3: |
374 | 6.84k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2; |
375 | 6.84k | break; |
376 | 6.73k | case 4: |
377 | 6.73k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1; |
378 | 6.73k | break; |
379 | 7.16k | case 5: |
380 | 7.16k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2; |
381 | 7.16k | break; |
382 | 7.24k | case 6: |
383 | 7.24k | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0; |
384 | 7.24k | break; |
385 | 0 | default: |
386 | 0 | Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; |
387 | 0 | ret = MCDisassembler_Fail; |
388 | 0 | break; |
389 | 69.9k | } |
390 | | |
391 | 69.9k | return ret; |
392 | 69.9k | } |
393 | | |
394 | | static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, |
395 | | uint64_t Address, void *Decoder) |
396 | 69.9k | { |
397 | 69.9k | DecodeStatus ret = MCDisassembler_Success; |
398 | | |
399 | 69.9k | if(!Inst->flat_insn->detail) |
400 | 0 | return MCDisassembler_Success; |
401 | | |
402 | 69.9k | switch(Val) { |
403 | 30.7k | case 0: |
404 | 30.7k | Inst->flat_insn->detail->tms320c64x.condition.zero = 0; |
405 | 30.7k | break; |
406 | 39.1k | case 1: |
407 | 39.1k | Inst->flat_insn->detail->tms320c64x.condition.zero = 1; |
408 | 39.1k | break; |
409 | 0 | default: |
410 | 0 | Inst->flat_insn->detail->tms320c64x.condition.zero = 0; |
411 | 0 | ret = MCDisassembler_Fail; |
412 | 0 | break; |
413 | 69.9k | } |
414 | | |
415 | 69.9k | return ret; |
416 | 69.9k | } |
417 | | |
418 | | static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, |
419 | | uint64_t Address, void *Decoder) |
420 | 69.9k | { |
421 | 69.9k | DecodeStatus ret = MCDisassembler_Success; |
422 | 69.9k | MCOperand *op; |
423 | 69.9k | int i; |
424 | | |
425 | | /* This is pretty messy, probably we should find a better way */ |
426 | 69.9k | if(Val == 1) { |
427 | 92.1k | for(i = 0; i < Inst->size; i++) { |
428 | 64.5k | op = &Inst->Operands[i]; |
429 | 64.5k | if(op->Kind == kRegister) { |
430 | 45.2k | if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) |
431 | 38.5k | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
432 | 6.77k | else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) |
433 | 4.22k | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
434 | 45.2k | } |
435 | 64.5k | } |
436 | 27.5k | } |
437 | | |
438 | 69.9k | if(!Inst->flat_insn->detail) |
439 | 0 | return MCDisassembler_Success; |
440 | | |
441 | 69.9k | switch(Val) { |
442 | 42.3k | case 0: |
443 | 42.3k | Inst->flat_insn->detail->tms320c64x.funit.side = 1; |
444 | 42.3k | break; |
445 | 27.5k | case 1: |
446 | 27.5k | Inst->flat_insn->detail->tms320c64x.funit.side = 2; |
447 | 27.5k | break; |
448 | 0 | default: |
449 | 0 | Inst->flat_insn->detail->tms320c64x.funit.side = 0; |
450 | 0 | ret = MCDisassembler_Fail; |
451 | 0 | break; |
452 | 69.9k | } |
453 | | |
454 | 69.9k | return ret; |
455 | 69.9k | } |
456 | | |
457 | | static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, |
458 | | uint64_t Address, void *Decoder) |
459 | 69.9k | { |
460 | 69.9k | DecodeStatus ret = MCDisassembler_Success; |
461 | | |
462 | 69.9k | if(!Inst->flat_insn->detail) |
463 | 0 | return MCDisassembler_Success; |
464 | | |
465 | 69.9k | switch(Val) { |
466 | 36.3k | case 0: |
467 | 36.3k | Inst->flat_insn->detail->tms320c64x.parallel = 0; |
468 | 36.3k | break; |
469 | 33.6k | case 1: |
470 | 33.6k | Inst->flat_insn->detail->tms320c64x.parallel = 1; |
471 | 33.6k | break; |
472 | 0 | default: |
473 | 0 | Inst->flat_insn->detail->tms320c64x.parallel = -1; |
474 | 0 | ret = MCDisassembler_Fail; |
475 | 0 | break; |
476 | 69.9k | } |
477 | | |
478 | 69.9k | return ret; |
479 | 69.9k | } |
480 | | |
481 | | static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, |
482 | | uint64_t Address, void *Decoder) |
483 | 674 | { |
484 | 674 | DecodeStatus ret = MCDisassembler_Success; |
485 | 674 | MCOperand *op; |
486 | | |
487 | 674 | if(!Inst->flat_insn->detail) |
488 | 0 | return MCDisassembler_Success; |
489 | | |
490 | 674 | switch(Val) { |
491 | 384 | case 0: |
492 | 384 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
493 | 384 | break; |
494 | 290 | case 1: |
495 | 290 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; |
496 | 290 | op = &Inst->Operands[0]; |
497 | 290 | if(op->Kind == kRegister) { |
498 | 290 | if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) |
499 | 290 | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
500 | 0 | else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) |
501 | 0 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
502 | 290 | } |
503 | 290 | break; |
504 | 0 | default: |
505 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
506 | 0 | ret = MCDisassembler_Fail; |
507 | 0 | break; |
508 | 674 | } |
509 | | |
510 | 674 | return ret; |
511 | 674 | } |
512 | | |
513 | | static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, |
514 | | uint64_t Address, void *Decoder) |
515 | 23.3k | { |
516 | 23.3k | DecodeStatus ret = MCDisassembler_Success; |
517 | 23.3k | MCOperand *op; |
518 | | |
519 | 23.3k | if(!Inst->flat_insn->detail) |
520 | 0 | return MCDisassembler_Success; |
521 | | |
522 | 23.3k | switch(Val) { |
523 | 10.9k | case 0: |
524 | 10.9k | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
525 | 10.9k | break; |
526 | 12.4k | case 1: |
527 | 12.4k | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; |
528 | 12.4k | op = &Inst->Operands[1]; |
529 | 12.4k | if(op->Kind == kRegister) { |
530 | 12.0k | if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) |
531 | 9.65k | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
532 | 2.40k | else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) |
533 | 0 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
534 | 12.0k | } |
535 | 12.4k | break; |
536 | 0 | default: |
537 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
538 | 0 | ret = MCDisassembler_Fail; |
539 | 0 | break; |
540 | 23.3k | } |
541 | | |
542 | 23.3k | return ret; |
543 | 23.3k | } |
544 | | |
545 | | static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, |
546 | | uint64_t Address, void *Decoder) |
547 | 10.0k | { |
548 | 10.0k | DecodeStatus ret = MCDisassembler_Success; |
549 | 10.0k | MCOperand *op; |
550 | | |
551 | 10.0k | if(!Inst->flat_insn->detail) |
552 | 0 | return MCDisassembler_Success; |
553 | | |
554 | 10.0k | switch(Val) { |
555 | 2.72k | case 0: |
556 | 2.72k | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
557 | 2.72k | break; |
558 | 7.29k | case 1: |
559 | 7.29k | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2; |
560 | 7.29k | op = &Inst->Operands[2]; |
561 | 7.29k | if(op->Kind == kRegister) { |
562 | 4.49k | if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) |
563 | 3.47k | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
564 | 1.02k | else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) |
565 | 591 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); |
566 | 4.49k | } |
567 | 7.29k | break; |
568 | 0 | default: |
569 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
570 | 0 | ret = MCDisassembler_Fail; |
571 | 0 | break; |
572 | 10.0k | } |
573 | | |
574 | 10.0k | return ret; |
575 | 10.0k | } |
576 | | |
577 | | |
578 | | static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, |
579 | | uint64_t Address, void *Decoder) |
580 | 1.82k | { |
581 | 1.82k | MCOperand_CreateImm0(Inst, Val + 1); |
582 | | |
583 | 1.82k | return MCDisassembler_Success; |
584 | 1.82k | } |
585 | | |
586 | | #define GET_INSTRINFO_ENUM |
587 | | #include "TMS320C64xGenInstrInfo.inc" |
588 | | |
589 | | bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, |
590 | | MCInst *MI, uint16_t *size, uint64_t address, void *info) |
591 | 71.3k | { |
592 | 71.3k | uint32_t insn; |
593 | 71.3k | DecodeStatus result; |
594 | | |
595 | 71.3k | if(code_len < 4) { |
596 | 803 | *size = 0; |
597 | 803 | return MCDisassembler_Fail; |
598 | 803 | } |
599 | | |
600 | 70.5k | if(MI->flat_insn->detail) |
601 | 70.5k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x)); |
602 | | |
603 | 70.5k | insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); |
604 | 70.5k | result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0); |
605 | | |
606 | 70.5k | if(result == MCDisassembler_Success) { |
607 | 69.9k | *size = 4; |
608 | 69.9k | return true; |
609 | 69.9k | } |
610 | | |
611 | 624 | MCInst_clear(MI); |
612 | 624 | *size = 0; |
613 | 624 | return false; |
614 | 70.5k | } |
615 | | |
616 | | void TMS320C64x_init(MCRegisterInfo *MRI) |
617 | 1.91k | { |
618 | 1.91k | MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, |
619 | 1.91k | 0, 0, |
620 | 1.91k | TMS320C64xMCRegisterClasses, 7, |
621 | 1.91k | 0, 0, |
622 | 1.91k | TMS320C64xRegDiffLists, |
623 | 1.91k | 0, |
624 | 1.91k | TMS320C64xSubRegIdxLists, 1, |
625 | 1.91k | 0); |
626 | 1.91k | } |
627 | | |
628 | | #endif |