/src/capstonev5/arch/TriCore/TriCoreGenAsmWriter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Do not edit. */ |
10 | | |
11 | | /* Capstone's LLVM TableGen Backends: */ |
12 | | /* https://github.com/capstone-engine/llvm-capstone */ |
13 | | |
14 | | #include <capstone/platform.h> |
15 | | #include <assert.h> |
16 | | |
17 | | /// getMnemonic - This method is automatically generated by tablegen |
18 | | /// from the instruction set description. |
19 | 0 | static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { |
20 | 0 | #ifndef CAPSTONE_DIET |
21 | 0 | static const char AsmStrs[] = { |
22 | 0 | /* 0 */ "sub d15, \0" |
23 | 0 | /* 10 */ "add d15, \0" |
24 | 0 | /* 20 */ "and d15, \0" |
25 | 0 | /* 30 */ "jne d15, \0" |
26 | 0 | /* 40 */ "jeq d15, \0" |
27 | 0 | /* 50 */ "or d15, \0" |
28 | 0 | /* 59 */ "jz.t d15, \0" |
29 | 0 | /* 70 */ "jnz.t d15, \0" |
30 | 0 | /* 82 */ "lt d15, \0" |
31 | 0 | /* 91 */ "lt.u d15, \0" |
32 | 0 | /* 102 */ "mov d15, \0" |
33 | 0 | /* 112 */ "jz d15, \0" |
34 | 0 | /* 121 */ "jnz d15, \0" |
35 | 0 | /* 131 */ "sub.a sp, \0" |
36 | 0 | /* 142 */ "ftoq31 \0" |
37 | 0 | /* 150 */ "csub.a \0" |
38 | 0 | /* 158 */ "subsc.a \0" |
39 | 0 | /* 167 */ "addsc.a \0" |
40 | 0 | /* 176 */ "difsc.a \0" |
41 | 0 | /* 185 */ "cadd.a \0" |
42 | 0 | /* 193 */ "ld.a \0" |
43 | 0 | /* 199 */ "tlbprobe.a \0" |
44 | 0 | /* 211 */ "ge.a \0" |
45 | 0 | /* 217 */ "jne.a \0" |
46 | 0 | /* 224 */ "addih.a \0" |
47 | 0 | /* 233 */ "movh.a \0" |
48 | 0 | /* 241 */ "sel.a \0" |
49 | 0 | /* 248 */ "csubn.a \0" |
50 | 0 | /* 257 */ "caddn.a \0" |
51 | 0 | /* 266 */ "seln.a \0" |
52 | 0 | /* 274 */ "swap.a \0" |
53 | 0 | /* 282 */ "jeq.a \0" |
54 | 0 | /* 289 */ "lt.a \0" |
55 | 0 | /* 295 */ "st.a \0" |
56 | 0 | /* 301 */ "mov.a \0" |
57 | 0 | /* 308 */ "nez.a \0" |
58 | 0 | /* 315 */ "jz.a \0" |
59 | 0 | /* 321 */ "jnz.a \0" |
60 | 0 | /* 328 */ "eqz.a \0" |
61 | 0 | /* 335 */ "movz.a \0" |
62 | 0 | /* 343 */ "mov.aa \0" |
63 | 0 | /* 351 */ "ld.da \0" |
64 | 0 | /* 358 */ "st.da \0" |
65 | 0 | /* 365 */ "lea \0" |
66 | 0 | /* 370 */ "lha \0" |
67 | 0 | /* 375 */ "sha \0" |
68 | 0 | /* 380 */ "ja \0" |
69 | 0 | /* 384 */ "jla \0" |
70 | 0 | /* 389 */ "fcalla \0" |
71 | 0 | /* 397 */ "crc32.b \0" |
72 | 0 | /* 406 */ "sha.b \0" |
73 | 0 | /* 413 */ "sub.b \0" |
74 | 0 | /* 420 */ "add.b \0" |
75 | 0 | /* 427 */ "ld.b \0" |
76 | 0 | /* 433 */ "absdif.b \0" |
77 | 0 | /* 443 */ "sh.b \0" |
78 | 0 | /* 449 */ "min.b \0" |
79 | 0 | /* 456 */ "clo.b \0" |
80 | 0 | /* 463 */ "eq.b \0" |
81 | 0 | /* 469 */ "abs.b \0" |
82 | 0 | /* 476 */ "subs.b \0" |
83 | 0 | /* 484 */ "adds.b \0" |
84 | 0 | /* 492 */ "absdifs.b \0" |
85 | 0 | /* 503 */ "cls.b \0" |
86 | 0 | /* 510 */ "abss.b \0" |
87 | 0 | /* 518 */ "sat.b \0" |
88 | 0 | /* 525 */ "dvinit.b \0" |
89 | 0 | /* 535 */ "lt.b \0" |
90 | 0 | /* 541 */ "st.b \0" |
91 | 0 | /* 547 */ "max.b \0" |
92 | 0 | /* 554 */ "eqany.b \0" |
93 | 0 | /* 563 */ "clz.b \0" |
94 | 0 | /* 570 */ "csub \0" |
95 | 0 | /* 576 */ "msub \0" |
96 | 0 | /* 582 */ "rsub \0" |
97 | 0 | /* 588 */ "subc \0" |
98 | 0 | /* 594 */ "addc \0" |
99 | 0 | /* 600 */ "ld.d \0" |
100 | 0 | /* 606 */ "st.d \0" |
101 | 0 | /* 612 */ "mov.d \0" |
102 | 0 | /* 619 */ "cadd \0" |
103 | 0 | /* 625 */ "madd \0" |
104 | 0 | /* 631 */ "jned \0" |
105 | 0 | /* 637 */ "nand \0" |
106 | 0 | /* 643 */ "and.ge \0" |
107 | 0 | /* 651 */ "sh.ge \0" |
108 | 0 | /* 658 */ "xor.ge \0" |
109 | 0 | /* 666 */ "jge \0" |
110 | 0 | /* 671 */ "bmerge \0" |
111 | 0 | /* 679 */ "disable \0" |
112 | 0 | /* 688 */ "shuffle \0" |
113 | 0 | /* 697 */ "and.ne \0" |
114 | 0 | /* 705 */ "sh.ne \0" |
115 | 0 | /* 712 */ "xor.ne \0" |
116 | 0 | /* 720 */ "jne \0" |
117 | 0 | /* 725 */ "restore \0" |
118 | 0 | /* 734 */ "msub.f \0" |
119 | 0 | /* 742 */ "madd.f \0" |
120 | 0 | /* 750 */ "qseed.f \0" |
121 | 0 | /* 759 */ "mul.f \0" |
122 | 0 | /* 766 */ "cmp.f \0" |
123 | 0 | /* 773 */ "div.f \0" |
124 | 0 | /* 780 */ "absdif \0" |
125 | 0 | /* 788 */ "q31tof \0" |
126 | 0 | /* 796 */ "itof \0" |
127 | 0 | /* 802 */ "hptof \0" |
128 | 0 | /* 809 */ "utof \0" |
129 | 0 | /* 815 */ "sha.h \0" |
130 | 0 | /* 822 */ "msub.h \0" |
131 | 0 | /* 830 */ "msubad.h \0" |
132 | 0 | /* 840 */ "madd.h \0" |
133 | 0 | /* 848 */ "ld.h \0" |
134 | 0 | /* 854 */ "absdif.h \0" |
135 | 0 | /* 864 */ "sh.h \0" |
136 | 0 | /* 870 */ "mul.h \0" |
137 | 0 | /* 877 */ "msubm.h \0" |
138 | 0 | /* 886 */ "msubadm.h \0" |
139 | 0 | /* 897 */ "maddm.h \0" |
140 | 0 | /* 906 */ "mulm.h \0" |
141 | 0 | /* 914 */ "maddsum.h \0" |
142 | 0 | /* 925 */ "min.h \0" |
143 | 0 | /* 932 */ "clo.h \0" |
144 | 0 | /* 939 */ "eq.h \0" |
145 | 0 | /* 945 */ "msubr.h \0" |
146 | 0 | /* 954 */ "msubadr.h \0" |
147 | 0 | /* 965 */ "maddr.h \0" |
148 | 0 | /* 974 */ "mulr.h \0" |
149 | 0 | /* 982 */ "maddsur.h \0" |
150 | 0 | /* 993 */ "abs.h \0" |
151 | 0 | /* 1000 */ "msubs.h \0" |
152 | 0 | /* 1009 */ "msubads.h \0" |
153 | 0 | /* 1020 */ "madds.h \0" |
154 | 0 | /* 1029 */ "absdifs.h \0" |
155 | 0 | /* 1040 */ "cls.h \0" |
156 | 0 | /* 1047 */ "msubms.h \0" |
157 | 0 | /* 1057 */ "msubadms.h \0" |
158 | 0 | /* 1069 */ "maddms.h \0" |
159 | 0 | /* 1079 */ "mulms.h \0" |
160 | 0 | /* 1088 */ "maddsums.h \0" |
161 | 0 | /* 1100 */ "msubrs.h \0" |
162 | 0 | /* 1110 */ "msubadrs.h \0" |
163 | 0 | /* 1122 */ "maddrs.h \0" |
164 | 0 | /* 1132 */ "maddsurs.h \0" |
165 | 0 | /* 1144 */ "abss.h \0" |
166 | 0 | /* 1152 */ "maddsus.h \0" |
167 | 0 | /* 1163 */ "sat.h \0" |
168 | 0 | /* 1170 */ "dvinit.h \0" |
169 | 0 | /* 1180 */ "lt.h \0" |
170 | 0 | /* 1186 */ "st.h \0" |
171 | 0 | /* 1192 */ "maddsu.h \0" |
172 | 0 | /* 1202 */ "max.h \0" |
173 | 0 | /* 1209 */ "eqany.h \0" |
174 | 0 | /* 1218 */ "clz.h \0" |
175 | 0 | /* 1225 */ "addih \0" |
176 | 0 | /* 1232 */ "sh \0" |
177 | 0 | /* 1236 */ "movh \0" |
178 | 0 | /* 1242 */ "tlbprobe.i \0" |
179 | 0 | /* 1254 */ "addi \0" |
180 | 0 | /* 1260 */ "jnei \0" |
181 | 0 | /* 1266 */ "ji \0" |
182 | 0 | /* 1270 */ "jli \0" |
183 | 0 | /* 1275 */ "fcalli \0" |
184 | 0 | /* 1283 */ "ftoi \0" |
185 | 0 | /* 1289 */ "dvadj \0" |
186 | 0 | /* 1296 */ "unpack \0" |
187 | 0 | /* 1304 */ "imask \0" |
188 | 0 | /* 1311 */ "sel \0" |
189 | 0 | /* 1316 */ "updfl \0" |
190 | 0 | /* 1323 */ "jl \0" |
191 | 0 | /* 1327 */ "fcall \0" |
192 | 0 | /* 1334 */ "syscall \0" |
193 | 0 | /* 1343 */ "mul \0" |
194 | 0 | /* 1348 */ "msubm \0" |
195 | 0 | /* 1355 */ "maddm \0" |
196 | 0 | /* 1362 */ "mulm \0" |
197 | 0 | /* 1368 */ "csubn \0" |
198 | 0 | /* 1375 */ "crcn \0" |
199 | 0 | /* 1381 */ "caddn \0" |
200 | 0 | /* 1388 */ "andn \0" |
201 | 0 | /* 1394 */ "ixmin \0" |
202 | 0 | /* 1401 */ "seln \0" |
203 | 0 | /* 1407 */ "orn \0" |
204 | 0 | /* 1412 */ "cmovn \0" |
205 | 0 | /* 1419 */ "clo \0" |
206 | 0 | /* 1424 */ "tlbmap \0" |
207 | 0 | /* 1432 */ "tlbdemap \0" |
208 | 0 | /* 1442 */ "dvstep \0" |
209 | 0 | /* 1450 */ "ftohp \0" |
210 | 0 | /* 1457 */ "loop \0" |
211 | 0 | /* 1463 */ "msub.q \0" |
212 | 0 | /* 1471 */ "madd.q \0" |
213 | 0 | /* 1479 */ "ld.q \0" |
214 | 0 | /* 1485 */ "mul.q \0" |
215 | 0 | /* 1492 */ "msubm.q \0" |
216 | 0 | /* 1501 */ "maddm.q \0" |
217 | 0 | /* 1510 */ "msubr.q \0" |
218 | 0 | /* 1519 */ "maddr.q \0" |
219 | 0 | /* 1528 */ "mulr.q \0" |
220 | 0 | /* 1536 */ "msubs.q \0" |
221 | 0 | /* 1545 */ "madds.q \0" |
222 | 0 | /* 1554 */ "msubrs.q \0" |
223 | 0 | /* 1564 */ "maddrs.q \0" |
224 | 0 | /* 1574 */ "st.q \0" |
225 | 0 | /* 1580 */ "and.eq \0" |
226 | 0 | /* 1588 */ "sh.eq \0" |
227 | 0 | /* 1595 */ "xor.eq \0" |
228 | 0 | /* 1603 */ "jeq \0" |
229 | 0 | /* 1608 */ "mfcr \0" |
230 | 0 | /* 1614 */ "mtcr \0" |
231 | 0 | /* 1620 */ "xnor \0" |
232 | 0 | /* 1626 */ "xor \0" |
233 | 0 | /* 1631 */ "bisr \0" |
234 | 0 | /* 1637 */ "dextr \0" |
235 | 0 | /* 1644 */ "shas \0" |
236 | 0 | /* 1650 */ "abs \0" |
237 | 0 | /* 1655 */ "msubs \0" |
238 | 0 | /* 1662 */ "rsubs \0" |
239 | 0 | /* 1669 */ "madds \0" |
240 | 0 | /* 1676 */ "absdifs \0" |
241 | 0 | /* 1685 */ "cls \0" |
242 | 0 | /* 1690 */ "muls \0" |
243 | 0 | /* 1696 */ "msubms \0" |
244 | 0 | /* 1704 */ "maddms \0" |
245 | 0 | /* 1712 */ "abss \0" |
246 | 0 | /* 1718 */ "and.and.t \0" |
247 | 0 | /* 1729 */ "sh.and.t \0" |
248 | 0 | /* 1739 */ "or.and.t \0" |
249 | 0 | /* 1749 */ "sh.nand.t \0" |
250 | 0 | /* 1760 */ "and.andn.t \0" |
251 | 0 | /* 1772 */ "sh.andn.t \0" |
252 | 0 | /* 1783 */ "or.andn.t \0" |
253 | 0 | /* 1794 */ "sh.orn.t \0" |
254 | 0 | /* 1804 */ "insn.t \0" |
255 | 0 | /* 1812 */ "and.or.t \0" |
256 | 0 | /* 1822 */ "sh.or.t \0" |
257 | 0 | /* 1831 */ "or.or.t \0" |
258 | 0 | /* 1840 */ "and.nor.t \0" |
259 | 0 | /* 1851 */ "sh.nor.t \0" |
260 | 0 | /* 1861 */ "or.nor.t \0" |
261 | 0 | /* 1871 */ "sh.xnor.t \0" |
262 | 0 | /* 1882 */ "sh.xor.t \0" |
263 | 0 | /* 1892 */ "ins.t \0" |
264 | 0 | /* 1899 */ "st.t \0" |
265 | 0 | /* 1905 */ "jz.t \0" |
266 | 0 | /* 1911 */ "jnz.t \0" |
267 | 0 | /* 1918 */ "addsc.at \0" |
268 | 0 | /* 1928 */ "bsplit \0" |
269 | 0 | /* 1936 */ "dvinit \0" |
270 | 0 | /* 1944 */ "and.lt \0" |
271 | 0 | /* 1952 */ "sh.lt \0" |
272 | 0 | /* 1959 */ "xor.lt \0" |
273 | 0 | /* 1967 */ "jlt \0" |
274 | 0 | /* 1972 */ "not \0" |
275 | 0 | /* 1977 */ "insert \0" |
276 | 0 | /* 1985 */ "ldmst \0" |
277 | 0 | /* 1992 */ "msub.u \0" |
278 | 0 | /* 2000 */ "madd.u \0" |
279 | 0 | /* 2008 */ "and.ge.u \0" |
280 | 0 | /* 2018 */ "sh.ge.u \0" |
281 | 0 | /* 2027 */ "xor.ge.u \0" |
282 | 0 | /* 2037 */ "jge.u \0" |
283 | 0 | /* 2044 */ "mul.u \0" |
284 | 0 | /* 2051 */ "msubm.u \0" |
285 | 0 | /* 2060 */ "maddm.u \0" |
286 | 0 | /* 2069 */ "mulm.u \0" |
287 | 0 | /* 2077 */ "ixmin.u \0" |
288 | 0 | /* 2086 */ "dvstep.u \0" |
289 | 0 | /* 2096 */ "extr.u \0" |
290 | 0 | /* 2104 */ "msubs.u \0" |
291 | 0 | /* 2113 */ "rsubs.u \0" |
292 | 0 | /* 2122 */ "madds.u \0" |
293 | 0 | /* 2131 */ "muls.u \0" |
294 | 0 | /* 2139 */ "msubms.u \0" |
295 | 0 | /* 2149 */ "maddms.u \0" |
296 | 0 | /* 2159 */ "dvinit.u \0" |
297 | 0 | /* 2169 */ "and.lt.u \0" |
298 | 0 | /* 2179 */ "sh.lt.u \0" |
299 | 0 | /* 2188 */ "xor.lt.u \0" |
300 | 0 | /* 2198 */ "jlt.u \0" |
301 | 0 | /* 2205 */ "div.u \0" |
302 | 0 | /* 2212 */ "mov.u \0" |
303 | 0 | /* 2219 */ "ixmax.u \0" |
304 | 0 | /* 2228 */ "ld.bu \0" |
305 | 0 | /* 2235 */ "min.bu \0" |
306 | 0 | /* 2243 */ "subs.bu \0" |
307 | 0 | /* 2252 */ "adds.bu \0" |
308 | 0 | /* 2261 */ "sat.bu \0" |
309 | 0 | /* 2269 */ "dvinit.bu \0" |
310 | 0 | /* 2280 */ "lt.bu \0" |
311 | 0 | /* 2287 */ "max.bu \0" |
312 | 0 | /* 2295 */ "ld.hu \0" |
313 | 0 | /* 2302 */ "min.hu \0" |
314 | 0 | /* 2310 */ "subs.hu \0" |
315 | 0 | /* 2319 */ "adds.hu \0" |
316 | 0 | /* 2328 */ "sat.hu \0" |
317 | 0 | /* 2336 */ "dvinit.hu \0" |
318 | 0 | /* 2347 */ "lt.hu \0" |
319 | 0 | /* 2354 */ "max.hu \0" |
320 | 0 | /* 2362 */ "ftou \0" |
321 | 0 | /* 2368 */ "loopu \0" |
322 | 0 | /* 2375 */ "lt.wu \0" |
323 | 0 | /* 2382 */ "div \0" |
324 | 0 | /* 2387 */ "cmov \0" |
325 | 0 | /* 2393 */ "crc32b.w \0" |
326 | 0 | /* 2403 */ "ld.w \0" |
327 | 0 | /* 2409 */ "crc32l.w \0" |
328 | 0 | /* 2419 */ "swap.w \0" |
329 | 0 | /* 2427 */ "eq.w \0" |
330 | 0 | /* 2433 */ "lt.w \0" |
331 | 0 | /* 2439 */ "popcnt.w \0" |
332 | 0 | /* 2449 */ "st.w \0" |
333 | 0 | /* 2455 */ "ixmax \0" |
334 | 0 | /* 2462 */ "subx \0" |
335 | 0 | /* 2468 */ "ldlcx \0" |
336 | 0 | /* 2475 */ "stlcx \0" |
337 | 0 | /* 2482 */ "lducx \0" |
338 | 0 | /* 2489 */ "stucx \0" |
339 | 0 | /* 2496 */ "addx \0" |
340 | 0 | /* 2502 */ "parity \0" |
341 | 0 | /* 2510 */ "ftoq31z \0" |
342 | 0 | /* 2519 */ "jgez \0" |
343 | 0 | /* 2525 */ "jlez \0" |
344 | 0 | /* 2531 */ "ftoiz \0" |
345 | 0 | /* 2538 */ "jz \0" |
346 | 0 | /* 2542 */ "clz \0" |
347 | 0 | /* 2547 */ "jnz \0" |
348 | 0 | /* 2552 */ "jgtz \0" |
349 | 0 | /* 2558 */ "jltz \0" |
350 | 0 | /* 2564 */ "ftouz \0" |
351 | 0 | /* 2571 */ "swap.a [+\0" |
352 | 0 | /* 2581 */ "st.a [+\0" |
353 | 0 | /* 2589 */ "st.da [+\0" |
354 | 0 | /* 2598 */ "st.b [+\0" |
355 | 0 | /* 2606 */ "st.d [+\0" |
356 | 0 | /* 2614 */ "st.h [+\0" |
357 | 0 | /* 2622 */ "cachea.i [+\0" |
358 | 0 | /* 2634 */ "cachei.i [+\0" |
359 | 0 | /* 2646 */ "cachea.wi [+\0" |
360 | 0 | /* 2659 */ "cachei.wi [+\0" |
361 | 0 | /* 2672 */ "st.q [+\0" |
362 | 0 | /* 2680 */ "ldmst [+\0" |
363 | 0 | /* 2689 */ "cachea.w [+\0" |
364 | 0 | /* 2701 */ "cachei.w [+\0" |
365 | 0 | /* 2713 */ "swapmsk.w [+\0" |
366 | 0 | /* 2726 */ "cmpswap.w [+\0" |
367 | 0 | /* 2739 */ "st.w [+\0" |
368 | 0 | /* 2747 */ "# XRay Function Patchable RET.\0" |
369 | 0 | /* 2778 */ "# XRay Typed Event Log.\0" |
370 | 0 | /* 2802 */ "# XRay Custom Event Log.\0" |
371 | 0 | /* 2827 */ "# XRay Function Enter.\0" |
372 | 0 | /* 2850 */ "# XRay Tail Call Exit.\0" |
373 | 0 | /* 2873 */ "# XRay Function Exit.\0" |
374 | 0 | /* 2895 */ "LIFETIME_END\0" |
375 | 0 | /* 2908 */ "PSEUDO_PROBE\0" |
376 | 0 | /* 2921 */ "BUNDLE\0" |
377 | 0 | /* 2928 */ "DBG_VALUE\0" |
378 | 0 | /* 2938 */ "DBG_INSTR_REF\0" |
379 | 0 | /* 2952 */ "DBG_PHI\0" |
380 | 0 | /* 2960 */ "DBG_LABEL\0" |
381 | 0 | /* 2970 */ "LIFETIME_START\0" |
382 | 0 | /* 2985 */ "DBG_VALUE_LIST\0" |
383 | 0 | /* 3000 */ "ld.a a15, [\0" |
384 | 0 | /* 3012 */ "ld.b d15, [\0" |
385 | 0 | /* 3024 */ "ld.h d15, [\0" |
386 | 0 | /* 3036 */ "ld.bu d15, [\0" |
387 | 0 | /* 3049 */ "ld.w d15, [\0" |
388 | 0 | /* 3061 */ "swap.a [\0" |
389 | 0 | /* 3070 */ "st.a [\0" |
390 | 0 | /* 3077 */ "st.da [\0" |
391 | 0 | /* 3085 */ "st.b [\0" |
392 | 0 | /* 3092 */ "st.d [\0" |
393 | 0 | /* 3099 */ "st.h [\0" |
394 | 0 | /* 3106 */ "cachea.i [\0" |
395 | 0 | /* 3117 */ "cachei.i [\0" |
396 | 0 | /* 3128 */ "cachea.wi [\0" |
397 | 0 | /* 3140 */ "cachei.wi [\0" |
398 | 0 | /* 3152 */ "st.q [\0" |
399 | 0 | /* 3159 */ "ldmst [\0" |
400 | 0 | /* 3167 */ "cachea.w [\0" |
401 | 0 | /* 3178 */ "cachei.w [\0" |
402 | 0 | /* 3189 */ "swapmsk.w [\0" |
403 | 0 | /* 3201 */ "cmpswap.w [\0" |
404 | 0 | /* 3213 */ "st.w [\0" |
405 | 0 | /* 3220 */ "ldlcx [\0" |
406 | 0 | /* 3228 */ "stlcx [\0" |
407 | 0 | /* 3236 */ "lducx [\0" |
408 | 0 | /* 3244 */ "stucx [\0" |
409 | 0 | /* 3252 */ "st.a [a15]\0" |
410 | 0 | /* 3263 */ "st.b [a15]\0" |
411 | 0 | /* 3274 */ "st.h [a15]\0" |
412 | 0 | /* 3285 */ "st.w [a15]\0" |
413 | 0 | /* 3296 */ "ld.a a15, [sp]\0" |
414 | 0 | /* 3311 */ "ld.w d15, [sp]\0" |
415 | 0 | /* 3326 */ "st.a [sp]\0" |
416 | 0 | /* 3336 */ "st.w [sp]\0" |
417 | 0 | /* 3346 */ "tlbflush.a\0" |
418 | 0 | /* 3357 */ "tlbflush.b\0" |
419 | 0 | /* 3368 */ "dsync\0" |
420 | 0 | /* 3374 */ "isync\0" |
421 | 0 | /* 3380 */ "rfe\0" |
422 | 0 | /* 3384 */ "enable\0" |
423 | 0 | /* 3391 */ "disable\0" |
424 | 0 | /* 3399 */ "debug\0" |
425 | 0 | /* 3405 */ "# FEntry call\0" |
426 | 0 | /* 3419 */ "rfm\0" |
427 | 0 | /* 3423 */ "nop\0" |
428 | 0 | /* 3427 */ "fret\0" |
429 | 0 | /* 3432 */ "wait\0" |
430 | 0 | /* 3437 */ "trapv\0" |
431 | 0 | /* 3443 */ "trapsv\0" |
432 | 0 | /* 3450 */ "rstv\0" |
433 | 0 | /* 3455 */ "rslcx\0" |
434 | 0 | /* 3461 */ "svlcx\0" |
435 | 0 | }; |
436 | 0 | #endif // CAPSTONE_DIET |
437 | |
|
438 | 0 | static const uint32_t OpInfo0[] = { |
439 | 0 | 0U, // PHI |
440 | 0 | 0U, // INLINEASM |
441 | 0 | 0U, // INLINEASM_BR |
442 | 0 | 0U, // CFI_INSTRUCTION |
443 | 0 | 0U, // EH_LABEL |
444 | 0 | 0U, // GC_LABEL |
445 | 0 | 0U, // ANNOTATION_LABEL |
446 | 0 | 0U, // KILL |
447 | 0 | 0U, // EXTRACT_SUBREG |
448 | 0 | 0U, // INSERT_SUBREG |
449 | 0 | 0U, // IMPLICIT_DEF |
450 | 0 | 0U, // SUBREG_TO_REG |
451 | 0 | 0U, // COPY_TO_REGCLASS |
452 | 0 | 2929U, // DBG_VALUE |
453 | 0 | 2986U, // DBG_VALUE_LIST |
454 | 0 | 2939U, // DBG_INSTR_REF |
455 | 0 | 2953U, // DBG_PHI |
456 | 0 | 2961U, // DBG_LABEL |
457 | 0 | 0U, // REG_SEQUENCE |
458 | 0 | 0U, // COPY |
459 | 0 | 2922U, // BUNDLE |
460 | 0 | 2971U, // LIFETIME_START |
461 | 0 | 2896U, // LIFETIME_END |
462 | 0 | 2909U, // PSEUDO_PROBE |
463 | 0 | 0U, // ARITH_FENCE |
464 | 0 | 0U, // STACKMAP |
465 | 0 | 3406U, // FENTRY_CALL |
466 | 0 | 0U, // PATCHPOINT |
467 | 0 | 0U, // LOAD_STACK_GUARD |
468 | 0 | 0U, // PREALLOCATED_SETUP |
469 | 0 | 0U, // PREALLOCATED_ARG |
470 | 0 | 0U, // STATEPOINT |
471 | 0 | 0U, // LOCAL_ESCAPE |
472 | 0 | 0U, // FAULTING_OP |
473 | 0 | 0U, // PATCHABLE_OP |
474 | 0 | 2828U, // PATCHABLE_FUNCTION_ENTER |
475 | 0 | 2748U, // PATCHABLE_RET |
476 | 0 | 2874U, // PATCHABLE_FUNCTION_EXIT |
477 | 0 | 2851U, // PATCHABLE_TAIL_CALL |
478 | 0 | 2803U, // PATCHABLE_EVENT_CALL |
479 | 0 | 2779U, // PATCHABLE_TYPED_EVENT_CALL |
480 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
481 | 0 | 0U, // MEMBARRIER |
482 | 0 | 0U, // G_ASSERT_SEXT |
483 | 0 | 0U, // G_ASSERT_ZEXT |
484 | 0 | 0U, // G_ASSERT_ALIGN |
485 | 0 | 0U, // G_ADD |
486 | 0 | 0U, // G_SUB |
487 | 0 | 0U, // G_MUL |
488 | 0 | 0U, // G_SDIV |
489 | 0 | 0U, // G_UDIV |
490 | 0 | 0U, // G_SREM |
491 | 0 | 0U, // G_UREM |
492 | 0 | 0U, // G_SDIVREM |
493 | 0 | 0U, // G_UDIVREM |
494 | 0 | 0U, // G_AND |
495 | 0 | 0U, // G_OR |
496 | 0 | 0U, // G_XOR |
497 | 0 | 0U, // G_IMPLICIT_DEF |
498 | 0 | 0U, // G_PHI |
499 | 0 | 0U, // G_FRAME_INDEX |
500 | 0 | 0U, // G_GLOBAL_VALUE |
501 | 0 | 0U, // G_EXTRACT |
502 | 0 | 0U, // G_UNMERGE_VALUES |
503 | 0 | 0U, // G_INSERT |
504 | 0 | 0U, // G_MERGE_VALUES |
505 | 0 | 0U, // G_BUILD_VECTOR |
506 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
507 | 0 | 0U, // G_CONCAT_VECTORS |
508 | 0 | 0U, // G_PTRTOINT |
509 | 0 | 0U, // G_INTTOPTR |
510 | 0 | 0U, // G_BITCAST |
511 | 0 | 0U, // G_FREEZE |
512 | 0 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
513 | 0 | 0U, // G_INTRINSIC_TRUNC |
514 | 0 | 0U, // G_INTRINSIC_ROUND |
515 | 0 | 0U, // G_INTRINSIC_LRINT |
516 | 0 | 0U, // G_INTRINSIC_ROUNDEVEN |
517 | 0 | 0U, // G_READCYCLECOUNTER |
518 | 0 | 0U, // G_LOAD |
519 | 0 | 0U, // G_SEXTLOAD |
520 | 0 | 0U, // G_ZEXTLOAD |
521 | 0 | 0U, // G_INDEXED_LOAD |
522 | 0 | 0U, // G_INDEXED_SEXTLOAD |
523 | 0 | 0U, // G_INDEXED_ZEXTLOAD |
524 | 0 | 0U, // G_STORE |
525 | 0 | 0U, // G_INDEXED_STORE |
526 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
527 | 0 | 0U, // G_ATOMIC_CMPXCHG |
528 | 0 | 0U, // G_ATOMICRMW_XCHG |
529 | 0 | 0U, // G_ATOMICRMW_ADD |
530 | 0 | 0U, // G_ATOMICRMW_SUB |
531 | 0 | 0U, // G_ATOMICRMW_AND |
532 | 0 | 0U, // G_ATOMICRMW_NAND |
533 | 0 | 0U, // G_ATOMICRMW_OR |
534 | 0 | 0U, // G_ATOMICRMW_XOR |
535 | 0 | 0U, // G_ATOMICRMW_MAX |
536 | 0 | 0U, // G_ATOMICRMW_MIN |
537 | 0 | 0U, // G_ATOMICRMW_UMAX |
538 | 0 | 0U, // G_ATOMICRMW_UMIN |
539 | 0 | 0U, // G_ATOMICRMW_FADD |
540 | 0 | 0U, // G_ATOMICRMW_FSUB |
541 | 0 | 0U, // G_ATOMICRMW_FMAX |
542 | 0 | 0U, // G_ATOMICRMW_FMIN |
543 | 0 | 0U, // G_ATOMICRMW_UINC_WRAP |
544 | 0 | 0U, // G_ATOMICRMW_UDEC_WRAP |
545 | 0 | 0U, // G_FENCE |
546 | 0 | 0U, // G_BRCOND |
547 | 0 | 0U, // G_BRINDIRECT |
548 | 0 | 0U, // G_INVOKE_REGION_START |
549 | 0 | 0U, // G_INTRINSIC |
550 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
551 | 0 | 0U, // G_ANYEXT |
552 | 0 | 0U, // G_TRUNC |
553 | 0 | 0U, // G_CONSTANT |
554 | 0 | 0U, // G_FCONSTANT |
555 | 0 | 0U, // G_VASTART |
556 | 0 | 0U, // G_VAARG |
557 | 0 | 0U, // G_SEXT |
558 | 0 | 0U, // G_SEXT_INREG |
559 | 0 | 0U, // G_ZEXT |
560 | 0 | 0U, // G_SHL |
561 | 0 | 0U, // G_LSHR |
562 | 0 | 0U, // G_ASHR |
563 | 0 | 0U, // G_FSHL |
564 | 0 | 0U, // G_FSHR |
565 | 0 | 0U, // G_ROTR |
566 | 0 | 0U, // G_ROTL |
567 | 0 | 0U, // G_ICMP |
568 | 0 | 0U, // G_FCMP |
569 | 0 | 0U, // G_SELECT |
570 | 0 | 0U, // G_UADDO |
571 | 0 | 0U, // G_UADDE |
572 | 0 | 0U, // G_USUBO |
573 | 0 | 0U, // G_USUBE |
574 | 0 | 0U, // G_SADDO |
575 | 0 | 0U, // G_SADDE |
576 | 0 | 0U, // G_SSUBO |
577 | 0 | 0U, // G_SSUBE |
578 | 0 | 0U, // G_UMULO |
579 | 0 | 0U, // G_SMULO |
580 | 0 | 0U, // G_UMULH |
581 | 0 | 0U, // G_SMULH |
582 | 0 | 0U, // G_UADDSAT |
583 | 0 | 0U, // G_SADDSAT |
584 | 0 | 0U, // G_USUBSAT |
585 | 0 | 0U, // G_SSUBSAT |
586 | 0 | 0U, // G_USHLSAT |
587 | 0 | 0U, // G_SSHLSAT |
588 | 0 | 0U, // G_SMULFIX |
589 | 0 | 0U, // G_UMULFIX |
590 | 0 | 0U, // G_SMULFIXSAT |
591 | 0 | 0U, // G_UMULFIXSAT |
592 | 0 | 0U, // G_SDIVFIX |
593 | 0 | 0U, // G_UDIVFIX |
594 | 0 | 0U, // G_SDIVFIXSAT |
595 | 0 | 0U, // G_UDIVFIXSAT |
596 | 0 | 0U, // G_FADD |
597 | 0 | 0U, // G_FSUB |
598 | 0 | 0U, // G_FMUL |
599 | 0 | 0U, // G_FMA |
600 | 0 | 0U, // G_FMAD |
601 | 0 | 0U, // G_FDIV |
602 | 0 | 0U, // G_FREM |
603 | 0 | 0U, // G_FPOW |
604 | 0 | 0U, // G_FPOWI |
605 | 0 | 0U, // G_FEXP |
606 | 0 | 0U, // G_FEXP2 |
607 | 0 | 0U, // G_FLOG |
608 | 0 | 0U, // G_FLOG2 |
609 | 0 | 0U, // G_FLOG10 |
610 | 0 | 0U, // G_FNEG |
611 | 0 | 0U, // G_FPEXT |
612 | 0 | 0U, // G_FPTRUNC |
613 | 0 | 0U, // G_FPTOSI |
614 | 0 | 0U, // G_FPTOUI |
615 | 0 | 0U, // G_SITOFP |
616 | 0 | 0U, // G_UITOFP |
617 | 0 | 0U, // G_FABS |
618 | 0 | 0U, // G_FCOPYSIGN |
619 | 0 | 0U, // G_IS_FPCLASS |
620 | 0 | 0U, // G_FCANONICALIZE |
621 | 0 | 0U, // G_FMINNUM |
622 | 0 | 0U, // G_FMAXNUM |
623 | 0 | 0U, // G_FMINNUM_IEEE |
624 | 0 | 0U, // G_FMAXNUM_IEEE |
625 | 0 | 0U, // G_FMINIMUM |
626 | 0 | 0U, // G_FMAXIMUM |
627 | 0 | 0U, // G_PTR_ADD |
628 | 0 | 0U, // G_PTRMASK |
629 | 0 | 0U, // G_SMIN |
630 | 0 | 0U, // G_SMAX |
631 | 0 | 0U, // G_UMIN |
632 | 0 | 0U, // G_UMAX |
633 | 0 | 0U, // G_ABS |
634 | 0 | 0U, // G_LROUND |
635 | 0 | 0U, // G_LLROUND |
636 | 0 | 0U, // G_BR |
637 | 0 | 0U, // G_BRJT |
638 | 0 | 0U, // G_INSERT_VECTOR_ELT |
639 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
640 | 0 | 0U, // G_SHUFFLE_VECTOR |
641 | 0 | 0U, // G_CTTZ |
642 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
643 | 0 | 0U, // G_CTLZ |
644 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
645 | 0 | 0U, // G_CTPOP |
646 | 0 | 0U, // G_BSWAP |
647 | 0 | 0U, // G_BITREVERSE |
648 | 0 | 0U, // G_FCEIL |
649 | 0 | 0U, // G_FCOS |
650 | 0 | 0U, // G_FSIN |
651 | 0 | 0U, // G_FSQRT |
652 | 0 | 0U, // G_FFLOOR |
653 | 0 | 0U, // G_FRINT |
654 | 0 | 0U, // G_FNEARBYINT |
655 | 0 | 0U, // G_ADDRSPACE_CAST |
656 | 0 | 0U, // G_BLOCK_ADDR |
657 | 0 | 0U, // G_JUMP_TABLE |
658 | 0 | 0U, // G_DYN_STACKALLOC |
659 | 0 | 0U, // G_STRICT_FADD |
660 | 0 | 0U, // G_STRICT_FSUB |
661 | 0 | 0U, // G_STRICT_FMUL |
662 | 0 | 0U, // G_STRICT_FDIV |
663 | 0 | 0U, // G_STRICT_FREM |
664 | 0 | 0U, // G_STRICT_FMA |
665 | 0 | 0U, // G_STRICT_FSQRT |
666 | 0 | 0U, // G_READ_REGISTER |
667 | 0 | 0U, // G_WRITE_REGISTER |
668 | 0 | 0U, // G_MEMCPY |
669 | 0 | 0U, // G_MEMCPY_INLINE |
670 | 0 | 0U, // G_MEMMOVE |
671 | 0 | 0U, // G_MEMSET |
672 | 0 | 0U, // G_BZERO |
673 | 0 | 0U, // G_VECREDUCE_SEQ_FADD |
674 | 0 | 0U, // G_VECREDUCE_SEQ_FMUL |
675 | 0 | 0U, // G_VECREDUCE_FADD |
676 | 0 | 0U, // G_VECREDUCE_FMUL |
677 | 0 | 0U, // G_VECREDUCE_FMAX |
678 | 0 | 0U, // G_VECREDUCE_FMIN |
679 | 0 | 0U, // G_VECREDUCE_ADD |
680 | 0 | 0U, // G_VECREDUCE_MUL |
681 | 0 | 0U, // G_VECREDUCE_AND |
682 | 0 | 0U, // G_VECREDUCE_OR |
683 | 0 | 0U, // G_VECREDUCE_XOR |
684 | 0 | 0U, // G_VECREDUCE_SMAX |
685 | 0 | 0U, // G_VECREDUCE_SMIN |
686 | 0 | 0U, // G_VECREDUCE_UMAX |
687 | 0 | 0U, // G_VECREDUCE_UMIN |
688 | 0 | 0U, // G_SBFX |
689 | 0 | 0U, // G_UBFX |
690 | 0 | 4589U, // ABSDIFS_B_rr_v110 |
691 | 0 | 5126U, // ABSDIFS_H_rr |
692 | 0 | 5773U, // ABSDIFS_rc |
693 | 0 | 5773U, // ABSDIFS_rr |
694 | 0 | 4530U, // ABSDIF_B_rr |
695 | 0 | 4951U, // ABSDIF_H_rr |
696 | 0 | 536875789U, // ABSDIF_rc |
697 | 0 | 4877U, // ABSDIF_rr |
698 | 0 | 34607615U, // ABSS_B_rr_v110 |
699 | 0 | 34608249U, // ABSS_H_rr |
700 | 0 | 34608817U, // ABSS_rr |
701 | 0 | 33558998U, // ABS_B_rr |
702 | 0 | 33559522U, // ABS_H_rr |
703 | 0 | 33560179U, // ABS_rr |
704 | 0 | 536875603U, // ADDC_rc |
705 | 0 | 4691U, // ADDC_rr |
706 | 0 | 1073746145U, // ADDIH_A_rlc |
707 | 0 | 1073747146U, // ADDIH_rlc |
708 | 0 | 1610618087U, // ADDI_rlc |
709 | 0 | 2148538239U, // ADDSC_AT_rr |
710 | 0 | 6015U, // ADDSC_AT_rr_v110 |
711 | 0 | 2148536488U, // ADDSC_A_rr |
712 | 0 | 4264U, // ADDSC_A_rr_v110 |
713 | 0 | 67113128U, // ADDSC_A_srrs |
714 | 0 | 2684358824U, // ADDSC_A_srrs_v110 |
715 | 0 | 6349U, // ADDS_BU_rr_v110 |
716 | 0 | 4581U, // ADDS_B_rr |
717 | 0 | 5118U, // ADDS_H |
718 | 0 | 6416U, // ADDS_HU |
719 | 0 | 6220U, // ADDS_U |
720 | 0 | 536877132U, // ADDS_U_rc |
721 | 0 | 536876679U, // ADDS_rc |
722 | 0 | 5767U, // ADDS_rr |
723 | 0 | 33560199U, // ADDS_srr |
724 | 0 | 536877505U, // ADDX_rc |
725 | 0 | 6593U, // ADDX_rr |
726 | 0 | 4283U, // ADD_A_rr |
727 | 0 | 35655867U, // ADD_A_src |
728 | 0 | 33558715U, // ADD_A_srr |
729 | 0 | 4517U, // ADD_B_rr |
730 | 0 | 3325039336U, // ADD_F_rrr |
731 | 0 | 4938U, // ADD_H_rr |
732 | 0 | 536875629U, // ADD_rc |
733 | 0 | 4717U, // ADD_rr |
734 | 0 | 35656301U, // ADD_src |
735 | 0 | 35655691U, // ADD_src_15a |
736 | 0 | 35721837U, // ADD_src_a15 |
737 | 0 | 33559149U, // ADD_srr |
738 | 0 | 33558539U, // ADD_srr_15a |
739 | 0 | 33624685U, // ADD_srr_a15 |
740 | 0 | 3758102245U, // ANDN_T |
741 | 0 | 536876397U, // ANDN_rc |
742 | 0 | 5485U, // ANDN_rr |
743 | 0 | 3758102241U, // AND_ANDN_T |
744 | 0 | 3758102199U, // AND_AND_T |
745 | 0 | 536876589U, // AND_EQ_rc |
746 | 0 | 5677U, // AND_EQ_rr |
747 | 0 | 536877017U, // AND_GE_U_rc |
748 | 0 | 6105U, // AND_GE_U_rr |
749 | 0 | 536875652U, // AND_GE_rc |
750 | 0 | 4740U, // AND_GE_rr |
751 | 0 | 536877178U, // AND_LT_U_rc |
752 | 0 | 6266U, // AND_LT_U_rr |
753 | 0 | 536876953U, // AND_LT_rc |
754 | 0 | 6041U, // AND_LT_rr |
755 | 0 | 536875706U, // AND_NE_rc |
756 | 0 | 4794U, // AND_NE_rr |
757 | 0 | 3758102321U, // AND_NOR_T |
758 | 0 | 3758102293U, // AND_OR_T |
759 | 0 | 3758102203U, // AND_T |
760 | 0 | 536875647U, // AND_rc |
761 | 0 | 4735U, // AND_rr |
762 | 0 | 139285U, // AND_sc |
763 | 0 | 139285U, // AND_sc_v110 |
764 | 0 | 33559167U, // AND_srr |
765 | 0 | 33559167U, // AND_srr_v110 |
766 | 0 | 13920U, // BISR_rc |
767 | 0 | 13920U, // BISR_rc_v161 |
768 | 0 | 140896U, // BISR_sc |
769 | 0 | 140896U, // BISR_sc_v110 |
770 | 0 | 4768U, // BMERGAE_rr_v110 |
771 | 0 | 4768U, // BMERGE_rr |
772 | 0 | 33560457U, // BSPLIT_rr |
773 | 0 | 33560457U, // BSPLIT_rr_v110 |
774 | 0 | 4398115U, // CACHEA_I_bo_bso |
775 | 0 | 4463651U, // CACHEA_I_bo_c |
776 | 0 | 4529187U, // CACHEA_I_bo_pos |
777 | 0 | 4397631U, // CACHEA_I_bo_pre |
778 | 0 | 400419U, // CACHEA_I_bo_r |
779 | 0 | 4398137U, // CACHEA_WI_bo_bso |
780 | 0 | 4463673U, // CACHEA_WI_bo_c |
781 | 0 | 4529209U, // CACHEA_WI_bo_pos |
782 | 0 | 4397655U, // CACHEA_WI_bo_pre |
783 | 0 | 400441U, // CACHEA_WI_bo_r |
784 | 0 | 4398176U, // CACHEA_W_bo_bso |
785 | 0 | 4463712U, // CACHEA_W_bo_c |
786 | 0 | 4529248U, // CACHEA_W_bo_pos |
787 | 0 | 4397698U, // CACHEA_W_bo_pre |
788 | 0 | 400480U, // CACHEA_W_bo_r |
789 | 0 | 4398126U, // CACHEI_I_bo_bso |
790 | 0 | 4529198U, // CACHEI_I_bo_pos |
791 | 0 | 4397643U, // CACHEI_I_bo_pre |
792 | 0 | 4398149U, // CACHEI_WI_bo_bso |
793 | 0 | 4529221U, // CACHEI_WI_bo_pos |
794 | 0 | 4397668U, // CACHEI_WI_bo_pre |
795 | 0 | 4398187U, // CACHEI_W_bo_bso |
796 | 0 | 4529259U, // CACHEI_W_bo_pos |
797 | 0 | 4397710U, // CACHEI_W_bo_pre |
798 | 0 | 2148536578U, // CADDN_A_rcr_v110 |
799 | 0 | 103813378U, // CADDN_A_rrr_v110 |
800 | 0 | 2148537702U, // CADDN_rcr |
801 | 0 | 103814502U, // CADDN_rrr |
802 | 0 | 35722598U, // CADDN_src |
803 | 0 | 33625446U, // CADDN_srr_v110 |
804 | 0 | 2148536506U, // CADD_A_rcr_v110 |
805 | 0 | 103813306U, // CADD_A_rrr_v110 |
806 | 0 | 2148536940U, // CADD_rcr |
807 | 0 | 103813740U, // CADD_rrr |
808 | 0 | 35721836U, // CADD_src |
809 | 0 | 33624684U, // CADD_srr_v110 |
810 | 0 | 16775U, // CALLA_b |
811 | 0 | 136445U, // CALLI_rr |
812 | 0 | 136445U, // CALLI_rr_v110 |
813 | 0 | 17713U, // CALL_b |
814 | 0 | 21809U, // CALL_sb |
815 | 0 | 33558985U, // CLO_B_rr_v110 |
816 | 0 | 33559461U, // CLO_H_rr |
817 | 0 | 33559948U, // CLO_rr |
818 | 0 | 33559032U, // CLS_B_rr_v110 |
819 | 0 | 33559569U, // CLS_H_rr |
820 | 0 | 33560214U, // CLS_rr |
821 | 0 | 33559092U, // CLZ_B_rr_v110 |
822 | 0 | 33559747U, // CLZ_H_rr |
823 | 0 | 33561071U, // CLZ_rr |
824 | 0 | 35722629U, // CMOVN_src |
825 | 0 | 33625477U, // CMOVN_srr |
826 | 0 | 35723604U, // CMOV_src |
827 | 0 | 33626452U, // CMOV_srr |
828 | 0 | 139684994U, // CMPSWAP_W_bo_bso |
829 | 0 | 139750530U, // CMPSWAP_W_bo_c |
830 | 0 | 139816066U, // CMPSWAP_W_bo_pos |
831 | 0 | 139684519U, // CMPSWAP_W_bo_pre |
832 | 0 | 6777986U, // CMPSWAP_W_bo_r |
833 | 0 | 4863U, // CMP_F_rr |
834 | 0 | 2148538714U, // CRC32B_W_rr |
835 | 0 | 2148538730U, // CRC32L_W_rr |
836 | 0 | 2148536718U, // CRC32_B_rr |
837 | 0 | 103814496U, // CRCN_rrr |
838 | 0 | 103813369U, // CSUBN_A__rrr_v110 |
839 | 0 | 103814489U, // CSUBN_rrr |
840 | 0 | 103813271U, // CSUB_A__rrr_v110 |
841 | 0 | 103813691U, // CSUB_rrr |
842 | 0 | 3400U, // DEBUG_sr |
843 | 0 | 3400U, // DEBUG_sys |
844 | 0 | 5734U, // DEXTR_rrpw |
845 | 0 | 5734U, // DEXTR_rrrr |
846 | 0 | 4273U, // DIFSC_A_rr_v110 |
847 | 0 | 3392U, // DISABLE_sys |
848 | 0 | 135848U, // DISABLE_sys_1 |
849 | 0 | 4870U, // DIV_F_rr |
850 | 0 | 6302U, // DIV_U_rr |
851 | 0 | 6479U, // DIV_rr |
852 | 0 | 3369U, // DSYNC_sys |
853 | 0 | 3392148746U, // DVADJ_rrr |
854 | 0 | 3392148746U, // DVADJ_rrr_v110 |
855 | 0 | 33559818U, // DVADJ_srr_v110 |
856 | 0 | 6366U, // DVINIT_BU_rr |
857 | 0 | 6366U, // DVINIT_BU_rr_v110 |
858 | 0 | 4622U, // DVINIT_B_rr |
859 | 0 | 4622U, // DVINIT_B_rr_v110 |
860 | 0 | 6433U, // DVINIT_HU_rr |
861 | 0 | 6433U, // DVINIT_HU_rr_v110 |
862 | 0 | 5267U, // DVINIT_H_rr |
863 | 0 | 5267U, // DVINIT_H_rr_v110 |
864 | 0 | 6256U, // DVINIT_U_rr |
865 | 0 | 6256U, // DVINIT_U_rr_v110 |
866 | 0 | 6033U, // DVINIT_rr |
867 | 0 | 6033U, // DVINIT_rr_v110 |
868 | 0 | 3392149543U, // DVSTEP_U_rrr |
869 | 0 | 3392149543U, // DVSTEP_U_rrrv110 |
870 | 0 | 33560615U, // DVSTEP_Uv110 |
871 | 0 | 3392148899U, // DVSTEP_rrr |
872 | 0 | 3392148899U, // DVSTEP_rrrv110 |
873 | 0 | 33559971U, // DVSTEPv110 |
874 | 0 | 3385U, // ENABLE_sys |
875 | 0 | 536875563U, // EQANY_B_rc |
876 | 0 | 4651U, // EQANY_B_rr |
877 | 0 | 536876218U, // EQANY_H_rc |
878 | 0 | 5306U, // EQANY_H_rr |
879 | 0 | 33558857U, // EQZ_A_rr |
880 | 0 | 4380U, // EQ_A_rr |
881 | 0 | 4560U, // EQ_B_rr |
882 | 0 | 5036U, // EQ_H_rr |
883 | 0 | 6524U, // EQ_W_rr |
884 | 0 | 536876593U, // EQ_rc |
885 | 0 | 5681U, // EQ_rr |
886 | 0 | 35655722U, // EQ_src |
887 | 0 | 33558570U, // EQ_srr |
888 | 0 | 536877105U, // EXTR_U_rrpw |
889 | 0 | 6193U, // EXTR_U_rrrr |
890 | 0 | 536877105U, // EXTR_U_rrrw |
891 | 0 | 536876647U, // EXTR_rrpw |
892 | 0 | 5735U, // EXTR_rrrr |
893 | 0 | 536876647U, // EXTR_rrrw |
894 | 0 | 16774U, // FCALLA_b |
895 | 0 | 136444U, // FCALLA_i |
896 | 0 | 17712U, // FCALL_b |
897 | 0 | 3428U, // FRET_sr |
898 | 0 | 3428U, // FRET_sys |
899 | 0 | 33559979U, // FTOHP_rr |
900 | 0 | 33561060U, // FTOIZ_rr |
901 | 0 | 33559812U, // FTOI_rr |
902 | 0 | 6607U, // FTOQ31Z_rr |
903 | 0 | 4239U, // FTOQ31_rr |
904 | 0 | 33561093U, // FTOUZ_rr |
905 | 0 | 33560891U, // FTOU_rr |
906 | 0 | 4308U, // GE_A_rr |
907 | 0 | 536877021U, // GE_U_rc |
908 | 0 | 6109U, // GE_U_rr |
909 | 0 | 536875656U, // GE_rc |
910 | 0 | 4744U, // GE_rr |
911 | 0 | 33559331U, // HPTOF_rr |
912 | 0 | 537924889U, // IMASK_rcpw |
913 | 0 | 170923289U, // IMASK_rcrw |
914 | 0 | 537924889U, // IMASK_rrpw |
915 | 0 | 537924889U, // IMASK_rrrw |
916 | 0 | 6074U, // INSERT_rcpw |
917 | 0 | 6074U, // INSERT_rcrr |
918 | 0 | 536876986U, // INSERT_rcrw |
919 | 0 | 6074U, // INSERT_rrpw |
920 | 0 | 6074U, // INSERT_rrrr |
921 | 0 | 6074U, // INSERT_rrrw |
922 | 0 | 3758102285U, // INSN_T |
923 | 0 | 3758102373U, // INS_T |
924 | 0 | 3375U, // ISYNC_sys |
925 | 0 | 33559325U, // ITOF_rr |
926 | 0 | 3392149676U, // IXMAX_U_rrr |
927 | 0 | 3392149912U, // IXMAX_rrr |
928 | 0 | 3392149534U, // IXMIN_U_rrr |
929 | 0 | 3392148851U, // IXMIN_rrr |
930 | 0 | 16765U, // JA_b |
931 | 0 | 1073746203U, // JEQ_A_brr |
932 | 0 | 1075844676U, // JEQ_brc |
933 | 0 | 1073747524U, // JEQ_brr |
934 | 0 | 28713U, // JEQ_sbc1 |
935 | 0 | 28713U, // JEQ_sbc2 |
936 | 0 | 28713U, // JEQ_sbc_v110 |
937 | 0 | 7344169U, // JEQ_sbr1 |
938 | 0 | 7344169U, // JEQ_sbr2 |
939 | 0 | 7344169U, // JEQ_sbr_v110 |
940 | 0 | 7346648U, // JGEZ_sbr |
941 | 0 | 7346648U, // JGEZ_sbr_v110 |
942 | 0 | 1082136566U, // JGE_U_brc |
943 | 0 | 1073747958U, // JGE_U_brr |
944 | 0 | 1075843739U, // JGE_brc |
945 | 0 | 1073746587U, // JGE_brr |
946 | 0 | 7346681U, // JGTZ_sbr |
947 | 0 | 7346681U, // JGTZ_sbr_v110 |
948 | 0 | 136435U, // JI_rr |
949 | 0 | 136435U, // JI_rr_v110 |
950 | 0 | 136435U, // JI_sbr_v110 |
951 | 0 | 136435U, // JI_sr |
952 | 0 | 16769U, // JLA_b |
953 | 0 | 7346654U, // JLEZ_sbr |
954 | 0 | 7346654U, // JLEZ_sbr_v110 |
955 | 0 | 136439U, // JLI_rr |
956 | 0 | 136439U, // JLI_rr_v110 |
957 | 0 | 7346687U, // JLTZ_sbr |
958 | 0 | 7346687U, // JLTZ_sbr_v110 |
959 | 0 | 1082136727U, // JLT_U_brc |
960 | 0 | 1073748119U, // JLT_U_brr |
961 | 0 | 1082136496U, // JLT_brc |
962 | 0 | 1073747888U, // JLT_brr |
963 | 0 | 17708U, // JL_b |
964 | 0 | 1082135160U, // JNED_brc |
965 | 0 | 1073746552U, // JNED_brr |
966 | 0 | 1082135789U, // JNEI_brc |
967 | 0 | 1073747181U, // JNEI_brr |
968 | 0 | 1073746138U, // JNE_A_brr |
969 | 0 | 1075843793U, // JNE_brc |
970 | 0 | 1073746641U, // JNE_brr |
971 | 0 | 28703U, // JNE_sbc1 |
972 | 0 | 28703U, // JNE_sbc2 |
973 | 0 | 28703U, // JNE_sbc_v110 |
974 | 0 | 7344159U, // JNE_sbr1 |
975 | 0 | 7344159U, // JNE_sbr2 |
976 | 0 | 7344159U, // JNE_sbr_v110 |
977 | 0 | 9441602U, // JNZ_A_brr |
978 | 0 | 7344450U, // JNZ_A_sbr |
979 | 0 | 1073747832U, // JNZ_T_brn |
980 | 0 | 7344199U, // JNZ_T_sbrn |
981 | 0 | 7344199U, // JNZ_T_sbrn_v110 |
982 | 0 | 20602U, // JNZ_sb |
983 | 0 | 20602U, // JNZ_sb_v110 |
984 | 0 | 7346676U, // JNZ_sbr |
985 | 0 | 7346676U, // JNZ_sbr_v110 |
986 | 0 | 9441596U, // JZ_A_brr |
987 | 0 | 7344444U, // JZ_A_sbr |
988 | 0 | 1073747826U, // JZ_T_brn |
989 | 0 | 7344188U, // JZ_T_sbrn |
990 | 0 | 7344188U, // JZ_T_sbrn_v110 |
991 | 0 | 20593U, // JZ_sb |
992 | 0 | 20593U, // JZ_sb_v110 |
993 | 0 | 7346667U, // JZ_sbr |
994 | 0 | 7346667U, // JZ_sbr_v110 |
995 | 0 | 17678U, // J_b |
996 | 0 | 21774U, // J_sb |
997 | 0 | 21774U, // J_sb_v110 |
998 | 0 | 166309U, // LDLCX_abs |
999 | 0 | 4398229U, // LDLCX_bo_bso |
1000 | 0 | 38850U, // LDMST_abs |
1001 | 0 | 139684952U, // LDMST_bo_bso |
1002 | 0 | 139750488U, // LDMST_bo_c |
1003 | 0 | 139816024U, // LDMST_bo_pos |
1004 | 0 | 139684473U, // LDMST_bo_pre |
1005 | 0 | 6777944U, // LDMST_bo_r |
1006 | 0 | 166323U, // LDUCX_abs |
1007 | 0 | 4398245U, // LDUCX_bo_bso |
1008 | 0 | 10490050U, // LD_A_abs |
1009 | 0 | 213389506U, // LD_A_bo_bso |
1010 | 0 | 13111490U, // LD_A_bo_c |
1011 | 0 | 215486658U, // LD_A_bo_pos |
1012 | 0 | 594114U, // LD_A_bo_pre |
1013 | 0 | 15208642U, // LD_A_bo_r |
1014 | 0 | 246943938U, // LD_A_bol |
1015 | 0 | 142561U, // LD_A_sc |
1016 | 0 | 45617346U, // LD_A_slr |
1017 | 0 | 47714498U, // LD_A_slr_post |
1018 | 0 | 47714498U, // LD_A_slr_post_v110 |
1019 | 0 | 45617346U, // LD_A_slr_v110 |
1020 | 0 | 659650U, // LD_A_slro |
1021 | 0 | 659650U, // LD_A_slro_v110 |
1022 | 0 | 42146745U, // LD_A_sro |
1023 | 0 | 42146745U, // LD_A_sro_v110 |
1024 | 0 | 10492085U, // LD_BU_abs |
1025 | 0 | 213391541U, // LD_BU_bo_bso |
1026 | 0 | 13113525U, // LD_BU_bo_c |
1027 | 0 | 215488693U, // LD_BU_bo_pos |
1028 | 0 | 596149U, // LD_BU_bo_pre |
1029 | 0 | 15210677U, // LD_BU_bo_r |
1030 | 0 | 246945973U, // LD_BU_bol |
1031 | 0 | 45619381U, // LD_BU_slr |
1032 | 0 | 47716533U, // LD_BU_slr_post |
1033 | 0 | 47716533U, // LD_BU_slr_post_v110 |
1034 | 0 | 45619381U, // LD_BU_slr_v110 |
1035 | 0 | 661685U, // LD_BU_slro |
1036 | 0 | 661685U, // LD_BU_slro_v110 |
1037 | 0 | 42146781U, // LD_BU_sro |
1038 | 0 | 42146781U, // LD_BU_sro_v110 |
1039 | 0 | 10490284U, // LD_B_abs |
1040 | 0 | 213389740U, // LD_B_bo_bso |
1041 | 0 | 13111724U, // LD_B_bo_c |
1042 | 0 | 215486892U, // LD_B_bo_pos |
1043 | 0 | 594348U, // LD_B_bo_pre |
1044 | 0 | 15208876U, // LD_B_bo_r |
1045 | 0 | 246944172U, // LD_B_bol |
1046 | 0 | 47714732U, // LD_B_slr_post_v110 |
1047 | 0 | 45617580U, // LD_B_slr_v110 |
1048 | 0 | 659884U, // LD_B_slro_v110 |
1049 | 0 | 42146757U, // LD_B_sro_v110 |
1050 | 0 | 10490208U, // LD_DA_abs |
1051 | 0 | 213389664U, // LD_DA_bo_bso |
1052 | 0 | 13111648U, // LD_DA_bo_c |
1053 | 0 | 215486816U, // LD_DA_bo_pos |
1054 | 0 | 594272U, // LD_DA_bo_pre |
1055 | 0 | 15208800U, // LD_DA_bo_r |
1056 | 0 | 10490457U, // LD_D_abs |
1057 | 0 | 213389913U, // LD_D_bo_bso |
1058 | 0 | 13111897U, // LD_D_bo_c |
1059 | 0 | 215487065U, // LD_D_bo_pos |
1060 | 0 | 594521U, // LD_D_bo_pre |
1061 | 0 | 15209049U, // LD_D_bo_r |
1062 | 0 | 10492152U, // LD_HU_abs |
1063 | 0 | 213391608U, // LD_HU_bo_bso |
1064 | 0 | 13113592U, // LD_HU_bo_c |
1065 | 0 | 215488760U, // LD_HU_bo_pos |
1066 | 0 | 596216U, // LD_HU_bo_pre |
1067 | 0 | 15210744U, // LD_HU_bo_r |
1068 | 0 | 246946040U, // LD_HU_bol |
1069 | 0 | 10490705U, // LD_H_abs |
1070 | 0 | 213390161U, // LD_H_bo_bso |
1071 | 0 | 13112145U, // LD_H_bo_c |
1072 | 0 | 215487313U, // LD_H_bo_pos |
1073 | 0 | 594769U, // LD_H_bo_pre |
1074 | 0 | 15209297U, // LD_H_bo_r |
1075 | 0 | 246944593U, // LD_H_bol |
1076 | 0 | 45618001U, // LD_H_slr |
1077 | 0 | 47715153U, // LD_H_slr_post |
1078 | 0 | 47715153U, // LD_H_slr_post_v110 |
1079 | 0 | 45618001U, // LD_H_slr_v110 |
1080 | 0 | 660305U, // LD_H_slro |
1081 | 0 | 660305U, // LD_H_slro_v110 |
1082 | 0 | 42146769U, // LD_H_sro |
1083 | 0 | 42146769U, // LD_H_sro_v110 |
1084 | 0 | 10491336U, // LD_Q_abs |
1085 | 0 | 213390792U, // LD_Q_bo_bso |
1086 | 0 | 13112776U, // LD_Q_bo_c |
1087 | 0 | 215487944U, // LD_Q_bo_pos |
1088 | 0 | 595400U, // LD_Q_bo_pre |
1089 | 0 | 15209928U, // LD_Q_bo_r |
1090 | 0 | 10492260U, // LD_W_abs |
1091 | 0 | 213391716U, // LD_W_bo_bso |
1092 | 0 | 13113700U, // LD_W_bo_c |
1093 | 0 | 215488868U, // LD_W_bo_pos |
1094 | 0 | 596324U, // LD_W_bo_pre |
1095 | 0 | 15210852U, // LD_W_bo_r |
1096 | 0 | 246946148U, // LD_W_bol |
1097 | 0 | 142576U, // LD_W_sc |
1098 | 0 | 45619556U, // LD_W_slr |
1099 | 0 | 47716708U, // LD_W_slr_post |
1100 | 0 | 47716708U, // LD_W_slr_post_v110 |
1101 | 0 | 45619556U, // LD_W_slr_v110 |
1102 | 0 | 661860U, // LD_W_slro |
1103 | 0 | 661860U, // LD_W_slro_v110 |
1104 | 0 | 42146794U, // LD_W_sro |
1105 | 0 | 42146794U, // LD_W_sro_v110 |
1106 | 0 | 10490222U, // LEA_abs |
1107 | 0 | 213389678U, // LEA_bo_bso |
1108 | 0 | 246944110U, // LEA_bol |
1109 | 0 | 10490227U, // LHA_abs |
1110 | 0 | 43329U, // LOOPU_brr |
1111 | 0 | 9442738U, // LOOP_brr |
1112 | 0 | 15734194U, // LOOP_sbr |
1113 | 0 | 4386U, // LT_A_rr |
1114 | 0 | 4632U, // LT_B |
1115 | 0 | 6377U, // LT_BU |
1116 | 0 | 5277U, // LT_H |
1117 | 0 | 6444U, // LT_HU |
1118 | 0 | 536877182U, // LT_U_rc |
1119 | 0 | 6270U, // LT_U_rr |
1120 | 0 | 41947228U, // LT_U_srcv110 |
1121 | 0 | 33558620U, // LT_U_srrv110 |
1122 | 0 | 6530U, // LT_W |
1123 | 0 | 6472U, // LT_WU |
1124 | 0 | 536876957U, // LT_rc |
1125 | 0 | 6045U, // LT_rr |
1126 | 0 | 35655763U, // LT_src |
1127 | 0 | 33558611U, // LT_srr |
1128 | 0 | 103814190U, // MADDMS_H_rrr1_LL |
1129 | 0 | 103814190U, // MADDMS_H_rrr1_LU |
1130 | 0 | 103814190U, // MADDMS_H_rrr1_UL |
1131 | 0 | 103814190U, // MADDMS_H_rrr1_UU |
1132 | 0 | 2148538470U, // MADDMS_U_rcr_v110 |
1133 | 0 | 103815270U, // MADDMS_U_rrr2_v110 |
1134 | 0 | 2148538025U, // MADDMS_rcr_v110 |
1135 | 0 | 103814825U, // MADDMS_rrr2_v110 |
1136 | 0 | 103814018U, // MADDM_H_rrr1_LL |
1137 | 0 | 103814018U, // MADDM_H_rrr1_LU |
1138 | 0 | 103814018U, // MADDM_H_rrr1_UL |
1139 | 0 | 103814018U, // MADDM_H_rrr1_UU |
1140 | 0 | 103814018U, // MADDM_H_rrr1_v110 |
1141 | 0 | 103814622U, // MADDM_Q_rrr1_v110 |
1142 | 0 | 2148538381U, // MADDM_U_rcr_v110 |
1143 | 0 | 103815181U, // MADDM_U_rrr2_v110 |
1144 | 0 | 2148537676U, // MADDM_rcr_v110 |
1145 | 0 | 103814476U, // MADDM_rrr2_v110 |
1146 | 0 | 103814243U, // MADDRS_H_rrr1_LL |
1147 | 0 | 103814243U, // MADDRS_H_rrr1_LU |
1148 | 0 | 103814243U, // MADDRS_H_rrr1_UL |
1149 | 0 | 103814243U, // MADDRS_H_rrr1_UL_2 |
1150 | 0 | 103814243U, // MADDRS_H_rrr1_UU |
1151 | 0 | 103814243U, // MADDRS_H_rrr1_v110 |
1152 | 0 | 1714427421U, // MADDRS_Q_rrr1_L_L |
1153 | 0 | 2251298333U, // MADDRS_Q_rrr1_U_U |
1154 | 0 | 103814685U, // MADDRS_Q_rrr1_v110 |
1155 | 0 | 103814086U, // MADDR_H_rrr1_LL |
1156 | 0 | 103814086U, // MADDR_H_rrr1_LU |
1157 | 0 | 103814086U, // MADDR_H_rrr1_UL |
1158 | 0 | 103814086U, // MADDR_H_rrr1_UL_2 |
1159 | 0 | 103814086U, // MADDR_H_rrr1_UU |
1160 | 0 | 103814086U, // MADDR_H_rrr1_v110 |
1161 | 0 | 1714427376U, // MADDR_Q_rrr1_L_L |
1162 | 0 | 2251298288U, // MADDR_Q_rrr1_U_U |
1163 | 0 | 103814640U, // MADDR_Q_rrr1_v110 |
1164 | 0 | 103814209U, // MADDSUMS_H_rrr1_LL |
1165 | 0 | 103814209U, // MADDSUMS_H_rrr1_LU |
1166 | 0 | 103814209U, // MADDSUMS_H_rrr1_UL |
1167 | 0 | 103814209U, // MADDSUMS_H_rrr1_UU |
1168 | 0 | 103814035U, // MADDSUM_H_rrr1_LL |
1169 | 0 | 103814035U, // MADDSUM_H_rrr1_LU |
1170 | 0 | 103814035U, // MADDSUM_H_rrr1_UL |
1171 | 0 | 103814035U, // MADDSUM_H_rrr1_UU |
1172 | 0 | 103814253U, // MADDSURS_H_rrr1_LL |
1173 | 0 | 103814253U, // MADDSURS_H_rrr1_LU |
1174 | 0 | 103814253U, // MADDSURS_H_rrr1_UL |
1175 | 0 | 103814253U, // MADDSURS_H_rrr1_UU |
1176 | 0 | 103814103U, // MADDSUR_H_rrr1_LL |
1177 | 0 | 103814103U, // MADDSUR_H_rrr1_LU |
1178 | 0 | 103814103U, // MADDSUR_H_rrr1_UL |
1179 | 0 | 103814103U, // MADDSUR_H_rrr1_UU |
1180 | 0 | 103814273U, // MADDSUS_H_rrr1_LL |
1181 | 0 | 103814273U, // MADDSUS_H_rrr1_LU |
1182 | 0 | 103814273U, // MADDSUS_H_rrr1_UL |
1183 | 0 | 103814273U, // MADDSUS_H_rrr1_UU |
1184 | 0 | 103814313U, // MADDSU_H_rrr1_LL |
1185 | 0 | 103814313U, // MADDSU_H_rrr1_LU |
1186 | 0 | 103814313U, // MADDSU_H_rrr1_UL |
1187 | 0 | 103814313U, // MADDSU_H_rrr1_UU |
1188 | 0 | 103814141U, // MADDS_H_rrr1_LL |
1189 | 0 | 103814141U, // MADDS_H_rrr1_LU |
1190 | 0 | 103814141U, // MADDS_H_rrr1_UL |
1191 | 0 | 103814141U, // MADDS_H_rrr1_UU |
1192 | 0 | 103814141U, // MADDS_H_rrr1_v110 |
1193 | 0 | 103814666U, // MADDS_Q_rrr1 |
1194 | 0 | 103814666U, // MADDS_Q_rrr1_L |
1195 | 0 | 1714427402U, // MADDS_Q_rrr1_L_L |
1196 | 0 | 103814666U, // MADDS_Q_rrr1_U |
1197 | 0 | 103814666U, // MADDS_Q_rrr1_UU2_v110 |
1198 | 0 | 2251298314U, // MADDS_Q_rrr1_U_U |
1199 | 0 | 103814666U, // MADDS_Q_rrr1_e |
1200 | 0 | 103814666U, // MADDS_Q_rrr1_e_L |
1201 | 0 | 1714427402U, // MADDS_Q_rrr1_e_L_L |
1202 | 0 | 103814666U, // MADDS_Q_rrr1_e_U |
1203 | 0 | 2251298314U, // MADDS_Q_rrr1_e_U_U |
1204 | 0 | 2148538443U, // MADDS_U_rcr |
1205 | 0 | 2148538443U, // MADDS_U_rcr_e |
1206 | 0 | 103815243U, // MADDS_U_rrr2 |
1207 | 0 | 103815243U, // MADDS_U_rrr2_e |
1208 | 0 | 2148537990U, // MADDS_rcr |
1209 | 0 | 2148537990U, // MADDS_rcr_e |
1210 | 0 | 103814790U, // MADDS_rrr2 |
1211 | 0 | 103814790U, // MADDS_rrr2_e |
1212 | 0 | 103813863U, // MADD_F_rrr |
1213 | 0 | 103813961U, // MADD_H_rrr1_LL |
1214 | 0 | 103813961U, // MADD_H_rrr1_LU |
1215 | 0 | 103813961U, // MADD_H_rrr1_UL |
1216 | 0 | 103813961U, // MADD_H_rrr1_UU |
1217 | 0 | 103813961U, // MADD_H_rrr1_v110 |
1218 | 0 | 103814592U, // MADD_Q_rrr1 |
1219 | 0 | 103814592U, // MADD_Q_rrr1_L |
1220 | 0 | 1714427328U, // MADD_Q_rrr1_L_L |
1221 | 0 | 103814592U, // MADD_Q_rrr1_U |
1222 | 0 | 103814592U, // MADD_Q_rrr1_UU2_v110 |
1223 | 0 | 2251298240U, // MADD_Q_rrr1_U_U |
1224 | 0 | 103814592U, // MADD_Q_rrr1_e |
1225 | 0 | 103814592U, // MADD_Q_rrr1_e_L |
1226 | 0 | 1714427328U, // MADD_Q_rrr1_e_L_L |
1227 | 0 | 103814592U, // MADD_Q_rrr1_e_U |
1228 | 0 | 2251298240U, // MADD_Q_rrr1_e_U_U |
1229 | 0 | 2148538321U, // MADD_U_rcr |
1230 | 0 | 103815121U, // MADD_U_rrr2 |
1231 | 0 | 2148536946U, // MADD_rcr |
1232 | 0 | 2148536946U, // MADD_rcr_e |
1233 | 0 | 103813746U, // MADD_rrr2 |
1234 | 0 | 103813746U, // MADD_rrr2_e |
1235 | 0 | 4644U, // MAX_B |
1236 | 0 | 6384U, // MAX_BU |
1237 | 0 | 5299U, // MAX_H |
1238 | 0 | 6451U, // MAX_HU |
1239 | 0 | 536877230U, // MAX_U_rc |
1240 | 0 | 6318U, // MAX_U_rr |
1241 | 0 | 536877466U, // MAX_rc |
1242 | 0 | 6554U, // MAX_rr |
1243 | 0 | 16782921U, // MFCR_rlc |
1244 | 0 | 4546U, // MIN_B |
1245 | 0 | 6332U, // MIN_BU |
1246 | 0 | 5022U, // MIN_H |
1247 | 0 | 6399U, // MIN_HU |
1248 | 0 | 536877088U, // MIN_U_rc |
1249 | 0 | 6176U, // MIN_U_rr |
1250 | 0 | 536876405U, // MIN_rc |
1251 | 0 | 5493U, // MIN_rr |
1252 | 0 | 16781546U, // MOVH_A_rlc |
1253 | 0 | 16782549U, // MOVH_rlc |
1254 | 0 | 135504U, // MOVZ_A_sr |
1255 | 0 | 34607448U, // MOV_AA_rr |
1256 | 0 | 33558872U, // MOV_AA_srr_srr |
1257 | 0 | 33558872U, // MOV_AA_srr_srr_v110 |
1258 | 0 | 34607406U, // MOV_A_rr |
1259 | 0 | 41947438U, // MOV_A_src |
1260 | 0 | 33558830U, // MOV_A_srr |
1261 | 0 | 33558830U, // MOV_A_srr_v110 |
1262 | 0 | 34607717U, // MOV_D_rr |
1263 | 0 | 33559141U, // MOV_D_srr_srr |
1264 | 0 | 33559141U, // MOV_D_srr_srr_v110 |
1265 | 0 | 16783525U, // MOV_U_rlc |
1266 | 0 | 17832277U, // MOV_rlc |
1267 | 0 | 16783701U, // MOV_rlc_e |
1268 | 0 | 34609493U, // MOV_rr |
1269 | 0 | 34609493U, // MOV_rr_e |
1270 | 0 | 6485U, // MOV_rr_eab |
1271 | 0 | 139367U, // MOV_sc |
1272 | 0 | 139367U, // MOV_sc_v110 |
1273 | 0 | 35658069U, // MOV_src |
1274 | 0 | 35658069U, // MOV_src_e |
1275 | 0 | 33560917U, // MOV_srr |
1276 | 0 | 103814178U, // MSUBADMS_H_rrr1_LL |
1277 | 0 | 103814178U, // MSUBADMS_H_rrr1_LU |
1278 | 0 | 103814178U, // MSUBADMS_H_rrr1_UL |
1279 | 0 | 103814178U, // MSUBADMS_H_rrr1_UU |
1280 | 0 | 103814007U, // MSUBADM_H_rrr1_LL |
1281 | 0 | 103814007U, // MSUBADM_H_rrr1_LU |
1282 | 0 | 103814007U, // MSUBADM_H_rrr1_UL |
1283 | 0 | 103814007U, // MSUBADM_H_rrr1_UU |
1284 | 0 | 103814231U, // MSUBADRS_H_rrr1_LL |
1285 | 0 | 103814231U, // MSUBADRS_H_rrr1_LU |
1286 | 0 | 103814231U, // MSUBADRS_H_rrr1_UL |
1287 | 0 | 103814231U, // MSUBADRS_H_rrr1_UU |
1288 | 0 | 103814231U, // MSUBADRS_H_rrr1_v110 |
1289 | 0 | 103814075U, // MSUBADR_H_rrr1_LL |
1290 | 0 | 103814075U, // MSUBADR_H_rrr1_LU |
1291 | 0 | 103814075U, // MSUBADR_H_rrr1_UL |
1292 | 0 | 103814075U, // MSUBADR_H_rrr1_UU |
1293 | 0 | 103814075U, // MSUBADR_H_rrr1_v110 |
1294 | 0 | 103814130U, // MSUBADS_H_rrr1_LL |
1295 | 0 | 103814130U, // MSUBADS_H_rrr1_LU |
1296 | 0 | 103814130U, // MSUBADS_H_rrr1_UL |
1297 | 0 | 103814130U, // MSUBADS_H_rrr1_UU |
1298 | 0 | 103813951U, // MSUBAD_H_rrr1_LL |
1299 | 0 | 103813951U, // MSUBAD_H_rrr1_LU |
1300 | 0 | 103813951U, // MSUBAD_H_rrr1_UL |
1301 | 0 | 103813951U, // MSUBAD_H_rrr1_UU |
1302 | 0 | 103814168U, // MSUBMS_H_rrr1_LL |
1303 | 0 | 103814168U, // MSUBMS_H_rrr1_LU |
1304 | 0 | 103814168U, // MSUBMS_H_rrr1_UL |
1305 | 0 | 103814168U, // MSUBMS_H_rrr1_UU |
1306 | 0 | 2148538460U, // MSUBMS_U_rcrv110 |
1307 | 0 | 103815260U, // MSUBMS_U_rrr2v110 |
1308 | 0 | 2148538017U, // MSUBMS_rcrv110 |
1309 | 0 | 103814817U, // MSUBMS_rrr2v110 |
1310 | 0 | 103813998U, // MSUBM_H_rrr1_LL |
1311 | 0 | 103813998U, // MSUBM_H_rrr1_LU |
1312 | 0 | 103813998U, // MSUBM_H_rrr1_UL |
1313 | 0 | 103813998U, // MSUBM_H_rrr1_UU |
1314 | 0 | 103813998U, // MSUBM_H_rrr1_v110 |
1315 | 0 | 103814613U, // MSUBM_Q_rrr1_v110 |
1316 | 0 | 2148538372U, // MSUBM_U_rcrv110 |
1317 | 0 | 103815172U, // MSUBM_U_rrr2v110 |
1318 | 0 | 2148537669U, // MSUBM_rcrv110 |
1319 | 0 | 103814469U, // MSUBM_rrr2v110 |
1320 | 0 | 103814221U, // MSUBRS_H_rrr1_LL |
1321 | 0 | 103814221U, // MSUBRS_H_rrr1_LU |
1322 | 0 | 103814221U, // MSUBRS_H_rrr1_UL |
1323 | 0 | 103814221U, // MSUBRS_H_rrr1_UL_2 |
1324 | 0 | 103814221U, // MSUBRS_H_rrr1_UU |
1325 | 0 | 103814221U, // MSUBRS_H_rrr1_v110 |
1326 | 0 | 1714427411U, // MSUBRS_Q_rrr1_L_L |
1327 | 0 | 2251298323U, // MSUBRS_Q_rrr1_U_U |
1328 | 0 | 103814675U, // MSUBRS_Q_rrr1_v110 |
1329 | 0 | 103814066U, // MSUBR_H_rrr1_LL |
1330 | 0 | 103814066U, // MSUBR_H_rrr1_LU |
1331 | 0 | 103814066U, // MSUBR_H_rrr1_UL |
1332 | 0 | 103814066U, // MSUBR_H_rrr1_UL_2 |
1333 | 0 | 103814066U, // MSUBR_H_rrr1_UU |
1334 | 0 | 103814066U, // MSUBR_H_rrr1_v110 |
1335 | 0 | 1714427367U, // MSUBR_Q_rrr1_L_L |
1336 | 0 | 2251298279U, // MSUBR_Q_rrr1_U_U |
1337 | 0 | 103814631U, // MSUBR_Q_rrr1_v110 |
1338 | 0 | 103814121U, // MSUBS_H_rrr1_LL |
1339 | 0 | 103814121U, // MSUBS_H_rrr1_LU |
1340 | 0 | 103814121U, // MSUBS_H_rrr1_UL |
1341 | 0 | 103814121U, // MSUBS_H_rrr1_UU |
1342 | 0 | 103814121U, // MSUBS_H_rrr1_v110 |
1343 | 0 | 103814657U, // MSUBS_Q_rrr1 |
1344 | 0 | 103814657U, // MSUBS_Q_rrr1_L |
1345 | 0 | 1714427393U, // MSUBS_Q_rrr1_L_L |
1346 | 0 | 103814657U, // MSUBS_Q_rrr1_U |
1347 | 0 | 103814657U, // MSUBS_Q_rrr1_UU2_v110 |
1348 | 0 | 2251298305U, // MSUBS_Q_rrr1_U_U |
1349 | 0 | 103814657U, // MSUBS_Q_rrr1_e |
1350 | 0 | 103814657U, // MSUBS_Q_rrr1_e_L |
1351 | 0 | 1714427393U, // MSUBS_Q_rrr1_e_L_L |
1352 | 0 | 103814657U, // MSUBS_Q_rrr1_e_U |
1353 | 0 | 2251298305U, // MSUBS_Q_rrr1_e_U_U |
1354 | 0 | 2148538425U, // MSUBS_U_rcr |
1355 | 0 | 2148538425U, // MSUBS_U_rcr_e |
1356 | 0 | 103815225U, // MSUBS_U_rrr2 |
1357 | 0 | 103815225U, // MSUBS_U_rrr2_e |
1358 | 0 | 2148537976U, // MSUBS_rcr |
1359 | 0 | 2148537976U, // MSUBS_rcr_e |
1360 | 0 | 103814776U, // MSUBS_rrr2 |
1361 | 0 | 103814776U, // MSUBS_rrr2_e |
1362 | 0 | 103813855U, // MSUB_F_rrr |
1363 | 0 | 103813943U, // MSUB_H_rrr1_LL |
1364 | 0 | 103813943U, // MSUB_H_rrr1_LU |
1365 | 0 | 103813943U, // MSUB_H_rrr1_UL |
1366 | 0 | 103813943U, // MSUB_H_rrr1_UU |
1367 | 0 | 103813943U, // MSUB_H_rrr1_v110 |
1368 | 0 | 103814584U, // MSUB_Q_rrr1 |
1369 | 0 | 103814584U, // MSUB_Q_rrr1_L |
1370 | 0 | 1714427320U, // MSUB_Q_rrr1_L_L |
1371 | 0 | 103814584U, // MSUB_Q_rrr1_U |
1372 | 0 | 103814584U, // MSUB_Q_rrr1_UU2_v110 |
1373 | 0 | 2251298232U, // MSUB_Q_rrr1_U_U |
1374 | 0 | 103814584U, // MSUB_Q_rrr1_e |
1375 | 0 | 103814584U, // MSUB_Q_rrr1_e_L |
1376 | 0 | 1714427320U, // MSUB_Q_rrr1_e_L_L |
1377 | 0 | 103814584U, // MSUB_Q_rrr1_e_U |
1378 | 0 | 2251298232U, // MSUB_Q_rrr1_e_U_U |
1379 | 0 | 2148538313U, // MSUB_U_rcr |
1380 | 0 | 103815113U, // MSUB_U_rrr2 |
1381 | 0 | 2148536897U, // MSUB_rcr |
1382 | 0 | 2148536897U, // MSUB_rcr_e |
1383 | 0 | 103813697U, // MSUB_rrr2 |
1384 | 0 | 103813697U, // MSUB_rrr2_e |
1385 | 0 | 46671U, // MTCR_rlc |
1386 | 0 | 5176U, // MULMS_H_rr1_LL2e |
1387 | 0 | 5176U, // MULMS_H_rr1_LU2e |
1388 | 0 | 5176U, // MULMS_H_rr1_UL2e |
1389 | 0 | 5176U, // MULMS_H_rr1_UU2e |
1390 | 0 | 5003U, // MULM_H_rr1_LL2e |
1391 | 0 | 5003U, // MULM_H_rr1_LU2e |
1392 | 0 | 5003U, // MULM_H_rr1_UL2e |
1393 | 0 | 5003U, // MULM_H_rr1_UU2e |
1394 | 0 | 536877078U, // MULM_U_rc |
1395 | 0 | 6166U, // MULM_U_rr |
1396 | 0 | 536876371U, // MULM_rc |
1397 | 0 | 5459U, // MULM_rr |
1398 | 0 | 5071U, // MULR_H_rr1_LL2e |
1399 | 0 | 5071U, // MULR_H_rr1_LU2e |
1400 | 0 | 5071U, // MULR_H_rr1_UL2e |
1401 | 0 | 5071U, // MULR_H_rr1_UU2e |
1402 | 0 | 5071U, // MULR_H_rr_v110 |
1403 | 0 | 268441081U, // MULR_Q_rr1_2LL |
1404 | 0 | 301995513U, // MULR_Q_rr1_2UU |
1405 | 0 | 5625U, // MULR_Q_rr_v110 |
1406 | 0 | 536877140U, // MULS_U_rc |
1407 | 0 | 6228U, // MULS_U_rr2 |
1408 | 0 | 6228U, // MULS_U_rr_v110 |
1409 | 0 | 536876699U, // MULS_rc |
1410 | 0 | 5787U, // MULS_rr2 |
1411 | 0 | 5787U, // MULS_rr_v110 |
1412 | 0 | 4856U, // MUL_F_rrr |
1413 | 0 | 4967U, // MUL_H_rr1_LL2e |
1414 | 0 | 4967U, // MUL_H_rr1_LU2e |
1415 | 0 | 4967U, // MUL_H_rr1_UL2e |
1416 | 0 | 4967U, // MUL_H_rr1_UU2e |
1417 | 0 | 4967U, // MUL_H_rr_v110 |
1418 | 0 | 5582U, // MUL_Q_rr1_2 |
1419 | 0 | 268441038U, // MUL_Q_rr1_2LL |
1420 | 0 | 301995470U, // MUL_Q_rr1_2UU |
1421 | 0 | 5582U, // MUL_Q_rr1_2_L |
1422 | 0 | 5582U, // MUL_Q_rr1_2_Le |
1423 | 0 | 5582U, // MUL_Q_rr1_2_U |
1424 | 0 | 5582U, // MUL_Q_rr1_2_Ue |
1425 | 0 | 5582U, // MUL_Q_rr1_2__e |
1426 | 0 | 5582U, // MUL_Q_rr_v110 |
1427 | 0 | 536877053U, // MUL_U_rc |
1428 | 0 | 6141U, // MUL_U_rr2 |
1429 | 0 | 536876352U, // MUL_rc |
1430 | 0 | 536876352U, // MUL_rc_e |
1431 | 0 | 5440U, // MUL_rr2 |
1432 | 0 | 5440U, // MUL_rr2_e |
1433 | 0 | 5440U, // MUL_rr_v110 |
1434 | 0 | 33559872U, // MUL_srr |
1435 | 0 | 3758102233U, // NAND_T |
1436 | 0 | 536875646U, // NAND_rc |
1437 | 0 | 4734U, // NAND_rr |
1438 | 0 | 33558837U, // NEZ_A |
1439 | 0 | 4315U, // NE_A |
1440 | 0 | 536875710U, // NE_rc |
1441 | 0 | 4798U, // NE_rr |
1442 | 0 | 3424U, // NOP_sr |
1443 | 0 | 3424U, // NOP_sys |
1444 | 0 | 3758102325U, // NOR_T |
1445 | 0 | 536876630U, // NOR_rc |
1446 | 0 | 5718U, // NOR_rr |
1447 | 0 | 136790U, // NOR_sr |
1448 | 0 | 136790U, // NOR_sr_v110 |
1449 | 0 | 137141U, // NOT_sr_v162 |
1450 | 0 | 3758102278U, // ORN_T |
1451 | 0 | 536876416U, // ORN_rc |
1452 | 0 | 5504U, // ORN_rr |
1453 | 0 | 3758102264U, // OR_ANDN_T |
1454 | 0 | 3758102220U, // OR_AND_T |
1455 | 0 | 536876605U, // OR_EQ_rc |
1456 | 0 | 5693U, // OR_EQ_rr |
1457 | 0 | 536877037U, // OR_GE_U_rc |
1458 | 0 | 6125U, // OR_GE_U_rr |
1459 | 0 | 536875668U, // OR_GE_rc |
1460 | 0 | 4756U, // OR_GE_rr |
1461 | 0 | 536877198U, // OR_LT_U_rc |
1462 | 0 | 6286U, // OR_LT_U_rr |
1463 | 0 | 536876969U, // OR_LT_rc |
1464 | 0 | 6057U, // OR_LT_rr |
1465 | 0 | 536875722U, // OR_NE_rc |
1466 | 0 | 4810U, // OR_NE_rr |
1467 | 0 | 3758102342U, // OR_NOR_T |
1468 | 0 | 3758102312U, // OR_OR_T |
1469 | 0 | 3758102297U, // OR_T |
1470 | 0 | 2684360279U, // OR_rc |
1471 | 0 | 5719U, // OR_rr |
1472 | 0 | 139315U, // OR_sc |
1473 | 0 | 139315U, // OR_sc_v110 |
1474 | 0 | 33560151U, // OR_srr |
1475 | 0 | 33560151U, // OR_srr_v110 |
1476 | 0 | 3325039891U, // PACK_rrr |
1477 | 0 | 33561031U, // PARITY_rr |
1478 | 0 | 33561031U, // PARITY_rr_v110 |
1479 | 0 | 33560968U, // POPCNT_W_rr |
1480 | 0 | 4885U, // Q31TOF_rr |
1481 | 0 | 33559279U, // QSEED_F_rr |
1482 | 0 | 135894U, // RESTORE_sys |
1483 | 0 | 3429U, // RET_sr |
1484 | 0 | 3429U, // RET_sys |
1485 | 0 | 3429U, // RET_sys_v110 |
1486 | 0 | 3381U, // RFE_sr |
1487 | 0 | 3381U, // RFE_sys_sys |
1488 | 0 | 3381U, // RFE_sys_sys_v110 |
1489 | 0 | 3420U, // RFM_sys |
1490 | 0 | 3456U, // RSLCX_sys |
1491 | 0 | 3451U, // RSTV_sys |
1492 | 0 | 536877122U, // RSUBS_U_rc |
1493 | 0 | 536876671U, // RSUBS_rc |
1494 | 0 | 536875591U, // RSUB_rc |
1495 | 0 | 135751U, // RSUB_sr_sr |
1496 | 0 | 135751U, // RSUB_sr_sr_v110 |
1497 | 0 | 33560790U, // SAT_BU_rr |
1498 | 0 | 137430U, // SAT_BU_sr |
1499 | 0 | 137430U, // SAT_BU_sr_v110 |
1500 | 0 | 33559047U, // SAT_B_rr |
1501 | 0 | 135687U, // SAT_B_sr |
1502 | 0 | 135687U, // SAT_B_sr_v110 |
1503 | 0 | 33560857U, // SAT_HU_rr |
1504 | 0 | 137497U, // SAT_HU_sr |
1505 | 0 | 137497U, // SAT_HU_sr_v110 |
1506 | 0 | 33559692U, // SAT_H_rr |
1507 | 0 | 136332U, // SAT_H_sr |
1508 | 0 | 136332U, // SAT_H_sr_v110 |
1509 | 0 | 2148536587U, // SELN_A_rcr_v110 |
1510 | 0 | 103813387U, // SELN_A_rrr_v110 |
1511 | 0 | 2148537722U, // SELN_rcr |
1512 | 0 | 103814522U, // SELN_rrr |
1513 | 0 | 2148536562U, // SEL_A_rcr_v110 |
1514 | 0 | 103813362U, // SEL_A_rrr_v110 |
1515 | 0 | 2148537632U, // SEL_rcr |
1516 | 0 | 103814432U, // SEL_rrr |
1517 | 0 | 536876653U, // SHAS_rc |
1518 | 0 | 5741U, // SHAS_rr |
1519 | 0 | 536875415U, // SHA_B_rc |
1520 | 0 | 4503U, // SHA_B_rr |
1521 | 0 | 536875824U, // SHA_H_rc |
1522 | 0 | 4912U, // SHA_H_rr |
1523 | 0 | 536875384U, // SHA_rc |
1524 | 0 | 4472U, // SHA_rr |
1525 | 0 | 35656056U, // SHA_src |
1526 | 0 | 35656056U, // SHA_src_v110 |
1527 | 0 | 536875697U, // SHUFFLE_rc |
1528 | 0 | 3758102253U, // SH_ANDN_T |
1529 | 0 | 3758102210U, // SH_AND_T |
1530 | 0 | 536875452U, // SH_B_rc |
1531 | 0 | 4540U, // SH_B_rr |
1532 | 0 | 536876597U, // SH_EQ_rc |
1533 | 0 | 5685U, // SH_EQ_rr |
1534 | 0 | 536877027U, // SH_GE_U_rc |
1535 | 0 | 6115U, // SH_GE_U_rr |
1536 | 0 | 536875660U, // SH_GE_rc |
1537 | 0 | 4748U, // SH_GE_rr |
1538 | 0 | 536875873U, // SH_H_rc |
1539 | 0 | 4961U, // SH_H_rr |
1540 | 0 | 536877188U, // SH_LT_U_rc |
1541 | 0 | 6276U, // SH_LT_U_rr |
1542 | 0 | 536876961U, // SH_LT_rc |
1543 | 0 | 6049U, // SH_LT_rr |
1544 | 0 | 3758102230U, // SH_NAND_T |
1545 | 0 | 536875714U, // SH_NE_rc |
1546 | 0 | 4802U, // SH_NE_rr |
1547 | 0 | 3758102332U, // SH_NOR_T |
1548 | 0 | 3758102275U, // SH_ORN_T |
1549 | 0 | 3758102303U, // SH_OR_T |
1550 | 0 | 3758102352U, // SH_XNOR_T |
1551 | 0 | 3758102363U, // SH_XOR_T |
1552 | 0 | 536876241U, // SH_rc |
1553 | 0 | 5329U, // SH_rr |
1554 | 0 | 35656913U, // SH_src |
1555 | 0 | 35656913U, // SH_src_v110 |
1556 | 0 | 166316U, // STLCX_abs |
1557 | 0 | 4398237U, // STLCX_bo_bso |
1558 | 0 | 166330U, // STUCX_abs |
1559 | 0 | 4398253U, // STUCX_bo_bso |
1560 | 0 | 37160U, // ST_A_abs |
1561 | 0 | 139684863U, // ST_A_bo_bso |
1562 | 0 | 3327400959U, // ST_A_bo_c |
1563 | 0 | 139815935U, // ST_A_bo_pos |
1564 | 0 | 139684374U, // ST_A_bo_pre |
1565 | 0 | 34020351U, // ST_A_bo_r |
1566 | 0 | 19078143U, // ST_A_bol |
1567 | 0 | 732415U, // ST_A_sc |
1568 | 0 | 344136703U, // ST_A_sro |
1569 | 0 | 344136703U, // ST_A_sro_v110 |
1570 | 0 | 793599U, // ST_A_ssr |
1571 | 0 | 859135U, // ST_A_ssr_pos |
1572 | 0 | 859135U, // ST_A_ssr_pos_v110 |
1573 | 0 | 793599U, // ST_A_ssr_v110 |
1574 | 0 | 52405U, // ST_A_ssro |
1575 | 0 | 52405U, // ST_A_ssro_v110 |
1576 | 0 | 37406U, // ST_B_abs |
1577 | 0 | 139684878U, // ST_B_bo_bso |
1578 | 0 | 3327400974U, // ST_B_bo_c |
1579 | 0 | 139815950U, // ST_B_bo_pos |
1580 | 0 | 139684391U, // ST_B_bo_pre |
1581 | 0 | 34020366U, // ST_B_bo_r |
1582 | 0 | 19078158U, // ST_B_bol |
1583 | 0 | 377691150U, // ST_B_sro |
1584 | 0 | 377691150U, // ST_B_sro_v110 |
1585 | 0 | 793614U, // ST_B_ssr |
1586 | 0 | 859150U, // ST_B_ssr_pos |
1587 | 0 | 859150U, // ST_B_ssr_pos_v110 |
1588 | 0 | 793614U, // ST_B_ssr_v110 |
1589 | 0 | 52416U, // ST_B_ssro |
1590 | 0 | 52416U, // ST_B_ssro_v110 |
1591 | 0 | 37223U, // ST_DA_abs |
1592 | 0 | 139684870U, // ST_DA_bo_bso |
1593 | 0 | 3327400966U, // ST_DA_bo_c |
1594 | 0 | 139815942U, // ST_DA_bo_pos |
1595 | 0 | 139684382U, // ST_DA_bo_pre |
1596 | 0 | 34020358U, // ST_DA_bo_r |
1597 | 0 | 37471U, // ST_D_abs |
1598 | 0 | 139684885U, // ST_D_bo_bso |
1599 | 0 | 3327400981U, // ST_D_bo_c |
1600 | 0 | 139815957U, // ST_D_bo_pos |
1601 | 0 | 139684399U, // ST_D_bo_pre |
1602 | 0 | 34020373U, // ST_D_bo_r |
1603 | 0 | 38051U, // ST_H_abs |
1604 | 0 | 139684892U, // ST_H_bo_bso |
1605 | 0 | 3327400988U, // ST_H_bo_c |
1606 | 0 | 139815964U, // ST_H_bo_pos |
1607 | 0 | 139684407U, // ST_H_bo_pre |
1608 | 0 | 34020380U, // ST_H_bo_r |
1609 | 0 | 19078172U, // ST_H_bol |
1610 | 0 | 377691164U, // ST_H_sro |
1611 | 0 | 377691164U, // ST_H_sro_v110 |
1612 | 0 | 793628U, // ST_H_ssr |
1613 | 0 | 859164U, // ST_H_ssr_pos |
1614 | 0 | 859164U, // ST_H_ssr_pos_v110 |
1615 | 0 | 793628U, // ST_H_ssr_v110 |
1616 | 0 | 52427U, // ST_H_ssro |
1617 | 0 | 52427U, // ST_H_ssro_v110 |
1618 | 0 | 38439U, // ST_Q_abs |
1619 | 0 | 139684945U, // ST_Q_bo_bso |
1620 | 0 | 3327401041U, // ST_Q_bo_c |
1621 | 0 | 139816017U, // ST_Q_bo_pos |
1622 | 0 | 139684465U, // ST_Q_bo_pre |
1623 | 0 | 34020433U, // ST_Q_bo_r |
1624 | 0 | 34668U, // ST_T |
1625 | 0 | 39314U, // ST_W_abs |
1626 | 0 | 139685006U, // ST_W_bo_bso |
1627 | 0 | 3327401102U, // ST_W_bo_c |
1628 | 0 | 139816078U, // ST_W_bo_pos |
1629 | 0 | 139684532U, // ST_W_bo_pre |
1630 | 0 | 34020494U, // ST_W_bo_r |
1631 | 0 | 19078286U, // ST_W_bol |
1632 | 0 | 929033U, // ST_W_sc |
1633 | 0 | 377691278U, // ST_W_sro |
1634 | 0 | 377691278U, // ST_W_sro_v110 |
1635 | 0 | 793742U, // ST_W_ssr |
1636 | 0 | 859278U, // ST_W_ssr_pos |
1637 | 0 | 859278U, // ST_W_ssr_pos_v110 |
1638 | 0 | 793742U, // ST_W_ssr_v110 |
1639 | 0 | 52438U, // ST_W_ssro |
1640 | 0 | 52438U, // ST_W_ssro_v110 |
1641 | 0 | 4685U, // SUBC_rr |
1642 | 0 | 4255U, // SUBSC_A_rr |
1643 | 0 | 6340U, // SUBS_BU_rr |
1644 | 0 | 4573U, // SUBS_B_rr |
1645 | 0 | 6407U, // SUBS_HU_rr |
1646 | 0 | 5098U, // SUBS_H_rr |
1647 | 0 | 6202U, // SUBS_U_rr |
1648 | 0 | 5753U, // SUBS_rr |
1649 | 0 | 33560185U, // SUBS_srr |
1650 | 0 | 6559U, // SUBX_rr |
1651 | 0 | 4248U, // SUB_A_rr |
1652 | 0 | 139396U, // SUB_A_sc |
1653 | 0 | 139396U, // SUB_A_sc_v110 |
1654 | 0 | 4510U, // SUB_B_rr |
1655 | 0 | 3325039328U, // SUB_F_rrr |
1656 | 0 | 4920U, // SUB_H_rr |
1657 | 0 | 4668U, // SUB_rr |
1658 | 0 | 33559100U, // SUB_srr |
1659 | 0 | 33558529U, // SUB_srr_15a |
1660 | 0 | 33624636U, // SUB_srr_a15 |
1661 | 0 | 3462U, // SVLCX_sys |
1662 | 0 | 139684982U, // SWAPMSK_W_bo_bso |
1663 | 0 | 3327401078U, // SWAPMSK_W_bo_c |
1664 | 0 | 1010806U, // SWAPMSK_W_bo_i |
1665 | 0 | 139816054U, // SWAPMSK_W_bo_pos |
1666 | 0 | 139684506U, // SWAPMSK_W_bo_pre |
1667 | 0 | 34020470U, // SWAPMSK_W_bo_r |
1668 | 0 | 37139U, // SWAP_A_abs |
1669 | 0 | 139684854U, // SWAP_A_bo_bso |
1670 | 0 | 3327400950U, // SWAP_A_bo_c |
1671 | 0 | 139815926U, // SWAP_A_bo_pos |
1672 | 0 | 139684364U, // SWAP_A_bo_pre |
1673 | 0 | 34020342U, // SWAP_A_bo_r |
1674 | 0 | 39284U, // SWAP_W_abs |
1675 | 0 | 139684997U, // SWAP_W_bo_bso |
1676 | 0 | 3327401093U, // SWAP_W_bo_c |
1677 | 0 | 1010821U, // SWAP_W_bo_i |
1678 | 0 | 139816069U, // SWAP_W_bo_pos |
1679 | 0 | 139684522U, // SWAP_W_bo_pre |
1680 | 0 | 34020485U, // SWAP_W_bo_r |
1681 | 0 | 13623U, // SYSCALL_rc |
1682 | 0 | 136601U, // TLBDEMAP_rr |
1683 | 0 | 3347U, // TLBFLUSH_A_rr |
1684 | 0 | 3358U, // TLBFLUSH_B_rr |
1685 | 0 | 136593U, // TLBMAP_rr |
1686 | 0 | 135368U, // TLBPROBE_A_rr |
1687 | 0 | 136411U, // TLBPROBE_I_rr |
1688 | 0 | 3444U, // TRAPSV_sys |
1689 | 0 | 3438U, // TRAPV_sys |
1690 | 0 | 33559825U, // UNPACK_rr_rr |
1691 | 0 | 33559825U, // UNPACK_rr_rr_v110 |
1692 | 0 | 136485U, // UPDFL_rr |
1693 | 0 | 33559338U, // UTOF_rr |
1694 | 0 | 3433U, // WAIT_sys |
1695 | 0 | 3758102355U, // XNOR_T |
1696 | 0 | 536876629U, // XNOR_rc |
1697 | 0 | 5717U, // XNOR_rr |
1698 | 0 | 536876604U, // XOR_EQ_rc |
1699 | 0 | 5692U, // XOR_EQ_rr |
1700 | 0 | 536877036U, // XOR_GE_U_rc |
1701 | 0 | 6124U, // XOR_GE_U_rr |
1702 | 0 | 536875667U, // XOR_GE_rc |
1703 | 0 | 4755U, // XOR_GE_rr |
1704 | 0 | 536877197U, // XOR_LT_U_rc |
1705 | 0 | 6285U, // XOR_LT_U_rr |
1706 | 0 | 536876968U, // XOR_LT_rc |
1707 | 0 | 6056U, // XOR_LT_rr |
1708 | 0 | 536875721U, // XOR_NE_rc |
1709 | 0 | 4809U, // XOR_NE_rr |
1710 | 0 | 3758102366U, // XOR_T |
1711 | 0 | 536876635U, // XOR_rc |
1712 | 0 | 5723U, // XOR_rr |
1713 | 0 | 33560155U, // XOR_srr |
1714 | 0 | }; |
1715 | |
|
1716 | 0 | static const uint16_t OpInfo1[] = { |
1717 | 0 | 0U, // PHI |
1718 | 0 | 0U, // INLINEASM |
1719 | 0 | 0U, // INLINEASM_BR |
1720 | 0 | 0U, // CFI_INSTRUCTION |
1721 | 0 | 0U, // EH_LABEL |
1722 | 0 | 0U, // GC_LABEL |
1723 | 0 | 0U, // ANNOTATION_LABEL |
1724 | 0 | 0U, // KILL |
1725 | 0 | 0U, // EXTRACT_SUBREG |
1726 | 0 | 0U, // INSERT_SUBREG |
1727 | 0 | 0U, // IMPLICIT_DEF |
1728 | 0 | 0U, // SUBREG_TO_REG |
1729 | 0 | 0U, // COPY_TO_REGCLASS |
1730 | 0 | 0U, // DBG_VALUE |
1731 | 0 | 0U, // DBG_VALUE_LIST |
1732 | 0 | 0U, // DBG_INSTR_REF |
1733 | 0 | 0U, // DBG_PHI |
1734 | 0 | 0U, // DBG_LABEL |
1735 | 0 | 0U, // REG_SEQUENCE |
1736 | 0 | 0U, // COPY |
1737 | 0 | 0U, // BUNDLE |
1738 | 0 | 0U, // LIFETIME_START |
1739 | 0 | 0U, // LIFETIME_END |
1740 | 0 | 0U, // PSEUDO_PROBE |
1741 | 0 | 0U, // ARITH_FENCE |
1742 | 0 | 0U, // STACKMAP |
1743 | 0 | 0U, // FENTRY_CALL |
1744 | 0 | 0U, // PATCHPOINT |
1745 | 0 | 0U, // LOAD_STACK_GUARD |
1746 | 0 | 0U, // PREALLOCATED_SETUP |
1747 | 0 | 0U, // PREALLOCATED_ARG |
1748 | 0 | 0U, // STATEPOINT |
1749 | 0 | 0U, // LOCAL_ESCAPE |
1750 | 0 | 0U, // FAULTING_OP |
1751 | 0 | 0U, // PATCHABLE_OP |
1752 | 0 | 0U, // PATCHABLE_FUNCTION_ENTER |
1753 | 0 | 0U, // PATCHABLE_RET |
1754 | 0 | 0U, // PATCHABLE_FUNCTION_EXIT |
1755 | 0 | 0U, // PATCHABLE_TAIL_CALL |
1756 | 0 | 0U, // PATCHABLE_EVENT_CALL |
1757 | 0 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
1758 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
1759 | 0 | 0U, // MEMBARRIER |
1760 | 0 | 0U, // G_ASSERT_SEXT |
1761 | 0 | 0U, // G_ASSERT_ZEXT |
1762 | 0 | 0U, // G_ASSERT_ALIGN |
1763 | 0 | 0U, // G_ADD |
1764 | 0 | 0U, // G_SUB |
1765 | 0 | 0U, // G_MUL |
1766 | 0 | 0U, // G_SDIV |
1767 | 0 | 0U, // G_UDIV |
1768 | 0 | 0U, // G_SREM |
1769 | 0 | 0U, // G_UREM |
1770 | 0 | 0U, // G_SDIVREM |
1771 | 0 | 0U, // G_UDIVREM |
1772 | 0 | 0U, // G_AND |
1773 | 0 | 0U, // G_OR |
1774 | 0 | 0U, // G_XOR |
1775 | 0 | 0U, // G_IMPLICIT_DEF |
1776 | 0 | 0U, // G_PHI |
1777 | 0 | 0U, // G_FRAME_INDEX |
1778 | 0 | 0U, // G_GLOBAL_VALUE |
1779 | 0 | 0U, // G_EXTRACT |
1780 | 0 | 0U, // G_UNMERGE_VALUES |
1781 | 0 | 0U, // G_INSERT |
1782 | 0 | 0U, // G_MERGE_VALUES |
1783 | 0 | 0U, // G_BUILD_VECTOR |
1784 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
1785 | 0 | 0U, // G_CONCAT_VECTORS |
1786 | 0 | 0U, // G_PTRTOINT |
1787 | 0 | 0U, // G_INTTOPTR |
1788 | 0 | 0U, // G_BITCAST |
1789 | 0 | 0U, // G_FREEZE |
1790 | 0 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
1791 | 0 | 0U, // G_INTRINSIC_TRUNC |
1792 | 0 | 0U, // G_INTRINSIC_ROUND |
1793 | 0 | 0U, // G_INTRINSIC_LRINT |
1794 | 0 | 0U, // G_INTRINSIC_ROUNDEVEN |
1795 | 0 | 0U, // G_READCYCLECOUNTER |
1796 | 0 | 0U, // G_LOAD |
1797 | 0 | 0U, // G_SEXTLOAD |
1798 | 0 | 0U, // G_ZEXTLOAD |
1799 | 0 | 0U, // G_INDEXED_LOAD |
1800 | 0 | 0U, // G_INDEXED_SEXTLOAD |
1801 | 0 | 0U, // G_INDEXED_ZEXTLOAD |
1802 | 0 | 0U, // G_STORE |
1803 | 0 | 0U, // G_INDEXED_STORE |
1804 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
1805 | 0 | 0U, // G_ATOMIC_CMPXCHG |
1806 | 0 | 0U, // G_ATOMICRMW_XCHG |
1807 | 0 | 0U, // G_ATOMICRMW_ADD |
1808 | 0 | 0U, // G_ATOMICRMW_SUB |
1809 | 0 | 0U, // G_ATOMICRMW_AND |
1810 | 0 | 0U, // G_ATOMICRMW_NAND |
1811 | 0 | 0U, // G_ATOMICRMW_OR |
1812 | 0 | 0U, // G_ATOMICRMW_XOR |
1813 | 0 | 0U, // G_ATOMICRMW_MAX |
1814 | 0 | 0U, // G_ATOMICRMW_MIN |
1815 | 0 | 0U, // G_ATOMICRMW_UMAX |
1816 | 0 | 0U, // G_ATOMICRMW_UMIN |
1817 | 0 | 0U, // G_ATOMICRMW_FADD |
1818 | 0 | 0U, // G_ATOMICRMW_FSUB |
1819 | 0 | 0U, // G_ATOMICRMW_FMAX |
1820 | 0 | 0U, // G_ATOMICRMW_FMIN |
1821 | 0 | 0U, // G_ATOMICRMW_UINC_WRAP |
1822 | 0 | 0U, // G_ATOMICRMW_UDEC_WRAP |
1823 | 0 | 0U, // G_FENCE |
1824 | 0 | 0U, // G_BRCOND |
1825 | 0 | 0U, // G_BRINDIRECT |
1826 | 0 | 0U, // G_INVOKE_REGION_START |
1827 | 0 | 0U, // G_INTRINSIC |
1828 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
1829 | 0 | 0U, // G_ANYEXT |
1830 | 0 | 0U, // G_TRUNC |
1831 | 0 | 0U, // G_CONSTANT |
1832 | 0 | 0U, // G_FCONSTANT |
1833 | 0 | 0U, // G_VASTART |
1834 | 0 | 0U, // G_VAARG |
1835 | 0 | 0U, // G_SEXT |
1836 | 0 | 0U, // G_SEXT_INREG |
1837 | 0 | 0U, // G_ZEXT |
1838 | 0 | 0U, // G_SHL |
1839 | 0 | 0U, // G_LSHR |
1840 | 0 | 0U, // G_ASHR |
1841 | 0 | 0U, // G_FSHL |
1842 | 0 | 0U, // G_FSHR |
1843 | 0 | 0U, // G_ROTR |
1844 | 0 | 0U, // G_ROTL |
1845 | 0 | 0U, // G_ICMP |
1846 | 0 | 0U, // G_FCMP |
1847 | 0 | 0U, // G_SELECT |
1848 | 0 | 0U, // G_UADDO |
1849 | 0 | 0U, // G_UADDE |
1850 | 0 | 0U, // G_USUBO |
1851 | 0 | 0U, // G_USUBE |
1852 | 0 | 0U, // G_SADDO |
1853 | 0 | 0U, // G_SADDE |
1854 | 0 | 0U, // G_SSUBO |
1855 | 0 | 0U, // G_SSUBE |
1856 | 0 | 0U, // G_UMULO |
1857 | 0 | 0U, // G_SMULO |
1858 | 0 | 0U, // G_UMULH |
1859 | 0 | 0U, // G_SMULH |
1860 | 0 | 0U, // G_UADDSAT |
1861 | 0 | 0U, // G_SADDSAT |
1862 | 0 | 0U, // G_USUBSAT |
1863 | 0 | 0U, // G_SSUBSAT |
1864 | 0 | 0U, // G_USHLSAT |
1865 | 0 | 0U, // G_SSHLSAT |
1866 | 0 | 0U, // G_SMULFIX |
1867 | 0 | 0U, // G_UMULFIX |
1868 | 0 | 0U, // G_SMULFIXSAT |
1869 | 0 | 0U, // G_UMULFIXSAT |
1870 | 0 | 0U, // G_SDIVFIX |
1871 | 0 | 0U, // G_UDIVFIX |
1872 | 0 | 0U, // G_SDIVFIXSAT |
1873 | 0 | 0U, // G_UDIVFIXSAT |
1874 | 0 | 0U, // G_FADD |
1875 | 0 | 0U, // G_FSUB |
1876 | 0 | 0U, // G_FMUL |
1877 | 0 | 0U, // G_FMA |
1878 | 0 | 0U, // G_FMAD |
1879 | 0 | 0U, // G_FDIV |
1880 | 0 | 0U, // G_FREM |
1881 | 0 | 0U, // G_FPOW |
1882 | 0 | 0U, // G_FPOWI |
1883 | 0 | 0U, // G_FEXP |
1884 | 0 | 0U, // G_FEXP2 |
1885 | 0 | 0U, // G_FLOG |
1886 | 0 | 0U, // G_FLOG2 |
1887 | 0 | 0U, // G_FLOG10 |
1888 | 0 | 0U, // G_FNEG |
1889 | 0 | 0U, // G_FPEXT |
1890 | 0 | 0U, // G_FPTRUNC |
1891 | 0 | 0U, // G_FPTOSI |
1892 | 0 | 0U, // G_FPTOUI |
1893 | 0 | 0U, // G_SITOFP |
1894 | 0 | 0U, // G_UITOFP |
1895 | 0 | 0U, // G_FABS |
1896 | 0 | 0U, // G_FCOPYSIGN |
1897 | 0 | 0U, // G_IS_FPCLASS |
1898 | 0 | 0U, // G_FCANONICALIZE |
1899 | 0 | 0U, // G_FMINNUM |
1900 | 0 | 0U, // G_FMAXNUM |
1901 | 0 | 0U, // G_FMINNUM_IEEE |
1902 | 0 | 0U, // G_FMAXNUM_IEEE |
1903 | 0 | 0U, // G_FMINIMUM |
1904 | 0 | 0U, // G_FMAXIMUM |
1905 | 0 | 0U, // G_PTR_ADD |
1906 | 0 | 0U, // G_PTRMASK |
1907 | 0 | 0U, // G_SMIN |
1908 | 0 | 0U, // G_SMAX |
1909 | 0 | 0U, // G_UMIN |
1910 | 0 | 0U, // G_UMAX |
1911 | 0 | 0U, // G_ABS |
1912 | 0 | 0U, // G_LROUND |
1913 | 0 | 0U, // G_LLROUND |
1914 | 0 | 0U, // G_BR |
1915 | 0 | 0U, // G_BRJT |
1916 | 0 | 0U, // G_INSERT_VECTOR_ELT |
1917 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
1918 | 0 | 0U, // G_SHUFFLE_VECTOR |
1919 | 0 | 0U, // G_CTTZ |
1920 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
1921 | 0 | 0U, // G_CTLZ |
1922 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
1923 | 0 | 0U, // G_CTPOP |
1924 | 0 | 0U, // G_BSWAP |
1925 | 0 | 0U, // G_BITREVERSE |
1926 | 0 | 0U, // G_FCEIL |
1927 | 0 | 0U, // G_FCOS |
1928 | 0 | 0U, // G_FSIN |
1929 | 0 | 0U, // G_FSQRT |
1930 | 0 | 0U, // G_FFLOOR |
1931 | 0 | 0U, // G_FRINT |
1932 | 0 | 0U, // G_FNEARBYINT |
1933 | 0 | 0U, // G_ADDRSPACE_CAST |
1934 | 0 | 0U, // G_BLOCK_ADDR |
1935 | 0 | 0U, // G_JUMP_TABLE |
1936 | 0 | 0U, // G_DYN_STACKALLOC |
1937 | 0 | 0U, // G_STRICT_FADD |
1938 | 0 | 0U, // G_STRICT_FSUB |
1939 | 0 | 0U, // G_STRICT_FMUL |
1940 | 0 | 0U, // G_STRICT_FDIV |
1941 | 0 | 0U, // G_STRICT_FREM |
1942 | 0 | 0U, // G_STRICT_FMA |
1943 | 0 | 0U, // G_STRICT_FSQRT |
1944 | 0 | 0U, // G_READ_REGISTER |
1945 | 0 | 0U, // G_WRITE_REGISTER |
1946 | 0 | 0U, // G_MEMCPY |
1947 | 0 | 0U, // G_MEMCPY_INLINE |
1948 | 0 | 0U, // G_MEMMOVE |
1949 | 0 | 0U, // G_MEMSET |
1950 | 0 | 0U, // G_BZERO |
1951 | 0 | 0U, // G_VECREDUCE_SEQ_FADD |
1952 | 0 | 0U, // G_VECREDUCE_SEQ_FMUL |
1953 | 0 | 0U, // G_VECREDUCE_FADD |
1954 | 0 | 0U, // G_VECREDUCE_FMUL |
1955 | 0 | 0U, // G_VECREDUCE_FMAX |
1956 | 0 | 0U, // G_VECREDUCE_FMIN |
1957 | 0 | 0U, // G_VECREDUCE_ADD |
1958 | 0 | 0U, // G_VECREDUCE_MUL |
1959 | 0 | 0U, // G_VECREDUCE_AND |
1960 | 0 | 0U, // G_VECREDUCE_OR |
1961 | 0 | 0U, // G_VECREDUCE_XOR |
1962 | 0 | 0U, // G_VECREDUCE_SMAX |
1963 | 0 | 0U, // G_VECREDUCE_SMIN |
1964 | 0 | 0U, // G_VECREDUCE_UMAX |
1965 | 0 | 0U, // G_VECREDUCE_UMIN |
1966 | 0 | 0U, // G_SBFX |
1967 | 0 | 0U, // G_UBFX |
1968 | 0 | 0U, // ABSDIFS_B_rr_v110 |
1969 | 0 | 0U, // ABSDIFS_H_rr |
1970 | 0 | 0U, // ABSDIFS_rc |
1971 | 0 | 0U, // ABSDIFS_rr |
1972 | 0 | 0U, // ABSDIF_B_rr |
1973 | 0 | 0U, // ABSDIF_H_rr |
1974 | 0 | 0U, // ABSDIF_rc |
1975 | 0 | 0U, // ABSDIF_rr |
1976 | 0 | 0U, // ABSS_B_rr_v110 |
1977 | 0 | 0U, // ABSS_H_rr |
1978 | 0 | 0U, // ABSS_rr |
1979 | 0 | 0U, // ABS_B_rr |
1980 | 0 | 0U, // ABS_H_rr |
1981 | 0 | 0U, // ABS_rr |
1982 | 0 | 0U, // ADDC_rc |
1983 | 0 | 0U, // ADDC_rr |
1984 | 0 | 0U, // ADDIH_A_rlc |
1985 | 0 | 0U, // ADDIH_rlc |
1986 | 0 | 0U, // ADDI_rlc |
1987 | 0 | 0U, // ADDSC_AT_rr |
1988 | 0 | 0U, // ADDSC_AT_rr_v110 |
1989 | 0 | 2U, // ADDSC_A_rr |
1990 | 0 | 2U, // ADDSC_A_rr_v110 |
1991 | 0 | 0U, // ADDSC_A_srrs |
1992 | 0 | 0U, // ADDSC_A_srrs_v110 |
1993 | 0 | 0U, // ADDS_BU_rr_v110 |
1994 | 0 | 0U, // ADDS_B_rr |
1995 | 0 | 0U, // ADDS_H |
1996 | 0 | 0U, // ADDS_HU |
1997 | 0 | 0U, // ADDS_U |
1998 | 0 | 0U, // ADDS_U_rc |
1999 | 0 | 0U, // ADDS_rc |
2000 | 0 | 0U, // ADDS_rr |
2001 | 0 | 0U, // ADDS_srr |
2002 | 0 | 0U, // ADDX_rc |
2003 | 0 | 0U, // ADDX_rr |
2004 | 0 | 0U, // ADD_A_rr |
2005 | 0 | 0U, // ADD_A_src |
2006 | 0 | 0U, // ADD_A_srr |
2007 | 0 | 0U, // ADD_B_rr |
2008 | 0 | 0U, // ADD_F_rrr |
2009 | 0 | 0U, // ADD_H_rr |
2010 | 0 | 0U, // ADD_rc |
2011 | 0 | 0U, // ADD_rr |
2012 | 0 | 0U, // ADD_src |
2013 | 0 | 0U, // ADD_src_15a |
2014 | 0 | 0U, // ADD_src_a15 |
2015 | 0 | 0U, // ADD_srr |
2016 | 0 | 0U, // ADD_srr_15a |
2017 | 0 | 0U, // ADD_srr_a15 |
2018 | 0 | 0U, // ANDN_T |
2019 | 0 | 0U, // ANDN_rc |
2020 | 0 | 0U, // ANDN_rr |
2021 | 0 | 0U, // AND_ANDN_T |
2022 | 0 | 0U, // AND_AND_T |
2023 | 0 | 0U, // AND_EQ_rc |
2024 | 0 | 0U, // AND_EQ_rr |
2025 | 0 | 0U, // AND_GE_U_rc |
2026 | 0 | 0U, // AND_GE_U_rr |
2027 | 0 | 0U, // AND_GE_rc |
2028 | 0 | 0U, // AND_GE_rr |
2029 | 0 | 0U, // AND_LT_U_rc |
2030 | 0 | 0U, // AND_LT_U_rr |
2031 | 0 | 0U, // AND_LT_rc |
2032 | 0 | 0U, // AND_LT_rr |
2033 | 0 | 0U, // AND_NE_rc |
2034 | 0 | 0U, // AND_NE_rr |
2035 | 0 | 0U, // AND_NOR_T |
2036 | 0 | 0U, // AND_OR_T |
2037 | 0 | 0U, // AND_T |
2038 | 0 | 0U, // AND_rc |
2039 | 0 | 0U, // AND_rr |
2040 | 0 | 0U, // AND_sc |
2041 | 0 | 0U, // AND_sc_v110 |
2042 | 0 | 0U, // AND_srr |
2043 | 0 | 0U, // AND_srr_v110 |
2044 | 0 | 0U, // BISR_rc |
2045 | 0 | 0U, // BISR_rc_v161 |
2046 | 0 | 0U, // BISR_sc |
2047 | 0 | 0U, // BISR_sc_v110 |
2048 | 0 | 0U, // BMERGAE_rr_v110 |
2049 | 0 | 0U, // BMERGE_rr |
2050 | 0 | 0U, // BSPLIT_rr |
2051 | 0 | 0U, // BSPLIT_rr_v110 |
2052 | 0 | 0U, // CACHEA_I_bo_bso |
2053 | 0 | 0U, // CACHEA_I_bo_c |
2054 | 0 | 0U, // CACHEA_I_bo_pos |
2055 | 0 | 0U, // CACHEA_I_bo_pre |
2056 | 0 | 0U, // CACHEA_I_bo_r |
2057 | 0 | 0U, // CACHEA_WI_bo_bso |
2058 | 0 | 0U, // CACHEA_WI_bo_c |
2059 | 0 | 0U, // CACHEA_WI_bo_pos |
2060 | 0 | 0U, // CACHEA_WI_bo_pre |
2061 | 0 | 0U, // CACHEA_WI_bo_r |
2062 | 0 | 0U, // CACHEA_W_bo_bso |
2063 | 0 | 0U, // CACHEA_W_bo_c |
2064 | 0 | 0U, // CACHEA_W_bo_pos |
2065 | 0 | 0U, // CACHEA_W_bo_pre |
2066 | 0 | 0U, // CACHEA_W_bo_r |
2067 | 0 | 0U, // CACHEI_I_bo_bso |
2068 | 0 | 0U, // CACHEI_I_bo_pos |
2069 | 0 | 0U, // CACHEI_I_bo_pre |
2070 | 0 | 0U, // CACHEI_WI_bo_bso |
2071 | 0 | 0U, // CACHEI_WI_bo_pos |
2072 | 0 | 0U, // CACHEI_WI_bo_pre |
2073 | 0 | 0U, // CACHEI_W_bo_bso |
2074 | 0 | 0U, // CACHEI_W_bo_pos |
2075 | 0 | 0U, // CACHEI_W_bo_pre |
2076 | 0 | 34U, // CADDN_A_rcr_v110 |
2077 | 0 | 69U, // CADDN_A_rrr_v110 |
2078 | 0 | 34U, // CADDN_rcr |
2079 | 0 | 69U, // CADDN_rrr |
2080 | 0 | 0U, // CADDN_src |
2081 | 0 | 0U, // CADDN_srr_v110 |
2082 | 0 | 34U, // CADD_A_rcr_v110 |
2083 | 0 | 69U, // CADD_A_rrr_v110 |
2084 | 0 | 34U, // CADD_rcr |
2085 | 0 | 69U, // CADD_rrr |
2086 | 0 | 0U, // CADD_src |
2087 | 0 | 0U, // CADD_srr_v110 |
2088 | 0 | 0U, // CALLA_b |
2089 | 0 | 0U, // CALLI_rr |
2090 | 0 | 0U, // CALLI_rr_v110 |
2091 | 0 | 0U, // CALL_b |
2092 | 0 | 0U, // CALL_sb |
2093 | 0 | 0U, // CLO_B_rr_v110 |
2094 | 0 | 0U, // CLO_H_rr |
2095 | 0 | 0U, // CLO_rr |
2096 | 0 | 0U, // CLS_B_rr_v110 |
2097 | 0 | 0U, // CLS_H_rr |
2098 | 0 | 0U, // CLS_rr |
2099 | 0 | 0U, // CLZ_B_rr_v110 |
2100 | 0 | 0U, // CLZ_H_rr |
2101 | 0 | 0U, // CLZ_rr |
2102 | 0 | 0U, // CMOVN_src |
2103 | 0 | 0U, // CMOVN_srr |
2104 | 0 | 0U, // CMOV_src |
2105 | 0 | 0U, // CMOV_srr |
2106 | 0 | 0U, // CMPSWAP_W_bo_bso |
2107 | 0 | 0U, // CMPSWAP_W_bo_c |
2108 | 0 | 0U, // CMPSWAP_W_bo_pos |
2109 | 0 | 0U, // CMPSWAP_W_bo_pre |
2110 | 0 | 0U, // CMPSWAP_W_bo_r |
2111 | 0 | 0U, // CMP_F_rr |
2112 | 0 | 0U, // CRC32B_W_rr |
2113 | 0 | 0U, // CRC32L_W_rr |
2114 | 0 | 0U, // CRC32_B_rr |
2115 | 0 | 69U, // CRCN_rrr |
2116 | 0 | 69U, // CSUBN_A__rrr_v110 |
2117 | 0 | 69U, // CSUBN_rrr |
2118 | 0 | 69U, // CSUB_A__rrr_v110 |
2119 | 0 | 69U, // CSUB_rrr |
2120 | 0 | 0U, // DEBUG_sr |
2121 | 0 | 0U, // DEBUG_sys |
2122 | 0 | 98U, // DEXTR_rrpw |
2123 | 0 | 98U, // DEXTR_rrrr |
2124 | 0 | 2U, // DIFSC_A_rr_v110 |
2125 | 0 | 0U, // DISABLE_sys |
2126 | 0 | 0U, // DISABLE_sys_1 |
2127 | 0 | 0U, // DIV_F_rr |
2128 | 0 | 0U, // DIV_U_rr |
2129 | 0 | 0U, // DIV_rr |
2130 | 0 | 0U, // DSYNC_sys |
2131 | 0 | 0U, // DVADJ_rrr |
2132 | 0 | 0U, // DVADJ_rrr_v110 |
2133 | 0 | 0U, // DVADJ_srr_v110 |
2134 | 0 | 0U, // DVINIT_BU_rr |
2135 | 0 | 0U, // DVINIT_BU_rr_v110 |
2136 | 0 | 0U, // DVINIT_B_rr |
2137 | 0 | 0U, // DVINIT_B_rr_v110 |
2138 | 0 | 0U, // DVINIT_HU_rr |
2139 | 0 | 0U, // DVINIT_HU_rr_v110 |
2140 | 0 | 0U, // DVINIT_H_rr |
2141 | 0 | 0U, // DVINIT_H_rr_v110 |
2142 | 0 | 0U, // DVINIT_U_rr |
2143 | 0 | 0U, // DVINIT_U_rr_v110 |
2144 | 0 | 0U, // DVINIT_rr |
2145 | 0 | 0U, // DVINIT_rr_v110 |
2146 | 0 | 0U, // DVSTEP_U_rrr |
2147 | 0 | 0U, // DVSTEP_U_rrrv110 |
2148 | 0 | 0U, // DVSTEP_Uv110 |
2149 | 0 | 0U, // DVSTEP_rrr |
2150 | 0 | 0U, // DVSTEP_rrrv110 |
2151 | 0 | 0U, // DVSTEPv110 |
2152 | 0 | 0U, // ENABLE_sys |
2153 | 0 | 0U, // EQANY_B_rc |
2154 | 0 | 0U, // EQANY_B_rr |
2155 | 0 | 0U, // EQANY_H_rc |
2156 | 0 | 0U, // EQANY_H_rr |
2157 | 0 | 0U, // EQZ_A_rr |
2158 | 0 | 0U, // EQ_A_rr |
2159 | 0 | 0U, // EQ_B_rr |
2160 | 0 | 0U, // EQ_H_rr |
2161 | 0 | 0U, // EQ_W_rr |
2162 | 0 | 0U, // EQ_rc |
2163 | 0 | 0U, // EQ_rr |
2164 | 0 | 0U, // EQ_src |
2165 | 0 | 0U, // EQ_srr |
2166 | 0 | 7U, // EXTR_U_rrpw |
2167 | 0 | 0U, // EXTR_U_rrrr |
2168 | 0 | 7U, // EXTR_U_rrrw |
2169 | 0 | 7U, // EXTR_rrpw |
2170 | 0 | 0U, // EXTR_rrrr |
2171 | 0 | 7U, // EXTR_rrrw |
2172 | 0 | 0U, // FCALLA_b |
2173 | 0 | 0U, // FCALLA_i |
2174 | 0 | 0U, // FCALL_b |
2175 | 0 | 0U, // FRET_sr |
2176 | 0 | 0U, // FRET_sys |
2177 | 0 | 0U, // FTOHP_rr |
2178 | 0 | 0U, // FTOIZ_rr |
2179 | 0 | 0U, // FTOI_rr |
2180 | 0 | 0U, // FTOQ31Z_rr |
2181 | 0 | 0U, // FTOQ31_rr |
2182 | 0 | 0U, // FTOUZ_rr |
2183 | 0 | 0U, // FTOU_rr |
2184 | 0 | 0U, // GE_A_rr |
2185 | 0 | 0U, // GE_U_rc |
2186 | 0 | 0U, // GE_U_rr |
2187 | 0 | 0U, // GE_rc |
2188 | 0 | 0U, // GE_rr |
2189 | 0 | 0U, // HPTOF_rr |
2190 | 0 | 7U, // IMASK_rcpw |
2191 | 0 | 7U, // IMASK_rcrw |
2192 | 0 | 7U, // IMASK_rrpw |
2193 | 0 | 7U, // IMASK_rrrw |
2194 | 0 | 610U, // INSERT_rcpw |
2195 | 0 | 98U, // INSERT_rcrr |
2196 | 0 | 1157U, // INSERT_rcrw |
2197 | 0 | 610U, // INSERT_rrpw |
2198 | 0 | 98U, // INSERT_rrrr |
2199 | 0 | 610U, // INSERT_rrrw |
2200 | 0 | 0U, // INSN_T |
2201 | 0 | 0U, // INS_T |
2202 | 0 | 0U, // ISYNC_sys |
2203 | 0 | 0U, // ITOF_rr |
2204 | 0 | 0U, // IXMAX_U_rrr |
2205 | 0 | 0U, // IXMAX_rrr |
2206 | 0 | 0U, // IXMIN_U_rrr |
2207 | 0 | 0U, // IXMIN_rrr |
2208 | 0 | 0U, // JA_b |
2209 | 0 | 1U, // JEQ_A_brr |
2210 | 0 | 1U, // JEQ_brc |
2211 | 0 | 1U, // JEQ_brr |
2212 | 0 | 0U, // JEQ_sbc1 |
2213 | 0 | 0U, // JEQ_sbc2 |
2214 | 0 | 0U, // JEQ_sbc_v110 |
2215 | 0 | 0U, // JEQ_sbr1 |
2216 | 0 | 0U, // JEQ_sbr2 |
2217 | 0 | 0U, // JEQ_sbr_v110 |
2218 | 0 | 0U, // JGEZ_sbr |
2219 | 0 | 0U, // JGEZ_sbr_v110 |
2220 | 0 | 1U, // JGE_U_brc |
2221 | 0 | 1U, // JGE_U_brr |
2222 | 0 | 1U, // JGE_brc |
2223 | 0 | 1U, // JGE_brr |
2224 | 0 | 0U, // JGTZ_sbr |
2225 | 0 | 0U, // JGTZ_sbr_v110 |
2226 | 0 | 0U, // JI_rr |
2227 | 0 | 0U, // JI_rr_v110 |
2228 | 0 | 0U, // JI_sbr_v110 |
2229 | 0 | 0U, // JI_sr |
2230 | 0 | 0U, // JLA_b |
2231 | 0 | 0U, // JLEZ_sbr |
2232 | 0 | 0U, // JLEZ_sbr_v110 |
2233 | 0 | 0U, // JLI_rr |
2234 | 0 | 0U, // JLI_rr_v110 |
2235 | 0 | 0U, // JLTZ_sbr |
2236 | 0 | 0U, // JLTZ_sbr_v110 |
2237 | 0 | 1U, // JLT_U_brc |
2238 | 0 | 1U, // JLT_U_brr |
2239 | 0 | 1U, // JLT_brc |
2240 | 0 | 1U, // JLT_brr |
2241 | 0 | 0U, // JL_b |
2242 | 0 | 1U, // JNED_brc |
2243 | 0 | 1U, // JNED_brr |
2244 | 0 | 1U, // JNEI_brc |
2245 | 0 | 1U, // JNEI_brr |
2246 | 0 | 1U, // JNE_A_brr |
2247 | 0 | 1U, // JNE_brc |
2248 | 0 | 1U, // JNE_brr |
2249 | 0 | 0U, // JNE_sbc1 |
2250 | 0 | 0U, // JNE_sbc2 |
2251 | 0 | 0U, // JNE_sbc_v110 |
2252 | 0 | 0U, // JNE_sbr1 |
2253 | 0 | 0U, // JNE_sbr2 |
2254 | 0 | 0U, // JNE_sbr_v110 |
2255 | 0 | 0U, // JNZ_A_brr |
2256 | 0 | 0U, // JNZ_A_sbr |
2257 | 0 | 1U, // JNZ_T_brn |
2258 | 0 | 0U, // JNZ_T_sbrn |
2259 | 0 | 0U, // JNZ_T_sbrn_v110 |
2260 | 0 | 0U, // JNZ_sb |
2261 | 0 | 0U, // JNZ_sb_v110 |
2262 | 0 | 0U, // JNZ_sbr |
2263 | 0 | 0U, // JNZ_sbr_v110 |
2264 | 0 | 0U, // JZ_A_brr |
2265 | 0 | 0U, // JZ_A_sbr |
2266 | 0 | 1U, // JZ_T_brn |
2267 | 0 | 0U, // JZ_T_sbrn |
2268 | 0 | 0U, // JZ_T_sbrn_v110 |
2269 | 0 | 0U, // JZ_sb |
2270 | 0 | 0U, // JZ_sb_v110 |
2271 | 0 | 0U, // JZ_sbr |
2272 | 0 | 0U, // JZ_sbr_v110 |
2273 | 0 | 0U, // J_b |
2274 | 0 | 0U, // J_sb |
2275 | 0 | 0U, // J_sb_v110 |
2276 | 0 | 0U, // LDLCX_abs |
2277 | 0 | 0U, // LDLCX_bo_bso |
2278 | 0 | 0U, // LDMST_abs |
2279 | 0 | 0U, // LDMST_bo_bso |
2280 | 0 | 0U, // LDMST_bo_c |
2281 | 0 | 0U, // LDMST_bo_pos |
2282 | 0 | 0U, // LDMST_bo_pre |
2283 | 0 | 0U, // LDMST_bo_r |
2284 | 0 | 0U, // LDUCX_abs |
2285 | 0 | 0U, // LDUCX_bo_bso |
2286 | 0 | 0U, // LD_A_abs |
2287 | 0 | 0U, // LD_A_bo_bso |
2288 | 0 | 0U, // LD_A_bo_c |
2289 | 0 | 0U, // LD_A_bo_pos |
2290 | 0 | 0U, // LD_A_bo_pre |
2291 | 0 | 0U, // LD_A_bo_r |
2292 | 0 | 0U, // LD_A_bol |
2293 | 0 | 0U, // LD_A_sc |
2294 | 0 | 0U, // LD_A_slr |
2295 | 0 | 0U, // LD_A_slr_post |
2296 | 0 | 0U, // LD_A_slr_post_v110 |
2297 | 0 | 0U, // LD_A_slr_v110 |
2298 | 0 | 0U, // LD_A_slro |
2299 | 0 | 0U, // LD_A_slro_v110 |
2300 | 0 | 0U, // LD_A_sro |
2301 | 0 | 0U, // LD_A_sro_v110 |
2302 | 0 | 0U, // LD_BU_abs |
2303 | 0 | 0U, // LD_BU_bo_bso |
2304 | 0 | 0U, // LD_BU_bo_c |
2305 | 0 | 0U, // LD_BU_bo_pos |
2306 | 0 | 0U, // LD_BU_bo_pre |
2307 | 0 | 0U, // LD_BU_bo_r |
2308 | 0 | 0U, // LD_BU_bol |
2309 | 0 | 0U, // LD_BU_slr |
2310 | 0 | 0U, // LD_BU_slr_post |
2311 | 0 | 0U, // LD_BU_slr_post_v110 |
2312 | 0 | 0U, // LD_BU_slr_v110 |
2313 | 0 | 0U, // LD_BU_slro |
2314 | 0 | 0U, // LD_BU_slro_v110 |
2315 | 0 | 0U, // LD_BU_sro |
2316 | 0 | 0U, // LD_BU_sro_v110 |
2317 | 0 | 0U, // LD_B_abs |
2318 | 0 | 0U, // LD_B_bo_bso |
2319 | 0 | 0U, // LD_B_bo_c |
2320 | 0 | 0U, // LD_B_bo_pos |
2321 | 0 | 0U, // LD_B_bo_pre |
2322 | 0 | 0U, // LD_B_bo_r |
2323 | 0 | 0U, // LD_B_bol |
2324 | 0 | 0U, // LD_B_slr_post_v110 |
2325 | 0 | 0U, // LD_B_slr_v110 |
2326 | 0 | 0U, // LD_B_slro_v110 |
2327 | 0 | 0U, // LD_B_sro_v110 |
2328 | 0 | 0U, // LD_DA_abs |
2329 | 0 | 0U, // LD_DA_bo_bso |
2330 | 0 | 0U, // LD_DA_bo_c |
2331 | 0 | 0U, // LD_DA_bo_pos |
2332 | 0 | 0U, // LD_DA_bo_pre |
2333 | 0 | 0U, // LD_DA_bo_r |
2334 | 0 | 0U, // LD_D_abs |
2335 | 0 | 0U, // LD_D_bo_bso |
2336 | 0 | 0U, // LD_D_bo_c |
2337 | 0 | 0U, // LD_D_bo_pos |
2338 | 0 | 0U, // LD_D_bo_pre |
2339 | 0 | 0U, // LD_D_bo_r |
2340 | 0 | 0U, // LD_HU_abs |
2341 | 0 | 0U, // LD_HU_bo_bso |
2342 | 0 | 0U, // LD_HU_bo_c |
2343 | 0 | 0U, // LD_HU_bo_pos |
2344 | 0 | 0U, // LD_HU_bo_pre |
2345 | 0 | 0U, // LD_HU_bo_r |
2346 | 0 | 0U, // LD_HU_bol |
2347 | 0 | 0U, // LD_H_abs |
2348 | 0 | 0U, // LD_H_bo_bso |
2349 | 0 | 0U, // LD_H_bo_c |
2350 | 0 | 0U, // LD_H_bo_pos |
2351 | 0 | 0U, // LD_H_bo_pre |
2352 | 0 | 0U, // LD_H_bo_r |
2353 | 0 | 0U, // LD_H_bol |
2354 | 0 | 0U, // LD_H_slr |
2355 | 0 | 0U, // LD_H_slr_post |
2356 | 0 | 0U, // LD_H_slr_post_v110 |
2357 | 0 | 0U, // LD_H_slr_v110 |
2358 | 0 | 0U, // LD_H_slro |
2359 | 0 | 0U, // LD_H_slro_v110 |
2360 | 0 | 0U, // LD_H_sro |
2361 | 0 | 0U, // LD_H_sro_v110 |
2362 | 0 | 0U, // LD_Q_abs |
2363 | 0 | 0U, // LD_Q_bo_bso |
2364 | 0 | 0U, // LD_Q_bo_c |
2365 | 0 | 0U, // LD_Q_bo_pos |
2366 | 0 | 0U, // LD_Q_bo_pre |
2367 | 0 | 0U, // LD_Q_bo_r |
2368 | 0 | 0U, // LD_W_abs |
2369 | 0 | 0U, // LD_W_bo_bso |
2370 | 0 | 0U, // LD_W_bo_c |
2371 | 0 | 0U, // LD_W_bo_pos |
2372 | 0 | 0U, // LD_W_bo_pre |
2373 | 0 | 0U, // LD_W_bo_r |
2374 | 0 | 0U, // LD_W_bol |
2375 | 0 | 0U, // LD_W_sc |
2376 | 0 | 0U, // LD_W_slr |
2377 | 0 | 0U, // LD_W_slr_post |
2378 | 0 | 0U, // LD_W_slr_post_v110 |
2379 | 0 | 0U, // LD_W_slr_v110 |
2380 | 0 | 0U, // LD_W_slro |
2381 | 0 | 0U, // LD_W_slro_v110 |
2382 | 0 | 0U, // LD_W_sro |
2383 | 0 | 0U, // LD_W_sro_v110 |
2384 | 0 | 0U, // LEA_abs |
2385 | 0 | 0U, // LEA_bo_bso |
2386 | 0 | 0U, // LEA_bol |
2387 | 0 | 0U, // LHA_abs |
2388 | 0 | 0U, // LOOPU_brr |
2389 | 0 | 0U, // LOOP_brr |
2390 | 0 | 0U, // LOOP_sbr |
2391 | 0 | 0U, // LT_A_rr |
2392 | 0 | 0U, // LT_B |
2393 | 0 | 0U, // LT_BU |
2394 | 0 | 0U, // LT_H |
2395 | 0 | 0U, // LT_HU |
2396 | 0 | 0U, // LT_U_rc |
2397 | 0 | 0U, // LT_U_rr |
2398 | 0 | 0U, // LT_U_srcv110 |
2399 | 0 | 0U, // LT_U_srrv110 |
2400 | 0 | 0U, // LT_W |
2401 | 0 | 0U, // LT_WU |
2402 | 0 | 0U, // LT_rc |
2403 | 0 | 0U, // LT_rr |
2404 | 0 | 0U, // LT_src |
2405 | 0 | 0U, // LT_srr |
2406 | 0 | 165U, // MADDMS_H_rrr1_LL |
2407 | 0 | 197U, // MADDMS_H_rrr1_LU |
2408 | 0 | 229U, // MADDMS_H_rrr1_UL |
2409 | 0 | 261U, // MADDMS_H_rrr1_UU |
2410 | 0 | 290U, // MADDMS_U_rcr_v110 |
2411 | 0 | 69U, // MADDMS_U_rrr2_v110 |
2412 | 0 | 34U, // MADDMS_rcr_v110 |
2413 | 0 | 69U, // MADDMS_rrr2_v110 |
2414 | 0 | 165U, // MADDM_H_rrr1_LL |
2415 | 0 | 197U, // MADDM_H_rrr1_LU |
2416 | 0 | 229U, // MADDM_H_rrr1_UL |
2417 | 0 | 261U, // MADDM_H_rrr1_UU |
2418 | 0 | 69U, // MADDM_H_rrr1_v110 |
2419 | 0 | 69U, // MADDM_Q_rrr1_v110 |
2420 | 0 | 290U, // MADDM_U_rcr_v110 |
2421 | 0 | 69U, // MADDM_U_rrr2_v110 |
2422 | 0 | 34U, // MADDM_rcr_v110 |
2423 | 0 | 69U, // MADDM_rrr2_v110 |
2424 | 0 | 165U, // MADDRS_H_rrr1_LL |
2425 | 0 | 197U, // MADDRS_H_rrr1_LU |
2426 | 0 | 229U, // MADDRS_H_rrr1_UL |
2427 | 0 | 229U, // MADDRS_H_rrr1_UL_2 |
2428 | 0 | 261U, // MADDRS_H_rrr1_UU |
2429 | 0 | 1669U, // MADDRS_H_rrr1_v110 |
2430 | 0 | 1U, // MADDRS_Q_rrr1_L_L |
2431 | 0 | 1U, // MADDRS_Q_rrr1_U_U |
2432 | 0 | 1669U, // MADDRS_Q_rrr1_v110 |
2433 | 0 | 165U, // MADDR_H_rrr1_LL |
2434 | 0 | 197U, // MADDR_H_rrr1_LU |
2435 | 0 | 229U, // MADDR_H_rrr1_UL |
2436 | 0 | 229U, // MADDR_H_rrr1_UL_2 |
2437 | 0 | 261U, // MADDR_H_rrr1_UU |
2438 | 0 | 1669U, // MADDR_H_rrr1_v110 |
2439 | 0 | 1U, // MADDR_Q_rrr1_L_L |
2440 | 0 | 1U, // MADDR_Q_rrr1_U_U |
2441 | 0 | 1669U, // MADDR_Q_rrr1_v110 |
2442 | 0 | 165U, // MADDSUMS_H_rrr1_LL |
2443 | 0 | 197U, // MADDSUMS_H_rrr1_LU |
2444 | 0 | 229U, // MADDSUMS_H_rrr1_UL |
2445 | 0 | 261U, // MADDSUMS_H_rrr1_UU |
2446 | 0 | 165U, // MADDSUM_H_rrr1_LL |
2447 | 0 | 197U, // MADDSUM_H_rrr1_LU |
2448 | 0 | 229U, // MADDSUM_H_rrr1_UL |
2449 | 0 | 261U, // MADDSUM_H_rrr1_UU |
2450 | 0 | 165U, // MADDSURS_H_rrr1_LL |
2451 | 0 | 197U, // MADDSURS_H_rrr1_LU |
2452 | 0 | 229U, // MADDSURS_H_rrr1_UL |
2453 | 0 | 261U, // MADDSURS_H_rrr1_UU |
2454 | 0 | 165U, // MADDSUR_H_rrr1_LL |
2455 | 0 | 197U, // MADDSUR_H_rrr1_LU |
2456 | 0 | 229U, // MADDSUR_H_rrr1_UL |
2457 | 0 | 261U, // MADDSUR_H_rrr1_UU |
2458 | 0 | 165U, // MADDSUS_H_rrr1_LL |
2459 | 0 | 197U, // MADDSUS_H_rrr1_LU |
2460 | 0 | 229U, // MADDSUS_H_rrr1_UL |
2461 | 0 | 261U, // MADDSUS_H_rrr1_UU |
2462 | 0 | 165U, // MADDSU_H_rrr1_LL |
2463 | 0 | 197U, // MADDSU_H_rrr1_LU |
2464 | 0 | 229U, // MADDSU_H_rrr1_UL |
2465 | 0 | 261U, // MADDSU_H_rrr1_UU |
2466 | 0 | 165U, // MADDS_H_rrr1_LL |
2467 | 0 | 197U, // MADDS_H_rrr1_LU |
2468 | 0 | 229U, // MADDS_H_rrr1_UL |
2469 | 0 | 261U, // MADDS_H_rrr1_UU |
2470 | 0 | 1669U, // MADDS_H_rrr1_v110 |
2471 | 0 | 1669U, // MADDS_Q_rrr1 |
2472 | 0 | 325U, // MADDS_Q_rrr1_L |
2473 | 0 | 1U, // MADDS_Q_rrr1_L_L |
2474 | 0 | 357U, // MADDS_Q_rrr1_U |
2475 | 0 | 1669U, // MADDS_Q_rrr1_UU2_v110 |
2476 | 0 | 1U, // MADDS_Q_rrr1_U_U |
2477 | 0 | 1669U, // MADDS_Q_rrr1_e |
2478 | 0 | 325U, // MADDS_Q_rrr1_e_L |
2479 | 0 | 1U, // MADDS_Q_rrr1_e_L_L |
2480 | 0 | 357U, // MADDS_Q_rrr1_e_U |
2481 | 0 | 1U, // MADDS_Q_rrr1_e_U_U |
2482 | 0 | 34U, // MADDS_U_rcr |
2483 | 0 | 34U, // MADDS_U_rcr_e |
2484 | 0 | 69U, // MADDS_U_rrr2 |
2485 | 0 | 69U, // MADDS_U_rrr2_e |
2486 | 0 | 34U, // MADDS_rcr |
2487 | 0 | 34U, // MADDS_rcr_e |
2488 | 0 | 69U, // MADDS_rrr2 |
2489 | 0 | 69U, // MADDS_rrr2_e |
2490 | 0 | 69U, // MADD_F_rrr |
2491 | 0 | 165U, // MADD_H_rrr1_LL |
2492 | 0 | 197U, // MADD_H_rrr1_LU |
2493 | 0 | 229U, // MADD_H_rrr1_UL |
2494 | 0 | 261U, // MADD_H_rrr1_UU |
2495 | 0 | 1669U, // MADD_H_rrr1_v110 |
2496 | 0 | 1669U, // MADD_Q_rrr1 |
2497 | 0 | 325U, // MADD_Q_rrr1_L |
2498 | 0 | 1U, // MADD_Q_rrr1_L_L |
2499 | 0 | 357U, // MADD_Q_rrr1_U |
2500 | 0 | 1669U, // MADD_Q_rrr1_UU2_v110 |
2501 | 0 | 1U, // MADD_Q_rrr1_U_U |
2502 | 0 | 1669U, // MADD_Q_rrr1_e |
2503 | 0 | 325U, // MADD_Q_rrr1_e_L |
2504 | 0 | 1U, // MADD_Q_rrr1_e_L_L |
2505 | 0 | 357U, // MADD_Q_rrr1_e_U |
2506 | 0 | 1U, // MADD_Q_rrr1_e_U_U |
2507 | 0 | 290U, // MADD_U_rcr |
2508 | 0 | 69U, // MADD_U_rrr2 |
2509 | 0 | 34U, // MADD_rcr |
2510 | 0 | 34U, // MADD_rcr_e |
2511 | 0 | 69U, // MADD_rrr2 |
2512 | 0 | 69U, // MADD_rrr2_e |
2513 | 0 | 0U, // MAX_B |
2514 | 0 | 0U, // MAX_BU |
2515 | 0 | 0U, // MAX_H |
2516 | 0 | 0U, // MAX_HU |
2517 | 0 | 0U, // MAX_U_rc |
2518 | 0 | 0U, // MAX_U_rr |
2519 | 0 | 0U, // MAX_rc |
2520 | 0 | 0U, // MAX_rr |
2521 | 0 | 0U, // MFCR_rlc |
2522 | 0 | 0U, // MIN_B |
2523 | 0 | 0U, // MIN_BU |
2524 | 0 | 0U, // MIN_H |
2525 | 0 | 0U, // MIN_HU |
2526 | 0 | 0U, // MIN_U_rc |
2527 | 0 | 0U, // MIN_U_rr |
2528 | 0 | 0U, // MIN_rc |
2529 | 0 | 0U, // MIN_rr |
2530 | 0 | 0U, // MOVH_A_rlc |
2531 | 0 | 0U, // MOVH_rlc |
2532 | 0 | 0U, // MOVZ_A_sr |
2533 | 0 | 0U, // MOV_AA_rr |
2534 | 0 | 0U, // MOV_AA_srr_srr |
2535 | 0 | 0U, // MOV_AA_srr_srr_v110 |
2536 | 0 | 0U, // MOV_A_rr |
2537 | 0 | 0U, // MOV_A_src |
2538 | 0 | 0U, // MOV_A_srr |
2539 | 0 | 0U, // MOV_A_srr_v110 |
2540 | 0 | 0U, // MOV_D_rr |
2541 | 0 | 0U, // MOV_D_srr_srr |
2542 | 0 | 0U, // MOV_D_srr_srr_v110 |
2543 | 0 | 0U, // MOV_U_rlc |
2544 | 0 | 0U, // MOV_rlc |
2545 | 0 | 0U, // MOV_rlc_e |
2546 | 0 | 0U, // MOV_rr |
2547 | 0 | 0U, // MOV_rr_e |
2548 | 0 | 0U, // MOV_rr_eab |
2549 | 0 | 0U, // MOV_sc |
2550 | 0 | 0U, // MOV_sc_v110 |
2551 | 0 | 0U, // MOV_src |
2552 | 0 | 0U, // MOV_src_e |
2553 | 0 | 0U, // MOV_srr |
2554 | 0 | 165U, // MSUBADMS_H_rrr1_LL |
2555 | 0 | 197U, // MSUBADMS_H_rrr1_LU |
2556 | 0 | 229U, // MSUBADMS_H_rrr1_UL |
2557 | 0 | 261U, // MSUBADMS_H_rrr1_UU |
2558 | 0 | 165U, // MSUBADM_H_rrr1_LL |
2559 | 0 | 197U, // MSUBADM_H_rrr1_LU |
2560 | 0 | 229U, // MSUBADM_H_rrr1_UL |
2561 | 0 | 261U, // MSUBADM_H_rrr1_UU |
2562 | 0 | 165U, // MSUBADRS_H_rrr1_LL |
2563 | 0 | 197U, // MSUBADRS_H_rrr1_LU |
2564 | 0 | 229U, // MSUBADRS_H_rrr1_UL |
2565 | 0 | 261U, // MSUBADRS_H_rrr1_UU |
2566 | 0 | 1669U, // MSUBADRS_H_rrr1_v110 |
2567 | 0 | 165U, // MSUBADR_H_rrr1_LL |
2568 | 0 | 197U, // MSUBADR_H_rrr1_LU |
2569 | 0 | 229U, // MSUBADR_H_rrr1_UL |
2570 | 0 | 261U, // MSUBADR_H_rrr1_UU |
2571 | 0 | 1669U, // MSUBADR_H_rrr1_v110 |
2572 | 0 | 165U, // MSUBADS_H_rrr1_LL |
2573 | 0 | 197U, // MSUBADS_H_rrr1_LU |
2574 | 0 | 229U, // MSUBADS_H_rrr1_UL |
2575 | 0 | 261U, // MSUBADS_H_rrr1_UU |
2576 | 0 | 165U, // MSUBAD_H_rrr1_LL |
2577 | 0 | 197U, // MSUBAD_H_rrr1_LU |
2578 | 0 | 229U, // MSUBAD_H_rrr1_UL |
2579 | 0 | 261U, // MSUBAD_H_rrr1_UU |
2580 | 0 | 165U, // MSUBMS_H_rrr1_LL |
2581 | 0 | 197U, // MSUBMS_H_rrr1_LU |
2582 | 0 | 229U, // MSUBMS_H_rrr1_UL |
2583 | 0 | 261U, // MSUBMS_H_rrr1_UU |
2584 | 0 | 34U, // MSUBMS_U_rcrv110 |
2585 | 0 | 69U, // MSUBMS_U_rrr2v110 |
2586 | 0 | 34U, // MSUBMS_rcrv110 |
2587 | 0 | 69U, // MSUBMS_rrr2v110 |
2588 | 0 | 165U, // MSUBM_H_rrr1_LL |
2589 | 0 | 197U, // MSUBM_H_rrr1_LU |
2590 | 0 | 229U, // MSUBM_H_rrr1_UL |
2591 | 0 | 261U, // MSUBM_H_rrr1_UU |
2592 | 0 | 69U, // MSUBM_H_rrr1_v110 |
2593 | 0 | 69U, // MSUBM_Q_rrr1_v110 |
2594 | 0 | 34U, // MSUBM_U_rcrv110 |
2595 | 0 | 69U, // MSUBM_U_rrr2v110 |
2596 | 0 | 34U, // MSUBM_rcrv110 |
2597 | 0 | 69U, // MSUBM_rrr2v110 |
2598 | 0 | 165U, // MSUBRS_H_rrr1_LL |
2599 | 0 | 197U, // MSUBRS_H_rrr1_LU |
2600 | 0 | 229U, // MSUBRS_H_rrr1_UL |
2601 | 0 | 229U, // MSUBRS_H_rrr1_UL_2 |
2602 | 0 | 261U, // MSUBRS_H_rrr1_UU |
2603 | 0 | 1669U, // MSUBRS_H_rrr1_v110 |
2604 | 0 | 1U, // MSUBRS_Q_rrr1_L_L |
2605 | 0 | 1U, // MSUBRS_Q_rrr1_U_U |
2606 | 0 | 1669U, // MSUBRS_Q_rrr1_v110 |
2607 | 0 | 165U, // MSUBR_H_rrr1_LL |
2608 | 0 | 197U, // MSUBR_H_rrr1_LU |
2609 | 0 | 229U, // MSUBR_H_rrr1_UL |
2610 | 0 | 229U, // MSUBR_H_rrr1_UL_2 |
2611 | 0 | 261U, // MSUBR_H_rrr1_UU |
2612 | 0 | 1669U, // MSUBR_H_rrr1_v110 |
2613 | 0 | 1U, // MSUBR_Q_rrr1_L_L |
2614 | 0 | 1U, // MSUBR_Q_rrr1_U_U |
2615 | 0 | 1669U, // MSUBR_Q_rrr1_v110 |
2616 | 0 | 165U, // MSUBS_H_rrr1_LL |
2617 | 0 | 197U, // MSUBS_H_rrr1_LU |
2618 | 0 | 229U, // MSUBS_H_rrr1_UL |
2619 | 0 | 261U, // MSUBS_H_rrr1_UU |
2620 | 0 | 1669U, // MSUBS_H_rrr1_v110 |
2621 | 0 | 1669U, // MSUBS_Q_rrr1 |
2622 | 0 | 325U, // MSUBS_Q_rrr1_L |
2623 | 0 | 1U, // MSUBS_Q_rrr1_L_L |
2624 | 0 | 357U, // MSUBS_Q_rrr1_U |
2625 | 0 | 1669U, // MSUBS_Q_rrr1_UU2_v110 |
2626 | 0 | 1U, // MSUBS_Q_rrr1_U_U |
2627 | 0 | 1669U, // MSUBS_Q_rrr1_e |
2628 | 0 | 325U, // MSUBS_Q_rrr1_e_L |
2629 | 0 | 1U, // MSUBS_Q_rrr1_e_L_L |
2630 | 0 | 357U, // MSUBS_Q_rrr1_e_U |
2631 | 0 | 1U, // MSUBS_Q_rrr1_e_U_U |
2632 | 0 | 34U, // MSUBS_U_rcr |
2633 | 0 | 34U, // MSUBS_U_rcr_e |
2634 | 0 | 69U, // MSUBS_U_rrr2 |
2635 | 0 | 69U, // MSUBS_U_rrr2_e |
2636 | 0 | 34U, // MSUBS_rcr |
2637 | 0 | 34U, // MSUBS_rcr_e |
2638 | 0 | 69U, // MSUBS_rrr2 |
2639 | 0 | 69U, // MSUBS_rrr2_e |
2640 | 0 | 69U, // MSUB_F_rrr |
2641 | 0 | 165U, // MSUB_H_rrr1_LL |
2642 | 0 | 197U, // MSUB_H_rrr1_LU |
2643 | 0 | 229U, // MSUB_H_rrr1_UL |
2644 | 0 | 261U, // MSUB_H_rrr1_UU |
2645 | 0 | 1669U, // MSUB_H_rrr1_v110 |
2646 | 0 | 1669U, // MSUB_Q_rrr1 |
2647 | 0 | 325U, // MSUB_Q_rrr1_L |
2648 | 0 | 1U, // MSUB_Q_rrr1_L_L |
2649 | 0 | 357U, // MSUB_Q_rrr1_U |
2650 | 0 | 1669U, // MSUB_Q_rrr1_UU2_v110 |
2651 | 0 | 1U, // MSUB_Q_rrr1_U_U |
2652 | 0 | 1669U, // MSUB_Q_rrr1_e |
2653 | 0 | 325U, // MSUB_Q_rrr1_e_L |
2654 | 0 | 1U, // MSUB_Q_rrr1_e_L_L |
2655 | 0 | 357U, // MSUB_Q_rrr1_e_U |
2656 | 0 | 1U, // MSUB_Q_rrr1_e_U_U |
2657 | 0 | 290U, // MSUB_U_rcr |
2658 | 0 | 69U, // MSUB_U_rrr2 |
2659 | 0 | 34U, // MSUB_rcr |
2660 | 0 | 34U, // MSUB_rcr_e |
2661 | 0 | 69U, // MSUB_rrr2 |
2662 | 0 | 69U, // MSUB_rrr2_e |
2663 | 0 | 0U, // MTCR_rlc |
2664 | 0 | 8U, // MULMS_H_rr1_LL2e |
2665 | 0 | 10U, // MULMS_H_rr1_LU2e |
2666 | 0 | 12U, // MULMS_H_rr1_UL2e |
2667 | 0 | 14U, // MULMS_H_rr1_UU2e |
2668 | 0 | 8U, // MULM_H_rr1_LL2e |
2669 | 0 | 10U, // MULM_H_rr1_LU2e |
2670 | 0 | 12U, // MULM_H_rr1_UL2e |
2671 | 0 | 14U, // MULM_H_rr1_UU2e |
2672 | 0 | 0U, // MULM_U_rc |
2673 | 0 | 0U, // MULM_U_rr |
2674 | 0 | 0U, // MULM_rc |
2675 | 0 | 0U, // MULM_rr |
2676 | 0 | 8U, // MULR_H_rr1_LL2e |
2677 | 0 | 10U, // MULR_H_rr1_LU2e |
2678 | 0 | 12U, // MULR_H_rr1_UL2e |
2679 | 0 | 14U, // MULR_H_rr1_UU2e |
2680 | 0 | 2U, // MULR_H_rr_v110 |
2681 | 0 | 0U, // MULR_Q_rr1_2LL |
2682 | 0 | 0U, // MULR_Q_rr1_2UU |
2683 | 0 | 2U, // MULR_Q_rr_v110 |
2684 | 0 | 0U, // MULS_U_rc |
2685 | 0 | 0U, // MULS_U_rr2 |
2686 | 0 | 0U, // MULS_U_rr_v110 |
2687 | 0 | 0U, // MULS_rc |
2688 | 0 | 0U, // MULS_rr2 |
2689 | 0 | 0U, // MULS_rr_v110 |
2690 | 0 | 0U, // MUL_F_rrr |
2691 | 0 | 8U, // MUL_H_rr1_LL2e |
2692 | 0 | 10U, // MUL_H_rr1_LU2e |
2693 | 0 | 12U, // MUL_H_rr1_UL2e |
2694 | 0 | 14U, // MUL_H_rr1_UU2e |
2695 | 0 | 2U, // MUL_H_rr_v110 |
2696 | 0 | 2U, // MUL_Q_rr1_2 |
2697 | 0 | 0U, // MUL_Q_rr1_2LL |
2698 | 0 | 0U, // MUL_Q_rr1_2UU |
2699 | 0 | 16U, // MUL_Q_rr1_2_L |
2700 | 0 | 16U, // MUL_Q_rr1_2_Le |
2701 | 0 | 18U, // MUL_Q_rr1_2_U |
2702 | 0 | 18U, // MUL_Q_rr1_2_Ue |
2703 | 0 | 2U, // MUL_Q_rr1_2__e |
2704 | 0 | 2U, // MUL_Q_rr_v110 |
2705 | 0 | 0U, // MUL_U_rc |
2706 | 0 | 0U, // MUL_U_rr2 |
2707 | 0 | 0U, // MUL_rc |
2708 | 0 | 0U, // MUL_rc_e |
2709 | 0 | 0U, // MUL_rr2 |
2710 | 0 | 0U, // MUL_rr2_e |
2711 | 0 | 0U, // MUL_rr_v110 |
2712 | 0 | 0U, // MUL_srr |
2713 | 0 | 0U, // NAND_T |
2714 | 0 | 0U, // NAND_rc |
2715 | 0 | 0U, // NAND_rr |
2716 | 0 | 0U, // NEZ_A |
2717 | 0 | 0U, // NE_A |
2718 | 0 | 0U, // NE_rc |
2719 | 0 | 0U, // NE_rr |
2720 | 0 | 0U, // NOP_sr |
2721 | 0 | 0U, // NOP_sys |
2722 | 0 | 0U, // NOR_T |
2723 | 0 | 0U, // NOR_rc |
2724 | 0 | 0U, // NOR_rr |
2725 | 0 | 0U, // NOR_sr |
2726 | 0 | 0U, // NOR_sr_v110 |
2727 | 0 | 0U, // NOT_sr_v162 |
2728 | 0 | 0U, // ORN_T |
2729 | 0 | 0U, // ORN_rc |
2730 | 0 | 0U, // ORN_rr |
2731 | 0 | 0U, // OR_ANDN_T |
2732 | 0 | 0U, // OR_AND_T |
2733 | 0 | 0U, // OR_EQ_rc |
2734 | 0 | 0U, // OR_EQ_rr |
2735 | 0 | 0U, // OR_GE_U_rc |
2736 | 0 | 0U, // OR_GE_U_rr |
2737 | 0 | 0U, // OR_GE_rc |
2738 | 0 | 0U, // OR_GE_rr |
2739 | 0 | 0U, // OR_LT_U_rc |
2740 | 0 | 0U, // OR_LT_U_rr |
2741 | 0 | 0U, // OR_LT_rc |
2742 | 0 | 0U, // OR_LT_rr |
2743 | 0 | 0U, // OR_NE_rc |
2744 | 0 | 0U, // OR_NE_rr |
2745 | 0 | 0U, // OR_NOR_T |
2746 | 0 | 0U, // OR_OR_T |
2747 | 0 | 0U, // OR_T |
2748 | 0 | 1U, // OR_rc |
2749 | 0 | 0U, // OR_rr |
2750 | 0 | 0U, // OR_sc |
2751 | 0 | 0U, // OR_sc_v110 |
2752 | 0 | 0U, // OR_srr |
2753 | 0 | 0U, // OR_srr_v110 |
2754 | 0 | 0U, // PACK_rrr |
2755 | 0 | 0U, // PARITY_rr |
2756 | 0 | 0U, // PARITY_rr_v110 |
2757 | 0 | 0U, // POPCNT_W_rr |
2758 | 0 | 0U, // Q31TOF_rr |
2759 | 0 | 0U, // QSEED_F_rr |
2760 | 0 | 0U, // RESTORE_sys |
2761 | 0 | 0U, // RET_sr |
2762 | 0 | 0U, // RET_sys |
2763 | 0 | 0U, // RET_sys_v110 |
2764 | 0 | 0U, // RFE_sr |
2765 | 0 | 0U, // RFE_sys_sys |
2766 | 0 | 0U, // RFE_sys_sys_v110 |
2767 | 0 | 0U, // RFM_sys |
2768 | 0 | 0U, // RSLCX_sys |
2769 | 0 | 0U, // RSTV_sys |
2770 | 0 | 0U, // RSUBS_U_rc |
2771 | 0 | 0U, // RSUBS_rc |
2772 | 0 | 0U, // RSUB_rc |
2773 | 0 | 0U, // RSUB_sr_sr |
2774 | 0 | 0U, // RSUB_sr_sr_v110 |
2775 | 0 | 0U, // SAT_BU_rr |
2776 | 0 | 0U, // SAT_BU_sr |
2777 | 0 | 0U, // SAT_BU_sr_v110 |
2778 | 0 | 0U, // SAT_B_rr |
2779 | 0 | 0U, // SAT_B_sr |
2780 | 0 | 0U, // SAT_B_sr_v110 |
2781 | 0 | 0U, // SAT_HU_rr |
2782 | 0 | 0U, // SAT_HU_sr |
2783 | 0 | 0U, // SAT_HU_sr_v110 |
2784 | 0 | 0U, // SAT_H_rr |
2785 | 0 | 0U, // SAT_H_sr |
2786 | 0 | 0U, // SAT_H_sr_v110 |
2787 | 0 | 34U, // SELN_A_rcr_v110 |
2788 | 0 | 69U, // SELN_A_rrr_v110 |
2789 | 0 | 34U, // SELN_rcr |
2790 | 0 | 69U, // SELN_rrr |
2791 | 0 | 34U, // SEL_A_rcr_v110 |
2792 | 0 | 69U, // SEL_A_rrr_v110 |
2793 | 0 | 34U, // SEL_rcr |
2794 | 0 | 69U, // SEL_rrr |
2795 | 0 | 0U, // SHAS_rc |
2796 | 0 | 0U, // SHAS_rr |
2797 | 0 | 0U, // SHA_B_rc |
2798 | 0 | 0U, // SHA_B_rr |
2799 | 0 | 0U, // SHA_H_rc |
2800 | 0 | 0U, // SHA_H_rr |
2801 | 0 | 0U, // SHA_rc |
2802 | 0 | 0U, // SHA_rr |
2803 | 0 | 0U, // SHA_src |
2804 | 0 | 0U, // SHA_src_v110 |
2805 | 0 | 0U, // SHUFFLE_rc |
2806 | 0 | 0U, // SH_ANDN_T |
2807 | 0 | 0U, // SH_AND_T |
2808 | 0 | 0U, // SH_B_rc |
2809 | 0 | 0U, // SH_B_rr |
2810 | 0 | 0U, // SH_EQ_rc |
2811 | 0 | 0U, // SH_EQ_rr |
2812 | 0 | 0U, // SH_GE_U_rc |
2813 | 0 | 0U, // SH_GE_U_rr |
2814 | 0 | 0U, // SH_GE_rc |
2815 | 0 | 0U, // SH_GE_rr |
2816 | 0 | 0U, // SH_H_rc |
2817 | 0 | 0U, // SH_H_rr |
2818 | 0 | 0U, // SH_LT_U_rc |
2819 | 0 | 0U, // SH_LT_U_rr |
2820 | 0 | 0U, // SH_LT_rc |
2821 | 0 | 0U, // SH_LT_rr |
2822 | 0 | 0U, // SH_NAND_T |
2823 | 0 | 0U, // SH_NE_rc |
2824 | 0 | 0U, // SH_NE_rr |
2825 | 0 | 0U, // SH_NOR_T |
2826 | 0 | 0U, // SH_ORN_T |
2827 | 0 | 0U, // SH_OR_T |
2828 | 0 | 0U, // SH_XNOR_T |
2829 | 0 | 0U, // SH_XOR_T |
2830 | 0 | 0U, // SH_rc |
2831 | 0 | 0U, // SH_rr |
2832 | 0 | 0U, // SH_src |
2833 | 0 | 0U, // SH_src_v110 |
2834 | 0 | 0U, // STLCX_abs |
2835 | 0 | 0U, // STLCX_bo_bso |
2836 | 0 | 0U, // STUCX_abs |
2837 | 0 | 0U, // STUCX_bo_bso |
2838 | 0 | 0U, // ST_A_abs |
2839 | 0 | 0U, // ST_A_bo_bso |
2840 | 0 | 0U, // ST_A_bo_c |
2841 | 0 | 0U, // ST_A_bo_pos |
2842 | 0 | 0U, // ST_A_bo_pre |
2843 | 0 | 0U, // ST_A_bo_r |
2844 | 0 | 0U, // ST_A_bol |
2845 | 0 | 0U, // ST_A_sc |
2846 | 0 | 0U, // ST_A_sro |
2847 | 0 | 0U, // ST_A_sro_v110 |
2848 | 0 | 0U, // ST_A_ssr |
2849 | 0 | 0U, // ST_A_ssr_pos |
2850 | 0 | 0U, // ST_A_ssr_pos_v110 |
2851 | 0 | 0U, // ST_A_ssr_v110 |
2852 | 0 | 0U, // ST_A_ssro |
2853 | 0 | 0U, // ST_A_ssro_v110 |
2854 | 0 | 0U, // ST_B_abs |
2855 | 0 | 0U, // ST_B_bo_bso |
2856 | 0 | 0U, // ST_B_bo_c |
2857 | 0 | 0U, // ST_B_bo_pos |
2858 | 0 | 0U, // ST_B_bo_pre |
2859 | 0 | 0U, // ST_B_bo_r |
2860 | 0 | 0U, // ST_B_bol |
2861 | 0 | 0U, // ST_B_sro |
2862 | 0 | 0U, // ST_B_sro_v110 |
2863 | 0 | 0U, // ST_B_ssr |
2864 | 0 | 0U, // ST_B_ssr_pos |
2865 | 0 | 0U, // ST_B_ssr_pos_v110 |
2866 | 0 | 0U, // ST_B_ssr_v110 |
2867 | 0 | 0U, // ST_B_ssro |
2868 | 0 | 0U, // ST_B_ssro_v110 |
2869 | 0 | 0U, // ST_DA_abs |
2870 | 0 | 0U, // ST_DA_bo_bso |
2871 | 0 | 0U, // ST_DA_bo_c |
2872 | 0 | 0U, // ST_DA_bo_pos |
2873 | 0 | 0U, // ST_DA_bo_pre |
2874 | 0 | 0U, // ST_DA_bo_r |
2875 | 0 | 0U, // ST_D_abs |
2876 | 0 | 0U, // ST_D_bo_bso |
2877 | 0 | 0U, // ST_D_bo_c |
2878 | 0 | 0U, // ST_D_bo_pos |
2879 | 0 | 0U, // ST_D_bo_pre |
2880 | 0 | 0U, // ST_D_bo_r |
2881 | 0 | 0U, // ST_H_abs |
2882 | 0 | 0U, // ST_H_bo_bso |
2883 | 0 | 0U, // ST_H_bo_c |
2884 | 0 | 0U, // ST_H_bo_pos |
2885 | 0 | 0U, // ST_H_bo_pre |
2886 | 0 | 0U, // ST_H_bo_r |
2887 | 0 | 0U, // ST_H_bol |
2888 | 0 | 0U, // ST_H_sro |
2889 | 0 | 0U, // ST_H_sro_v110 |
2890 | 0 | 0U, // ST_H_ssr |
2891 | 0 | 0U, // ST_H_ssr_pos |
2892 | 0 | 0U, // ST_H_ssr_pos_v110 |
2893 | 0 | 0U, // ST_H_ssr_v110 |
2894 | 0 | 0U, // ST_H_ssro |
2895 | 0 | 0U, // ST_H_ssro_v110 |
2896 | 0 | 0U, // ST_Q_abs |
2897 | 0 | 0U, // ST_Q_bo_bso |
2898 | 0 | 0U, // ST_Q_bo_c |
2899 | 0 | 0U, // ST_Q_bo_pos |
2900 | 0 | 0U, // ST_Q_bo_pre |
2901 | 0 | 0U, // ST_Q_bo_r |
2902 | 0 | 0U, // ST_T |
2903 | 0 | 0U, // ST_W_abs |
2904 | 0 | 0U, // ST_W_bo_bso |
2905 | 0 | 0U, // ST_W_bo_c |
2906 | 0 | 0U, // ST_W_bo_pos |
2907 | 0 | 0U, // ST_W_bo_pre |
2908 | 0 | 0U, // ST_W_bo_r |
2909 | 0 | 0U, // ST_W_bol |
2910 | 0 | 0U, // ST_W_sc |
2911 | 0 | 0U, // ST_W_sro |
2912 | 0 | 0U, // ST_W_sro_v110 |
2913 | 0 | 0U, // ST_W_ssr |
2914 | 0 | 0U, // ST_W_ssr_pos |
2915 | 0 | 0U, // ST_W_ssr_pos_v110 |
2916 | 0 | 0U, // ST_W_ssr_v110 |
2917 | 0 | 0U, // ST_W_ssro |
2918 | 0 | 0U, // ST_W_ssro_v110 |
2919 | 0 | 0U, // SUBC_rr |
2920 | 0 | 2U, // SUBSC_A_rr |
2921 | 0 | 0U, // SUBS_BU_rr |
2922 | 0 | 0U, // SUBS_B_rr |
2923 | 0 | 0U, // SUBS_HU_rr |
2924 | 0 | 0U, // SUBS_H_rr |
2925 | 0 | 0U, // SUBS_U_rr |
2926 | 0 | 0U, // SUBS_rr |
2927 | 0 | 0U, // SUBS_srr |
2928 | 0 | 0U, // SUBX_rr |
2929 | 0 | 0U, // SUB_A_rr |
2930 | 0 | 0U, // SUB_A_sc |
2931 | 0 | 0U, // SUB_A_sc_v110 |
2932 | 0 | 0U, // SUB_B_rr |
2933 | 0 | 0U, // SUB_F_rrr |
2934 | 0 | 0U, // SUB_H_rr |
2935 | 0 | 0U, // SUB_rr |
2936 | 0 | 0U, // SUB_srr |
2937 | 0 | 0U, // SUB_srr_15a |
2938 | 0 | 0U, // SUB_srr_a15 |
2939 | 0 | 0U, // SVLCX_sys |
2940 | 0 | 0U, // SWAPMSK_W_bo_bso |
2941 | 0 | 0U, // SWAPMSK_W_bo_c |
2942 | 0 | 0U, // SWAPMSK_W_bo_i |
2943 | 0 | 0U, // SWAPMSK_W_bo_pos |
2944 | 0 | 0U, // SWAPMSK_W_bo_pre |
2945 | 0 | 0U, // SWAPMSK_W_bo_r |
2946 | 0 | 0U, // SWAP_A_abs |
2947 | 0 | 0U, // SWAP_A_bo_bso |
2948 | 0 | 0U, // SWAP_A_bo_c |
2949 | 0 | 0U, // SWAP_A_bo_pos |
2950 | 0 | 0U, // SWAP_A_bo_pre |
2951 | 0 | 0U, // SWAP_A_bo_r |
2952 | 0 | 0U, // SWAP_W_abs |
2953 | 0 | 0U, // SWAP_W_bo_bso |
2954 | 0 | 0U, // SWAP_W_bo_c |
2955 | 0 | 0U, // SWAP_W_bo_i |
2956 | 0 | 0U, // SWAP_W_bo_pos |
2957 | 0 | 0U, // SWAP_W_bo_pre |
2958 | 0 | 0U, // SWAP_W_bo_r |
2959 | 0 | 0U, // SYSCALL_rc |
2960 | 0 | 0U, // TLBDEMAP_rr |
2961 | 0 | 0U, // TLBFLUSH_A_rr |
2962 | 0 | 0U, // TLBFLUSH_B_rr |
2963 | 0 | 0U, // TLBMAP_rr |
2964 | 0 | 0U, // TLBPROBE_A_rr |
2965 | 0 | 0U, // TLBPROBE_I_rr |
2966 | 0 | 0U, // TRAPSV_sys |
2967 | 0 | 0U, // TRAPV_sys |
2968 | 0 | 0U, // UNPACK_rr_rr |
2969 | 0 | 0U, // UNPACK_rr_rr_v110 |
2970 | 0 | 0U, // UPDFL_rr |
2971 | 0 | 0U, // UTOF_rr |
2972 | 0 | 0U, // WAIT_sys |
2973 | 0 | 0U, // XNOR_T |
2974 | 0 | 0U, // XNOR_rc |
2975 | 0 | 0U, // XNOR_rr |
2976 | 0 | 0U, // XOR_EQ_rc |
2977 | 0 | 0U, // XOR_EQ_rr |
2978 | 0 | 0U, // XOR_GE_U_rc |
2979 | 0 | 0U, // XOR_GE_U_rr |
2980 | 0 | 0U, // XOR_GE_rc |
2981 | 0 | 0U, // XOR_GE_rr |
2982 | 0 | 0U, // XOR_LT_U_rc |
2983 | 0 | 0U, // XOR_LT_U_rr |
2984 | 0 | 0U, // XOR_LT_rc |
2985 | 0 | 0U, // XOR_LT_rr |
2986 | 0 | 0U, // XOR_NE_rc |
2987 | 0 | 0U, // XOR_NE_rr |
2988 | 0 | 0U, // XOR_T |
2989 | 0 | 0U, // XOR_rc |
2990 | 0 | 0U, // XOR_rr |
2991 | 0 | 0U, // XOR_srr |
2992 | 0 | }; |
2993 | | |
2994 | | // Emit the opcode for the instruction. |
2995 | 0 | uint64_t Bits = 0; |
2996 | 0 | Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; |
2997 | 0 | Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; |
2998 | 0 | MnemonicBitsInfo MBI = { |
2999 | 0 | #ifndef CAPSTONE_DIET |
3000 | 0 | AsmStrs+(Bits & 4095)-1, |
3001 | | #else |
3002 | | NULL, |
3003 | | #endif // CAPSTONE_DIET |
3004 | 0 | Bits |
3005 | 0 | }; |
3006 | 0 | return MBI; |
3007 | 0 | } |
3008 | | |
3009 | | /// printInstruction - This method is automatically generated by tablegen |
3010 | | /// from the instruction set description. |
3011 | 0 | void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { |
3012 | 0 | SStream_concat0(O, ""); |
3013 | 0 | MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); |
3014 | |
|
3015 | 0 | SStream_concat0(O, MnemonicInfo.first); |
3016 | |
|
3017 | 0 | uint64_t Bits = MnemonicInfo.second; |
3018 | 0 | assert(Bits != 0 && "Cannot print this instruction."); |
3019 | | |
3020 | | // Fragment 0 encoded into 4 bits for 13 unique commands. |
3021 | 0 | switch ((Bits >> 12) & 15) { |
3022 | 0 | default: assert(0 && "Invalid command number."); |
3023 | 0 | case 0: |
3024 | | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
3025 | 0 | return; |
3026 | 0 | break; |
3027 | 0 | case 1: |
3028 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3029 | 0 | printOperand(MI, 0, O); |
3030 | 0 | break; |
3031 | 0 | case 2: |
3032 | | // AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, LD_A_sc, LD_W_sc, MOV_sc, ... |
3033 | 0 | printZExtImm_8(MI, 0, O); |
3034 | 0 | break; |
3035 | 0 | case 3: |
3036 | | // BISR_rc, BISR_rc_v161, SYSCALL_rc |
3037 | 0 | printSExtImm_9(MI, 0, O); |
3038 | 0 | return; |
3039 | 0 | break; |
3040 | 0 | case 4: |
3041 | | // CALLA_b, CALL_b, FCALLA_b, FCALL_b, JA_b, JLA_b, JL_b, J_b |
3042 | 0 | printDisp24Imm(MI, 0, O); |
3043 | 0 | return; |
3044 | 0 | break; |
3045 | 0 | case 5: |
3046 | | // CALL_sb, JNZ_sb, JNZ_sb_v110, JZ_sb, JZ_sb_v110, J_sb, J_sb_v110 |
3047 | 0 | printDisp8Imm(MI, 0, O); |
3048 | 0 | return; |
3049 | 0 | break; |
3050 | 0 | case 6: |
3051 | | // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ... |
3052 | 0 | printOperand(MI, 1, O); |
3053 | 0 | break; |
3054 | 0 | case 7: |
3055 | | // JEQ_sbc1, JEQ_sbc2, JEQ_sbc_v110, JNE_sbc1, JNE_sbc2, JNE_sbc_v110 |
3056 | 0 | printSExtImm_4(MI, 1, O); |
3057 | 0 | SStream_concat0(O, ", "); |
3058 | 0 | printDisp4Imm(MI, 0, O); |
3059 | 0 | return; |
3060 | 0 | break; |
3061 | 0 | case 8: |
3062 | | // LDLCX_abs, LDUCX_abs, STLCX_abs, STUCX_abs, ST_T |
3063 | 0 | printOff18Imm(MI, 0, O); |
3064 | 0 | break; |
3065 | 0 | case 9: |
3066 | | // LDMST_abs, ST_A_abs, ST_B_abs, ST_DA_abs, ST_D_abs, ST_H_abs, ST_Q_abs... |
3067 | 0 | printOff18Imm(MI, 1, O); |
3068 | 0 | SStream_concat0(O, ", "); |
3069 | 0 | printOperand(MI, 0, O); |
3070 | 0 | return; |
3071 | 0 | break; |
3072 | 0 | case 10: |
3073 | | // LOOPU_brr |
3074 | 0 | printDisp15Imm(MI, 0, O); |
3075 | 0 | return; |
3076 | 0 | break; |
3077 | 0 | case 11: |
3078 | | // MTCR_rlc |
3079 | 0 | printSExtImm_16(MI, 0, O); |
3080 | 0 | SStream_concat0(O, ", "); |
3081 | 0 | printOperand(MI, 1, O); |
3082 | 0 | return; |
3083 | 0 | break; |
3084 | 0 | case 12: |
3085 | | // ST_A_ssro, ST_A_ssro_v110, ST_B_ssro, ST_B_ssro_v110, ST_H_ssro, ST_H_... |
3086 | 0 | printZExtImm_4(MI, 1, O); |
3087 | 0 | SStream_concat0(O, ", "); |
3088 | 0 | printOperand(MI, 0, O); |
3089 | 0 | return; |
3090 | 0 | break; |
3091 | 0 | } |
3092 | | |
3093 | | |
3094 | | // Fragment 1 encoded into 4 bits for 16 unique commands. |
3095 | 0 | switch ((Bits >> 16) & 15) { |
3096 | 0 | default: assert(0 && "Invalid command number."); |
3097 | 0 | case 0: |
3098 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3099 | 0 | SStream_concat0(O, ", "); |
3100 | 0 | break; |
3101 | 0 | case 1: |
3102 | | // ADD_src_a15, ADD_srr_a15, CADDN_src, CADDN_srr_v110, CADD_src, CADD_sr... |
3103 | 0 | SStream_concat0(O, ", d15, "); |
3104 | 0 | break; |
3105 | 0 | case 2: |
3106 | | // AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, CALLI_rr, CALLI_rr_v110, D... |
3107 | 0 | return; |
3108 | 0 | break; |
3109 | 0 | case 3: |
3110 | | // CACHEA_I_bo_bso, CACHEA_I_bo_pre, CACHEA_WI_bo_bso, CACHEA_WI_bo_pre, ... |
3111 | 0 | SStream_concat1(O, ']'); |
3112 | 0 | break; |
3113 | 0 | case 4: |
3114 | | // CACHEA_I_bo_c, CACHEA_WI_bo_c, CACHEA_W_bo_c, CMPSWAP_W_bo_c, LDMST_bo... |
3115 | 0 | SStream_concat0(O, "+c]"); |
3116 | 0 | set_mem_access(MI, false); |
3117 | 0 | break; |
3118 | 0 | case 5: |
3119 | | // CACHEA_I_bo_pos, CACHEA_WI_bo_pos, CACHEA_W_bo_pos, CACHEI_I_bo_pos, C... |
3120 | 0 | SStream_concat0(O, "+]"); |
3121 | 0 | set_mem_access(MI, false); |
3122 | 0 | break; |
3123 | 0 | case 6: |
3124 | | // CACHEA_I_bo_r, CACHEA_WI_bo_r, CACHEA_W_bo_r |
3125 | 0 | SStream_concat0(O, "+r]"); |
3126 | 0 | set_mem_access(MI, false); |
3127 | 0 | return; |
3128 | 0 | break; |
3129 | 0 | case 7: |
3130 | | // CMPSWAP_W_bo_r, LDMST_bo_r, ST_A_bo_r, ST_B_bo_r, ST_DA_bo_r, ST_D_bo_... |
3131 | 0 | SStream_concat0(O, "+r], "); |
3132 | 0 | set_mem_access(MI, false); |
3133 | 0 | break; |
3134 | 0 | case 8: |
3135 | | // LD_A_bo_bso, LD_A_bo_c, LD_A_bo_pos, LD_A_bo_r, LD_A_bol, LD_A_slr, LD... |
3136 | 0 | SStream_concat0(O, ", ["); |
3137 | 0 | set_mem_access(MI, true); |
3138 | 0 | printOperand(MI, 1, O); |
3139 | 0 | break; |
3140 | 0 | case 9: |
3141 | | // LD_A_bo_pre, LD_BU_bo_pre, LD_B_bo_pre, LD_DA_bo_pre, LD_D_bo_pre, LD_... |
3142 | 0 | SStream_concat0(O, ", [+"); |
3143 | 0 | set_mem_access(MI, true); |
3144 | 0 | printOperand(MI, 1, O); |
3145 | 0 | SStream_concat1(O, ']'); |
3146 | 0 | printSExtImm_10(MI, 2, O); |
3147 | 0 | return; |
3148 | 0 | break; |
3149 | 0 | case 10: |
3150 | | // LD_A_slro, LD_A_slro_v110, LD_BU_slro, LD_BU_slro_v110, LD_B_slro_v110... |
3151 | 0 | SStream_concat0(O, ", [a15]"); |
3152 | 0 | set_mem_access(MI, true); |
3153 | 0 | printZExtImm_4(MI, 1, O); |
3154 | 0 | return; |
3155 | 0 | break; |
3156 | 0 | case 11: |
3157 | | // ST_A_sc |
3158 | 0 | SStream_concat0(O, ", a15"); |
3159 | 0 | return; |
3160 | 0 | break; |
3161 | 0 | case 12: |
3162 | | // ST_A_ssr, ST_A_ssr_v110, ST_B_ssr, ST_B_ssr_v110, ST_H_ssr, ST_H_ssr_v... |
3163 | 0 | SStream_concat0(O, "], "); |
3164 | 0 | set_mem_access(MI, false); |
3165 | 0 | printOperand(MI, 1, O); |
3166 | 0 | return; |
3167 | 0 | break; |
3168 | 0 | case 13: |
3169 | | // ST_A_ssr_pos, ST_A_ssr_pos_v110, ST_B_ssr_pos, ST_B_ssr_pos_v110, ST_H... |
3170 | 0 | SStream_concat0(O, "+], "); |
3171 | 0 | set_mem_access(MI, false); |
3172 | 0 | printOperand(MI, 1, O); |
3173 | 0 | return; |
3174 | 0 | break; |
3175 | 0 | case 14: |
3176 | | // ST_W_sc |
3177 | 0 | SStream_concat0(O, ", d15"); |
3178 | 0 | return; |
3179 | 0 | break; |
3180 | 0 | case 15: |
3181 | | // SWAPMSK_W_bo_i, SWAP_W_bo_i |
3182 | 0 | SStream_concat0(O, "+i], "); |
3183 | 0 | set_mem_access(MI, false); |
3184 | 0 | printOperand(MI, 0, O); |
3185 | 0 | return; |
3186 | 0 | break; |
3187 | 0 | } |
3188 | | |
3189 | | |
3190 | | // Fragment 2 encoded into 5 bits for 19 unique commands. |
3191 | 0 | switch ((Bits >> 20) & 31) { |
3192 | 0 | default: assert(0 && "Invalid command number."); |
3193 | 0 | case 0: |
3194 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3195 | 0 | printOperand(MI, 1, O); |
3196 | 0 | break; |
3197 | 0 | case 1: |
3198 | | // ABSS_B_rr_v110, ABSS_H_rr, ABSS_rr, ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_r... |
3199 | 0 | printOperand(MI, 2, O); |
3200 | 0 | break; |
3201 | 0 | case 2: |
3202 | | // ADD_A_src, ADD_src, ADD_src_15a, ADD_src_a15, CADDN_src, CADD_src, CMO... |
3203 | 0 | printSExtImm_4(MI, 1, O); |
3204 | 0 | break; |
3205 | 0 | case 3: |
3206 | | // ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC... |
3207 | 0 | printOperand(MI, 3, O); |
3208 | 0 | SStream_concat0(O, ", "); |
3209 | 0 | break; |
3210 | 0 | case 4: |
3211 | | // CACHEA_I_bo_bso, CACHEA_I_bo_c, CACHEA_I_bo_pos, CACHEA_I_bo_pre, CACH... |
3212 | 0 | printSExtImm_10(MI, 1, O); |
3213 | 0 | return; |
3214 | 0 | break; |
3215 | 0 | case 5: |
3216 | | // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ... |
3217 | 0 | printSExtImm_10(MI, 2, O); |
3218 | 0 | SStream_concat0(O, ", "); |
3219 | 0 | break; |
3220 | 0 | case 6: |
3221 | | // CMPSWAP_W_bo_r, LDMST_bo_r |
3222 | 0 | printOperand(MI, 0, O); |
3223 | 0 | return; |
3224 | 0 | break; |
3225 | 0 | case 7: |
3226 | | // JEQ_sbr1, JEQ_sbr2, JEQ_sbr_v110, JGEZ_sbr, JGEZ_sbr_v110, JGTZ_sbr, J... |
3227 | 0 | printDisp4Imm(MI, 1, O); |
3228 | 0 | return; |
3229 | 0 | break; |
3230 | 0 | case 8: |
3231 | | // JGE_U_brc, JLT_U_brc, JLT_brc, JNED_brc, JNEI_brc, LD_A_sro, LD_A_sro_... |
3232 | 0 | printZExtImm_4(MI, 1, O); |
3233 | 0 | break; |
3234 | 0 | case 9: |
3235 | | // JNZ_A_brr, JZ_A_brr, LOOP_brr |
3236 | 0 | printDisp15Imm(MI, 1, O); |
3237 | 0 | return; |
3238 | 0 | break; |
3239 | 0 | case 10: |
3240 | | // LD_A_abs, LD_BU_abs, LD_B_abs, LD_DA_abs, LD_D_abs, LD_HU_abs, LD_H_ab... |
3241 | 0 | printOff18Imm(MI, 1, O); |
3242 | 0 | return; |
3243 | 0 | break; |
3244 | 0 | case 11: |
3245 | | // LD_A_bo_bso, LD_A_bol, LD_A_slr, LD_A_slr_v110, LD_BU_bo_bso, LD_BU_bo... |
3246 | 0 | SStream_concat1(O, ']'); |
3247 | 0 | break; |
3248 | 0 | case 12: |
3249 | | // LD_A_bo_c, LD_BU_bo_c, LD_B_bo_c, LD_DA_bo_c, LD_D_bo_c, LD_HU_bo_c, L... |
3250 | 0 | SStream_concat0(O, "+c]"); |
3251 | 0 | set_mem_access(MI, false); |
3252 | 0 | printSExtImm_10(MI, 2, O); |
3253 | 0 | return; |
3254 | 0 | break; |
3255 | 0 | case 13: |
3256 | | // LD_A_bo_pos, LD_A_slr_post, LD_A_slr_post_v110, LD_BU_bo_pos, LD_BU_sl... |
3257 | 0 | SStream_concat0(O, "+]"); |
3258 | 0 | set_mem_access(MI, false); |
3259 | 0 | break; |
3260 | 0 | case 14: |
3261 | | // LD_A_bo_r, LD_BU_bo_r, LD_B_bo_r, LD_DA_bo_r, LD_D_bo_r, LD_HU_bo_r, L... |
3262 | 0 | SStream_concat0(O, "+r]"); |
3263 | 0 | set_mem_access(MI, false); |
3264 | 0 | return; |
3265 | 0 | break; |
3266 | 0 | case 15: |
3267 | | // LOOP_sbr |
3268 | 0 | printOExtImm_4(MI, 1, O); |
3269 | 0 | return; |
3270 | 0 | break; |
3271 | 0 | case 16: |
3272 | | // MFCR_rlc, MOVH_A_rlc, MOVH_rlc, MOV_U_rlc, MOV_rlc_e |
3273 | 0 | printZExtImm_16(MI, 1, O); |
3274 | 0 | return; |
3275 | 0 | break; |
3276 | 0 | case 17: |
3277 | | // MOV_rlc |
3278 | 0 | printSExtImm_16(MI, 1, O); |
3279 | 0 | return; |
3280 | 0 | break; |
3281 | 0 | case 18: |
3282 | | // ST_A_bol, ST_B_bol, ST_H_bol, ST_W_bol |
3283 | 0 | printSExtImm_16(MI, 2, O); |
3284 | 0 | SStream_concat0(O, ", "); |
3285 | 0 | printOperand(MI, 1, O); |
3286 | 0 | return; |
3287 | 0 | break; |
3288 | 0 | } |
3289 | | |
3290 | | |
3291 | | // Fragment 3 encoded into 4 bits for 12 unique commands. |
3292 | 0 | switch ((Bits >> 25) & 15) { |
3293 | 0 | default: assert(0 && "Invalid command number."); |
3294 | 0 | case 0: |
3295 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3296 | 0 | SStream_concat0(O, ", "); |
3297 | 0 | break; |
3298 | 0 | case 1: |
3299 | | // ABSS_B_rr_v110, ABSS_H_rr, ABSS_rr, ABS_B_rr, ABS_H_rr, ABS_rr, ADDS_s... |
3300 | 0 | return; |
3301 | 0 | break; |
3302 | 0 | case 2: |
3303 | | // ADDSC_A_srrs |
3304 | 0 | SStream_concat0(O, ", d15, "); |
3305 | 0 | printZExtImm_2(MI, 2, O); |
3306 | 0 | return; |
3307 | 0 | break; |
3308 | 0 | case 3: |
3309 | | // ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC... |
3310 | 0 | printOperand(MI, 1, O); |
3311 | 0 | break; |
3312 | 0 | case 4: |
3313 | | // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ... |
3314 | 0 | printOperand(MI, 0, O); |
3315 | 0 | return; |
3316 | 0 | break; |
3317 | 0 | case 5: |
3318 | | // DVADJ_rrr, DVADJ_rrr_v110, DVSTEP_U_rrr, DVSTEP_U_rrrv110, DVSTEP_rrr,... |
3319 | 0 | printOperand(MI, 2, O); |
3320 | 0 | break; |
3321 | 0 | case 6: |
3322 | | // LD_A_bo_bso, LD_A_bo_pos, LD_BU_bo_bso, LD_BU_bo_pos, LD_B_bo_bso, LD_... |
3323 | 0 | printSExtImm_10(MI, 2, O); |
3324 | 0 | return; |
3325 | 0 | break; |
3326 | 0 | case 7: |
3327 | | // LD_A_bol, LD_BU_bol, LD_B_bol, LD_HU_bol, LD_H_bol, LD_W_bol, LEA_bol |
3328 | 0 | printSExtImm_16(MI, 2, O); |
3329 | 0 | return; |
3330 | 0 | break; |
3331 | 0 | case 8: |
3332 | | // MULR_Q_rr1_2LL, MUL_Q_rr1_2LL |
3333 | 0 | SStream_concat0(O, "l, "); |
3334 | 0 | printOperand(MI, 2, O); |
3335 | 0 | SStream_concat0(O, "l, "); |
3336 | 0 | printZExtImm_2(MI, 3, O); |
3337 | 0 | return; |
3338 | 0 | break; |
3339 | 0 | case 9: |
3340 | | // MULR_Q_rr1_2UU, MUL_Q_rr1_2UU |
3341 | 0 | SStream_concat0(O, "u, "); |
3342 | 0 | printOperand(MI, 2, O); |
3343 | 0 | SStream_concat0(O, "u, "); |
3344 | 0 | printZExtImm_2(MI, 3, O); |
3345 | 0 | return; |
3346 | 0 | break; |
3347 | 0 | case 10: |
3348 | | // ST_A_sro, ST_A_sro_v110 |
3349 | 0 | SStream_concat0(O, ", a15"); |
3350 | 0 | return; |
3351 | 0 | break; |
3352 | 0 | case 11: |
3353 | | // ST_B_sro, ST_B_sro_v110, ST_H_sro, ST_H_sro_v110, ST_W_sro, ST_W_sro_v... |
3354 | 0 | SStream_concat0(O, ", d15"); |
3355 | 0 | return; |
3356 | 0 | break; |
3357 | 0 | } |
3358 | | |
3359 | | |
3360 | | // Fragment 4 encoded into 4 bits for 14 unique commands. |
3361 | 0 | switch ((Bits >> 29) & 15) { |
3362 | 0 | default: assert(0 && "Invalid command number."); |
3363 | 0 | case 0: |
3364 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3365 | 0 | printOperand(MI, 2, O); |
3366 | 0 | break; |
3367 | 0 | case 1: |
3368 | | // ABSDIF_rc, ADDC_rc, ADDS_U_rc, ADDS_rc, ADDX_rc, ADD_rc, ANDN_rc, AND_... |
3369 | 0 | printSExtImm_9(MI, 2, O); |
3370 | 0 | return; |
3371 | 0 | break; |
3372 | 0 | case 2: |
3373 | | // ADDIH_A_rlc, ADDIH_rlc |
3374 | 0 | printZExtImm_16(MI, 2, O); |
3375 | 0 | return; |
3376 | 0 | break; |
3377 | 0 | case 3: |
3378 | | // ADDI_rlc |
3379 | 0 | printSExtImm_16(MI, 2, O); |
3380 | 0 | return; |
3381 | 0 | break; |
3382 | 0 | case 4: |
3383 | | // ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110,... |
3384 | 0 | printOperand(MI, 1, O); |
3385 | 0 | break; |
3386 | 0 | case 5: |
3387 | | // ADDSC_A_srrs_v110 |
3388 | 0 | printZExtImm_2(MI, 2, O); |
3389 | 0 | return; |
3390 | 0 | break; |
3391 | 0 | case 6: |
3392 | | // ADD_F_rrr, DVADJ_rrr, DVADJ_rrr_v110, DVSTEP_U_rrr, DVSTEP_U_rrrv110, ... |
3393 | 0 | return; |
3394 | 0 | break; |
3395 | 0 | case 7: |
3396 | | // ANDN_T, AND_ANDN_T, AND_AND_T, AND_NOR_T, AND_OR_T, AND_T, INSN_T, INS... |
3397 | 0 | printZExtImm_4(MI, 3, O); |
3398 | 0 | SStream_concat0(O, ", "); |
3399 | 0 | printOperand(MI, 2, O); |
3400 | 0 | SStream_concat0(O, ", "); |
3401 | 0 | printZExtImm_4(MI, 4, O); |
3402 | 0 | return; |
3403 | 0 | break; |
3404 | 0 | case 8: |
3405 | | // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB... |
3406 | 0 | SStream_concat0(O, ", "); |
3407 | 0 | break; |
3408 | 0 | case 9: |
3409 | | // EXTR_U_rrpw, EXTR_U_rrrw, EXTR_rrpw, EXTR_rrrw, IMASK_rcpw, IMASK_rrpw... |
3410 | 0 | printOperand(MI, 3, O); |
3411 | 0 | SStream_concat0(O, ", "); |
3412 | 0 | break; |
3413 | 0 | case 10: |
3414 | | // JEQ_A_brr, JEQ_brc, JEQ_brr, JGE_U_brc, JGE_U_brr, JGE_brc, JGE_brr, J... |
3415 | 0 | printDisp15Imm(MI, 2, O); |
3416 | 0 | return; |
3417 | 0 | break; |
3418 | 0 | case 11: |
3419 | | // MADDRS_Q_rrr1_L_L, MADDR_Q_rrr1_L_L, MADDS_Q_rrr1_L_L, MADDS_Q_rrr1_e_... |
3420 | 0 | SStream_concat0(O, "l, "); |
3421 | 0 | printOperand(MI, 2, O); |
3422 | 0 | SStream_concat0(O, "l, "); |
3423 | 0 | printZExtImm_2(MI, 4, O); |
3424 | 0 | return; |
3425 | 0 | break; |
3426 | 0 | case 12: |
3427 | | // MADDRS_Q_rrr1_U_U, MADDR_Q_rrr1_U_U, MADDS_Q_rrr1_U_U, MADDS_Q_rrr1_e_... |
3428 | 0 | SStream_concat0(O, "u, "); |
3429 | 0 | printOperand(MI, 2, O); |
3430 | 0 | SStream_concat0(O, "u, "); |
3431 | 0 | printZExtImm_2(MI, 4, O); |
3432 | 0 | return; |
3433 | 0 | break; |
3434 | 0 | case 13: |
3435 | | // OR_rc |
3436 | 0 | printZExtImm_9(MI, 2, O); |
3437 | 0 | return; |
3438 | 0 | break; |
3439 | 0 | } |
3440 | | |
3441 | | |
3442 | | // Fragment 5 encoded into 4 bits for 10 unique commands. |
3443 | 0 | switch ((Bits >> 33) & 15) { |
3444 | 0 | default: assert(0 && "Invalid command number."); |
3445 | 0 | case 0: |
3446 | | // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ... |
3447 | 0 | return; |
3448 | 0 | break; |
3449 | 0 | case 1: |
3450 | | // ADDSC_A_rr, ADDSC_A_rr_v110, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v... |
3451 | 0 | SStream_concat0(O, ", "); |
3452 | 0 | break; |
3453 | 0 | case 2: |
3454 | | // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB... |
3455 | 0 | printOperand(MI, 2, O); |
3456 | 0 | break; |
3457 | 0 | case 3: |
3458 | | // EXTR_U_rrpw, EXTR_U_rrrw, EXTR_rrpw, EXTR_rrrw, IMASK_rcpw, IMASK_rcrw... |
3459 | 0 | printOperand(MI, 4, O); |
3460 | 0 | return; |
3461 | 0 | break; |
3462 | 0 | case 4: |
3463 | | // MULMS_H_rr1_LL2e, MULM_H_rr1_LL2e, MULR_H_rr1_LL2e, MUL_H_rr1_LL2e |
3464 | 0 | SStream_concat0(O, "ll, "); |
3465 | 0 | printZExtImm_2(MI, 3, O); |
3466 | 0 | return; |
3467 | 0 | break; |
3468 | 0 | case 5: |
3469 | | // MULMS_H_rr1_LU2e, MULM_H_rr1_LU2e, MULR_H_rr1_LU2e, MUL_H_rr1_LU2e |
3470 | 0 | SStream_concat0(O, "lu, "); |
3471 | 0 | printZExtImm_2(MI, 3, O); |
3472 | 0 | return; |
3473 | 0 | break; |
3474 | 0 | case 6: |
3475 | | // MULMS_H_rr1_UL2e, MULM_H_rr1_UL2e, MULR_H_rr1_UL2e, MUL_H_rr1_UL2e |
3476 | 0 | SStream_concat0(O, "ul, "); |
3477 | 0 | printZExtImm_2(MI, 3, O); |
3478 | 0 | return; |
3479 | 0 | break; |
3480 | 0 | case 7: |
3481 | | // MULMS_H_rr1_UU2e, MULM_H_rr1_UU2e, MULR_H_rr1_UU2e, MUL_H_rr1_UU2e |
3482 | 0 | SStream_concat0(O, "uu, "); |
3483 | 0 | printZExtImm_2(MI, 3, O); |
3484 | 0 | return; |
3485 | 0 | break; |
3486 | 0 | case 8: |
3487 | | // MUL_Q_rr1_2_L, MUL_Q_rr1_2_Le |
3488 | 0 | SStream_concat0(O, "l, "); |
3489 | 0 | printZExtImm_2(MI, 3, O); |
3490 | 0 | return; |
3491 | 0 | break; |
3492 | 0 | case 9: |
3493 | | // MUL_Q_rr1_2_U, MUL_Q_rr1_2_Ue |
3494 | 0 | SStream_concat0(O, "u, "); |
3495 | 0 | printZExtImm_2(MI, 3, O); |
3496 | 0 | return; |
3497 | 0 | break; |
3498 | 0 | } |
3499 | | |
3500 | | |
3501 | | // Fragment 6 encoded into 4 bits for 12 unique commands. |
3502 | 0 | switch ((Bits >> 37) & 15) { |
3503 | 0 | default: assert(0 && "Invalid command number."); |
3504 | 0 | case 0: |
3505 | | // ADDSC_A_rr, ADDSC_A_rr_v110, DIFSC_A_rr_v110, MULR_H_rr_v110, MULR_Q_r... |
3506 | 0 | printZExtImm_2(MI, 3, O); |
3507 | 0 | return; |
3508 | 0 | break; |
3509 | 0 | case 1: |
3510 | | // CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110, CADD_rcr, MADDMS_rcr_v11... |
3511 | 0 | printSExtImm_9(MI, 3, O); |
3512 | 0 | return; |
3513 | 0 | break; |
3514 | 0 | case 2: |
3515 | | // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB... |
3516 | 0 | return; |
3517 | 0 | break; |
3518 | 0 | case 3: |
3519 | | // DEXTR_rrpw, DEXTR_rrrr, INSERT_rcpw, INSERT_rcrr, INSERT_rrpw, INSERT_... |
3520 | 0 | printOperand(MI, 3, O); |
3521 | 0 | break; |
3522 | 0 | case 4: |
3523 | | // INSERT_rcrw, MADDRS_H_rrr1_v110, MADDRS_Q_rrr1_v110, MADDR_H_rrr1_v110... |
3524 | 0 | SStream_concat0(O, ", "); |
3525 | 0 | break; |
3526 | 0 | case 5: |
3527 | | // MADDMS_H_rrr1_LL, MADDM_H_rrr1_LL, MADDRS_H_rrr1_LL, MADDR_H_rrr1_LL, ... |
3528 | 0 | SStream_concat0(O, "ll, "); |
3529 | 0 | printZExtImm_2(MI, 4, O); |
3530 | 0 | return; |
3531 | 0 | break; |
3532 | 0 | case 6: |
3533 | | // MADDMS_H_rrr1_LU, MADDM_H_rrr1_LU, MADDRS_H_rrr1_LU, MADDR_H_rrr1_LU, ... |
3534 | 0 | SStream_concat0(O, "lu, "); |
3535 | 0 | printZExtImm_2(MI, 4, O); |
3536 | 0 | return; |
3537 | 0 | break; |
3538 | 0 | case 7: |
3539 | | // MADDMS_H_rrr1_UL, MADDM_H_rrr1_UL, MADDRS_H_rrr1_UL, MADDRS_H_rrr1_UL_... |
3540 | 0 | SStream_concat0(O, "ul, "); |
3541 | 0 | printZExtImm_2(MI, 4, O); |
3542 | 0 | return; |
3543 | 0 | break; |
3544 | 0 | case 8: |
3545 | | // MADDMS_H_rrr1_UU, MADDM_H_rrr1_UU, MADDRS_H_rrr1_UU, MADDR_H_rrr1_UU, ... |
3546 | 0 | SStream_concat0(O, "uu, "); |
3547 | 0 | printZExtImm_2(MI, 4, O); |
3548 | 0 | return; |
3549 | 0 | break; |
3550 | 0 | case 9: |
3551 | | // MADDMS_U_rcr_v110, MADDM_U_rcr_v110, MADD_U_rcr, MSUB_U_rcr |
3552 | 0 | printZExtImm_9(MI, 3, O); |
3553 | 0 | return; |
3554 | 0 | break; |
3555 | 0 | case 10: |
3556 | | // MADDS_Q_rrr1_L, MADDS_Q_rrr1_e_L, MADD_Q_rrr1_L, MADD_Q_rrr1_e_L, MSUB... |
3557 | 0 | SStream_concat0(O, "l, "); |
3558 | 0 | printZExtImm_2(MI, 4, O); |
3559 | 0 | return; |
3560 | 0 | break; |
3561 | 0 | case 11: |
3562 | | // MADDS_Q_rrr1_U, MADDS_Q_rrr1_e_U, MADD_Q_rrr1_U, MADD_Q_rrr1_e_U, MSUB... |
3563 | 0 | SStream_concat0(O, "u, "); |
3564 | 0 | printZExtImm_2(MI, 4, O); |
3565 | 0 | return; |
3566 | 0 | break; |
3567 | 0 | } |
3568 | | |
3569 | | |
3570 | | // Fragment 7 encoded into 2 bits for 4 unique commands. |
3571 | 0 | switch ((Bits >> 41) & 3) { |
3572 | 0 | default: assert(0 && "Invalid command number."); |
3573 | 0 | case 0: |
3574 | | // DEXTR_rrpw, DEXTR_rrrr, INSERT_rcrr, INSERT_rrrr |
3575 | 0 | return; |
3576 | 0 | break; |
3577 | 0 | case 1: |
3578 | | // INSERT_rcpw, INSERT_rrpw, INSERT_rrrw |
3579 | 0 | SStream_concat0(O, ", "); |
3580 | 0 | printOperand(MI, 4, O); |
3581 | 0 | return; |
3582 | 0 | break; |
3583 | 0 | case 2: |
3584 | | // INSERT_rcrw |
3585 | 0 | printOperand(MI, 4, O); |
3586 | 0 | return; |
3587 | 0 | break; |
3588 | 0 | case 3: |
3589 | | // MADDRS_H_rrr1_v110, MADDRS_Q_rrr1_v110, MADDR_H_rrr1_v110, MADDR_Q_rrr... |
3590 | 0 | printZExtImm_2(MI, 4, O); |
3591 | 0 | return; |
3592 | 0 | break; |
3593 | 0 | } |
3594 | |
|
3595 | 0 | } |
3596 | | |
3597 | | |
3598 | | /// getRegisterName - This method is automatically generated by tblgen |
3599 | | /// from the register set description. This returns the assembler name |
3600 | | /// for the specified register. |
3601 | 0 | const char *getRegisterName(unsigned RegNo) { |
3602 | 0 | #ifndef CAPSTONE_DIET |
3603 | 0 | assert(RegNo && RegNo < 61 && "Invalid register number!"); |
3604 | | |
3605 | 0 | static const char AsmStrs[] = { |
3606 | 0 | /* 0 */ "d10\0" |
3607 | 0 | /* 4 */ "e10\0" |
3608 | 0 | /* 8 */ "p10\0" |
3609 | 0 | /* 12 */ "a0\0" |
3610 | 0 | /* 15 */ "d0\0" |
3611 | 0 | /* 18 */ "e0\0" |
3612 | 0 | /* 21 */ "p0\0" |
3613 | 0 | /* 24 */ "A10_A11\0" |
3614 | 0 | /* 32 */ "a11\0" |
3615 | 0 | /* 36 */ "d11\0" |
3616 | 0 | /* 40 */ "A0_A1\0" |
3617 | 0 | /* 46 */ "a1\0" |
3618 | 0 | /* 49 */ "d1\0" |
3619 | 0 | /* 52 */ "a12\0" |
3620 | 0 | /* 56 */ "d12\0" |
3621 | 0 | /* 60 */ "e12\0" |
3622 | 0 | /* 64 */ "p12\0" |
3623 | 0 | /* 68 */ "a2\0" |
3624 | 0 | /* 71 */ "d2\0" |
3625 | 0 | /* 74 */ "e2\0" |
3626 | 0 | /* 77 */ "p2\0" |
3627 | 0 | /* 80 */ "A12_A13\0" |
3628 | 0 | /* 88 */ "a13\0" |
3629 | 0 | /* 92 */ "d13\0" |
3630 | 0 | /* 96 */ "A2_A3\0" |
3631 | 0 | /* 102 */ "a3\0" |
3632 | 0 | /* 105 */ "d3\0" |
3633 | 0 | /* 108 */ "a14\0" |
3634 | 0 | /* 112 */ "d14\0" |
3635 | 0 | /* 116 */ "e14\0" |
3636 | 0 | /* 120 */ "p14\0" |
3637 | 0 | /* 124 */ "a4\0" |
3638 | 0 | /* 127 */ "d4\0" |
3639 | 0 | /* 130 */ "e4\0" |
3640 | 0 | /* 133 */ "p4\0" |
3641 | 0 | /* 136 */ "A14_A15\0" |
3642 | 0 | /* 144 */ "a15\0" |
3643 | 0 | /* 148 */ "d15\0" |
3644 | 0 | /* 152 */ "A4_A5\0" |
3645 | 0 | /* 158 */ "a5\0" |
3646 | 0 | /* 161 */ "d5\0" |
3647 | 0 | /* 164 */ "a6\0" |
3648 | 0 | /* 167 */ "d6\0" |
3649 | 0 | /* 170 */ "e6\0" |
3650 | 0 | /* 173 */ "p6\0" |
3651 | 0 | /* 176 */ "A6_A7\0" |
3652 | 0 | /* 182 */ "a7\0" |
3653 | 0 | /* 185 */ "d7\0" |
3654 | 0 | /* 188 */ "a8\0" |
3655 | 0 | /* 191 */ "d8\0" |
3656 | 0 | /* 194 */ "e8\0" |
3657 | 0 | /* 197 */ "p8\0" |
3658 | 0 | /* 200 */ "A8_A9\0" |
3659 | 0 | /* 206 */ "a9\0" |
3660 | 0 | /* 209 */ "d9\0" |
3661 | 0 | /* 212 */ "pc\0" |
3662 | 0 | /* 215 */ "pcxi\0" |
3663 | 0 | /* 220 */ "sp\0" |
3664 | 0 | /* 223 */ "psw\0" |
3665 | 0 | /* 227 */ "fcx\0" |
3666 | 0 | }; |
3667 | 0 | static const uint8_t RegAsmOffset[] = { |
3668 | 0 | 227, 212, 215, 223, 12, 46, 68, 102, 124, 158, 164, 182, 188, 206, |
3669 | 0 | 220, 32, 52, 88, 108, 144, 15, 49, 71, 105, 127, 161, 167, 185, |
3670 | 0 | 191, 209, 0, 36, 56, 92, 112, 148, 18, 74, 130, 170, 194, 4, |
3671 | 0 | 60, 116, 21, 77, 133, 173, 197, 8, 64, 120, 40, 96, 152, 176, |
3672 | 0 | 200, 24, 80, 136, |
3673 | 0 | }; |
3674 | |
|
3675 | 0 | assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
3676 | 0 | "Invalid alt name index for register!"); |
3677 | 0 | return AsmStrs+RegAsmOffset[RegNo-1]; |
3678 | | #else |
3679 | | return NULL; |
3680 | | #endif // CAPSTONE_DIET |
3681 | 0 | } |
3682 | | #ifdef PRINT_ALIAS_INSTR |
3683 | | #undef PRINT_ALIAS_INSTR |
3684 | | |
3685 | | static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { |
3686 | | #ifndef CAPSTONE_DIET |
3687 | | return false; |
3688 | | #endif // CAPSTONE_DIET |
3689 | | } |
3690 | | |
3691 | | #endif // PRINT_ALIAS_INSTR |