/src/capstonev5/arch/X86/X86ATTInstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file includes code for rendering MCInst instances as AT&T-style |
11 | | // assembly. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | /* Capstone Disassembly Engine */ |
16 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
17 | | |
18 | | // this code is only relevant when DIET mode is disable |
19 | | #if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) |
20 | | |
21 | | #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) |
22 | | #pragma warning(disable:4996) // disable MSVC's warning on strncpy() |
23 | | #pragma warning(disable:28719) // disable MSVC's warning on strncpy() |
24 | | #endif |
25 | | |
26 | | #if !defined(CAPSTONE_HAS_OSXKERNEL) |
27 | | #include <ctype.h> |
28 | | #endif |
29 | | #include <capstone/platform.h> |
30 | | |
31 | | #if defined(CAPSTONE_HAS_OSXKERNEL) |
32 | | #include <Availability.h> |
33 | | #include <libkern/libkern.h> |
34 | | #else |
35 | | #include <stdio.h> |
36 | | #include <stdlib.h> |
37 | | #endif |
38 | | |
39 | | #include <string.h> |
40 | | |
41 | | #include "../../utils.h" |
42 | | #include "../../MCInst.h" |
43 | | #include "../../SStream.h" |
44 | | #include "../../MCRegisterInfo.h" |
45 | | #include "X86Mapping.h" |
46 | | #include "X86BaseInfo.h" |
47 | | #include "X86InstPrinterCommon.h" |
48 | | |
49 | | #define GET_INSTRINFO_ENUM |
50 | | #ifdef CAPSTONE_X86_REDUCE |
51 | | #include "X86GenInstrInfo_reduce.inc" |
52 | | #else |
53 | | #include "X86GenInstrInfo.inc" |
54 | | #endif |
55 | | |
56 | | #define GET_REGINFO_ENUM |
57 | | #include "X86GenRegisterInfo.inc" |
58 | | |
59 | | static void printMemReference(MCInst *MI, unsigned Op, SStream *O); |
60 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
61 | | |
62 | | |
63 | | static void set_mem_access(MCInst *MI, bool status) |
64 | 241k | { |
65 | 241k | if (MI->csh->detail != CS_OPT_ON) |
66 | 0 | return; |
67 | | |
68 | 241k | MI->csh->doing_mem = status; |
69 | 241k | if (!status) |
70 | | // done, create the next operand slot |
71 | 120k | MI->flat_insn->detail->x86.op_count++; |
72 | 241k | } |
73 | | |
74 | | static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) |
75 | 17.2k | { |
76 | 17.2k | switch(MI->csh->mode) { |
77 | 6.52k | case CS_MODE_16: |
78 | 6.52k | switch(MI->flat_insn->id) { |
79 | 2.27k | default: |
80 | 2.27k | MI->x86opsize = 2; |
81 | 2.27k | break; |
82 | 1.67k | case X86_INS_LJMP: |
83 | 2.11k | case X86_INS_LCALL: |
84 | 2.11k | MI->x86opsize = 4; |
85 | 2.11k | break; |
86 | 545 | case X86_INS_SGDT: |
87 | 987 | case X86_INS_SIDT: |
88 | 1.57k | case X86_INS_LGDT: |
89 | 2.12k | case X86_INS_LIDT: |
90 | 2.12k | MI->x86opsize = 6; |
91 | 2.12k | break; |
92 | 6.52k | } |
93 | 6.52k | break; |
94 | 6.52k | case CS_MODE_32: |
95 | 5.88k | switch(MI->flat_insn->id) { |
96 | 1.97k | default: |
97 | 1.97k | MI->x86opsize = 4; |
98 | 1.97k | break; |
99 | 163 | case X86_INS_LJMP: |
100 | 1.12k | case X86_INS_JMP: |
101 | 1.63k | case X86_INS_LCALL: |
102 | 2.22k | case X86_INS_SGDT: |
103 | 2.75k | case X86_INS_SIDT: |
104 | 3.12k | case X86_INS_LGDT: |
105 | 3.91k | case X86_INS_LIDT: |
106 | 3.91k | MI->x86opsize = 6; |
107 | 3.91k | break; |
108 | 5.88k | } |
109 | 5.88k | break; |
110 | 5.88k | case CS_MODE_64: |
111 | 4.79k | switch(MI->flat_insn->id) { |
112 | 1.01k | default: |
113 | 1.01k | MI->x86opsize = 8; |
114 | 1.01k | break; |
115 | 1.30k | case X86_INS_LJMP: |
116 | 1.99k | case X86_INS_LCALL: |
117 | 2.36k | case X86_INS_SGDT: |
118 | 2.85k | case X86_INS_SIDT: |
119 | 3.16k | case X86_INS_LGDT: |
120 | 3.77k | case X86_INS_LIDT: |
121 | 3.77k | MI->x86opsize = 10; |
122 | 3.77k | break; |
123 | 4.79k | } |
124 | 4.79k | break; |
125 | 4.79k | default: // never reach |
126 | 0 | break; |
127 | 17.2k | } |
128 | | |
129 | 17.2k | printMemReference(MI, OpNo, O); |
130 | 17.2k | } |
131 | | |
132 | | static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) |
133 | 213k | { |
134 | 213k | MI->x86opsize = 1; |
135 | 213k | printMemReference(MI, OpNo, O); |
136 | 213k | } |
137 | | |
138 | | static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) |
139 | 68.1k | { |
140 | 68.1k | MI->x86opsize = 2; |
141 | | |
142 | 68.1k | printMemReference(MI, OpNo, O); |
143 | 68.1k | } |
144 | | |
145 | | static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) |
146 | 66.1k | { |
147 | 66.1k | MI->x86opsize = 4; |
148 | | |
149 | 66.1k | printMemReference(MI, OpNo, O); |
150 | 66.1k | } |
151 | | |
152 | | static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) |
153 | 23.3k | { |
154 | 23.3k | MI->x86opsize = 8; |
155 | 23.3k | printMemReference(MI, OpNo, O); |
156 | 23.3k | } |
157 | | |
158 | | static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) |
159 | 7.21k | { |
160 | 7.21k | MI->x86opsize = 16; |
161 | 7.21k | printMemReference(MI, OpNo, O); |
162 | 7.21k | } |
163 | | |
164 | | static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) |
165 | 4.56k | { |
166 | 4.56k | MI->x86opsize = 64; |
167 | 4.56k | printMemReference(MI, OpNo, O); |
168 | 4.56k | } |
169 | | |
170 | | #ifndef CAPSTONE_X86_REDUCE |
171 | | static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) |
172 | 4.30k | { |
173 | 4.30k | MI->x86opsize = 32; |
174 | 4.30k | printMemReference(MI, OpNo, O); |
175 | 4.30k | } |
176 | | |
177 | | static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) |
178 | 7.60k | { |
179 | 7.60k | switch(MCInst_getOpcode(MI)) { |
180 | 5.22k | default: |
181 | 5.22k | MI->x86opsize = 4; |
182 | 5.22k | break; |
183 | 1.41k | case X86_FSTENVm: |
184 | 2.37k | case X86_FLDENVm: |
185 | | // TODO: fix this in tablegen instead |
186 | 2.37k | switch(MI->csh->mode) { |
187 | 0 | default: // never reach |
188 | 0 | break; |
189 | 1.32k | case CS_MODE_16: |
190 | 1.32k | MI->x86opsize = 14; |
191 | 1.32k | break; |
192 | 355 | case CS_MODE_32: |
193 | 1.05k | case CS_MODE_64: |
194 | 1.05k | MI->x86opsize = 28; |
195 | 1.05k | break; |
196 | 2.37k | } |
197 | 2.37k | break; |
198 | 7.60k | } |
199 | | |
200 | 7.60k | printMemReference(MI, OpNo, O); |
201 | 7.60k | } |
202 | | |
203 | | static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) |
204 | 9.46k | { |
205 | 9.46k | MI->x86opsize = 8; |
206 | 9.46k | printMemReference(MI, OpNo, O); |
207 | 9.46k | } |
208 | | |
209 | | static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) |
210 | 934 | { |
211 | 934 | MI->x86opsize = 10; |
212 | 934 | printMemReference(MI, OpNo, O); |
213 | 934 | } |
214 | | |
215 | | static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) |
216 | 5.92k | { |
217 | 5.92k | MI->x86opsize = 16; |
218 | 5.92k | printMemReference(MI, OpNo, O); |
219 | 5.92k | } |
220 | | |
221 | | static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) |
222 | 3.90k | { |
223 | 3.90k | MI->x86opsize = 32; |
224 | 3.90k | printMemReference(MI, OpNo, O); |
225 | 3.90k | } |
226 | | |
227 | | static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) |
228 | 4.45k | { |
229 | 4.45k | MI->x86opsize = 64; |
230 | 4.45k | printMemReference(MI, OpNo, O); |
231 | 4.45k | } |
232 | | |
233 | | #endif |
234 | | |
235 | | static void printRegName(SStream *OS, unsigned RegNo); |
236 | | |
237 | | // local printOperand, without updating public operands |
238 | | static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
239 | 619k | { |
240 | 619k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
241 | 619k | if (MCOperand_isReg(Op)) { |
242 | 619k | printRegName(O, MCOperand_getReg(Op)); |
243 | 619k | } else if (MCOperand_isImm(Op)) { |
244 | 0 | uint8_t encsize; |
245 | 0 | uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); |
246 | | |
247 | | // Print X86 immediates as signed values. |
248 | 0 | int64_t imm = MCOperand_getImm(Op); |
249 | 0 | if (imm < 0) { |
250 | 0 | if (MI->csh->imm_unsigned) { |
251 | 0 | if (opsize) { |
252 | 0 | switch(opsize) { |
253 | 0 | default: |
254 | 0 | break; |
255 | 0 | case 1: |
256 | 0 | imm &= 0xff; |
257 | 0 | break; |
258 | 0 | case 2: |
259 | 0 | imm &= 0xffff; |
260 | 0 | break; |
261 | 0 | case 4: |
262 | 0 | imm &= 0xffffffff; |
263 | 0 | break; |
264 | 0 | } |
265 | 0 | } |
266 | | |
267 | 0 | SStream_concat(O, "$0x%"PRIx64, imm); |
268 | 0 | } else { |
269 | 0 | if (imm < -HEX_THRESHOLD) |
270 | 0 | SStream_concat(O, "$-0x%"PRIx64, -imm); |
271 | 0 | else |
272 | 0 | SStream_concat(O, "$-%"PRIu64, -imm); |
273 | 0 | } |
274 | 0 | } else { |
275 | 0 | if (imm > HEX_THRESHOLD) |
276 | 0 | SStream_concat(O, "$0x%"PRIx64, imm); |
277 | 0 | else |
278 | 0 | SStream_concat(O, "$%"PRIu64, imm); |
279 | 0 | } |
280 | 0 | } |
281 | 619k | } |
282 | | |
283 | | // convert Intel access info to AT&T access info |
284 | | static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) |
285 | 2.45M | { |
286 | 2.45M | uint8_t count, i; |
287 | 2.45M | const uint8_t *arr = X86_get_op_access(h, id, eflags); |
288 | | |
289 | 2.45M | if (!arr) { |
290 | 0 | access[0] = 0; |
291 | 0 | return; |
292 | 0 | } |
293 | | |
294 | | // find the non-zero last entry |
295 | 6.94M | for(count = 0; arr[count]; count++); |
296 | | |
297 | 2.45M | if (count == 0) |
298 | 147k | return; |
299 | | |
300 | | // copy in reverse order this access array from Intel syntax -> AT&T syntax |
301 | 2.30M | count--; |
302 | 6.79M | for(i = 0; i <= count; i++) { |
303 | 4.48M | if (arr[count - i] != CS_AC_IGNORE) |
304 | 3.90M | access[i] = arr[count - i]; |
305 | 582k | else |
306 | 582k | access[i] = 0; |
307 | 4.48M | } |
308 | 2.30M | } |
309 | | |
310 | | static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) |
311 | 58.5k | { |
312 | 58.5k | MCOperand *SegReg; |
313 | 58.5k | int reg; |
314 | | |
315 | 58.5k | if (MI->csh->detail) { |
316 | 58.5k | uint8_t access[6]; |
317 | | |
318 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
319 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
320 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
321 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
322 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
323 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
324 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
325 | | |
326 | 58.5k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
327 | 58.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
328 | 58.5k | } |
329 | | |
330 | 58.5k | SegReg = MCInst_getOperand(MI, Op+1); |
331 | 58.5k | reg = MCOperand_getReg(SegReg); |
332 | | // If this has a segment register, print it. |
333 | 58.5k | if (reg) { |
334 | 1.79k | _printOperand(MI, Op + 1, O); |
335 | 1.79k | SStream_concat0(O, ":"); |
336 | | |
337 | 1.79k | if (MI->csh->detail) { |
338 | 1.79k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); |
339 | 1.79k | } |
340 | 1.79k | } |
341 | | |
342 | 58.5k | SStream_concat0(O, "("); |
343 | 58.5k | set_mem_access(MI, true); |
344 | | |
345 | 58.5k | printOperand(MI, Op, O); |
346 | | |
347 | 58.5k | SStream_concat0(O, ")"); |
348 | 58.5k | set_mem_access(MI, false); |
349 | 58.5k | } |
350 | | |
351 | | static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) |
352 | 62.3k | { |
353 | 62.3k | if (MI->csh->detail) { |
354 | 62.3k | uint8_t access[6]; |
355 | | |
356 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
357 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
358 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
359 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
360 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
361 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
362 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
363 | | |
364 | 62.3k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
365 | 62.3k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
366 | 62.3k | } |
367 | | |
368 | | // DI accesses are always ES-based on non-64bit mode |
369 | 62.3k | if (MI->csh->mode != CS_MODE_64) { |
370 | 39.5k | SStream_concat0(O, "%es:("); |
371 | 39.5k | if (MI->csh->detail) { |
372 | 39.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; |
373 | 39.5k | } |
374 | 39.5k | } else |
375 | 22.7k | SStream_concat0(O, "("); |
376 | | |
377 | 62.3k | set_mem_access(MI, true); |
378 | | |
379 | 62.3k | printOperand(MI, Op, O); |
380 | | |
381 | 62.3k | SStream_concat0(O, ")"); |
382 | 62.3k | set_mem_access(MI, false); |
383 | 62.3k | } |
384 | | |
385 | | static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
386 | 20.3k | { |
387 | 20.3k | MI->x86opsize = 1; |
388 | 20.3k | printSrcIdx(MI, OpNo, O); |
389 | 20.3k | } |
390 | | |
391 | | static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
392 | 18.7k | { |
393 | 18.7k | MI->x86opsize = 2; |
394 | 18.7k | printSrcIdx(MI, OpNo, O); |
395 | 18.7k | } |
396 | | |
397 | | static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
398 | 15.3k | { |
399 | 15.3k | MI->x86opsize = 4; |
400 | 15.3k | printSrcIdx(MI, OpNo, O); |
401 | 15.3k | } |
402 | | |
403 | | static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
404 | 3.98k | { |
405 | 3.98k | MI->x86opsize = 8; |
406 | 3.98k | printSrcIdx(MI, OpNo, O); |
407 | 3.98k | } |
408 | | |
409 | | static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
410 | 26.2k | { |
411 | 26.2k | MI->x86opsize = 1; |
412 | 26.2k | printDstIdx(MI, OpNo, O); |
413 | 26.2k | } |
414 | | |
415 | | static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
416 | 18.2k | { |
417 | 18.2k | MI->x86opsize = 2; |
418 | 18.2k | printDstIdx(MI, OpNo, O); |
419 | 18.2k | } |
420 | | |
421 | | static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
422 | 13.7k | { |
423 | 13.7k | MI->x86opsize = 4; |
424 | 13.7k | printDstIdx(MI, OpNo, O); |
425 | 13.7k | } |
426 | | |
427 | | static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
428 | 4.00k | { |
429 | 4.00k | MI->x86opsize = 8; |
430 | 4.00k | printDstIdx(MI, OpNo, O); |
431 | 4.00k | } |
432 | | |
433 | | static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) |
434 | 11.1k | { |
435 | 11.1k | MCOperand *DispSpec = MCInst_getOperand(MI, Op); |
436 | 11.1k | MCOperand *SegReg = MCInst_getOperand(MI, Op+1); |
437 | 11.1k | int reg; |
438 | | |
439 | 11.1k | if (MI->csh->detail) { |
440 | 11.1k | uint8_t access[6]; |
441 | | |
442 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
443 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
444 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
445 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
446 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
447 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
448 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
449 | | |
450 | 11.1k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
451 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
452 | 11.1k | } |
453 | | |
454 | | // If this has a segment register, print it. |
455 | 11.1k | reg = MCOperand_getReg(SegReg); |
456 | 11.1k | if (reg) { |
457 | 771 | _printOperand(MI, Op + 1, O); |
458 | 771 | SStream_concat0(O, ":"); |
459 | | |
460 | 771 | if (MI->csh->detail) { |
461 | 771 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); |
462 | 771 | } |
463 | 771 | } |
464 | | |
465 | 11.1k | if (MCOperand_isImm(DispSpec)) { |
466 | 11.1k | int64_t imm = MCOperand_getImm(DispSpec); |
467 | 11.1k | if (MI->csh->detail) |
468 | 11.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
469 | 11.1k | if (imm < 0) { |
470 | 2.01k | SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); |
471 | 9.10k | } else { |
472 | 9.10k | if (imm > HEX_THRESHOLD) |
473 | 8.64k | SStream_concat(O, "0x%"PRIx64, imm); |
474 | 459 | else |
475 | 459 | SStream_concat(O, "%"PRIu64, imm); |
476 | 9.10k | } |
477 | 11.1k | } |
478 | | |
479 | 11.1k | if (MI->csh->detail) |
480 | 11.1k | MI->flat_insn->detail->x86.op_count++; |
481 | 11.1k | } |
482 | | |
483 | | static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) |
484 | 48.5k | { |
485 | 48.5k | uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; |
486 | | |
487 | 48.5k | if (val > HEX_THRESHOLD) |
488 | 42.1k | SStream_concat(O, "$0x%x", val); |
489 | 6.41k | else |
490 | 6.41k | SStream_concat(O, "$%u", val); |
491 | | |
492 | 48.5k | if (MI->csh->detail) { |
493 | 48.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
494 | 48.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; |
495 | 48.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; |
496 | 48.5k | MI->flat_insn->detail->x86.op_count++; |
497 | 48.5k | } |
498 | 48.5k | } |
499 | | |
500 | | static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) |
501 | 6.49k | { |
502 | 6.49k | MI->x86opsize = 1; |
503 | 6.49k | printMemOffset(MI, OpNo, O); |
504 | 6.49k | } |
505 | | |
506 | | static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) |
507 | 2.08k | { |
508 | 2.08k | MI->x86opsize = 2; |
509 | 2.08k | printMemOffset(MI, OpNo, O); |
510 | 2.08k | } |
511 | | |
512 | | static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) |
513 | 2.18k | { |
514 | 2.18k | MI->x86opsize = 4; |
515 | 2.18k | printMemOffset(MI, OpNo, O); |
516 | 2.18k | } |
517 | | |
518 | | static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) |
519 | 351 | { |
520 | 351 | MI->x86opsize = 8; |
521 | 351 | printMemOffset(MI, OpNo, O); |
522 | 351 | } |
523 | | |
524 | | /// printPCRelImm - This is used to print an immediate value that ends up |
525 | | /// being encoded as a pc-relative value (e.g. for jumps and calls). These |
526 | | /// print slightly differently than normal immediates. For example, a $ is not |
527 | | /// emitted. |
528 | | static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) |
529 | 77.9k | { |
530 | 77.9k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
531 | 77.9k | if (MCOperand_isImm(Op)) { |
532 | 77.9k | int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; |
533 | | |
534 | | // truncat imm for non-64bit |
535 | 77.9k | if (MI->csh->mode != CS_MODE_64) { |
536 | 52.3k | imm = imm & 0xffffffff; |
537 | 52.3k | } |
538 | | |
539 | 77.9k | if (imm < 0) { |
540 | 1.85k | SStream_concat(O, "0x%"PRIx64, imm); |
541 | 76.1k | } else { |
542 | 76.1k | if (imm > HEX_THRESHOLD) |
543 | 76.1k | SStream_concat(O, "0x%"PRIx64, imm); |
544 | 24 | else |
545 | 24 | SStream_concat(O, "%"PRIu64, imm); |
546 | 76.1k | } |
547 | 77.9k | if (MI->csh->detail) { |
548 | 77.9k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
549 | 77.9k | MI->has_imm = true; |
550 | 77.9k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
551 | 77.9k | MI->flat_insn->detail->x86.op_count++; |
552 | 77.9k | } |
553 | 77.9k | } |
554 | 77.9k | } |
555 | | |
556 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
557 | 1.02M | { |
558 | 1.02M | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
559 | 1.02M | if (MCOperand_isReg(Op)) { |
560 | 892k | unsigned int reg = MCOperand_getReg(Op); |
561 | 892k | printRegName(O, reg); |
562 | 892k | if (MI->csh->detail) { |
563 | 892k | if (MI->csh->doing_mem) { |
564 | 120k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); |
565 | 771k | } else { |
566 | 771k | uint8_t access[6]; |
567 | | |
568 | 771k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; |
569 | 771k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); |
570 | 771k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; |
571 | | |
572 | 771k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
573 | 771k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
574 | | |
575 | 771k | MI->flat_insn->detail->x86.op_count++; |
576 | 771k | } |
577 | 892k | } |
578 | 892k | } else if (MCOperand_isImm(Op)) { |
579 | | // Print X86 immediates as signed values. |
580 | 132k | uint8_t encsize; |
581 | 132k | int64_t imm = MCOperand_getImm(Op); |
582 | 132k | uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); |
583 | | |
584 | 132k | if (opsize == 1) // print 1 byte immediate in positive form |
585 | 57.6k | imm = imm & 0xff; |
586 | | |
587 | 132k | switch(MI->flat_insn->id) { |
588 | 58.1k | default: |
589 | 58.1k | if (imm >= 0) { |
590 | 52.0k | if (imm > HEX_THRESHOLD) |
591 | 44.8k | SStream_concat(O, "$0x%"PRIx64, imm); |
592 | 7.27k | else |
593 | 7.27k | SStream_concat(O, "$%"PRIu64, imm); |
594 | 52.0k | } else { |
595 | 6.10k | if (MI->csh->imm_unsigned) { |
596 | 0 | if (opsize) { |
597 | 0 | switch(opsize) { |
598 | 0 | default: |
599 | 0 | break; |
600 | 0 | case 1: |
601 | 0 | imm &= 0xff; |
602 | 0 | break; |
603 | 0 | case 2: |
604 | 0 | imm &= 0xffff; |
605 | 0 | break; |
606 | 0 | case 4: |
607 | 0 | imm &= 0xffffffff; |
608 | 0 | break; |
609 | 0 | } |
610 | 0 | } |
611 | | |
612 | 0 | SStream_concat(O, "$0x%"PRIx64, imm); |
613 | 6.10k | } else { |
614 | 6.10k | if (imm == 0x8000000000000000LL) // imm == -imm |
615 | 0 | SStream_concat0(O, "$0x8000000000000000"); |
616 | 6.10k | else if (imm < -HEX_THRESHOLD) |
617 | 5.29k | SStream_concat(O, "$-0x%"PRIx64, -imm); |
618 | 804 | else |
619 | 804 | SStream_concat(O, "$-%"PRIu64, -imm); |
620 | 6.10k | } |
621 | 6.10k | } |
622 | 58.1k | break; |
623 | | |
624 | 58.1k | case X86_INS_MOVABS: |
625 | 21.6k | case X86_INS_MOV: |
626 | | // do not print number in negative form |
627 | 21.6k | if (imm > HEX_THRESHOLD) |
628 | 19.8k | SStream_concat(O, "$0x%"PRIx64, imm); |
629 | 1.79k | else |
630 | 1.79k | SStream_concat(O, "$%"PRIu64, imm); |
631 | 21.6k | break; |
632 | | |
633 | 0 | case X86_INS_IN: |
634 | 0 | case X86_INS_OUT: |
635 | 0 | case X86_INS_INT: |
636 | | // do not print number in negative form |
637 | 0 | imm = imm & 0xff; |
638 | 0 | if (imm >= 0 && imm <= HEX_THRESHOLD) |
639 | 0 | SStream_concat(O, "$%u", imm); |
640 | 0 | else { |
641 | 0 | SStream_concat(O, "$0x%x", imm); |
642 | 0 | } |
643 | 0 | break; |
644 | | |
645 | 2.23k | case X86_INS_LCALL: |
646 | 5.24k | case X86_INS_LJMP: |
647 | 5.24k | case X86_INS_JMP: |
648 | | // always print address in positive form |
649 | 5.24k | if (OpNo == 1) { // selector is ptr16 |
650 | 2.62k | imm = imm & 0xffff; |
651 | 2.62k | opsize = 2; |
652 | 2.62k | } else |
653 | 2.62k | opsize = 4; |
654 | 5.24k | SStream_concat(O, "$0x%"PRIx64, imm); |
655 | 5.24k | break; |
656 | | |
657 | 12.2k | case X86_INS_AND: |
658 | 25.2k | case X86_INS_OR: |
659 | 34.2k | case X86_INS_XOR: |
660 | | // do not print number in negative form |
661 | 34.2k | if (imm >= 0 && imm <= HEX_THRESHOLD) |
662 | 3.54k | SStream_concat(O, "$%u", imm); |
663 | 30.6k | else { |
664 | 30.6k | imm = arch_masks[opsize? opsize : MI->imm_size] & imm; |
665 | 30.6k | SStream_concat(O, "$0x%"PRIx64, imm); |
666 | 30.6k | } |
667 | 34.2k | break; |
668 | | |
669 | 11.1k | case X86_INS_RET: |
670 | 13.1k | case X86_INS_RETF: |
671 | | // RET imm16 |
672 | 13.1k | if (imm >= 0 && imm <= HEX_THRESHOLD) |
673 | 845 | SStream_concat(O, "$%u", imm); |
674 | 12.2k | else { |
675 | 12.2k | imm = 0xffff & imm; |
676 | 12.2k | SStream_concat(O, "$0x%x", imm); |
677 | 12.2k | } |
678 | 13.1k | break; |
679 | 132k | } |
680 | | |
681 | 132k | if (MI->csh->detail) { |
682 | 132k | if (MI->csh->doing_mem) { |
683 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
684 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
685 | 132k | } else { |
686 | 132k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
687 | 132k | MI->has_imm = true; |
688 | 132k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
689 | | |
690 | 132k | if (opsize > 0) { |
691 | 111k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; |
692 | 111k | MI->flat_insn->detail->x86.encoding.imm_size = encsize; |
693 | 111k | } else if (MI->op1_size > 0) |
694 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size; |
695 | 21.0k | else |
696 | 21.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
697 | | |
698 | 132k | MI->flat_insn->detail->x86.op_count++; |
699 | 132k | } |
700 | 132k | } |
701 | 132k | } |
702 | 1.02M | } |
703 | | |
704 | | static void printMemReference(MCInst *MI, unsigned Op, SStream *O) |
705 | 443k | { |
706 | 443k | MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); |
707 | 443k | MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); |
708 | 443k | MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); |
709 | 443k | MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); |
710 | 443k | uint64_t ScaleVal; |
711 | 443k | int segreg; |
712 | 443k | int64_t DispVal = 1; |
713 | | |
714 | 443k | if (MI->csh->detail) { |
715 | 443k | uint8_t access[6]; |
716 | | |
717 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
718 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
719 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
720 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); |
721 | 443k | if (MCOperand_getReg(IndexReg) != X86_EIZ) { |
722 | 442k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); |
723 | 442k | } |
724 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
725 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
726 | | |
727 | 443k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
728 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
729 | 443k | } |
730 | | |
731 | | // If this has a segment register, print it. |
732 | 443k | segreg = MCOperand_getReg(SegReg); |
733 | 443k | if (segreg) { |
734 | 10.9k | _printOperand(MI, Op + X86_AddrSegmentReg, O); |
735 | 10.9k | SStream_concat0(O, ":"); |
736 | | |
737 | 10.9k | if (MI->csh->detail) { |
738 | 10.9k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(segreg); |
739 | 10.9k | } |
740 | 10.9k | } |
741 | | |
742 | 443k | if (MCOperand_isImm(DispSpec)) { |
743 | 443k | DispVal = MCOperand_getImm(DispSpec); |
744 | 443k | if (MI->csh->detail) |
745 | 443k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; |
746 | 443k | if (DispVal) { |
747 | 137k | if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
748 | 128k | printInt64(O, DispVal); |
749 | 128k | } else { |
750 | | // only immediate as address of memory |
751 | 8.39k | if (DispVal < 0) { |
752 | 2.83k | SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); |
753 | 5.56k | } else { |
754 | 5.56k | if (DispVal > HEX_THRESHOLD) |
755 | 5.12k | SStream_concat(O, "0x%"PRIx64, DispVal); |
756 | 438 | else |
757 | 438 | SStream_concat(O, "%"PRIu64, DispVal); |
758 | 5.56k | } |
759 | 8.39k | } |
760 | 137k | } |
761 | 443k | } |
762 | | |
763 | 443k | if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
764 | 434k | SStream_concat0(O, "("); |
765 | | |
766 | 434k | if (MCOperand_getReg(BaseReg)) |
767 | 433k | _printOperand(MI, Op + X86_AddrBaseReg, O); |
768 | | |
769 | 434k | if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { |
770 | 172k | SStream_concat0(O, ", "); |
771 | 172k | _printOperand(MI, Op + X86_AddrIndexReg, O); |
772 | 172k | ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); |
773 | 172k | if (MI->csh->detail) |
774 | 172k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; |
775 | 172k | if (ScaleVal != 1) { |
776 | 11.4k | SStream_concat(O, ", %u", ScaleVal); |
777 | 11.4k | } |
778 | 172k | } |
779 | | |
780 | 434k | SStream_concat0(O, ")"); |
781 | 434k | } else { |
782 | 8.87k | if (!DispVal) |
783 | 484 | SStream_concat0(O, "0"); |
784 | 8.87k | } |
785 | | |
786 | 443k | if (MI->csh->detail) |
787 | 443k | MI->flat_insn->detail->x86.op_count++; |
788 | 443k | } |
789 | | |
790 | | static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) |
791 | 7.14k | { |
792 | 7.14k | switch(MI->Opcode) { |
793 | 320 | default: break; |
794 | 1.14k | case X86_LEA16r: |
795 | 1.14k | MI->x86opsize = 2; |
796 | 1.14k | break; |
797 | 750 | case X86_LEA32r: |
798 | 1.43k | case X86_LEA64_32r: |
799 | 1.43k | MI->x86opsize = 4; |
800 | 1.43k | break; |
801 | 257 | case X86_LEA64r: |
802 | 257 | MI->x86opsize = 8; |
803 | 257 | break; |
804 | 470 | case X86_BNDCL32rm: |
805 | 1.37k | case X86_BNDCN32rm: |
806 | 1.55k | case X86_BNDCU32rm: |
807 | 2.24k | case X86_BNDSTXmr: |
808 | 3.35k | case X86_BNDLDXrm: |
809 | 3.66k | case X86_BNDCL64rm: |
810 | 3.84k | case X86_BNDCN64rm: |
811 | 3.99k | case X86_BNDCU64rm: |
812 | 3.99k | MI->x86opsize = 16; |
813 | 3.99k | break; |
814 | 7.14k | } |
815 | | |
816 | 7.14k | printMemReference(MI, OpNo, O); |
817 | 7.14k | } |
818 | | |
819 | | #include "X86InstPrinter.h" |
820 | | |
821 | | // Include the auto-generated portion of the assembly writer. |
822 | | #ifdef CAPSTONE_X86_REDUCE |
823 | | #include "X86GenAsmWriter_reduce.inc" |
824 | | #else |
825 | | #include "X86GenAsmWriter.inc" |
826 | | #endif |
827 | | |
828 | | #include "X86GenRegisterName.inc" |
829 | | |
830 | | static void printRegName(SStream *OS, unsigned RegNo) |
831 | 1.51M | { |
832 | 1.51M | SStream_concat(OS, "%%%s", getRegisterName(RegNo)); |
833 | 1.51M | } |
834 | | |
835 | | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) |
836 | 1.10M | { |
837 | 1.10M | x86_reg reg, reg2; |
838 | 1.10M | enum cs_ac_type access1, access2; |
839 | 1.10M | int i; |
840 | | |
841 | | // perhaps this instruction does not need printer |
842 | 1.10M | if (MI->assembly[0]) { |
843 | 0 | strncpy(OS->buffer, MI->assembly, sizeof(OS->buffer)); |
844 | 0 | return; |
845 | 0 | } |
846 | | |
847 | | // Output CALLpcrel32 as "callq" in 64-bit mode. |
848 | | // In Intel annotation it's always emitted as "call". |
849 | | // |
850 | | // TODO: Probably this hack should be redesigned via InstAlias in |
851 | | // InstrInfo.td as soon as Requires clause is supported properly |
852 | | // for InstAlias. |
853 | 1.10M | if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { |
854 | 0 | SStream_concat0(OS, "callq\t"); |
855 | 0 | MCInst_setOpcodePub(MI, X86_INS_CALL); |
856 | 0 | printPCRelImm(MI, 0, OS); |
857 | 0 | return; |
858 | 0 | } |
859 | | |
860 | 1.10M | X86_lockrep(MI, OS); |
861 | 1.10M | printInstruction(MI, OS); |
862 | | |
863 | 1.10M | if (MI->has_imm) { |
864 | | // if op_count > 1, then this operand's size is taken from the destination op |
865 | 205k | if (MI->flat_insn->detail->x86.op_count > 1) { |
866 | 109k | if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP && MI->flat_insn->id != X86_INS_JMP) { |
867 | 325k | for (i = 0; i < MI->flat_insn->detail->x86.op_count; i++) { |
868 | 219k | if (MI->flat_insn->detail->x86.operands[i].type == X86_OP_IMM) |
869 | 108k | MI->flat_insn->detail->x86.operands[i].size = |
870 | 108k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].size; |
871 | 219k | } |
872 | 106k | } |
873 | 109k | } else |
874 | 96.5k | MI->flat_insn->detail->x86.operands[0].size = MI->imm_size; |
875 | 205k | } |
876 | | |
877 | 1.10M | if (MI->csh->detail) { |
878 | 1.10M | uint8_t access[6] = {0}; |
879 | | |
880 | | // some instructions need to supply immediate 1 in the first op |
881 | 1.10M | switch(MCInst_getOpcode(MI)) { |
882 | 1.04M | default: |
883 | 1.04M | break; |
884 | 1.04M | case X86_SHL8r1: |
885 | 2.37k | case X86_SHL16r1: |
886 | 3.83k | case X86_SHL32r1: |
887 | 4.56k | case X86_SHL64r1: |
888 | 4.78k | case X86_SAL8r1: |
889 | 5.90k | case X86_SAL16r1: |
890 | 6.74k | case X86_SAL32r1: |
891 | 7.16k | case X86_SAL64r1: |
892 | 7.41k | case X86_SHR8r1: |
893 | 8.37k | case X86_SHR16r1: |
894 | 10.3k | case X86_SHR32r1: |
895 | 11.4k | case X86_SHR64r1: |
896 | 12.0k | case X86_SAR8r1: |
897 | 12.8k | case X86_SAR16r1: |
898 | 13.6k | case X86_SAR32r1: |
899 | 14.0k | case X86_SAR64r1: |
900 | 16.2k | case X86_RCL8r1: |
901 | 18.1k | case X86_RCL16r1: |
902 | 20.6k | case X86_RCL32r1: |
903 | 21.4k | case X86_RCL64r1: |
904 | 21.7k | case X86_RCR8r1: |
905 | 22.2k | case X86_RCR16r1: |
906 | 23.1k | case X86_RCR32r1: |
907 | 23.8k | case X86_RCR64r1: |
908 | 24.5k | case X86_ROL8r1: |
909 | 25.1k | case X86_ROL16r1: |
910 | 25.8k | case X86_ROL32r1: |
911 | 26.4k | case X86_ROL64r1: |
912 | 27.0k | case X86_ROR8r1: |
913 | 28.7k | case X86_ROR16r1: |
914 | 30.0k | case X86_ROR32r1: |
915 | 30.3k | case X86_ROR64r1: |
916 | 31.1k | case X86_SHL8m1: |
917 | 32.2k | case X86_SHL16m1: |
918 | 33.3k | case X86_SHL32m1: |
919 | 33.9k | case X86_SHL64m1: |
920 | 34.5k | case X86_SAL8m1: |
921 | 35.2k | case X86_SAL16m1: |
922 | 35.8k | case X86_SAL32m1: |
923 | 36.2k | case X86_SAL64m1: |
924 | 37.3k | case X86_SHR8m1: |
925 | 38.0k | case X86_SHR16m1: |
926 | 38.9k | case X86_SHR32m1: |
927 | 39.4k | case X86_SHR64m1: |
928 | 40.0k | case X86_SAR8m1: |
929 | 40.4k | case X86_SAR16m1: |
930 | 41.3k | case X86_SAR32m1: |
931 | 41.8k | case X86_SAR64m1: |
932 | 42.4k | case X86_RCL8m1: |
933 | 43.1k | case X86_RCL16m1: |
934 | 43.6k | case X86_RCL32m1: |
935 | 43.9k | case X86_RCL64m1: |
936 | 44.1k | case X86_RCR8m1: |
937 | 44.9k | case X86_RCR16m1: |
938 | 45.7k | case X86_RCR32m1: |
939 | 46.2k | case X86_RCR64m1: |
940 | 47.4k | case X86_ROL8m1: |
941 | 47.9k | case X86_ROL16m1: |
942 | 50.1k | case X86_ROL32m1: |
943 | 50.4k | case X86_ROL64m1: |
944 | 51.4k | case X86_ROR8m1: |
945 | 52.4k | case X86_ROR16m1: |
946 | 54.0k | case X86_ROR32m1: |
947 | 55.3k | case X86_ROR64m1: |
948 | | // shift all the ops right to leave 1st slot for this new register op |
949 | 55.3k | memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), |
950 | 55.3k | sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); |
951 | 55.3k | MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM; |
952 | 55.3k | MI->flat_insn->detail->x86.operands[0].imm = 1; |
953 | 55.3k | MI->flat_insn->detail->x86.operands[0].size = 1; |
954 | 55.3k | MI->flat_insn->detail->x86.op_count++; |
955 | 1.10M | } |
956 | | |
957 | | // special instruction needs to supply register op |
958 | | // first op can be embedded in the asm by llvm. |
959 | | // so we have to add the missing register as the first operand |
960 | | |
961 | | //printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); |
962 | | |
963 | 1.10M | reg = X86_insn_reg_att(MCInst_getOpcode(MI), &access1); |
964 | 1.10M | if (reg) { |
965 | | // shift all the ops right to leave 1st slot for this new register op |
966 | 61.1k | memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), |
967 | 61.1k | sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); |
968 | 61.1k | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
969 | 61.1k | MI->flat_insn->detail->x86.operands[0].reg = reg; |
970 | 61.1k | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
971 | 61.1k | MI->flat_insn->detail->x86.operands[0].access = access1; |
972 | | |
973 | 61.1k | MI->flat_insn->detail->x86.op_count++; |
974 | 1.04M | } else { |
975 | 1.04M | if (X86_insn_reg_att2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { |
976 | | |
977 | 19.4k | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
978 | 19.4k | MI->flat_insn->detail->x86.operands[0].reg = reg; |
979 | 19.4k | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
980 | 19.4k | MI->flat_insn->detail->x86.operands[0].access = access1; |
981 | 19.4k | MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; |
982 | 19.4k | MI->flat_insn->detail->x86.operands[1].reg = reg2; |
983 | 19.4k | MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; |
984 | 19.4k | MI->flat_insn->detail->x86.operands[0].access = access2; |
985 | 19.4k | MI->flat_insn->detail->x86.op_count = 2; |
986 | 19.4k | } |
987 | 1.04M | } |
988 | | |
989 | 1.10M | #ifndef CAPSTONE_DIET |
990 | 1.10M | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
991 | 1.10M | MI->flat_insn->detail->x86.operands[0].access = access[0]; |
992 | 1.10M | MI->flat_insn->detail->x86.operands[1].access = access[1]; |
993 | 1.10M | #endif |
994 | 1.10M | } |
995 | 1.10M | } |
996 | | |
997 | | #endif |