/src/capstonev5/arch/X86/X86IntelInstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file includes code for rendering MCInst instances as Intel-style |
11 | | // assembly. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | /* Capstone Disassembly Engine */ |
16 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
17 | | |
18 | | #ifdef CAPSTONE_HAS_X86 |
19 | | |
20 | | #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) |
21 | | #pragma warning(disable:4996) // disable MSVC's warning on strncpy() |
22 | | #pragma warning(disable:28719) // disable MSVC's warning on strncpy() |
23 | | #endif |
24 | | |
25 | | #if !defined(CAPSTONE_HAS_OSXKERNEL) |
26 | | #include <ctype.h> |
27 | | #endif |
28 | | #include <capstone/platform.h> |
29 | | |
30 | | #if defined(CAPSTONE_HAS_OSXKERNEL) |
31 | | #include <Availability.h> |
32 | | #include <libkern/libkern.h> |
33 | | #else |
34 | | #include <stdio.h> |
35 | | #include <stdlib.h> |
36 | | #endif |
37 | | #include <string.h> |
38 | | |
39 | | #include "../../utils.h" |
40 | | #include "../../MCInst.h" |
41 | | #include "../../SStream.h" |
42 | | #include "../../MCRegisterInfo.h" |
43 | | |
44 | | #include "X86InstPrinter.h" |
45 | | #include "X86Mapping.h" |
46 | | #include "X86InstPrinterCommon.h" |
47 | | |
48 | | #define GET_INSTRINFO_ENUM |
49 | | #ifdef CAPSTONE_X86_REDUCE |
50 | | #include "X86GenInstrInfo_reduce.inc" |
51 | | #else |
52 | | #include "X86GenInstrInfo.inc" |
53 | | #endif |
54 | | |
55 | | #define GET_REGINFO_ENUM |
56 | | #include "X86GenRegisterInfo.inc" |
57 | | |
58 | | #include "X86BaseInfo.h" |
59 | | |
60 | | static void printMemReference(MCInst *MI, unsigned Op, SStream *O); |
61 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
62 | | |
63 | | |
64 | | static void set_mem_access(MCInst *MI, bool status) |
65 | 196k | { |
66 | 196k | if (MI->csh->detail != CS_OPT_ON) |
67 | 0 | return; |
68 | | |
69 | 196k | MI->csh->doing_mem = status; |
70 | 196k | if (!status) |
71 | | // done, create the next operand slot |
72 | 98.2k | MI->flat_insn->detail->x86.op_count++; |
73 | | |
74 | 196k | } |
75 | | |
76 | | static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) |
77 | 14.1k | { |
78 | | // FIXME: do this with autogen |
79 | | // printf(">>> ID = %u\n", MI->flat_insn->id); |
80 | 14.1k | switch(MI->flat_insn->id) { |
81 | 4.81k | default: |
82 | 4.81k | SStream_concat0(O, "ptr "); |
83 | 4.81k | break; |
84 | 1.75k | case X86_INS_SGDT: |
85 | 3.00k | case X86_INS_SIDT: |
86 | 4.46k | case X86_INS_LGDT: |
87 | 6.09k | case X86_INS_LIDT: |
88 | 6.50k | case X86_INS_FXRSTOR: |
89 | 6.87k | case X86_INS_FXSAVE: |
90 | 8.10k | case X86_INS_LJMP: |
91 | 9.36k | case X86_INS_LCALL: |
92 | | // do not print "ptr" |
93 | 9.36k | break; |
94 | 14.1k | } |
95 | | |
96 | 14.1k | switch(MI->csh->mode) { |
97 | 3.48k | case CS_MODE_16: |
98 | 3.48k | switch(MI->flat_insn->id) { |
99 | 936 | default: |
100 | 936 | MI->x86opsize = 2; |
101 | 936 | break; |
102 | 463 | case X86_INS_LJMP: |
103 | 980 | case X86_INS_LCALL: |
104 | 980 | MI->x86opsize = 4; |
105 | 980 | break; |
106 | 380 | case X86_INS_SGDT: |
107 | 678 | case X86_INS_SIDT: |
108 | 1.09k | case X86_INS_LGDT: |
109 | 1.56k | case X86_INS_LIDT: |
110 | 1.56k | MI->x86opsize = 6; |
111 | 1.56k | break; |
112 | 3.48k | } |
113 | 3.48k | break; |
114 | 6.93k | case CS_MODE_32: |
115 | 6.93k | switch(MI->flat_insn->id) { |
116 | 2.82k | default: |
117 | 2.82k | MI->x86opsize = 4; |
118 | 2.82k | break; |
119 | 245 | case X86_INS_LJMP: |
120 | 1.24k | case X86_INS_JMP: |
121 | 1.58k | case X86_INS_LCALL: |
122 | 2.42k | case X86_INS_SGDT: |
123 | 3.03k | case X86_INS_SIDT: |
124 | 3.70k | case X86_INS_LGDT: |
125 | 4.11k | case X86_INS_LIDT: |
126 | 4.11k | MI->x86opsize = 6; |
127 | 4.11k | break; |
128 | 6.93k | } |
129 | 6.93k | break; |
130 | 6.93k | case CS_MODE_64: |
131 | 3.75k | switch(MI->flat_insn->id) { |
132 | 829 | default: |
133 | 829 | MI->x86opsize = 8; |
134 | 829 | break; |
135 | 524 | case X86_INS_LJMP: |
136 | 926 | case X86_INS_LCALL: |
137 | 1.45k | case X86_INS_SGDT: |
138 | 1.80k | case X86_INS_SIDT: |
139 | 2.17k | case X86_INS_LGDT: |
140 | 2.92k | case X86_INS_LIDT: |
141 | 2.92k | MI->x86opsize = 10; |
142 | 2.92k | break; |
143 | 3.75k | } |
144 | 3.75k | break; |
145 | 3.75k | default: // never reach |
146 | 0 | break; |
147 | 14.1k | } |
148 | | |
149 | 14.1k | printMemReference(MI, OpNo, O); |
150 | 14.1k | } |
151 | | |
152 | | static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) |
153 | 193k | { |
154 | 193k | SStream_concat0(O, "byte ptr "); |
155 | 193k | MI->x86opsize = 1; |
156 | 193k | printMemReference(MI, OpNo, O); |
157 | 193k | } |
158 | | |
159 | | static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) |
160 | 26.3k | { |
161 | 26.3k | MI->x86opsize = 2; |
162 | 26.3k | SStream_concat0(O, "word ptr "); |
163 | 26.3k | printMemReference(MI, OpNo, O); |
164 | 26.3k | } |
165 | | |
166 | | static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) |
167 | 69.0k | { |
168 | 69.0k | MI->x86opsize = 4; |
169 | 69.0k | SStream_concat0(O, "dword ptr "); |
170 | 69.0k | printMemReference(MI, OpNo, O); |
171 | 69.0k | } |
172 | | |
173 | | static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) |
174 | 21.1k | { |
175 | 21.1k | SStream_concat0(O, "qword ptr "); |
176 | 21.1k | MI->x86opsize = 8; |
177 | 21.1k | printMemReference(MI, OpNo, O); |
178 | 21.1k | } |
179 | | |
180 | | static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) |
181 | 5.78k | { |
182 | 5.78k | SStream_concat0(O, "xmmword ptr "); |
183 | 5.78k | MI->x86opsize = 16; |
184 | 5.78k | printMemReference(MI, OpNo, O); |
185 | 5.78k | } |
186 | | |
187 | | static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) |
188 | 4.40k | { |
189 | 4.40k | SStream_concat0(O, "zmmword ptr "); |
190 | 4.40k | MI->x86opsize = 64; |
191 | 4.40k | printMemReference(MI, OpNo, O); |
192 | 4.40k | } |
193 | | |
194 | | #ifndef CAPSTONE_X86_REDUCE |
195 | | static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) |
196 | 3.75k | { |
197 | 3.75k | SStream_concat0(O, "ymmword ptr "); |
198 | 3.75k | MI->x86opsize = 32; |
199 | 3.75k | printMemReference(MI, OpNo, O); |
200 | 3.75k | } |
201 | | |
202 | | static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) |
203 | 6.92k | { |
204 | 6.92k | switch(MCInst_getOpcode(MI)) { |
205 | 5.06k | default: |
206 | 5.06k | SStream_concat0(O, "dword ptr "); |
207 | 5.06k | MI->x86opsize = 4; |
208 | 5.06k | break; |
209 | 908 | case X86_FSTENVm: |
210 | 1.85k | case X86_FLDENVm: |
211 | | // TODO: fix this in tablegen instead |
212 | 1.85k | switch(MI->csh->mode) { |
213 | 0 | default: // never reach |
214 | 0 | break; |
215 | 730 | case CS_MODE_16: |
216 | 730 | MI->x86opsize = 14; |
217 | 730 | break; |
218 | 793 | case CS_MODE_32: |
219 | 1.12k | case CS_MODE_64: |
220 | 1.12k | MI->x86opsize = 28; |
221 | 1.12k | break; |
222 | 1.85k | } |
223 | 1.85k | break; |
224 | 6.92k | } |
225 | | |
226 | 6.92k | printMemReference(MI, OpNo, O); |
227 | 6.92k | } |
228 | | |
229 | | static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) |
230 | 6.56k | { |
231 | | // TODO: fix COMISD in Tablegen instead (#1456) |
232 | 6.56k | if (MI->op1_size == 16) { |
233 | | // printf("printf64mem id = %u\n", MCInst_getOpcode(MI)); |
234 | 2.67k | switch(MCInst_getOpcode(MI)) { |
235 | 2.36k | default: |
236 | 2.36k | SStream_concat0(O, "qword ptr "); |
237 | 2.36k | MI->x86opsize = 8; |
238 | 2.36k | break; |
239 | 0 | case X86_MOVPQI2QImr: |
240 | 310 | case X86_COMISDrm: |
241 | 310 | SStream_concat0(O, "xmmword ptr "); |
242 | 310 | MI->x86opsize = 16; |
243 | 310 | break; |
244 | 2.67k | } |
245 | 3.89k | } else { |
246 | 3.89k | SStream_concat0(O, "qword ptr "); |
247 | 3.89k | MI->x86opsize = 8; |
248 | 3.89k | } |
249 | | |
250 | 6.56k | printMemReference(MI, OpNo, O); |
251 | 6.56k | } |
252 | | |
253 | | static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) |
254 | 1.29k | { |
255 | 1.29k | switch(MCInst_getOpcode(MI)) { |
256 | 719 | default: |
257 | 719 | SStream_concat0(O, "xword ptr "); |
258 | 719 | break; |
259 | 379 | case X86_FBLDm: |
260 | 578 | case X86_FBSTPm: |
261 | 578 | break; |
262 | 1.29k | } |
263 | | |
264 | 1.29k | MI->x86opsize = 10; |
265 | 1.29k | printMemReference(MI, OpNo, O); |
266 | 1.29k | } |
267 | | |
268 | | static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) |
269 | 5.67k | { |
270 | 5.67k | SStream_concat0(O, "xmmword ptr "); |
271 | 5.67k | MI->x86opsize = 16; |
272 | 5.67k | printMemReference(MI, OpNo, O); |
273 | 5.67k | } |
274 | | |
275 | | static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) |
276 | 2.59k | { |
277 | 2.59k | SStream_concat0(O, "ymmword ptr "); |
278 | 2.59k | MI->x86opsize = 32; |
279 | 2.59k | printMemReference(MI, OpNo, O); |
280 | 2.59k | } |
281 | | |
282 | | static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) |
283 | 2.64k | { |
284 | 2.64k | SStream_concat0(O, "zmmword ptr "); |
285 | 2.64k | MI->x86opsize = 64; |
286 | 2.64k | printMemReference(MI, OpNo, O); |
287 | 2.64k | } |
288 | | #endif |
289 | | |
290 | | static const char *getRegisterName(unsigned RegNo); |
291 | | static void printRegName(SStream *OS, unsigned RegNo) |
292 | 1.20M | { |
293 | 1.20M | SStream_concat0(OS, getRegisterName(RegNo)); |
294 | 1.20M | } |
295 | | |
296 | | // for MASM syntax, 0x123 = 123h, 0xA123 = 0A123h |
297 | | // this function tell us if we need to have prefix 0 in front of a number |
298 | | static bool need_zero_prefix(uint64_t imm) |
299 | 0 | { |
300 | | // find the first hex letter representing imm |
301 | 0 | while(imm >= 0x10) |
302 | 0 | imm >>= 4; |
303 | |
|
304 | 0 | if (imm < 0xa) |
305 | 0 | return false; |
306 | 0 | else // this need 0 prefix |
307 | 0 | return true; |
308 | 0 | } |
309 | | |
310 | | static void printImm(MCInst *MI, SStream *O, int64_t imm, bool positive) |
311 | 328k | { |
312 | 328k | if (positive) { |
313 | | // always print this number in positive form |
314 | 277k | if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { |
315 | 0 | if (imm < 0) { |
316 | 0 | if (MI->op1_size) { |
317 | 0 | switch(MI->op1_size) { |
318 | 0 | default: |
319 | 0 | break; |
320 | 0 | case 1: |
321 | 0 | imm &= 0xff; |
322 | 0 | break; |
323 | 0 | case 2: |
324 | 0 | imm &= 0xffff; |
325 | 0 | break; |
326 | 0 | case 4: |
327 | 0 | imm &= 0xffffffff; |
328 | 0 | break; |
329 | 0 | } |
330 | 0 | } |
331 | | |
332 | 0 | if (imm == 0x8000000000000000LL) // imm == -imm |
333 | 0 | SStream_concat0(O, "8000000000000000h"); |
334 | 0 | else if (need_zero_prefix(imm)) |
335 | 0 | SStream_concat(O, "0%"PRIx64"h", imm); |
336 | 0 | else |
337 | 0 | SStream_concat(O, "%"PRIx64"h", imm); |
338 | 0 | } else { |
339 | 0 | if (imm > HEX_THRESHOLD) { |
340 | 0 | if (need_zero_prefix(imm)) |
341 | 0 | SStream_concat(O, "0%"PRIx64"h", imm); |
342 | 0 | else |
343 | 0 | SStream_concat(O, "%"PRIx64"h", imm); |
344 | 0 | } else |
345 | 0 | SStream_concat(O, "%"PRIu64, imm); |
346 | 0 | } |
347 | 277k | } else { // Intel syntax |
348 | 277k | if (imm < 0) { |
349 | 4.29k | if (MI->op1_size) { |
350 | 935 | switch(MI->op1_size) { |
351 | 935 | default: |
352 | 935 | break; |
353 | 935 | case 1: |
354 | 0 | imm &= 0xff; |
355 | 0 | break; |
356 | 0 | case 2: |
357 | 0 | imm &= 0xffff; |
358 | 0 | break; |
359 | 0 | case 4: |
360 | 0 | imm &= 0xffffffff; |
361 | 0 | break; |
362 | 935 | } |
363 | 935 | } |
364 | | |
365 | 4.29k | SStream_concat(O, "0x%"PRIx64, imm); |
366 | 273k | } else { |
367 | 273k | if (imm > HEX_THRESHOLD) |
368 | 258k | SStream_concat(O, "0x%"PRIx64, imm); |
369 | 14.9k | else |
370 | 14.9k | SStream_concat(O, "%"PRIu64, imm); |
371 | 273k | } |
372 | 277k | } |
373 | 277k | } else { |
374 | 50.3k | if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { |
375 | 0 | if (imm < 0) { |
376 | 0 | if (imm == 0x8000000000000000LL) // imm == -imm |
377 | 0 | SStream_concat0(O, "8000000000000000h"); |
378 | 0 | else if (imm < -HEX_THRESHOLD) { |
379 | 0 | if (need_zero_prefix(imm)) |
380 | 0 | SStream_concat(O, "-0%"PRIx64"h", -imm); |
381 | 0 | else |
382 | 0 | SStream_concat(O, "-%"PRIx64"h", -imm); |
383 | 0 | } else |
384 | 0 | SStream_concat(O, "-%"PRIu64, -imm); |
385 | 0 | } else { |
386 | 0 | if (imm > HEX_THRESHOLD) { |
387 | 0 | if (need_zero_prefix(imm)) |
388 | 0 | SStream_concat(O, "0%"PRIx64"h", imm); |
389 | 0 | else |
390 | 0 | SStream_concat(O, "%"PRIx64"h", imm); |
391 | 0 | } else |
392 | 0 | SStream_concat(O, "%"PRIu64, imm); |
393 | 0 | } |
394 | 50.3k | } else { // Intel syntax |
395 | 50.3k | if (imm < 0) { |
396 | 5.70k | if (imm == 0x8000000000000000LL) // imm == -imm |
397 | 0 | SStream_concat0(O, "0x8000000000000000"); |
398 | 5.70k | else if (imm < -HEX_THRESHOLD) |
399 | 5.15k | SStream_concat(O, "-0x%"PRIx64, -imm); |
400 | 548 | else |
401 | 548 | SStream_concat(O, "-%"PRIu64, -imm); |
402 | | |
403 | 44.6k | } else { |
404 | 44.6k | if (imm > HEX_THRESHOLD) |
405 | 37.8k | SStream_concat(O, "0x%"PRIx64, imm); |
406 | 6.78k | else |
407 | 6.78k | SStream_concat(O, "%"PRIu64, imm); |
408 | 44.6k | } |
409 | 50.3k | } |
410 | 50.3k | } |
411 | 328k | } |
412 | | |
413 | | // local printOperand, without updating public operands |
414 | | static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
415 | 439k | { |
416 | 439k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
417 | 439k | if (MCOperand_isReg(Op)) { |
418 | 439k | printRegName(O, MCOperand_getReg(Op)); |
419 | 439k | } else if (MCOperand_isImm(Op)) { |
420 | 0 | int64_t imm = MCOperand_getImm(Op); |
421 | 0 | printImm(MI, O, imm, MI->csh->imm_unsigned); |
422 | 0 | } |
423 | 439k | } |
424 | | |
425 | | #ifndef CAPSTONE_DIET |
426 | | // copy & normalize access info |
427 | | static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) |
428 | 2.28M | { |
429 | 2.28M | #ifndef CAPSTONE_DIET |
430 | 2.28M | uint8_t i; |
431 | 2.28M | const uint8_t *arr = X86_get_op_access(h, id, eflags); |
432 | | |
433 | 2.28M | if (!arr) { |
434 | 0 | access[0] = 0; |
435 | 0 | return; |
436 | 0 | } |
437 | | |
438 | | // copy to access but zero out CS_AC_IGNORE |
439 | 6.40M | for(i = 0; arr[i]; i++) { |
440 | 4.11M | if (arr[i] != CS_AC_IGNORE) |
441 | 3.48M | access[i] = arr[i]; |
442 | 638k | else |
443 | 638k | access[i] = 0; |
444 | 4.11M | } |
445 | | |
446 | | // mark the end of array |
447 | 2.28M | access[i] = 0; |
448 | 2.28M | #endif |
449 | 2.28M | } |
450 | | #endif |
451 | | |
452 | | static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) |
453 | 44.1k | { |
454 | 44.1k | MCOperand *SegReg; |
455 | 44.1k | int reg; |
456 | | |
457 | 44.1k | if (MI->csh->detail) { |
458 | 44.1k | #ifndef CAPSTONE_DIET |
459 | 44.1k | uint8_t access[6]; |
460 | 44.1k | #endif |
461 | | |
462 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
463 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
464 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
465 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
466 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
467 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
468 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
469 | | |
470 | 44.1k | #ifndef CAPSTONE_DIET |
471 | 44.1k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
472 | 44.1k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
473 | 44.1k | #endif |
474 | 44.1k | } |
475 | | |
476 | 44.1k | SegReg = MCInst_getOperand(MI, Op + 1); |
477 | 44.1k | reg = MCOperand_getReg(SegReg); |
478 | | |
479 | | // If this has a segment register, print it. |
480 | 44.1k | if (reg) { |
481 | 1.06k | _printOperand(MI, Op + 1, O); |
482 | 1.06k | if (MI->csh->detail) { |
483 | 1.06k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); |
484 | 1.06k | } |
485 | 1.06k | SStream_concat0(O, ":"); |
486 | 1.06k | } |
487 | | |
488 | 44.1k | SStream_concat0(O, "["); |
489 | 44.1k | set_mem_access(MI, true); |
490 | 44.1k | printOperand(MI, Op, O); |
491 | 44.1k | SStream_concat0(O, "]"); |
492 | 44.1k | set_mem_access(MI, false); |
493 | 44.1k | } |
494 | | |
495 | | static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) |
496 | 54.0k | { |
497 | 54.0k | if (MI->csh->detail) { |
498 | 54.0k | #ifndef CAPSTONE_DIET |
499 | 54.0k | uint8_t access[6]; |
500 | 54.0k | #endif |
501 | | |
502 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
503 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
504 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
505 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
506 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
507 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
508 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
509 | | |
510 | 54.0k | #ifndef CAPSTONE_DIET |
511 | 54.0k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
512 | 54.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
513 | 54.0k | #endif |
514 | 54.0k | } |
515 | | |
516 | | // DI accesses are always ES-based on non-64bit mode |
517 | 54.0k | if (MI->csh->mode != CS_MODE_64) { |
518 | 36.6k | SStream_concat0(O, "es:["); |
519 | 36.6k | if (MI->csh->detail) { |
520 | 36.6k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; |
521 | 36.6k | } |
522 | 36.6k | } else |
523 | 17.4k | SStream_concat0(O, "["); |
524 | | |
525 | 54.0k | set_mem_access(MI, true); |
526 | 54.0k | printOperand(MI, Op, O); |
527 | 54.0k | SStream_concat0(O, "]"); |
528 | 54.0k | set_mem_access(MI, false); |
529 | 54.0k | } |
530 | | |
531 | | static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
532 | 14.3k | { |
533 | 14.3k | SStream_concat0(O, "byte ptr "); |
534 | 14.3k | MI->x86opsize = 1; |
535 | 14.3k | printSrcIdx(MI, OpNo, O); |
536 | 14.3k | } |
537 | | |
538 | | static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
539 | 6.51k | { |
540 | 6.51k | SStream_concat0(O, "word ptr "); |
541 | 6.51k | MI->x86opsize = 2; |
542 | 6.51k | printSrcIdx(MI, OpNo, O); |
543 | 6.51k | } |
544 | | |
545 | | static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
546 | 20.7k | { |
547 | 20.7k | SStream_concat0(O, "dword ptr "); |
548 | 20.7k | MI->x86opsize = 4; |
549 | 20.7k | printSrcIdx(MI, OpNo, O); |
550 | 20.7k | } |
551 | | |
552 | | static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
553 | 2.56k | { |
554 | 2.56k | SStream_concat0(O, "qword ptr "); |
555 | 2.56k | MI->x86opsize = 8; |
556 | 2.56k | printSrcIdx(MI, OpNo, O); |
557 | 2.56k | } |
558 | | |
559 | | static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
560 | 19.2k | { |
561 | 19.2k | SStream_concat0(O, "byte ptr "); |
562 | 19.2k | MI->x86opsize = 1; |
563 | 19.2k | printDstIdx(MI, OpNo, O); |
564 | 19.2k | } |
565 | | |
566 | | static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
567 | 8.16k | { |
568 | 8.16k | SStream_concat0(O, "word ptr "); |
569 | 8.16k | MI->x86opsize = 2; |
570 | 8.16k | printDstIdx(MI, OpNo, O); |
571 | 8.16k | } |
572 | | |
573 | | static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
574 | 22.9k | { |
575 | 22.9k | SStream_concat0(O, "dword ptr "); |
576 | 22.9k | MI->x86opsize = 4; |
577 | 22.9k | printDstIdx(MI, OpNo, O); |
578 | 22.9k | } |
579 | | |
580 | | static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
581 | 3.77k | { |
582 | 3.77k | SStream_concat0(O, "qword ptr "); |
583 | 3.77k | MI->x86opsize = 8; |
584 | 3.77k | printDstIdx(MI, OpNo, O); |
585 | 3.77k | } |
586 | | |
587 | | static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) |
588 | 9.95k | { |
589 | 9.95k | MCOperand *DispSpec = MCInst_getOperand(MI, Op); |
590 | 9.95k | MCOperand *SegReg = MCInst_getOperand(MI, Op + 1); |
591 | 9.95k | int reg; |
592 | | |
593 | 9.95k | if (MI->csh->detail) { |
594 | 9.95k | #ifndef CAPSTONE_DIET |
595 | 9.95k | uint8_t access[6]; |
596 | 9.95k | #endif |
597 | | |
598 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
599 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
600 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
601 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
602 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
603 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
604 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
605 | | |
606 | 9.95k | #ifndef CAPSTONE_DIET |
607 | 9.95k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
608 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
609 | 9.95k | #endif |
610 | 9.95k | } |
611 | | |
612 | | // If this has a segment register, print it. |
613 | 9.95k | reg = MCOperand_getReg(SegReg); |
614 | 9.95k | if (reg) { |
615 | 397 | _printOperand(MI, Op + 1, O); |
616 | 397 | SStream_concat0(O, ":"); |
617 | 397 | if (MI->csh->detail) { |
618 | 397 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); |
619 | 397 | } |
620 | 397 | } |
621 | | |
622 | 9.95k | SStream_concat0(O, "["); |
623 | | |
624 | 9.95k | if (MCOperand_isImm(DispSpec)) { |
625 | 9.95k | int64_t imm = MCOperand_getImm(DispSpec); |
626 | 9.95k | if (MI->csh->detail) |
627 | 9.95k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
628 | | |
629 | 9.95k | if (imm < 0) |
630 | 1.73k | printImm(MI, O, arch_masks[MI->csh->mode] & imm, true); |
631 | 8.21k | else |
632 | 8.21k | printImm(MI, O, imm, true); |
633 | 9.95k | } |
634 | | |
635 | 9.95k | SStream_concat0(O, "]"); |
636 | | |
637 | 9.95k | if (MI->csh->detail) |
638 | 9.95k | MI->flat_insn->detail->x86.op_count++; |
639 | | |
640 | 9.95k | if (MI->op1_size == 0) |
641 | 9.95k | MI->op1_size = MI->x86opsize; |
642 | 9.95k | } |
643 | | |
644 | | static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) |
645 | 38.0k | { |
646 | 38.0k | uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; |
647 | | |
648 | 38.0k | printImm(MI, O, val, true); |
649 | | |
650 | 38.0k | if (MI->csh->detail) { |
651 | 38.0k | #ifndef CAPSTONE_DIET |
652 | 38.0k | uint8_t access[6]; |
653 | 38.0k | #endif |
654 | | |
655 | 38.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
656 | 38.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; |
657 | 38.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; |
658 | | |
659 | 38.0k | #ifndef CAPSTONE_DIET |
660 | 38.0k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
661 | 38.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
662 | 38.0k | #endif |
663 | | |
664 | 38.0k | MI->flat_insn->detail->x86.op_count++; |
665 | 38.0k | } |
666 | 38.0k | } |
667 | | |
668 | | static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) |
669 | 5.80k | { |
670 | 5.80k | SStream_concat0(O, "byte ptr "); |
671 | 5.80k | MI->x86opsize = 1; |
672 | 5.80k | printMemOffset(MI, OpNo, O); |
673 | 5.80k | } |
674 | | |
675 | | static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) |
676 | 1.21k | { |
677 | 1.21k | SStream_concat0(O, "word ptr "); |
678 | 1.21k | MI->x86opsize = 2; |
679 | 1.21k | printMemOffset(MI, OpNo, O); |
680 | 1.21k | } |
681 | | |
682 | | static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) |
683 | 2.58k | { |
684 | 2.58k | SStream_concat0(O, "dword ptr "); |
685 | 2.58k | MI->x86opsize = 4; |
686 | 2.58k | printMemOffset(MI, OpNo, O); |
687 | 2.58k | } |
688 | | |
689 | | static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) |
690 | 347 | { |
691 | 347 | SStream_concat0(O, "qword ptr "); |
692 | 347 | MI->x86opsize = 8; |
693 | 347 | printMemOffset(MI, OpNo, O); |
694 | 347 | } |
695 | | |
696 | | static void printInstruction(MCInst *MI, SStream *O); |
697 | | |
698 | | void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info) |
699 | 922k | { |
700 | 922k | x86_reg reg, reg2; |
701 | 922k | enum cs_ac_type access1, access2; |
702 | | |
703 | | // printf("opcode = %u\n", MCInst_getOpcode(MI)); |
704 | | |
705 | | // perhaps this instruction does not need printer |
706 | 922k | if (MI->assembly[0]) { |
707 | 0 | strncpy(O->buffer, MI->assembly, sizeof(O->buffer)); |
708 | 0 | return; |
709 | 0 | } |
710 | | |
711 | 922k | X86_lockrep(MI, O); |
712 | 922k | printInstruction(MI, O); |
713 | | |
714 | 922k | reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1); |
715 | 922k | if (MI->csh->detail) { |
716 | 922k | #ifndef CAPSTONE_DIET |
717 | 922k | uint8_t access[6] = {0}; |
718 | 922k | #endif |
719 | | |
720 | | // first op can be embedded in the asm by llvm. |
721 | | // so we have to add the missing register as the first operand |
722 | 922k | if (reg) { |
723 | | // shift all the ops right to leave 1st slot for this new register op |
724 | 100k | memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), |
725 | 100k | sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); |
726 | 100k | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
727 | 100k | MI->flat_insn->detail->x86.operands[0].reg = reg; |
728 | 100k | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
729 | 100k | MI->flat_insn->detail->x86.operands[0].access = access1; |
730 | 100k | MI->flat_insn->detail->x86.op_count++; |
731 | 822k | } else { |
732 | 822k | if (X86_insn_reg_intel2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { |
733 | 15.2k | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
734 | 15.2k | MI->flat_insn->detail->x86.operands[0].reg = reg; |
735 | 15.2k | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
736 | 15.2k | MI->flat_insn->detail->x86.operands[0].access = access1; |
737 | 15.2k | MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; |
738 | 15.2k | MI->flat_insn->detail->x86.operands[1].reg = reg2; |
739 | 15.2k | MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; |
740 | 15.2k | MI->flat_insn->detail->x86.operands[1].access = access2; |
741 | 15.2k | MI->flat_insn->detail->x86.op_count = 2; |
742 | 15.2k | } |
743 | 822k | } |
744 | | |
745 | 922k | #ifndef CAPSTONE_DIET |
746 | 922k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
747 | 922k | MI->flat_insn->detail->x86.operands[0].access = access[0]; |
748 | 922k | MI->flat_insn->detail->x86.operands[1].access = access[1]; |
749 | 922k | #endif |
750 | 922k | } |
751 | | |
752 | 922k | if (MI->op1_size == 0 && reg) |
753 | 76.2k | MI->op1_size = MI->csh->regsize_map[reg]; |
754 | 922k | } |
755 | | |
756 | | /// printPCRelImm - This is used to print an immediate value that ends up |
757 | | /// being encoded as a pc-relative value. |
758 | | static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) |
759 | 63.5k | { |
760 | 63.5k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
761 | 63.5k | if (MCOperand_isImm(Op)) { |
762 | 63.5k | int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; |
763 | 63.5k | uint8_t opsize = X86_immediate_size(MI->Opcode, NULL); |
764 | | |
765 | | // truncat imm for non-64bit |
766 | 63.5k | if (MI->csh->mode != CS_MODE_64) { |
767 | 44.7k | imm = imm & 0xffffffff; |
768 | 44.7k | } |
769 | | |
770 | 63.5k | printImm(MI, O, imm, true); |
771 | | |
772 | 63.5k | if (MI->csh->detail) { |
773 | 63.5k | #ifndef CAPSTONE_DIET |
774 | 63.5k | uint8_t access[6]; |
775 | 63.5k | #endif |
776 | | |
777 | 63.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
778 | | // if op_count > 0, then this operand's size is taken from the destination op |
779 | 63.5k | if (MI->flat_insn->detail->x86.op_count > 0) |
780 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; |
781 | 63.5k | else if (opsize > 0) |
782 | 2.06k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; |
783 | 61.4k | else |
784 | 61.4k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
785 | 63.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
786 | | |
787 | 63.5k | #ifndef CAPSTONE_DIET |
788 | 63.5k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
789 | 63.5k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
790 | 63.5k | #endif |
791 | | |
792 | 63.5k | MI->flat_insn->detail->x86.op_count++; |
793 | 63.5k | } |
794 | | |
795 | 63.5k | if (MI->op1_size == 0) |
796 | 63.5k | MI->op1_size = MI->imm_size; |
797 | 63.5k | } |
798 | 63.5k | } |
799 | | |
800 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
801 | 876k | { |
802 | 876k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
803 | | |
804 | 876k | if (MCOperand_isReg(Op)) { |
805 | 764k | unsigned int reg = MCOperand_getReg(Op); |
806 | | |
807 | 764k | printRegName(O, reg); |
808 | 764k | if (MI->csh->detail) { |
809 | 764k | if (MI->csh->doing_mem) { |
810 | 98.2k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); |
811 | 666k | } else { |
812 | 666k | #ifndef CAPSTONE_DIET |
813 | 666k | uint8_t access[6]; |
814 | 666k | #endif |
815 | | |
816 | 666k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; |
817 | 666k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); |
818 | 666k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; |
819 | | |
820 | 666k | #ifndef CAPSTONE_DIET |
821 | 666k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
822 | 666k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
823 | 666k | #endif |
824 | | |
825 | 666k | MI->flat_insn->detail->x86.op_count++; |
826 | 666k | } |
827 | 764k | } |
828 | | |
829 | 764k | if (MI->op1_size == 0) |
830 | 391k | MI->op1_size = MI->csh->regsize_map[X86_register_map(reg)]; |
831 | 764k | } else if (MCOperand_isImm(Op)) { |
832 | 112k | uint8_t encsize; |
833 | 112k | int64_t imm = MCOperand_getImm(Op); |
834 | 112k | uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); |
835 | | |
836 | 112k | if (opsize == 1) // print 1 byte immediate in positive form |
837 | 51.1k | imm = imm & 0xff; |
838 | | |
839 | | // printf(">>> id = %u\n", MI->flat_insn->id); |
840 | 112k | switch(MI->flat_insn->id) { |
841 | 50.3k | default: |
842 | 50.3k | printImm(MI, O, imm, MI->csh->imm_unsigned); |
843 | 50.3k | break; |
844 | | |
845 | 211 | case X86_INS_MOVABS: |
846 | 18.8k | case X86_INS_MOV: |
847 | | // do not print number in negative form |
848 | 18.8k | printImm(MI, O, imm, true); |
849 | 18.8k | break; |
850 | | |
851 | 0 | case X86_INS_IN: |
852 | 0 | case X86_INS_OUT: |
853 | 0 | case X86_INS_INT: |
854 | | // do not print number in negative form |
855 | 0 | imm = imm & 0xff; |
856 | 0 | printImm(MI, O, imm, true); |
857 | 0 | break; |
858 | | |
859 | 1.98k | case X86_INS_LCALL: |
860 | 4.24k | case X86_INS_LJMP: |
861 | 4.24k | case X86_INS_JMP: |
862 | | // always print address in positive form |
863 | 4.24k | if (OpNo == 1) { // ptr16 part |
864 | 2.12k | imm = imm & 0xffff; |
865 | 2.12k | opsize = 2; |
866 | 2.12k | } else |
867 | 2.12k | opsize = 4; |
868 | 4.24k | printImm(MI, O, imm, true); |
869 | 4.24k | break; |
870 | | |
871 | 9.53k | case X86_INS_AND: |
872 | 18.7k | case X86_INS_OR: |
873 | 26.8k | case X86_INS_XOR: |
874 | | // do not print number in negative form |
875 | 26.8k | if (imm >= 0 && imm <= HEX_THRESHOLD) |
876 | 3.35k | printImm(MI, O, imm, true); |
877 | 23.4k | else { |
878 | 23.4k | imm = arch_masks[opsize? opsize : MI->imm_size] & imm; |
879 | 23.4k | printImm(MI, O, imm, true); |
880 | 23.4k | } |
881 | 26.8k | break; |
882 | | |
883 | 10.1k | case X86_INS_RET: |
884 | 11.8k | case X86_INS_RETF: |
885 | | // RET imm16 |
886 | 11.8k | if (imm >= 0 && imm <= HEX_THRESHOLD) |
887 | 662 | printImm(MI, O, imm, true); |
888 | 11.1k | else { |
889 | 11.1k | imm = 0xffff & imm; |
890 | 11.1k | printImm(MI, O, imm, true); |
891 | 11.1k | } |
892 | 11.8k | break; |
893 | 112k | } |
894 | | |
895 | 112k | if (MI->csh->detail) { |
896 | 112k | if (MI->csh->doing_mem) { |
897 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
898 | 112k | } else { |
899 | 112k | #ifndef CAPSTONE_DIET |
900 | 112k | uint8_t access[6]; |
901 | 112k | #endif |
902 | | |
903 | 112k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
904 | 112k | if (opsize > 0) { |
905 | 93.4k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; |
906 | 93.4k | MI->flat_insn->detail->x86.encoding.imm_size = encsize; |
907 | 93.4k | } else if (MI->flat_insn->detail->x86.op_count > 0) { |
908 | 4.65k | if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) { |
909 | 4.65k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = |
910 | 4.65k | MI->flat_insn->detail->x86.operands[0].size; |
911 | 4.65k | } else |
912 | 0 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
913 | 4.65k | } else |
914 | 14.0k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
915 | 112k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
916 | | |
917 | 112k | #ifndef CAPSTONE_DIET |
918 | 112k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
919 | 112k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
920 | 112k | #endif |
921 | | |
922 | 112k | MI->flat_insn->detail->x86.op_count++; |
923 | 112k | } |
924 | 112k | } |
925 | 112k | } |
926 | 876k | } |
927 | | |
928 | | static void printMemReference(MCInst *MI, unsigned Op, SStream *O) |
929 | 370k | { |
930 | 370k | bool NeedPlus = false; |
931 | 370k | MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); |
932 | 370k | uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); |
933 | 370k | MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); |
934 | 370k | MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); |
935 | 370k | MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); |
936 | 370k | int reg; |
937 | | |
938 | 370k | if (MI->csh->detail) { |
939 | 370k | #ifndef CAPSTONE_DIET |
940 | 370k | uint8_t access[6]; |
941 | 370k | #endif |
942 | | |
943 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
944 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
945 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
946 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); |
947 | 370k | if (MCOperand_getReg(IndexReg) != X86_EIZ) { |
948 | 368k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); |
949 | 368k | } |
950 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; |
951 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
952 | | |
953 | 370k | #ifndef CAPSTONE_DIET |
954 | 370k | get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); |
955 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; |
956 | 370k | #endif |
957 | 370k | } |
958 | | |
959 | | // If this has a segment register, print it. |
960 | 370k | reg = MCOperand_getReg(SegReg); |
961 | 370k | if (reg) { |
962 | 9.13k | _printOperand(MI, Op + X86_AddrSegmentReg, O); |
963 | 9.13k | if (MI->csh->detail) { |
964 | 9.13k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); |
965 | 9.13k | } |
966 | 9.13k | SStream_concat0(O, ":"); |
967 | 9.13k | } |
968 | | |
969 | 370k | SStream_concat0(O, "["); |
970 | | |
971 | 370k | if (MCOperand_getReg(BaseReg)) { |
972 | 362k | _printOperand(MI, Op + X86_AddrBaseReg, O); |
973 | 362k | NeedPlus = true; |
974 | 362k | } |
975 | | |
976 | 370k | if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { |
977 | 65.9k | if (NeedPlus) SStream_concat0(O, " + "); |
978 | 65.9k | _printOperand(MI, Op + X86_AddrIndexReg, O); |
979 | 65.9k | if (ScaleVal != 1) |
980 | 11.7k | SStream_concat(O, "*%u", ScaleVal); |
981 | 65.9k | NeedPlus = true; |
982 | 65.9k | } |
983 | | |
984 | 370k | if (MCOperand_isImm(DispSpec)) { |
985 | 370k | int64_t DispVal = MCOperand_getImm(DispSpec); |
986 | 370k | if (MI->csh->detail) |
987 | 370k | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; |
988 | 370k | if (DispVal) { |
989 | 104k | if (NeedPlus) { |
990 | 97.6k | if (DispVal < 0) { |
991 | 38.7k | SStream_concat0(O, " - "); |
992 | 38.7k | printImm(MI, O, -DispVal, true); |
993 | 58.9k | } else { |
994 | 58.9k | SStream_concat0(O, " + "); |
995 | 58.9k | printImm(MI, O, DispVal, true); |
996 | 58.9k | } |
997 | 97.6k | } else { |
998 | | // memory reference to an immediate address |
999 | 6.84k | if (MI->csh->mode == CS_MODE_64) |
1000 | 424 | MI->op1_size = 8; |
1001 | 6.84k | if (DispVal < 0) { |
1002 | 2.68k | printImm(MI, O, arch_masks[MI->csh->mode] & DispVal, true); |
1003 | 4.16k | } else { |
1004 | 4.16k | printImm(MI, O, DispVal, true); |
1005 | 4.16k | } |
1006 | 6.84k | } |
1007 | | |
1008 | 266k | } else { |
1009 | | // DispVal = 0 |
1010 | 266k | if (!NeedPlus) // [0] |
1011 | 529 | SStream_concat0(O, "0"); |
1012 | 266k | } |
1013 | 370k | } |
1014 | | |
1015 | 370k | SStream_concat0(O, "]"); |
1016 | | |
1017 | 370k | if (MI->csh->detail) |
1018 | 370k | MI->flat_insn->detail->x86.op_count++; |
1019 | | |
1020 | 370k | if (MI->op1_size == 0) |
1021 | 263k | MI->op1_size = MI->x86opsize; |
1022 | 370k | } |
1023 | | |
1024 | | static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) |
1025 | 7.22k | { |
1026 | 7.22k | switch(MI->Opcode) { |
1027 | 236 | default: break; |
1028 | 817 | case X86_LEA16r: |
1029 | 817 | MI->x86opsize = 2; |
1030 | 817 | break; |
1031 | 887 | case X86_LEA32r: |
1032 | 1.67k | case X86_LEA64_32r: |
1033 | 1.67k | MI->x86opsize = 4; |
1034 | 1.67k | break; |
1035 | 288 | case X86_LEA64r: |
1036 | 288 | MI->x86opsize = 8; |
1037 | 288 | break; |
1038 | 328 | case X86_BNDCL32rm: |
1039 | 881 | case X86_BNDCN32rm: |
1040 | 1.06k | case X86_BNDCU32rm: |
1041 | 2.18k | case X86_BNDSTXmr: |
1042 | 3.04k | case X86_BNDLDXrm: |
1043 | 3.41k | case X86_BNDCL64rm: |
1044 | 4.01k | case X86_BNDCN64rm: |
1045 | 4.21k | case X86_BNDCU64rm: |
1046 | 4.21k | MI->x86opsize = 16; |
1047 | 4.21k | break; |
1048 | 7.22k | } |
1049 | | |
1050 | 7.22k | printMemReference(MI, OpNo, O); |
1051 | 7.22k | } |
1052 | | |
1053 | | #ifdef CAPSTONE_X86_REDUCE |
1054 | | #include "X86GenAsmWriter1_reduce.inc" |
1055 | | #else |
1056 | | #include "X86GenAsmWriter1.inc" |
1057 | | #endif |
1058 | | |
1059 | | #include "X86GenRegisterName1.inc" |
1060 | | |
1061 | | #endif |