/src/capstonev5/arch/XCore/XCoreDisassembler.c
Line | Count | Source (jump to first uncovered line) |
1 | | //===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | /* Capstone Disassembly Engine */ |
11 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
12 | | |
13 | | #ifdef CAPSTONE_HAS_XCORE |
14 | | |
15 | | #include <stdio.h> // DEBUG |
16 | | #include <stdlib.h> |
17 | | #include <string.h> |
18 | | |
19 | | #include "../../cs_priv.h" |
20 | | #include "../../utils.h" |
21 | | |
22 | | #include "XCoreDisassembler.h" |
23 | | |
24 | | #include "../../MCInst.h" |
25 | | #include "../../MCInstrDesc.h" |
26 | | #include "../../MCFixedLenDisassembler.h" |
27 | | #include "../../MCRegisterInfo.h" |
28 | | #include "../../MCDisassembler.h" |
29 | | #include "../../MathExtras.h" |
30 | | |
31 | | static uint64_t getFeatureBits(int mode) |
32 | 91.6k | { |
33 | | // support everything |
34 | 91.6k | return (uint64_t)-1; |
35 | 91.6k | } |
36 | | |
37 | | static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) |
38 | 84.7k | { |
39 | 84.7k | if (code_len < 2) |
40 | | // insufficient data |
41 | 346 | return false; |
42 | | |
43 | | // Encoded as a little-endian 16-bit word in the stream. |
44 | 84.4k | *insn = (code[0] << 0) | (code[1] << 8); |
45 | 84.4k | return true; |
46 | 84.7k | } |
47 | | |
48 | | static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) |
49 | 7.26k | { |
50 | 7.26k | if (code_len < 4) |
51 | | // insufficient data |
52 | 60 | return false; |
53 | | |
54 | | // Encoded as a little-endian 32-bit word in the stream. |
55 | 7.20k | *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24); |
56 | | |
57 | 7.20k | return true; |
58 | 7.26k | } |
59 | | |
60 | | static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) |
61 | 161k | { |
62 | 161k | const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); |
63 | 161k | return rc->RegsBegin[RegNo]; |
64 | 161k | } |
65 | | |
66 | | static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
67 | | uint64_t Address, const void *Decoder); |
68 | | |
69 | | static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
70 | | uint64_t Address, const void *Decoder); |
71 | | |
72 | | static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, |
73 | | uint64_t Address, const void *Decoder); |
74 | | |
75 | | static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, |
76 | | uint64_t Address, const void *Decoder); |
77 | | |
78 | | static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, |
79 | | uint64_t Address, const void *Decoder); |
80 | | |
81 | | static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, |
82 | | uint64_t Address, const void *Decoder); |
83 | | |
84 | | static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, |
85 | | uint64_t Address, const void *Decoder); |
86 | | |
87 | | static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, |
88 | | uint64_t Address, const void *Decoder); |
89 | | |
90 | | static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, |
91 | | uint64_t Address, const void *Decoder); |
92 | | |
93 | | static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, |
94 | | uint64_t Address, const void *Decoder); |
95 | | |
96 | | static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, |
97 | | uint64_t Address, const void *Decoder); |
98 | | |
99 | | static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, |
100 | | uint64_t Address, const void *Decoder); |
101 | | |
102 | | static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, |
103 | | uint64_t Address, const void *Decoder); |
104 | | |
105 | | static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, |
106 | | uint64_t Address, const void *Decoder); |
107 | | |
108 | | static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, |
109 | | uint64_t Address, const void *Decoder); |
110 | | |
111 | | static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, |
112 | | uint64_t Address, const void *Decoder); |
113 | | |
114 | | static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, |
115 | | uint64_t Address, const void *Decoder); |
116 | | |
117 | | static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, |
118 | | uint64_t Address, const void *Decoder); |
119 | | |
120 | | static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, |
121 | | uint64_t Address, const void *Decoder); |
122 | | |
123 | | static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, |
124 | | uint64_t Address, const void *Decoder); |
125 | | |
126 | | static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, |
127 | | uint64_t Address, const void *Decoder); |
128 | | |
129 | | static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, |
130 | | uint64_t Address, const void *Decoder); |
131 | | |
132 | | static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, |
133 | | uint64_t Address, const void *Decoder); |
134 | | |
135 | | static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, |
136 | | uint64_t Address, const void *Decoder); |
137 | | |
138 | | static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, |
139 | | uint64_t Address, const void *Decoder); |
140 | | |
141 | | #include "XCoreGenDisassemblerTables.inc" |
142 | | |
143 | | #define GET_REGINFO_ENUM |
144 | | #define GET_REGINFO_MC_DESC |
145 | | #include "XCoreGenRegisterInfo.inc" |
146 | | |
147 | | static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
148 | | uint64_t Address, const void *Decoder) |
149 | 152k | { |
150 | 152k | unsigned Reg; |
151 | | |
152 | 152k | if (RegNo > 11) |
153 | 33 | return MCDisassembler_Fail; |
154 | | |
155 | 152k | Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo); |
156 | 152k | MCOperand_CreateReg0(Inst, Reg); |
157 | | |
158 | 152k | return MCDisassembler_Success; |
159 | 152k | } |
160 | | |
161 | | static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
162 | | uint64_t Address, const void *Decoder) |
163 | 8.68k | { |
164 | 8.68k | unsigned Reg; |
165 | 8.68k | if (RegNo > 15) |
166 | 0 | return MCDisassembler_Fail; |
167 | | |
168 | 8.68k | Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo); |
169 | 8.68k | MCOperand_CreateReg0(Inst, Reg); |
170 | | |
171 | 8.68k | return MCDisassembler_Success; |
172 | 8.68k | } |
173 | | |
174 | | static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, |
175 | | uint64_t Address, const void *Decoder) |
176 | 5.03k | { |
177 | 5.03k | static const unsigned Values[] = { |
178 | 5.03k | 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 |
179 | 5.03k | }; |
180 | | |
181 | 5.03k | if (Val > 11) |
182 | 0 | return MCDisassembler_Fail; |
183 | | |
184 | 5.03k | MCOperand_CreateImm0(Inst, Values[Val]); |
185 | 5.03k | return MCDisassembler_Success; |
186 | 5.03k | } |
187 | | |
188 | | static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, |
189 | | uint64_t Address, const void *Decoder) |
190 | 4.66k | { |
191 | 4.66k | MCOperand_CreateImm0(Inst, -(int64_t)Val); |
192 | 4.66k | return MCDisassembler_Success; |
193 | 4.66k | } |
194 | | |
195 | | static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) |
196 | 54.7k | { |
197 | 54.7k | unsigned Op1High, Op2High; |
198 | 54.7k | unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); |
199 | | |
200 | 54.7k | if (Combined < 27) |
201 | 39.8k | return MCDisassembler_Fail; |
202 | | |
203 | 14.8k | if (fieldFromInstruction_4(Insn, 5, 1)) { |
204 | 5.88k | if (Combined == 31) |
205 | 17 | return MCDisassembler_Fail; |
206 | 5.86k | Combined += 5; |
207 | 5.86k | } |
208 | | |
209 | 14.8k | Combined -= 27; |
210 | 14.8k | Op1High = Combined % 3; |
211 | 14.8k | Op2High = Combined / 3; |
212 | 14.8k | *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); |
213 | 14.8k | *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); |
214 | | |
215 | 14.8k | return MCDisassembler_Success; |
216 | 14.8k | } |
217 | | |
218 | | static DecodeStatus Decode3OpInstruction(unsigned Insn, |
219 | | unsigned *Op1, unsigned *Op2, unsigned *Op3) |
220 | 45.9k | { |
221 | 45.9k | unsigned Op1High, Op2High, Op3High; |
222 | 45.9k | unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); |
223 | 45.9k | if (Combined >= 27) |
224 | 129 | return MCDisassembler_Fail; |
225 | | |
226 | 45.8k | Op1High = Combined % 3; |
227 | 45.8k | Op2High = (Combined / 3) % 3; |
228 | 45.8k | Op3High = Combined / 9; |
229 | 45.8k | *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); |
230 | 45.8k | *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); |
231 | 45.8k | *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2); |
232 | | |
233 | 45.8k | return MCDisassembler_Success; |
234 | 45.9k | } |
235 | | |
236 | | #define GET_INSTRINFO_ENUM |
237 | | #include "XCoreGenInstrInfo.inc" |
238 | | static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, |
239 | | const void *Decoder) |
240 | 37.5k | { |
241 | | // Try and decode as a 3R instruction. |
242 | 37.5k | unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); |
243 | 37.5k | switch (Opcode) { |
244 | 10.9k | case 0x0: |
245 | 10.9k | MCInst_setOpcode(Inst, XCore_STW_2rus); |
246 | 10.9k | return Decode2RUSInstruction(Inst, Insn, Address, Decoder); |
247 | 1.61k | case 0x1: |
248 | 1.61k | MCInst_setOpcode(Inst, XCore_LDW_2rus); |
249 | 1.61k | return Decode2RUSInstruction(Inst, Insn, Address, Decoder); |
250 | 1.51k | case 0x2: |
251 | 1.51k | MCInst_setOpcode(Inst, XCore_ADD_3r); |
252 | 1.51k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
253 | 2.11k | case 0x3: |
254 | 2.11k | MCInst_setOpcode(Inst, XCore_SUB_3r); |
255 | 2.11k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
256 | 855 | case 0x4: |
257 | 855 | MCInst_setOpcode(Inst, XCore_SHL_3r); |
258 | 855 | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
259 | 1.56k | case 0x5: |
260 | 1.56k | MCInst_setOpcode(Inst, XCore_SHR_3r); |
261 | 1.56k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
262 | 2.31k | case 0x6: |
263 | 2.31k | MCInst_setOpcode(Inst, XCore_EQ_3r); |
264 | 2.31k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
265 | 1.15k | case 0x7: |
266 | 1.15k | MCInst_setOpcode(Inst, XCore_AND_3r); |
267 | 1.15k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
268 | 2.67k | case 0x8: |
269 | 2.67k | MCInst_setOpcode(Inst, XCore_OR_3r); |
270 | 2.67k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
271 | 1.29k | case 0x9: |
272 | 1.29k | MCInst_setOpcode(Inst, XCore_LDW_3r); |
273 | 1.29k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
274 | 1.74k | case 0x10: |
275 | 1.74k | MCInst_setOpcode(Inst, XCore_LD16S_3r); |
276 | 1.74k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
277 | 1.05k | case 0x11: |
278 | 1.05k | MCInst_setOpcode(Inst, XCore_LD8U_3r); |
279 | 1.05k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
280 | 1.07k | case 0x12: |
281 | 1.07k | MCInst_setOpcode(Inst, XCore_ADD_2rus); |
282 | 1.07k | return Decode2RUSInstruction(Inst, Insn, Address, Decoder); |
283 | 0 | case 0x13: |
284 | 0 | MCInst_setOpcode(Inst, XCore_SUB_2rus); |
285 | 0 | return Decode2RUSInstruction(Inst, Insn, Address, Decoder); |
286 | 1.85k | case 0x14: |
287 | 1.85k | MCInst_setOpcode(Inst, XCore_SHL_2rus); |
288 | 1.85k | return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); |
289 | 919 | case 0x15: |
290 | 919 | MCInst_setOpcode(Inst, XCore_SHR_2rus); |
291 | 919 | return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); |
292 | 1.53k | case 0x16: |
293 | 1.53k | MCInst_setOpcode(Inst, XCore_EQ_2rus); |
294 | 1.53k | return Decode2RUSInstruction(Inst, Insn, Address, Decoder); |
295 | 1.19k | case 0x17: |
296 | 1.19k | MCInst_setOpcode(Inst, XCore_TSETR_3r); |
297 | 1.19k | return Decode3RImmInstruction(Inst, Insn, Address, Decoder); |
298 | 1.07k | case 0x18: |
299 | 1.07k | MCInst_setOpcode(Inst, XCore_LSS_3r); |
300 | 1.07k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
301 | 1.06k | case 0x19: |
302 | 1.06k | MCInst_setOpcode(Inst, XCore_LSU_3r); |
303 | 1.06k | return Decode3RInstruction(Inst, Insn, Address, Decoder); |
304 | 37.5k | } |
305 | | |
306 | 0 | return MCDisassembler_Fail; |
307 | 37.5k | } |
308 | | |
309 | | static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
310 | | const void *Decoder) |
311 | 27.4k | { |
312 | 27.4k | unsigned Op1, Op2; |
313 | 27.4k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
314 | 27.4k | if (S != MCDisassembler_Success) |
315 | 21.8k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
316 | | |
317 | 5.65k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
318 | 5.65k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
319 | | |
320 | 5.65k | return S; |
321 | 27.4k | } |
322 | | |
323 | | static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
324 | | const void *Decoder) |
325 | 2.41k | { |
326 | 2.41k | unsigned Op1, Op2; |
327 | 2.41k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
328 | 2.41k | if (S != MCDisassembler_Success) |
329 | 1.66k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
330 | | |
331 | 751 | MCOperand_CreateImm0(Inst, Op1); |
332 | 751 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
333 | | |
334 | 751 | return S; |
335 | 2.41k | } |
336 | | |
337 | | static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
338 | | const void *Decoder) |
339 | 5.87k | { |
340 | 5.87k | unsigned Op1, Op2; |
341 | 5.87k | DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); |
342 | 5.87k | if (S != MCDisassembler_Success) |
343 | 4.21k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
344 | | |
345 | 1.66k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
346 | 1.66k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
347 | | |
348 | 1.66k | return S; |
349 | 5.87k | } |
350 | | |
351 | | static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
352 | | const void *Decoder) |
353 | 7.15k | { |
354 | 7.15k | unsigned Op1, Op2; |
355 | 7.15k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
356 | 7.15k | if (S != MCDisassembler_Success) |
357 | 4.94k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
358 | | |
359 | 2.21k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
360 | 2.21k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
361 | 2.21k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
362 | | |
363 | 2.21k | return S; |
364 | 7.15k | } |
365 | | |
366 | | static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
367 | | const void *Decoder) |
368 | 2.42k | { |
369 | 2.42k | unsigned Op1, Op2; |
370 | 2.42k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
371 | 2.42k | if (S != MCDisassembler_Success) |
372 | 1.65k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
373 | | |
374 | 769 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
375 | 769 | MCOperand_CreateImm0(Inst, Op2); |
376 | | |
377 | 769 | return S; |
378 | 2.42k | } |
379 | | |
380 | | static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
381 | | const void *Decoder) |
382 | 1.46k | { |
383 | 1.46k | unsigned Op1, Op2; |
384 | 1.46k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
385 | 1.46k | if (S != MCDisassembler_Success) |
386 | 766 | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
387 | | |
388 | 701 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
389 | 701 | DecodeBitpOperand(Inst, Op2, Address, Decoder); |
390 | | |
391 | 701 | return S; |
392 | 1.46k | } |
393 | | |
394 | | static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
395 | | const void *Decoder) |
396 | 3.84k | { |
397 | 3.84k | unsigned Op1, Op2; |
398 | 3.84k | DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); |
399 | 3.84k | if (S != MCDisassembler_Success) |
400 | 2.51k | return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); |
401 | | |
402 | 1.32k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
403 | 1.32k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
404 | 1.32k | DecodeBitpOperand(Inst, Op2, Address, Decoder); |
405 | | |
406 | 1.32k | return S; |
407 | 3.84k | } |
408 | | |
409 | | static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, |
410 | | const void *Decoder) |
411 | 1.74k | { |
412 | | // Try and decode as a L3R / L2RUS instruction. |
413 | 1.74k | unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | |
414 | 1.74k | fieldFromInstruction_4(Insn, 27, 5) << 4; |
415 | 1.74k | switch (Opcode) { |
416 | 128 | case 0x0c: |
417 | 128 | MCInst_setOpcode(Inst, XCore_STW_l3r); |
418 | 128 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
419 | 279 | case 0x1c: |
420 | 279 | MCInst_setOpcode(Inst, XCore_XOR_l3r); |
421 | 279 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
422 | 117 | case 0x2c: |
423 | 117 | MCInst_setOpcode(Inst, XCore_ASHR_l3r); |
424 | 117 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
425 | 172 | case 0x3c: |
426 | 172 | MCInst_setOpcode(Inst, XCore_LDAWF_l3r); |
427 | 172 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
428 | 615 | case 0x4c: |
429 | 615 | MCInst_setOpcode(Inst, XCore_LDAWB_l3r); |
430 | 615 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
431 | 249 | case 0x5c: |
432 | 249 | MCInst_setOpcode(Inst, XCore_LDA16F_l3r); |
433 | 249 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
434 | 185 | case 0x6c: |
435 | 185 | MCInst_setOpcode(Inst, XCore_LDA16B_l3r); |
436 | 185 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
437 | 0 | case 0x7c: |
438 | 0 | MCInst_setOpcode(Inst, XCore_MUL_l3r); |
439 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
440 | 0 | case 0x8c: |
441 | 0 | MCInst_setOpcode(Inst, XCore_DIVS_l3r); |
442 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
443 | 0 | case 0x9c: |
444 | 0 | MCInst_setOpcode(Inst, XCore_DIVU_l3r); |
445 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
446 | 0 | case 0x10c: |
447 | 0 | MCInst_setOpcode(Inst, XCore_ST16_l3r); |
448 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
449 | 0 | case 0x11c: |
450 | 0 | MCInst_setOpcode(Inst, XCore_ST8_l3r); |
451 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
452 | 0 | case 0x12c: |
453 | 0 | MCInst_setOpcode(Inst, XCore_ASHR_l2rus); |
454 | 0 | return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); |
455 | 0 | case 0x12d: |
456 | 0 | MCInst_setOpcode(Inst, XCore_OUTPW_l2rus); |
457 | 0 | return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); |
458 | 0 | case 0x12e: |
459 | 0 | MCInst_setOpcode(Inst, XCore_INPW_l2rus); |
460 | 0 | return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); |
461 | 0 | case 0x13c: |
462 | 0 | MCInst_setOpcode(Inst, XCore_LDAWF_l2rus); |
463 | 0 | return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); |
464 | 0 | case 0x14c: |
465 | 0 | MCInst_setOpcode(Inst, XCore_LDAWB_l2rus); |
466 | 0 | return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); |
467 | 0 | case 0x15c: |
468 | 0 | MCInst_setOpcode(Inst, XCore_CRC_l3r); |
469 | 0 | return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); |
470 | 0 | case 0x18c: |
471 | 0 | MCInst_setOpcode(Inst, XCore_REMS_l3r); |
472 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
473 | 0 | case 0x19c: |
474 | 0 | MCInst_setOpcode(Inst, XCore_REMU_l3r); |
475 | 0 | return DecodeL3RInstruction(Inst, Insn, Address, Decoder); |
476 | 1.74k | } |
477 | | |
478 | 0 | return MCDisassembler_Fail; |
479 | 1.74k | } |
480 | | |
481 | | static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
482 | | const void *Decoder) |
483 | 1.23k | { |
484 | 1.23k | unsigned Op1, Op2; |
485 | 1.23k | DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); |
486 | 1.23k | if (S != MCDisassembler_Success) |
487 | 831 | return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); |
488 | | |
489 | 400 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
490 | 400 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
491 | | |
492 | 400 | return S; |
493 | 1.23k | } |
494 | | |
495 | | static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
496 | | const void *Decoder) |
497 | 1.41k | { |
498 | 1.41k | unsigned Op1, Op2; |
499 | 1.41k | DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); |
500 | 1.41k | if (S != MCDisassembler_Success) |
501 | 914 | return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); |
502 | | |
503 | 500 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
504 | 500 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
505 | | |
506 | 500 | return S; |
507 | 1.41k | } |
508 | | |
509 | | static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
510 | | const void *Decoder) |
511 | 20.0k | { |
512 | 20.0k | unsigned Op1, Op2, Op3; |
513 | 20.0k | DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); |
514 | 20.0k | if (S == MCDisassembler_Success) { |
515 | 20.0k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
516 | 20.0k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
517 | 20.0k | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
518 | 20.0k | } |
519 | | |
520 | 20.0k | return S; |
521 | 20.0k | } |
522 | | |
523 | | static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
524 | | const void *Decoder) |
525 | 1.19k | { |
526 | 1.19k | unsigned Op1, Op2, Op3; |
527 | 1.19k | DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); |
528 | 1.19k | if (S == MCDisassembler_Success) { |
529 | 1.19k | MCOperand_CreateImm0(Inst, Op1); |
530 | 1.19k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
531 | 1.19k | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
532 | 1.19k | } |
533 | | |
534 | 1.19k | return S; |
535 | 1.19k | } |
536 | | |
537 | | static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
538 | | const void *Decoder) |
539 | 16.3k | { |
540 | 16.3k | unsigned Op1, Op2, Op3; |
541 | 16.3k | DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); |
542 | 16.3k | if (S == MCDisassembler_Success) { |
543 | 16.3k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
544 | 16.3k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
545 | 16.3k | MCOperand_CreateImm0(Inst, Op3); |
546 | 16.3k | } |
547 | | |
548 | 16.3k | return S; |
549 | 16.3k | } |
550 | | |
551 | | static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
552 | | const void *Decoder) |
553 | 2.77k | { |
554 | 2.77k | unsigned Op1, Op2, Op3; |
555 | 2.77k | DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); |
556 | 2.77k | if (S == MCDisassembler_Success) { |
557 | 2.76k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
558 | 2.76k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
559 | 2.76k | DecodeBitpOperand(Inst, Op3, Address, Decoder); |
560 | 2.76k | } |
561 | | |
562 | 2.77k | return S; |
563 | 2.77k | } |
564 | | |
565 | | static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
566 | | const void *Decoder) |
567 | 1.85k | { |
568 | 1.85k | unsigned Op1, Op2, Op3; |
569 | 1.85k | DecodeStatus S = |
570 | 1.85k | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
571 | 1.85k | if (S == MCDisassembler_Success) { |
572 | 1.84k | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
573 | 1.84k | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
574 | 1.84k | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
575 | 1.84k | } |
576 | | |
577 | 1.85k | return S; |
578 | 1.85k | } |
579 | | |
580 | | static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
581 | | const void *Decoder) |
582 | 86 | { |
583 | 86 | unsigned Op1, Op2, Op3; |
584 | 86 | DecodeStatus S = |
585 | 86 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
586 | 86 | if (S == MCDisassembler_Success) { |
587 | 83 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
588 | 83 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
589 | 83 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
590 | 83 | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
591 | 83 | } |
592 | | |
593 | 86 | return S; |
594 | 86 | } |
595 | | |
596 | | static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
597 | | const void *Decoder) |
598 | 90 | { |
599 | 90 | unsigned Op1, Op2, Op3; |
600 | 90 | DecodeStatus S = |
601 | 90 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
602 | 90 | if (S == MCDisassembler_Success) { |
603 | 89 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
604 | 89 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
605 | 89 | MCOperand_CreateImm0(Inst, Op3); |
606 | 89 | } |
607 | | |
608 | 90 | return S; |
609 | 90 | } |
610 | | |
611 | | static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
612 | | const void *Decoder) |
613 | 243 | { |
614 | 243 | unsigned Op1, Op2, Op3; |
615 | 243 | DecodeStatus S = |
616 | 243 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
617 | 243 | if (S == MCDisassembler_Success) { |
618 | 240 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
619 | 240 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
620 | 240 | DecodeBitpOperand(Inst, Op3, Address, Decoder); |
621 | 240 | } |
622 | | |
623 | 243 | return S; |
624 | 243 | } |
625 | | |
626 | | static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
627 | | const void *Decoder) |
628 | 579 | { |
629 | 579 | unsigned Op1, Op2, Op3, Op4, Op5, Op6; |
630 | 579 | DecodeStatus S = |
631 | 579 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
632 | 579 | if (S != MCDisassembler_Success) |
633 | 38 | return S; |
634 | | |
635 | 541 | S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); |
636 | 541 | if (S != MCDisassembler_Success) |
637 | 0 | return S; |
638 | | |
639 | 541 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
640 | 541 | DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
641 | 541 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
642 | 541 | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
643 | 541 | DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); |
644 | 541 | DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); |
645 | 541 | return S; |
646 | 541 | } |
647 | | |
648 | | static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, |
649 | | const void *Decoder) |
650 | 587 | { |
651 | 587 | unsigned Opcode; |
652 | | |
653 | | // Try and decode as a L6R instruction. |
654 | 587 | MCInst_clear(Inst); |
655 | 587 | Opcode = fieldFromInstruction_4(Insn, 27, 5); |
656 | 587 | switch (Opcode) { |
657 | 8 | default: |
658 | 8 | break; |
659 | 579 | case 0x00: |
660 | 579 | MCInst_setOpcode(Inst, XCore_LMUL_l6r); |
661 | 579 | return DecodeL6RInstruction(Inst, Insn, Address, Decoder); |
662 | 587 | } |
663 | | |
664 | 8 | return MCDisassembler_Fail; |
665 | 587 | } |
666 | | |
667 | | static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
668 | | const void *Decoder) |
669 | 1.45k | { |
670 | 1.45k | unsigned Op1, Op2, Op3, Op4, Op5; |
671 | 1.45k | DecodeStatus S = |
672 | 1.45k | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
673 | 1.45k | if (S != MCDisassembler_Success) |
674 | 42 | return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); |
675 | | |
676 | 1.41k | S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); |
677 | 1.41k | if (S != MCDisassembler_Success) |
678 | 545 | return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); |
679 | | |
680 | 866 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
681 | 866 | DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
682 | 866 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
683 | 866 | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
684 | 866 | DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); |
685 | 866 | return S; |
686 | 1.41k | } |
687 | | |
688 | | static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
689 | | const void *Decoder) |
690 | 376 | { |
691 | 376 | unsigned Op1, Op2, Op3; |
692 | 376 | unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); |
693 | 376 | DecodeStatus S = |
694 | 376 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
695 | 376 | if (S == MCDisassembler_Success) { |
696 | 374 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
697 | 374 | S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
698 | 374 | } |
699 | | |
700 | 376 | if (S == MCDisassembler_Success) { |
701 | 371 | DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
702 | 371 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
703 | 371 | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
704 | 371 | } |
705 | 376 | return S; |
706 | 376 | } |
707 | | |
708 | | static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, |
709 | | const void *Decoder) |
710 | 353 | { |
711 | 353 | unsigned Op1, Op2, Op3; |
712 | 353 | unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); |
713 | 353 | DecodeStatus S = |
714 | 353 | Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); |
715 | 353 | if (S == MCDisassembler_Success) { |
716 | 350 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
717 | 350 | S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
718 | 350 | } |
719 | | |
720 | 353 | if (S == MCDisassembler_Success) { |
721 | 348 | DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); |
722 | 348 | DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); |
723 | 348 | DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); |
724 | 348 | DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); |
725 | 348 | } |
726 | | |
727 | 353 | return S; |
728 | 353 | } |
729 | | |
730 | | #define GET_SUBTARGETINFO_ENUM |
731 | | #include "XCoreGenInstrInfo.inc" |
732 | | bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, |
733 | | uint16_t *size, uint64_t address, void *info) |
734 | 84.7k | { |
735 | 84.7k | uint16_t insn16; |
736 | 84.7k | uint32_t insn32; |
737 | 84.7k | DecodeStatus Result; |
738 | | |
739 | 84.7k | if (!readInstruction16(code, code_len, &insn16)) { |
740 | 346 | return false; |
741 | 346 | } |
742 | | |
743 | 84.4k | if (MI->flat_insn->detail) { |
744 | 84.4k | memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore)); |
745 | 84.4k | } |
746 | | |
747 | | // Calling the auto-generated decoder function. |
748 | 84.4k | Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0); |
749 | 84.4k | if (Result != MCDisassembler_Fail) { |
750 | 77.1k | *size = 2; |
751 | 77.1k | return true; |
752 | 77.1k | } |
753 | | |
754 | 7.26k | if (!readInstruction32(code, code_len, &insn32)) { |
755 | 60 | return false; |
756 | 60 | } |
757 | | |
758 | | // Calling the auto-generated decoder function. |
759 | 7.20k | Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0); |
760 | 7.20k | if (Result != MCDisassembler_Fail) { |
761 | 6.86k | *size = 4; |
762 | 6.86k | return true; |
763 | 6.86k | } |
764 | | |
765 | 340 | return false; |
766 | 7.20k | } |
767 | | |
768 | | void XCore_init(MCRegisterInfo *MRI) |
769 | 1.26k | { |
770 | | /* |
771 | | InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, |
772 | | XCoreMCRegisterClasses, 2, |
773 | | XCoreRegUnitRoots, |
774 | | 16, |
775 | | XCoreRegDiffLists, |
776 | | XCoreRegStrings, |
777 | | XCoreSubRegIdxLists, |
778 | | 1, |
779 | | XCoreSubRegIdxRanges, |
780 | | XCoreRegEncodingTable); |
781 | | */ |
782 | | |
783 | | |
784 | 1.26k | MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17, |
785 | 1.26k | 0, 0, |
786 | 1.26k | XCoreMCRegisterClasses, 2, |
787 | 1.26k | 0, 0, |
788 | 1.26k | XCoreRegDiffLists, |
789 | 1.26k | 0, |
790 | 1.26k | XCoreSubRegIdxLists, 1, |
791 | 1.26k | 0); |
792 | 1.26k | } |
793 | | |
794 | | #endif |