/src/capstonev5/arch/AArch64/AArch64InstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This class prints an AArch64 MCInst to a .s file. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | /* Capstone Disassembly Engine */ |
15 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */ |
16 | | |
17 | | #ifdef CAPSTONE_HAS_ARM64 |
18 | | |
19 | | #include <capstone/platform.h> |
20 | | #include <stdio.h> |
21 | | #include <stdlib.h> |
22 | | |
23 | | #include "AArch64InstPrinter.h" |
24 | | #include "AArch64Disassembler.h" |
25 | | #include "AArch64BaseInfo.h" |
26 | | #include "../../utils.h" |
27 | | #include "../../MCInst.h" |
28 | | #include "../../SStream.h" |
29 | | #include "../../MCRegisterInfo.h" |
30 | | #include "../../MathExtras.h" |
31 | | |
32 | | #include "AArch64Mapping.h" |
33 | | #include "AArch64AddressingModes.h" |
34 | | |
35 | | #define GET_REGINFO_ENUM |
36 | | #include "AArch64GenRegisterInfo.inc" |
37 | | |
38 | | #define GET_INSTRINFO_ENUM |
39 | | #include "AArch64GenInstrInfo.inc" |
40 | | |
41 | | #include "AArch64GenSubtargetInfo.inc" |
42 | | |
43 | | |
44 | | static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); |
45 | | static void printOperand(MCInst *MI, unsigned OpNum, SStream *O); |
46 | | static bool printSysAlias(MCInst *MI, SStream *O); |
47 | | static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); |
48 | | static void printInstruction(MCInst *MI, SStream *O); |
49 | | static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); |
50 | | static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx, |
51 | | unsigned PrintMethodIdx, SStream *OS); |
52 | | |
53 | | |
54 | | static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index) |
55 | 482k | { |
56 | 482k | #ifndef CAPSTONE_DIET |
57 | 482k | const uint8_t *arr = AArch64_get_op_access(h, id); |
58 | | |
59 | 482k | if (arr[index] == CS_AC_IGNORE) |
60 | 0 | return 0; |
61 | | |
62 | 482k | return arr[index]; |
63 | | #else |
64 | | return 0; |
65 | | #endif |
66 | 482k | } |
67 | | |
68 | | static void op_addImm(MCInst *MI, int v) |
69 | 811 | { |
70 | 811 | if (MI->csh->detail) { |
71 | 811 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
72 | 811 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v; |
73 | 811 | MI->flat_insn->detail->arm64.op_count++; |
74 | 811 | } |
75 | 811 | } |
76 | | |
77 | | static void set_sme_index(MCInst *MI, bool status) |
78 | 4.53k | { |
79 | | // Doing SME Index operand |
80 | 4.53k | MI->csh->doing_SME_Index = status; |
81 | | |
82 | 4.53k | if (MI->csh->detail != CS_OPT_ON) |
83 | 0 | return; |
84 | | |
85 | 4.53k | if (status) { |
86 | 3.29k | unsigned prevOpNum = MI->flat_insn->detail->arm64.op_count - 1; |
87 | 3.29k | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, prevOpNum)); |
88 | | // Replace previous SME register operand with an OP_SME_INDEX operand |
89 | 3.29k | MI->flat_insn->detail->arm64.operands[prevOpNum].type = ARM64_OP_SME_INDEX; |
90 | 3.29k | MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.reg = Reg; |
91 | 3.29k | MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.base = ARM64_REG_INVALID; |
92 | 3.29k | MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.disp = 0; |
93 | 3.29k | } |
94 | 4.53k | } |
95 | | |
96 | | static void set_mem_access(MCInst *MI, bool status) |
97 | 151k | { |
98 | | // If status == false, check if this is meant for SME_index |
99 | 151k | if(!status && MI->csh->doing_SME_Index) { |
100 | 2.05k | MI->csh->doing_SME_Index = status; |
101 | 2.05k | return; |
102 | 2.05k | } |
103 | | |
104 | | // Doing Memory Operation |
105 | 149k | MI->csh->doing_mem = status; |
106 | | |
107 | | |
108 | 149k | if (MI->csh->detail != CS_OPT_ON) |
109 | 0 | return; |
110 | | |
111 | 149k | if (status) { |
112 | 74.5k | #ifndef CAPSTONE_DIET |
113 | 74.5k | uint8_t access; |
114 | 74.5k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
115 | 74.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
116 | 74.5k | MI->ac_idx++; |
117 | 74.5k | #endif |
118 | 74.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; |
119 | 74.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID; |
120 | 74.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID; |
121 | 74.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; |
122 | 74.6k | } else { |
123 | | // done, create the next operand slot |
124 | 74.6k | MI->flat_insn->detail->arm64.op_count++; |
125 | 74.6k | } |
126 | 149k | } |
127 | | |
128 | | void AArch64_printInst(MCInst *MI, SStream *O, void *Info) |
129 | 180k | { |
130 | | // Check for special encodings and print the canonical alias instead. |
131 | 180k | unsigned Opcode = MCInst_getOpcode(MI); |
132 | 180k | int LSB, Width; |
133 | 180k | char *mnem; |
134 | | |
135 | | // printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); |
136 | | |
137 | 180k | if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) |
138 | 1.06k | return; |
139 | | |
140 | | // SBFM/UBFM should print to a nicer aliased form if possible. |
141 | 179k | if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || |
142 | 179k | Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { |
143 | 4.89k | bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); |
144 | 4.89k | bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); |
145 | | |
146 | 4.89k | MCOperand *Op0 = MCInst_getOperand(MI, 0); |
147 | 4.89k | MCOperand *Op1 = MCInst_getOperand(MI, 1); |
148 | 4.89k | MCOperand *Op2 = MCInst_getOperand(MI, 2); |
149 | 4.89k | MCOperand *Op3 = MCInst_getOperand(MI, 3); |
150 | | |
151 | 4.89k | if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { |
152 | 4.07k | const char *AsmMnemonic = NULL; |
153 | | |
154 | 4.07k | switch (MCOperand_getImm(Op3)) { |
155 | 953 | default: |
156 | 953 | break; |
157 | | |
158 | 1.63k | case 7: |
159 | 1.63k | if (IsSigned) |
160 | 1.52k | AsmMnemonic = "sxtb"; |
161 | 112 | else if (!Is64Bit) |
162 | 93 | AsmMnemonic = "uxtb"; |
163 | 1.63k | break; |
164 | | |
165 | 438 | case 15: |
166 | 438 | if (IsSigned) |
167 | 418 | AsmMnemonic = "sxth"; |
168 | 20 | else if (!Is64Bit) |
169 | 11 | AsmMnemonic = "uxth"; |
170 | 438 | break; |
171 | | |
172 | 1.05k | case 31: |
173 | | // *xtw is only valid for signed 64-bit operations. |
174 | 1.05k | if (Is64Bit && IsSigned) |
175 | 908 | AsmMnemonic = "sxtw"; |
176 | 1.05k | break; |
177 | 4.07k | } |
178 | | |
179 | 4.07k | if (AsmMnemonic) { |
180 | 2.95k | SStream_concat(O, "%s\t%s, %s", AsmMnemonic, |
181 | 2.95k | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
182 | 2.95k | getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName)); |
183 | | |
184 | 2.95k | if (MI->csh->detail) { |
185 | 2.95k | #ifndef CAPSTONE_DIET |
186 | 2.95k | uint8_t access; |
187 | 2.95k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
188 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
189 | 2.95k | MI->ac_idx++; |
190 | 2.95k | #endif |
191 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
192 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
193 | 2.95k | MI->flat_insn->detail->arm64.op_count++; |
194 | 2.95k | #ifndef CAPSTONE_DIET |
195 | 2.95k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
196 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
197 | 2.95k | MI->ac_idx++; |
198 | 2.95k | #endif |
199 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
200 | 2.95k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1)); |
201 | 2.95k | MI->flat_insn->detail->arm64.op_count++; |
202 | 2.95k | } |
203 | | |
204 | 2.95k | MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); |
205 | | |
206 | 2.95k | return; |
207 | 2.95k | } |
208 | 4.07k | } |
209 | | |
210 | | // All immediate shifts are aliases, implemented using the Bitfield |
211 | | // instruction. In all cases the immediate shift amount shift must be in |
212 | | // the range 0 to (reg.size -1). |
213 | 1.94k | if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { |
214 | 1.94k | const char *AsmMnemonic = NULL; |
215 | 1.94k | int shift = 0; |
216 | 1.94k | int immr = (int)MCOperand_getImm(Op2); |
217 | 1.94k | int imms = (int)MCOperand_getImm(Op3); |
218 | | |
219 | 1.94k | if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { |
220 | 19 | AsmMnemonic = "lsl"; |
221 | 19 | shift = 31 - imms; |
222 | 1.92k | } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && |
223 | 1.92k | ((imms + 1 == immr))) { |
224 | 13 | AsmMnemonic = "lsl"; |
225 | 13 | shift = 63 - imms; |
226 | 1.91k | } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { |
227 | 14 | AsmMnemonic = "lsr"; |
228 | 14 | shift = immr; |
229 | 1.90k | } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { |
230 | 9 | AsmMnemonic = "lsr"; |
231 | 9 | shift = immr; |
232 | 1.89k | } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { |
233 | 4 | AsmMnemonic = "asr"; |
234 | 4 | shift = immr; |
235 | 1.88k | } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { |
236 | 14 | AsmMnemonic = "asr"; |
237 | 14 | shift = immr; |
238 | 14 | } |
239 | | |
240 | 1.94k | if (AsmMnemonic) { |
241 | 73 | SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic, |
242 | 73 | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
243 | 73 | getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); |
244 | | |
245 | 73 | printInt32Bang(O, shift); |
246 | | |
247 | 73 | MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); |
248 | | |
249 | 73 | if (MI->csh->detail) { |
250 | 73 | #ifndef CAPSTONE_DIET |
251 | 73 | uint8_t access; |
252 | 73 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
253 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
254 | 73 | MI->ac_idx++; |
255 | 73 | #endif |
256 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
257 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
258 | 73 | MI->flat_insn->detail->arm64.op_count++; |
259 | 73 | #ifndef CAPSTONE_DIET |
260 | 73 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
261 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
262 | 73 | MI->ac_idx++; |
263 | 73 | #endif |
264 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
265 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); |
266 | 73 | MI->flat_insn->detail->arm64.op_count++; |
267 | 73 | #ifndef CAPSTONE_DIET |
268 | 73 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
269 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
270 | 73 | MI->ac_idx++; |
271 | 73 | #endif |
272 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
273 | 73 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; |
274 | 73 | MI->flat_insn->detail->arm64.op_count++; |
275 | 73 | } |
276 | | |
277 | 73 | return; |
278 | 73 | } |
279 | 1.94k | } |
280 | | |
281 | | // SBFIZ/UBFIZ aliases |
282 | 1.87k | if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { |
283 | 654 | SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), |
284 | 654 | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
285 | 654 | getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); |
286 | | |
287 | 654 | printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); |
288 | | |
289 | 654 | SStream_concat0(O, ", "); |
290 | | |
291 | 654 | printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); |
292 | | |
293 | 654 | MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); |
294 | | |
295 | 654 | if (MI->csh->detail) { |
296 | 654 | #ifndef CAPSTONE_DIET |
297 | 654 | uint8_t access; |
298 | 654 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
299 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
300 | 654 | MI->ac_idx++; |
301 | 654 | #endif |
302 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
303 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
304 | 654 | MI->flat_insn->detail->arm64.op_count++; |
305 | 654 | #ifndef CAPSTONE_DIET |
306 | 654 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
307 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
308 | 654 | MI->ac_idx++; |
309 | 654 | #endif |
310 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
311 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); |
312 | 654 | MI->flat_insn->detail->arm64.op_count++; |
313 | 654 | #ifndef CAPSTONE_DIET |
314 | 654 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
315 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
316 | 654 | MI->ac_idx++; |
317 | 654 | #endif |
318 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
319 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); |
320 | 654 | MI->flat_insn->detail->arm64.op_count++; |
321 | 654 | #ifndef CAPSTONE_DIET |
322 | 654 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
323 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
324 | 654 | MI->ac_idx++; |
325 | 654 | #endif |
326 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
327 | 654 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; |
328 | 654 | MI->flat_insn->detail->arm64.op_count++; |
329 | 654 | } |
330 | | |
331 | 654 | return; |
332 | 654 | } |
333 | | |
334 | | // Otherwise SBFX/UBFX is the preferred form |
335 | 1.21k | SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), |
336 | 1.21k | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
337 | 1.21k | getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); |
338 | | |
339 | 1.21k | printInt32Bang(O, (int)MCOperand_getImm(Op2)); |
340 | 1.21k | SStream_concat0(O, ", "); |
341 | 1.21k | printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); |
342 | | |
343 | 1.21k | MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); |
344 | | |
345 | 1.21k | if (MI->csh->detail) { |
346 | 1.21k | #ifndef CAPSTONE_DIET |
347 | 1.21k | uint8_t access; |
348 | 1.21k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
349 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
350 | 1.21k | MI->ac_idx++; |
351 | 1.21k | #endif |
352 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
353 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
354 | 1.21k | MI->flat_insn->detail->arm64.op_count++; |
355 | 1.21k | #ifndef CAPSTONE_DIET |
356 | 1.21k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
357 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
358 | 1.21k | MI->ac_idx++; |
359 | 1.21k | #endif |
360 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
361 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); |
362 | 1.21k | MI->flat_insn->detail->arm64.op_count++; |
363 | 1.21k | #ifndef CAPSTONE_DIET |
364 | 1.21k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
365 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
366 | 1.21k | MI->ac_idx++; |
367 | 1.21k | #endif |
368 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
369 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2); |
370 | 1.21k | MI->flat_insn->detail->arm64.op_count++; |
371 | 1.21k | #ifndef CAPSTONE_DIET |
372 | 1.21k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
373 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
374 | 1.21k | MI->ac_idx++; |
375 | 1.21k | #endif |
376 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
377 | 1.21k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; |
378 | 1.21k | MI->flat_insn->detail->arm64.op_count++; |
379 | 1.21k | } |
380 | | |
381 | 1.21k | return; |
382 | 1.87k | } |
383 | | |
384 | 174k | if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { |
385 | 159 | MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 |
386 | 159 | MCOperand *Op2 = MCInst_getOperand(MI, 2); |
387 | 159 | int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); |
388 | 159 | int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); |
389 | | |
390 | 159 | if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) && |
391 | 159 | (ImmR == 0 || ImmS < ImmR)) { |
392 | | // BFC takes precedence over its entire range, sligtly differently to BFI. |
393 | 42 | int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; |
394 | 42 | int LSB = (BitWidth - ImmR) % BitWidth; |
395 | 42 | int Width = ImmS + 1; |
396 | | |
397 | 42 | SStream_concat(O, "bfc\t%s, ", |
398 | 42 | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName)); |
399 | | |
400 | 42 | printInt32Bang(O, LSB); |
401 | 42 | SStream_concat0(O, ", "); |
402 | 42 | printInt32Bang(O, Width); |
403 | 42 | MCInst_setOpcodePub(MI, AArch64_map_insn("bfc")); |
404 | | |
405 | 42 | if (MI->csh->detail) { |
406 | 42 | #ifndef CAPSTONE_DIET |
407 | 42 | uint8_t access; |
408 | 42 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
409 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
410 | 42 | MI->ac_idx++; |
411 | 42 | #endif |
412 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
413 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
414 | 42 | MI->flat_insn->detail->arm64.op_count++; |
415 | | |
416 | 42 | #ifndef CAPSTONE_DIET |
417 | 42 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
418 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
419 | 42 | MI->ac_idx++; |
420 | 42 | #endif |
421 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
422 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; |
423 | 42 | MI->flat_insn->detail->arm64.op_count++; |
424 | 42 | #ifndef CAPSTONE_DIET |
425 | 42 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
426 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
427 | 42 | MI->ac_idx++; |
428 | 42 | #endif |
429 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
430 | 42 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; |
431 | 42 | MI->flat_insn->detail->arm64.op_count++; |
432 | 42 | } |
433 | | |
434 | 42 | return; |
435 | 117 | } else if (ImmS < ImmR) { |
436 | | // BFI alias |
437 | 48 | int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; |
438 | 48 | LSB = (BitWidth - ImmR) % BitWidth; |
439 | 48 | Width = ImmS + 1; |
440 | | |
441 | 48 | SStream_concat(O, "bfi\t%s, %s, ", |
442 | 48 | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
443 | 48 | getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); |
444 | | |
445 | 48 | printInt32Bang(O, LSB); |
446 | 48 | SStream_concat0(O, ", "); |
447 | 48 | printInt32Bang(O, Width); |
448 | | |
449 | 48 | MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); |
450 | | |
451 | 48 | if (MI->csh->detail) { |
452 | 48 | #ifndef CAPSTONE_DIET |
453 | 48 | uint8_t access; |
454 | 48 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
455 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
456 | 48 | MI->ac_idx++; |
457 | 48 | #endif |
458 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
459 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
460 | 48 | MI->flat_insn->detail->arm64.op_count++; |
461 | 48 | #ifndef CAPSTONE_DIET |
462 | 48 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
463 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
464 | 48 | MI->ac_idx++; |
465 | 48 | #endif |
466 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
467 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); |
468 | 48 | MI->flat_insn->detail->arm64.op_count++; |
469 | 48 | #ifndef CAPSTONE_DIET |
470 | 48 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
471 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
472 | 48 | MI->ac_idx++; |
473 | 48 | #endif |
474 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
475 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; |
476 | 48 | MI->flat_insn->detail->arm64.op_count++; |
477 | 48 | #ifndef CAPSTONE_DIET |
478 | 48 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
479 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
480 | 48 | MI->ac_idx++; |
481 | 48 | #endif |
482 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
483 | 48 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; |
484 | 48 | MI->flat_insn->detail->arm64.op_count++; |
485 | 48 | } |
486 | | |
487 | 48 | return; |
488 | 48 | } |
489 | | |
490 | 69 | LSB = ImmR; |
491 | 69 | Width = ImmS - ImmR + 1; |
492 | | // Otherwise BFXIL the preferred form |
493 | 69 | SStream_concat(O, "bfxil\t%s, %s, ", |
494 | 69 | getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), |
495 | 69 | getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); |
496 | | |
497 | 69 | printInt32Bang(O, LSB); |
498 | 69 | SStream_concat0(O, ", "); |
499 | 69 | printInt32Bang(O, Width); |
500 | | |
501 | 69 | MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); |
502 | | |
503 | 69 | if (MI->csh->detail) { |
504 | 69 | #ifndef CAPSTONE_DIET |
505 | 69 | uint8_t access; |
506 | 69 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
507 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
508 | 69 | MI->ac_idx++; |
509 | 69 | #endif |
510 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
511 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); |
512 | 69 | MI->flat_insn->detail->arm64.op_count++; |
513 | 69 | #ifndef CAPSTONE_DIET |
514 | 69 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
515 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
516 | 69 | MI->ac_idx++; |
517 | 69 | #endif |
518 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
519 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); |
520 | 69 | MI->flat_insn->detail->arm64.op_count++; |
521 | 69 | #ifndef CAPSTONE_DIET |
522 | 69 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
523 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
524 | 69 | MI->ac_idx++; |
525 | 69 | #endif |
526 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
527 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; |
528 | 69 | MI->flat_insn->detail->arm64.op_count++; |
529 | 69 | #ifndef CAPSTONE_DIET |
530 | 69 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
531 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
532 | 69 | MI->ac_idx++; |
533 | 69 | #endif |
534 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
535 | 69 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; |
536 | 69 | MI->flat_insn->detail->arm64.op_count++; |
537 | 69 | } |
538 | | |
539 | 69 | return; |
540 | 159 | } |
541 | | |
542 | | // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their |
543 | | // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > |
544 | | // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction |
545 | | // that can represent the move is the MOV alias, and the rest get printed |
546 | | // normally. |
547 | 174k | if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && |
548 | 174k | MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { |
549 | 607 | int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; |
550 | 607 | int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); |
551 | 607 | uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift; |
552 | | |
553 | 607 | if (isMOVZMovAlias(Value, Shift, |
554 | 607 | Opcode == AArch64_MOVZXi ? 64 : 32)) { |
555 | 600 | SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); |
556 | | |
557 | 600 | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
558 | | |
559 | 600 | if (MI->csh->detail) { |
560 | 600 | #ifndef CAPSTONE_DIET |
561 | 600 | uint8_t access; |
562 | 600 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
563 | 600 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
564 | 600 | MI->ac_idx++; |
565 | 600 | #endif |
566 | 600 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
567 | 600 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
568 | 600 | MI->flat_insn->detail->arm64.op_count++; |
569 | | |
570 | 600 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
571 | 600 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); |
572 | 600 | MI->flat_insn->detail->arm64.op_count++; |
573 | 600 | } |
574 | | |
575 | 600 | MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); |
576 | | |
577 | 600 | return; |
578 | 600 | } |
579 | 607 | } |
580 | | |
581 | 173k | if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && |
582 | 173k | MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { |
583 | 1.64k | int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; |
584 | 1.64k | int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); |
585 | 1.64k | uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift); |
586 | | |
587 | 1.64k | if (RegWidth == 32) |
588 | 72 | Value = Value & 0xffffffff; |
589 | | |
590 | 1.64k | if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { |
591 | 1.60k | SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); |
592 | | |
593 | 1.60k | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
594 | | |
595 | 1.60k | if (MI->csh->detail) { |
596 | 1.60k | #ifndef CAPSTONE_DIET |
597 | 1.60k | uint8_t access; |
598 | 1.60k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
599 | 1.60k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
600 | 1.60k | MI->ac_idx++; |
601 | 1.60k | #endif |
602 | 1.60k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
603 | 1.60k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
604 | 1.60k | MI->flat_insn->detail->arm64.op_count++; |
605 | | |
606 | 1.60k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
607 | 1.60k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); |
608 | 1.60k | MI->flat_insn->detail->arm64.op_count++; |
609 | 1.60k | } |
610 | | |
611 | 1.60k | MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); |
612 | | |
613 | 1.60k | return; |
614 | 1.60k | } |
615 | 1.64k | } |
616 | | |
617 | 171k | if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && |
618 | 171k | (MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR || |
619 | 622 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) && |
620 | 171k | MCOperand_isImm(MCInst_getOperand(MI, 2))) { |
621 | 127 | int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; |
622 | 127 | uint64_t Value = AArch64_AM_decodeLogicalImmediate( |
623 | 127 | MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth); |
624 | 127 | SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); |
625 | | |
626 | 127 | printInt64Bang(O, SignExtend64(Value, RegWidth)); |
627 | | |
628 | 127 | if (MI->csh->detail) { |
629 | 127 | #ifndef CAPSTONE_DIET |
630 | 127 | uint8_t access; |
631 | 127 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
632 | 127 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
633 | 127 | MI->ac_idx++; |
634 | 127 | #endif |
635 | 127 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
636 | 127 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
637 | 127 | MI->flat_insn->detail->arm64.op_count++; |
638 | | |
639 | 127 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
640 | 127 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); |
641 | 127 | MI->flat_insn->detail->arm64.op_count++; |
642 | 127 | } |
643 | | |
644 | 127 | MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); |
645 | | |
646 | 127 | return; |
647 | 127 | } |
648 | | |
649 | | // Instruction TSB is specified as a one operand instruction, but 'csync' is |
650 | | // not encoded, so for printing it is treated as a special case here: |
651 | 171k | if (Opcode == AArch64_TSB) { |
652 | 53 | SStream_concat0(O, "tsb\tcsync"); |
653 | 53 | MCInst_setOpcodePub(MI, AArch64_map_insn("tsb")); |
654 | 53 | return; |
655 | 53 | } |
656 | | |
657 | 171k | MI->MRI = Info; |
658 | | |
659 | 171k | mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info); |
660 | 171k | if (mnem) { |
661 | 24.1k | MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); |
662 | 24.1k | cs_mem_free(mnem); |
663 | | |
664 | 24.1k | switch(MCInst_getOpcode(MI)) { |
665 | 16.8k | default: break; |
666 | 16.8k | case AArch64_LD1i8_POST: |
667 | 106 | arm64_op_addImm(MI, 1); |
668 | 106 | break; |
669 | 23 | case AArch64_LD1i16_POST: |
670 | 23 | arm64_op_addImm(MI, 2); |
671 | 23 | break; |
672 | 97 | case AArch64_LD1i32_POST: |
673 | 97 | arm64_op_addImm(MI, 4); |
674 | 97 | break; |
675 | 13 | case AArch64_LD1Onev1d_POST: |
676 | 82 | case AArch64_LD1Onev2s_POST: |
677 | 140 | case AArch64_LD1Onev4h_POST: |
678 | 214 | case AArch64_LD1Onev8b_POST: |
679 | 256 | case AArch64_LD1i64_POST: |
680 | 256 | arm64_op_addImm(MI, 8); |
681 | 256 | break; |
682 | 14 | case AArch64_LD1Onev16b_POST: |
683 | 28 | case AArch64_LD1Onev2d_POST: |
684 | 94 | case AArch64_LD1Onev4s_POST: |
685 | 190 | case AArch64_LD1Onev8h_POST: |
686 | 209 | case AArch64_LD1Twov1d_POST: |
687 | 219 | case AArch64_LD1Twov2s_POST: |
688 | 254 | case AArch64_LD1Twov4h_POST: |
689 | 597 | case AArch64_LD1Twov8b_POST: |
690 | 597 | arm64_op_addImm(MI, 16); |
691 | 597 | break; |
692 | 28 | case AArch64_LD1Threev1d_POST: |
693 | 179 | case AArch64_LD1Threev2s_POST: |
694 | 778 | case AArch64_LD1Threev4h_POST: |
695 | 843 | case AArch64_LD1Threev8b_POST: |
696 | 843 | arm64_op_addImm(MI, 24); |
697 | 843 | break; |
698 | 26 | case AArch64_LD1Fourv1d_POST: |
699 | 97 | case AArch64_LD1Fourv2s_POST: |
700 | 133 | case AArch64_LD1Fourv4h_POST: |
701 | 158 | case AArch64_LD1Fourv8b_POST: |
702 | 176 | case AArch64_LD1Twov16b_POST: |
703 | 250 | case AArch64_LD1Twov2d_POST: |
704 | 362 | case AArch64_LD1Twov4s_POST: |
705 | 386 | case AArch64_LD1Twov8h_POST: |
706 | 386 | arm64_op_addImm(MI, 32); |
707 | 386 | break; |
708 | 59 | case AArch64_LD1Threev16b_POST: |
709 | 172 | case AArch64_LD1Threev2d_POST: |
710 | 446 | case AArch64_LD1Threev4s_POST: |
711 | 508 | case AArch64_LD1Threev8h_POST: |
712 | 508 | arm64_op_addImm(MI, 48); |
713 | 508 | break; |
714 | 21 | case AArch64_LD1Fourv16b_POST: |
715 | 101 | case AArch64_LD1Fourv2d_POST: |
716 | 190 | case AArch64_LD1Fourv4s_POST: |
717 | 736 | case AArch64_LD1Fourv8h_POST: |
718 | 736 | arm64_op_addImm(MI, 64); |
719 | 736 | break; |
720 | 29 | case AArch64_UMOVvi64: |
721 | 29 | arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); |
722 | 29 | break; |
723 | 11 | case AArch64_UMOVvi32: |
724 | 11 | arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); |
725 | 11 | break; |
726 | 16 | case AArch64_INSvi8gpr: |
727 | 40 | case AArch64_DUP_ZI_B: |
728 | 93 | case AArch64_CPY_ZPmI_B: |
729 | 110 | case AArch64_CPY_ZPzI_B: |
730 | 207 | case AArch64_CPY_ZPmV_B: |
731 | 230 | case AArch64_CPY_ZPmR_B: |
732 | 245 | case AArch64_DUP_ZR_B: |
733 | 245 | if (MI->csh->detail) { |
734 | 245 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B; |
735 | 245 | } |
736 | 245 | break; |
737 | 58 | case AArch64_INSvi16gpr: |
738 | 90 | case AArch64_DUP_ZI_H: |
739 | 106 | case AArch64_CPY_ZPmI_H: |
740 | 138 | case AArch64_CPY_ZPzI_H: |
741 | 150 | case AArch64_CPY_ZPmV_H: |
742 | 170 | case AArch64_CPY_ZPmR_H: |
743 | 240 | case AArch64_DUP_ZR_H: |
744 | 250 | case AArch64_FCPY_ZPmI_H: |
745 | 433 | case AArch64_FDUP_ZI_H: |
746 | 433 | if (MI->csh->detail) { |
747 | 433 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H; |
748 | 433 | } |
749 | 433 | break; |
750 | 32 | case AArch64_INSvi32gpr: |
751 | 38 | case AArch64_DUP_ZI_S: |
752 | 54 | case AArch64_CPY_ZPmI_S: |
753 | 123 | case AArch64_CPY_ZPzI_S: |
754 | 136 | case AArch64_CPY_ZPmV_S: |
755 | 353 | case AArch64_CPY_ZPmR_S: |
756 | 523 | case AArch64_DUP_ZR_S: |
757 | 606 | case AArch64_FCPY_ZPmI_S: |
758 | 616 | case AArch64_FDUP_ZI_S: |
759 | 616 | if (MI->csh->detail) { |
760 | 616 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S; |
761 | 616 | } |
762 | 616 | break; |
763 | 32 | case AArch64_INSvi64gpr: |
764 | 40 | case AArch64_DUP_ZI_D: |
765 | 143 | case AArch64_CPY_ZPmI_D: |
766 | 863 | case AArch64_CPY_ZPzI_D: |
767 | 879 | case AArch64_CPY_ZPmV_D: |
768 | 906 | case AArch64_CPY_ZPmR_D: |
769 | 953 | case AArch64_DUP_ZR_D: |
770 | 992 | case AArch64_FCPY_ZPmI_D: |
771 | 1.00k | case AArch64_FDUP_ZI_D: |
772 | 1.00k | if (MI->csh->detail) { |
773 | 1.00k | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D; |
774 | 1.00k | } |
775 | 1.00k | break; |
776 | 93 | case AArch64_INSvi8lane: |
777 | 356 | case AArch64_ORR_PPzPP: |
778 | 386 | case AArch64_ORRS_PPzPP: |
779 | 386 | if (MI->csh->detail) { |
780 | 386 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B; |
781 | 386 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B; |
782 | 386 | } |
783 | 386 | break; |
784 | 12 | case AArch64_INSvi16lane: |
785 | 12 | if (MI->csh->detail) { |
786 | 12 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H; |
787 | 12 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H; |
788 | 12 | } |
789 | 12 | break; |
790 | 321 | case AArch64_INSvi32lane: |
791 | 321 | if (MI->csh->detail) { |
792 | 321 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S; |
793 | 321 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S; |
794 | 321 | } |
795 | 321 | break; |
796 | 10 | case AArch64_INSvi64lane: |
797 | 20 | case AArch64_ORR_ZZZ: |
798 | 20 | if (MI->csh->detail) { |
799 | 20 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D; |
800 | 20 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D; |
801 | 20 | } |
802 | 20 | break; |
803 | 12 | case AArch64_ORRv16i8: |
804 | 31 | case AArch64_NOTv16i8: |
805 | 31 | if (MI->csh->detail) { |
806 | 31 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_16B; |
807 | 31 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_16B; |
808 | 31 | } |
809 | 31 | break; |
810 | 5 | case AArch64_ORRv8i8: |
811 | 77 | case AArch64_NOTv8i8: |
812 | 77 | if (MI->csh->detail) { |
813 | 77 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_8B; |
814 | 77 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_8B; |
815 | 77 | } |
816 | 77 | break; |
817 | 14 | case AArch64_AND_PPzPP: |
818 | 18 | case AArch64_ANDS_PPzPP: |
819 | 30 | case AArch64_EOR_PPzPP: |
820 | 37 | case AArch64_EORS_PPzPP: |
821 | 120 | case AArch64_SEL_PPPP: |
822 | 132 | case AArch64_SEL_ZPZZ_B: |
823 | 132 | if (MI->csh->detail) { |
824 | 132 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B; |
825 | 132 | MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1B; |
826 | 132 | } |
827 | 132 | break; |
828 | 106 | case AArch64_SEL_ZPZZ_D: |
829 | 106 | if (MI->csh->detail) { |
830 | 106 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D; |
831 | 106 | MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1D; |
832 | 106 | } |
833 | 106 | break; |
834 | 27 | case AArch64_SEL_ZPZZ_H: |
835 | 27 | if (MI->csh->detail) { |
836 | 27 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H; |
837 | 27 | MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1H; |
838 | 27 | } |
839 | 27 | break; |
840 | 145 | case AArch64_SEL_ZPZZ_S: |
841 | 145 | if (MI->csh->detail) { |
842 | 145 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S; |
843 | 145 | MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1S; |
844 | 145 | } |
845 | 145 | break; |
846 | 13 | case AArch64_DUP_ZZI_B: |
847 | 13 | if (MI->csh->detail) { |
848 | 13 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B; |
849 | 13 | if (MI->flat_insn->detail->arm64.op_count == 1) { |
850 | 0 | arm64_op_addReg(MI, ARM64_REG_B0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0); |
851 | 13 | } else { |
852 | 13 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B; |
853 | 13 | } |
854 | 13 | } |
855 | 13 | break; |
856 | 20 | case AArch64_DUP_ZZI_D: |
857 | 20 | if (MI->csh->detail) { |
858 | 20 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D; |
859 | 20 | if (MI->flat_insn->detail->arm64.op_count == 1) { |
860 | 0 | arm64_op_addReg(MI, ARM64_REG_D0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0); |
861 | 20 | } else { |
862 | 20 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D; |
863 | 20 | } |
864 | 20 | } |
865 | 20 | break; |
866 | 14 | case AArch64_DUP_ZZI_H: |
867 | 14 | if (MI->csh->detail) { |
868 | 14 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H; |
869 | 14 | if (MI->flat_insn->detail->arm64.op_count == 1) { |
870 | 0 | arm64_op_addReg(MI, ARM64_REG_H0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0); |
871 | 14 | } else { |
872 | 14 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H; |
873 | 14 | } |
874 | 14 | } |
875 | 14 | break; |
876 | 7 | case AArch64_DUP_ZZI_Q: |
877 | 7 | if (MI->csh->detail) { |
878 | 7 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1Q; |
879 | 7 | if (MI->flat_insn->detail->arm64.op_count == 1) { |
880 | 0 | arm64_op_addReg(MI, ARM64_REG_Q0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0); |
881 | 7 | } else { |
882 | 7 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1Q; |
883 | 7 | } |
884 | 7 | } |
885 | 7 | break; |
886 | 37 | case AArch64_DUP_ZZI_S: |
887 | 37 | if (MI->csh->detail) { |
888 | 37 | MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S; |
889 | 37 | if (MI->flat_insn->detail->arm64.op_count == 1) { |
890 | 0 | arm64_op_addReg(MI, ARM64_REG_S0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0); |
891 | 37 | } else { |
892 | 37 | MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S; |
893 | 37 | } |
894 | 37 | } |
895 | 37 | break; |
896 | | // Hacky detail filling of SMSTART and SMSTOP alias' |
897 | 27 | case AArch64_MSRpstatesvcrImm1:{ |
898 | 27 | if(MI->csh->detail){ |
899 | 27 | MI->flat_insn->detail->arm64.op_count = 2; |
900 | 27 | #ifndef CAPSTONE_DIET |
901 | 27 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
902 | 27 | MI->ac_idx++; |
903 | 27 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
904 | 27 | MI->ac_idx++; |
905 | 27 | #endif |
906 | 27 | MI->flat_insn->detail->arm64.operands[0].type = ARM64_OP_SVCR; |
907 | 27 | MI->flat_insn->detail->arm64.operands[0].sys = (unsigned)ARM64_SYSREG_SVCR; |
908 | 27 | MI->flat_insn->detail->arm64.operands[0].svcr = lookupSVCRByEncoding(MCOperand_getImm(MCInst_getOperand(MI, 0)))->Encoding; |
909 | 27 | MI->flat_insn->detail->arm64.operands[1].type = ARM64_OP_IMM; |
910 | 27 | MI->flat_insn->detail->arm64.operands[1].imm = MCOperand_getImm(MCInst_getOperand(MI, 1)); |
911 | 27 | } |
912 | 27 | break; |
913 | 120 | } |
914 | 24.1k | } |
915 | 147k | } else { |
916 | 147k | printInstruction(MI, O); |
917 | 147k | } |
918 | 171k | } |
919 | | |
920 | | static bool printSysAlias(MCInst *MI, SStream *O) |
921 | 2.30k | { |
922 | | // unsigned Opcode = MCInst_getOpcode(MI); |
923 | | //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); |
924 | | |
925 | 2.30k | const char *Ins; |
926 | 2.30k | uint16_t Encoding; |
927 | 2.30k | bool NeedsReg; |
928 | 2.30k | char Name[64]; |
929 | 2.30k | MCOperand *Op1 = MCInst_getOperand(MI, 0); |
930 | 2.30k | MCOperand *Cn = MCInst_getOperand(MI, 1); |
931 | 2.30k | MCOperand *Cm = MCInst_getOperand(MI, 2); |
932 | 2.30k | MCOperand *Op2 = MCInst_getOperand(MI, 3); |
933 | | |
934 | 2.30k | unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); |
935 | 2.30k | unsigned CnVal = (unsigned)MCOperand_getImm(Cn); |
936 | 2.30k | unsigned CmVal = (unsigned)MCOperand_getImm(Cm); |
937 | 2.30k | unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); |
938 | | |
939 | 2.30k | Encoding = Op2Val; |
940 | 2.30k | Encoding |= CmVal << 3; |
941 | 2.30k | Encoding |= CnVal << 7; |
942 | 2.30k | Encoding |= Op1Val << 11; |
943 | | |
944 | 2.30k | if (CnVal == 7) { |
945 | 1.99k | switch (CmVal) { |
946 | 8 | default: |
947 | 8 | return false; |
948 | | |
949 | | // IC aliases |
950 | 217 | case 1: case 5: { |
951 | 217 | const IC *IC = lookupICByEncoding(Encoding); |
952 | | // if (!IC || !IC->haveFeatures(STI.getFeatureBits())) |
953 | 217 | if (!IC) |
954 | 188 | return false; |
955 | | |
956 | 29 | NeedsReg = IC->NeedsReg; |
957 | 29 | Ins = "ic"; |
958 | 29 | strncpy(Name, IC->Name, sizeof(Name) - 1); |
959 | 29 | } |
960 | 0 | break; |
961 | | |
962 | | // DC aliases |
963 | 716 | case 4: case 6: case 10: case 11: case 12: case 14: { |
964 | 716 | const DC *DC = lookupDCByEncoding(Encoding); |
965 | | // if (!DC || !DC->haveFeatures(STI.getFeatureBits())) |
966 | 716 | if (!DC) |
967 | 645 | return false; |
968 | | |
969 | 71 | NeedsReg = true; |
970 | 71 | Ins = "dc"; |
971 | 71 | strncpy(Name, DC->Name, sizeof(Name) - 1); |
972 | 71 | } |
973 | 0 | break; |
974 | | |
975 | | // AT aliases |
976 | 1.05k | case 8: case 9: { |
977 | 1.05k | const AT *AT = lookupATByEncoding(Encoding); |
978 | | // if (!AT || !AT->haveFeatures(STI.getFeatureBits())) |
979 | 1.05k | if (!AT) |
980 | 138 | return false; |
981 | | |
982 | 919 | NeedsReg = true; |
983 | 919 | Ins = "at"; |
984 | 919 | strncpy(Name, AT->Name, sizeof(Name) - 1); |
985 | 919 | } |
986 | 0 | break; |
987 | 1.99k | } |
988 | 1.99k | } else if (CnVal == 8) { |
989 | | // TLBI aliases |
990 | 76 | const TLBI *TLBI = lookupTLBIByEncoding(Encoding); |
991 | | // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) |
992 | 76 | if (!TLBI) |
993 | 30 | return false; |
994 | | |
995 | 46 | NeedsReg = TLBI->NeedsReg; |
996 | 46 | Ins = "tlbi"; |
997 | 46 | strncpy(Name, TLBI->Name, sizeof(Name) - 1); |
998 | 46 | } else |
999 | 229 | return false; |
1000 | | |
1001 | 1.06k | SStream_concat(O, "%s\t%s", Ins, Name); |
1002 | | |
1003 | 1.06k | if (NeedsReg) { |
1004 | 1.01k | SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName)); |
1005 | 1.01k | } |
1006 | | |
1007 | 1.06k | MCInst_setOpcodePub(MI, AArch64_map_insn(Ins)); |
1008 | | |
1009 | 1.06k | if (MI->csh->detail) { |
1010 | | #if 0 |
1011 | | #ifndef CAPSTONE_DIET |
1012 | | uint8_t access; |
1013 | | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1014 | | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1015 | | MI->ac_idx++; |
1016 | | #endif |
1017 | | #endif |
1018 | 1.06k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
1019 | 1.06k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = AArch64_map_sys_op(Name); |
1020 | 1.06k | MI->flat_insn->detail->arm64.op_count++; |
1021 | | |
1022 | 1.06k | if (NeedsReg) { |
1023 | 1.01k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1024 | 1.01k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); |
1025 | 1.01k | MI->flat_insn->detail->arm64.op_count++; |
1026 | 1.01k | } |
1027 | 1.06k | } |
1028 | | |
1029 | 1.06k | return true; |
1030 | 2.30k | } |
1031 | | |
1032 | | static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) |
1033 | 253k | { |
1034 | 253k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1035 | | |
1036 | 253k | if (MCOperand_isReg(Op)) { |
1037 | 216k | unsigned Reg = MCOperand_getReg(Op); |
1038 | | |
1039 | 216k | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
1040 | | |
1041 | 216k | if (MI->csh->detail) { |
1042 | 216k | if (MI->csh->doing_mem) { |
1043 | 85.5k | if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { |
1044 | 73.7k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; |
1045 | 73.7k | } |
1046 | 11.8k | else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) { |
1047 | 11.8k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; |
1048 | 11.8k | } |
1049 | 130k | } else if (MI->csh->doing_SME_Index) { |
1050 | | // Access op_count-1 as We want to add info to previous operand, not create a new one |
1051 | 3.29k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.base = Reg; |
1052 | 127k | } else { |
1053 | 127k | #ifndef CAPSTONE_DIET |
1054 | 127k | uint8_t access; |
1055 | | |
1056 | 127k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1057 | 127k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1058 | 127k | MI->ac_idx++; |
1059 | 127k | #endif |
1060 | 127k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1061 | 127k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
1062 | 127k | MI->flat_insn->detail->arm64.op_count++; |
1063 | 127k | } |
1064 | 216k | } |
1065 | 216k | } else if (MCOperand_isImm(Op)) { |
1066 | 37.2k | int64_t imm = MCOperand_getImm(Op); |
1067 | | |
1068 | 37.2k | if (MI->Opcode == AArch64_ADR) { |
1069 | 3.00k | imm += MI->address; |
1070 | 3.00k | printUInt64Bang(O, imm); |
1071 | 34.1k | } else { |
1072 | 34.1k | if (MI->csh->doing_mem) { |
1073 | 7.81k | if (MI->csh->imm_unsigned) { |
1074 | 0 | printUInt64Bang(O, imm); |
1075 | 7.81k | } else { |
1076 | 7.81k | printInt64Bang(O, imm); |
1077 | 7.81k | } |
1078 | 7.81k | } else |
1079 | 26.3k | printUInt64Bang(O, imm); |
1080 | 34.1k | } |
1081 | | |
1082 | 37.2k | if (MI->csh->detail) { |
1083 | 37.2k | if (MI->csh->doing_mem) { |
1084 | 7.81k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm; |
1085 | 29.3k | } else if (MI->csh->doing_SME_Index) { |
1086 | | // Access op_count-1 as We want to add info to previous operand, not create a new one |
1087 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = (int32_t)imm; |
1088 | 29.3k | } else { |
1089 | 29.3k | #ifndef CAPSTONE_DIET |
1090 | 29.3k | uint8_t access; |
1091 | | |
1092 | 29.3k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1093 | 29.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1094 | 29.3k | #endif |
1095 | 29.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1096 | 29.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; |
1097 | 29.3k | MI->flat_insn->detail->arm64.op_count++; |
1098 | 29.3k | } |
1099 | 37.2k | } |
1100 | 37.2k | } |
1101 | 253k | } |
1102 | | |
1103 | | static void printImm(MCInst *MI, unsigned OpNum, SStream *O) |
1104 | 2.86k | { |
1105 | 2.86k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1106 | 2.86k | printUInt64Bang(O, MCOperand_getImm(Op)); |
1107 | | |
1108 | 2.86k | if (MI->csh->detail) { |
1109 | 2.86k | #ifndef CAPSTONE_DIET |
1110 | 2.86k | uint8_t access; |
1111 | 2.86k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1112 | 2.86k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1113 | 2.86k | MI->ac_idx++; |
1114 | 2.86k | #endif |
1115 | 2.86k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1116 | 2.86k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); |
1117 | 2.86k | MI->flat_insn->detail->arm64.op_count++; |
1118 | 2.86k | } |
1119 | 2.86k | } |
1120 | | |
1121 | | static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) |
1122 | 15 | { |
1123 | 15 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1124 | 15 | printUInt64Bang(O, MCOperand_getImm(Op)); |
1125 | | |
1126 | 15 | if (MI->csh->detail) { |
1127 | 15 | #ifndef CAPSTONE_DIET |
1128 | 15 | uint8_t access; |
1129 | 15 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1130 | 15 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1131 | 15 | MI->ac_idx++; |
1132 | 15 | #endif |
1133 | 15 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1134 | 15 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); |
1135 | 15 | MI->flat_insn->detail->arm64.op_count++; |
1136 | 15 | } |
1137 | 15 | } |
1138 | | |
1139 | 1.27k | static void printSImm(MCInst *MI, unsigned OpNo, SStream *O, int Size) { |
1140 | 1.27k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
1141 | 1.27k | if (Size == 8) |
1142 | 151 | printInt64Bang(O, (signed char) MCOperand_getImm(Op)); |
1143 | 1.12k | else if (Size == 16) |
1144 | 1.12k | printInt64Bang(O, (signed short) MCOperand_getImm(Op)); |
1145 | 0 | else |
1146 | 0 | printInt64Bang(O, MCOperand_getImm(Op)); |
1147 | | |
1148 | 1.27k | if (MI->csh->detail) { |
1149 | 1.27k | #ifndef CAPSTONE_DIET |
1150 | 1.27k | uint8_t access; |
1151 | 1.27k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1152 | 1.27k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1153 | 1.27k | MI->ac_idx++; |
1154 | 1.27k | #endif |
1155 | 1.27k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1156 | 1.27k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); |
1157 | 1.27k | MI->flat_insn->detail->arm64.op_count++; |
1158 | 1.27k | } |
1159 | 1.27k | } |
1160 | | |
1161 | | static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O, |
1162 | | unsigned Imm) |
1163 | 9.90k | { |
1164 | 9.90k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1165 | | |
1166 | 9.90k | if (MCOperand_isReg(Op)) { |
1167 | 9.90k | unsigned Reg = MCOperand_getReg(Op); |
1168 | 9.90k | if (Reg == AArch64_XZR) { |
1169 | 0 | printInt32Bang(O, Imm); |
1170 | |
|
1171 | 0 | if (MI->csh->detail) { |
1172 | 0 | #ifndef CAPSTONE_DIET |
1173 | 0 | uint8_t access; |
1174 | |
|
1175 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1176 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1177 | 0 | MI->ac_idx++; |
1178 | 0 | #endif |
1179 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1180 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; |
1181 | 0 | MI->flat_insn->detail->arm64.op_count++; |
1182 | 0 | } |
1183 | 9.90k | } else { |
1184 | 9.90k | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
1185 | | |
1186 | 9.90k | if (MI->csh->detail) { |
1187 | 9.90k | #ifndef CAPSTONE_DIET |
1188 | 9.90k | uint8_t access; |
1189 | | |
1190 | 9.90k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1191 | 9.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1192 | 9.90k | MI->ac_idx++; |
1193 | 9.90k | #endif |
1194 | 9.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1195 | 9.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
1196 | 9.90k | MI->flat_insn->detail->arm64.op_count++; |
1197 | 9.90k | } |
1198 | 9.90k | } |
1199 | 9.90k | } |
1200 | | //llvm_unreachable("unknown operand kind in printPostIncOperand64"); |
1201 | 9.90k | } |
1202 | | |
1203 | | static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O) |
1204 | 26.0k | { |
1205 | 26.0k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1206 | | //assert(Op.isReg() && "Non-register vreg operand!"); |
1207 | 26.0k | unsigned Reg = MCOperand_getReg(Op); |
1208 | | |
1209 | 26.0k | SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); |
1210 | | |
1211 | 26.0k | if (MI->csh->detail) { |
1212 | 26.0k | #ifndef CAPSTONE_DIET |
1213 | 26.0k | uint8_t access; |
1214 | 26.0k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1215 | 26.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1216 | 26.0k | MI->ac_idx++; |
1217 | 26.0k | #endif |
1218 | 26.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1219 | 26.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); |
1220 | 26.0k | MI->flat_insn->detail->arm64.op_count++; |
1221 | 26.0k | } |
1222 | 26.0k | } |
1223 | | |
1224 | | static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O) |
1225 | 2.51k | { |
1226 | 2.51k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1227 | | //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); |
1228 | 2.51k | SStream_concat(O, "c%u", MCOperand_getImm(Op)); |
1229 | | |
1230 | 2.51k | if (MI->csh->detail) { |
1231 | 2.51k | #ifndef CAPSTONE_DIET |
1232 | 2.51k | uint8_t access; |
1233 | | |
1234 | 2.51k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1235 | 2.51k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1236 | 2.51k | MI->ac_idx++; |
1237 | 2.51k | #endif |
1238 | 2.51k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; |
1239 | 2.51k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); |
1240 | 2.51k | MI->flat_insn->detail->arm64.op_count++; |
1241 | 2.51k | } |
1242 | 2.51k | } |
1243 | | |
1244 | | static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) |
1245 | 3.38k | { |
1246 | 3.38k | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
1247 | 3.38k | if (MCOperand_isImm(MO)) { |
1248 | 3.38k | unsigned Val = (MCOperand_getImm(MO) & 0xfff); |
1249 | | //assert(Val == MO.getImm() && "Add/sub immediate out of range!"); |
1250 | 3.38k | unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); |
1251 | | |
1252 | 3.38k | printInt32Bang(O, Val); |
1253 | | |
1254 | 3.38k | if (MI->csh->detail) { |
1255 | 3.38k | #ifndef CAPSTONE_DIET |
1256 | 3.38k | uint8_t access; |
1257 | | |
1258 | 3.38k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1259 | 3.38k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1260 | 3.38k | MI->ac_idx++; |
1261 | 3.38k | #endif |
1262 | 3.38k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1263 | 3.38k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
1264 | 3.38k | MI->flat_insn->detail->arm64.op_count++; |
1265 | 3.38k | } |
1266 | | |
1267 | 3.38k | if (Shift != 0) |
1268 | 1.71k | printShifter(MI, OpNum + 1, O); |
1269 | 3.38k | } |
1270 | 3.38k | } |
1271 | | |
1272 | | static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) |
1273 | 4.41k | { |
1274 | 4.41k | int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1275 | | |
1276 | 4.41k | Val = AArch64_AM_decodeLogicalImmediate(Val, 32); |
1277 | 4.41k | printUInt32Bang(O, (int)Val); |
1278 | | |
1279 | 4.41k | if (MI->csh->detail) { |
1280 | 4.41k | #ifndef CAPSTONE_DIET |
1281 | 4.41k | uint8_t access; |
1282 | | |
1283 | 4.41k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1284 | 4.41k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1285 | 4.41k | MI->ac_idx++; |
1286 | 4.41k | #endif |
1287 | 4.41k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1288 | 4.41k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
1289 | 4.41k | MI->flat_insn->detail->arm64.op_count++; |
1290 | 4.41k | } |
1291 | 4.41k | } |
1292 | | |
1293 | | static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) |
1294 | 2.00k | { |
1295 | 2.00k | int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1296 | 2.00k | Val = AArch64_AM_decodeLogicalImmediate(Val, 64); |
1297 | | |
1298 | 2.00k | switch(MI->flat_insn->id) { |
1299 | 593 | default: |
1300 | 593 | printInt64Bang(O, Val); |
1301 | 593 | break; |
1302 | | |
1303 | 166 | case ARM64_INS_ORR: |
1304 | 537 | case ARM64_INS_AND: |
1305 | 1.41k | case ARM64_INS_EOR: |
1306 | 1.41k | case ARM64_INS_TST: |
1307 | | // do not print number in negative form |
1308 | 1.41k | if (Val >= 0 && Val <= HEX_THRESHOLD) |
1309 | 19 | SStream_concat(O, "#%u", (int)Val); |
1310 | 1.39k | else |
1311 | 1.39k | SStream_concat(O, "#0x%"PRIx64, Val); |
1312 | 1.41k | break; |
1313 | 2.00k | } |
1314 | | |
1315 | 2.00k | if (MI->csh->detail) { |
1316 | 2.00k | #ifndef CAPSTONE_DIET |
1317 | 2.00k | uint8_t access; |
1318 | | |
1319 | 2.00k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1320 | 2.00k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1321 | 2.00k | MI->ac_idx++; |
1322 | 2.00k | #endif |
1323 | 2.00k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1324 | 2.00k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val; |
1325 | 2.00k | MI->flat_insn->detail->arm64.op_count++; |
1326 | 2.00k | } |
1327 | 2.00k | } |
1328 | | |
1329 | | static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) |
1330 | 9.98k | { |
1331 | 9.98k | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1332 | | |
1333 | | // LSL #0 should not be printed. |
1334 | 9.98k | if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && |
1335 | 9.98k | AArch64_AM_getShiftValue(Val) == 0) |
1336 | 424 | return; |
1337 | | |
1338 | 9.55k | SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); |
1339 | 9.55k | printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); |
1340 | | |
1341 | 9.55k | if (MI->csh->detail) { |
1342 | 9.55k | arm64_shifter shifter = ARM64_SFT_INVALID; |
1343 | | |
1344 | 9.55k | switch(AArch64_AM_getShiftType(Val)) { |
1345 | 0 | default: // never reach |
1346 | 5.26k | case AArch64_AM_LSL: |
1347 | 5.26k | shifter = ARM64_SFT_LSL; |
1348 | 5.26k | break; |
1349 | | |
1350 | 1.69k | case AArch64_AM_LSR: |
1351 | 1.69k | shifter = ARM64_SFT_LSR; |
1352 | 1.69k | break; |
1353 | | |
1354 | 1.52k | case AArch64_AM_ASR: |
1355 | 1.52k | shifter = ARM64_SFT_ASR; |
1356 | 1.52k | break; |
1357 | | |
1358 | 987 | case AArch64_AM_ROR: |
1359 | 987 | shifter = ARM64_SFT_ROR; |
1360 | 987 | break; |
1361 | | |
1362 | 89 | case AArch64_AM_MSL: |
1363 | 89 | shifter = ARM64_SFT_MSL; |
1364 | 89 | break; |
1365 | 9.55k | } |
1366 | | |
1367 | 9.55k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; |
1368 | 9.55k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val); |
1369 | 9.55k | } |
1370 | 9.55k | } |
1371 | | |
1372 | | static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) |
1373 | 6.58k | { |
1374 | 6.58k | SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); |
1375 | | |
1376 | 6.58k | if (MI->csh->detail) { |
1377 | 6.58k | #ifndef CAPSTONE_DIET |
1378 | 6.58k | uint8_t access; |
1379 | 6.58k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1380 | 6.58k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1381 | 6.58k | MI->ac_idx++; |
1382 | 6.58k | #endif |
1383 | 6.58k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1384 | 6.58k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
1385 | 6.58k | MI->flat_insn->detail->arm64.op_count++; |
1386 | 6.58k | } |
1387 | | |
1388 | 6.58k | printShifter(MI, OpNum + 1, O); |
1389 | 6.58k | } |
1390 | | |
1391 | | static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) |
1392 | 2.88k | { |
1393 | 2.88k | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1394 | 2.88k | AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); |
1395 | 2.88k | unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); |
1396 | | |
1397 | | // If the destination or first source register operand is [W]SP, print |
1398 | | // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at |
1399 | | // all. |
1400 | 2.88k | if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { |
1401 | 853 | unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
1402 | 853 | unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); |
1403 | | |
1404 | 853 | if (((Dest == AArch64_SP || Src1 == AArch64_SP) && |
1405 | 853 | ExtType == AArch64_AM_UXTX) || |
1406 | 853 | ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && |
1407 | 744 | ExtType == AArch64_AM_UXTW)) { |
1408 | 414 | if (ShiftVal != 0) { |
1409 | 414 | SStream_concat0(O, ", lsl "); |
1410 | 414 | printInt32Bang(O, ShiftVal); |
1411 | | |
1412 | 414 | if (MI->csh->detail) { |
1413 | 414 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; |
1414 | 414 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; |
1415 | 414 | } |
1416 | 414 | } |
1417 | | |
1418 | 414 | return; |
1419 | 414 | } |
1420 | 853 | } |
1421 | | |
1422 | 2.46k | SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); |
1423 | | |
1424 | 2.46k | if (MI->csh->detail) { |
1425 | 2.46k | arm64_extender ext = ARM64_EXT_INVALID; |
1426 | 2.46k | switch(ExtType) { |
1427 | 0 | default: // never reach |
1428 | |
|
1429 | 157 | case AArch64_AM_UXTB: |
1430 | 157 | ext = ARM64_EXT_UXTB; |
1431 | 157 | break; |
1432 | | |
1433 | 1.32k | case AArch64_AM_UXTH: |
1434 | 1.32k | ext = ARM64_EXT_UXTH; |
1435 | 1.32k | break; |
1436 | | |
1437 | 211 | case AArch64_AM_UXTW: |
1438 | 211 | ext = ARM64_EXT_UXTW; |
1439 | 211 | break; |
1440 | | |
1441 | 228 | case AArch64_AM_UXTX: |
1442 | 228 | ext = ARM64_EXT_UXTX; |
1443 | 228 | break; |
1444 | | |
1445 | 104 | case AArch64_AM_SXTB: |
1446 | 104 | ext = ARM64_EXT_SXTB; |
1447 | 104 | break; |
1448 | | |
1449 | 303 | case AArch64_AM_SXTH: |
1450 | 303 | ext = ARM64_EXT_SXTH; |
1451 | 303 | break; |
1452 | | |
1453 | 29 | case AArch64_AM_SXTW: |
1454 | 29 | ext = ARM64_EXT_SXTW; |
1455 | 29 | break; |
1456 | | |
1457 | 109 | case AArch64_AM_SXTX: |
1458 | 109 | ext = ARM64_EXT_SXTX; |
1459 | 109 | break; |
1460 | 2.46k | } |
1461 | | |
1462 | 2.46k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; |
1463 | 2.46k | } |
1464 | | |
1465 | 2.46k | if (ShiftVal != 0) { |
1466 | 2.08k | SStream_concat0(O, " "); |
1467 | 2.08k | printInt32Bang(O, ShiftVal); |
1468 | | |
1469 | 2.08k | if (MI->csh->detail) { |
1470 | 2.08k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; |
1471 | 2.08k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; |
1472 | 2.08k | } |
1473 | 2.08k | } |
1474 | 2.46k | } |
1475 | | |
1476 | | static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) |
1477 | 2.26k | { |
1478 | 2.26k | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
1479 | | |
1480 | 2.26k | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
1481 | | |
1482 | 2.26k | if (MI->csh->detail) { |
1483 | 2.26k | #ifndef CAPSTONE_DIET |
1484 | 2.26k | uint8_t access; |
1485 | 2.26k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1486 | 2.26k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1487 | 2.26k | MI->ac_idx++; |
1488 | 2.26k | #endif |
1489 | 2.26k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1490 | 2.26k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
1491 | 2.26k | MI->flat_insn->detail->arm64.op_count++; |
1492 | 2.26k | } |
1493 | | |
1494 | 2.26k | printArithExtend(MI, OpNum + 1, O); |
1495 | 2.26k | } |
1496 | | |
1497 | | static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width, |
1498 | | char SrcRegKind, SStream *O) |
1499 | 9.51k | { |
1500 | | // sxtw, sxtx, uxtw or lsl (== uxtx) |
1501 | 9.51k | bool IsLSL = !SignExtend && SrcRegKind == 'x'; |
1502 | 9.51k | if (IsLSL) { |
1503 | 3.89k | SStream_concat0(O, "lsl"); |
1504 | | |
1505 | 3.89k | if (MI->csh->detail) { |
1506 | 3.89k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; |
1507 | 3.89k | } |
1508 | 5.61k | } else { |
1509 | 5.61k | SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); |
1510 | | |
1511 | 5.61k | if (MI->csh->detail) { |
1512 | 5.61k | if (!SignExtend) { |
1513 | 3.04k | switch(SrcRegKind) { |
1514 | 0 | default: break; |
1515 | 0 | case 'b': |
1516 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; |
1517 | 0 | break; |
1518 | 0 | case 'h': |
1519 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; |
1520 | 0 | break; |
1521 | 3.04k | case 'w': |
1522 | 3.04k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; |
1523 | 3.04k | break; |
1524 | 3.04k | } |
1525 | 3.04k | } else { |
1526 | 2.57k | switch(SrcRegKind) { |
1527 | 0 | default: break; |
1528 | 0 | case 'b': |
1529 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; |
1530 | 0 | break; |
1531 | 0 | case 'h': |
1532 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; |
1533 | 0 | break; |
1534 | 2.09k | case 'w': |
1535 | 2.09k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; |
1536 | 2.09k | break; |
1537 | 472 | case 'x': |
1538 | 472 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; |
1539 | 472 | break; |
1540 | 2.57k | } |
1541 | 2.57k | } |
1542 | 5.61k | } |
1543 | 5.61k | } |
1544 | | |
1545 | 9.51k | if (DoShift || IsLSL) { |
1546 | 6.66k | SStream_concat(O, " #%u", Log2_32(Width / 8)); |
1547 | | |
1548 | 6.66k | if (MI->csh->detail) { |
1549 | 6.66k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; |
1550 | 6.66k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); |
1551 | 6.66k | } |
1552 | 6.66k | } |
1553 | 9.51k | } |
1554 | | |
1555 | | static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width) |
1556 | 2.79k | { |
1557 | 2.79k | unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1558 | 2.79k | unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); |
1559 | | |
1560 | 2.79k | printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O); |
1561 | 2.79k | } |
1562 | | |
1563 | | static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O, |
1564 | | bool SignExtend, int ExtWidth, |
1565 | | char SrcRegKind, char Suffix) |
1566 | 8.83k | { |
1567 | 8.83k | bool DoShift; |
1568 | | |
1569 | 8.83k | printOperand(MI, OpNum, O); |
1570 | | |
1571 | 8.83k | if (Suffix == 's' || Suffix == 'd') |
1572 | 6.23k | SStream_concat(O, ".%c", Suffix); |
1573 | | |
1574 | 8.83k | DoShift = ExtWidth != 8; |
1575 | 8.83k | if (SignExtend || DoShift || SrcRegKind == 'w') { |
1576 | 6.71k | SStream_concat0(O, ", "); |
1577 | 6.71k | printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O); |
1578 | 6.71k | } |
1579 | 8.83k | } |
1580 | | |
1581 | | static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) |
1582 | 2.09k | { |
1583 | 2.09k | AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1584 | 2.09k | SStream_concat0(O, getCondCodeName(CC)); |
1585 | | |
1586 | 2.09k | if (MI->csh->detail) |
1587 | 2.09k | MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); |
1588 | 2.09k | } |
1589 | | |
1590 | | static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) |
1591 | 94 | { |
1592 | 94 | AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1593 | 94 | SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); |
1594 | | |
1595 | 94 | if (MI->csh->detail) { |
1596 | 94 | MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); |
1597 | 94 | } |
1598 | 94 | } |
1599 | | |
1600 | | static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) |
1601 | 16.0k | { |
1602 | 16.0k | int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1603 | | |
1604 | 16.0k | printInt64Bang(O, val); |
1605 | | |
1606 | 16.0k | if (MI->csh->detail) { |
1607 | 16.0k | if (MI->csh->doing_mem) { |
1608 | 11.5k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; |
1609 | 11.5k | } else { |
1610 | 4.53k | #ifndef CAPSTONE_DIET |
1611 | 4.53k | uint8_t access; |
1612 | | |
1613 | 4.53k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1614 | 4.53k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1615 | 4.53k | MI->ac_idx++; |
1616 | 4.53k | #endif |
1617 | 4.53k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1618 | 4.53k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; |
1619 | 4.53k | MI->flat_insn->detail->arm64.op_count++; |
1620 | 4.53k | } |
1621 | 16.0k | } |
1622 | 16.0k | } |
1623 | | |
1624 | | static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale) |
1625 | 4.82k | { |
1626 | 4.82k | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
1627 | | |
1628 | 4.82k | if (MCOperand_isImm(MO)) { |
1629 | 4.82k | int64_t val = Scale * MCOperand_getImm(MO); |
1630 | 4.82k | printInt64Bang(O, val); |
1631 | | |
1632 | 4.82k | if (MI->csh->detail) { |
1633 | 4.82k | if (MI->csh->doing_mem) { |
1634 | 4.82k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; |
1635 | 4.82k | } else { |
1636 | 0 | #ifndef CAPSTONE_DIET |
1637 | 0 | uint8_t access; |
1638 | |
|
1639 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1640 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1641 | 0 | MI->ac_idx++; |
1642 | 0 | #endif |
1643 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1644 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val; |
1645 | 0 | MI->flat_insn->detail->arm64.op_count++; |
1646 | 0 | } |
1647 | 4.82k | } |
1648 | 4.82k | } |
1649 | 4.82k | } |
1650 | | |
1651 | | #if 0 |
1652 | | static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) |
1653 | | { |
1654 | | MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); |
1655 | | |
1656 | | SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); |
1657 | | |
1658 | | if (MCOperand_isImm(MO)) { |
1659 | | int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1660 | | printInt64Bang(O, val); |
1661 | | // } else { |
1662 | | // // assert(MO1.isExpr() && "Unexpected operand type!"); |
1663 | | // SStream_concat0(O, ", "); |
1664 | | // MO1.getExpr()->print(O, &MAI); |
1665 | | } |
1666 | | |
1667 | | SStream_concat0(O, "]"); |
1668 | | } |
1669 | | #endif |
1670 | | |
1671 | | // IsSVEPrefetch = false |
1672 | | static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch) |
1673 | 2.41k | { |
1674 | 2.41k | unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1675 | | |
1676 | 2.41k | if (IsSVEPrefetch) { |
1677 | 1.40k | const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop); |
1678 | 1.40k | if (PRFM) |
1679 | 1.26k | SStream_concat0(O, PRFM->Name); |
1680 | | |
1681 | 1.40k | return; |
1682 | 1.40k | } else { |
1683 | 1.00k | const PRFM *PRFM = lookupPRFMByEncoding(prfop); |
1684 | 1.00k | if (PRFM) |
1685 | 463 | SStream_concat0(O, PRFM->Name); |
1686 | | |
1687 | 1.00k | return; |
1688 | 1.00k | } |
1689 | | |
1690 | | // FIXME: set OpcodePub? |
1691 | | |
1692 | 0 | printInt32Bang(O, prfop); |
1693 | |
|
1694 | 0 | if (MI->csh->detail) { |
1695 | 0 | #ifndef CAPSTONE_DIET |
1696 | 0 | uint8_t access; |
1697 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1698 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1699 | 0 | MI->ac_idx++; |
1700 | 0 | #endif |
1701 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
1702 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; |
1703 | 0 | MI->flat_insn->detail->arm64.op_count++; |
1704 | 0 | } |
1705 | 0 | } |
1706 | | |
1707 | | static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) |
1708 | 712 | { |
1709 | 712 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1710 | 712 | unsigned int psbhintop = MCOperand_getImm(Op); |
1711 | | |
1712 | 712 | const PSB *PSB = lookupPSBByEncoding(psbhintop); |
1713 | 712 | if (PSB) |
1714 | 712 | SStream_concat0(O, PSB->Name); |
1715 | 0 | else |
1716 | 0 | printUInt32Bang(O, psbhintop); |
1717 | 712 | } |
1718 | | |
1719 | 25 | static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) { |
1720 | 25 | unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) ^ 32; |
1721 | | |
1722 | 25 | const BTI *BTI = lookupBTIByEncoding(btihintop); |
1723 | 25 | if (BTI) |
1724 | 25 | SStream_concat0(O, BTI->Name); |
1725 | 0 | else |
1726 | 0 | printUInt32Bang(O, btihintop); |
1727 | 25 | } |
1728 | | |
1729 | | static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
1730 | 413 | { |
1731 | 413 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
1732 | 413 | float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); |
1733 | | |
1734 | | // 8 decimal places are enough to perfectly represent permitted floats. |
1735 | | #if defined(_KERNEL_MODE) |
1736 | | // Issue #681: Windows kernel does not support formatting float point |
1737 | | SStream_concat0(O, "#<float_point_unsupported>"); |
1738 | | #else |
1739 | 413 | SStream_concat(O, "#%.8f", FPImm); |
1740 | 413 | #endif |
1741 | | |
1742 | 413 | if (MI->csh->detail) { |
1743 | 413 | #ifndef CAPSTONE_DIET |
1744 | 413 | uint8_t access; |
1745 | | |
1746 | 413 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1747 | 413 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1748 | 413 | MI->ac_idx++; |
1749 | 413 | #endif |
1750 | 413 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; |
1751 | 413 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; |
1752 | 413 | MI->flat_insn->detail->arm64.op_count++; |
1753 | 413 | } |
1754 | 413 | } |
1755 | | |
1756 | | //static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) |
1757 | | static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) |
1758 | 78.3k | { |
1759 | 156k | while (Stride--) { |
1760 | 78.3k | if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30 |
1761 | 62.3k | Reg += 1; |
1762 | 16.0k | else if (Reg == AArch64_Q31) // Vector lists can wrap around. |
1763 | 3.77k | Reg = AArch64_Q0; |
1764 | 12.2k | else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30 |
1765 | 11.8k | Reg += 1; |
1766 | 384 | else if (Reg == AArch64_Z31) // Vector lists can wrap around. |
1767 | 384 | Reg = AArch64_Z0; |
1768 | 78.3k | } |
1769 | | |
1770 | 78.3k | return Reg; |
1771 | 78.3k | } |
1772 | | |
1773 | | static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size) |
1774 | 198 | { |
1775 | | // static_assert(size == 64 || size == 32, |
1776 | | // "Template parameter must be either 32 or 64"); |
1777 | 198 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
1778 | 198 | unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64; |
1779 | 198 | unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64; |
1780 | 198 | unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); |
1781 | 198 | unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); |
1782 | | |
1783 | 198 | SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName), |
1784 | 198 | getRegisterName(Odd, AArch64_NoRegAltName)); |
1785 | | |
1786 | 198 | if (MI->csh->detail) { |
1787 | 198 | #ifndef CAPSTONE_DIET |
1788 | 198 | uint8_t access; |
1789 | | |
1790 | 198 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1791 | 198 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1792 | 198 | MI->ac_idx++; |
1793 | 198 | #endif |
1794 | | |
1795 | 198 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1796 | 198 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Even; |
1797 | 198 | MI->flat_insn->detail->arm64.op_count++; |
1798 | | |
1799 | 198 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1800 | 198 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Odd; |
1801 | 198 | MI->flat_insn->detail->arm64.op_count++; |
1802 | 198 | } |
1803 | 198 | } |
1804 | | |
1805 | | static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, |
1806 | | char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas) |
1807 | 35.6k | { |
1808 | 540k | #define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) |
1809 | 35.6k | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
1810 | 35.6k | unsigned NumRegs = 1, FirstReg, i; |
1811 | | |
1812 | 35.6k | SStream_concat0(O, "{"); |
1813 | | |
1814 | | // Work out how many registers there are in the list (if there is an actual |
1815 | | // list). |
1816 | 35.6k | if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || |
1817 | 35.6k | GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) || |
1818 | 35.6k | GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) |
1819 | 4.94k | NumRegs = 2; |
1820 | 30.6k | else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || |
1821 | 30.6k | GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) || |
1822 | 30.6k | GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) |
1823 | 9.35k | NumRegs = 3; |
1824 | 21.3k | else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || |
1825 | 21.3k | GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) || |
1826 | 21.3k | GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) |
1827 | 6.34k | NumRegs = 4; |
1828 | | |
1829 | | // Now forget about the list and find out what the first register is. |
1830 | 35.6k | if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) |
1831 | 5.47k | Reg = FirstReg; |
1832 | 30.1k | else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) |
1833 | 14.0k | Reg = FirstReg; |
1834 | 16.1k | else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0))) |
1835 | 1.17k | Reg = FirstReg; |
1836 | | |
1837 | | // If it's a D-reg, we need to promote it to the equivalent Q-reg before |
1838 | | // printing (otherwise getRegisterName fails). |
1839 | 35.6k | if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { |
1840 | 6.00k | const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); |
1841 | 6.00k | Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); |
1842 | 6.00k | } |
1843 | | |
1844 | 113k | for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { |
1845 | 78.3k | bool isZReg = GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg); |
1846 | 78.3k | if (isZReg) |
1847 | 12.2k | SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix); |
1848 | 66.1k | else |
1849 | 66.1k | SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); |
1850 | | |
1851 | 78.3k | if (MI->csh->detail) { |
1852 | 78.3k | #ifndef CAPSTONE_DIET |
1853 | 78.3k | uint8_t access; |
1854 | | |
1855 | 78.3k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
1856 | 78.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
1857 | 78.3k | MI->ac_idx++; |
1858 | 78.3k | #endif |
1859 | 78.3k | unsigned regForDetail = isZReg ? Reg : AArch64_map_vregister(Reg); |
1860 | 78.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
1861 | 78.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = regForDetail; |
1862 | 78.3k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; |
1863 | 78.3k | MI->flat_insn->detail->arm64.op_count++; |
1864 | 78.3k | } |
1865 | | |
1866 | 78.3k | if (i + 1 != NumRegs) |
1867 | 42.6k | SStream_concat0(O, ", "); |
1868 | 78.3k | } |
1869 | | |
1870 | 35.6k | SStream_concat0(O, "}"); |
1871 | 35.6k | } |
1872 | | |
1873 | | static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind) |
1874 | 35.6k | { |
1875 | 35.6k | char Suffix[32]; |
1876 | 35.6k | arm64_vas vas = 0; |
1877 | | |
1878 | 35.6k | if (NumLanes) { |
1879 | 12.6k | cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); |
1880 | | |
1881 | 12.6k | switch(LaneKind) { |
1882 | 0 | default: break; |
1883 | 3.15k | case 'b': |
1884 | 3.15k | switch(NumLanes) { |
1885 | 0 | default: break; |
1886 | 0 | case 1: |
1887 | 0 | vas = ARM64_VAS_1B; |
1888 | 0 | break; |
1889 | 0 | case 4: |
1890 | 0 | vas = ARM64_VAS_4B; |
1891 | 0 | break; |
1892 | 1.54k | case 8: |
1893 | 1.54k | vas = ARM64_VAS_8B; |
1894 | 1.54k | break; |
1895 | 1.61k | case 16: |
1896 | 1.61k | vas = ARM64_VAS_16B; |
1897 | 1.61k | break; |
1898 | 3.15k | } |
1899 | 3.15k | break; |
1900 | 3.98k | case 'h': |
1901 | 3.98k | switch(NumLanes) { |
1902 | 0 | default: break; |
1903 | 0 | case 1: |
1904 | 0 | vas = ARM64_VAS_1H; |
1905 | 0 | break; |
1906 | 0 | case 2: |
1907 | 0 | vas = ARM64_VAS_2H; |
1908 | 0 | break; |
1909 | 2.33k | case 4: |
1910 | 2.33k | vas = ARM64_VAS_4H; |
1911 | 2.33k | break; |
1912 | 1.64k | case 8: |
1913 | 1.64k | vas = ARM64_VAS_8H; |
1914 | 1.64k | break; |
1915 | 3.98k | } |
1916 | 3.98k | break; |
1917 | 3.98k | case 's': |
1918 | 3.37k | switch(NumLanes) { |
1919 | 0 | default: break; |
1920 | 0 | case 1: |
1921 | 0 | vas = ARM64_VAS_1S; |
1922 | 0 | break; |
1923 | 1.65k | case 2: |
1924 | 1.65k | vas = ARM64_VAS_2S; |
1925 | 1.65k | break; |
1926 | 1.72k | case 4: |
1927 | 1.72k | vas = ARM64_VAS_4S; |
1928 | 1.72k | break; |
1929 | 3.37k | } |
1930 | 3.37k | break; |
1931 | 3.37k | case 'd': |
1932 | 2.16k | switch(NumLanes) { |
1933 | 0 | default: break; |
1934 | 472 | case 1: |
1935 | 472 | vas = ARM64_VAS_1D; |
1936 | 472 | break; |
1937 | 1.68k | case 2: |
1938 | 1.68k | vas = ARM64_VAS_2D; |
1939 | 1.68k | break; |
1940 | 2.16k | } |
1941 | 2.16k | break; |
1942 | 2.16k | case 'q': |
1943 | 0 | switch(NumLanes) { |
1944 | 0 | default: break; |
1945 | 0 | case 1: |
1946 | 0 | vas = ARM64_VAS_1Q; |
1947 | 0 | break; |
1948 | 0 | } |
1949 | 0 | break; |
1950 | 12.6k | } |
1951 | 22.9k | } else { |
1952 | 22.9k | cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); |
1953 | | |
1954 | 22.9k | switch(LaneKind) { |
1955 | 0 | default: break; |
1956 | 5.31k | case 'b': |
1957 | 5.31k | vas = ARM64_VAS_1B; |
1958 | 5.31k | break; |
1959 | 5.11k | case 'h': |
1960 | 5.11k | vas = ARM64_VAS_1H; |
1961 | 5.11k | break; |
1962 | 5.14k | case 's': |
1963 | 5.14k | vas = ARM64_VAS_1S; |
1964 | 5.14k | break; |
1965 | 7.39k | case 'd': |
1966 | 7.39k | vas = ARM64_VAS_1D; |
1967 | 7.39k | break; |
1968 | 0 | case 'q': |
1969 | 0 | vas = ARM64_VAS_1Q; |
1970 | 0 | break; |
1971 | 22.9k | } |
1972 | 22.9k | } |
1973 | | |
1974 | 35.6k | printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas); |
1975 | 35.6k | } |
1976 | | |
1977 | | static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) |
1978 | 17.4k | { |
1979 | 17.4k | SStream_concat0(O, "["); |
1980 | 17.4k | printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); |
1981 | 17.4k | SStream_concat0(O, "]"); |
1982 | | |
1983 | 17.4k | if (MI->csh->detail) { |
1984 | 17.4k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
1985 | 17.4k | } |
1986 | 17.4k | } |
1987 | | |
1988 | | static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) |
1989 | 8.87k | { |
1990 | 8.87k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
1991 | | |
1992 | | // If the label has already been resolved to an immediate offset (say, when |
1993 | | // we're running the disassembler), just print the immediate. |
1994 | 8.87k | if (MCOperand_isImm(Op)) { |
1995 | 8.87k | uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; |
1996 | 8.87k | printUInt64Bang(O, imm); |
1997 | | |
1998 | 8.87k | if (MI->csh->detail) { |
1999 | 8.87k | #ifndef CAPSTONE_DIET |
2000 | 8.87k | uint8_t access; |
2001 | | |
2002 | 8.87k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2003 | 8.87k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2004 | 8.87k | MI->ac_idx++; |
2005 | 8.87k | #endif |
2006 | 8.87k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2007 | 8.87k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; |
2008 | 8.87k | MI->flat_insn->detail->arm64.op_count++; |
2009 | 8.87k | } |
2010 | 8.87k | } |
2011 | 8.87k | } |
2012 | | |
2013 | | static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) |
2014 | 1.74k | { |
2015 | 1.74k | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
2016 | | |
2017 | 1.74k | if (MCOperand_isImm(Op)) { |
2018 | | // ADRP sign extends a 21-bit offset, shifts it left by 12 |
2019 | | // and adds it to the value of the PC with its bottom 12 bits cleared |
2020 | 1.74k | uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff); |
2021 | 1.74k | printUInt64Bang(O, imm); |
2022 | | |
2023 | 1.74k | if (MI->csh->detail) { |
2024 | 1.74k | #ifndef CAPSTONE_DIET |
2025 | 1.74k | uint8_t access; |
2026 | | |
2027 | 1.74k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2028 | 1.74k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2029 | 1.74k | MI->ac_idx++; |
2030 | 1.74k | #endif |
2031 | 1.74k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2032 | 1.74k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; |
2033 | 1.74k | MI->flat_insn->detail->arm64.op_count++; |
2034 | 1.74k | } |
2035 | 1.74k | } |
2036 | 1.74k | } |
2037 | | |
2038 | | static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) |
2039 | 196 | { |
2040 | 196 | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2041 | 196 | unsigned Opcode = MCInst_getOpcode(MI); |
2042 | 196 | const char *Name = NULL; |
2043 | | |
2044 | 196 | if (Opcode == AArch64_ISB) { |
2045 | 10 | const ISB *ISB = lookupISBByEncoding(Val); |
2046 | 10 | Name = ISB ? ISB->Name : NULL; |
2047 | 186 | } else if (Opcode == AArch64_TSB) { |
2048 | 0 | const TSB *TSB = lookupTSBByEncoding(Val); |
2049 | 0 | Name = TSB ? TSB->Name : NULL; |
2050 | 186 | } else { |
2051 | 186 | const DB *DB = lookupDBByEncoding(Val); |
2052 | 186 | Name = DB ? DB->Name : NULL; |
2053 | 186 | } |
2054 | | |
2055 | 196 | if (Name) { |
2056 | 88 | SStream_concat0(O, Name); |
2057 | | |
2058 | 88 | if (MI->csh->detail) { |
2059 | 88 | #ifndef CAPSTONE_DIET |
2060 | 88 | uint8_t access; |
2061 | | |
2062 | 88 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2063 | 88 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2064 | 88 | MI->ac_idx++; |
2065 | 88 | #endif |
2066 | 88 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; |
2067 | 88 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; |
2068 | 88 | MI->flat_insn->detail->arm64.op_count++; |
2069 | 88 | } |
2070 | 108 | } else { |
2071 | 108 | printUInt32Bang(O, Val); |
2072 | | |
2073 | 108 | if (MI->csh->detail) { |
2074 | 108 | #ifndef CAPSTONE_DIET |
2075 | 108 | uint8_t access; |
2076 | | |
2077 | 108 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2078 | 108 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2079 | 108 | MI->ac_idx++; |
2080 | 108 | #endif |
2081 | 108 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2082 | 108 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
2083 | 108 | MI->flat_insn->detail->arm64.op_count++; |
2084 | 108 | } |
2085 | 108 | } |
2086 | 196 | } |
2087 | | |
2088 | 24 | static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) { |
2089 | 24 | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); |
2090 | | // assert(MI->getOpcode() == AArch64::DSBnXS); |
2091 | | |
2092 | 24 | const char *Name = NULL; |
2093 | 24 | const DBnXS *DB = lookupDBnXSByEncoding(Val); |
2094 | 24 | Name = DB ? DB->Name : NULL; |
2095 | | |
2096 | 24 | if (Name) { |
2097 | 24 | SStream_concat0(O, Name); |
2098 | | |
2099 | 24 | if (MI->csh->detail) { |
2100 | 24 | #ifndef CAPSTONE_DIET |
2101 | 24 | uint8_t access; |
2102 | | |
2103 | 24 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2104 | 24 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2105 | 24 | MI->ac_idx++; |
2106 | 24 | #endif |
2107 | 24 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; |
2108 | 24 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; |
2109 | 24 | MI->flat_insn->detail->arm64.op_count++; |
2110 | 24 | } |
2111 | 24 | } |
2112 | 0 | else { |
2113 | 0 | printUInt32Bang(O, Val); |
2114 | |
|
2115 | 0 | if (MI->csh->detail) { |
2116 | 0 | #ifndef CAPSTONE_DIET |
2117 | 0 | uint8_t access; |
2118 | |
|
2119 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2120 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2121 | 0 | MI->ac_idx++; |
2122 | 0 | #endif |
2123 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2124 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
2125 | 0 | MI->flat_insn->detail->arm64.op_count++; |
2126 | 0 | } |
2127 | 0 | } |
2128 | 24 | } |
2129 | | |
2130 | | static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) |
2131 | 1.22k | { |
2132 | 1.22k | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2133 | 1.22k | const SysReg *Reg = lookupSysRegByEncoding(Val); |
2134 | | |
2135 | | // Horrible hack for the one register that has identical encodings but |
2136 | | // different names in MSR and MRS. Because of this, one of MRS and MSR is |
2137 | | // going to get the wrong entry |
2138 | 1.22k | if (Val == ARM64_SYSREG_DBGDTRRX_EL0) { |
2139 | 8 | SStream_concat0(O, "dbgdtrrx_el0"); |
2140 | | |
2141 | 8 | if (MI->csh->detail) { |
2142 | 8 | #ifndef CAPSTONE_DIET |
2143 | 8 | uint8_t access; |
2144 | | |
2145 | 8 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2146 | 8 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2147 | 8 | MI->ac_idx++; |
2148 | 8 | #endif |
2149 | | |
2150 | 8 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2151 | 8 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; |
2152 | 8 | MI->flat_insn->detail->arm64.op_count++; |
2153 | 8 | } |
2154 | | |
2155 | 8 | return; |
2156 | 8 | } |
2157 | | |
2158 | | // Another hack for a register which has an alternative name which is not an alias, |
2159 | | // and is not in the Armv9-A documentation. |
2160 | 1.21k | if( Val == ARM64_SYSREG_VSCTLR_EL2){ |
2161 | 14 | SStream_concat0(O, "ttbr0_el2"); |
2162 | | |
2163 | 14 | if (MI->csh->detail) { |
2164 | 14 | #ifndef CAPSTONE_DIET |
2165 | 14 | uint8_t access; |
2166 | | |
2167 | 14 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2168 | 14 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2169 | 14 | MI->ac_idx++; |
2170 | 14 | #endif |
2171 | | |
2172 | 14 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2173 | 14 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; |
2174 | 14 | MI->flat_insn->detail->arm64.op_count++; |
2175 | 14 | } |
2176 | | |
2177 | 14 | return; |
2178 | 14 | } |
2179 | | |
2180 | | // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) |
2181 | 1.20k | if (Reg && Reg->Readable) { |
2182 | 76 | SStream_concat0(O, Reg->Name); |
2183 | | |
2184 | 76 | if (MI->csh->detail) { |
2185 | 76 | #ifndef CAPSTONE_DIET |
2186 | 76 | uint8_t access; |
2187 | | |
2188 | 76 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2189 | 76 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2190 | 76 | MI->ac_idx++; |
2191 | 76 | #endif |
2192 | | |
2193 | 76 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2194 | 76 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; |
2195 | 76 | MI->flat_insn->detail->arm64.op_count++; |
2196 | 76 | } |
2197 | 1.12k | } else { |
2198 | 1.12k | char result[128]; |
2199 | | |
2200 | 1.12k | AArch64SysReg_genericRegisterString(Val, result); |
2201 | 1.12k | SStream_concat0(O, result); |
2202 | | |
2203 | 1.12k | if (MI->csh->detail) { |
2204 | 1.12k | #ifndef CAPSTONE_DIET |
2205 | 1.12k | uint8_t access; |
2206 | 1.12k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2207 | 1.12k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2208 | 1.12k | MI->ac_idx++; |
2209 | 1.12k | #endif |
2210 | 1.12k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; |
2211 | 1.12k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; |
2212 | 1.12k | MI->flat_insn->detail->arm64.op_count++; |
2213 | 1.12k | } |
2214 | 1.12k | } |
2215 | 1.20k | } |
2216 | | |
2217 | | static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) |
2218 | 974 | { |
2219 | 974 | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2220 | 974 | const SysReg *Reg = lookupSysRegByEncoding(Val); |
2221 | | |
2222 | | // Horrible hack for the one register that has identical encodings but |
2223 | | // different names in MSR and MRS. Because of this, one of MRS and MSR is |
2224 | | // going to get the wrong entry |
2225 | 974 | if (Val == ARM64_SYSREG_DBGDTRTX_EL0) { |
2226 | 5 | SStream_concat0(O, "dbgdtrtx_el0"); |
2227 | | |
2228 | 5 | if (MI->csh->detail) { |
2229 | 5 | #ifndef CAPSTONE_DIET |
2230 | 5 | uint8_t access; |
2231 | | |
2232 | 5 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2233 | 5 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2234 | 5 | MI->ac_idx++; |
2235 | 5 | #endif |
2236 | | |
2237 | 5 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2238 | 5 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; |
2239 | 5 | MI->flat_insn->detail->arm64.op_count++; |
2240 | 5 | } |
2241 | | |
2242 | 5 | return; |
2243 | 5 | } |
2244 | | |
2245 | | // Another hack for a register which has an alternative name which is not an alias, |
2246 | | // and is not in the Armv9-A documentation. |
2247 | 969 | if( Val == ARM64_SYSREG_VSCTLR_EL2){ |
2248 | 10 | SStream_concat0(O, "ttbr0_el2"); |
2249 | | |
2250 | 10 | if (MI->csh->detail) { |
2251 | 10 | #ifndef CAPSTONE_DIET |
2252 | 10 | uint8_t access; |
2253 | | |
2254 | 10 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2255 | 10 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2256 | 10 | MI->ac_idx++; |
2257 | 10 | #endif |
2258 | | |
2259 | 10 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2260 | 10 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; |
2261 | 10 | MI->flat_insn->detail->arm64.op_count++; |
2262 | 10 | } |
2263 | | |
2264 | 10 | return; |
2265 | 10 | } |
2266 | | |
2267 | | // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) |
2268 | 959 | if (Reg && Reg->Writeable) { |
2269 | 118 | SStream_concat0(O, Reg->Name); |
2270 | | |
2271 | 118 | if (MI->csh->detail) { |
2272 | 118 | #ifndef CAPSTONE_DIET |
2273 | 118 | uint8_t access; |
2274 | | |
2275 | 118 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2276 | 118 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2277 | 118 | MI->ac_idx++; |
2278 | 118 | #endif |
2279 | | |
2280 | 118 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; |
2281 | 118 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; |
2282 | 118 | MI->flat_insn->detail->arm64.op_count++; |
2283 | 118 | } |
2284 | 841 | } else { |
2285 | 841 | char result[128]; |
2286 | | |
2287 | 841 | AArch64SysReg_genericRegisterString(Val, result); |
2288 | 841 | SStream_concat0(O, result); |
2289 | | |
2290 | 841 | if (MI->csh->detail) { |
2291 | 841 | #ifndef CAPSTONE_DIET |
2292 | 841 | uint8_t access; |
2293 | 841 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2294 | 841 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2295 | 841 | MI->ac_idx++; |
2296 | 841 | #endif |
2297 | 841 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; |
2298 | 841 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; |
2299 | 841 | MI->flat_insn->detail->arm64.op_count++; |
2300 | 841 | } |
2301 | 841 | } |
2302 | 959 | } |
2303 | | |
2304 | | static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) |
2305 | 29 | { |
2306 | 29 | unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2307 | | |
2308 | 29 | const PState *PState = lookupPStateByEncoding(Val); |
2309 | | |
2310 | 29 | if (PState) { |
2311 | 29 | SStream_concat0(O, PState->Name); |
2312 | | |
2313 | 29 | if (MI->csh->detail) { |
2314 | 29 | #ifndef CAPSTONE_DIET |
2315 | 29 | uint8_t access; |
2316 | 29 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2317 | 29 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2318 | 29 | MI->ac_idx++; |
2319 | 29 | #endif |
2320 | 29 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE; |
2321 | 29 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; |
2322 | 29 | MI->flat_insn->detail->arm64.op_count++; |
2323 | 29 | } |
2324 | 29 | } else { |
2325 | 0 | printUInt32Bang(O, Val); |
2326 | |
|
2327 | 0 | if (MI->csh->detail) { |
2328 | 0 | #ifndef CAPSTONE_DIET |
2329 | 0 | unsigned char access; |
2330 | |
|
2331 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2332 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2333 | 0 | MI->ac_idx++; |
2334 | 0 | #endif |
2335 | |
|
2336 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2337 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
2338 | 0 | MI->flat_insn->detail->arm64.op_count++; |
2339 | 0 | } |
2340 | 0 | } |
2341 | 29 | } |
2342 | | |
2343 | | static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) |
2344 | 111 | { |
2345 | 111 | uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2346 | 111 | uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); |
2347 | | |
2348 | 111 | SStream_concat(O, "#%#016llx", Val); |
2349 | | |
2350 | 111 | if (MI->csh->detail) { |
2351 | 111 | #ifndef CAPSTONE_DIET |
2352 | 111 | unsigned char access; |
2353 | | |
2354 | 111 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2355 | 111 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2356 | 111 | MI->ac_idx++; |
2357 | 111 | #endif |
2358 | 111 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
2359 | 111 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; |
2360 | 111 | MI->flat_insn->detail->arm64.op_count++; |
2361 | 111 | } |
2362 | 111 | } |
2363 | | |
2364 | | static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder) |
2365 | 800 | { |
2366 | 800 | unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2367 | 800 | printInt64Bang(O, (Val * Angle) + Remainder); |
2368 | 800 | op_addImm(MI, (Val * Angle) + Remainder); |
2369 | 800 | } |
2370 | | |
2371 | | static void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O) |
2372 | 0 | { |
2373 | 0 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
2374 | | // assert(MCOperand_isImm(MO) && "Unexpected operand type!"); |
2375 | 0 | unsigned svcrop = MCOperand_getImm(MO); |
2376 | 0 | const SVCR *svcr = lookupSVCRByEncoding(svcrop); |
2377 | | // assert(svcr && "Unexpected SVCR operand!"); |
2378 | 0 | SStream_concat0(O, svcr->Name); |
2379 | |
|
2380 | 0 | if (MI->csh->detail) { |
2381 | 0 | #ifndef CAPSTONE_DIET |
2382 | 0 | uint8_t access; |
2383 | |
|
2384 | 0 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2385 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2386 | 0 | MI->ac_idx++; |
2387 | 0 | #endif |
2388 | |
|
2389 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SVCR; |
2390 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = (unsigned)ARM64_SYSREG_SVCR; |
2391 | 0 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].svcr = svcr->Encoding; |
2392 | 0 | MI->flat_insn->detail->arm64.op_count++; |
2393 | 0 | } |
2394 | 0 | } |
2395 | | |
2396 | | static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize) |
2397 | 136 | { |
2398 | 136 | MCOperand *RegOp = MCInst_getOperand(MI, OpNum); |
2399 | | // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!"); |
2400 | 136 | unsigned Reg = MCOperand_getReg(RegOp); |
2401 | | |
2402 | 136 | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
2403 | 136 | const char *sizeStr = ""; |
2404 | 136 | switch (EltSize) { |
2405 | 136 | case 0: |
2406 | 136 | sizeStr = ""; |
2407 | 136 | break; |
2408 | 0 | case 8: |
2409 | 0 | sizeStr = ".b"; |
2410 | 0 | break; |
2411 | 0 | case 16: |
2412 | 0 | sizeStr = ".h"; |
2413 | 0 | break; |
2414 | 0 | case 32: |
2415 | 0 | sizeStr = ".s"; |
2416 | 0 | break; |
2417 | 0 | case 64: |
2418 | 0 | sizeStr = ".d"; |
2419 | 0 | break; |
2420 | 0 | case 128: |
2421 | 0 | sizeStr = ".q"; |
2422 | 0 | break; |
2423 | 0 | default: |
2424 | 0 | break; |
2425 | | // llvm_unreachable("Unsupported element size"); |
2426 | 136 | } |
2427 | 136 | SStream_concat0(O, sizeStr); |
2428 | | |
2429 | 136 | if (MI->csh->detail) { |
2430 | 136 | #ifndef CAPSTONE_DIET |
2431 | 136 | uint8_t access; |
2432 | | |
2433 | 136 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2434 | 136 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2435 | 136 | MI->ac_idx++; |
2436 | 136 | #endif |
2437 | | |
2438 | 136 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2439 | 136 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
2440 | 136 | MI->flat_insn->detail->arm64.op_count++; |
2441 | 136 | } |
2442 | 136 | } |
2443 | | |
2444 | | static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O) |
2445 | 3.29k | { |
2446 | 3.29k | int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2447 | 3.29k | printInt64(O, imm); |
2448 | | |
2449 | 3.29k | if (MI->csh->detail) { |
2450 | 3.29k | if (MI->csh->doing_SME_Index) { |
2451 | | // Access op_count-1 as We want to add info to previous operand, not create a new one |
2452 | 3.29k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = imm; |
2453 | 3.29k | } |
2454 | 3.29k | } |
2455 | 3.29k | } |
2456 | | |
2457 | | static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O) |
2458 | 2.15k | { |
2459 | 2.15k | MCOperand *RegOp = MCInst_getOperand(MI, OpNum); |
2460 | | // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!"); |
2461 | 2.15k | unsigned Reg = MCOperand_getReg(RegOp); |
2462 | 2.15k | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
2463 | | |
2464 | 2.15k | if (MI->csh->detail) { |
2465 | 2.15k | #ifndef CAPSTONE_DIET |
2466 | 2.15k | uint8_t access; |
2467 | | |
2468 | 2.15k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2469 | 2.15k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2470 | 2.15k | MI->ac_idx++; |
2471 | 2.15k | #endif |
2472 | | |
2473 | 2.15k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2474 | 2.15k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
2475 | 2.15k | MI->flat_insn->detail->arm64.op_count++; |
2476 | 2.15k | } |
2477 | 2.15k | } |
2478 | | |
2479 | | static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool IsVertical) |
2480 | 2.90k | { |
2481 | 2.90k | MCOperand *RegOp = MCInst_getOperand(MI, OpNum); |
2482 | | // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!"); |
2483 | 2.90k | unsigned Reg = MCOperand_getReg(RegOp); |
2484 | 2.90k | #ifndef CAPSTONE_DIET |
2485 | 2.90k | const char *RegName = getRegisterName(Reg, AArch64_NoRegAltName); |
2486 | | |
2487 | 2.90k | const size_t strLn = strlen(RegName); |
2488 | | // +2 for extra chars, + 1 for null char \0 |
2489 | 2.90k | char *RegNameNew = cs_mem_malloc(sizeof(char) * (strLn + 2 + 1)); |
2490 | 2.90k | int index = 0, i; |
2491 | 23.2k | for (i = 0; i < (strLn + 2); i++){ |
2492 | 20.3k | if(RegName[i] != '.'){ |
2493 | 17.4k | RegNameNew[index] = RegName[i]; |
2494 | 17.4k | index++; |
2495 | 17.4k | } |
2496 | 2.90k | else{ |
2497 | 2.90k | RegNameNew[index] = IsVertical ? 'v' : 'h'; |
2498 | 2.90k | RegNameNew[index + 1] = '.'; |
2499 | 2.90k | index += 2; |
2500 | 2.90k | } |
2501 | 20.3k | } |
2502 | 2.90k | SStream_concat0(O, RegNameNew); |
2503 | 2.90k | #endif |
2504 | | |
2505 | 2.90k | if (MI->csh->detail) { |
2506 | 2.90k | #ifndef CAPSTONE_DIET |
2507 | 2.90k | uint8_t access; |
2508 | | |
2509 | 2.90k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2510 | 2.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2511 | 2.90k | MI->ac_idx++; |
2512 | 2.90k | #endif |
2513 | | |
2514 | 2.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2515 | 2.90k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
2516 | 2.90k | MI->flat_insn->detail->arm64.op_count++; |
2517 | 2.90k | } |
2518 | 2.90k | #ifndef CAPSTONE_DIET |
2519 | 2.90k | cs_mem_free(RegNameNew); |
2520 | 2.90k | #endif |
2521 | 2.90k | } |
2522 | | |
2523 | | static const unsigned MatrixZADRegisterTable[] = { |
2524 | | AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3, |
2525 | | AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7 |
2526 | | }; |
2527 | | |
2528 | 42 | static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){ |
2529 | 42 | unsigned MaxRegs = 8; |
2530 | 42 | unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2531 | | |
2532 | 42 | unsigned NumRegs = 0, I; |
2533 | 378 | for (I = 0; I < MaxRegs; ++I) |
2534 | 336 | if ((RegMask & (1 << I)) != 0) |
2535 | 195 | ++NumRegs; |
2536 | | |
2537 | 42 | SStream_concat0(O, "{"); |
2538 | 42 | unsigned Printed = 0, J; |
2539 | 378 | for (J = 0; J < MaxRegs; ++J) { |
2540 | 336 | unsigned Reg = RegMask & (1 << J); |
2541 | 336 | if (Reg == 0) |
2542 | 141 | continue; |
2543 | 195 | SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName)); |
2544 | | |
2545 | 195 | if (MI->csh->detail) { |
2546 | 195 | #ifndef CAPSTONE_DIET |
2547 | 195 | uint8_t access; |
2548 | | |
2549 | 195 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2550 | 195 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2551 | 195 | MI->ac_idx++; |
2552 | 195 | #endif |
2553 | | |
2554 | 195 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2555 | 195 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[J]; |
2556 | 195 | MI->flat_insn->detail->arm64.op_count++; |
2557 | 195 | } |
2558 | | |
2559 | 195 | if (Printed + 1 != NumRegs) |
2560 | 155 | SStream_concat0(O, ", "); |
2561 | 195 | ++Printed; |
2562 | 195 | } |
2563 | 42 | SStream_concat0(O, "}"); |
2564 | 42 | } |
2565 | | |
2566 | | static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) |
2567 | 1.98k | { |
2568 | 1.98k | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2569 | | |
2570 | 1.98k | const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val); |
2571 | 1.98k | if (Pat) |
2572 | 1.10k | SStream_concat0(O, Pat->Name); |
2573 | 878 | else |
2574 | 878 | printUInt32Bang(O, Val); |
2575 | 1.98k | } |
2576 | | |
2577 | | // default suffix = 0 |
2578 | | static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) |
2579 | 71.0k | { |
2580 | 71.0k | unsigned int Reg; |
2581 | | |
2582 | | #if 0 |
2583 | | switch (suffix) { |
2584 | | case 0: |
2585 | | case 'b': |
2586 | | case 'h': |
2587 | | case 's': |
2588 | | case 'd': |
2589 | | case 'q': |
2590 | | break; |
2591 | | default: |
2592 | | // llvm_unreachable("Invalid kind specifier."); |
2593 | | } |
2594 | | #endif |
2595 | | |
2596 | 71.0k | Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
2597 | | |
2598 | 71.0k | if (MI->csh->detail) { |
2599 | 71.0k | #ifndef CAPSTONE_DIET |
2600 | 71.0k | uint8_t access; |
2601 | | |
2602 | 71.0k | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2603 | 71.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2604 | 71.0k | MI->ac_idx++; |
2605 | 71.0k | #endif |
2606 | 71.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2607 | 71.0k | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
2608 | 71.0k | MI->flat_insn->detail->arm64.op_count++; |
2609 | 71.0k | } |
2610 | | |
2611 | 71.0k | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
2612 | | |
2613 | 71.0k | if (suffix != '\0') |
2614 | 44.7k | SStream_concat(O, ".%c", suffix); |
2615 | 71.0k | } |
2616 | | |
2617 | | static void printImmSVE16(int16_t Val, SStream *O) |
2618 | 1.92k | { |
2619 | 1.92k | printUInt32Bang(O, Val); |
2620 | 1.92k | } |
2621 | | |
2622 | | static void printImmSVE32(int32_t Val, SStream *O) |
2623 | 380 | { |
2624 | 380 | printUInt32Bang(O, Val); |
2625 | 380 | } |
2626 | | |
2627 | | static void printImmSVE64(int64_t Val, SStream *O) |
2628 | 1.86k | { |
2629 | 1.86k | printUInt64Bang(O, Val); |
2630 | 1.86k | } |
2631 | | |
2632 | | static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O) |
2633 | 418 | { |
2634 | 418 | unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2635 | 418 | unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); |
2636 | 418 | uint32_t Val; |
2637 | | |
2638 | | // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && |
2639 | | // "Unexepected shift type!"); |
2640 | | |
2641 | | // #0 lsl #8 is never pretty printed |
2642 | 418 | if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { |
2643 | 38 | printUInt32Bang(O, UnscaledVal); |
2644 | 38 | printShifter(MI, OpNum + 1, O); |
2645 | 38 | return; |
2646 | 38 | } |
2647 | | |
2648 | 380 | Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); |
2649 | 380 | printImmSVE32(Val, O); |
2650 | 380 | } |
2651 | | |
2652 | | static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O) |
2653 | 850 | { |
2654 | 850 | unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2655 | 850 | unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); |
2656 | 850 | uint64_t Val; |
2657 | | |
2658 | | // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && |
2659 | | // "Unexepected shift type!"); |
2660 | | |
2661 | | // #0 lsl #8 is never pretty printed |
2662 | 850 | if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { |
2663 | 22 | printUInt32Bang(O, UnscaledVal); |
2664 | 22 | printShifter(MI, OpNum + 1, O); |
2665 | 22 | return; |
2666 | 22 | } |
2667 | | |
2668 | 828 | Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); |
2669 | 828 | printImmSVE64(Val, O); |
2670 | 828 | } |
2671 | | |
2672 | | static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O) |
2673 | 523 | { |
2674 | 523 | uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2675 | 523 | uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); |
2676 | | |
2677 | | // Prefer the default format for 16bit values, hex otherwise. |
2678 | 523 | printImmSVE16(PrintVal, O); |
2679 | 523 | } |
2680 | | |
2681 | | static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) |
2682 | 2.69k | { |
2683 | 2.69k | uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2684 | 2.69k | uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); |
2685 | | |
2686 | | // Prefer the default format for 16bit values, hex otherwise. |
2687 | 2.69k | if ((uint16_t)PrintVal == (uint32_t)PrintVal) |
2688 | 1.40k | printImmSVE16(PrintVal, O); |
2689 | 1.29k | else |
2690 | 1.29k | printUInt64Bang(O, PrintVal); |
2691 | 2.69k | } |
2692 | | |
2693 | | static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) |
2694 | 1.03k | { |
2695 | 1.03k | uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2696 | 1.03k | uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); |
2697 | | |
2698 | 1.03k | printImmSVE64(PrintVal, O); |
2699 | 1.03k | } |
2700 | | |
2701 | | static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width) |
2702 | 798 | { |
2703 | 798 | unsigned int Base, Reg; |
2704 | | |
2705 | 798 | switch (Width) { |
2706 | 0 | default: // llvm_unreachable("Unsupported width"); |
2707 | 29 | case 8: Base = AArch64_B0; break; |
2708 | 69 | case 16: Base = AArch64_H0; break; |
2709 | 188 | case 32: Base = AArch64_S0; break; |
2710 | 505 | case 64: Base = AArch64_D0; break; |
2711 | 7 | case 128: Base = AArch64_Q0; break; |
2712 | 798 | } |
2713 | | |
2714 | 798 | Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) - AArch64_Z0 + Base; |
2715 | | |
2716 | 798 | SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); |
2717 | | |
2718 | 798 | if (MI->csh->detail) { |
2719 | 798 | #ifndef CAPSTONE_DIET |
2720 | 798 | uint8_t access; |
2721 | | |
2722 | 798 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
2723 | 798 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; |
2724 | 798 | MI->ac_idx++; |
2725 | 798 | #endif |
2726 | 798 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; |
2727 | 798 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; |
2728 | 798 | MI->flat_insn->detail->arm64.op_count++; |
2729 | 798 | } |
2730 | 798 | } |
2731 | | |
2732 | | static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1) |
2733 | 134 | { |
2734 | 134 | const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0); |
2735 | 134 | const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1); |
2736 | 134 | unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
2737 | | |
2738 | 134 | SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr); |
2739 | 134 | } |
2740 | | |
2741 | | static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) |
2742 | 2.52k | { |
2743 | 2.52k | unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
2744 | | |
2745 | 2.52k | SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName)); |
2746 | 2.52k | } |
2747 | | |
2748 | | static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) |
2749 | 631 | { |
2750 | 631 | unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
2751 | | |
2752 | 631 | SStream_concat0(O, getRegisterName(MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0), AArch64_NoRegAltName)); |
2753 | 631 | } |
2754 | | |
2755 | | #define PRINT_ALIAS_INSTR |
2756 | | #include "AArch64GenAsmWriter.inc" |
2757 | | #include "AArch64GenRegisterName.inc" |
2758 | | |
2759 | | void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) |
2760 | 180k | { |
2761 | 180k | if (((cs_struct *)handle)->detail != CS_OPT_ON) |
2762 | 0 | return; |
2763 | | |
2764 | 180k | if (mci->csh->detail) { |
2765 | 180k | unsigned opcode = MCInst_getOpcode(mci); |
2766 | | |
2767 | 180k | switch (opcode) { |
2768 | 154k | default: |
2769 | 154k | break; |
2770 | 154k | case AArch64_LD1Fourv16b_POST: |
2771 | 61 | case AArch64_LD1Fourv1d_POST: |
2772 | 141 | case AArch64_LD1Fourv2d_POST: |
2773 | 213 | case AArch64_LD1Fourv2s_POST: |
2774 | 253 | case AArch64_LD1Fourv4h_POST: |
2775 | 354 | case AArch64_LD1Fourv4s_POST: |
2776 | 380 | case AArch64_LD1Fourv8b_POST: |
2777 | 930 | case AArch64_LD1Fourv8h_POST: |
2778 | 948 | case AArch64_LD1Onev16b_POST: |
2779 | 965 | case AArch64_LD1Onev1d_POST: |
2780 | 987 | case AArch64_LD1Onev2d_POST: |
2781 | 1.06k | case AArch64_LD1Onev2s_POST: |
2782 | 1.12k | case AArch64_LD1Onev4h_POST: |
2783 | 1.18k | case AArch64_LD1Onev4s_POST: |
2784 | 1.26k | case AArch64_LD1Onev8b_POST: |
2785 | 1.36k | case AArch64_LD1Onev8h_POST: |
2786 | 1.37k | case AArch64_LD1Rv16b_POST: |
2787 | 1.39k | case AArch64_LD1Rv1d_POST: |
2788 | 1.56k | case AArch64_LD1Rv2d_POST: |
2789 | 1.57k | case AArch64_LD1Rv2s_POST: |
2790 | 1.62k | case AArch64_LD1Rv4h_POST: |
2791 | 1.68k | case AArch64_LD1Rv4s_POST: |
2792 | 1.71k | case AArch64_LD1Rv8b_POST: |
2793 | 1.73k | case AArch64_LD1Rv8h_POST: |
2794 | 1.80k | case AArch64_LD1Threev16b_POST: |
2795 | 1.83k | case AArch64_LD1Threev1d_POST: |
2796 | 1.94k | case AArch64_LD1Threev2d_POST: |
2797 | 2.27k | case AArch64_LD1Threev2s_POST: |
2798 | 2.87k | case AArch64_LD1Threev4h_POST: |
2799 | 3.42k | case AArch64_LD1Threev4s_POST: |
2800 | 3.48k | case AArch64_LD1Threev8b_POST: |
2801 | 3.61k | case AArch64_LD1Threev8h_POST: |
2802 | 3.69k | case AArch64_LD1Twov16b_POST: |
2803 | 3.71k | case AArch64_LD1Twov1d_POST: |
2804 | 3.79k | case AArch64_LD1Twov2d_POST: |
2805 | 3.80k | case AArch64_LD1Twov2s_POST: |
2806 | 3.85k | case AArch64_LD1Twov4h_POST: |
2807 | 3.96k | case AArch64_LD1Twov4s_POST: |
2808 | 4.31k | case AArch64_LD1Twov8b_POST: |
2809 | 4.34k | case AArch64_LD1Twov8h_POST: |
2810 | 4.47k | case AArch64_LD1i16_POST: |
2811 | 4.67k | case AArch64_LD1i32_POST: |
2812 | 4.81k | case AArch64_LD1i64_POST: |
2813 | 5.83k | case AArch64_LD1i8_POST: |
2814 | 5.84k | case AArch64_LD2Rv16b_POST: |
2815 | 5.85k | case AArch64_LD2Rv1d_POST: |
2816 | 5.87k | case AArch64_LD2Rv2d_POST: |
2817 | 5.90k | case AArch64_LD2Rv2s_POST: |
2818 | 5.90k | case AArch64_LD2Rv4h_POST: |
2819 | 5.92k | case AArch64_LD2Rv4s_POST: |
2820 | 5.93k | case AArch64_LD2Rv8b_POST: |
2821 | 5.98k | case AArch64_LD2Rv8h_POST: |
2822 | 6.07k | case AArch64_LD2Twov16b_POST: |
2823 | 6.17k | case AArch64_LD2Twov2d_POST: |
2824 | 6.20k | case AArch64_LD2Twov2s_POST: |
2825 | 6.21k | case AArch64_LD2Twov4h_POST: |
2826 | 6.30k | case AArch64_LD2Twov4s_POST: |
2827 | 6.33k | case AArch64_LD2Twov8b_POST: |
2828 | 6.34k | case AArch64_LD2Twov8h_POST: |
2829 | 6.40k | case AArch64_LD2i16_POST: |
2830 | 6.55k | case AArch64_LD2i32_POST: |
2831 | 6.69k | case AArch64_LD2i64_POST: |
2832 | 6.80k | case AArch64_LD2i8_POST: |
2833 | 6.81k | case AArch64_LD3Rv16b_POST: |
2834 | 6.86k | case AArch64_LD3Rv1d_POST: |
2835 | 7.13k | case AArch64_LD3Rv2d_POST: |
2836 | 7.46k | case AArch64_LD3Rv2s_POST: |
2837 | 7.51k | case AArch64_LD3Rv4h_POST: |
2838 | 7.54k | case AArch64_LD3Rv4s_POST: |
2839 | 7.57k | case AArch64_LD3Rv8b_POST: |
2840 | 7.91k | case AArch64_LD3Rv8h_POST: |
2841 | 7.92k | case AArch64_LD3Threev16b_POST: |
2842 | 8.11k | case AArch64_LD3Threev2d_POST: |
2843 | 8.13k | case AArch64_LD3Threev2s_POST: |
2844 | 8.40k | case AArch64_LD3Threev4h_POST: |
2845 | 8.41k | case AArch64_LD3Threev4s_POST: |
2846 | 8.42k | case AArch64_LD3Threev8b_POST: |
2847 | 8.48k | case AArch64_LD3Threev8h_POST: |
2848 | 8.58k | case AArch64_LD3i16_POST: |
2849 | 8.68k | case AArch64_LD3i32_POST: |
2850 | 8.99k | case AArch64_LD3i64_POST: |
2851 | 9.19k | case AArch64_LD3i8_POST: |
2852 | 9.24k | case AArch64_LD4Fourv16b_POST: |
2853 | 9.28k | case AArch64_LD4Fourv2d_POST: |
2854 | 9.31k | case AArch64_LD4Fourv2s_POST: |
2855 | 9.99k | case AArch64_LD4Fourv4h_POST: |
2856 | 10.0k | case AArch64_LD4Fourv4s_POST: |
2857 | 10.1k | case AArch64_LD4Fourv8b_POST: |
2858 | 10.1k | case AArch64_LD4Fourv8h_POST: |
2859 | 10.1k | case AArch64_LD4Rv16b_POST: |
2860 | 10.2k | case AArch64_LD4Rv1d_POST: |
2861 | 10.2k | case AArch64_LD4Rv2d_POST: |
2862 | 10.3k | case AArch64_LD4Rv2s_POST: |
2863 | 10.3k | case AArch64_LD4Rv4h_POST: |
2864 | 10.3k | case AArch64_LD4Rv4s_POST: |
2865 | 10.4k | case AArch64_LD4Rv8b_POST: |
2866 | 10.4k | case AArch64_LD4Rv8h_POST: |
2867 | 10.4k | case AArch64_LD4i16_POST: |
2868 | 10.5k | case AArch64_LD4i32_POST: |
2869 | 10.6k | case AArch64_LD4i64_POST: |
2870 | 10.7k | case AArch64_LD4i8_POST: |
2871 | 10.8k | case AArch64_LDRBBpost: |
2872 | 10.9k | case AArch64_LDRBpost: |
2873 | 10.9k | case AArch64_LDRDpost: |
2874 | 11.2k | case AArch64_LDRHHpost: |
2875 | 11.2k | case AArch64_LDRHpost: |
2876 | 11.3k | case AArch64_LDRQpost: |
2877 | 11.3k | case AArch64_LDPDpost: |
2878 | 11.9k | case AArch64_LDPQpost: |
2879 | 12.0k | case AArch64_LDPSWpost: |
2880 | 12.2k | case AArch64_LDPSpost: |
2881 | 12.5k | case AArch64_LDPWpost: |
2882 | 12.6k | case AArch64_LDPXpost: |
2883 | 12.6k | case AArch64_ST1Fourv16b_POST: |
2884 | 12.6k | case AArch64_ST1Fourv1d_POST: |
2885 | 12.7k | case AArch64_ST1Fourv2d_POST: |
2886 | 12.7k | case AArch64_ST1Fourv2s_POST: |
2887 | 12.7k | case AArch64_ST1Fourv4h_POST: |
2888 | 12.7k | case AArch64_ST1Fourv4s_POST: |
2889 | 12.9k | case AArch64_ST1Fourv8b_POST: |
2890 | 13.0k | case AArch64_ST1Fourv8h_POST: |
2891 | 13.2k | case AArch64_ST1Onev16b_POST: |
2892 | 13.2k | case AArch64_ST1Onev1d_POST: |
2893 | 13.3k | case AArch64_ST1Onev2d_POST: |
2894 | 13.3k | case AArch64_ST1Onev2s_POST: |
2895 | 13.3k | case AArch64_ST1Onev4h_POST: |
2896 | 13.4k | case AArch64_ST1Onev4s_POST: |
2897 | 13.4k | case AArch64_ST1Onev8b_POST: |
2898 | 13.4k | case AArch64_ST1Onev8h_POST: |
2899 | 13.5k | case AArch64_ST1Threev16b_POST: |
2900 | 13.5k | case AArch64_ST1Threev1d_POST: |
2901 | 13.6k | case AArch64_ST1Threev2d_POST: |
2902 | 13.7k | case AArch64_ST1Threev2s_POST: |
2903 | 13.9k | case AArch64_ST1Threev4h_POST: |
2904 | 13.9k | case AArch64_ST1Threev4s_POST: |
2905 | 14.3k | case AArch64_ST1Threev8b_POST: |
2906 | 14.3k | case AArch64_ST1Threev8h_POST: |
2907 | 14.3k | case AArch64_ST1Twov16b_POST: |
2908 | 14.4k | case AArch64_ST1Twov1d_POST: |
2909 | 14.4k | case AArch64_ST1Twov2d_POST: |
2910 | 14.5k | case AArch64_ST1Twov2s_POST: |
2911 | 14.5k | case AArch64_ST1Twov4h_POST: |
2912 | 14.5k | case AArch64_ST1Twov4s_POST: |
2913 | 14.5k | case AArch64_ST1Twov8b_POST: |
2914 | 14.5k | case AArch64_ST1Twov8h_POST: |
2915 | 14.6k | case AArch64_ST1i16_POST: |
2916 | 14.7k | case AArch64_ST1i32_POST: |
2917 | 15.0k | case AArch64_ST1i64_POST: |
2918 | 15.2k | case AArch64_ST1i8_POST: |
2919 | 15.5k | case AArch64_ST2GPostIndex: |
2920 | 15.5k | case AArch64_ST2Twov16b_POST: |
2921 | 15.5k | case AArch64_ST2Twov2d_POST: |
2922 | 15.6k | case AArch64_ST2Twov2s_POST: |
2923 | 15.8k | case AArch64_ST2Twov4h_POST: |
2924 | 15.8k | case AArch64_ST2Twov4s_POST: |
2925 | 15.9k | case AArch64_ST2Twov8b_POST: |
2926 | 15.9k | case AArch64_ST2Twov8h_POST: |
2927 | 15.9k | case AArch64_ST2i16_POST: |
2928 | 16.0k | case AArch64_ST2i32_POST: |
2929 | 16.2k | case AArch64_ST2i64_POST: |
2930 | 16.4k | case AArch64_ST2i8_POST: |
2931 | 16.4k | case AArch64_ST3Threev16b_POST: |
2932 | 16.6k | case AArch64_ST3Threev2d_POST: |
2933 | 16.8k | case AArch64_ST3Threev2s_POST: |
2934 | 16.8k | case AArch64_ST3Threev4h_POST: |
2935 | 16.8k | case AArch64_ST3Threev4s_POST: |
2936 | 16.9k | case AArch64_ST3Threev8b_POST: |
2937 | 16.9k | case AArch64_ST3Threev8h_POST: |
2938 | 17.0k | case AArch64_ST3i16_POST: |
2939 | 17.0k | case AArch64_ST3i32_POST: |
2940 | 17.1k | case AArch64_ST3i64_POST: |
2941 | 17.3k | case AArch64_ST3i8_POST: |
2942 | 17.3k | case AArch64_ST4Fourv16b_POST: |
2943 | 17.4k | case AArch64_ST4Fourv2d_POST: |
2944 | 17.4k | case AArch64_ST4Fourv2s_POST: |
2945 | 17.5k | case AArch64_ST4Fourv4h_POST: |
2946 | 17.5k | case AArch64_ST4Fourv4s_POST: |
2947 | 17.5k | case AArch64_ST4Fourv8b_POST: |
2948 | 17.5k | case AArch64_ST4Fourv8h_POST: |
2949 | 17.6k | case AArch64_ST4i16_POST: |
2950 | 17.7k | case AArch64_ST4i32_POST: |
2951 | 17.9k | case AArch64_ST4i64_POST: |
2952 | 18.0k | case AArch64_ST4i8_POST: |
2953 | 19.2k | case AArch64_STPDpost: |
2954 | 19.7k | case AArch64_STPQpost: |
2955 | 19.8k | case AArch64_STPSpost: |
2956 | 20.1k | case AArch64_STPWpost: |
2957 | 20.8k | case AArch64_STPXpost: |
2958 | 20.8k | case AArch64_STRBBpost: |
2959 | 20.9k | case AArch64_STRBpost: |
2960 | 20.9k | case AArch64_STRDpost: |
2961 | 21.1k | case AArch64_STRHHpost: |
2962 | 21.1k | case AArch64_STRHpost: |
2963 | 21.2k | case AArch64_STRQpost: |
2964 | 21.2k | case AArch64_STRSpost: |
2965 | 21.2k | case AArch64_STRWpost: |
2966 | 21.4k | case AArch64_STRXpost: |
2967 | 21.5k | case AArch64_STZ2GPostIndex: |
2968 | 21.5k | case AArch64_STZGPostIndex: |
2969 | 21.6k | case AArch64_STGPostIndex: |
2970 | 21.6k | case AArch64_STGPpost: |
2971 | 21.6k | case AArch64_LDRSBWpost: |
2972 | 21.7k | case AArch64_LDRSBXpost: |
2973 | 21.7k | case AArch64_LDRSHWpost: |
2974 | 21.8k | case AArch64_LDRSHXpost: |
2975 | 21.8k | case AArch64_LDRSWpost: |
2976 | 21.8k | case AArch64_LDRSpost: |
2977 | 21.8k | case AArch64_LDRWpost: |
2978 | 21.9k | case AArch64_LDRXpost: |
2979 | 21.9k | flat_insn->detail->arm64.writeback = true; |
2980 | 21.9k | flat_insn->detail->arm64.post_index = true; |
2981 | 21.9k | break; |
2982 | 62 | case AArch64_LDRAAwriteback: |
2983 | 492 | case AArch64_LDRABwriteback: |
2984 | 519 | case AArch64_ST2GPreIndex: |
2985 | 571 | case AArch64_LDPDpre: |
2986 | 618 | case AArch64_LDPQpre: |
2987 | 636 | case AArch64_LDPSWpre: |
2988 | 688 | case AArch64_LDPSpre: |
2989 | 721 | case AArch64_LDPWpre: |
2990 | 868 | case AArch64_LDPXpre: |
2991 | 926 | case AArch64_LDRBBpre: |
2992 | 950 | case AArch64_LDRBpre: |
2993 | 981 | case AArch64_LDRDpre: |
2994 | 1.10k | case AArch64_LDRHHpre: |
2995 | 1.42k | case AArch64_LDRHpre: |
2996 | 1.44k | case AArch64_LDRQpre: |
2997 | 1.46k | case AArch64_LDRSBWpre: |
2998 | 1.49k | case AArch64_LDRSBXpre: |
2999 | 2.04k | case AArch64_LDRSHWpre: |
3000 | 2.20k | case AArch64_LDRSHXpre: |
3001 | 2.22k | case AArch64_LDRSWpre: |
3002 | 2.24k | case AArch64_LDRSpre: |
3003 | 2.27k | case AArch64_LDRWpre: |
3004 | 2.32k | case AArch64_LDRXpre: |
3005 | 2.38k | case AArch64_STGPreIndex: |
3006 | 2.49k | case AArch64_STPDpre: |
3007 | 2.98k | case AArch64_STPQpre: |
3008 | 3.08k | case AArch64_STPSpre: |
3009 | 3.11k | case AArch64_STPWpre: |
3010 | 3.52k | case AArch64_STPXpre: |
3011 | 3.55k | case AArch64_STRBBpre: |
3012 | 3.67k | case AArch64_STRBpre: |
3013 | 3.69k | case AArch64_STRDpre: |
3014 | 3.79k | case AArch64_STRHHpre: |
3015 | 3.80k | case AArch64_STRHpre: |
3016 | 3.83k | case AArch64_STRQpre: |
3017 | 3.85k | case AArch64_STRSpre: |
3018 | 3.89k | case AArch64_STRWpre: |
3019 | 4.00k | case AArch64_STRXpre: |
3020 | 4.12k | case AArch64_STZ2GPreIndex: |
3021 | 4.19k | case AArch64_STZGPreIndex: |
3022 | 4.19k | case AArch64_STGPpre: |
3023 | 4.19k | flat_insn->detail->arm64.writeback = true; |
3024 | 4.19k | break; |
3025 | 180k | } |
3026 | 180k | } |
3027 | 180k | } |
3028 | | |
3029 | | #endif |