/src/capstonev5/arch/ARM/ARMGenAsmWriter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ |
3 | | |
4 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
5 | | |* *| |
6 | | |* Assembly Writer Source Fragment *| |
7 | | |* *| |
8 | | |* Automatically generated file, do not edit! *| |
9 | | |* *| |
10 | | \*===----------------------------------------------------------------------===*/ |
11 | | |
12 | | /// printInstruction - This method is automatically generated by tablegen |
13 | | /// from the instruction set description. |
14 | | static void printInstruction(MCInst *MI, SStream *O) |
15 | 1.35M | { |
16 | 1.35M | #ifndef CAPSTONE_DIET |
17 | 1.35M | static const char AsmStrs[] = { |
18 | 1.35M | /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, |
19 | 1.35M | /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, |
20 | 1.35M | /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, |
21 | 1.35M | /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, |
22 | 1.35M | /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, |
23 | 1.35M | /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, |
24 | 1.35M | /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, |
25 | 1.35M | /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, |
26 | 1.35M | /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, |
27 | 1.35M | /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, |
28 | 1.35M | /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, |
29 | 1.35M | /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, |
30 | 1.35M | /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, |
31 | 1.35M | /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, |
32 | 1.35M | /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, |
33 | 1.35M | /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, |
34 | 1.35M | /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, |
35 | 1.35M | /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, |
36 | 1.35M | /* 237 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '3', '2', 9, 0, |
37 | 1.35M | /* 248 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, |
38 | 1.35M | /* 260 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '3', '2', 9, 0, |
39 | 1.35M | /* 271 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, |
40 | 1.35M | /* 283 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, |
41 | 1.35M | /* 295 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, |
42 | 1.35M | /* 307 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, |
43 | 1.35M | /* 319 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, |
44 | 1.35M | /* 331 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, |
45 | 1.35M | /* 343 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, |
46 | 1.35M | /* 355 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, |
47 | 1.35M | /* 367 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, |
48 | 1.35M | /* 379 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, |
49 | 1.35M | /* 391 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, |
50 | 1.35M | /* 403 */ 'l', 'd', 'c', '2', 9, 0, |
51 | 1.35M | /* 409 */ 'm', 'r', 'c', '2', 9, 0, |
52 | 1.35M | /* 415 */ 'm', 'r', 'r', 'c', '2', 9, 0, |
53 | 1.35M | /* 422 */ 's', 't', 'c', '2', 9, 0, |
54 | 1.35M | /* 428 */ 'c', 'd', 'p', '2', 9, 0, |
55 | 1.35M | /* 434 */ 'm', 'c', 'r', '2', 9, 0, |
56 | 1.35M | /* 440 */ 'm', 'c', 'r', 'r', '2', 9, 0, |
57 | 1.35M | /* 447 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, |
58 | 1.35M | /* 462 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, |
59 | 1.35M | /* 477 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, |
60 | 1.35M | /* 492 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, |
61 | 1.35M | /* 507 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, |
62 | 1.35M | /* 522 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, |
63 | 1.35M | /* 537 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, |
64 | 1.35M | /* 552 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, |
65 | 1.35M | /* 567 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, |
66 | 1.35M | /* 579 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, |
67 | 1.35M | /* 591 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, |
68 | 1.35M | /* 603 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, |
69 | 1.35M | /* 615 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, |
70 | 1.35M | /* 627 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, |
71 | 1.35M | /* 639 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, |
72 | 1.35M | /* 651 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, |
73 | 1.35M | /* 663 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, |
74 | 1.35M | /* 675 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, |
75 | 1.35M | /* 687 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, |
76 | 1.35M | /* 698 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, |
77 | 1.35M | /* 713 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, |
78 | 1.35M | /* 728 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, |
79 | 1.35M | /* 743 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, |
80 | 1.35M | /* 758 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, |
81 | 1.35M | /* 773 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, |
82 | 1.35M | /* 788 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, |
83 | 1.35M | /* 803 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, |
84 | 1.35M | /* 818 */ 'v', 'c', 'v', 't', 'a', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, |
85 | 1.35M | /* 833 */ 'v', 'c', 'v', 't', 'm', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, |
86 | 1.35M | /* 848 */ 'v', 'c', 'v', 't', 'n', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, |
87 | 1.35M | /* 863 */ 'v', 'c', 'v', 't', 'p', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, |
88 | 1.35M | /* 878 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, |
89 | 1.35M | /* 893 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, |
90 | 1.35M | /* 908 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, |
91 | 1.35M | /* 923 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, |
92 | 1.35M | /* 938 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '1', '6', 9, 0, |
93 | 1.35M | /* 949 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '1', '6', 9, 0, |
94 | 1.35M | /* 961 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '1', '6', 9, 0, |
95 | 1.35M | /* 972 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '1', '6', 9, 0, |
96 | 1.35M | /* 984 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '1', '6', 9, 0, |
97 | 1.35M | /* 996 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '1', '6', 9, 0, |
98 | 1.35M | /* 1008 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '1', '6', 9, 0, |
99 | 1.35M | /* 1020 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '1', '6', 9, 0, |
100 | 1.35M | /* 1032 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '1', '6', 9, 0, |
101 | 1.35M | /* 1044 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '1', '6', 9, 0, |
102 | 1.35M | /* 1056 */ 'v', 'i', 'n', 's', '.', 'f', '1', '6', 9, 0, |
103 | 1.35M | /* 1066 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '1', '6', 9, 0, |
104 | 1.35M | /* 1078 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '1', '6', 9, 0, |
105 | 1.35M | /* 1090 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '1', '6', 9, 0, |
106 | 1.35M | /* 1102 */ 'v', 'm', 'o', 'v', 'x', '.', 'f', '1', '6', 9, 0, |
107 | 1.35M | /* 1113 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '1', '6', 9, 0, |
108 | 1.35M | /* 1125 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0, |
109 | 1.35M | /* 1135 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0, |
110 | 1.35M | /* 1144 */ 'a', 'e', 's', 'd', '.', '8', 9, 0, |
111 | 1.35M | /* 1152 */ 'a', 'e', 's', 'e', '.', '8', 9, 0, |
112 | 1.35M | /* 1160 */ 'v', 's', 'd', 'o', 't', '.', 's', '8', 9, 0, |
113 | 1.35M | /* 1170 */ 'v', 'u', 'd', 'o', 't', '.', 'u', '8', 9, 0, |
114 | 1.35M | /* 1180 */ 'r', 'f', 'e', 'd', 'a', 9, 0, |
115 | 1.35M | /* 1187 */ 'r', 'f', 'e', 'i', 'a', 9, 0, |
116 | 1.35M | /* 1194 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, |
117 | 1.35M | /* 1202 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, |
118 | 1.35M | /* 1211 */ 'r', 'f', 'e', 'd', 'b', 9, 0, |
119 | 1.35M | /* 1218 */ 'r', 'f', 'e', 'i', 'b', 9, 0, |
120 | 1.35M | /* 1225 */ 'd', 'm', 'b', 9, 0, |
121 | 1.35M | /* 1230 */ 'd', 's', 'b', 9, 0, |
122 | 1.35M | /* 1235 */ 'i', 's', 'b', 9, 0, |
123 | 1.35M | /* 1240 */ 't', 's', 'b', 9, 0, |
124 | 1.35M | /* 1245 */ 'h', 'v', 'c', 9, 0, |
125 | 1.35M | /* 1250 */ 'p', 'l', 'd', 9, 0, |
126 | 1.35M | /* 1255 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0, |
127 | 1.35M | /* 1263 */ 'u', 'd', 'f', 9, 0, |
128 | 1.35M | /* 1268 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, |
129 | 1.35M | /* 1276 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, |
130 | 1.35M | /* 1285 */ 'p', 'l', 'i', 9, 0, |
131 | 1.35M | /* 1290 */ 'l', 'd', 'c', '2', 'l', 9, 0, |
132 | 1.35M | /* 1297 */ 's', 't', 'c', '2', 'l', 9, 0, |
133 | 1.35M | /* 1304 */ 'b', 'l', 9, 0, |
134 | 1.35M | /* 1308 */ 's', 'e', 't', 'p', 'a', 'n', 9, 0, |
135 | 1.35M | /* 1316 */ 'c', 'p', 's', 9, 0, |
136 | 1.35M | /* 1321 */ 'm', 'o', 'v', 's', 9, 0, |
137 | 1.35M | /* 1327 */ 'h', 'l', 't', 9, 0, |
138 | 1.35M | /* 1332 */ 'b', 'k', 'p', 't', 9, 0, |
139 | 1.35M | /* 1338 */ 'h', 'v', 'c', '.', 'w', 9, 0, |
140 | 1.35M | /* 1345 */ 'u', 'd', 'f', '.', 'w', 9, 0, |
141 | 1.35M | /* 1352 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, |
142 | 1.35M | /* 1360 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, |
143 | 1.35M | /* 1369 */ 'p', 'l', 'd', 'w', 9, 0, |
144 | 1.35M | /* 1375 */ 'b', 'x', 9, 0, |
145 | 1.35M | /* 1379 */ 'b', 'l', 'x', 9, 0, |
146 | 1.35M | /* 1384 */ 'c', 'b', 'z', 9, 0, |
147 | 1.35M | /* 1389 */ 'c', 'b', 'n', 'z', 9, 0, |
148 | 1.35M | /* 1395 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0, |
149 | 1.35M | /* 1407 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0, |
150 | 1.35M | /* 1419 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0, |
151 | 1.35M | /* 1431 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0, |
152 | 1.35M | /* 1443 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0, |
153 | 1.35M | /* 1454 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0, |
154 | 1.35M | /* 1465 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0, |
155 | 1.35M | /* 1476 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0, |
156 | 1.35M | /* 1487 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
157 | 1.35M | /* 1518 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
158 | 1.35M | /* 1542 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
159 | 1.35M | /* 1567 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, |
160 | 1.35M | /* 1590 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
161 | 1.35M | /* 1613 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, |
162 | 1.35M | /* 1635 */ '_', '_', 'b', 'r', 'k', 'd', 'i', 'v', '0', 0, |
163 | 1.35M | /* 1645 */ 'v', 'l', 'd', '1', 0, |
164 | 1.35M | /* 1650 */ 'd', 'c', 'p', 's', '1', 0, |
165 | 1.35M | /* 1656 */ 'v', 's', 't', '1', 0, |
166 | 1.35M | /* 1661 */ 'v', 'r', 'e', 'v', '3', '2', 0, |
167 | 1.35M | /* 1668 */ 'l', 'd', 'c', '2', 0, |
168 | 1.35M | /* 1673 */ 'm', 'r', 'c', '2', 0, |
169 | 1.35M | /* 1678 */ 'm', 'r', 'r', 'c', '2', 0, |
170 | 1.35M | /* 1684 */ 's', 't', 'c', '2', 0, |
171 | 1.35M | /* 1689 */ 'v', 'l', 'd', '2', 0, |
172 | 1.35M | /* 1694 */ 'c', 'd', 'p', '2', 0, |
173 | 1.35M | /* 1699 */ 'm', 'c', 'r', '2', 0, |
174 | 1.35M | /* 1704 */ 'm', 'c', 'r', 'r', '2', 0, |
175 | 1.35M | /* 1710 */ 'd', 'c', 'p', 's', '2', 0, |
176 | 1.35M | /* 1716 */ 'v', 's', 't', '2', 0, |
177 | 1.35M | /* 1721 */ 'v', 'l', 'd', '3', 0, |
178 | 1.35M | /* 1726 */ 'd', 'c', 'p', 's', '3', 0, |
179 | 1.35M | /* 1732 */ 'v', 's', 't', '3', 0, |
180 | 1.35M | /* 1737 */ 'v', 'r', 'e', 'v', '6', '4', 0, |
181 | 1.35M | /* 1744 */ 'v', 'l', 'd', '4', 0, |
182 | 1.35M | /* 1749 */ 'v', 's', 't', '4', 0, |
183 | 1.35M | /* 1754 */ 's', 'x', 't', 'a', 'b', '1', '6', 0, |
184 | 1.35M | /* 1762 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0, |
185 | 1.35M | /* 1770 */ 's', 'x', 't', 'b', '1', '6', 0, |
186 | 1.35M | /* 1777 */ 'u', 'x', 't', 'b', '1', '6', 0, |
187 | 1.35M | /* 1784 */ 's', 'h', 's', 'u', 'b', '1', '6', 0, |
188 | 1.35M | /* 1792 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0, |
189 | 1.35M | /* 1800 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0, |
190 | 1.35M | /* 1808 */ 's', 's', 'u', 'b', '1', '6', 0, |
191 | 1.35M | /* 1815 */ 'u', 's', 'u', 'b', '1', '6', 0, |
192 | 1.35M | /* 1822 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0, |
193 | 1.35M | /* 1830 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0, |
194 | 1.35M | /* 1838 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0, |
195 | 1.35M | /* 1846 */ 's', 'a', 'd', 'd', '1', '6', 0, |
196 | 1.35M | /* 1853 */ 'u', 'a', 'd', 'd', '1', '6', 0, |
197 | 1.35M | /* 1860 */ 's', 's', 'a', 't', '1', '6', 0, |
198 | 1.35M | /* 1867 */ 'u', 's', 'a', 't', '1', '6', 0, |
199 | 1.35M | /* 1874 */ 'v', 'r', 'e', 'v', '1', '6', 0, |
200 | 1.35M | /* 1881 */ 'u', 's', 'a', 'd', 'a', '8', 0, |
201 | 1.35M | /* 1888 */ 's', 'h', 's', 'u', 'b', '8', 0, |
202 | 1.35M | /* 1895 */ 'u', 'h', 's', 'u', 'b', '8', 0, |
203 | 1.35M | /* 1902 */ 'u', 'q', 's', 'u', 'b', '8', 0, |
204 | 1.35M | /* 1909 */ 's', 's', 'u', 'b', '8', 0, |
205 | 1.35M | /* 1915 */ 'u', 's', 'u', 'b', '8', 0, |
206 | 1.35M | /* 1921 */ 'u', 's', 'a', 'd', '8', 0, |
207 | 1.35M | /* 1927 */ 's', 'h', 'a', 'd', 'd', '8', 0, |
208 | 1.35M | /* 1934 */ 'u', 'h', 'a', 'd', 'd', '8', 0, |
209 | 1.35M | /* 1941 */ 'u', 'q', 'a', 'd', 'd', '8', 0, |
210 | 1.35M | /* 1948 */ 's', 'a', 'd', 'd', '8', 0, |
211 | 1.35M | /* 1954 */ 'u', 'a', 'd', 'd', '8', 0, |
212 | 1.35M | /* 1960 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
213 | 1.35M | /* 1973 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
214 | 1.35M | /* 1980 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
215 | 1.35M | /* 1990 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
216 | 1.35M | /* 2000 */ '@', 32, 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', 32, 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, |
217 | 1.35M | /* 2019 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
218 | 1.35M | /* 2034 */ 'v', 'a', 'b', 'a', 0, |
219 | 1.35M | /* 2039 */ 'l', 'd', 'a', 0, |
220 | 1.35M | /* 2043 */ 'l', 'd', 'm', 'd', 'a', 0, |
221 | 1.35M | /* 2049 */ 's', 't', 'm', 'd', 'a', 0, |
222 | 1.35M | /* 2055 */ 'r', 'f', 'e', 'i', 'a', 0, |
223 | 1.35M | /* 2061 */ 'v', 'l', 'd', 'm', 'i', 'a', 0, |
224 | 1.35M | /* 2068 */ 'v', 's', 't', 'm', 'i', 'a', 0, |
225 | 1.35M | /* 2075 */ 's', 'r', 's', 'i', 'a', 0, |
226 | 1.35M | /* 2081 */ 's', 'm', 'm', 'l', 'a', 0, |
227 | 1.35M | /* 2087 */ 'v', 'n', 'm', 'l', 'a', 0, |
228 | 1.35M | /* 2093 */ 'v', 'm', 'l', 'a', 0, |
229 | 1.35M | /* 2098 */ 'v', 'f', 'm', 'a', 0, |
230 | 1.35M | /* 2103 */ 'v', 'f', 'n', 'm', 'a', 0, |
231 | 1.35M | /* 2109 */ 'v', 'r', 's', 'r', 'a', 0, |
232 | 1.35M | /* 2115 */ 'v', 's', 'r', 'a', 0, |
233 | 1.35M | /* 2120 */ 't', 't', 'a', 0, |
234 | 1.35M | /* 2124 */ 'l', 'd', 'a', 'b', 0, |
235 | 1.35M | /* 2129 */ 's', 'x', 't', 'a', 'b', 0, |
236 | 1.35M | /* 2135 */ 'u', 'x', 't', 'a', 'b', 0, |
237 | 1.35M | /* 2141 */ 's', 'm', 'l', 'a', 'b', 'b', 0, |
238 | 1.35M | /* 2148 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0, |
239 | 1.35M | /* 2156 */ 's', 'm', 'u', 'l', 'b', 'b', 0, |
240 | 1.35M | /* 2163 */ 't', 'b', 'b', 0, |
241 | 1.35M | /* 2167 */ 'r', 'f', 'e', 'd', 'b', 0, |
242 | 1.35M | /* 2173 */ 'v', 'l', 'd', 'm', 'd', 'b', 0, |
243 | 1.35M | /* 2180 */ 'v', 's', 't', 'm', 'd', 'b', 0, |
244 | 1.35M | /* 2187 */ 's', 'r', 's', 'd', 'b', 0, |
245 | 1.35M | /* 2193 */ 'l', 'd', 'm', 'i', 'b', 0, |
246 | 1.35M | /* 2199 */ 's', 't', 'm', 'i', 'b', 0, |
247 | 1.35M | /* 2205 */ 's', 't', 'l', 'b', 0, |
248 | 1.35M | /* 2210 */ 'd', 'm', 'b', 0, |
249 | 1.35M | /* 2214 */ 's', 'w', 'p', 'b', 0, |
250 | 1.35M | /* 2219 */ 'l', 'd', 'r', 'b', 0, |
251 | 1.35M | /* 2224 */ 's', 't', 'r', 'b', 0, |
252 | 1.35M | /* 2229 */ 'd', 's', 'b', 0, |
253 | 1.35M | /* 2233 */ 'i', 's', 'b', 0, |
254 | 1.35M | /* 2237 */ 'l', 'd', 'r', 's', 'b', 0, |
255 | 1.35M | /* 2243 */ 't', 's', 'b', 0, |
256 | 1.35M | /* 2247 */ 's', 'm', 'l', 'a', 't', 'b', 0, |
257 | 1.35M | /* 2254 */ 'p', 'k', 'h', 't', 'b', 0, |
258 | 1.35M | /* 2260 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0, |
259 | 1.35M | /* 2268 */ 's', 'm', 'u', 'l', 't', 'b', 0, |
260 | 1.35M | /* 2275 */ 'v', 'c', 'v', 't', 'b', 0, |
261 | 1.35M | /* 2281 */ 's', 'x', 't', 'b', 0, |
262 | 1.35M | /* 2286 */ 'u', 'x', 't', 'b', 0, |
263 | 1.35M | /* 2291 */ 'q', 'd', 's', 'u', 'b', 0, |
264 | 1.35M | /* 2297 */ 'v', 'h', 's', 'u', 'b', 0, |
265 | 1.35M | /* 2303 */ 'v', 'q', 's', 'u', 'b', 0, |
266 | 1.35M | /* 2309 */ 'v', 's', 'u', 'b', 0, |
267 | 1.35M | /* 2314 */ 's', 'm', 'l', 'a', 'w', 'b', 0, |
268 | 1.35M | /* 2321 */ 's', 'm', 'u', 'l', 'w', 'b', 0, |
269 | 1.35M | /* 2328 */ 'l', 'd', 'a', 'e', 'x', 'b', 0, |
270 | 1.35M | /* 2335 */ 's', 't', 'l', 'e', 'x', 'b', 0, |
271 | 1.35M | /* 2342 */ 'l', 'd', 'r', 'e', 'x', 'b', 0, |
272 | 1.35M | /* 2349 */ 's', 't', 'r', 'e', 'x', 'b', 0, |
273 | 1.35M | /* 2356 */ 's', 'b', 'c', 0, |
274 | 1.35M | /* 2360 */ 'a', 'd', 'c', 0, |
275 | 1.35M | /* 2364 */ 'l', 'd', 'c', 0, |
276 | 1.35M | /* 2368 */ 'b', 'f', 'c', 0, |
277 | 1.35M | /* 2372 */ 'v', 'b', 'i', 'c', 0, |
278 | 1.35M | /* 2377 */ 's', 'm', 'c', 0, |
279 | 1.35M | /* 2381 */ 'm', 'r', 'c', 0, |
280 | 1.35M | /* 2385 */ 'm', 'r', 'r', 'c', 0, |
281 | 1.35M | /* 2390 */ 'r', 's', 'c', 0, |
282 | 1.35M | /* 2394 */ 's', 't', 'c', 0, |
283 | 1.35M | /* 2398 */ 's', 'v', 'c', 0, |
284 | 1.35M | /* 2402 */ 's', 'm', 'l', 'a', 'd', 0, |
285 | 1.35M | /* 2408 */ 's', 'm', 'u', 'a', 'd', 0, |
286 | 1.35M | /* 2414 */ 'v', 'a', 'b', 'd', 0, |
287 | 1.35M | /* 2419 */ 'q', 'd', 'a', 'd', 'd', 0, |
288 | 1.35M | /* 2425 */ 'v', 'r', 'h', 'a', 'd', 'd', 0, |
289 | 1.35M | /* 2432 */ 'v', 'h', 'a', 'd', 'd', 0, |
290 | 1.35M | /* 2438 */ 'v', 'p', 'a', 'd', 'd', 0, |
291 | 1.35M | /* 2444 */ 'v', 'q', 'a', 'd', 'd', 0, |
292 | 1.35M | /* 2450 */ 'v', 'a', 'd', 'd', 0, |
293 | 1.35M | /* 2455 */ 's', 'm', 'l', 'a', 'l', 'd', 0, |
294 | 1.35M | /* 2462 */ 'p', 'l', 'd', 0, |
295 | 1.35M | /* 2466 */ 's', 'm', 'l', 's', 'l', 'd', 0, |
296 | 1.35M | /* 2473 */ 'v', 'a', 'n', 'd', 0, |
297 | 1.35M | /* 2478 */ 'l', 'd', 'r', 'd', 0, |
298 | 1.35M | /* 2483 */ 's', 't', 'r', 'd', 0, |
299 | 1.35M | /* 2488 */ 's', 'm', 'l', 's', 'd', 0, |
300 | 1.35M | /* 2494 */ 's', 'm', 'u', 's', 'd', 0, |
301 | 1.35M | /* 2500 */ 'l', 'd', 'a', 'e', 'x', 'd', 0, |
302 | 1.35M | /* 2507 */ 's', 't', 'l', 'e', 'x', 'd', 0, |
303 | 1.35M | /* 2514 */ 'l', 'd', 'r', 'e', 'x', 'd', 0, |
304 | 1.35M | /* 2521 */ 's', 't', 'r', 'e', 'x', 'd', 0, |
305 | 1.35M | /* 2528 */ 'v', 'a', 'c', 'g', 'e', 0, |
306 | 1.35M | /* 2534 */ 'v', 'c', 'g', 'e', 0, |
307 | 1.35M | /* 2539 */ 'v', 'c', 'l', 'e', 0, |
308 | 1.35M | /* 2544 */ 'v', 'r', 'e', 'c', 'p', 'e', 0, |
309 | 1.35M | /* 2551 */ 'v', 'c', 'm', 'p', 'e', 0, |
310 | 1.35M | /* 2557 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0, |
311 | 1.35M | /* 2565 */ 'v', 'b', 'i', 'f', 0, |
312 | 1.35M | /* 2570 */ 'd', 'b', 'g', 0, |
313 | 1.35M | /* 2574 */ 'v', 'q', 'n', 'e', 'g', 0, |
314 | 1.35M | /* 2580 */ 'v', 'n', 'e', 'g', 0, |
315 | 1.35M | /* 2585 */ 's', 'g', 0, |
316 | 1.35M | /* 2588 */ 'l', 'd', 'a', 'h', 0, |
317 | 1.35M | /* 2593 */ 'v', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 0, |
318 | 1.35M | /* 2602 */ 's', 'x', 't', 'a', 'h', 0, |
319 | 1.35M | /* 2608 */ 'u', 'x', 't', 'a', 'h', 0, |
320 | 1.35M | /* 2614 */ 't', 'b', 'h', 0, |
321 | 1.35M | /* 2618 */ 's', 't', 'l', 'h', 0, |
322 | 1.35M | /* 2623 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0, |
323 | 1.35M | /* 2631 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0, |
324 | 1.35M | /* 2640 */ 'l', 'd', 'r', 'h', 0, |
325 | 1.35M | /* 2645 */ 's', 't', 'r', 'h', 0, |
326 | 1.35M | /* 2650 */ 'v', 'q', 'r', 'd', 'm', 'l', 's', 'h', 0, |
327 | 1.35M | /* 2659 */ 'l', 'd', 'r', 's', 'h', 0, |
328 | 1.35M | /* 2665 */ 'p', 'u', 's', 'h', 0, |
329 | 1.35M | /* 2670 */ 'r', 'e', 'v', 's', 'h', 0, |
330 | 1.35M | /* 2676 */ 's', 'x', 't', 'h', 0, |
331 | 1.35M | /* 2681 */ 'u', 'x', 't', 'h', 0, |
332 | 1.35M | /* 2686 */ 'l', 'd', 'a', 'e', 'x', 'h', 0, |
333 | 1.35M | /* 2693 */ 's', 't', 'l', 'e', 'x', 'h', 0, |
334 | 1.35M | /* 2700 */ 'l', 'd', 'r', 'e', 'x', 'h', 0, |
335 | 1.35M | /* 2707 */ 's', 't', 'r', 'e', 'x', 'h', 0, |
336 | 1.35M | /* 2714 */ 'b', 'f', 'i', 0, |
337 | 1.35M | /* 2718 */ 'p', 'l', 'i', 0, |
338 | 1.35M | /* 2722 */ 'v', 's', 'l', 'i', 0, |
339 | 1.35M | /* 2727 */ 'v', 's', 'r', 'i', 0, |
340 | 1.35M | /* 2732 */ 'b', 'x', 'j', 0, |
341 | 1.35M | /* 2736 */ 'l', 'd', 'c', '2', 'l', 0, |
342 | 1.35M | /* 2742 */ 's', 't', 'c', '2', 'l', 0, |
343 | 1.35M | /* 2748 */ 'u', 'm', 'a', 'a', 'l', 0, |
344 | 1.35M | /* 2754 */ 'v', 'a', 'b', 'a', 'l', 0, |
345 | 1.35M | /* 2760 */ 'v', 'p', 'a', 'd', 'a', 'l', 0, |
346 | 1.35M | /* 2767 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0, |
347 | 1.35M | /* 2775 */ 's', 'm', 'l', 'a', 'l', 0, |
348 | 1.35M | /* 2781 */ 'u', 'm', 'l', 'a', 'l', 0, |
349 | 1.35M | /* 2787 */ 'v', 'm', 'l', 'a', 'l', 0, |
350 | 1.35M | /* 2793 */ 'v', 't', 'b', 'l', 0, |
351 | 1.35M | /* 2798 */ 'v', 's', 'u', 'b', 'l', 0, |
352 | 1.35M | /* 2804 */ 'l', 'd', 'c', 'l', 0, |
353 | 1.35M | /* 2809 */ 's', 't', 'c', 'l', 0, |
354 | 1.35M | /* 2814 */ 'v', 'a', 'b', 'd', 'l', 0, |
355 | 1.35M | /* 2820 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, |
356 | 1.35M | /* 2827 */ 'v', 'a', 'd', 'd', 'l', 0, |
357 | 1.35M | /* 2833 */ 's', 'e', 'l', 0, |
358 | 1.35M | /* 2837 */ 'v', 'q', 's', 'h', 'l', 0, |
359 | 1.35M | /* 2843 */ 'v', 'q', 'r', 's', 'h', 'l', 0, |
360 | 1.35M | /* 2850 */ 'v', 'r', 's', 'h', 'l', 0, |
361 | 1.35M | /* 2856 */ 'v', 's', 'h', 'l', 0, |
362 | 1.35M | /* 2861 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
363 | 1.35M | /* 2875 */ 'v', 's', 'h', 'l', 'l', 0, |
364 | 1.35M | /* 2881 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, |
365 | 1.35M | /* 2889 */ 's', 'm', 'u', 'l', 'l', 0, |
366 | 1.35M | /* 2895 */ 'u', 'm', 'u', 'l', 'l', 0, |
367 | 1.35M | /* 2901 */ 'v', 'm', 'u', 'l', 'l', 0, |
368 | 1.35M | /* 2907 */ 'v', 'b', 's', 'l', 0, |
369 | 1.35M | /* 2912 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, |
370 | 1.35M | /* 2920 */ 'v', 'm', 'l', 's', 'l', 0, |
371 | 1.35M | /* 2926 */ 's', 't', 'l', 0, |
372 | 1.35M | /* 2930 */ 's', 'm', 'm', 'u', 'l', 0, |
373 | 1.35M | /* 2936 */ 'v', 'n', 'm', 'u', 'l', 0, |
374 | 1.35M | /* 2942 */ 'v', 'm', 'u', 'l', 0, |
375 | 1.35M | /* 2947 */ 'v', 'm', 'o', 'v', 'l', 0, |
376 | 1.35M | /* 2953 */ 'v', 'l', 'l', 'd', 'm', 0, |
377 | 1.35M | /* 2959 */ 'v', 'l', 's', 't', 'm', 0, |
378 | 1.35M | /* 2965 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, |
379 | 1.35M | /* 2973 */ 'v', 's', 'u', 'b', 'h', 'n', 0, |
380 | 1.35M | /* 2980 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, |
381 | 1.35M | /* 2988 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, |
382 | 1.35M | /* 2995 */ 'v', 'p', 'm', 'i', 'n', 0, |
383 | 1.35M | /* 3001 */ 'v', 'm', 'i', 'n', 0, |
384 | 1.35M | /* 3006 */ 'c', 'm', 'n', 0, |
385 | 1.35M | /* 3010 */ 'v', 'q', 's', 'h', 'r', 'n', 0, |
386 | 1.35M | /* 3017 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, |
387 | 1.35M | /* 3025 */ 'v', 'r', 's', 'h', 'r', 'n', 0, |
388 | 1.35M | /* 3032 */ 'v', 's', 'h', 'r', 'n', 0, |
389 | 1.35M | /* 3038 */ 'v', 'o', 'r', 'n', 0, |
390 | 1.35M | /* 3043 */ 'v', 't', 'r', 'n', 0, |
391 | 1.35M | /* 3048 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, |
392 | 1.35M | /* 3056 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, |
393 | 1.35M | /* 3065 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, |
394 | 1.35M | /* 3073 */ 'v', 'm', 'v', 'n', 0, |
395 | 1.35M | /* 3078 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, |
396 | 1.35M | /* 3085 */ 'v', 'm', 'o', 'v', 'n', 0, |
397 | 1.35M | /* 3091 */ 't', 'r', 'a', 'p', 0, |
398 | 1.35M | /* 3096 */ 'c', 'd', 'p', 0, |
399 | 1.35M | /* 3100 */ 'v', 'z', 'i', 'p', 0, |
400 | 1.35M | /* 3105 */ 'v', 'c', 'm', 'p', 0, |
401 | 1.35M | /* 3110 */ 'p', 'o', 'p', 0, |
402 | 1.35M | /* 3114 */ 'v', 'd', 'u', 'p', 0, |
403 | 1.35M | /* 3119 */ 'v', 's', 'w', 'p', 0, |
404 | 1.35M | /* 3124 */ 'v', 'u', 'z', 'p', 0, |
405 | 1.35M | /* 3129 */ 'v', 'c', 'e', 'q', 0, |
406 | 1.35M | /* 3134 */ 't', 'e', 'q', 0, |
407 | 1.35M | /* 3138 */ 's', 'm', 'm', 'l', 'a', 'r', 0, |
408 | 1.35M | /* 3145 */ 'm', 'c', 'r', 0, |
409 | 1.35M | /* 3149 */ 'a', 'd', 'r', 0, |
410 | 1.35M | /* 3153 */ 'v', 'l', 'd', 'r', 0, |
411 | 1.35M | /* 3158 */ 'v', 'r', 's', 'h', 'r', 0, |
412 | 1.35M | /* 3164 */ 'v', 's', 'h', 'r', 0, |
413 | 1.35M | /* 3169 */ 's', 'm', 'm', 'u', 'l', 'r', 0, |
414 | 1.35M | /* 3176 */ 'v', 'e', 'o', 'r', 0, |
415 | 1.35M | /* 3181 */ 'r', 'o', 'r', 0, |
416 | 1.35M | /* 3185 */ 'm', 'c', 'r', 'r', 0, |
417 | 1.35M | /* 3190 */ 'v', 'o', 'r', 'r', 0, |
418 | 1.35M | /* 3195 */ 'a', 's', 'r', 0, |
419 | 1.35M | /* 3199 */ 's', 'm', 'm', 'l', 's', 'r', 0, |
420 | 1.35M | /* 3206 */ 'v', 'm', 's', 'r', 0, |
421 | 1.35M | /* 3211 */ 'v', 'r', 'i', 'n', 't', 'r', 0, |
422 | 1.35M | /* 3218 */ 'v', 's', 't', 'r', 0, |
423 | 1.35M | /* 3223 */ 'v', 'c', 'v', 't', 'r', 0, |
424 | 1.35M | /* 3229 */ 'v', 'q', 'a', 'b', 's', 0, |
425 | 1.35M | /* 3235 */ 'v', 'a', 'b', 's', 0, |
426 | 1.35M | /* 3240 */ 's', 'u', 'b', 's', 0, |
427 | 1.35M | /* 3245 */ 'v', 'c', 'l', 's', 0, |
428 | 1.35M | /* 3250 */ 's', 'm', 'm', 'l', 's', 0, |
429 | 1.35M | /* 3256 */ 'v', 'n', 'm', 'l', 's', 0, |
430 | 1.35M | /* 3262 */ 'v', 'm', 'l', 's', 0, |
431 | 1.35M | /* 3267 */ 'v', 'f', 'm', 's', 0, |
432 | 1.35M | /* 3272 */ 'v', 'f', 'n', 'm', 's', 0, |
433 | 1.35M | /* 3278 */ 'b', 'x', 'n', 's', 0, |
434 | 1.35M | /* 3283 */ 'b', 'l', 'x', 'n', 's', 0, |
435 | 1.35M | /* 3289 */ 'v', 'r', 'e', 'c', 'p', 's', 0, |
436 | 1.35M | /* 3296 */ 'v', 'm', 'r', 's', 0, |
437 | 1.35M | /* 3301 */ 'a', 's', 'r', 's', 0, |
438 | 1.35M | /* 3306 */ 'l', 's', 'r', 's', 0, |
439 | 1.35M | /* 3311 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, |
440 | 1.35M | /* 3319 */ 'm', 'o', 'v', 's', 0, |
441 | 1.35M | /* 3324 */ 's', 's', 'a', 't', 0, |
442 | 1.35M | /* 3329 */ 'u', 's', 'a', 't', 0, |
443 | 1.35M | /* 3334 */ 't', 't', 'a', 't', 0, |
444 | 1.35M | /* 3339 */ 's', 'm', 'l', 'a', 'b', 't', 0, |
445 | 1.35M | /* 3346 */ 'p', 'k', 'h', 'b', 't', 0, |
446 | 1.35M | /* 3352 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, |
447 | 1.35M | /* 3360 */ 's', 'm', 'u', 'l', 'b', 't', 0, |
448 | 1.35M | /* 3367 */ 'l', 'd', 'r', 'b', 't', 0, |
449 | 1.35M | /* 3373 */ 's', 't', 'r', 'b', 't', 0, |
450 | 1.35M | /* 3379 */ 'l', 'd', 'r', 's', 'b', 't', 0, |
451 | 1.35M | /* 3386 */ 'e', 'r', 'e', 't', 0, |
452 | 1.35M | /* 3391 */ 'v', 'a', 'c', 'g', 't', 0, |
453 | 1.35M | /* 3397 */ 'v', 'c', 'g', 't', 0, |
454 | 1.35M | /* 3402 */ 'l', 'd', 'r', 'h', 't', 0, |
455 | 1.35M | /* 3408 */ 's', 't', 'r', 'h', 't', 0, |
456 | 1.35M | /* 3414 */ 'l', 'd', 'r', 's', 'h', 't', 0, |
457 | 1.35M | /* 3421 */ 'r', 'b', 'i', 't', 0, |
458 | 1.35M | /* 3426 */ 'v', 'b', 'i', 't', 0, |
459 | 1.35M | /* 3431 */ 'v', 'c', 'l', 't', 0, |
460 | 1.35M | /* 3436 */ 'v', 'c', 'n', 't', 0, |
461 | 1.35M | /* 3441 */ 'h', 'i', 'n', 't', 0, |
462 | 1.35M | /* 3446 */ 'l', 'd', 'r', 't', 0, |
463 | 1.35M | /* 3451 */ 'v', 's', 'q', 'r', 't', 0, |
464 | 1.35M | /* 3457 */ 's', 't', 'r', 't', 0, |
465 | 1.35M | /* 3462 */ 'v', 't', 's', 't', 0, |
466 | 1.35M | /* 3467 */ 's', 'm', 'l', 'a', 't', 't', 0, |
467 | 1.35M | /* 3474 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, |
468 | 1.35M | /* 3482 */ 's', 'm', 'u', 'l', 't', 't', 0, |
469 | 1.35M | /* 3489 */ 't', 't', 't', 0, |
470 | 1.35M | /* 3493 */ 'v', 'c', 'v', 't', 't', 0, |
471 | 1.35M | /* 3499 */ 'v', 'j', 'c', 'v', 't', 0, |
472 | 1.35M | /* 3505 */ 'v', 'c', 'v', 't', 0, |
473 | 1.35M | /* 3510 */ 'm', 'o', 'v', 't', 0, |
474 | 1.35M | /* 3515 */ 's', 'm', 'l', 'a', 'w', 't', 0, |
475 | 1.35M | /* 3522 */ 's', 'm', 'u', 'l', 'w', 't', 0, |
476 | 1.35M | /* 3529 */ 'v', 'e', 'x', 't', 0, |
477 | 1.35M | /* 3534 */ 'v', 'q', 's', 'h', 'l', 'u', 0, |
478 | 1.35M | /* 3541 */ 'r', 'e', 'v', 0, |
479 | 1.35M | /* 3545 */ 's', 'd', 'i', 'v', 0, |
480 | 1.35M | /* 3550 */ 'u', 'd', 'i', 'v', 0, |
481 | 1.35M | /* 3555 */ 'v', 'd', 'i', 'v', 0, |
482 | 1.35M | /* 3560 */ 'v', 'm', 'o', 'v', 0, |
483 | 1.35M | /* 3565 */ 'v', 's', 'u', 'b', 'w', 0, |
484 | 1.35M | /* 3571 */ 'v', 'a', 'd', 'd', 'w', 0, |
485 | 1.35M | /* 3577 */ 'p', 'l', 'd', 'w', 0, |
486 | 1.35M | /* 3582 */ 'm', 'o', 'v', 'w', 0, |
487 | 1.35M | /* 3587 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, |
488 | 1.35M | /* 3595 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, |
489 | 1.35M | /* 3603 */ 'v', 'p', 'm', 'a', 'x', 0, |
490 | 1.35M | /* 3609 */ 'v', 'm', 'a', 'x', 0, |
491 | 1.35M | /* 3614 */ 's', 'h', 's', 'a', 'x', 0, |
492 | 1.35M | /* 3620 */ 'u', 'h', 's', 'a', 'x', 0, |
493 | 1.35M | /* 3626 */ 'u', 'q', 's', 'a', 'x', 0, |
494 | 1.35M | /* 3632 */ 's', 's', 'a', 'x', 0, |
495 | 1.35M | /* 3637 */ 'u', 's', 'a', 'x', 0, |
496 | 1.35M | /* 3642 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, |
497 | 1.35M | /* 3650 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, |
498 | 1.35M | /* 3658 */ 'v', 't', 'b', 'x', 0, |
499 | 1.35M | /* 3663 */ 's', 'm', 'l', 'a', 'd', 'x', 0, |
500 | 1.35M | /* 3670 */ 's', 'm', 'u', 'a', 'd', 'x', 0, |
501 | 1.35M | /* 3677 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, |
502 | 1.35M | /* 3685 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, |
503 | 1.35M | /* 3693 */ 's', 'm', 'l', 's', 'd', 'x', 0, |
504 | 1.35M | /* 3700 */ 's', 'm', 'u', 's', 'd', 'x', 0, |
505 | 1.35M | /* 3707 */ 'l', 'd', 'a', 'e', 'x', 0, |
506 | 1.35M | /* 3713 */ 's', 't', 'l', 'e', 'x', 0, |
507 | 1.35M | /* 3719 */ 'l', 'd', 'r', 'e', 'x', 0, |
508 | 1.35M | /* 3725 */ 'c', 'l', 'r', 'e', 'x', 0, |
509 | 1.35M | /* 3731 */ 's', 't', 'r', 'e', 'x', 0, |
510 | 1.35M | /* 3737 */ 's', 'b', 'f', 'x', 0, |
511 | 1.35M | /* 3742 */ 'u', 'b', 'f', 'x', 0, |
512 | 1.35M | /* 3747 */ 'b', 'l', 'x', 0, |
513 | 1.35M | /* 3751 */ 'r', 'r', 'x', 0, |
514 | 1.35M | /* 3755 */ 's', 'h', 'a', 's', 'x', 0, |
515 | 1.35M | /* 3761 */ 'u', 'h', 'a', 's', 'x', 0, |
516 | 1.35M | /* 3767 */ 'u', 'q', 'a', 's', 'x', 0, |
517 | 1.35M | /* 3773 */ 's', 'a', 's', 'x', 0, |
518 | 1.35M | /* 3778 */ 'u', 'a', 's', 'x', 0, |
519 | 1.35M | /* 3783 */ 'v', 'r', 'i', 'n', 't', 'x', 0, |
520 | 1.35M | /* 3790 */ 'v', 'c', 'l', 'z', 0, |
521 | 1.35M | /* 3795 */ 'v', 'r', 'i', 'n', 't', 'z', 0, |
522 | 1.35M | }; |
523 | 1.35M | #endif |
524 | | |
525 | 1.35M | static const uint32_t OpInfo0[] = { |
526 | 1.35M | 0U, // PHI |
527 | 1.35M | 0U, // INLINEASM |
528 | 1.35M | 0U, // CFI_INSTRUCTION |
529 | 1.35M | 0U, // EH_LABEL |
530 | 1.35M | 0U, // GC_LABEL |
531 | 1.35M | 0U, // ANNOTATION_LABEL |
532 | 1.35M | 0U, // KILL |
533 | 1.35M | 0U, // EXTRACT_SUBREG |
534 | 1.35M | 0U, // INSERT_SUBREG |
535 | 1.35M | 0U, // IMPLICIT_DEF |
536 | 1.35M | 0U, // SUBREG_TO_REG |
537 | 1.35M | 0U, // COPY_TO_REGCLASS |
538 | 1.35M | 1981U, // DBG_VALUE |
539 | 1.35M | 1991U, // DBG_LABEL |
540 | 1.35M | 0U, // REG_SEQUENCE |
541 | 1.35M | 0U, // COPY |
542 | 1.35M | 1974U, // BUNDLE |
543 | 1.35M | 2020U, // LIFETIME_START |
544 | 1.35M | 1961U, // LIFETIME_END |
545 | 1.35M | 0U, // STACKMAP |
546 | 1.35M | 2862U, // FENTRY_CALL |
547 | 1.35M | 0U, // PATCHPOINT |
548 | 1.35M | 0U, // LOAD_STACK_GUARD |
549 | 1.35M | 0U, // STATEPOINT |
550 | 1.35M | 0U, // LOCAL_ESCAPE |
551 | 1.35M | 0U, // FAULTING_OP |
552 | 1.35M | 0U, // PATCHABLE_OP |
553 | 1.35M | 1568U, // PATCHABLE_FUNCTION_ENTER |
554 | 1.35M | 1488U, // PATCHABLE_RET |
555 | 1.35M | 1614U, // PATCHABLE_FUNCTION_EXIT |
556 | 1.35M | 1591U, // PATCHABLE_TAIL_CALL |
557 | 1.35M | 1543U, // PATCHABLE_EVENT_CALL |
558 | 1.35M | 1519U, // PATCHABLE_TYPED_EVENT_CALL |
559 | 1.35M | 0U, // ICALL_BRANCH_FUNNEL |
560 | 1.35M | 0U, // G_ADD |
561 | 1.35M | 0U, // G_SUB |
562 | 1.35M | 0U, // G_MUL |
563 | 1.35M | 0U, // G_SDIV |
564 | 1.35M | 0U, // G_UDIV |
565 | 1.35M | 0U, // G_SREM |
566 | 1.35M | 0U, // G_UREM |
567 | 1.35M | 0U, // G_AND |
568 | 1.35M | 0U, // G_OR |
569 | 1.35M | 0U, // G_XOR |
570 | 1.35M | 0U, // G_IMPLICIT_DEF |
571 | 1.35M | 0U, // G_PHI |
572 | 1.35M | 0U, // G_FRAME_INDEX |
573 | 1.35M | 0U, // G_GLOBAL_VALUE |
574 | 1.35M | 0U, // G_EXTRACT |
575 | 1.35M | 0U, // G_UNMERGE_VALUES |
576 | 1.35M | 0U, // G_INSERT |
577 | 1.35M | 0U, // G_MERGE_VALUES |
578 | 1.35M | 0U, // G_PTRTOINT |
579 | 1.35M | 0U, // G_INTTOPTR |
580 | 1.35M | 0U, // G_BITCAST |
581 | 1.35M | 0U, // G_LOAD |
582 | 1.35M | 0U, // G_SEXTLOAD |
583 | 1.35M | 0U, // G_ZEXTLOAD |
584 | 1.35M | 0U, // G_STORE |
585 | 1.35M | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
586 | 1.35M | 0U, // G_ATOMIC_CMPXCHG |
587 | 1.35M | 0U, // G_ATOMICRMW_XCHG |
588 | 1.35M | 0U, // G_ATOMICRMW_ADD |
589 | 1.35M | 0U, // G_ATOMICRMW_SUB |
590 | 1.35M | 0U, // G_ATOMICRMW_AND |
591 | 1.35M | 0U, // G_ATOMICRMW_NAND |
592 | 1.35M | 0U, // G_ATOMICRMW_OR |
593 | 1.35M | 0U, // G_ATOMICRMW_XOR |
594 | 1.35M | 0U, // G_ATOMICRMW_MAX |
595 | 1.35M | 0U, // G_ATOMICRMW_MIN |
596 | 1.35M | 0U, // G_ATOMICRMW_UMAX |
597 | 1.35M | 0U, // G_ATOMICRMW_UMIN |
598 | 1.35M | 0U, // G_BRCOND |
599 | 1.35M | 0U, // G_BRINDIRECT |
600 | 1.35M | 0U, // G_INTRINSIC |
601 | 1.35M | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
602 | 1.35M | 0U, // G_ANYEXT |
603 | 1.35M | 0U, // G_TRUNC |
604 | 1.35M | 0U, // G_CONSTANT |
605 | 1.35M | 0U, // G_FCONSTANT |
606 | 1.35M | 0U, // G_VASTART |
607 | 1.35M | 0U, // G_VAARG |
608 | 1.35M | 0U, // G_SEXT |
609 | 1.35M | 0U, // G_ZEXT |
610 | 1.35M | 0U, // G_SHL |
611 | 1.35M | 0U, // G_LSHR |
612 | 1.35M | 0U, // G_ASHR |
613 | 1.35M | 0U, // G_ICMP |
614 | 1.35M | 0U, // G_FCMP |
615 | 1.35M | 0U, // G_SELECT |
616 | 1.35M | 0U, // G_UADDE |
617 | 1.35M | 0U, // G_USUBE |
618 | 1.35M | 0U, // G_SADDO |
619 | 1.35M | 0U, // G_SSUBO |
620 | 1.35M | 0U, // G_UMULO |
621 | 1.35M | 0U, // G_SMULO |
622 | 1.35M | 0U, // G_UMULH |
623 | 1.35M | 0U, // G_SMULH |
624 | 1.35M | 0U, // G_FADD |
625 | 1.35M | 0U, // G_FSUB |
626 | 1.35M | 0U, // G_FMUL |
627 | 1.35M | 0U, // G_FMA |
628 | 1.35M | 0U, // G_FDIV |
629 | 1.35M | 0U, // G_FREM |
630 | 1.35M | 0U, // G_FPOW |
631 | 1.35M | 0U, // G_FEXP |
632 | 1.35M | 0U, // G_FEXP2 |
633 | 1.35M | 0U, // G_FLOG |
634 | 1.35M | 0U, // G_FLOG2 |
635 | 1.35M | 0U, // G_FNEG |
636 | 1.35M | 0U, // G_FPEXT |
637 | 1.35M | 0U, // G_FPTRUNC |
638 | 1.35M | 0U, // G_FPTOSI |
639 | 1.35M | 0U, // G_FPTOUI |
640 | 1.35M | 0U, // G_SITOFP |
641 | 1.35M | 0U, // G_UITOFP |
642 | 1.35M | 0U, // G_FABS |
643 | 1.35M | 0U, // G_GEP |
644 | 1.35M | 0U, // G_PTR_MASK |
645 | 1.35M | 0U, // G_BR |
646 | 1.35M | 0U, // G_INSERT_VECTOR_ELT |
647 | 1.35M | 0U, // G_EXTRACT_VECTOR_ELT |
648 | 1.35M | 0U, // G_SHUFFLE_VECTOR |
649 | 1.35M | 0U, // G_BSWAP |
650 | 1.35M | 0U, // G_ADDRSPACE_CAST |
651 | 1.35M | 0U, // G_BLOCK_ADDR |
652 | 1.35M | 0U, // ABS |
653 | 1.35M | 0U, // ADDSri |
654 | 1.35M | 0U, // ADDSrr |
655 | 1.35M | 0U, // ADDSrsi |
656 | 1.35M | 0U, // ADDSrsr |
657 | 1.35M | 0U, // ADJCALLSTACKDOWN |
658 | 1.35M | 0U, // ADJCALLSTACKUP |
659 | 1.35M | 7292U, // ASRi |
660 | 1.35M | 7292U, // ASRr |
661 | 1.35M | 0U, // B |
662 | 1.35M | 0U, // BCCZi64 |
663 | 1.35M | 0U, // BCCi64 |
664 | 1.35M | 0U, // BMOVPCB_CALL |
665 | 1.35M | 0U, // BMOVPCRX_CALL |
666 | 1.35M | 0U, // BR_JTadd |
667 | 1.35M | 0U, // BR_JTm_i12 |
668 | 1.35M | 0U, // BR_JTm_rs |
669 | 1.35M | 0U, // BR_JTr |
670 | 1.35M | 0U, // BX_CALL |
671 | 1.35M | 0U, // CMP_SWAP_16 |
672 | 1.35M | 0U, // CMP_SWAP_32 |
673 | 1.35M | 0U, // CMP_SWAP_64 |
674 | 1.35M | 0U, // CMP_SWAP_8 |
675 | 1.35M | 0U, // CONSTPOOL_ENTRY |
676 | 1.35M | 0U, // COPY_STRUCT_BYVAL_I32 |
677 | 1.35M | 2001U, // CompilerBarrier |
678 | 1.35M | 16788832U, // ITasm |
679 | 1.35M | 0U, // Int_eh_sjlj_dispatchsetup |
680 | 1.35M | 0U, // Int_eh_sjlj_longjmp |
681 | 1.35M | 0U, // Int_eh_sjlj_setjmp |
682 | 1.35M | 0U, // Int_eh_sjlj_setjmp_nofp |
683 | 1.35M | 0U, // Int_eh_sjlj_setup_dispatch |
684 | 1.35M | 0U, // JUMPTABLE_ADDRS |
685 | 1.35M | 0U, // JUMPTABLE_INSTS |
686 | 1.35M | 0U, // JUMPTABLE_TBB |
687 | 1.35M | 0U, // JUMPTABLE_TBH |
688 | 1.35M | 0U, // LDMIA_RET |
689 | 1.35M | 15656U, // LDRBT_POST |
690 | 1.35M | 15443U, // LDRConstPool |
691 | 1.35M | 0U, // LDRLIT_ga_abs |
692 | 1.35M | 0U, // LDRLIT_ga_pcrel |
693 | 1.35M | 0U, // LDRLIT_ga_pcrel_ldr |
694 | 1.35M | 15735U, // LDRT_POST |
695 | 1.35M | 0U, // LEApcrel |
696 | 1.35M | 0U, // LEApcrelJT |
697 | 1.35M | 7013U, // LSLi |
698 | 1.35M | 7013U, // LSLr |
699 | 1.35M | 7299U, // LSRi |
700 | 1.35M | 7299U, // LSRr |
701 | 1.35M | 0U, // MEMCPY |
702 | 1.35M | 0U, // MLAv5 |
703 | 1.35M | 0U, // MOVCCi |
704 | 1.35M | 0U, // MOVCCi16 |
705 | 1.35M | 0U, // MOVCCi32imm |
706 | 1.35M | 0U, // MOVCCr |
707 | 1.35M | 0U, // MOVCCsi |
708 | 1.35M | 0U, // MOVCCsr |
709 | 1.35M | 0U, // MOVPCRX |
710 | 1.35M | 0U, // MOVTi16_ga_pcrel |
711 | 1.35M | 0U, // MOV_ga_pcrel |
712 | 1.35M | 0U, // MOV_ga_pcrel_ldr |
713 | 1.35M | 0U, // MOVi16_ga_pcrel |
714 | 1.35M | 0U, // MOVi32imm |
715 | 1.35M | 0U, // MOVsra_flag |
716 | 1.35M | 0U, // MOVsrl_flag |
717 | 1.35M | 0U, // MULv5 |
718 | 1.35M | 0U, // MVNCCi |
719 | 1.35M | 0U, // PICADD |
720 | 1.35M | 0U, // PICLDR |
721 | 1.35M | 0U, // PICLDRB |
722 | 1.35M | 0U, // PICLDRH |
723 | 1.35M | 0U, // PICLDRSB |
724 | 1.35M | 0U, // PICLDRSH |
725 | 1.35M | 0U, // PICSTR |
726 | 1.35M | 0U, // PICSTRB |
727 | 1.35M | 0U, // PICSTRH |
728 | 1.35M | 7278U, // RORi |
729 | 1.35M | 7278U, // RORr |
730 | 1.35M | 0U, // RRX |
731 | 1.35M | 20136U, // RRXi |
732 | 1.35M | 0U, // RSBSri |
733 | 1.35M | 0U, // RSBSrsi |
734 | 1.35M | 0U, // RSBSrsr |
735 | 1.35M | 0U, // SMLALv5 |
736 | 1.35M | 0U, // SMULLv5 |
737 | 1.35M | 0U, // SPACE |
738 | 1.35M | 15662U, // STRBT_POST |
739 | 1.35M | 0U, // STRBi_preidx |
740 | 1.35M | 0U, // STRBr_preidx |
741 | 1.35M | 0U, // STRH_preidx |
742 | 1.35M | 15746U, // STRT_POST |
743 | 1.35M | 0U, // STRi_preidx |
744 | 1.35M | 0U, // STRr_preidx |
745 | 1.35M | 0U, // SUBS_PC_LR |
746 | 1.35M | 0U, // SUBSri |
747 | 1.35M | 0U, // SUBSrr |
748 | 1.35M | 0U, // SUBSrsi |
749 | 1.35M | 0U, // SUBSrsr |
750 | 1.35M | 0U, // TAILJMPd |
751 | 1.35M | 0U, // TAILJMPr |
752 | 1.35M | 0U, // TAILJMPr4 |
753 | 1.35M | 0U, // TCRETURNdi |
754 | 1.35M | 0U, // TCRETURNri |
755 | 1.35M | 0U, // TPsoft |
756 | 1.35M | 0U, // UMLALv5 |
757 | 1.35M | 0U, // UMULLv5 |
758 | 1.35M | 153198U, // VLD1LNdAsm_16 |
759 | 1.35M | 284270U, // VLD1LNdAsm_32 |
760 | 1.35M | 415342U, // VLD1LNdAsm_8 |
761 | 1.35M | 153198U, // VLD1LNdWB_fixed_Asm_16 |
762 | 1.35M | 284270U, // VLD1LNdWB_fixed_Asm_32 |
763 | 1.35M | 415342U, // VLD1LNdWB_fixed_Asm_8 |
764 | 1.35M | 157294U, // VLD1LNdWB_register_Asm_16 |
765 | 1.35M | 288366U, // VLD1LNdWB_register_Asm_32 |
766 | 1.35M | 419438U, // VLD1LNdWB_register_Asm_8 |
767 | 1.35M | 153242U, // VLD2LNdAsm_16 |
768 | 1.35M | 284314U, // VLD2LNdAsm_32 |
769 | 1.35M | 415386U, // VLD2LNdAsm_8 |
770 | 1.35M | 153242U, // VLD2LNdWB_fixed_Asm_16 |
771 | 1.35M | 284314U, // VLD2LNdWB_fixed_Asm_32 |
772 | 1.35M | 415386U, // VLD2LNdWB_fixed_Asm_8 |
773 | 1.35M | 157338U, // VLD2LNdWB_register_Asm_16 |
774 | 1.35M | 288410U, // VLD2LNdWB_register_Asm_32 |
775 | 1.35M | 419482U, // VLD2LNdWB_register_Asm_8 |
776 | 1.35M | 153242U, // VLD2LNqAsm_16 |
777 | 1.35M | 284314U, // VLD2LNqAsm_32 |
778 | 1.35M | 153242U, // VLD2LNqWB_fixed_Asm_16 |
779 | 1.35M | 284314U, // VLD2LNqWB_fixed_Asm_32 |
780 | 1.35M | 157338U, // VLD2LNqWB_register_Asm_16 |
781 | 1.35M | 288410U, // VLD2LNqWB_register_Asm_32 |
782 | 1.35M | 1107457722U, // VLD3DUPdAsm_16 |
783 | 1.35M | 1107588794U, // VLD3DUPdAsm_32 |
784 | 1.35M | 1107719866U, // VLD3DUPdAsm_8 |
785 | 1.35M | 2181199546U, // VLD3DUPdWB_fixed_Asm_16 |
786 | 1.35M | 2181330618U, // VLD3DUPdWB_fixed_Asm_32 |
787 | 1.35M | 2181461690U, // VLD3DUPdWB_fixed_Asm_8 |
788 | 1.35M | 33707706U, // VLD3DUPdWB_register_Asm_16 |
789 | 1.35M | 33838778U, // VLD3DUPdWB_register_Asm_32 |
790 | 1.35M | 33969850U, // VLD3DUPdWB_register_Asm_8 |
791 | 1.35M | 1124234938U, // VLD3DUPqAsm_16 |
792 | 1.35M | 1124366010U, // VLD3DUPqAsm_32 |
793 | 1.35M | 1124497082U, // VLD3DUPqAsm_8 |
794 | 1.35M | 2197976762U, // VLD3DUPqWB_fixed_Asm_16 |
795 | 1.35M | 2198107834U, // VLD3DUPqWB_fixed_Asm_32 |
796 | 1.35M | 2198238906U, // VLD3DUPqWB_fixed_Asm_8 |
797 | 1.35M | 50484922U, // VLD3DUPqWB_register_Asm_16 |
798 | 1.35M | 50615994U, // VLD3DUPqWB_register_Asm_32 |
799 | 1.35M | 50747066U, // VLD3DUPqWB_register_Asm_8 |
800 | 1.35M | 153274U, // VLD3LNdAsm_16 |
801 | 1.35M | 284346U, // VLD3LNdAsm_32 |
802 | 1.35M | 415418U, // VLD3LNdAsm_8 |
803 | 1.35M | 153274U, // VLD3LNdWB_fixed_Asm_16 |
804 | 1.35M | 284346U, // VLD3LNdWB_fixed_Asm_32 |
805 | 1.35M | 415418U, // VLD3LNdWB_fixed_Asm_8 |
806 | 1.35M | 157370U, // VLD3LNdWB_register_Asm_16 |
807 | 1.35M | 288442U, // VLD3LNdWB_register_Asm_32 |
808 | 1.35M | 419514U, // VLD3LNdWB_register_Asm_8 |
809 | 1.35M | 153274U, // VLD3LNqAsm_16 |
810 | 1.35M | 284346U, // VLD3LNqAsm_32 |
811 | 1.35M | 153274U, // VLD3LNqWB_fixed_Asm_16 |
812 | 1.35M | 284346U, // VLD3LNqWB_fixed_Asm_32 |
813 | 1.35M | 157370U, // VLD3LNqWB_register_Asm_16 |
814 | 1.35M | 288442U, // VLD3LNqWB_register_Asm_32 |
815 | 1.35M | 3288495802U, // VLD3dAsm_16 |
816 | 1.35M | 3288626874U, // VLD3dAsm_32 |
817 | 1.35M | 3288757946U, // VLD3dAsm_8 |
818 | 1.35M | 3288495802U, // VLD3dWB_fixed_Asm_16 |
819 | 1.35M | 3288626874U, // VLD3dWB_fixed_Asm_32 |
820 | 1.35M | 3288757946U, // VLD3dWB_fixed_Asm_8 |
821 | 1.35M | 3288487610U, // VLD3dWB_register_Asm_16 |
822 | 1.35M | 3288618682U, // VLD3dWB_register_Asm_32 |
823 | 1.35M | 3288749754U, // VLD3dWB_register_Asm_8 |
824 | 1.35M | 1157789370U, // VLD3qAsm_16 |
825 | 1.35M | 1157920442U, // VLD3qAsm_32 |
826 | 1.35M | 1158051514U, // VLD3qAsm_8 |
827 | 1.35M | 2231531194U, // VLD3qWB_fixed_Asm_16 |
828 | 1.35M | 2231662266U, // VLD3qWB_fixed_Asm_32 |
829 | 1.35M | 2231793338U, // VLD3qWB_fixed_Asm_8 |
830 | 1.35M | 84039354U, // VLD3qWB_register_Asm_16 |
831 | 1.35M | 84170426U, // VLD3qWB_register_Asm_32 |
832 | 1.35M | 84301498U, // VLD3qWB_register_Asm_8 |
833 | 1.35M | 1174566609U, // VLD4DUPdAsm_16 |
834 | 1.35M | 1174697681U, // VLD4DUPdAsm_32 |
835 | 1.35M | 1174828753U, // VLD4DUPdAsm_8 |
836 | 1.35M | 2248308433U, // VLD4DUPdWB_fixed_Asm_16 |
837 | 1.35M | 2248439505U, // VLD4DUPdWB_fixed_Asm_32 |
838 | 1.35M | 2248570577U, // VLD4DUPdWB_fixed_Asm_8 |
839 | 1.35M | 100816593U, // VLD4DUPdWB_register_Asm_16 |
840 | 1.35M | 100947665U, // VLD4DUPdWB_register_Asm_32 |
841 | 1.35M | 101078737U, // VLD4DUPdWB_register_Asm_8 |
842 | 1.35M | 1191343825U, // VLD4DUPqAsm_16 |
843 | 1.35M | 1191474897U, // VLD4DUPqAsm_32 |
844 | 1.35M | 1191605969U, // VLD4DUPqAsm_8 |
845 | 1.35M | 2265085649U, // VLD4DUPqWB_fixed_Asm_16 |
846 | 1.35M | 2265216721U, // VLD4DUPqWB_fixed_Asm_32 |
847 | 1.35M | 2265347793U, // VLD4DUPqWB_fixed_Asm_8 |
848 | 1.35M | 117593809U, // VLD4DUPqWB_register_Asm_16 |
849 | 1.35M | 117724881U, // VLD4DUPqWB_register_Asm_32 |
850 | 1.35M | 117855953U, // VLD4DUPqWB_register_Asm_8 |
851 | 1.35M | 153297U, // VLD4LNdAsm_16 |
852 | 1.35M | 284369U, // VLD4LNdAsm_32 |
853 | 1.35M | 415441U, // VLD4LNdAsm_8 |
854 | 1.35M | 153297U, // VLD4LNdWB_fixed_Asm_16 |
855 | 1.35M | 284369U, // VLD4LNdWB_fixed_Asm_32 |
856 | 1.35M | 415441U, // VLD4LNdWB_fixed_Asm_8 |
857 | 1.35M | 157393U, // VLD4LNdWB_register_Asm_16 |
858 | 1.35M | 288465U, // VLD4LNdWB_register_Asm_32 |
859 | 1.35M | 419537U, // VLD4LNdWB_register_Asm_8 |
860 | 1.35M | 153297U, // VLD4LNqAsm_16 |
861 | 1.35M | 284369U, // VLD4LNqAsm_32 |
862 | 1.35M | 153297U, // VLD4LNqWB_fixed_Asm_16 |
863 | 1.35M | 284369U, // VLD4LNqWB_fixed_Asm_32 |
864 | 1.35M | 157393U, // VLD4LNqWB_register_Asm_16 |
865 | 1.35M | 288465U, // VLD4LNqWB_register_Asm_32 |
866 | 1.35M | 3355604689U, // VLD4dAsm_16 |
867 | 1.35M | 3355735761U, // VLD4dAsm_32 |
868 | 1.35M | 3355866833U, // VLD4dAsm_8 |
869 | 1.35M | 3355604689U, // VLD4dWB_fixed_Asm_16 |
870 | 1.35M | 3355735761U, // VLD4dWB_fixed_Asm_32 |
871 | 1.35M | 3355866833U, // VLD4dWB_fixed_Asm_8 |
872 | 1.35M | 3355596497U, // VLD4dWB_register_Asm_16 |
873 | 1.35M | 3355727569U, // VLD4dWB_register_Asm_32 |
874 | 1.35M | 3355858641U, // VLD4dWB_register_Asm_8 |
875 | 1.35M | 1224898257U, // VLD4qAsm_16 |
876 | 1.35M | 1225029329U, // VLD4qAsm_32 |
877 | 1.35M | 1225160401U, // VLD4qAsm_8 |
878 | 1.35M | 2298640081U, // VLD4qWB_fixed_Asm_16 |
879 | 1.35M | 2298771153U, // VLD4qWB_fixed_Asm_32 |
880 | 1.35M | 2298902225U, // VLD4qWB_fixed_Asm_8 |
881 | 1.35M | 151148241U, // VLD4qWB_register_Asm_16 |
882 | 1.35M | 151279313U, // VLD4qWB_register_Asm_32 |
883 | 1.35M | 151410385U, // VLD4qWB_register_Asm_8 |
884 | 1.35M | 0U, // VMOVD0 |
885 | 1.35M | 0U, // VMOVDcc |
886 | 1.35M | 0U, // VMOVQ0 |
887 | 1.35M | 0U, // VMOVScc |
888 | 1.35M | 153209U, // VST1LNdAsm_16 |
889 | 1.35M | 284281U, // VST1LNdAsm_32 |
890 | 1.35M | 415353U, // VST1LNdAsm_8 |
891 | 1.35M | 153209U, // VST1LNdWB_fixed_Asm_16 |
892 | 1.35M | 284281U, // VST1LNdWB_fixed_Asm_32 |
893 | 1.35M | 415353U, // VST1LNdWB_fixed_Asm_8 |
894 | 1.35M | 157305U, // VST1LNdWB_register_Asm_16 |
895 | 1.35M | 288377U, // VST1LNdWB_register_Asm_32 |
896 | 1.35M | 419449U, // VST1LNdWB_register_Asm_8 |
897 | 1.35M | 153269U, // VST2LNdAsm_16 |
898 | 1.35M | 284341U, // VST2LNdAsm_32 |
899 | 1.35M | 415413U, // VST2LNdAsm_8 |
900 | 1.35M | 153269U, // VST2LNdWB_fixed_Asm_16 |
901 | 1.35M | 284341U, // VST2LNdWB_fixed_Asm_32 |
902 | 1.35M | 415413U, // VST2LNdWB_fixed_Asm_8 |
903 | 1.35M | 157365U, // VST2LNdWB_register_Asm_16 |
904 | 1.35M | 288437U, // VST2LNdWB_register_Asm_32 |
905 | 1.35M | 419509U, // VST2LNdWB_register_Asm_8 |
906 | 1.35M | 153269U, // VST2LNqAsm_16 |
907 | 1.35M | 284341U, // VST2LNqAsm_32 |
908 | 1.35M | 153269U, // VST2LNqWB_fixed_Asm_16 |
909 | 1.35M | 284341U, // VST2LNqWB_fixed_Asm_32 |
910 | 1.35M | 157365U, // VST2LNqWB_register_Asm_16 |
911 | 1.35M | 288437U, // VST2LNqWB_register_Asm_32 |
912 | 1.35M | 153285U, // VST3LNdAsm_16 |
913 | 1.35M | 284357U, // VST3LNdAsm_32 |
914 | 1.35M | 415429U, // VST3LNdAsm_8 |
915 | 1.35M | 153285U, // VST3LNdWB_fixed_Asm_16 |
916 | 1.35M | 284357U, // VST3LNdWB_fixed_Asm_32 |
917 | 1.35M | 415429U, // VST3LNdWB_fixed_Asm_8 |
918 | 1.35M | 157381U, // VST3LNdWB_register_Asm_16 |
919 | 1.35M | 288453U, // VST3LNdWB_register_Asm_32 |
920 | 1.35M | 419525U, // VST3LNdWB_register_Asm_8 |
921 | 1.35M | 153285U, // VST3LNqAsm_16 |
922 | 1.35M | 284357U, // VST3LNqAsm_32 |
923 | 1.35M | 153285U, // VST3LNqWB_fixed_Asm_16 |
924 | 1.35M | 284357U, // VST3LNqWB_fixed_Asm_32 |
925 | 1.35M | 157381U, // VST3LNqWB_register_Asm_16 |
926 | 1.35M | 288453U, // VST3LNqWB_register_Asm_32 |
927 | 1.35M | 3288495813U, // VST3dAsm_16 |
928 | 1.35M | 3288626885U, // VST3dAsm_32 |
929 | 1.35M | 3288757957U, // VST3dAsm_8 |
930 | 1.35M | 3288495813U, // VST3dWB_fixed_Asm_16 |
931 | 1.35M | 3288626885U, // VST3dWB_fixed_Asm_32 |
932 | 1.35M | 3288757957U, // VST3dWB_fixed_Asm_8 |
933 | 1.35M | 3288487621U, // VST3dWB_register_Asm_16 |
934 | 1.35M | 3288618693U, // VST3dWB_register_Asm_32 |
935 | 1.35M | 3288749765U, // VST3dWB_register_Asm_8 |
936 | 1.35M | 1157789381U, // VST3qAsm_16 |
937 | 1.35M | 1157920453U, // VST3qAsm_32 |
938 | 1.35M | 1158051525U, // VST3qAsm_8 |
939 | 1.35M | 2231531205U, // VST3qWB_fixed_Asm_16 |
940 | 1.35M | 2231662277U, // VST3qWB_fixed_Asm_32 |
941 | 1.35M | 2231793349U, // VST3qWB_fixed_Asm_8 |
942 | 1.35M | 84039365U, // VST3qWB_register_Asm_16 |
943 | 1.35M | 84170437U, // VST3qWB_register_Asm_32 |
944 | 1.35M | 84301509U, // VST3qWB_register_Asm_8 |
945 | 1.35M | 153302U, // VST4LNdAsm_16 |
946 | 1.35M | 284374U, // VST4LNdAsm_32 |
947 | 1.35M | 415446U, // VST4LNdAsm_8 |
948 | 1.35M | 153302U, // VST4LNdWB_fixed_Asm_16 |
949 | 1.35M | 284374U, // VST4LNdWB_fixed_Asm_32 |
950 | 1.35M | 415446U, // VST4LNdWB_fixed_Asm_8 |
951 | 1.35M | 157398U, // VST4LNdWB_register_Asm_16 |
952 | 1.35M | 288470U, // VST4LNdWB_register_Asm_32 |
953 | 1.35M | 419542U, // VST4LNdWB_register_Asm_8 |
954 | 1.35M | 153302U, // VST4LNqAsm_16 |
955 | 1.35M | 284374U, // VST4LNqAsm_32 |
956 | 1.35M | 153302U, // VST4LNqWB_fixed_Asm_16 |
957 | 1.35M | 284374U, // VST4LNqWB_fixed_Asm_32 |
958 | 1.35M | 157398U, // VST4LNqWB_register_Asm_16 |
959 | 1.35M | 288470U, // VST4LNqWB_register_Asm_32 |
960 | 1.35M | 3355604694U, // VST4dAsm_16 |
961 | 1.35M | 3355735766U, // VST4dAsm_32 |
962 | 1.35M | 3355866838U, // VST4dAsm_8 |
963 | 1.35M | 3355604694U, // VST4dWB_fixed_Asm_16 |
964 | 1.35M | 3355735766U, // VST4dWB_fixed_Asm_32 |
965 | 1.35M | 3355866838U, // VST4dWB_fixed_Asm_8 |
966 | 1.35M | 3355596502U, // VST4dWB_register_Asm_16 |
967 | 1.35M | 3355727574U, // VST4dWB_register_Asm_32 |
968 | 1.35M | 3355858646U, // VST4dWB_register_Asm_8 |
969 | 1.35M | 1224898262U, // VST4qAsm_16 |
970 | 1.35M | 1225029334U, // VST4qAsm_32 |
971 | 1.35M | 1225160406U, // VST4qAsm_8 |
972 | 1.35M | 2298640086U, // VST4qWB_fixed_Asm_16 |
973 | 1.35M | 2298771158U, // VST4qWB_fixed_Asm_32 |
974 | 1.35M | 2298902230U, // VST4qWB_fixed_Asm_8 |
975 | 1.35M | 151148246U, // VST4qWB_register_Asm_16 |
976 | 1.35M | 151279318U, // VST4qWB_register_Asm_32 |
977 | 1.35M | 151410390U, // VST4qWB_register_Asm_8 |
978 | 1.35M | 0U, // WIN__CHKSTK |
979 | 1.35M | 0U, // WIN__DBZCHK |
980 | 1.35M | 0U, // t2ABS |
981 | 1.35M | 0U, // t2ADDSri |
982 | 1.35M | 0U, // t2ADDSrr |
983 | 1.35M | 0U, // t2ADDSrs |
984 | 1.35M | 0U, // t2BR_JT |
985 | 1.35M | 0U, // t2LDMIA_RET |
986 | 1.35M | 14508U, // t2LDRBpcrel |
987 | 1.35M | 15443U, // t2LDRConstPool |
988 | 1.35M | 14929U, // t2LDRHpcrel |
989 | 1.35M | 14526U, // t2LDRSBpcrel |
990 | 1.35M | 14948U, // t2LDRSHpcrel |
991 | 1.35M | 0U, // t2LDRpci_pic |
992 | 1.35M | 15443U, // t2LDRpcrel |
993 | 1.35M | 0U, // t2LEApcrel |
994 | 1.35M | 0U, // t2LEApcrelJT |
995 | 1.35M | 0U, // t2MOVCCasr |
996 | 1.35M | 0U, // t2MOVCCi |
997 | 1.35M | 0U, // t2MOVCCi16 |
998 | 1.35M | 0U, // t2MOVCCi32imm |
999 | 1.35M | 0U, // t2MOVCClsl |
1000 | 1.35M | 0U, // t2MOVCClsr |
1001 | 1.35M | 0U, // t2MOVCCr |
1002 | 1.35M | 0U, // t2MOVCCror |
1003 | 1.35M | 31992U, // t2MOVSsi |
1004 | 1.35M | 23800U, // t2MOVSsr |
1005 | 1.35M | 0U, // t2MOVTi16_ga_pcrel |
1006 | 1.35M | 0U, // t2MOV_ga_pcrel |
1007 | 1.35M | 0U, // t2MOVi16_ga_pcrel |
1008 | 1.35M | 0U, // t2MOVi32imm |
1009 | 1.35M | 32234U, // t2MOVsi |
1010 | 1.35M | 24042U, // t2MOVsr |
1011 | 1.35M | 0U, // t2MVNCCi |
1012 | 1.35M | 0U, // t2RSBSri |
1013 | 1.35M | 0U, // t2RSBSrs |
1014 | 1.35M | 0U, // t2STRB_preidx |
1015 | 1.35M | 0U, // t2STRH_preidx |
1016 | 1.35M | 0U, // t2STR_preidx |
1017 | 1.35M | 0U, // t2SUBSri |
1018 | 1.35M | 0U, // t2SUBSrr |
1019 | 1.35M | 0U, // t2SUBSrs |
1020 | 1.35M | 0U, // t2TBB_JT |
1021 | 1.35M | 0U, // t2TBH_JT |
1022 | 1.35M | 0U, // tADCS |
1023 | 1.35M | 0U, // tADDSi3 |
1024 | 1.35M | 0U, // tADDSi8 |
1025 | 1.35M | 0U, // tADDSrr |
1026 | 1.35M | 0U, // tADDframe |
1027 | 1.35M | 0U, // tADJCALLSTACKDOWN |
1028 | 1.35M | 0U, // tADJCALLSTACKUP |
1029 | 1.35M | 0U, // tBRIND |
1030 | 1.35M | 0U, // tBR_JTr |
1031 | 1.35M | 0U, // tBX_CALL |
1032 | 1.35M | 0U, // tBX_RET |
1033 | 1.35M | 0U, // tBX_RET_vararg |
1034 | 1.35M | 0U, // tBfar |
1035 | 1.35M | 0U, // tLDMIA_UPD |
1036 | 1.35M | 15443U, // tLDRConstPool |
1037 | 1.35M | 0U, // tLDRLIT_ga_abs |
1038 | 1.35M | 0U, // tLDRLIT_ga_pcrel |
1039 | 1.35M | 0U, // tLDR_postidx |
1040 | 1.35M | 0U, // tLDRpci_pic |
1041 | 1.35M | 0U, // tLEApcrel |
1042 | 1.35M | 0U, // tLEApcrelJT |
1043 | 1.35M | 0U, // tMOVCCr_pseudo |
1044 | 1.35M | 0U, // tPOP_RET |
1045 | 1.35M | 0U, // tSBCS |
1046 | 1.35M | 0U, // tSUBSi3 |
1047 | 1.35M | 0U, // tSUBSi8 |
1048 | 1.35M | 0U, // tSUBSrr |
1049 | 1.35M | 0U, // tTAILJMPd |
1050 | 1.35M | 0U, // tTAILJMPdND |
1051 | 1.35M | 0U, // tTAILJMPr |
1052 | 1.35M | 0U, // tTBB_JT |
1053 | 1.35M | 0U, // tTBH_JT |
1054 | 1.35M | 0U, // tTPsoft |
1055 | 1.35M | 530745U, // ADCri |
1056 | 1.35M | 530745U, // ADCrr |
1057 | 1.35M | 559417U, // ADCrsi |
1058 | 1.35M | 39225U, // ADCrsr |
1059 | 1.35M | 530806U, // ADDri |
1060 | 1.35M | 530806U, // ADDrr |
1061 | 1.35M | 559478U, // ADDrsi |
1062 | 1.35M | 39286U, // ADDrsr |
1063 | 1.35M | 539726U, // ADR |
1064 | 1.35M | 1242211449U, // AESD |
1065 | 1.35M | 1242211457U, // AESE |
1066 | 1.35M | 1258988646U, // AESIMC |
1067 | 1.35M | 1258988656U, // AESMC |
1068 | 1.35M | 530859U, // ANDri |
1069 | 1.35M | 530859U, // ANDrr |
1070 | 1.35M | 559531U, // ANDrsi |
1071 | 1.35M | 39339U, // ANDrsr |
1072 | 1.35M | 555329U, // BFC |
1073 | 1.35M | 547483U, // BFI |
1074 | 1.35M | 530758U, // BICri |
1075 | 1.35M | 530758U, // BICrr |
1076 | 1.35M | 559430U, // BICrsi |
1077 | 1.35M | 39238U, // BICrsr |
1078 | 1.35M | 828725U, // BKPT |
1079 | 1.35M | 828697U, // BL |
1080 | 1.35M | 828772U, // BLX |
1081 | 1.35M | 1074314916U, // BLX_pred |
1082 | 1.35M | 828772U, // BLXi |
1083 | 1.35M | 1074313964U, // BL_pred |
1084 | 1.35M | 828768U, // BX |
1085 | 1.35M | 1074313901U, // BXJ |
1086 | 1.35M | 970304U, // BX_RET |
1087 | 1.35M | 1074314816U, // BX_pred |
1088 | 1.35M | 1074313296U, // Bcc |
1089 | 1.35M | 201907225U, // CDP |
1090 | 1.35M | 219210157U, // CDP2 |
1091 | 1.35M | 3726U, // CLREX |
1092 | 1.35M | 540368U, // CLZ |
1093 | 1.35M | 539583U, // CMNri |
1094 | 1.35M | 539583U, // CMNzrr |
1095 | 1.35M | 555967U, // CMNzrsi |
1096 | 1.35M | 547775U, // CMNzrsr |
1097 | 1.35M | 539683U, // CMPri |
1098 | 1.35M | 539683U, // CMPrr |
1099 | 1.35M | 556067U, // CMPrsi |
1100 | 1.35M | 547875U, // CMPrsr |
1101 | 1.35M | 828709U, // CPS1p |
1102 | 1.35M | 1309211869U, // CPS2p |
1103 | 1.35M | 235470045U, // CPS3p |
1104 | 1.35M | 185246891U, // CRC32B |
1105 | 1.35M | 185246899U, // CRC32CB |
1106 | 1.35M | 185246973U, // CRC32CH |
1107 | 1.35M | 185247057U, // CRC32CW |
1108 | 1.35M | 185246965U, // CRC32H |
1109 | 1.35M | 185247049U, // CRC32W |
1110 | 1.35M | 1074313739U, // DBG |
1111 | 1.35M | 66762U, // DMB |
1112 | 1.35M | 66767U, // DSB |
1113 | 1.35M | 531562U, // EORri |
1114 | 1.35M | 531562U, // EORrr |
1115 | 1.35M | 560234U, // EORrsi |
1116 | 1.35M | 40042U, // EORrsr |
1117 | 1.35M | 838971U, // ERET |
1118 | 1.35M | 1326595561U, // FCONSTD |
1119 | 1.35M | 1326726633U, // FCONSTH |
1120 | 1.35M | 1326857705U, // FCONSTS |
1121 | 1.35M | 2332573243U, // FLDMXDB_UPD |
1122 | 1.35M | 572932U, // FLDMXIA |
1123 | 1.35M | 2332573188U, // FLDMXIA_UPD |
1124 | 1.35M | 1625313U, // FMSTAT |
1125 | 1.35M | 2332573251U, // FSTMXDB_UPD |
1126 | 1.35M | 572940U, // FSTMXIA |
1127 | 1.35M | 2332573196U, // FSTMXIA_UPD |
1128 | 1.35M | 1074314610U, // HINT |
1129 | 1.35M | 828720U, // HLT |
1130 | 1.35M | 828638U, // HVC |
1131 | 1.35M | 70868U, // ISB |
1132 | 1.35M | 538616U, // LDA |
1133 | 1.35M | 538701U, // LDAB |
1134 | 1.35M | 540284U, // LDAEX |
1135 | 1.35M | 538905U, // LDAEXB |
1136 | 1.35M | 268974533U, // LDAEXD |
1137 | 1.35M | 539263U, // LDAEXH |
1138 | 1.35M | 539165U, // LDAH |
1139 | 1.35M | 286975243U, // LDC2L_OFFSET |
1140 | 1.35M | 3524977931U, // LDC2L_OPTION |
1141 | 1.35M | 303752459U, // LDC2L_POST |
1142 | 1.35M | 320529675U, // LDC2L_PRE |
1143 | 1.35M | 286974356U, // LDC2_OFFSET |
1144 | 1.35M | 3524977044U, // LDC2_OPTION |
1145 | 1.35M | 303751572U, // LDC2_POST |
1146 | 1.35M | 320528788U, // LDC2_PRE |
1147 | 1.35M | 1275615989U, // LDCL_OFFSET |
1148 | 1.35M | 1275615989U, // LDCL_OPTION |
1149 | 1.35M | 1275615989U, // LDCL_POST |
1150 | 1.35M | 1275615989U, // LDCL_PRE |
1151 | 1.35M | 1275615549U, // LDC_OFFSET |
1152 | 1.35M | 1275615549U, // LDC_OPTION |
1153 | 1.35M | 1275615549U, // LDC_POST |
1154 | 1.35M | 1275615549U, // LDC_PRE |
1155 | 1.35M | 571388U, // LDMDA |
1156 | 1.35M | 2332571644U, // LDMDA_UPD |
1157 | 1.35M | 571519U, // LDMDB |
1158 | 1.35M | 2332571775U, // LDMDB_UPD |
1159 | 1.35M | 572300U, // LDMIA |
1160 | 1.35M | 2332572556U, // LDMIA_UPD |
1161 | 1.35M | 571538U, // LDMIB |
1162 | 1.35M | 2332571794U, // LDMIB_UPD |
1163 | 1.35M | 552232U, // LDRBT_POST_IMM |
1164 | 1.35M | 552232U, // LDRBT_POST_REG |
1165 | 1.35M | 551084U, // LDRB_POST_IMM |
1166 | 1.35M | 551084U, // LDRB_POST_REG |
1167 | 1.35M | 546988U, // LDRB_PRE_IMM |
1168 | 1.35M | 551084U, // LDRB_PRE_REG |
1169 | 1.35M | 555180U, // LDRBi12 |
1170 | 1.35M | 546988U, // LDRBrs |
1171 | 1.35M | 551343U, // LDRD |
1172 | 1.35M | 580015U, // LDRD_POST |
1173 | 1.35M | 580015U, // LDRD_PRE |
1174 | 1.35M | 540296U, // LDREX |
1175 | 1.35M | 538919U, // LDREXB |
1176 | 1.35M | 268974547U, // LDREXD |
1177 | 1.35M | 539277U, // LDREXH |
1178 | 1.35M | 547409U, // LDRH |
1179 | 1.35M | 548171U, // LDRHTi |
1180 | 1.35M | 552267U, // LDRHTr |
1181 | 1.35M | 551505U, // LDRH_POST |
1182 | 1.35M | 551505U, // LDRH_PRE |
1183 | 1.35M | 547006U, // LDRSB |
1184 | 1.35M | 548148U, // LDRSBTi |
1185 | 1.35M | 552244U, // LDRSBTr |
1186 | 1.35M | 551102U, // LDRSB_POST |
1187 | 1.35M | 551102U, // LDRSB_PRE |
1188 | 1.35M | 547428U, // LDRSH |
1189 | 1.35M | 548183U, // LDRSHTi |
1190 | 1.35M | 552279U, // LDRSHTr |
1191 | 1.35M | 551524U, // LDRSH_POST |
1192 | 1.35M | 551524U, // LDRSH_PRE |
1193 | 1.35M | 552311U, // LDRT_POST_IMM |
1194 | 1.35M | 552311U, // LDRT_POST_REG |
1195 | 1.35M | 552019U, // LDR_POST_IMM |
1196 | 1.35M | 552019U, // LDR_POST_REG |
1197 | 1.35M | 547923U, // LDR_PRE_IMM |
1198 | 1.35M | 552019U, // LDR_PRE_REG |
1199 | 1.35M | 556115U, // LDRcp |
1200 | 1.35M | 556115U, // LDRi12 |
1201 | 1.35M | 547923U, // LDRrs |
1202 | 1.35M | 201907274U, // MCR |
1203 | 1.35M | 168878515U, // MCR2 |
1204 | 1.35M | 201878642U, // MCRR |
1205 | 1.35M | 168878521U, // MCRR2 |
1206 | 1.35M | 559140U, // MLA |
1207 | 1.35M | 548021U, // MLS |
1208 | 1.35M | 1887722U, // MOVPCLR |
1209 | 1.35M | 556471U, // MOVTi16 |
1210 | 1.35M | 544234U, // MOVi |
1211 | 1.35M | 540159U, // MOVi16 |
1212 | 1.35M | 544234U, // MOVr |
1213 | 1.35M | 544234U, // MOVr_TC |
1214 | 1.35M | 531946U, // MOVsi |
1215 | 1.35M | 560618U, // MOVsr |
1216 | 1.35M | 336124238U, // MRC |
1217 | 1.35M | 74138U, // MRC2 |
1218 | 1.35M | 352872786U, // MRRC |
1219 | 1.35M | 78240U, // MRRC2 |
1220 | 1.35M | 2148056290U, // MRS |
1221 | 1.35M | 539874U, // MRSbanked |
1222 | 1.35M | 3221798114U, // MRSsys |
1223 | 1.35M | 369638536U, // MSR |
1224 | 1.35M | 386415752U, // MSRbanked |
1225 | 1.35M | 369638536U, // MSRi |
1226 | 1.35M | 531317U, // MUL |
1227 | 1.35M | 543747U, // MVNi |
1228 | 1.35M | 543747U, // MVNr |
1229 | 1.35M | 531459U, // MVNsi |
1230 | 1.35M | 560131U, // MVNsr |
1231 | 1.35M | 531576U, // ORRri |
1232 | 1.35M | 531576U, // ORRrr |
1233 | 1.35M | 560248U, // ORRrsi |
1234 | 1.35M | 40056U, // ORRrsr |
1235 | 1.35M | 548115U, // PKHBT |
1236 | 1.35M | 547023U, // PKHTB |
1237 | 1.35M | 83290U, // PLDWi12 |
1238 | 1.35M | 87386U, // PLDWrs |
1239 | 1.35M | 83171U, // PLDi12 |
1240 | 1.35M | 87267U, // PLDrs |
1241 | 1.35M | 83206U, // PLIi12 |
1242 | 1.35M | 87302U, // PLIrs |
1243 | 1.35M | 555406U, // QADD |
1244 | 1.35M | 554800U, // QADD16 |
1245 | 1.35M | 554903U, // QADD8 |
1246 | 1.35M | 556729U, // QASX |
1247 | 1.35M | 555380U, // QDADD |
1248 | 1.35M | 555252U, // QDSUB |
1249 | 1.35M | 556588U, // QSAX |
1250 | 1.35M | 555265U, // QSUB |
1251 | 1.35M | 554762U, // QSUB16 |
1252 | 1.35M | 554864U, // QSUB8 |
1253 | 1.35M | 539998U, // RBIT |
1254 | 1.35M | 540118U, // REV |
1255 | 1.35M | 538452U, // REV16 |
1256 | 1.35M | 539247U, // REVSH |
1257 | 1.35M | 828573U, // RFEDA |
1258 | 1.35M | 2008221U, // RFEDA_UPD |
1259 | 1.35M | 828604U, // RFEDB |
1260 | 1.35M | 2008252U, // RFEDB_UPD |
1261 | 1.35M | 828580U, // RFEIA |
1262 | 1.35M | 2008228U, // RFEIA_UPD |
1263 | 1.35M | 828611U, // RFEIB |
1264 | 1.35M | 2008259U, // RFEIB_UPD |
1265 | 1.35M | 530624U, // RSBri |
1266 | 1.35M | 530624U, // RSBrr |
1267 | 1.35M | 559296U, // RSBrsi |
1268 | 1.35M | 39104U, // RSBrsr |
1269 | 1.35M | 530775U, // RSCri |
1270 | 1.35M | 530775U, // RSCrr |
1271 | 1.35M | 559447U, // RSCrsi |
1272 | 1.35M | 39255U, // RSCrsr |
1273 | 1.35M | 554807U, // SADD16 |
1274 | 1.35M | 554909U, // SADD8 |
1275 | 1.35M | 556734U, // SASX |
1276 | 1.35M | 530741U, // SBCri |
1277 | 1.35M | 530741U, // SBCrr |
1278 | 1.35M | 559413U, // SBCrsi |
1279 | 1.35M | 39221U, // SBCrsr |
1280 | 1.35M | 548506U, // SBFX |
1281 | 1.35M | 556506U, // SDIV |
1282 | 1.35M | 555794U, // SEL |
1283 | 1.35M | 91368U, // SETEND |
1284 | 1.35M | 828701U, // SETPAN |
1285 | 1.35M | 168468546U, // SHA1C |
1286 | 1.35M | 1258987596U, // SHA1H |
1287 | 1.35M | 168468578U, // SHA1M |
1288 | 1.35M | 168468588U, // SHA1P |
1289 | 1.35M | 168468481U, // SHA1SU0 |
1290 | 1.35M | 1242210331U, // SHA1SU1 |
1291 | 1.35M | 168468566U, // SHA256H |
1292 | 1.35M | 168468533U, // SHA256H2 |
1293 | 1.35M | 1242210317U, // SHA256SU0 |
1294 | 1.35M | 168468519U, // SHA256SU1 |
1295 | 1.35M | 554783U, // SHADD16 |
1296 | 1.35M | 554888U, // SHADD8 |
1297 | 1.35M | 556716U, // SHASX |
1298 | 1.35M | 556575U, // SHSAX |
1299 | 1.35M | 554745U, // SHSUB16 |
1300 | 1.35M | 554849U, // SHSUB8 |
1301 | 1.35M | 1074313546U, // SMC |
1302 | 1.35M | 546910U, // SMLABB |
1303 | 1.35M | 548108U, // SMLABT |
1304 | 1.35M | 547171U, // SMLAD |
1305 | 1.35M | 548432U, // SMLADX |
1306 | 1.35M | 96984U, // SMLAL |
1307 | 1.35M | 579685U, // SMLALBB |
1308 | 1.35M | 580889U, // SMLALBT |
1309 | 1.35M | 579992U, // SMLALD |
1310 | 1.35M | 581214U, // SMLALDX |
1311 | 1.35M | 579797U, // SMLALTB |
1312 | 1.35M | 581011U, // SMLALTT |
1313 | 1.35M | 547016U, // SMLATB |
1314 | 1.35M | 548236U, // SMLATT |
1315 | 1.35M | 547083U, // SMLAWB |
1316 | 1.35M | 548284U, // SMLAWT |
1317 | 1.35M | 547257U, // SMLSD |
1318 | 1.35M | 548462U, // SMLSDX |
1319 | 1.35M | 580003U, // SMLSLD |
1320 | 1.35M | 581222U, // SMLSLDX |
1321 | 1.35M | 546850U, // SMMLA |
1322 | 1.35M | 547907U, // SMMLAR |
1323 | 1.35M | 548019U, // SMMLS |
1324 | 1.35M | 547968U, // SMMLSR |
1325 | 1.35M | 555891U, // SMMUL |
1326 | 1.35M | 556130U, // SMMULR |
1327 | 1.35M | 555369U, // SMUAD |
1328 | 1.35M | 556631U, // SMUADX |
1329 | 1.35M | 555117U, // SMULBB |
1330 | 1.35M | 556321U, // SMULBT |
1331 | 1.35M | 559946U, // SMULL |
1332 | 1.35M | 555229U, // SMULTB |
1333 | 1.35M | 556443U, // SMULTT |
1334 | 1.35M | 555282U, // SMULWB |
1335 | 1.35M | 556483U, // SMULWT |
1336 | 1.35M | 555455U, // SMUSD |
1337 | 1.35M | 556661U, // SMUSDX |
1338 | 1.35M | 828836U, // SRSDA |
1339 | 1.35M | 828788U, // SRSDA_UPD |
1340 | 1.35M | 828858U, // SRSDB |
1341 | 1.35M | 828812U, // SRSDB_UPD |
1342 | 1.35M | 828847U, // SRSIA |
1343 | 1.35M | 828800U, // SRSIA_UPD |
1344 | 1.35M | 828869U, // SRSIB |
1345 | 1.35M | 828824U, // SRSIB_UPD |
1346 | 1.35M | 548093U, // SSAT |
1347 | 1.35M | 554821U, // SSAT16 |
1348 | 1.35M | 556593U, // SSAX |
1349 | 1.35M | 554769U, // SSUB16 |
1350 | 1.35M | 554870U, // SSUB8 |
1351 | 1.35M | 286975250U, // STC2L_OFFSET |
1352 | 1.35M | 3524977938U, // STC2L_OPTION |
1353 | 1.35M | 303752466U, // STC2L_POST |
1354 | 1.35M | 320529682U, // STC2L_PRE |
1355 | 1.35M | 286974375U, // STC2_OFFSET |
1356 | 1.35M | 3524977063U, // STC2_OPTION |
1357 | 1.35M | 303751591U, // STC2_POST |
1358 | 1.35M | 320528807U, // STC2_PRE |
1359 | 1.35M | 1275615994U, // STCL_OFFSET |
1360 | 1.35M | 1275615994U, // STCL_OPTION |
1361 | 1.35M | 1275615994U, // STCL_POST |
1362 | 1.35M | 1275615994U, // STCL_PRE |
1363 | 1.35M | 1275615579U, // STC_OFFSET |
1364 | 1.35M | 1275615579U, // STC_OPTION |
1365 | 1.35M | 1275615579U, // STC_POST |
1366 | 1.35M | 1275615579U, // STC_PRE |
1367 | 1.35M | 539503U, // STL |
1368 | 1.35M | 538782U, // STLB |
1369 | 1.35M | 556674U, // STLEX |
1370 | 1.35M | 555296U, // STLEXB |
1371 | 1.35M | 555468U, // STLEXD |
1372 | 1.35M | 555654U, // STLEXH |
1373 | 1.35M | 539195U, // STLH |
1374 | 1.35M | 571394U, // STMDA |
1375 | 1.35M | 2332571650U, // STMDA_UPD |
1376 | 1.35M | 571526U, // STMDB |
1377 | 1.35M | 2332571782U, // STMDB_UPD |
1378 | 1.35M | 572306U, // STMIA |
1379 | 1.35M | 2332572562U, // STMIA_UPD |
1380 | 1.35M | 571544U, // STMIB |
1381 | 1.35M | 2332571800U, // STMIB_UPD |
1382 | 1.35M | 185101614U, // STRBT_POST_IMM |
1383 | 1.35M | 185101614U, // STRBT_POST_REG |
1384 | 1.35M | 185100465U, // STRB_POST_IMM |
1385 | 1.35M | 185100465U, // STRB_POST_REG |
1386 | 1.35M | 185096369U, // STRB_PRE_IMM |
1387 | 1.35M | 185100465U, // STRB_PRE_REG |
1388 | 1.35M | 555185U, // STRBi12 |
1389 | 1.35M | 546993U, // STRBrs |
1390 | 1.35M | 551348U, // STRD |
1391 | 1.35M | 185129396U, // STRD_POST |
1392 | 1.35M | 185129396U, // STRD_PRE |
1393 | 1.35M | 556692U, // STREX |
1394 | 1.35M | 555310U, // STREXB |
1395 | 1.35M | 555482U, // STREXD |
1396 | 1.35M | 555668U, // STREXH |
1397 | 1.35M | 547414U, // STRH |
1398 | 1.35M | 185097553U, // STRHTi |
1399 | 1.35M | 185101649U, // STRHTr |
1400 | 1.35M | 185100886U, // STRH_POST |
1401 | 1.35M | 185100886U, // STRH_PRE |
1402 | 1.35M | 185101698U, // STRT_POST_IMM |
1403 | 1.35M | 185101698U, // STRT_POST_REG |
1404 | 1.35M | 185101460U, // STR_POST_IMM |
1405 | 1.35M | 185101460U, // STR_POST_REG |
1406 | 1.35M | 185097364U, // STR_PRE_IMM |
1407 | 1.35M | 185101460U, // STR_PRE_REG |
1408 | 1.35M | 556180U, // STRi12 |
1409 | 1.35M | 547988U, // STRrs |
1410 | 1.35M | 530678U, // SUBri |
1411 | 1.35M | 530678U, // SUBrr |
1412 | 1.35M | 559350U, // SUBrsi |
1413 | 1.35M | 39158U, // SUBrsr |
1414 | 1.35M | 1074313567U, // SVC |
1415 | 1.35M | 556081U, // SWP |
1416 | 1.35M | 555175U, // SWPB |
1417 | 1.35M | 546898U, // SXTAB |
1418 | 1.35M | 546523U, // SXTAB16 |
1419 | 1.35M | 547371U, // SXTAH |
1420 | 1.35M | 555242U, // SXTB |
1421 | 1.35M | 554731U, // SXTB16 |
1422 | 1.35M | 555637U, // SXTH |
1423 | 1.35M | 539711U, // TEQri |
1424 | 1.35M | 539711U, // TEQrr |
1425 | 1.35M | 556095U, // TEQrsi |
1426 | 1.35M | 547903U, // TEQrsr |
1427 | 1.35M | 3092U, // TRAP |
1428 | 1.35M | 3092U, // TRAPNaCl |
1429 | 1.35M | 99545U, // TSB |
1430 | 1.35M | 540040U, // TSTri |
1431 | 1.35M | 540040U, // TSTrr |
1432 | 1.35M | 556424U, // TSTrsi |
1433 | 1.35M | 548232U, // TSTrsr |
1434 | 1.35M | 554814U, // UADD16 |
1435 | 1.35M | 554915U, // UADD8 |
1436 | 1.35M | 556739U, // UASX |
1437 | 1.35M | 548511U, // UBFX |
1438 | 1.35M | 828656U, // UDF |
1439 | 1.35M | 556511U, // UDIV |
1440 | 1.35M | 554791U, // UHADD16 |
1441 | 1.35M | 554895U, // UHADD8 |
1442 | 1.35M | 556722U, // UHASX |
1443 | 1.35M | 556581U, // UHSAX |
1444 | 1.35M | 554753U, // UHSUB16 |
1445 | 1.35M | 554856U, // UHSUB8 |
1446 | 1.35M | 580285U, // UMAAL |
1447 | 1.35M | 96990U, // UMLAL |
1448 | 1.35M | 559952U, // UMULL |
1449 | 1.35M | 554799U, // UQADD16 |
1450 | 1.35M | 554902U, // UQADD8 |
1451 | 1.35M | 556728U, // UQASX |
1452 | 1.35M | 556587U, // UQSAX |
1453 | 1.35M | 554761U, // UQSUB16 |
1454 | 1.35M | 554863U, // UQSUB8 |
1455 | 1.35M | 554882U, // USAD8 |
1456 | 1.35M | 546650U, // USADA8 |
1457 | 1.35M | 548098U, // USAT |
1458 | 1.35M | 554828U, // USAT16 |
1459 | 1.35M | 556598U, // USAX |
1460 | 1.35M | 554776U, // USUB16 |
1461 | 1.35M | 554876U, // USUB8 |
1462 | 1.35M | 546904U, // UXTAB |
1463 | 1.35M | 546531U, // UXTAB16 |
1464 | 1.35M | 547377U, // UXTAH |
1465 | 1.35M | 555247U, // UXTB |
1466 | 1.35M | 554738U, // UXTB16 |
1467 | 1.35M | 555642U, // UXTH |
1468 | 1.35M | 169892547U, // VABALsv2i64 |
1469 | 1.35M | 170023619U, // VABALsv4i32 |
1470 | 1.35M | 170154691U, // VABALsv8i16 |
1471 | 1.35M | 170285763U, // VABALuv2i64 |
1472 | 1.35M | 170416835U, // VABALuv4i32 |
1473 | 1.35M | 170547907U, // VABALuv8i16 |
1474 | 1.35M | 170153971U, // VABAsv16i8 |
1475 | 1.35M | 169891827U, // VABAsv2i32 |
1476 | 1.35M | 170022899U, // VABAsv4i16 |
1477 | 1.35M | 169891827U, // VABAsv4i32 |
1478 | 1.35M | 170022899U, // VABAsv8i16 |
1479 | 1.35M | 170153971U, // VABAsv8i8 |
1480 | 1.35M | 170547187U, // VABAuv16i8 |
1481 | 1.35M | 170285043U, // VABAuv2i32 |
1482 | 1.35M | 170416115U, // VABAuv4i16 |
1483 | 1.35M | 170285043U, // VABAuv4i32 |
1484 | 1.35M | 170416115U, // VABAuv8i16 |
1485 | 1.35M | 170547187U, // VABAuv8i8 |
1486 | 1.35M | 186678015U, // VABDLsv2i64 |
1487 | 1.35M | 186809087U, // VABDLsv4i32 |
1488 | 1.35M | 186940159U, // VABDLsv8i16 |
1489 | 1.35M | 187071231U, // VABDLuv2i64 |
1490 | 1.35M | 187202303U, // VABDLuv4i32 |
1491 | 1.35M | 187333375U, // VABDLuv8i16 |
1492 | 1.35M | 253131119U, // VABDfd |
1493 | 1.35M | 253131119U, // VABDfq |
1494 | 1.35M | 253000047U, // VABDhd |
1495 | 1.35M | 253000047U, // VABDhq |
1496 | 1.35M | 186939759U, // VABDsv16i8 |
1497 | 1.35M | 186677615U, // VABDsv2i32 |
1498 | 1.35M | 186808687U, // VABDsv4i16 |
1499 | 1.35M | 186677615U, // VABDsv4i32 |
1500 | 1.35M | 186808687U, // VABDsv8i16 |
1501 | 1.35M | 186939759U, // VABDsv8i8 |
1502 | 1.35M | 187332975U, // VABDuv16i8 |
1503 | 1.35M | 187070831U, // VABDuv2i32 |
1504 | 1.35M | 187201903U, // VABDuv4i16 |
1505 | 1.35M | 187070831U, // VABDuv4i32 |
1506 | 1.35M | 187201903U, // VABDuv8i16 |
1507 | 1.35M | 187332975U, // VABDuv8i8 |
1508 | 1.35M | 252853412U, // VABSD |
1509 | 1.35M | 252984484U, // VABSH |
1510 | 1.35M | 253115556U, // VABSS |
1511 | 1.35M | 253115556U, // VABSfd |
1512 | 1.35M | 253115556U, // VABSfq |
1513 | 1.35M | 252984484U, // VABShd |
1514 | 1.35M | 252984484U, // VABShq |
1515 | 1.35M | 1260666020U, // VABSv16i8 |
1516 | 1.35M | 1260403876U, // VABSv2i32 |
1517 | 1.35M | 1260534948U, // VABSv4i16 |
1518 | 1.35M | 1260403876U, // VABSv4i32 |
1519 | 1.35M | 1260534948U, // VABSv8i16 |
1520 | 1.35M | 1260666020U, // VABSv8i8 |
1521 | 1.35M | 253131233U, // VACGEfd |
1522 | 1.35M | 253131233U, // VACGEfq |
1523 | 1.35M | 253000161U, // VACGEhd |
1524 | 1.35M | 253000161U, // VACGEhq |
1525 | 1.35M | 253132096U, // VACGTfd |
1526 | 1.35M | 253132096U, // VACGTfq |
1527 | 1.35M | 253001024U, // VACGThd |
1528 | 1.35M | 253001024U, // VACGThq |
1529 | 1.35M | 252869011U, // VADDD |
1530 | 1.35M | 253000083U, // VADDH |
1531 | 1.35M | 187464621U, // VADDHNv2i32 |
1532 | 1.35M | 187595693U, // VADDHNv4i16 |
1533 | 1.35M | 187726765U, // VADDHNv8i8 |
1534 | 1.35M | 186678028U, // VADDLsv2i64 |
1535 | 1.35M | 186809100U, // VADDLsv4i32 |
1536 | 1.35M | 186940172U, // VADDLsv8i16 |
1537 | 1.35M | 187071244U, // VADDLuv2i64 |
1538 | 1.35M | 187202316U, // VADDLuv4i32 |
1539 | 1.35M | 187333388U, // VADDLuv8i16 |
1540 | 1.35M | 253131155U, // VADDS |
1541 | 1.35M | 186678772U, // VADDWsv2i64 |
1542 | 1.35M | 186809844U, // VADDWsv4i32 |
1543 | 1.35M | 186940916U, // VADDWsv8i16 |
1544 | 1.35M | 187071988U, // VADDWuv2i64 |
1545 | 1.35M | 187203060U, // VADDWuv4i32 |
1546 | 1.35M | 187334132U, // VADDWuv8i16 |
1547 | 1.35M | 253131155U, // VADDfd |
1548 | 1.35M | 253131155U, // VADDfq |
1549 | 1.35M | 253000083U, // VADDhd |
1550 | 1.35M | 253000083U, // VADDhq |
1551 | 1.35M | 187857299U, // VADDv16i8 |
1552 | 1.35M | 187464083U, // VADDv1i64 |
1553 | 1.35M | 187595155U, // VADDv2i32 |
1554 | 1.35M | 187464083U, // VADDv2i64 |
1555 | 1.35M | 187726227U, // VADDv4i16 |
1556 | 1.35M | 187595155U, // VADDv4i32 |
1557 | 1.35M | 187726227U, // VADDv8i16 |
1558 | 1.35M | 187857299U, // VADDv8i8 |
1559 | 1.35M | 555434U, // VANDd |
1560 | 1.35M | 555434U, // VANDq |
1561 | 1.35M | 555333U, // VBICd |
1562 | 1.35M | 405698885U, // VBICiv2i32 |
1563 | 1.35M | 405829957U, // VBICiv4i16 |
1564 | 1.35M | 405698885U, // VBICiv4i32 |
1565 | 1.35M | 405829957U, // VBICiv8i16 |
1566 | 1.35M | 555333U, // VBICq |
1567 | 1.35M | 547334U, // VBIFd |
1568 | 1.35M | 547334U, // VBIFq |
1569 | 1.35M | 548195U, // VBITd |
1570 | 1.35M | 548195U, // VBITq |
1571 | 1.35M | 547676U, // VBSLd |
1572 | 1.35M | 547676U, // VBSLq |
1573 | 1.35M | 185245957U, // VCADDv2f32 |
1574 | 1.35M | 185246658U, // VCADDv4f16 |
1575 | 1.35M | 185245957U, // VCADDv4f32 |
1576 | 1.35M | 185246658U, // VCADDv8f16 |
1577 | 1.35M | 253131834U, // VCEQfd |
1578 | 1.35M | 253131834U, // VCEQfq |
1579 | 1.35M | 253000762U, // VCEQhd |
1580 | 1.35M | 253000762U, // VCEQhq |
1581 | 1.35M | 187857978U, // VCEQv16i8 |
1582 | 1.35M | 187595834U, // VCEQv2i32 |
1583 | 1.35M | 187726906U, // VCEQv4i16 |
1584 | 1.35M | 187595834U, // VCEQv4i32 |
1585 | 1.35M | 187726906U, // VCEQv8i16 |
1586 | 1.35M | 187857978U, // VCEQv8i8 |
1587 | 1.35M | 1261583418U, // VCEQzv16i8 |
1588 | 1.35M | 253115450U, // VCEQzv2f32 |
1589 | 1.35M | 1261321274U, // VCEQzv2i32 |
1590 | 1.35M | 252984378U, // VCEQzv4f16 |
1591 | 1.35M | 253115450U, // VCEQzv4f32 |
1592 | 1.35M | 1261452346U, // VCEQzv4i16 |
1593 | 1.35M | 1261321274U, // VCEQzv4i32 |
1594 | 1.35M | 252984378U, // VCEQzv8f16 |
1595 | 1.35M | 1261452346U, // VCEQzv8i16 |
1596 | 1.35M | 1261583418U, // VCEQzv8i8 |
1597 | 1.35M | 253131239U, // VCGEfd |
1598 | 1.35M | 253131239U, // VCGEfq |
1599 | 1.35M | 253000167U, // VCGEhd |
1600 | 1.35M | 253000167U, // VCGEhq |
1601 | 1.35M | 186939879U, // VCGEsv16i8 |
1602 | 1.35M | 186677735U, // VCGEsv2i32 |
1603 | 1.35M | 186808807U, // VCGEsv4i16 |
1604 | 1.35M | 186677735U, // VCGEsv4i32 |
1605 | 1.35M | 186808807U, // VCGEsv8i16 |
1606 | 1.35M | 186939879U, // VCGEsv8i8 |
1607 | 1.35M | 187333095U, // VCGEuv16i8 |
1608 | 1.35M | 187070951U, // VCGEuv2i32 |
1609 | 1.35M | 187202023U, // VCGEuv4i16 |
1610 | 1.35M | 187070951U, // VCGEuv4i32 |
1611 | 1.35M | 187202023U, // VCGEuv8i16 |
1612 | 1.35M | 187333095U, // VCGEuv8i8 |
1613 | 1.35M | 1260665319U, // VCGEzv16i8 |
1614 | 1.35M | 253114855U, // VCGEzv2f32 |
1615 | 1.35M | 1260403175U, // VCGEzv2i32 |
1616 | 1.35M | 252983783U, // VCGEzv4f16 |
1617 | 1.35M | 253114855U, // VCGEzv4f32 |
1618 | 1.35M | 1260534247U, // VCGEzv4i16 |
1619 | 1.35M | 1260403175U, // VCGEzv4i32 |
1620 | 1.35M | 252983783U, // VCGEzv8f16 |
1621 | 1.35M | 1260534247U, // VCGEzv8i16 |
1622 | 1.35M | 1260665319U, // VCGEzv8i8 |
1623 | 1.35M | 253132102U, // VCGTfd |
1624 | 1.35M | 253132102U, // VCGTfq |
1625 | 1.35M | 253001030U, // VCGThd |
1626 | 1.35M | 253001030U, // VCGThq |
1627 | 1.35M | 186940742U, // VCGTsv16i8 |
1628 | 1.35M | 186678598U, // VCGTsv2i32 |
1629 | 1.35M | 186809670U, // VCGTsv4i16 |
1630 | 1.35M | 186678598U, // VCGTsv4i32 |
1631 | 1.35M | 186809670U, // VCGTsv8i16 |
1632 | 1.35M | 186940742U, // VCGTsv8i8 |
1633 | 1.35M | 187333958U, // VCGTuv16i8 |
1634 | 1.35M | 187071814U, // VCGTuv2i32 |
1635 | 1.35M | 187202886U, // VCGTuv4i16 |
1636 | 1.35M | 187071814U, // VCGTuv4i32 |
1637 | 1.35M | 187202886U, // VCGTuv8i16 |
1638 | 1.35M | 187333958U, // VCGTuv8i8 |
1639 | 1.35M | 1260666182U, // VCGTzv16i8 |
1640 | 1.35M | 253115718U, // VCGTzv2f32 |
1641 | 1.35M | 1260404038U, // VCGTzv2i32 |
1642 | 1.35M | 252984646U, // VCGTzv4f16 |
1643 | 1.35M | 253115718U, // VCGTzv4f32 |
1644 | 1.35M | 1260535110U, // VCGTzv4i16 |
1645 | 1.35M | 1260404038U, // VCGTzv4i32 |
1646 | 1.35M | 252984646U, // VCGTzv8f16 |
1647 | 1.35M | 1260535110U, // VCGTzv8i16 |
1648 | 1.35M | 1260666182U, // VCGTzv8i8 |
1649 | 1.35M | 1260665324U, // VCLEzv16i8 |
1650 | 1.35M | 253114860U, // VCLEzv2f32 |
1651 | 1.35M | 1260403180U, // VCLEzv2i32 |
1652 | 1.35M | 252983788U, // VCLEzv4f16 |
1653 | 1.35M | 253114860U, // VCLEzv4f32 |
1654 | 1.35M | 1260534252U, // VCLEzv4i16 |
1655 | 1.35M | 1260403180U, // VCLEzv4i32 |
1656 | 1.35M | 252983788U, // VCLEzv8f16 |
1657 | 1.35M | 1260534252U, // VCLEzv8i16 |
1658 | 1.35M | 1260665324U, // VCLEzv8i8 |
1659 | 1.35M | 1260666030U, // VCLSv16i8 |
1660 | 1.35M | 1260403886U, // VCLSv2i32 |
1661 | 1.35M | 1260534958U, // VCLSv4i16 |
1662 | 1.35M | 1260403886U, // VCLSv4i32 |
1663 | 1.35M | 1260534958U, // VCLSv8i16 |
1664 | 1.35M | 1260666030U, // VCLSv8i8 |
1665 | 1.35M | 1260666216U, // VCLTzv16i8 |
1666 | 1.35M | 253115752U, // VCLTzv2f32 |
1667 | 1.35M | 1260404072U, // VCLTzv2i32 |
1668 | 1.35M | 252984680U, // VCLTzv4f16 |
1669 | 1.35M | 253115752U, // VCLTzv4f32 |
1670 | 1.35M | 1260535144U, // VCLTzv4i16 |
1671 | 1.35M | 1260404072U, // VCLTzv4i32 |
1672 | 1.35M | 252984680U, // VCLTzv8f16 |
1673 | 1.35M | 1260535144U, // VCLTzv8i16 |
1674 | 1.35M | 1260666216U, // VCLTzv8i8 |
1675 | 1.35M | 1261584079U, // VCLZv16i8 |
1676 | 1.35M | 1261321935U, // VCLZv2i32 |
1677 | 1.35M | 1261453007U, // VCLZv4i16 |
1678 | 1.35M | 1261321935U, // VCLZv4i32 |
1679 | 1.35M | 1261453007U, // VCLZv8i16 |
1680 | 1.35M | 1261584079U, // VCLZv8i8 |
1681 | 1.35M | 168468718U, // VCMLAv2f32 |
1682 | 1.35M | 168468718U, // VCMLAv2f32_indexed |
1683 | 1.35M | 168469419U, // VCMLAv4f16 |
1684 | 1.35M | 168469419U, // VCMLAv4f16_indexed |
1685 | 1.35M | 168468718U, // VCMLAv4f32 |
1686 | 1.35M | 168468718U, // VCMLAv4f32_indexed |
1687 | 1.35M | 168469419U, // VCMLAv8f16 |
1688 | 1.35M | 168469419U, // VCMLAv8f16_indexed |
1689 | 1.35M | 252853282U, // VCMPD |
1690 | 1.35M | 252852728U, // VCMPED |
1691 | 1.35M | 252983800U, // VCMPEH |
1692 | 1.35M | 253114872U, // VCMPES |
1693 | 1.35M | 420657656U, // VCMPEZD |
1694 | 1.35M | 420788728U, // VCMPEZH |
1695 | 1.35M | 420919800U, // VCMPEZS |
1696 | 1.35M | 252984354U, // VCMPH |
1697 | 1.35M | 253115426U, // VCMPS |
1698 | 1.35M | 420658210U, // VCMPZD |
1699 | 1.35M | 420789282U, // VCMPZH |
1700 | 1.35M | 420920354U, // VCMPZS |
1701 | 1.35M | 408941U, // VCNTd |
1702 | 1.35M | 408941U, // VCNTq |
1703 | 1.35M | 1258987638U, // VCVTANSDf |
1704 | 1.35M | 1258988339U, // VCVTANSDh |
1705 | 1.35M | 1258987638U, // VCVTANSQf |
1706 | 1.35M | 1258988339U, // VCVTANSQh |
1707 | 1.35M | 1258987698U, // VCVTANUDf |
1708 | 1.35M | 1258988399U, // VCVTANUDh |
1709 | 1.35M | 1258987698U, // VCVTANUQf |
1710 | 1.35M | 1258988399U, // VCVTANUQh |
1711 | 1.35M | 1258987968U, // VCVTASD |
1712 | 1.35M | 1258988219U, // VCVTASH |
1713 | 1.35M | 1258987638U, // VCVTASS |
1714 | 1.35M | 1258988028U, // VCVTAUD |
1715 | 1.35M | 1258988279U, // VCVTAUH |
1716 | 1.35M | 1258987698U, // VCVTAUS |
1717 | 1.35M | 3422436U, // VCVTBDH |
1718 | 1.35M | 3553508U, // VCVTBHD |
1719 | 1.35M | 3684580U, // VCVTBHS |
1720 | 1.35M | 3815652U, // VCVTBSH |
1721 | 1.35M | 3947954U, // VCVTDS |
1722 | 1.35M | 1258987653U, // VCVTMNSDf |
1723 | 1.35M | 1258988354U, // VCVTMNSDh |
1724 | 1.35M | 1258987653U, // VCVTMNSQf |
1725 | 1.35M | 1258988354U, // VCVTMNSQh |
1726 | 1.35M | 1258987713U, // VCVTMNUDf |
1727 | 1.35M | 1258988414U, // VCVTMNUDh |
1728 | 1.35M | 1258987713U, // VCVTMNUQf |
1729 | 1.35M | 1258988414U, // VCVTMNUQh |
1730 | 1.35M | 1258987983U, // VCVTMSD |
1731 | 1.35M | 1258988234U, // VCVTMSH |
1732 | 1.35M | 1258987653U, // VCVTMSS |
1733 | 1.35M | 1258988043U, // VCVTMUD |
1734 | 1.35M | 1258988294U, // VCVTMUH |
1735 | 1.35M | 1258987713U, // VCVTMUS |
1736 | 1.35M | 1258987668U, // VCVTNNSDf |
1737 | 1.35M | 1258988369U, // VCVTNNSDh |
1738 | 1.35M | 1258987668U, // VCVTNNSQf |
1739 | 1.35M | 1258988369U, // VCVTNNSQh |
1740 | 1.35M | 1258987728U, // VCVTNNUDf |
1741 | 1.35M | 1258988429U, // VCVTNNUDh |
1742 | 1.35M | 1258987728U, // VCVTNNUQf |
1743 | 1.35M | 1258988429U, // VCVTNNUQh |
1744 | 1.35M | 1258987998U, // VCVTNSD |
1745 | 1.35M | 1258988249U, // VCVTNSH |
1746 | 1.35M | 1258987668U, // VCVTNSS |
1747 | 1.35M | 1258988058U, // VCVTNUD |
1748 | 1.35M | 1258988309U, // VCVTNUH |
1749 | 1.35M | 1258987728U, // VCVTNUS |
1750 | 1.35M | 1258987683U, // VCVTPNSDf |
1751 | 1.35M | 1258988384U, // VCVTPNSDh |
1752 | 1.35M | 1258987683U, // VCVTPNSQf |
1753 | 1.35M | 1258988384U, // VCVTPNSQh |
1754 | 1.35M | 1258987743U, // VCVTPNUDf |
1755 | 1.35M | 1258988444U, // VCVTPNUDh |
1756 | 1.35M | 1258987743U, // VCVTPNUQf |
1757 | 1.35M | 1258988444U, // VCVTPNUQh |
1758 | 1.35M | 1258988013U, // VCVTPSD |
1759 | 1.35M | 1258988264U, // VCVTPSH |
1760 | 1.35M | 1258987683U, // VCVTPSS |
1761 | 1.35M | 1258988073U, // VCVTPUD |
1762 | 1.35M | 1258988324U, // VCVTPUH |
1763 | 1.35M | 1258987743U, // VCVTPUS |
1764 | 1.35M | 4079026U, // VCVTSD |
1765 | 1.35M | 3423654U, // VCVTTDH |
1766 | 1.35M | 3554726U, // VCVTTHD |
1767 | 1.35M | 3685798U, // VCVTTHS |
1768 | 1.35M | 3816870U, // VCVTTSH |
1769 | 1.35M | 3816882U, // VCVTf2h |
1770 | 1.35M | 440417714U, // VCVTf2sd |
1771 | 1.35M | 440417714U, // VCVTf2sq |
1772 | 1.35M | 440548786U, // VCVTf2ud |
1773 | 1.35M | 440548786U, // VCVTf2uq |
1774 | 1.35M | 2403368370U, // VCVTf2xsd |
1775 | 1.35M | 2403368370U, // VCVTf2xsq |
1776 | 1.35M | 2403499442U, // VCVTf2xud |
1777 | 1.35M | 2403499442U, // VCVTf2xuq |
1778 | 1.35M | 3685810U, // VCVTh2f |
1779 | 1.35M | 440679858U, // VCVTh2sd |
1780 | 1.35M | 440679858U, // VCVTh2sq |
1781 | 1.35M | 440810930U, // VCVTh2ud |
1782 | 1.35M | 440810930U, // VCVTh2uq |
1783 | 1.35M | 2403630514U, // VCVTh2xsd |
1784 | 1.35M | 2403630514U, // VCVTh2xsq |
1785 | 1.35M | 2403761586U, // VCVTh2xud |
1786 | 1.35M | 2403761586U, // VCVTh2xuq |
1787 | 1.35M | 440942002U, // VCVTs2fd |
1788 | 1.35M | 440942002U, // VCVTs2fq |
1789 | 1.35M | 441073074U, // VCVTs2hd |
1790 | 1.35M | 441073074U, // VCVTs2hq |
1791 | 1.35M | 441204146U, // VCVTu2fd |
1792 | 1.35M | 441204146U, // VCVTu2fq |
1793 | 1.35M | 441335218U, // VCVTu2hd |
1794 | 1.35M | 441335218U, // VCVTu2hq |
1795 | 1.35M | 2403892658U, // VCVTxs2fd |
1796 | 1.35M | 2403892658U, // VCVTxs2fq |
1797 | 1.35M | 2404023730U, // VCVTxs2hd |
1798 | 1.35M | 2404023730U, // VCVTxs2hq |
1799 | 1.35M | 2404154802U, // VCVTxu2fd |
1800 | 1.35M | 2404154802U, // VCVTxu2fq |
1801 | 1.35M | 2404285874U, // VCVTxu2hd |
1802 | 1.35M | 2404285874U, // VCVTxu2hq |
1803 | 1.35M | 252870116U, // VDIVD |
1804 | 1.35M | 253001188U, // VDIVH |
1805 | 1.35M | 253132260U, // VDIVS |
1806 | 1.35M | 146475U, // VDUP16d |
1807 | 1.35M | 146475U, // VDUP16q |
1808 | 1.35M | 277547U, // VDUP32d |
1809 | 1.35M | 277547U, // VDUP32q |
1810 | 1.35M | 408619U, // VDUP8d |
1811 | 1.35M | 408619U, // VDUP8q |
1812 | 1.35M | 162859U, // VDUPLN16d |
1813 | 1.35M | 162859U, // VDUPLN16q |
1814 | 1.35M | 293931U, // VDUPLN32d |
1815 | 1.35M | 293931U, // VDUPLN32q |
1816 | 1.35M | 425003U, // VDUPLN8d |
1817 | 1.35M | 425003U, // VDUPLN8q |
1818 | 1.35M | 556137U, // VEORd |
1819 | 1.35M | 556137U, // VEORq |
1820 | 1.35M | 155082U, // VEXTd16 |
1821 | 1.35M | 286154U, // VEXTd32 |
1822 | 1.35M | 417226U, // VEXTd8 |
1823 | 1.35M | 155082U, // VEXTq16 |
1824 | 1.35M | 286154U, // VEXTq32 |
1825 | 1.35M | 5266890U, // VEXTq64 |
1826 | 1.35M | 417226U, // VEXTq8 |
1827 | 1.35M | 2400344115U, // VFMAD |
1828 | 1.35M | 2400475187U, // VFMAH |
1829 | 1.35M | 2400606259U, // VFMAS |
1830 | 1.35M | 2400606259U, // VFMAfd |
1831 | 1.35M | 2400606259U, // VFMAfq |
1832 | 1.35M | 2400475187U, // VFMAhd |
1833 | 1.35M | 2400475187U, // VFMAhq |
1834 | 1.35M | 2400345284U, // VFMSD |
1835 | 1.35M | 2400476356U, // VFMSH |
1836 | 1.35M | 2400607428U, // VFMSS |
1837 | 1.35M | 2400607428U, // VFMSfd |
1838 | 1.35M | 2400607428U, // VFMSfq |
1839 | 1.35M | 2400476356U, // VFMShd |
1840 | 1.35M | 2400476356U, // VFMShq |
1841 | 1.35M | 2400344120U, // VFNMAD |
1842 | 1.35M | 2400475192U, // VFNMAH |
1843 | 1.35M | 2400606264U, // VFNMAS |
1844 | 1.35M | 2400345289U, // VFNMSD |
1845 | 1.35M | 2400476361U, // VFNMSH |
1846 | 1.35M | 2400607433U, // VFNMSS |
1847 | 1.35M | 294377U, // VGETLNi32 |
1848 | 1.35M | 3408035305U, // VGETLNs16 |
1849 | 1.35M | 3408166377U, // VGETLNs8 |
1850 | 1.35M | 3408428521U, // VGETLNu16 |
1851 | 1.35M | 3408559593U, // VGETLNu8 |
1852 | 1.35M | 186939777U, // VHADDsv16i8 |
1853 | 1.35M | 186677633U, // VHADDsv2i32 |
1854 | 1.35M | 186808705U, // VHADDsv4i16 |
1855 | 1.35M | 186677633U, // VHADDsv4i32 |
1856 | 1.35M | 186808705U, // VHADDsv8i16 |
1857 | 1.35M | 186939777U, // VHADDsv8i8 |
1858 | 1.35M | 187332993U, // VHADDuv16i8 |
1859 | 1.35M | 187070849U, // VHADDuv2i32 |
1860 | 1.35M | 187201921U, // VHADDuv4i16 |
1861 | 1.35M | 187070849U, // VHADDuv4i32 |
1862 | 1.35M | 187201921U, // VHADDuv8i16 |
1863 | 1.35M | 187332993U, // VHADDuv8i8 |
1864 | 1.35M | 186939642U, // VHSUBsv16i8 |
1865 | 1.35M | 186677498U, // VHSUBsv2i32 |
1866 | 1.35M | 186808570U, // VHSUBsv4i16 |
1867 | 1.35M | 186677498U, // VHSUBsv4i32 |
1868 | 1.35M | 186808570U, // VHSUBsv8i16 |
1869 | 1.35M | 186939642U, // VHSUBsv8i8 |
1870 | 1.35M | 187332858U, // VHSUBuv16i8 |
1871 | 1.35M | 187070714U, // VHSUBuv2i32 |
1872 | 1.35M | 187201786U, // VHSUBuv4i16 |
1873 | 1.35M | 187070714U, // VHSUBuv4i32 |
1874 | 1.35M | 187201786U, // VHSUBuv8i16 |
1875 | 1.35M | 187332858U, // VHSUBuv8i8 |
1876 | 1.35M | 1258988577U, // VINSH |
1877 | 1.35M | 441597356U, // VJCVT |
1878 | 1.35M | 3674371694U, // VLD1DUPd16 |
1879 | 1.35M | 453138030U, // VLD1DUPd16wb_fixed |
1880 | 1.35M | 453142126U, // VLD1DUPd16wb_register |
1881 | 1.35M | 3674502766U, // VLD1DUPd32 |
1882 | 1.35M | 453269102U, // VLD1DUPd32wb_fixed |
1883 | 1.35M | 453273198U, // VLD1DUPd32wb_register |
1884 | 1.35M | 3674633838U, // VLD1DUPd8 |
1885 | 1.35M | 453400174U, // VLD1DUPd8wb_fixed |
1886 | 1.35M | 453404270U, // VLD1DUPd8wb_register |
1887 | 1.35M | 3691148910U, // VLD1DUPq16 |
1888 | 1.35M | 469915246U, // VLD1DUPq16wb_fixed |
1889 | 1.35M | 469919342U, // VLD1DUPq16wb_register |
1890 | 1.35M | 3691279982U, // VLD1DUPq32 |
1891 | 1.35M | 470046318U, // VLD1DUPq32wb_fixed |
1892 | 1.35M | 470050414U, // VLD1DUPq32wb_register |
1893 | 1.35M | 3691411054U, // VLD1DUPq8 |
1894 | 1.35M | 470177390U, // VLD1DUPq8wb_fixed |
1895 | 1.35M | 470181486U, // VLD1DUPq8wb_register |
1896 | 1.35M | 1079273070U, // VLD1LNd16 |
1897 | 1.35M | 1079350894U, // VLD1LNd16_UPD |
1898 | 1.35M | 1079404142U, // VLD1LNd32 |
1899 | 1.35M | 1079481966U, // VLD1LNd32_UPD |
1900 | 1.35M | 1079535214U, // VLD1LNd8 |
1901 | 1.35M | 1079613038U, // VLD1LNd8_UPD |
1902 | 1.35M | 0U, // VLD1LNq16Pseudo |
1903 | 1.35M | 0U, // VLD1LNq16Pseudo_UPD |
1904 | 1.35M | 0U, // VLD1LNq32Pseudo |
1905 | 1.35M | 0U, // VLD1LNq32Pseudo_UPD |
1906 | 1.35M | 0U, // VLD1LNq8Pseudo |
1907 | 1.35M | 0U, // VLD1LNq8Pseudo_UPD |
1908 | 1.35M | 3707926126U, // VLD1d16 |
1909 | 1.35M | 3355604590U, // VLD1d16Q |
1910 | 1.35M | 0U, // VLD1d16QPseudo |
1911 | 1.35M | 134370926U, // VLD1d16Qwb_fixed |
1912 | 1.35M | 134375022U, // VLD1d16Qwb_register |
1913 | 1.35M | 3288495726U, // VLD1d16T |
1914 | 1.35M | 0U, // VLD1d16TPseudo |
1915 | 1.35M | 67262062U, // VLD1d16Twb_fixed |
1916 | 1.35M | 67266158U, // VLD1d16Twb_register |
1917 | 1.35M | 486692462U, // VLD1d16wb_fixed |
1918 | 1.35M | 486696558U, // VLD1d16wb_register |
1919 | 1.35M | 3708057198U, // VLD1d32 |
1920 | 1.35M | 3355735662U, // VLD1d32Q |
1921 | 1.35M | 0U, // VLD1d32QPseudo |
1922 | 1.35M | 134501998U, // VLD1d32Qwb_fixed |
1923 | 1.35M | 134506094U, // VLD1d32Qwb_register |
1924 | 1.35M | 3288626798U, // VLD1d32T |
1925 | 1.35M | 0U, // VLD1d32TPseudo |
1926 | 1.35M | 67393134U, // VLD1d32Twb_fixed |
1927 | 1.35M | 67397230U, // VLD1d32Twb_register |
1928 | 1.35M | 486823534U, // VLD1d32wb_fixed |
1929 | 1.35M | 486827630U, // VLD1d32wb_register |
1930 | 1.35M | 3713037934U, // VLD1d64 |
1931 | 1.35M | 3360716398U, // VLD1d64Q |
1932 | 1.35M | 0U, // VLD1d64QPseudo |
1933 | 1.35M | 0U, // VLD1d64QPseudoWB_fixed |
1934 | 1.35M | 0U, // VLD1d64QPseudoWB_register |
1935 | 1.35M | 139482734U, // VLD1d64Qwb_fixed |
1936 | 1.35M | 139486830U, // VLD1d64Qwb_register |
1937 | 1.35M | 3293607534U, // VLD1d64T |
1938 | 1.35M | 0U, // VLD1d64TPseudo |
1939 | 1.35M | 0U, // VLD1d64TPseudoWB_fixed |
1940 | 1.35M | 0U, // VLD1d64TPseudoWB_register |
1941 | 1.35M | 72373870U, // VLD1d64Twb_fixed |
1942 | 1.35M | 72377966U, // VLD1d64Twb_register |
1943 | 1.35M | 491804270U, // VLD1d64wb_fixed |
1944 | 1.35M | 491808366U, // VLD1d64wb_register |
1945 | 1.35M | 3708188270U, // VLD1d8 |
1946 | 1.35M | 3355866734U, // VLD1d8Q |
1947 | 1.35M | 0U, // VLD1d8QPseudo |
1948 | 1.35M | 134633070U, // VLD1d8Qwb_fixed |
1949 | 1.35M | 134637166U, // VLD1d8Qwb_register |
1950 | 1.35M | 3288757870U, // VLD1d8T |
1951 | 1.35M | 0U, // VLD1d8TPseudo |
1952 | 1.35M | 67524206U, // VLD1d8Twb_fixed |
1953 | 1.35M | 67528302U, // VLD1d8Twb_register |
1954 | 1.35M | 486954606U, // VLD1d8wb_fixed |
1955 | 1.35M | 486958702U, // VLD1d8wb_register |
1956 | 1.35M | 3724703342U, // VLD1q16 |
1957 | 1.35M | 0U, // VLD1q16HighQPseudo |
1958 | 1.35M | 0U, // VLD1q16HighTPseudo |
1959 | 1.35M | 0U, // VLD1q16LowQPseudo_UPD |
1960 | 1.35M | 0U, // VLD1q16LowTPseudo_UPD |
1961 | 1.35M | 503469678U, // VLD1q16wb_fixed |
1962 | 1.35M | 503473774U, // VLD1q16wb_register |
1963 | 1.35M | 3724834414U, // VLD1q32 |
1964 | 1.35M | 0U, // VLD1q32HighQPseudo |
1965 | 1.35M | 0U, // VLD1q32HighTPseudo |
1966 | 1.35M | 0U, // VLD1q32LowQPseudo_UPD |
1967 | 1.35M | 0U, // VLD1q32LowTPseudo_UPD |
1968 | 1.35M | 503600750U, // VLD1q32wb_fixed |
1969 | 1.35M | 503604846U, // VLD1q32wb_register |
1970 | 1.35M | 3729815150U, // VLD1q64 |
1971 | 1.35M | 0U, // VLD1q64HighQPseudo |
1972 | 1.35M | 0U, // VLD1q64HighTPseudo |
1973 | 1.35M | 0U, // VLD1q64LowQPseudo_UPD |
1974 | 1.35M | 0U, // VLD1q64LowTPseudo_UPD |
1975 | 1.35M | 508581486U, // VLD1q64wb_fixed |
1976 | 1.35M | 508585582U, // VLD1q64wb_register |
1977 | 1.35M | 3724965486U, // VLD1q8 |
1978 | 1.35M | 0U, // VLD1q8HighQPseudo |
1979 | 1.35M | 0U, // VLD1q8HighTPseudo |
1980 | 1.35M | 0U, // VLD1q8LowQPseudo_UPD |
1981 | 1.35M | 0U, // VLD1q8LowTPseudo_UPD |
1982 | 1.35M | 503731822U, // VLD1q8wb_fixed |
1983 | 1.35M | 503735918U, // VLD1q8wb_register |
1984 | 1.35M | 3691148954U, // VLD2DUPd16 |
1985 | 1.35M | 469915290U, // VLD2DUPd16wb_fixed |
1986 | 1.35M | 469919386U, // VLD2DUPd16wb_register |
1987 | 1.35M | 3741480602U, // VLD2DUPd16x2 |
1988 | 1.35M | 520246938U, // VLD2DUPd16x2wb_fixed |
1989 | 1.35M | 520251034U, // VLD2DUPd16x2wb_register |
1990 | 1.35M | 3691280026U, // VLD2DUPd32 |
1991 | 1.35M | 470046362U, // VLD2DUPd32wb_fixed |
1992 | 1.35M | 470050458U, // VLD2DUPd32wb_register |
1993 | 1.35M | 3741611674U, // VLD2DUPd32x2 |
1994 | 1.35M | 520378010U, // VLD2DUPd32x2wb_fixed |
1995 | 1.35M | 520382106U, // VLD2DUPd32x2wb_register |
1996 | 1.35M | 3691411098U, // VLD2DUPd8 |
1997 | 1.35M | 470177434U, // VLD2DUPd8wb_fixed |
1998 | 1.35M | 470181530U, // VLD2DUPd8wb_register |
1999 | 1.35M | 3741742746U, // VLD2DUPd8x2 |
2000 | 1.35M | 520509082U, // VLD2DUPd8x2wb_fixed |
2001 | 1.35M | 520513178U, // VLD2DUPd8x2wb_register |
2002 | 1.35M | 0U, // VLD2DUPq16EvenPseudo |
2003 | 1.35M | 0U, // VLD2DUPq16OddPseudo |
2004 | 1.35M | 0U, // VLD2DUPq32EvenPseudo |
2005 | 1.35M | 0U, // VLD2DUPq32OddPseudo |
2006 | 1.35M | 0U, // VLD2DUPq8EvenPseudo |
2007 | 1.35M | 0U, // VLD2DUPq8OddPseudo |
2008 | 1.35M | 1079350938U, // VLD2LNd16 |
2009 | 1.35M | 0U, // VLD2LNd16Pseudo |
2010 | 1.35M | 0U, // VLD2LNd16Pseudo_UPD |
2011 | 1.35M | 1079355034U, // VLD2LNd16_UPD |
2012 | 1.35M | 1079482010U, // VLD2LNd32 |
2013 | 1.35M | 0U, // VLD2LNd32Pseudo |
2014 | 1.35M | 0U, // VLD2LNd32Pseudo_UPD |
2015 | 1.35M | 1079486106U, // VLD2LNd32_UPD |
2016 | 1.35M | 1079613082U, // VLD2LNd8 |
2017 | 1.35M | 0U, // VLD2LNd8Pseudo |
2018 | 1.35M | 0U, // VLD2LNd8Pseudo_UPD |
2019 | 1.35M | 1079617178U, // VLD2LNd8_UPD |
2020 | 1.35M | 1079350938U, // VLD2LNq16 |
2021 | 1.35M | 0U, // VLD2LNq16Pseudo |
2022 | 1.35M | 0U, // VLD2LNq16Pseudo_UPD |
2023 | 1.35M | 1079355034U, // VLD2LNq16_UPD |
2024 | 1.35M | 1079482010U, // VLD2LNq32 |
2025 | 1.35M | 0U, // VLD2LNq32Pseudo |
2026 | 1.35M | 0U, // VLD2LNq32Pseudo_UPD |
2027 | 1.35M | 1079486106U, // VLD2LNq32_UPD |
2028 | 1.35M | 3758257818U, // VLD2b16 |
2029 | 1.35M | 537024154U, // VLD2b16wb_fixed |
2030 | 1.35M | 537028250U, // VLD2b16wb_register |
2031 | 1.35M | 3758388890U, // VLD2b32 |
2032 | 1.35M | 537155226U, // VLD2b32wb_fixed |
2033 | 1.35M | 537159322U, // VLD2b32wb_register |
2034 | 1.35M | 3758519962U, // VLD2b8 |
2035 | 1.35M | 537286298U, // VLD2b8wb_fixed |
2036 | 1.35M | 537290394U, // VLD2b8wb_register |
2037 | 1.35M | 3724703386U, // VLD2d16 |
2038 | 1.35M | 503469722U, // VLD2d16wb_fixed |
2039 | 1.35M | 503473818U, // VLD2d16wb_register |
2040 | 1.35M | 3724834458U, // VLD2d32 |
2041 | 1.35M | 503600794U, // VLD2d32wb_fixed |
2042 | 1.35M | 503604890U, // VLD2d32wb_register |
2043 | 1.35M | 3724965530U, // VLD2d8 |
2044 | 1.35M | 503731866U, // VLD2d8wb_fixed |
2045 | 1.35M | 503735962U, // VLD2d8wb_register |
2046 | 1.35M | 3355604634U, // VLD2q16 |
2047 | 1.35M | 0U, // VLD2q16Pseudo |
2048 | 1.35M | 0U, // VLD2q16PseudoWB_fixed |
2049 | 1.35M | 0U, // VLD2q16PseudoWB_register |
2050 | 1.35M | 134370970U, // VLD2q16wb_fixed |
2051 | 1.35M | 134375066U, // VLD2q16wb_register |
2052 | 1.35M | 3355735706U, // VLD2q32 |
2053 | 1.35M | 0U, // VLD2q32Pseudo |
2054 | 1.35M | 0U, // VLD2q32PseudoWB_fixed |
2055 | 1.35M | 0U, // VLD2q32PseudoWB_register |
2056 | 1.35M | 134502042U, // VLD2q32wb_fixed |
2057 | 1.35M | 134506138U, // VLD2q32wb_register |
2058 | 1.35M | 3355866778U, // VLD2q8 |
2059 | 1.35M | 0U, // VLD2q8Pseudo |
2060 | 1.35M | 0U, // VLD2q8PseudoWB_fixed |
2061 | 1.35M | 0U, // VLD2q8PseudoWB_register |
2062 | 1.35M | 134633114U, // VLD2q8wb_fixed |
2063 | 1.35M | 134637210U, // VLD2q8wb_register |
2064 | 1.35M | 2153014970U, // VLD3DUPd16 |
2065 | 1.35M | 0U, // VLD3DUPd16Pseudo |
2066 | 1.35M | 0U, // VLD3DUPd16Pseudo_UPD |
2067 | 1.35M | 2153092794U, // VLD3DUPd16_UPD |
2068 | 1.35M | 2153146042U, // VLD3DUPd32 |
2069 | 1.35M | 0U, // VLD3DUPd32Pseudo |
2070 | 1.35M | 0U, // VLD3DUPd32Pseudo_UPD |
2071 | 1.35M | 2153223866U, // VLD3DUPd32_UPD |
2072 | 1.35M | 2153277114U, // VLD3DUPd8 |
2073 | 1.35M | 0U, // VLD3DUPd8Pseudo |
2074 | 1.35M | 0U, // VLD3DUPd8Pseudo_UPD |
2075 | 1.35M | 2153354938U, // VLD3DUPd8_UPD |
2076 | 1.35M | 2153014970U, // VLD3DUPq16 |
2077 | 1.35M | 0U, // VLD3DUPq16EvenPseudo |
2078 | 1.35M | 0U, // VLD3DUPq16OddPseudo |
2079 | 1.35M | 2153092794U, // VLD3DUPq16_UPD |
2080 | 1.35M | 2153146042U, // VLD3DUPq32 |
2081 | 1.35M | 0U, // VLD3DUPq32EvenPseudo |
2082 | 1.35M | 0U, // VLD3DUPq32OddPseudo |
2083 | 1.35M | 2153223866U, // VLD3DUPq32_UPD |
2084 | 1.35M | 2153277114U, // VLD3DUPq8 |
2085 | 1.35M | 0U, // VLD3DUPq8EvenPseudo |
2086 | 1.35M | 0U, // VLD3DUPq8OddPseudo |
2087 | 1.35M | 2153354938U, // VLD3DUPq8_UPD |
2088 | 1.35M | 1079355066U, // VLD3LNd16 |
2089 | 1.35M | 0U, // VLD3LNd16Pseudo |
2090 | 1.35M | 0U, // VLD3LNd16Pseudo_UPD |
2091 | 1.35M | 1079359162U, // VLD3LNd16_UPD |
2092 | 1.35M | 1079486138U, // VLD3LNd32 |
2093 | 1.35M | 0U, // VLD3LNd32Pseudo |
2094 | 1.35M | 0U, // VLD3LNd32Pseudo_UPD |
2095 | 1.35M | 1079490234U, // VLD3LNd32_UPD |
2096 | 1.35M | 1079617210U, // VLD3LNd8 |
2097 | 1.35M | 0U, // VLD3LNd8Pseudo |
2098 | 1.35M | 0U, // VLD3LNd8Pseudo_UPD |
2099 | 1.35M | 1079621306U, // VLD3LNd8_UPD |
2100 | 1.35M | 1079355066U, // VLD3LNq16 |
2101 | 1.35M | 0U, // VLD3LNq16Pseudo |
2102 | 1.35M | 0U, // VLD3LNq16Pseudo_UPD |
2103 | 1.35M | 1079359162U, // VLD3LNq16_UPD |
2104 | 1.35M | 1079486138U, // VLD3LNq32 |
2105 | 1.35M | 0U, // VLD3LNq32Pseudo |
2106 | 1.35M | 0U, // VLD3LNq32Pseudo_UPD |
2107 | 1.35M | 1079490234U, // VLD3LNq32_UPD |
2108 | 1.35M | 5531322U, // VLD3d16 |
2109 | 1.35M | 0U, // VLD3d16Pseudo |
2110 | 1.35M | 0U, // VLD3d16Pseudo_UPD |
2111 | 1.35M | 5609146U, // VLD3d16_UPD |
2112 | 1.35M | 5662394U, // VLD3d32 |
2113 | 1.35M | 0U, // VLD3d32Pseudo |
2114 | 1.35M | 0U, // VLD3d32Pseudo_UPD |
2115 | 1.35M | 5740218U, // VLD3d32_UPD |
2116 | 1.35M | 5793466U, // VLD3d8 |
2117 | 1.35M | 0U, // VLD3d8Pseudo |
2118 | 1.35M | 0U, // VLD3d8Pseudo_UPD |
2119 | 1.35M | 5871290U, // VLD3d8_UPD |
2120 | 1.35M | 5531322U, // VLD3q16 |
2121 | 1.35M | 0U, // VLD3q16Pseudo_UPD |
2122 | 1.35M | 5609146U, // VLD3q16_UPD |
2123 | 1.35M | 0U, // VLD3q16oddPseudo |
2124 | 1.35M | 0U, // VLD3q16oddPseudo_UPD |
2125 | 1.35M | 5662394U, // VLD3q32 |
2126 | 1.35M | 0U, // VLD3q32Pseudo_UPD |
2127 | 1.35M | 5740218U, // VLD3q32_UPD |
2128 | 1.35M | 0U, // VLD3q32oddPseudo |
2129 | 1.35M | 0U, // VLD3q32oddPseudo_UPD |
2130 | 1.35M | 5793466U, // VLD3q8 |
2131 | 1.35M | 0U, // VLD3q8Pseudo_UPD |
2132 | 1.35M | 5871290U, // VLD3q8_UPD |
2133 | 1.35M | 0U, // VLD3q8oddPseudo |
2134 | 1.35M | 0U, // VLD3q8oddPseudo_UPD |
2135 | 1.35M | 2153043665U, // VLD4DUPd16 |
2136 | 1.35M | 0U, // VLD4DUPd16Pseudo |
2137 | 1.35M | 0U, // VLD4DUPd16Pseudo_UPD |
2138 | 1.35M | 2153105105U, // VLD4DUPd16_UPD |
2139 | 1.35M | 2153174737U, // VLD4DUPd32 |
2140 | 1.35M | 0U, // VLD4DUPd32Pseudo |
2141 | 1.35M | 0U, // VLD4DUPd32Pseudo_UPD |
2142 | 1.35M | 2153236177U, // VLD4DUPd32_UPD |
2143 | 1.35M | 2153305809U, // VLD4DUPd8 |
2144 | 1.35M | 0U, // VLD4DUPd8Pseudo |
2145 | 1.35M | 0U, // VLD4DUPd8Pseudo_UPD |
2146 | 1.35M | 2153367249U, // VLD4DUPd8_UPD |
2147 | 1.35M | 2153043665U, // VLD4DUPq16 |
2148 | 1.35M | 0U, // VLD4DUPq16EvenPseudo |
2149 | 1.35M | 0U, // VLD4DUPq16OddPseudo |
2150 | 1.35M | 2153105105U, // VLD4DUPq16_UPD |
2151 | 1.35M | 2153174737U, // VLD4DUPq32 |
2152 | 1.35M | 0U, // VLD4DUPq32EvenPseudo |
2153 | 1.35M | 0U, // VLD4DUPq32OddPseudo |
2154 | 1.35M | 2153236177U, // VLD4DUPq32_UPD |
2155 | 1.35M | 2153305809U, // VLD4DUPq8 |
2156 | 1.35M | 0U, // VLD4DUPq8EvenPseudo |
2157 | 1.35M | 0U, // VLD4DUPq8OddPseudo |
2158 | 1.35M | 2153367249U, // VLD4DUPq8_UPD |
2159 | 1.35M | 1079359185U, // VLD4LNd16 |
2160 | 1.35M | 0U, // VLD4LNd16Pseudo |
2161 | 1.35M | 0U, // VLD4LNd16Pseudo_UPD |
2162 | 1.35M | 1079367377U, // VLD4LNd16_UPD |
2163 | 1.35M | 1079490257U, // VLD4LNd32 |
2164 | 1.35M | 0U, // VLD4LNd32Pseudo |
2165 | 1.35M | 0U, // VLD4LNd32Pseudo_UPD |
2166 | 1.35M | 1079498449U, // VLD4LNd32_UPD |
2167 | 1.35M | 1079621329U, // VLD4LNd8 |
2168 | 1.35M | 0U, // VLD4LNd8Pseudo |
2169 | 1.35M | 0U, // VLD4LNd8Pseudo_UPD |
2170 | 1.35M | 1079629521U, // VLD4LNd8_UPD |
2171 | 1.35M | 1079359185U, // VLD4LNq16 |
2172 | 1.35M | 0U, // VLD4LNq16Pseudo |
2173 | 1.35M | 0U, // VLD4LNq16Pseudo_UPD |
2174 | 1.35M | 1079367377U, // VLD4LNq16_UPD |
2175 | 1.35M | 1079490257U, // VLD4LNq32 |
2176 | 1.35M | 0U, // VLD4LNq32Pseudo |
2177 | 1.35M | 0U, // VLD4LNq32Pseudo_UPD |
2178 | 1.35M | 1079498449U, // VLD4LNq32_UPD |
2179 | 1.35M | 5560017U, // VLD4d16 |
2180 | 1.35M | 0U, // VLD4d16Pseudo |
2181 | 1.35M | 0U, // VLD4d16Pseudo_UPD |
2182 | 1.35M | 5621457U, // VLD4d16_UPD |
2183 | 1.35M | 5691089U, // VLD4d32 |
2184 | 1.35M | 0U, // VLD4d32Pseudo |
2185 | 1.35M | 0U, // VLD4d32Pseudo_UPD |
2186 | 1.35M | 5752529U, // VLD4d32_UPD |
2187 | 1.35M | 5822161U, // VLD4d8 |
2188 | 1.35M | 0U, // VLD4d8Pseudo |
2189 | 1.35M | 0U, // VLD4d8Pseudo_UPD |
2190 | 1.35M | 5883601U, // VLD4d8_UPD |
2191 | 1.35M | 5560017U, // VLD4q16 |
2192 | 1.35M | 0U, // VLD4q16Pseudo_UPD |
2193 | 1.35M | 5621457U, // VLD4q16_UPD |
2194 | 1.35M | 0U, // VLD4q16oddPseudo |
2195 | 1.35M | 0U, // VLD4q16oddPseudo_UPD |
2196 | 1.35M | 5691089U, // VLD4q32 |
2197 | 1.35M | 0U, // VLD4q32Pseudo_UPD |
2198 | 1.35M | 5752529U, // VLD4q32_UPD |
2199 | 1.35M | 0U, // VLD4q32oddPseudo |
2200 | 1.35M | 0U, // VLD4q32oddPseudo_UPD |
2201 | 1.35M | 5822161U, // VLD4q8 |
2202 | 1.35M | 0U, // VLD4q8Pseudo_UPD |
2203 | 1.35M | 5883601U, // VLD4q8_UPD |
2204 | 1.35M | 0U, // VLD4q8oddPseudo |
2205 | 1.35M | 0U, // VLD4q8oddPseudo_UPD |
2206 | 1.35M | 2332571774U, // VLDMDDB_UPD |
2207 | 1.35M | 571406U, // VLDMDIA |
2208 | 1.35M | 2332571662U, // VLDMDIA_UPD |
2209 | 1.35M | 0U, // VLDMQIA |
2210 | 1.35M | 2332571774U, // VLDMSDB_UPD |
2211 | 1.35M | 571406U, // VLDMSIA |
2212 | 1.35M | 2332571662U, // VLDMSIA_UPD |
2213 | 1.35M | 556114U, // VLDRD |
2214 | 1.35M | 162898U, // VLDRH |
2215 | 1.35M | 556114U, // VLDRS |
2216 | 1.35M | 1074314122U, // VLLDM |
2217 | 1.35M | 1074314128U, // VLSTM |
2218 | 1.35M | 185246300U, // VMAXNMD |
2219 | 1.35M | 185246693U, // VMAXNMH |
2220 | 1.35M | 185245992U, // VMAXNMNDf |
2221 | 1.35M | 185246693U, // VMAXNMNDh |
2222 | 1.35M | 185245992U, // VMAXNMNQf |
2223 | 1.35M | 185246693U, // VMAXNMNQh |
2224 | 1.35M | 185245992U, // VMAXNMS |
2225 | 1.35M | 253132314U, // VMAXfd |
2226 | 1.35M | 253132314U, // VMAXfq |
2227 | 1.35M | 253001242U, // VMAXhd |
2228 | 1.35M | 253001242U, // VMAXhq |
2229 | 1.35M | 186940954U, // VMAXsv16i8 |
2230 | 1.35M | 186678810U, // VMAXsv2i32 |
2231 | 1.35M | 186809882U, // VMAXsv4i16 |
2232 | 1.35M | 186678810U, // VMAXsv4i32 |
2233 | 1.35M | 186809882U, // VMAXsv8i16 |
2234 | 1.35M | 186940954U, // VMAXsv8i8 |
2235 | 1.35M | 187334170U, // VMAXuv16i8 |
2236 | 1.35M | 187072026U, // VMAXuv2i32 |
2237 | 1.35M | 187203098U, // VMAXuv4i16 |
2238 | 1.35M | 187072026U, // VMAXuv4i32 |
2239 | 1.35M | 187203098U, // VMAXuv8i16 |
2240 | 1.35M | 187334170U, // VMAXuv8i8 |
2241 | 1.35M | 185246288U, // VMINNMD |
2242 | 1.35M | 185246681U, // VMINNMH |
2243 | 1.35M | 185245980U, // VMINNMNDf |
2244 | 1.35M | 185246681U, // VMINNMNDh |
2245 | 1.35M | 185245980U, // VMINNMNQf |
2246 | 1.35M | 185246681U, // VMINNMNQh |
2247 | 1.35M | 185245980U, // VMINNMS |
2248 | 1.35M | 253131706U, // VMINfd |
2249 | 1.35M | 253131706U, // VMINfq |
2250 | 1.35M | 253000634U, // VMINhd |
2251 | 1.35M | 253000634U, // VMINhq |
2252 | 1.35M | 186940346U, // VMINsv16i8 |
2253 | 1.35M | 186678202U, // VMINsv2i32 |
2254 | 1.35M | 186809274U, // VMINsv4i16 |
2255 | 1.35M | 186678202U, // VMINsv4i32 |
2256 | 1.35M | 186809274U, // VMINsv8i16 |
2257 | 1.35M | 186940346U, // VMINsv8i8 |
2258 | 1.35M | 187333562U, // VMINuv16i8 |
2259 | 1.35M | 187071418U, // VMINuv2i32 |
2260 | 1.35M | 187202490U, // VMINuv4i16 |
2261 | 1.35M | 187071418U, // VMINuv4i32 |
2262 | 1.35M | 187202490U, // VMINuv8i16 |
2263 | 1.35M | 187333562U, // VMINuv8i8 |
2264 | 1.35M | 2400344110U, // VMLAD |
2265 | 1.35M | 2400475182U, // VMLAH |
2266 | 1.35M | 169896676U, // VMLALslsv2i32 |
2267 | 1.35M | 170027748U, // VMLALslsv4i16 |
2268 | 1.35M | 170289892U, // VMLALsluv2i32 |
2269 | 1.35M | 170420964U, // VMLALsluv4i16 |
2270 | 1.35M | 169892580U, // VMLALsv2i64 |
2271 | 1.35M | 170023652U, // VMLALsv4i32 |
2272 | 1.35M | 170154724U, // VMLALsv8i16 |
2273 | 1.35M | 170285796U, // VMLALuv2i64 |
2274 | 1.35M | 170416868U, // VMLALuv4i32 |
2275 | 1.35M | 170547940U, // VMLALuv8i16 |
2276 | 1.35M | 2400606254U, // VMLAS |
2277 | 1.35M | 2400606254U, // VMLAfd |
2278 | 1.35M | 2400606254U, // VMLAfq |
2279 | 1.35M | 2400475182U, // VMLAhd |
2280 | 1.35M | 2400475182U, // VMLAhq |
2281 | 1.35M | 2400610350U, // VMLAslfd |
2282 | 1.35M | 2400610350U, // VMLAslfq |
2283 | 1.35M | 2400479278U, // VMLAslhd |
2284 | 1.35M | 2400479278U, // VMLAslhq |
2285 | 1.35M | 170813486U, // VMLAslv2i32 |
2286 | 1.35M | 170944558U, // VMLAslv4i16 |
2287 | 1.35M | 170813486U, // VMLAslv4i32 |
2288 | 1.35M | 170944558U, // VMLAslv8i16 |
2289 | 1.35M | 171071534U, // VMLAv16i8 |
2290 | 1.35M | 170809390U, // VMLAv2i32 |
2291 | 1.35M | 170940462U, // VMLAv4i16 |
2292 | 1.35M | 170809390U, // VMLAv4i32 |
2293 | 1.35M | 170940462U, // VMLAv8i16 |
2294 | 1.35M | 171071534U, // VMLAv8i8 |
2295 | 1.35M | 2400345279U, // VMLSD |
2296 | 1.35M | 2400476351U, // VMLSH |
2297 | 1.35M | 169896809U, // VMLSLslsv2i32 |
2298 | 1.35M | 170027881U, // VMLSLslsv4i16 |
2299 | 1.35M | 170290025U, // VMLSLsluv2i32 |
2300 | 1.35M | 170421097U, // VMLSLsluv4i16 |
2301 | 1.35M | 169892713U, // VMLSLsv2i64 |
2302 | 1.35M | 170023785U, // VMLSLsv4i32 |
2303 | 1.35M | 170154857U, // VMLSLsv8i16 |
2304 | 1.35M | 170285929U, // VMLSLuv2i64 |
2305 | 1.35M | 170417001U, // VMLSLuv4i32 |
2306 | 1.35M | 170548073U, // VMLSLuv8i16 |
2307 | 1.35M | 2400607423U, // VMLSS |
2308 | 1.35M | 2400607423U, // VMLSfd |
2309 | 1.35M | 2400607423U, // VMLSfq |
2310 | 1.35M | 2400476351U, // VMLShd |
2311 | 1.35M | 2400476351U, // VMLShq |
2312 | 1.35M | 2400611519U, // VMLSslfd |
2313 | 1.35M | 2400611519U, // VMLSslfq |
2314 | 1.35M | 2400480447U, // VMLSslhd |
2315 | 1.35M | 2400480447U, // VMLSslhq |
2316 | 1.35M | 170814655U, // VMLSslv2i32 |
2317 | 1.35M | 170945727U, // VMLSslv4i16 |
2318 | 1.35M | 170814655U, // VMLSslv4i32 |
2319 | 1.35M | 170945727U, // VMLSslv8i16 |
2320 | 1.35M | 171072703U, // VMLSv16i8 |
2321 | 1.35M | 170810559U, // VMLSv2i32 |
2322 | 1.35M | 170941631U, // VMLSv4i16 |
2323 | 1.35M | 170810559U, // VMLSv4i32 |
2324 | 1.35M | 170941631U, // VMLSv8i16 |
2325 | 1.35M | 171072703U, // VMLSv8i8 |
2326 | 1.35M | 252853737U, // VMOVD |
2327 | 1.35M | 556521U, // VMOVDRR |
2328 | 1.35M | 1258988623U, // VMOVH |
2329 | 1.35M | 252984809U, // VMOVHR |
2330 | 1.35M | 1260403588U, // VMOVLsv2i64 |
2331 | 1.35M | 1260534660U, // VMOVLsv4i32 |
2332 | 1.35M | 1260665732U, // VMOVLsv8i16 |
2333 | 1.35M | 1260796804U, // VMOVLuv2i64 |
2334 | 1.35M | 1260927876U, // VMOVLuv4i32 |
2335 | 1.35M | 1261058948U, // VMOVLuv8i16 |
2336 | 1.35M | 1261190158U, // VMOVNv2i32 |
2337 | 1.35M | 1261321230U, // VMOVNv4i16 |
2338 | 1.35M | 1261452302U, // VMOVNv8i8 |
2339 | 1.35M | 252984809U, // VMOVRH |
2340 | 1.35M | 556521U, // VMOVRRD |
2341 | 1.35M | 548329U, // VMOVRRS |
2342 | 1.35M | 540137U, // VMOVRS |
2343 | 1.35M | 253115881U, // VMOVS |
2344 | 1.35M | 540137U, // VMOVSR |
2345 | 1.35M | 548329U, // VMOVSRR |
2346 | 1.35M | 405945833U, // VMOVv16i8 |
2347 | 1.35M | 405552617U, // VMOVv1i64 |
2348 | 1.35M | 1326857705U, // VMOVv2f32 |
2349 | 1.35M | 405683689U, // VMOVv2i32 |
2350 | 1.35M | 405552617U, // VMOVv2i64 |
2351 | 1.35M | 1326857705U, // VMOVv4f32 |
2352 | 1.35M | 405814761U, // VMOVv4i16 |
2353 | 1.35M | 405683689U, // VMOVv4i32 |
2354 | 1.35M | 405814761U, // VMOVv8i16 |
2355 | 1.35M | 405945833U, // VMOVv8i8 |
2356 | 1.35M | 3221798113U, // VMRS |
2357 | 1.35M | 572641U, // VMRS_FPEXC |
2358 | 1.35M | 1074314465U, // VMRS_FPINST |
2359 | 1.35M | 2148056289U, // VMRS_FPINST2 |
2360 | 1.35M | 3221798113U, // VMRS_FPSID |
2361 | 1.35M | 572641U, // VMRS_MVFR0 |
2362 | 1.35M | 1074314465U, // VMRS_MVFR1 |
2363 | 1.35M | 2148056289U, // VMRS_MVFR2 |
2364 | 1.35M | 5946503U, // VMSR |
2365 | 1.35M | 6077575U, // VMSR_FPEXC |
2366 | 1.35M | 6208647U, // VMSR_FPINST |
2367 | 1.35M | 6339719U, // VMSR_FPINST2 |
2368 | 1.35M | 6470791U, // VMSR_FPSID |
2369 | 1.35M | 252869503U, // VMULD |
2370 | 1.35M | 253000575U, // VMULH |
2371 | 1.35M | 185246384U, // VMULLp64 |
2372 | 1.35M | 6585174U, // VMULLp8 |
2373 | 1.35M | 186669910U, // VMULLslsv2i32 |
2374 | 1.35M | 186800982U, // VMULLslsv4i16 |
2375 | 1.35M | 187063126U, // VMULLsluv2i32 |
2376 | 1.35M | 187194198U, // VMULLsluv4i16 |
2377 | 1.35M | 186678102U, // VMULLsv2i64 |
2378 | 1.35M | 186809174U, // VMULLsv4i32 |
2379 | 1.35M | 186940246U, // VMULLsv8i16 |
2380 | 1.35M | 187071318U, // VMULLuv2i64 |
2381 | 1.35M | 187202390U, // VMULLuv4i32 |
2382 | 1.35M | 187333462U, // VMULLuv8i16 |
2383 | 1.35M | 253131647U, // VMULS |
2384 | 1.35M | 253131647U, // VMULfd |
2385 | 1.35M | 253131647U, // VMULfq |
2386 | 1.35M | 253000575U, // VMULhd |
2387 | 1.35M | 253000575U, // VMULhq |
2388 | 1.35M | 6585215U, // VMULpd |
2389 | 1.35M | 6585215U, // VMULpq |
2390 | 1.35M | 253123455U, // VMULslfd |
2391 | 1.35M | 253123455U, // VMULslfq |
2392 | 1.35M | 252992383U, // VMULslhd |
2393 | 1.35M | 252992383U, // VMULslhq |
2394 | 1.35M | 187587455U, // VMULslv2i32 |
2395 | 1.35M | 187718527U, // VMULslv4i16 |
2396 | 1.35M | 187587455U, // VMULslv4i32 |
2397 | 1.35M | 187718527U, // VMULslv8i16 |
2398 | 1.35M | 187857791U, // VMULv16i8 |
2399 | 1.35M | 187595647U, // VMULv2i32 |
2400 | 1.35M | 187726719U, // VMULv4i16 |
2401 | 1.35M | 187595647U, // VMULv4i32 |
2402 | 1.35M | 187726719U, // VMULv8i16 |
2403 | 1.35M | 187857791U, // VMULv8i8 |
2404 | 1.35M | 539650U, // VMVNd |
2405 | 1.35M | 539650U, // VMVNq |
2406 | 1.35M | 405683202U, // VMVNv2i32 |
2407 | 1.35M | 405814274U, // VMVNv4i16 |
2408 | 1.35M | 405683202U, // VMVNv4i32 |
2409 | 1.35M | 405814274U, // VMVNv8i16 |
2410 | 1.35M | 252852757U, // VNEGD |
2411 | 1.35M | 252983829U, // VNEGH |
2412 | 1.35M | 253114901U, // VNEGS |
2413 | 1.35M | 253114901U, // VNEGf32q |
2414 | 1.35M | 253114901U, // VNEGfd |
2415 | 1.35M | 252983829U, // VNEGhd |
2416 | 1.35M | 252983829U, // VNEGhq |
2417 | 1.35M | 1260534293U, // VNEGs16d |
2418 | 1.35M | 1260534293U, // VNEGs16q |
2419 | 1.35M | 1260403221U, // VNEGs32d |
2420 | 1.35M | 1260403221U, // VNEGs32q |
2421 | 1.35M | 1260665365U, // VNEGs8d |
2422 | 1.35M | 1260665365U, // VNEGs8q |
2423 | 1.35M | 2400344104U, // VNMLAD |
2424 | 1.35M | 2400475176U, // VNMLAH |
2425 | 1.35M | 2400606248U, // VNMLAS |
2426 | 1.35M | 2400345273U, // VNMLSD |
2427 | 1.35M | 2400476345U, // VNMLSH |
2428 | 1.35M | 2400607417U, // VNMLSS |
2429 | 1.35M | 252869497U, // VNMULD |
2430 | 1.35M | 253000569U, // VNMULH |
2431 | 1.35M | 253131641U, // VNMULS |
2432 | 1.35M | 555999U, // VORNd |
2433 | 1.35M | 555999U, // VORNq |
2434 | 1.35M | 556151U, // VORRd |
2435 | 1.35M | 405699703U, // VORRiv2i32 |
2436 | 1.35M | 405830775U, // VORRiv4i16 |
2437 | 1.35M | 405699703U, // VORRiv4i32 |
2438 | 1.35M | 405830775U, // VORRiv8i16 |
2439 | 1.35M | 556151U, // VORRq |
2440 | 1.35M | 1243904713U, // VPADALsv16i8 |
2441 | 1.35M | 1243642569U, // VPADALsv2i32 |
2442 | 1.35M | 1243773641U, // VPADALsv4i16 |
2443 | 1.35M | 1243642569U, // VPADALsv4i32 |
2444 | 1.35M | 1243773641U, // VPADALsv8i16 |
2445 | 1.35M | 1243904713U, // VPADALsv8i8 |
2446 | 1.35M | 1244297929U, // VPADALuv16i8 |
2447 | 1.35M | 1244035785U, // VPADALuv2i32 |
2448 | 1.35M | 1244166857U, // VPADALuv4i16 |
2449 | 1.35M | 1244035785U, // VPADALuv4i32 |
2450 | 1.35M | 1244166857U, // VPADALuv8i16 |
2451 | 1.35M | 1244297929U, // VPADALuv8i8 |
2452 | 1.35M | 1260665605U, // VPADDLsv16i8 |
2453 | 1.35M | 1260403461U, // VPADDLsv2i32 |
2454 | 1.35M | 1260534533U, // VPADDLsv4i16 |
2455 | 1.35M | 1260403461U, // VPADDLsv4i32 |
2456 | 1.35M | 1260534533U, // VPADDLsv8i16 |
2457 | 1.35M | 1260665605U, // VPADDLsv8i8 |
2458 | 1.35M | 1261058821U, // VPADDLuv16i8 |
2459 | 1.35M | 1260796677U, // VPADDLuv2i32 |
2460 | 1.35M | 1260927749U, // VPADDLuv4i16 |
2461 | 1.35M | 1260796677U, // VPADDLuv4i32 |
2462 | 1.35M | 1260927749U, // VPADDLuv8i16 |
2463 | 1.35M | 1261058821U, // VPADDLuv8i8 |
2464 | 1.35M | 253131143U, // VPADDf |
2465 | 1.35M | 253000071U, // VPADDh |
2466 | 1.35M | 187726215U, // VPADDi16 |
2467 | 1.35M | 187595143U, // VPADDi32 |
2468 | 1.35M | 187857287U, // VPADDi8 |
2469 | 1.35M | 253132308U, // VPMAXf |
2470 | 1.35M | 253001236U, // VPMAXh |
2471 | 1.35M | 186809876U, // VPMAXs16 |
2472 | 1.35M | 186678804U, // VPMAXs32 |
2473 | 1.35M | 186940948U, // VPMAXs8 |
2474 | 1.35M | 187203092U, // VPMAXu16 |
2475 | 1.35M | 187072020U, // VPMAXu32 |
2476 | 1.35M | 187334164U, // VPMAXu8 |
2477 | 1.35M | 253131700U, // VPMINf |
2478 | 1.35M | 253000628U, // VPMINh |
2479 | 1.35M | 186809268U, // VPMINs16 |
2480 | 1.35M | 186678196U, // VPMINs32 |
2481 | 1.35M | 186940340U, // VPMINs8 |
2482 | 1.35M | 187202484U, // VPMINu16 |
2483 | 1.35M | 187071412U, // VPMINu32 |
2484 | 1.35M | 187333556U, // VPMINu8 |
2485 | 1.35M | 1260666014U, // VQABSv16i8 |
2486 | 1.35M | 1260403870U, // VQABSv2i32 |
2487 | 1.35M | 1260534942U, // VQABSv4i16 |
2488 | 1.35M | 1260403870U, // VQABSv4i32 |
2489 | 1.35M | 1260534942U, // VQABSv8i16 |
2490 | 1.35M | 1260666014U, // VQABSv8i8 |
2491 | 1.35M | 186939789U, // VQADDsv16i8 |
2492 | 1.35M | 191265165U, // VQADDsv1i64 |
2493 | 1.35M | 186677645U, // VQADDsv2i32 |
2494 | 1.35M | 191265165U, // VQADDsv2i64 |
2495 | 1.35M | 186808717U, // VQADDsv4i16 |
2496 | 1.35M | 186677645U, // VQADDsv4i32 |
2497 | 1.35M | 186808717U, // VQADDsv8i16 |
2498 | 1.35M | 186939789U, // VQADDsv8i8 |
2499 | 1.35M | 187333005U, // VQADDuv16i8 |
2500 | 1.35M | 191396237U, // VQADDuv1i64 |
2501 | 1.35M | 187070861U, // VQADDuv2i32 |
2502 | 1.35M | 191396237U, // VQADDuv2i64 |
2503 | 1.35M | 187201933U, // VQADDuv4i16 |
2504 | 1.35M | 187070861U, // VQADDuv4i32 |
2505 | 1.35M | 187201933U, // VQADDuv8i16 |
2506 | 1.35M | 187333005U, // VQADDuv8i8 |
2507 | 1.35M | 169896656U, // VQDMLALslv2i32 |
2508 | 1.35M | 170027728U, // VQDMLALslv4i16 |
2509 | 1.35M | 169892560U, // VQDMLALv2i64 |
2510 | 1.35M | 170023632U, // VQDMLALv4i32 |
2511 | 1.35M | 169896801U, // VQDMLSLslv2i32 |
2512 | 1.35M | 170027873U, // VQDMLSLslv4i16 |
2513 | 1.35M | 169892705U, // VQDMLSLv2i64 |
2514 | 1.35M | 170023777U, // VQDMLSLv4i32 |
2515 | 1.35M | 186669632U, // VQDMULHslv2i32 |
2516 | 1.35M | 186800704U, // VQDMULHslv4i16 |
2517 | 1.35M | 186669632U, // VQDMULHslv4i32 |
2518 | 1.35M | 186800704U, // VQDMULHslv8i16 |
2519 | 1.35M | 186677824U, // VQDMULHv2i32 |
2520 | 1.35M | 186808896U, // VQDMULHv4i16 |
2521 | 1.35M | 186677824U, // VQDMULHv4i32 |
2522 | 1.35M | 186808896U, // VQDMULHv8i16 |
2523 | 1.35M | 186669890U, // VQDMULLslv2i32 |
2524 | 1.35M | 186800962U, // VQDMULLslv4i16 |
2525 | 1.35M | 186678082U, // VQDMULLv2i64 |
2526 | 1.35M | 186809154U, // VQDMULLv4i32 |
2527 | 1.35M | 1264991226U, // VQMOVNsuv2i32 |
2528 | 1.35M | 1260403706U, // VQMOVNsuv4i16 |
2529 | 1.35M | 1260534778U, // VQMOVNsuv8i8 |
2530 | 1.35M | 1264991239U, // VQMOVNsv2i32 |
2531 | 1.35M | 1260403719U, // VQMOVNsv4i16 |
2532 | 1.35M | 1260534791U, // VQMOVNsv8i8 |
2533 | 1.35M | 1265122311U, // VQMOVNuv2i32 |
2534 | 1.35M | 1260796935U, // VQMOVNuv4i16 |
2535 | 1.35M | 1260928007U, // VQMOVNuv8i8 |
2536 | 1.35M | 1260665359U, // VQNEGv16i8 |
2537 | 1.35M | 1260403215U, // VQNEGv2i32 |
2538 | 1.35M | 1260534287U, // VQNEGv4i16 |
2539 | 1.35M | 1260403215U, // VQNEGv4i32 |
2540 | 1.35M | 1260534287U, // VQNEGv8i16 |
2541 | 1.35M | 1260665359U, // VQNEGv8i8 |
2542 | 1.35M | 169896482U, // VQRDMLAHslv2i32 |
2543 | 1.35M | 170027554U, // VQRDMLAHslv4i16 |
2544 | 1.35M | 169896482U, // VQRDMLAHslv4i32 |
2545 | 1.35M | 170027554U, // VQRDMLAHslv8i16 |
2546 | 1.35M | 169892386U, // VQRDMLAHv2i32 |
2547 | 1.35M | 170023458U, // VQRDMLAHv4i16 |
2548 | 1.35M | 169892386U, // VQRDMLAHv4i32 |
2549 | 1.35M | 170023458U, // VQRDMLAHv8i16 |
2550 | 1.35M | 169896539U, // VQRDMLSHslv2i32 |
2551 | 1.35M | 170027611U, // VQRDMLSHslv4i16 |
2552 | 1.35M | 169896539U, // VQRDMLSHslv4i32 |
2553 | 1.35M | 170027611U, // VQRDMLSHslv8i16 |
2554 | 1.35M | 169892443U, // VQRDMLSHv2i32 |
2555 | 1.35M | 170023515U, // VQRDMLSHv4i16 |
2556 | 1.35M | 169892443U, // VQRDMLSHv4i32 |
2557 | 1.35M | 170023515U, // VQRDMLSHv8i16 |
2558 | 1.35M | 186669640U, // VQRDMULHslv2i32 |
2559 | 1.35M | 186800712U, // VQRDMULHslv4i16 |
2560 | 1.35M | 186669640U, // VQRDMULHslv4i32 |
2561 | 1.35M | 186800712U, // VQRDMULHslv8i16 |
2562 | 1.35M | 186677832U, // VQRDMULHv2i32 |
2563 | 1.35M | 186808904U, // VQRDMULHv4i16 |
2564 | 1.35M | 186677832U, // VQRDMULHv4i32 |
2565 | 1.35M | 186808904U, // VQRDMULHv8i16 |
2566 | 1.35M | 186940188U, // VQRSHLsv16i8 |
2567 | 1.35M | 191265564U, // VQRSHLsv1i64 |
2568 | 1.35M | 186678044U, // VQRSHLsv2i32 |
2569 | 1.35M | 191265564U, // VQRSHLsv2i64 |
2570 | 1.35M | 186809116U, // VQRSHLsv4i16 |
2571 | 1.35M | 186678044U, // VQRSHLsv4i32 |
2572 | 1.35M | 186809116U, // VQRSHLsv8i16 |
2573 | 1.35M | 186940188U, // VQRSHLsv8i8 |
2574 | 1.35M | 187333404U, // VQRSHLuv16i8 |
2575 | 1.35M | 191396636U, // VQRSHLuv1i64 |
2576 | 1.35M | 187071260U, // VQRSHLuv2i32 |
2577 | 1.35M | 191396636U, // VQRSHLuv2i64 |
2578 | 1.35M | 187202332U, // VQRSHLuv4i16 |
2579 | 1.35M | 187071260U, // VQRSHLuv4i32 |
2580 | 1.35M | 187202332U, // VQRSHLuv8i16 |
2581 | 1.35M | 187333404U, // VQRSHLuv8i8 |
2582 | 1.35M | 191265738U, // VQRSHRNsv2i32 |
2583 | 1.35M | 186678218U, // VQRSHRNsv4i16 |
2584 | 1.35M | 186809290U, // VQRSHRNsv8i8 |
2585 | 1.35M | 191396810U, // VQRSHRNuv2i32 |
2586 | 1.35M | 187071434U, // VQRSHRNuv4i16 |
2587 | 1.35M | 187202506U, // VQRSHRNuv8i8 |
2588 | 1.35M | 191265777U, // VQRSHRUNv2i32 |
2589 | 1.35M | 186678257U, // VQRSHRUNv4i16 |
2590 | 1.35M | 186809329U, // VQRSHRUNv8i8 |
2591 | 1.35M | 186940182U, // VQSHLsiv16i8 |
2592 | 1.35M | 191265558U, // VQSHLsiv1i64 |
2593 | 1.35M | 186678038U, // VQSHLsiv2i32 |
2594 | 1.35M | 191265558U, // VQSHLsiv2i64 |
2595 | 1.35M | 186809110U, // VQSHLsiv4i16 |
2596 | 1.35M | 186678038U, // VQSHLsiv4i32 |
2597 | 1.35M | 186809110U, // VQSHLsiv8i16 |
2598 | 1.35M | 186940182U, // VQSHLsiv8i8 |
2599 | 1.35M | 186940879U, // VQSHLsuv16i8 |
2600 | 1.35M | 191266255U, // VQSHLsuv1i64 |
2601 | 1.35M | 186678735U, // VQSHLsuv2i32 |
2602 | 1.35M | 191266255U, // VQSHLsuv2i64 |
2603 | 1.35M | 186809807U, // VQSHLsuv4i16 |
2604 | 1.35M | 186678735U, // VQSHLsuv4i32 |
2605 | 1.35M | 186809807U, // VQSHLsuv8i16 |
2606 | 1.35M | 186940879U, // VQSHLsuv8i8 |
2607 | 1.35M | 186940182U, // VQSHLsv16i8 |
2608 | 1.35M | 191265558U, // VQSHLsv1i64 |
2609 | 1.35M | 186678038U, // VQSHLsv2i32 |
2610 | 1.35M | 191265558U, // VQSHLsv2i64 |
2611 | 1.35M | 186809110U, // VQSHLsv4i16 |
2612 | 1.35M | 186678038U, // VQSHLsv4i32 |
2613 | 1.35M | 186809110U, // VQSHLsv8i16 |
2614 | 1.35M | 186940182U, // VQSHLsv8i8 |
2615 | 1.35M | 187333398U, // VQSHLuiv16i8 |
2616 | 1.35M | 191396630U, // VQSHLuiv1i64 |
2617 | 1.35M | 187071254U, // VQSHLuiv2i32 |
2618 | 1.35M | 191396630U, // VQSHLuiv2i64 |
2619 | 1.35M | 187202326U, // VQSHLuiv4i16 |
2620 | 1.35M | 187071254U, // VQSHLuiv4i32 |
2621 | 1.35M | 187202326U, // VQSHLuiv8i16 |
2622 | 1.35M | 187333398U, // VQSHLuiv8i8 |
2623 | 1.35M | 187333398U, // VQSHLuv16i8 |
2624 | 1.35M | 191396630U, // VQSHLuv1i64 |
2625 | 1.35M | 187071254U, // VQSHLuv2i32 |
2626 | 1.35M | 191396630U, // VQSHLuv2i64 |
2627 | 1.35M | 187202326U, // VQSHLuv4i16 |
2628 | 1.35M | 187071254U, // VQSHLuv4i32 |
2629 | 1.35M | 187202326U, // VQSHLuv8i16 |
2630 | 1.35M | 187333398U, // VQSHLuv8i8 |
2631 | 1.35M | 191265731U, // VQSHRNsv2i32 |
2632 | 1.35M | 186678211U, // VQSHRNsv4i16 |
2633 | 1.35M | 186809283U, // VQSHRNsv8i8 |
2634 | 1.35M | 191396803U, // VQSHRNuv2i32 |
2635 | 1.35M | 187071427U, // VQSHRNuv4i16 |
2636 | 1.35M | 187202499U, // VQSHRNuv8i8 |
2637 | 1.35M | 191265769U, // VQSHRUNv2i32 |
2638 | 1.35M | 186678249U, // VQSHRUNv4i16 |
2639 | 1.35M | 186809321U, // VQSHRUNv8i8 |
2640 | 1.35M | 186939648U, // VQSUBsv16i8 |
2641 | 1.35M | 191265024U, // VQSUBsv1i64 |
2642 | 1.35M | 186677504U, // VQSUBsv2i32 |
2643 | 1.35M | 191265024U, // VQSUBsv2i64 |
2644 | 1.35M | 186808576U, // VQSUBsv4i16 |
2645 | 1.35M | 186677504U, // VQSUBsv4i32 |
2646 | 1.35M | 186808576U, // VQSUBsv8i16 |
2647 | 1.35M | 186939648U, // VQSUBsv8i8 |
2648 | 1.35M | 187332864U, // VQSUBuv16i8 |
2649 | 1.35M | 191396096U, // VQSUBuv1i64 |
2650 | 1.35M | 187070720U, // VQSUBuv2i32 |
2651 | 1.35M | 191396096U, // VQSUBuv2i64 |
2652 | 1.35M | 187201792U, // VQSUBuv4i16 |
2653 | 1.35M | 187070720U, // VQSUBuv4i32 |
2654 | 1.35M | 187201792U, // VQSUBuv8i16 |
2655 | 1.35M | 187332864U, // VQSUBuv8i8 |
2656 | 1.35M | 187464613U, // VRADDHNv2i32 |
2657 | 1.35M | 187595685U, // VRADDHNv4i16 |
2658 | 1.35M | 187726757U, // VRADDHNv8i8 |
2659 | 1.35M | 1260796401U, // VRECPEd |
2660 | 1.35M | 253114865U, // VRECPEfd |
2661 | 1.35M | 253114865U, // VRECPEfq |
2662 | 1.35M | 252983793U, // VRECPEhd |
2663 | 1.35M | 252983793U, // VRECPEhq |
2664 | 1.35M | 1260796401U, // VRECPEq |
2665 | 1.35M | 253131994U, // VRECPSfd |
2666 | 1.35M | 253131994U, // VRECPSfq |
2667 | 1.35M | 253000922U, // VRECPShd |
2668 | 1.35M | 253000922U, // VRECPShq |
2669 | 1.35M | 407379U, // VREV16d8 |
2670 | 1.35M | 407379U, // VREV16q8 |
2671 | 1.35M | 145022U, // VREV32d16 |
2672 | 1.35M | 407166U, // VREV32d8 |
2673 | 1.35M | 145022U, // VREV32q16 |
2674 | 1.35M | 407166U, // VREV32q8 |
2675 | 1.35M | 145098U, // VREV64d16 |
2676 | 1.35M | 276170U, // VREV64d32 |
2677 | 1.35M | 407242U, // VREV64d8 |
2678 | 1.35M | 145098U, // VREV64q16 |
2679 | 1.35M | 276170U, // VREV64q32 |
2680 | 1.35M | 407242U, // VREV64q8 |
2681 | 1.35M | 186939770U, // VRHADDsv16i8 |
2682 | 1.35M | 186677626U, // VRHADDsv2i32 |
2683 | 1.35M | 186808698U, // VRHADDsv4i16 |
2684 | 1.35M | 186677626U, // VRHADDsv4i32 |
2685 | 1.35M | 186808698U, // VRHADDsv8i16 |
2686 | 1.35M | 186939770U, // VRHADDsv8i8 |
2687 | 1.35M | 187332986U, // VRHADDuv16i8 |
2688 | 1.35M | 187070842U, // VRHADDuv2i32 |
2689 | 1.35M | 187201914U, // VRHADDuv4i16 |
2690 | 1.35M | 187070842U, // VRHADDuv4i32 |
2691 | 1.35M | 187201914U, // VRHADDuv8i16 |
2692 | 1.35M | 187332986U, // VRHADDuv8i8 |
2693 | 1.35M | 1258988088U, // VRINTAD |
2694 | 1.35M | 1258988470U, // VRINTAH |
2695 | 1.35M | 1258987769U, // VRINTANDf |
2696 | 1.35M | 1258988470U, // VRINTANDh |
2697 | 1.35M | 1258987769U, // VRINTANQf |
2698 | 1.35M | 1258988470U, // VRINTANQh |
2699 | 1.35M | 1258987769U, // VRINTAS |
2700 | 1.35M | 1258988136U, // VRINTMD |
2701 | 1.35M | 1258988529U, // VRINTMH |
2702 | 1.35M | 1258987828U, // VRINTMNDf |
2703 | 1.35M | 1258988529U, // VRINTMNDh |
2704 | 1.35M | 1258987828U, // VRINTMNQf |
2705 | 1.35M | 1258988529U, // VRINTMNQh |
2706 | 1.35M | 1258987828U, // VRINTMS |
2707 | 1.35M | 1258988148U, // VRINTND |
2708 | 1.35M | 1258988541U, // VRINTNH |
2709 | 1.35M | 1258987840U, // VRINTNNDf |
2710 | 1.35M | 1258988541U, // VRINTNNDh |
2711 | 1.35M | 1258987840U, // VRINTNNQf |
2712 | 1.35M | 1258988541U, // VRINTNNQh |
2713 | 1.35M | 1258987840U, // VRINTNS |
2714 | 1.35M | 1258988160U, // VRINTPD |
2715 | 1.35M | 1258988553U, // VRINTPH |
2716 | 1.35M | 1258987852U, // VRINTPNDf |
2717 | 1.35M | 1258988553U, // VRINTPNDh |
2718 | 1.35M | 1258987852U, // VRINTPNQf |
2719 | 1.35M | 1258988553U, // VRINTPNQh |
2720 | 1.35M | 1258987852U, // VRINTPS |
2721 | 1.35M | 252853388U, // VRINTRD |
2722 | 1.35M | 252984460U, // VRINTRH |
2723 | 1.35M | 253115532U, // VRINTRS |
2724 | 1.35M | 252853960U, // VRINTXD |
2725 | 1.35M | 252985032U, // VRINTXH |
2726 | 1.35M | 1258987900U, // VRINTXNDf |
2727 | 1.35M | 1258988611U, // VRINTXNDh |
2728 | 1.35M | 1258987900U, // VRINTXNQf |
2729 | 1.35M | 1258988611U, // VRINTXNQh |
2730 | 1.35M | 253116104U, // VRINTXS |
2731 | 1.35M | 252853972U, // VRINTZD |
2732 | 1.35M | 252985044U, // VRINTZH |
2733 | 1.35M | 1258987912U, // VRINTZNDf |
2734 | 1.35M | 1258988634U, // VRINTZNDh |
2735 | 1.35M | 1258987912U, // VRINTZNQf |
2736 | 1.35M | 1258988634U, // VRINTZNQh |
2737 | 1.35M | 253116116U, // VRINTZS |
2738 | 1.35M | 186940195U, // VRSHLsv16i8 |
2739 | 1.35M | 191265571U, // VRSHLsv1i64 |
2740 | 1.35M | 186678051U, // VRSHLsv2i32 |
2741 | 1.35M | 191265571U, // VRSHLsv2i64 |
2742 | 1.35M | 186809123U, // VRSHLsv4i16 |
2743 | 1.35M | 186678051U, // VRSHLsv4i32 |
2744 | 1.35M | 186809123U, // VRSHLsv8i16 |
2745 | 1.35M | 186940195U, // VRSHLsv8i8 |
2746 | 1.35M | 187333411U, // VRSHLuv16i8 |
2747 | 1.35M | 191396643U, // VRSHLuv1i64 |
2748 | 1.35M | 187071267U, // VRSHLuv2i32 |
2749 | 1.35M | 191396643U, // VRSHLuv2i64 |
2750 | 1.35M | 187202339U, // VRSHLuv4i16 |
2751 | 1.35M | 187071267U, // VRSHLuv4i32 |
2752 | 1.35M | 187202339U, // VRSHLuv8i16 |
2753 | 1.35M | 187333411U, // VRSHLuv8i8 |
2754 | 1.35M | 187464658U, // VRSHRNv2i32 |
2755 | 1.35M | 187595730U, // VRSHRNv4i16 |
2756 | 1.35M | 187726802U, // VRSHRNv8i8 |
2757 | 1.35M | 186940503U, // VRSHRsv16i8 |
2758 | 1.35M | 191265879U, // VRSHRsv1i64 |
2759 | 1.35M | 186678359U, // VRSHRsv2i32 |
2760 | 1.35M | 191265879U, // VRSHRsv2i64 |
2761 | 1.35M | 186809431U, // VRSHRsv4i16 |
2762 | 1.35M | 186678359U, // VRSHRsv4i32 |
2763 | 1.35M | 186809431U, // VRSHRsv8i16 |
2764 | 1.35M | 186940503U, // VRSHRsv8i8 |
2765 | 1.35M | 187333719U, // VRSHRuv16i8 |
2766 | 1.35M | 191396951U, // VRSHRuv1i64 |
2767 | 1.35M | 187071575U, // VRSHRuv2i32 |
2768 | 1.35M | 191396951U, // VRSHRuv2i64 |
2769 | 1.35M | 187202647U, // VRSHRuv4i16 |
2770 | 1.35M | 187071575U, // VRSHRuv4i32 |
2771 | 1.35M | 187202647U, // VRSHRuv8i16 |
2772 | 1.35M | 187333719U, // VRSHRuv8i8 |
2773 | 1.35M | 1260796414U, // VRSQRTEd |
2774 | 1.35M | 253114878U, // VRSQRTEfd |
2775 | 1.35M | 253114878U, // VRSQRTEfq |
2776 | 1.35M | 252983806U, // VRSQRTEhd |
2777 | 1.35M | 252983806U, // VRSQRTEhq |
2778 | 1.35M | 1260796414U, // VRSQRTEq |
2779 | 1.35M | 253132016U, // VRSQRTSfd |
2780 | 1.35M | 253132016U, // VRSQRTSfq |
2781 | 1.35M | 253000944U, // VRSQRTShd |
2782 | 1.35M | 253000944U, // VRSQRTShq |
2783 | 1.35M | 170154046U, // VRSRAsv16i8 |
2784 | 1.35M | 174479422U, // VRSRAsv1i64 |
2785 | 1.35M | 169891902U, // VRSRAsv2i32 |
2786 | 1.35M | 174479422U, // VRSRAsv2i64 |
2787 | 1.35M | 170022974U, // VRSRAsv4i16 |
2788 | 1.35M | 169891902U, // VRSRAsv4i32 |
2789 | 1.35M | 170022974U, // VRSRAsv8i16 |
2790 | 1.35M | 170154046U, // VRSRAsv8i8 |
2791 | 1.35M | 170547262U, // VRSRAuv16i8 |
2792 | 1.35M | 174610494U, // VRSRAuv1i64 |
2793 | 1.35M | 170285118U, // VRSRAuv2i32 |
2794 | 1.35M | 174610494U, // VRSRAuv2i64 |
2795 | 1.35M | 170416190U, // VRSRAuv4i16 |
2796 | 1.35M | 170285118U, // VRSRAuv4i32 |
2797 | 1.35M | 170416190U, // VRSRAuv8i16 |
2798 | 1.35M | 170547262U, // VRSRAuv8i8 |
2799 | 1.35M | 187464598U, // VRSUBHNv2i32 |
2800 | 1.35M | 187595670U, // VRSUBHNv4i16 |
2801 | 1.35M | 187726742U, // VRSUBHNv8i8 |
2802 | 1.35M | 910473U, // VSDOTD |
2803 | 1.35M | 7070857U, // VSDOTDI |
2804 | 1.35M | 910473U, // VSDOTQ |
2805 | 1.35M | 7070857U, // VSDOTQI |
2806 | 1.35M | 185246348U, // VSELEQD |
2807 | 1.35M | 185246741U, // VSELEQH |
2808 | 1.35M | 185246040U, // VSELEQS |
2809 | 1.35M | 185246276U, // VSELGED |
2810 | 1.35M | 185246669U, // VSELGEH |
2811 | 1.35M | 185245968U, // VSELGES |
2812 | 1.35M | 185246372U, // VSELGTD |
2813 | 1.35M | 185246775U, // VSELGTH |
2814 | 1.35M | 185246064U, // VSELGTS |
2815 | 1.35M | 185246360U, // VSELVSD |
2816 | 1.35M | 185246763U, // VSELVSH |
2817 | 1.35M | 185246052U, // VSELVSS |
2818 | 1.35M | 3221380585U, // VSETLNi16 |
2819 | 1.35M | 3221511657U, // VSETLNi32 |
2820 | 1.35M | 3221642729U, // VSETLNi8 |
2821 | 1.35M | 187726652U, // VSHLLi16 |
2822 | 1.35M | 187595580U, // VSHLLi32 |
2823 | 1.35M | 187857724U, // VSHLLi8 |
2824 | 1.35M | 186678076U, // VSHLLsv2i64 |
2825 | 1.35M | 186809148U, // VSHLLsv4i32 |
2826 | 1.35M | 186940220U, // VSHLLsv8i16 |
2827 | 1.35M | 187071292U, // VSHLLuv2i64 |
2828 | 1.35M | 187202364U, // VSHLLuv4i32 |
2829 | 1.35M | 187333436U, // VSHLLuv8i16 |
2830 | 1.35M | 187857705U, // VSHLiv16i8 |
2831 | 1.35M | 187464489U, // VSHLiv1i64 |
2832 | 1.35M | 187595561U, // VSHLiv2i32 |
2833 | 1.35M | 187464489U, // VSHLiv2i64 |
2834 | 1.35M | 187726633U, // VSHLiv4i16 |
2835 | 1.35M | 187595561U, // VSHLiv4i32 |
2836 | 1.35M | 187726633U, // VSHLiv8i16 |
2837 | 1.35M | 187857705U, // VSHLiv8i8 |
2838 | 1.35M | 186940201U, // VSHLsv16i8 |
2839 | 1.35M | 191265577U, // VSHLsv1i64 |
2840 | 1.35M | 186678057U, // VSHLsv2i32 |
2841 | 1.35M | 191265577U, // VSHLsv2i64 |
2842 | 1.35M | 186809129U, // VSHLsv4i16 |
2843 | 1.35M | 186678057U, // VSHLsv4i32 |
2844 | 1.35M | 186809129U, // VSHLsv8i16 |
2845 | 1.35M | 186940201U, // VSHLsv8i8 |
2846 | 1.35M | 187333417U, // VSHLuv16i8 |
2847 | 1.35M | 191396649U, // VSHLuv1i64 |
2848 | 1.35M | 187071273U, // VSHLuv2i32 |
2849 | 1.35M | 191396649U, // VSHLuv2i64 |
2850 | 1.35M | 187202345U, // VSHLuv4i16 |
2851 | 1.35M | 187071273U, // VSHLuv4i32 |
2852 | 1.35M | 187202345U, // VSHLuv8i16 |
2853 | 1.35M | 187333417U, // VSHLuv8i8 |
2854 | 1.35M | 187464665U, // VSHRNv2i32 |
2855 | 1.35M | 187595737U, // VSHRNv4i16 |
2856 | 1.35M | 187726809U, // VSHRNv8i8 |
2857 | 1.35M | 186940509U, // VSHRsv16i8 |
2858 | 1.35M | 191265885U, // VSHRsv1i64 |
2859 | 1.35M | 186678365U, // VSHRsv2i32 |
2860 | 1.35M | 191265885U, // VSHRsv2i64 |
2861 | 1.35M | 186809437U, // VSHRsv4i16 |
2862 | 1.35M | 186678365U, // VSHRsv4i32 |
2863 | 1.35M | 186809437U, // VSHRsv8i16 |
2864 | 1.35M | 186940509U, // VSHRsv8i8 |
2865 | 1.35M | 187333725U, // VSHRuv16i8 |
2866 | 1.35M | 191396957U, // VSHRuv1i64 |
2867 | 1.35M | 187071581U, // VSHRuv2i32 |
2868 | 1.35M | 191396957U, // VSHRuv2i64 |
2869 | 1.35M | 187202653U, // VSHRuv4i16 |
2870 | 1.35M | 187071581U, // VSHRuv4i32 |
2871 | 1.35M | 187202653U, // VSHRuv8i16 |
2872 | 1.35M | 187333725U, // VSHRuv8i8 |
2873 | 1.35M | 7110066U, // VSHTOD |
2874 | 1.35M | 256540082U, // VSHTOH |
2875 | 1.35M | 7241138U, // VSHTOS |
2876 | 1.35M | 443563442U, // VSITOD |
2877 | 1.35M | 443694514U, // VSITOH |
2878 | 1.35M | 440942002U, // VSITOS |
2879 | 1.35M | 416419U, // VSLIv16i8 |
2880 | 1.35M | 5266083U, // VSLIv1i64 |
2881 | 1.35M | 285347U, // VSLIv2i32 |
2882 | 1.35M | 5266083U, // VSLIv2i64 |
2883 | 1.35M | 154275U, // VSLIv4i16 |
2884 | 1.35M | 285347U, // VSLIv4i32 |
2885 | 1.35M | 154275U, // VSLIv8i16 |
2886 | 1.35M | 416419U, // VSLIv8i8 |
2887 | 1.35M | 1332772274U, // VSLTOD |
2888 | 1.35M | 1332903346U, // VSLTOH |
2889 | 1.35M | 1330150834U, // VSLTOS |
2890 | 1.35M | 252853628U, // VSQRTD |
2891 | 1.35M | 252984700U, // VSQRTH |
2892 | 1.35M | 253115772U, // VSQRTS |
2893 | 1.35M | 170154052U, // VSRAsv16i8 |
2894 | 1.35M | 174479428U, // VSRAsv1i64 |
2895 | 1.35M | 169891908U, // VSRAsv2i32 |
2896 | 1.35M | 174479428U, // VSRAsv2i64 |
2897 | 1.35M | 170022980U, // VSRAsv4i16 |
2898 | 1.35M | 169891908U, // VSRAsv4i32 |
2899 | 1.35M | 170022980U, // VSRAsv8i16 |
2900 | 1.35M | 170154052U, // VSRAsv8i8 |
2901 | 1.35M | 170547268U, // VSRAuv16i8 |
2902 | 1.35M | 174610500U, // VSRAuv1i64 |
2903 | 1.35M | 170285124U, // VSRAuv2i32 |
2904 | 1.35M | 174610500U, // VSRAuv2i64 |
2905 | 1.35M | 170416196U, // VSRAuv4i16 |
2906 | 1.35M | 170285124U, // VSRAuv4i32 |
2907 | 1.35M | 170416196U, // VSRAuv8i16 |
2908 | 1.35M | 170547268U, // VSRAuv8i8 |
2909 | 1.35M | 416424U, // VSRIv16i8 |
2910 | 1.35M | 5266088U, // VSRIv1i64 |
2911 | 1.35M | 285352U, // VSRIv2i32 |
2912 | 1.35M | 5266088U, // VSRIv2i64 |
2913 | 1.35M | 154280U, // VSRIv4i16 |
2914 | 1.35M | 285352U, // VSRIv4i32 |
2915 | 1.35M | 154280U, // VSRIv8i16 |
2916 | 1.35M | 416424U, // VSRIv8i8 |
2917 | 1.35M | 1247041145U, // VST1LNd16 |
2918 | 1.35M | 1632949881U, // VST1LNd16_UPD |
2919 | 1.35M | 1247172217U, // VST1LNd32 |
2920 | 1.35M | 1633080953U, // VST1LNd32_UPD |
2921 | 1.35M | 1247303289U, // VST1LNd8 |
2922 | 1.35M | 1633212025U, // VST1LNd8_UPD |
2923 | 1.35M | 0U, // VST1LNq16Pseudo |
2924 | 1.35M | 0U, // VST1LNq16Pseudo_UPD |
2925 | 1.35M | 0U, // VST1LNq32Pseudo |
2926 | 1.35M | 0U, // VST1LNq32Pseudo_UPD |
2927 | 1.35M | 0U, // VST1LNq8Pseudo |
2928 | 1.35M | 0U, // VST1LNq8Pseudo_UPD |
2929 | 1.35M | 570586745U, // VST1d16 |
2930 | 1.35M | 587363961U, // VST1d16Q |
2931 | 1.35M | 0U, // VST1d16QPseudo |
2932 | 1.35M | 604132985U, // VST1d16Qwb_fixed |
2933 | 1.35M | 620914297U, // VST1d16Qwb_register |
2934 | 1.35M | 637695609U, // VST1d16T |
2935 | 1.35M | 0U, // VST1d16TPseudo |
2936 | 1.35M | 654464633U, // VST1d16Twb_fixed |
2937 | 1.35M | 671245945U, // VST1d16Twb_register |
2938 | 1.35M | 688019065U, // VST1d16wb_fixed |
2939 | 1.35M | 704800377U, // VST1d16wb_register |
2940 | 1.35M | 570717817U, // VST1d32 |
2941 | 1.35M | 587495033U, // VST1d32Q |
2942 | 1.35M | 0U, // VST1d32QPseudo |
2943 | 1.35M | 604264057U, // VST1d32Qwb_fixed |
2944 | 1.35M | 621045369U, // VST1d32Qwb_register |
2945 | 1.35M | 637826681U, // VST1d32T |
2946 | 1.35M | 0U, // VST1d32TPseudo |
2947 | 1.35M | 654595705U, // VST1d32Twb_fixed |
2948 | 1.35M | 671377017U, // VST1d32Twb_register |
2949 | 1.35M | 688150137U, // VST1d32wb_fixed |
2950 | 1.35M | 704931449U, // VST1d32wb_register |
2951 | 1.35M | 575698553U, // VST1d64 |
2952 | 1.35M | 592475769U, // VST1d64Q |
2953 | 1.35M | 0U, // VST1d64QPseudo |
2954 | 1.35M | 0U, // VST1d64QPseudoWB_fixed |
2955 | 1.35M | 0U, // VST1d64QPseudoWB_register |
2956 | 1.35M | 609244793U, // VST1d64Qwb_fixed |
2957 | 1.35M | 626026105U, // VST1d64Qwb_register |
2958 | 1.35M | 642807417U, // VST1d64T |
2959 | 1.35M | 0U, // VST1d64TPseudo |
2960 | 1.35M | 0U, // VST1d64TPseudoWB_fixed |
2961 | 1.35M | 0U, // VST1d64TPseudoWB_register |
2962 | 1.35M | 659576441U, // VST1d64Twb_fixed |
2963 | 1.35M | 676357753U, // VST1d64Twb_register |
2964 | 1.35M | 693130873U, // VST1d64wb_fixed |
2965 | 1.35M | 709912185U, // VST1d64wb_register |
2966 | 1.35M | 570848889U, // VST1d8 |
2967 | 1.35M | 587626105U, // VST1d8Q |
2968 | 1.35M | 0U, // VST1d8QPseudo |
2969 | 1.35M | 604395129U, // VST1d8Qwb_fixed |
2970 | 1.35M | 621176441U, // VST1d8Qwb_register |
2971 | 1.35M | 637957753U, // VST1d8T |
2972 | 1.35M | 0U, // VST1d8TPseudo |
2973 | 1.35M | 654726777U, // VST1d8Twb_fixed |
2974 | 1.35M | 671508089U, // VST1d8Twb_register |
2975 | 1.35M | 688281209U, // VST1d8wb_fixed |
2976 | 1.35M | 705062521U, // VST1d8wb_register |
2977 | 1.35M | 721581689U, // VST1q16 |
2978 | 1.35M | 0U, // VST1q16HighQPseudo |
2979 | 1.35M | 0U, // VST1q16HighTPseudo |
2980 | 1.35M | 0U, // VST1q16LowQPseudo_UPD |
2981 | 1.35M | 0U, // VST1q16LowTPseudo_UPD |
2982 | 1.35M | 738350713U, // VST1q16wb_fixed |
2983 | 1.35M | 755132025U, // VST1q16wb_register |
2984 | 1.35M | 721712761U, // VST1q32 |
2985 | 1.35M | 0U, // VST1q32HighQPseudo |
2986 | 1.35M | 0U, // VST1q32HighTPseudo |
2987 | 1.35M | 0U, // VST1q32LowQPseudo_UPD |
2988 | 1.35M | 0U, // VST1q32LowTPseudo_UPD |
2989 | 1.35M | 738481785U, // VST1q32wb_fixed |
2990 | 1.35M | 755263097U, // VST1q32wb_register |
2991 | 1.35M | 726693497U, // VST1q64 |
2992 | 1.35M | 0U, // VST1q64HighQPseudo |
2993 | 1.35M | 0U, // VST1q64HighTPseudo |
2994 | 1.35M | 0U, // VST1q64LowQPseudo_UPD |
2995 | 1.35M | 0U, // VST1q64LowTPseudo_UPD |
2996 | 1.35M | 743462521U, // VST1q64wb_fixed |
2997 | 1.35M | 760243833U, // VST1q64wb_register |
2998 | 1.35M | 721843833U, // VST1q8 |
2999 | 1.35M | 0U, // VST1q8HighQPseudo |
3000 | 1.35M | 0U, // VST1q8HighTPseudo |
3001 | 1.35M | 0U, // VST1q8LowQPseudo_UPD |
3002 | 1.35M | 0U, // VST1q8LowTPseudo_UPD |
3003 | 1.35M | 738612857U, // VST1q8wb_fixed |
3004 | 1.35M | 755394169U, // VST1q8wb_register |
3005 | 1.35M | 1247045301U, // VST2LNd16 |
3006 | 1.35M | 0U, // VST2LNd16Pseudo |
3007 | 1.35M | 0U, // VST2LNd16Pseudo_UPD |
3008 | 1.35M | 1632999093U, // VST2LNd16_UPD |
3009 | 1.35M | 1247176373U, // VST2LNd32 |
3010 | 1.35M | 0U, // VST2LNd32Pseudo |
3011 | 1.35M | 0U, // VST2LNd32Pseudo_UPD |
3012 | 1.35M | 1633130165U, // VST2LNd32_UPD |
3013 | 1.35M | 1247307445U, // VST2LNd8 |
3014 | 1.35M | 0U, // VST2LNd8Pseudo |
3015 | 1.35M | 0U, // VST2LNd8Pseudo_UPD |
3016 | 1.35M | 1633261237U, // VST2LNd8_UPD |
3017 | 1.35M | 1247045301U, // VST2LNq16 |
3018 | 1.35M | 0U, // VST2LNq16Pseudo |
3019 | 1.35M | 0U, // VST2LNq16Pseudo_UPD |
3020 | 1.35M | 1632999093U, // VST2LNq16_UPD |
3021 | 1.35M | 1247176373U, // VST2LNq32 |
3022 | 1.35M | 0U, // VST2LNq32Pseudo |
3023 | 1.35M | 0U, // VST2LNq32Pseudo_UPD |
3024 | 1.35M | 1633130165U, // VST2LNq32_UPD |
3025 | 1.35M | 771913397U, // VST2b16 |
3026 | 1.35M | 788682421U, // VST2b16wb_fixed |
3027 | 1.35M | 805463733U, // VST2b16wb_register |
3028 | 1.35M | 772044469U, // VST2b32 |
3029 | 1.35M | 788813493U, // VST2b32wb_fixed |
3030 | 1.35M | 805594805U, // VST2b32wb_register |
3031 | 1.35M | 772175541U, // VST2b8 |
3032 | 1.35M | 788944565U, // VST2b8wb_fixed |
3033 | 1.35M | 805725877U, // VST2b8wb_register |
3034 | 1.35M | 721581749U, // VST2d16 |
3035 | 1.35M | 738350773U, // VST2d16wb_fixed |
3036 | 1.35M | 755132085U, // VST2d16wb_register |
3037 | 1.35M | 721712821U, // VST2d32 |
3038 | 1.35M | 738481845U, // VST2d32wb_fixed |
3039 | 1.35M | 755263157U, // VST2d32wb_register |
3040 | 1.35M | 721843893U, // VST2d8 |
3041 | 1.35M | 738612917U, // VST2d8wb_fixed |
3042 | 1.35M | 755394229U, // VST2d8wb_register |
3043 | 1.35M | 587364021U, // VST2q16 |
3044 | 1.35M | 0U, // VST2q16Pseudo |
3045 | 1.35M | 0U, // VST2q16PseudoWB_fixed |
3046 | 1.35M | 0U, // VST2q16PseudoWB_register |
3047 | 1.35M | 604133045U, // VST2q16wb_fixed |
3048 | 1.35M | 620914357U, // VST2q16wb_register |
3049 | 1.35M | 587495093U, // VST2q32 |
3050 | 1.35M | 0U, // VST2q32Pseudo |
3051 | 1.35M | 0U, // VST2q32PseudoWB_fixed |
3052 | 1.35M | 0U, // VST2q32PseudoWB_register |
3053 | 1.35M | 604264117U, // VST2q32wb_fixed |
3054 | 1.35M | 621045429U, // VST2q32wb_register |
3055 | 1.35M | 587626165U, // VST2q8 |
3056 | 1.35M | 0U, // VST2q8Pseudo |
3057 | 1.35M | 0U, // VST2q8PseudoWB_fixed |
3058 | 1.35M | 0U, // VST2q8PseudoWB_register |
3059 | 1.35M | 604395189U, // VST2q8wb_fixed |
3060 | 1.35M | 621176501U, // VST2q8wb_register |
3061 | 1.35M | 1247073989U, // VST3LNd16 |
3062 | 1.35M | 0U, // VST3LNd16Pseudo |
3063 | 1.35M | 0U, // VST3LNd16Pseudo_UPD |
3064 | 1.35M | 1633011397U, // VST3LNd16_UPD |
3065 | 1.35M | 1247205061U, // VST3LNd32 |
3066 | 1.35M | 0U, // VST3LNd32Pseudo |
3067 | 1.35M | 0U, // VST3LNd32Pseudo_UPD |
3068 | 1.35M | 1633142469U, // VST3LNd32_UPD |
3069 | 1.35M | 1247336133U, // VST3LNd8 |
3070 | 1.35M | 0U, // VST3LNd8Pseudo |
3071 | 1.35M | 0U, // VST3LNd8Pseudo_UPD |
3072 | 1.35M | 1633273541U, // VST3LNd8_UPD |
3073 | 1.35M | 1247073989U, // VST3LNq16 |
3074 | 1.35M | 0U, // VST3LNq16Pseudo |
3075 | 1.35M | 0U, // VST3LNq16Pseudo_UPD |
3076 | 1.35M | 1633011397U, // VST3LNq16_UPD |
3077 | 1.35M | 1247205061U, // VST3LNq32 |
3078 | 1.35M | 0U, // VST3LNq32Pseudo |
3079 | 1.35M | 0U, // VST3LNq32Pseudo_UPD |
3080 | 1.35M | 1633142469U, // VST3LNq32_UPD |
3081 | 1.35M | 173303493U, // VST3d16 |
3082 | 1.35M | 0U, // VST3d16Pseudo |
3083 | 1.35M | 0U, // VST3d16Pseudo_UPD |
3084 | 1.35M | 559257285U, // VST3d16_UPD |
3085 | 1.35M | 173434565U, // VST3d32 |
3086 | 1.35M | 0U, // VST3d32Pseudo |
3087 | 1.35M | 0U, // VST3d32Pseudo_UPD |
3088 | 1.35M | 559388357U, // VST3d32_UPD |
3089 | 1.35M | 173565637U, // VST3d8 |
3090 | 1.35M | 0U, // VST3d8Pseudo |
3091 | 1.35M | 0U, // VST3d8Pseudo_UPD |
3092 | 1.35M | 559519429U, // VST3d8_UPD |
3093 | 1.35M | 173303493U, // VST3q16 |
3094 | 1.35M | 0U, // VST3q16Pseudo_UPD |
3095 | 1.35M | 559257285U, // VST3q16_UPD |
3096 | 1.35M | 0U, // VST3q16oddPseudo |
3097 | 1.35M | 0U, // VST3q16oddPseudo_UPD |
3098 | 1.35M | 173434565U, // VST3q32 |
3099 | 1.35M | 0U, // VST3q32Pseudo_UPD |
3100 | 1.35M | 559388357U, // VST3q32_UPD |
3101 | 1.35M | 0U, // VST3q32oddPseudo |
3102 | 1.35M | 0U, // VST3q32oddPseudo_UPD |
3103 | 1.35M | 173565637U, // VST3q8 |
3104 | 1.35M | 0U, // VST3q8Pseudo_UPD |
3105 | 1.35M | 559519429U, // VST3q8_UPD |
3106 | 1.35M | 0U, // VST3q8oddPseudo |
3107 | 1.35M | 0U, // VST3q8oddPseudo_UPD |
3108 | 1.35M | 1247123158U, // VST4LNd16 |
3109 | 1.35M | 0U, // VST4LNd16Pseudo |
3110 | 1.35M | 0U, // VST4LNd16Pseudo_UPD |
3111 | 1.35M | 1633003222U, // VST4LNd16_UPD |
3112 | 1.35M | 1247254230U, // VST4LNd32 |
3113 | 1.35M | 0U, // VST4LNd32Pseudo |
3114 | 1.35M | 0U, // VST4LNd32Pseudo_UPD |
3115 | 1.35M | 1633134294U, // VST4LNd32_UPD |
3116 | 1.35M | 1247385302U, // VST4LNd8 |
3117 | 1.35M | 0U, // VST4LNd8Pseudo |
3118 | 1.35M | 0U, // VST4LNd8Pseudo_UPD |
3119 | 1.35M | 1633265366U, // VST4LNd8_UPD |
3120 | 1.35M | 1247123158U, // VST4LNq16 |
3121 | 1.35M | 0U, // VST4LNq16Pseudo |
3122 | 1.35M | 0U, // VST4LNq16Pseudo_UPD |
3123 | 1.35M | 1633003222U, // VST4LNq16_UPD |
3124 | 1.35M | 1247254230U, // VST4LNq32 |
3125 | 1.35M | 0U, // VST4LNq32Pseudo |
3126 | 1.35M | 0U, // VST4LNq32Pseudo_UPD |
3127 | 1.35M | 1633134294U, // VST4LNq32_UPD |
3128 | 1.35M | 173332182U, // VST4d16 |
3129 | 1.35M | 0U, // VST4d16Pseudo |
3130 | 1.35M | 0U, // VST4d16Pseudo_UPD |
3131 | 1.35M | 559269590U, // VST4d16_UPD |
3132 | 1.35M | 173463254U, // VST4d32 |
3133 | 1.35M | 0U, // VST4d32Pseudo |
3134 | 1.35M | 0U, // VST4d32Pseudo_UPD |
3135 | 1.35M | 559400662U, // VST4d32_UPD |
3136 | 1.35M | 173594326U, // VST4d8 |
3137 | 1.35M | 0U, // VST4d8Pseudo |
3138 | 1.35M | 0U, // VST4d8Pseudo_UPD |
3139 | 1.35M | 559531734U, // VST4d8_UPD |
3140 | 1.35M | 173332182U, // VST4q16 |
3141 | 1.35M | 0U, // VST4q16Pseudo_UPD |
3142 | 1.35M | 559269590U, // VST4q16_UPD |
3143 | 1.35M | 0U, // VST4q16oddPseudo |
3144 | 1.35M | 0U, // VST4q16oddPseudo_UPD |
3145 | 1.35M | 173463254U, // VST4q32 |
3146 | 1.35M | 0U, // VST4q32Pseudo_UPD |
3147 | 1.35M | 559400662U, // VST4q32_UPD |
3148 | 1.35M | 0U, // VST4q32oddPseudo |
3149 | 1.35M | 0U, // VST4q32oddPseudo_UPD |
3150 | 1.35M | 173594326U, // VST4q8 |
3151 | 1.35M | 0U, // VST4q8Pseudo_UPD |
3152 | 1.35M | 559531734U, // VST4q8_UPD |
3153 | 1.35M | 0U, // VST4q8oddPseudo |
3154 | 1.35M | 0U, // VST4q8oddPseudo_UPD |
3155 | 1.35M | 2332571781U, // VSTMDDB_UPD |
3156 | 1.35M | 571413U, // VSTMDIA |
3157 | 1.35M | 2332571669U, // VSTMDIA_UPD |
3158 | 1.35M | 0U, // VSTMQIA |
3159 | 1.35M | 2332571781U, // VSTMSDB_UPD |
3160 | 1.35M | 571413U, // VSTMSIA |
3161 | 1.35M | 2332571669U, // VSTMSIA_UPD |
3162 | 1.35M | 556179U, // VSTRD |
3163 | 1.35M | 162963U, // VSTRH |
3164 | 1.35M | 556179U, // VSTRS |
3165 | 1.35M | 252868870U, // VSUBD |
3166 | 1.35M | 252999942U, // VSUBH |
3167 | 1.35M | 187464606U, // VSUBHNv2i32 |
3168 | 1.35M | 187595678U, // VSUBHNv4i16 |
3169 | 1.35M | 187726750U, // VSUBHNv8i8 |
3170 | 1.35M | 186677999U, // VSUBLsv2i64 |
3171 | 1.35M | 186809071U, // VSUBLsv4i32 |
3172 | 1.35M | 186940143U, // VSUBLsv8i16 |
3173 | 1.35M | 187071215U, // VSUBLuv2i64 |
3174 | 1.35M | 187202287U, // VSUBLuv4i32 |
3175 | 1.35M | 187333359U, // VSUBLuv8i16 |
3176 | 1.35M | 253131014U, // VSUBS |
3177 | 1.35M | 186678766U, // VSUBWsv2i64 |
3178 | 1.35M | 186809838U, // VSUBWsv4i32 |
3179 | 1.35M | 186940910U, // VSUBWsv8i16 |
3180 | 1.35M | 187071982U, // VSUBWuv2i64 |
3181 | 1.35M | 187203054U, // VSUBWuv4i32 |
3182 | 1.35M | 187334126U, // VSUBWuv8i16 |
3183 | 1.35M | 253131014U, // VSUBfd |
3184 | 1.35M | 253131014U, // VSUBfq |
3185 | 1.35M | 252999942U, // VSUBhd |
3186 | 1.35M | 252999942U, // VSUBhq |
3187 | 1.35M | 187857158U, // VSUBv16i8 |
3188 | 1.35M | 187463942U, // VSUBv1i64 |
3189 | 1.35M | 187595014U, // VSUBv2i32 |
3190 | 1.35M | 187463942U, // VSUBv2i64 |
3191 | 1.35M | 187726086U, // VSUBv4i16 |
3192 | 1.35M | 187595014U, // VSUBv4i32 |
3193 | 1.35M | 187726086U, // VSUBv8i16 |
3194 | 1.35M | 187857158U, // VSUBv8i8 |
3195 | 1.35M | 547888U, // VSWPd |
3196 | 1.35M | 547888U, // VSWPq |
3197 | 1.35M | 424682U, // VTBL1 |
3198 | 1.35M | 424682U, // VTBL2 |
3199 | 1.35M | 424682U, // VTBL3 |
3200 | 1.35M | 0U, // VTBL3Pseudo |
3201 | 1.35M | 424682U, // VTBL4 |
3202 | 1.35M | 0U, // VTBL4Pseudo |
3203 | 1.35M | 417355U, // VTBX1 |
3204 | 1.35M | 417355U, // VTBX2 |
3205 | 1.35M | 417355U, // VTBX3 |
3206 | 1.35M | 0U, // VTBX3Pseudo |
3207 | 1.35M | 417355U, // VTBX4 |
3208 | 1.35M | 0U, // VTBX4Pseudo |
3209 | 1.35M | 7634354U, // VTOSHD |
3210 | 1.35M | 256146866U, // VTOSHH |
3211 | 1.35M | 7765426U, // VTOSHS |
3212 | 1.35M | 441597080U, // VTOSIRD |
3213 | 1.35M | 444087448U, // VTOSIRH |
3214 | 1.35M | 440417432U, // VTOSIRS |
3215 | 1.35M | 441597362U, // VTOSIZD |
3216 | 1.35M | 444087730U, // VTOSIZH |
3217 | 1.35M | 440417714U, // VTOSIZS |
3218 | 1.35M | 1330806194U, // VTOSLD |
3219 | 1.35M | 1333296562U, // VTOSLH |
3220 | 1.35M | 1329626546U, // VTOSLS |
3221 | 1.35M | 8027570U, // VTOUHD |
3222 | 1.35M | 256277938U, // VTOUHH |
3223 | 1.35M | 8158642U, // VTOUHS |
3224 | 1.35M | 444480664U, // VTOUIRD |
3225 | 1.35M | 444611736U, // VTOUIRH |
3226 | 1.35M | 440548504U, // VTOUIRS |
3227 | 1.35M | 444480946U, // VTOUIZD |
3228 | 1.35M | 444612018U, // VTOUIZH |
3229 | 1.35M | 440548786U, // VTOUIZS |
3230 | 1.35M | 1333689778U, // VTOULD |
3231 | 1.35M | 1333820850U, // VTOULH |
3232 | 1.35M | 1329757618U, // VTOULS |
3233 | 1.35M | 154596U, // VTRNd16 |
3234 | 1.35M | 285668U, // VTRNd32 |
3235 | 1.35M | 416740U, // VTRNd8 |
3236 | 1.35M | 154596U, // VTRNq16 |
3237 | 1.35M | 285668U, // VTRNq32 |
3238 | 1.35M | 416740U, // VTRNq8 |
3239 | 1.35M | 425351U, // VTSTv16i8 |
3240 | 1.35M | 294279U, // VTSTv2i32 |
3241 | 1.35M | 163207U, // VTSTv4i16 |
3242 | 1.35M | 294279U, // VTSTv4i32 |
3243 | 1.35M | 163207U, // VTSTv8i16 |
3244 | 1.35M | 425351U, // VTSTv8i8 |
3245 | 1.35M | 910483U, // VUDOTD |
3246 | 1.35M | 7070867U, // VUDOTDI |
3247 | 1.35M | 910483U, // VUDOTQ |
3248 | 1.35M | 7070867U, // VUDOTQI |
3249 | 1.35M | 8551858U, // VUHTOD |
3250 | 1.35M | 256802226U, // VUHTOH |
3251 | 1.35M | 8682930U, // VUHTOS |
3252 | 1.35M | 445005234U, // VUITOD |
3253 | 1.35M | 445136306U, // VUITOH |
3254 | 1.35M | 441204146U, // VUITOS |
3255 | 1.35M | 1334214066U, // VULTOD |
3256 | 1.35M | 1334345138U, // VULTOH |
3257 | 1.35M | 1330412978U, // VULTOS |
3258 | 1.35M | 154677U, // VUZPd16 |
3259 | 1.35M | 416821U, // VUZPd8 |
3260 | 1.35M | 154677U, // VUZPq16 |
3261 | 1.35M | 285749U, // VUZPq32 |
3262 | 1.35M | 416821U, // VUZPq8 |
3263 | 1.35M | 154653U, // VZIPd16 |
3264 | 1.35M | 416797U, // VZIPd8 |
3265 | 1.35M | 154653U, // VZIPq16 |
3266 | 1.35M | 285725U, // VZIPq32 |
3267 | 1.35M | 416797U, // VZIPq8 |
3268 | 1.35M | 571388U, // sysLDMDA |
3269 | 1.35M | 2332571644U, // sysLDMDA_UPD |
3270 | 1.35M | 571519U, // sysLDMDB |
3271 | 1.35M | 2332571775U, // sysLDMDB_UPD |
3272 | 1.35M | 572300U, // sysLDMIA |
3273 | 1.35M | 2332572556U, // sysLDMIA_UPD |
3274 | 1.35M | 571538U, // sysLDMIB |
3275 | 1.35M | 2332571794U, // sysLDMIB_UPD |
3276 | 1.35M | 571394U, // sysSTMDA |
3277 | 1.35M | 2332571650U, // sysSTMDA_UPD |
3278 | 1.35M | 571526U, // sysSTMDB |
3279 | 1.35M | 2332571782U, // sysSTMDB_UPD |
3280 | 1.35M | 572306U, // sysSTMIA |
3281 | 1.35M | 2332572562U, // sysSTMIA_UPD |
3282 | 1.35M | 571544U, // sysSTMIB |
3283 | 1.35M | 2332571800U, // sysSTMIB_UPD |
3284 | 1.35M | 530745U, // t2ADCri |
3285 | 1.35M | 9050425U, // t2ADCrr |
3286 | 1.35M | 9079097U, // t2ADCrs |
3287 | 1.35M | 9050486U, // t2ADDri |
3288 | 1.35M | 556533U, // t2ADDri12 |
3289 | 1.35M | 9050486U, // t2ADDrr |
3290 | 1.35M | 9079158U, // t2ADDrs |
3291 | 1.35M | 9059406U, // t2ADR |
3292 | 1.35M | 530859U, // t2ANDri |
3293 | 1.35M | 9050539U, // t2ANDrr |
3294 | 1.35M | 9079211U, // t2ANDrs |
3295 | 1.35M | 9051260U, // t2ASRri |
3296 | 1.35M | 9051260U, // t2ASRrr |
3297 | 1.35M | 1082832976U, // t2B |
3298 | 1.35M | 555329U, // t2BFC |
3299 | 1.35M | 547483U, // t2BFI |
3300 | 1.35M | 530758U, // t2BICri |
3301 | 1.35M | 9050438U, // t2BICrr |
3302 | 1.35M | 9079110U, // t2BICrs |
3303 | 1.35M | 1074313901U, // t2BXJ |
3304 | 1.35M | 1082832976U, // t2Bcc |
3305 | 1.35M | 201907225U, // t2CDP |
3306 | 1.35M | 201905823U, // t2CDP2 |
3307 | 1.35M | 839310U, // t2CLREX |
3308 | 1.35M | 540368U, // t2CLZ |
3309 | 1.35M | 9059263U, // t2CMNri |
3310 | 1.35M | 9059263U, // t2CMNzrr |
3311 | 1.35M | 9075647U, // t2CMNzrs |
3312 | 1.35M | 9059363U, // t2CMPri |
3313 | 1.35M | 9059363U, // t2CMPrr |
3314 | 1.35M | 9075747U, // t2CMPrs |
3315 | 1.35M | 828709U, // t2CPS1p |
3316 | 1.35M | 1317731549U, // t2CPS2p |
3317 | 1.35M | 235470045U, // t2CPS3p |
3318 | 1.35M | 185246891U, // t2CRC32B |
3319 | 1.35M | 185246899U, // t2CRC32CB |
3320 | 1.35M | 185246973U, // t2CRC32CH |
3321 | 1.35M | 185247057U, // t2CRC32CW |
3322 | 1.35M | 185246965U, // t2CRC32H |
3323 | 1.35M | 185247049U, // t2CRC32W |
3324 | 1.35M | 1074313739U, // t2DBG |
3325 | 1.35M | 837235U, // t2DCPS1 |
3326 | 1.35M | 837295U, // t2DCPS2 |
3327 | 1.35M | 837311U, // t2DCPS3 |
3328 | 1.35M | 822655139U, // t2DMB |
3329 | 1.35M | 822655158U, // t2DSB |
3330 | 1.35M | 531562U, // t2EORri |
3331 | 1.35M | 9051242U, // t2EORrr |
3332 | 1.35M | 9079914U, // t2EORrs |
3333 | 1.35M | 1082834290U, // t2HINT |
3334 | 1.35M | 828731U, // t2HVC |
3335 | 1.35M | 839432378U, // t2ISB |
3336 | 1.35M | 17313120U, // t2IT |
3337 | 1.35M | 0U, // t2Int_eh_sjlj_setjmp |
3338 | 1.35M | 0U, // t2Int_eh_sjlj_setjmp_nofp |
3339 | 1.35M | 538616U, // t2LDA |
3340 | 1.35M | 538701U, // t2LDAB |
3341 | 1.35M | 540284U, // t2LDAEX |
3342 | 1.35M | 538905U, // t2LDAEXB |
3343 | 1.35M | 555461U, // t2LDAEXD |
3344 | 1.35M | 539263U, // t2LDAEXH |
3345 | 1.35M | 539165U, // t2LDAH |
3346 | 1.35M | 1275615921U, // t2LDC2L_OFFSET |
3347 | 1.35M | 1275615921U, // t2LDC2L_OPTION |
3348 | 1.35M | 1275615921U, // t2LDC2L_POST |
3349 | 1.35M | 1275615921U, // t2LDC2L_PRE |
3350 | 1.35M | 1275614853U, // t2LDC2_OFFSET |
3351 | 1.35M | 1275614853U, // t2LDC2_OPTION |
3352 | 1.35M | 1275614853U, // t2LDC2_POST |
3353 | 1.35M | 1275614853U, // t2LDC2_PRE |
3354 | 1.35M | 1275615989U, // t2LDCL_OFFSET |
3355 | 1.35M | 1275615989U, // t2LDCL_OPTION |
3356 | 1.35M | 1275615989U, // t2LDCL_POST |
3357 | 1.35M | 1275615989U, // t2LDCL_PRE |
3358 | 1.35M | 1275615549U, // t2LDC_OFFSET |
3359 | 1.35M | 1275615549U, // t2LDC_OPTION |
3360 | 1.35M | 1275615549U, // t2LDC_POST |
3361 | 1.35M | 1275615549U, // t2LDC_PRE |
3362 | 1.35M | 571519U, // t2LDMDB |
3363 | 1.35M | 2332571775U, // t2LDMDB_UPD |
3364 | 1.35M | 9091980U, // t2LDMIA |
3365 | 1.35M | 2341092236U, // t2LDMIA_UPD |
3366 | 1.35M | 556328U, // t2LDRBT |
3367 | 1.35M | 546988U, // t2LDRB_POST |
3368 | 1.35M | 546988U, // t2LDRB_PRE |
3369 | 1.35M | 9074860U, // t2LDRBi12 |
3370 | 1.35M | 555180U, // t2LDRBi8 |
3371 | 1.35M | 9058476U, // t2LDRBpci |
3372 | 1.35M | 9066668U, // t2LDRBs |
3373 | 1.35M | 551343U, // t2LDRD_POST |
3374 | 1.35M | 551343U, // t2LDRD_PRE |
3375 | 1.35M | 547247U, // t2LDRDi8 |
3376 | 1.35M | 556680U, // t2LDREX |
3377 | 1.35M | 538919U, // t2LDREXB |
3378 | 1.35M | 555475U, // t2LDREXD |
3379 | 1.35M | 539277U, // t2LDREXH |
3380 | 1.35M | 556363U, // t2LDRHT |
3381 | 1.35M | 547409U, // t2LDRH_POST |
3382 | 1.35M | 547409U, // t2LDRH_PRE |
3383 | 1.35M | 9075281U, // t2LDRHi12 |
3384 | 1.35M | 555601U, // t2LDRHi8 |
3385 | 1.35M | 9058897U, // t2LDRHpci |
3386 | 1.35M | 9067089U, // t2LDRHs |
3387 | 1.35M | 556340U, // t2LDRSBT |
3388 | 1.35M | 547006U, // t2LDRSB_POST |
3389 | 1.35M | 547006U, // t2LDRSB_PRE |
3390 | 1.35M | 9074878U, // t2LDRSBi12 |
3391 | 1.35M | 555198U, // t2LDRSBi8 |
3392 | 1.35M | 9058494U, // t2LDRSBpci |
3393 | 1.35M | 9066686U, // t2LDRSBs |
3394 | 1.35M | 556375U, // t2LDRSHT |
3395 | 1.35M | 547428U, // t2LDRSH_POST |
3396 | 1.35M | 547428U, // t2LDRSH_PRE |
3397 | 1.35M | 9075300U, // t2LDRSHi12 |
3398 | 1.35M | 555620U, // t2LDRSHi8 |
3399 | 1.35M | 9058916U, // t2LDRSHpci |
3400 | 1.35M | 9067108U, // t2LDRSHs |
3401 | 1.35M | 556407U, // t2LDRT |
3402 | 1.35M | 547923U, // t2LDR_POST |
3403 | 1.35M | 547923U, // t2LDR_PRE |
3404 | 1.35M | 9075795U, // t2LDRi12 |
3405 | 1.35M | 556115U, // t2LDRi8 |
3406 | 1.35M | 9059411U, // t2LDRpci |
3407 | 1.35M | 9067603U, // t2LDRs |
3408 | 1.35M | 9050981U, // t2LSLri |
3409 | 1.35M | 9050981U, // t2LSLrr |
3410 | 1.35M | 9051267U, // t2LSRri |
3411 | 1.35M | 9051267U, // t2LSRrr |
3412 | 1.35M | 201907274U, // t2MCR |
3413 | 1.35M | 201905828U, // t2MCR2 |
3414 | 1.35M | 201878642U, // t2MCRR |
3415 | 1.35M | 201877161U, // t2MCRR2 |
3416 | 1.35M | 546852U, // t2MLA |
3417 | 1.35M | 548021U, // t2MLS |
3418 | 1.35M | 556471U, // t2MOVTi16 |
3419 | 1.35M | 9063914U, // t2MOVi |
3420 | 1.35M | 540159U, // t2MOVi16 |
3421 | 1.35M | 9063914U, // t2MOVr |
3422 | 1.35M | 9059558U, // t2MOVsra_flag |
3423 | 1.35M | 9059563U, // t2MOVsrl_flag |
3424 | 1.35M | 336124238U, // t2MRC |
3425 | 1.35M | 336123530U, // t2MRC2 |
3426 | 1.35M | 352872786U, // t2MRRC |
3427 | 1.35M | 352872079U, // t2MRRC2 |
3428 | 1.35M | 2148056290U, // t2MRS_AR |
3429 | 1.35M | 539874U, // t2MRS_M |
3430 | 1.35M | 539874U, // t2MRSbanked |
3431 | 1.35M | 3221798114U, // t2MRSsys_AR |
3432 | 1.35M | 369638536U, // t2MSR_AR |
3433 | 1.35M | 369638536U, // t2MSR_M |
3434 | 1.35M | 386415752U, // t2MSRbanked |
3435 | 1.35M | 555893U, // t2MUL |
3436 | 1.35M | 543747U, // t2MVNi |
3437 | 1.35M | 9063427U, // t2MVNr |
3438 | 1.35M | 9051139U, // t2MVNs |
3439 | 1.35M | 531424U, // t2ORNri |
3440 | 1.35M | 531424U, // t2ORNrr |
3441 | 1.35M | 560096U, // t2ORNrs |
3442 | 1.35M | 531576U, // t2ORRri |
3443 | 1.35M | 9051256U, // t2ORRrr |
3444 | 1.35M | 9079928U, // t2ORRrs |
3445 | 1.35M | 548115U, // t2PKHBT |
3446 | 1.35M | 547023U, // t2PKHTB |
3447 | 1.35M | 856178170U, // t2PLDWi12 |
3448 | 1.35M | 872955386U, // t2PLDWi8 |
3449 | 1.35M | 889748986U, // t2PLDWs |
3450 | 1.35M | 856177055U, // t2PLDi12 |
3451 | 1.35M | 872954271U, // t2PLDi8 |
3452 | 1.35M | 906541471U, // t2PLDpci |
3453 | 1.35M | 889747871U, // t2PLDs |
3454 | 1.35M | 856177311U, // t2PLIi12 |
3455 | 1.35M | 872954527U, // t2PLIi8 |
3456 | 1.35M | 906541727U, // t2PLIpci |
3457 | 1.35M | 889748127U, // t2PLIs |
3458 | 1.35M | 555406U, // t2QADD |
3459 | 1.35M | 554800U, // t2QADD16 |
3460 | 1.35M | 554903U, // t2QADD8 |
3461 | 1.35M | 556729U, // t2QASX |
3462 | 1.35M | 555380U, // t2QDADD |
3463 | 1.35M | 555252U, // t2QDSUB |
3464 | 1.35M | 556588U, // t2QSAX |
3465 | 1.35M | 555265U, // t2QSUB |
3466 | 1.35M | 554762U, // t2QSUB16 |
3467 | 1.35M | 554864U, // t2QSUB8 |
3468 | 1.35M | 539998U, // t2RBIT |
3469 | 1.35M | 9059798U, // t2REV |
3470 | 1.35M | 9058132U, // t2REV16 |
3471 | 1.35M | 9058927U, // t2REVSH |
3472 | 1.35M | 1074313336U, // t2RFEDB |
3473 | 1.35M | 2148055160U, // t2RFEDBW |
3474 | 1.35M | 1074313224U, // t2RFEIA |
3475 | 1.35M | 2148055048U, // t2RFEIAW |
3476 | 1.35M | 9051246U, // t2RORri |
3477 | 1.35M | 9051246U, // t2RORrr |
3478 | 1.35M | 544424U, // t2RRX |
3479 | 1.35M | 9050304U, // t2RSBri |
3480 | 1.35M | 530624U, // t2RSBrr |
3481 | 1.35M | 559296U, // t2RSBrs |
3482 | 1.35M | 554807U, // t2SADD16 |
3483 | 1.35M | 554909U, // t2SADD8 |
3484 | 1.35M | 556734U, // t2SASX |
3485 | 1.35M | 530741U, // t2SBCri |
3486 | 1.35M | 9050421U, // t2SBCrr |
3487 | 1.35M | 9079093U, // t2SBCrs |
3488 | 1.35M | 548506U, // t2SBFX |
3489 | 1.35M | 556506U, // t2SDIV |
3490 | 1.35M | 555794U, // t2SEL |
3491 | 1.35M | 828701U, // t2SETPAN |
3492 | 1.35M | 838170U, // t2SG |
3493 | 1.35M | 554783U, // t2SHADD16 |
3494 | 1.35M | 554888U, // t2SHADD8 |
3495 | 1.35M | 556716U, // t2SHASX |
3496 | 1.35M | 556575U, // t2SHSAX |
3497 | 1.35M | 554745U, // t2SHSUB16 |
3498 | 1.35M | 554849U, // t2SHSUB8 |
3499 | 1.35M | 1074313546U, // t2SMC |
3500 | 1.35M | 546910U, // t2SMLABB |
3501 | 1.35M | 548108U, // t2SMLABT |
3502 | 1.35M | 547171U, // t2SMLAD |
3503 | 1.35M | 548432U, // t2SMLADX |
3504 | 1.35M | 580312U, // t2SMLAL |
3505 | 1.35M | 579685U, // t2SMLALBB |
3506 | 1.35M | 580889U, // t2SMLALBT |
3507 | 1.35M | 579992U, // t2SMLALD |
3508 | 1.35M | 581214U, // t2SMLALDX |
3509 | 1.35M | 579797U, // t2SMLALTB |
3510 | 1.35M | 581011U, // t2SMLALTT |
3511 | 1.35M | 547016U, // t2SMLATB |
3512 | 1.35M | 548236U, // t2SMLATT |
3513 | 1.35M | 547083U, // t2SMLAWB |
3514 | 1.35M | 548284U, // t2SMLAWT |
3515 | 1.35M | 547257U, // t2SMLSD |
3516 | 1.35M | 548462U, // t2SMLSDX |
3517 | 1.35M | 580003U, // t2SMLSLD |
3518 | 1.35M | 581222U, // t2SMLSLDX |
3519 | 1.35M | 546850U, // t2SMMLA |
3520 | 1.35M | 547907U, // t2SMMLAR |
3521 | 1.35M | 548019U, // t2SMMLS |
3522 | 1.35M | 547968U, // t2SMMLSR |
3523 | 1.35M | 555891U, // t2SMMUL |
3524 | 1.35M | 556130U, // t2SMMULR |
3525 | 1.35M | 555369U, // t2SMUAD |
3526 | 1.35M | 556631U, // t2SMUADX |
3527 | 1.35M | 555117U, // t2SMULBB |
3528 | 1.35M | 556321U, // t2SMULBT |
3529 | 1.35M | 547658U, // t2SMULL |
3530 | 1.35M | 555229U, // t2SMULTB |
3531 | 1.35M | 556443U, // t2SMULTT |
3532 | 1.35M | 555282U, // t2SMULWB |
3533 | 1.35M | 556483U, // t2SMULWT |
3534 | 1.35M | 555455U, // t2SMUSD |
3535 | 1.35M | 556661U, // t2SMUSDX |
3536 | 1.35M | 9222284U, // t2SRSDB |
3537 | 1.35M | 9353356U, // t2SRSDB_UPD |
3538 | 1.35M | 9222172U, // t2SRSIA |
3539 | 1.35M | 9353244U, // t2SRSIA_UPD |
3540 | 1.35M | 548093U, // t2SSAT |
3541 | 1.35M | 554821U, // t2SSAT16 |
3542 | 1.35M | 556593U, // t2SSAX |
3543 | 1.35M | 554769U, // t2SSUB16 |
3544 | 1.35M | 554870U, // t2SSUB8 |
3545 | 1.35M | 1275615927U, // t2STC2L_OFFSET |
3546 | 1.35M | 1275615927U, // t2STC2L_OPTION |
3547 | 1.35M | 1275615927U, // t2STC2L_POST |
3548 | 1.35M | 1275615927U, // t2STC2L_PRE |
3549 | 1.35M | 1275614869U, // t2STC2_OFFSET |
3550 | 1.35M | 1275614869U, // t2STC2_OPTION |
3551 | 1.35M | 1275614869U, // t2STC2_POST |
3552 | 1.35M | 1275614869U, // t2STC2_PRE |
3553 | 1.35M | 1275615994U, // t2STCL_OFFSET |
3554 | 1.35M | 1275615994U, // t2STCL_OPTION |
3555 | 1.35M | 1275615994U, // t2STCL_POST |
3556 | 1.35M | 1275615994U, // t2STCL_PRE |
3557 | 1.35M | 1275615579U, // t2STC_OFFSET |
3558 | 1.35M | 1275615579U, // t2STC_OPTION |
3559 | 1.35M | 1275615579U, // t2STC_POST |
3560 | 1.35M | 1275615579U, // t2STC_PRE |
3561 | 1.35M | 539503U, // t2STL |
3562 | 1.35M | 538782U, // t2STLB |
3563 | 1.35M | 556674U, // t2STLEX |
3564 | 1.35M | 555296U, // t2STLEXB |
3565 | 1.35M | 547276U, // t2STLEXD |
3566 | 1.35M | 555654U, // t2STLEXH |
3567 | 1.35M | 539195U, // t2STLH |
3568 | 1.35M | 571526U, // t2STMDB |
3569 | 1.35M | 2332571782U, // t2STMDB_UPD |
3570 | 1.35M | 9091986U, // t2STMIA |
3571 | 1.35M | 2341092242U, // t2STMIA_UPD |
3572 | 1.35M | 556334U, // t2STRBT |
3573 | 1.35M | 185096369U, // t2STRB_POST |
3574 | 1.35M | 185096369U, // t2STRB_PRE |
3575 | 1.35M | 9074865U, // t2STRBi12 |
3576 | 1.35M | 555185U, // t2STRBi8 |
3577 | 1.35M | 9066673U, // t2STRBs |
3578 | 1.35M | 185100724U, // t2STRD_POST |
3579 | 1.35M | 185100724U, // t2STRD_PRE |
3580 | 1.35M | 547252U, // t2STRDi8 |
3581 | 1.35M | 548500U, // t2STREX |
3582 | 1.35M | 555310U, // t2STREXB |
3583 | 1.35M | 547290U, // t2STREXD |
3584 | 1.35M | 555668U, // t2STREXH |
3585 | 1.35M | 556369U, // t2STRHT |
3586 | 1.35M | 185096790U, // t2STRH_POST |
3587 | 1.35M | 185096790U, // t2STRH_PRE |
3588 | 1.35M | 9075286U, // t2STRHi12 |
3589 | 1.35M | 555606U, // t2STRHi8 |
3590 | 1.35M | 9067094U, // t2STRHs |
3591 | 1.35M | 556418U, // t2STRT |
3592 | 1.35M | 185097364U, // t2STR_POST |
3593 | 1.35M | 185097364U, // t2STR_PRE |
3594 | 1.35M | 9075860U, // t2STRi12 |
3595 | 1.35M | 556180U, // t2STRi8 |
3596 | 1.35M | 9067668U, // t2STRs |
3597 | 1.35M | 9485481U, // t2SUBS_PC_LR |
3598 | 1.35M | 9050358U, // t2SUBri |
3599 | 1.35M | 556527U, // t2SUBri12 |
3600 | 1.35M | 9050358U, // t2SUBrr |
3601 | 1.35M | 9079030U, // t2SUBrs |
3602 | 1.35M | 546898U, // t2SXTAB |
3603 | 1.35M | 546523U, // t2SXTAB16 |
3604 | 1.35M | 547371U, // t2SXTAH |
3605 | 1.35M | 9074922U, // t2SXTB |
3606 | 1.35M | 554731U, // t2SXTB16 |
3607 | 1.35M | 9075317U, // t2SXTH |
3608 | 1.35M | 923285620U, // t2TBB |
3609 | 1.35M | 940063287U, // t2TBH |
3610 | 1.35M | 9059391U, // t2TEQri |
3611 | 1.35M | 9059391U, // t2TEQrr |
3612 | 1.35M | 9075775U, // t2TEQrs |
3613 | 1.35M | 956872900U, // t2TSB |
3614 | 1.35M | 9059720U, // t2TSTri |
3615 | 1.35M | 9059720U, // t2TSTrr |
3616 | 1.35M | 9076104U, // t2TSTrs |
3617 | 1.35M | 540048U, // t2TT |
3618 | 1.35M | 538697U, // t2TTA |
3619 | 1.35M | 539911U, // t2TTAT |
3620 | 1.35M | 540066U, // t2TTT |
3621 | 1.35M | 554814U, // t2UADD16 |
3622 | 1.35M | 554915U, // t2UADD8 |
3623 | 1.35M | 556739U, // t2UASX |
3624 | 1.35M | 548511U, // t2UBFX |
3625 | 1.35M | 828738U, // t2UDF |
3626 | 1.35M | 556511U, // t2UDIV |
3627 | 1.35M | 554791U, // t2UHADD16 |
3628 | 1.35M | 554895U, // t2UHADD8 |
3629 | 1.35M | 556722U, // t2UHASX |
3630 | 1.35M | 556581U, // t2UHSAX |
3631 | 1.35M | 554753U, // t2UHSUB16 |
3632 | 1.35M | 554856U, // t2UHSUB8 |
3633 | 1.35M | 580285U, // t2UMAAL |
3634 | 1.35M | 580318U, // t2UMLAL |
3635 | 1.35M | 547664U, // t2UMULL |
3636 | 1.35M | 554799U, // t2UQADD16 |
3637 | 1.35M | 554902U, // t2UQADD8 |
3638 | 1.35M | 556728U, // t2UQASX |
3639 | 1.35M | 556587U, // t2UQSAX |
3640 | 1.35M | 554761U, // t2UQSUB16 |
3641 | 1.35M | 554863U, // t2UQSUB8 |
3642 | 1.35M | 554882U, // t2USAD8 |
3643 | 1.35M | 546650U, // t2USADA8 |
3644 | 1.35M | 548098U, // t2USAT |
3645 | 1.35M | 554828U, // t2USAT16 |
3646 | 1.35M | 556598U, // t2USAX |
3647 | 1.35M | 554776U, // t2USUB16 |
3648 | 1.35M | 554876U, // t2USUB8 |
3649 | 1.35M | 546904U, // t2UXTAB |
3650 | 1.35M | 546531U, // t2UXTAB16 |
3651 | 1.35M | 547377U, // t2UXTAH |
3652 | 1.35M | 9074927U, // t2UXTB |
3653 | 1.35M | 554738U, // t2UXTB16 |
3654 | 1.35M | 9075322U, // t2UXTH |
3655 | 1.35M | 982776121U, // tADC |
3656 | 1.35M | 555382U, // tADDhirr |
3657 | 1.35M | 177469814U, // tADDi3 |
3658 | 1.35M | 982776182U, // tADDi8 |
3659 | 1.35M | 555382U, // tADDrSP |
3660 | 1.35M | 555382U, // tADDrSPi |
3661 | 1.35M | 177469814U, // tADDrr |
3662 | 1.35M | 555382U, // tADDspi |
3663 | 1.35M | 555382U, // tADDspr |
3664 | 1.35M | 539726U, // tADR |
3665 | 1.35M | 982776235U, // tAND |
3666 | 1.35M | 177470588U, // tASRri |
3667 | 1.35M | 982776956U, // tASRrr |
3668 | 1.35M | 1074313296U, // tB |
3669 | 1.35M | 982776134U, // tBIC |
3670 | 1.35M | 828725U, // tBKPT |
3671 | 1.35M | 1242090220U, // tBL |
3672 | 1.35M | 1242090708U, // tBLXNSr |
3673 | 1.35M | 1242091172U, // tBLXi |
3674 | 1.35M | 1242091172U, // tBLXr |
3675 | 1.35M | 1074314816U, // tBX |
3676 | 1.35M | 1074314447U, // tBXNS |
3677 | 1.35M | 1074313296U, // tBcc |
3678 | 1.35M | 1258988910U, // tCBNZ |
3679 | 1.35M | 1258988905U, // tCBZ |
3680 | 1.35M | 539583U, // tCMNz |
3681 | 1.35M | 539683U, // tCMPhir |
3682 | 1.35M | 539683U, // tCMPi8 |
3683 | 1.35M | 539683U, // tCMPr |
3684 | 1.35M | 1308687581U, // tCPS |
3685 | 1.35M | 982776938U, // tEOR |
3686 | 1.35M | 1074314610U, // tHINT |
3687 | 1.35M | 828720U, // tHLT |
3688 | 1.35M | 0U, // tInt_WIN_eh_sjlj_longjmp |
3689 | 1.35M | 0U, // tInt_eh_sjlj_longjmp |
3690 | 1.35M | 0U, // tInt_eh_sjlj_setjmp |
3691 | 1.35M | 572300U, // tLDMIA |
3692 | 1.35M | 555180U, // tLDRBi |
3693 | 1.35M | 555180U, // tLDRBr |
3694 | 1.35M | 555601U, // tLDRHi |
3695 | 1.35M | 555601U, // tLDRHr |
3696 | 1.35M | 555198U, // tLDRSB |
3697 | 1.35M | 555620U, // tLDRSH |
3698 | 1.35M | 556115U, // tLDRi |
3699 | 1.35M | 539731U, // tLDRpci |
3700 | 1.35M | 556115U, // tLDRr |
3701 | 1.35M | 556115U, // tLDRspi |
3702 | 1.35M | 177470309U, // tLSLri |
3703 | 1.35M | 982776677U, // tLSLrr |
3704 | 1.35M | 177470595U, // tLSRri |
3705 | 1.35M | 982776963U, // tLSRrr |
3706 | 1.35M | 1258988842U, // tMOVSr |
3707 | 1.35M | 446037482U, // tMOVi8 |
3708 | 1.35M | 540138U, // tMOVr |
3709 | 1.35M | 177470325U, // tMUL |
3710 | 1.35M | 446036995U, // tMVN |
3711 | 1.35M | 982776952U, // tORR |
3712 | 1.35M | 0U, // tPICADD |
3713 | 1.35M | 990432295U, // tPOP |
3714 | 1.35M | 990431850U, // tPUSH |
3715 | 1.35M | 540118U, // tREV |
3716 | 1.35M | 538452U, // tREV16 |
3717 | 1.35M | 539247U, // tREVSH |
3718 | 1.35M | 982776942U, // tROR |
3719 | 1.35M | 429258944U, // tRSB |
3720 | 1.35M | 982776117U, // tSBC |
3721 | 1.35M | 91368U, // tSETEND |
3722 | 1.35M | 2332572562U, // tSTMIA_UPD |
3723 | 1.35M | 555185U, // tSTRBi |
3724 | 1.35M | 555185U, // tSTRBr |
3725 | 1.35M | 555606U, // tSTRHi |
3726 | 1.35M | 555606U, // tSTRHr |
3727 | 1.35M | 556180U, // tSTRi |
3728 | 1.35M | 556180U, // tSTRr |
3729 | 1.35M | 556180U, // tSTRspi |
3730 | 1.35M | 177469686U, // tSUBi3 |
3731 | 1.35M | 982776054U, // tSUBi8 |
3732 | 1.35M | 177469686U, // tSUBrr |
3733 | 1.35M | 555254U, // tSUBspi |
3734 | 1.35M | 1074313567U, // tSVC |
3735 | 1.35M | 538858U, // tSXTB |
3736 | 1.35M | 539253U, // tSXTH |
3737 | 1.35M | 3092U, // tTRAP |
3738 | 1.35M | 540040U, // tTST |
3739 | 1.35M | 828656U, // tUDF |
3740 | 1.35M | 538863U, // tUXTB |
3741 | 1.35M | 539258U, // tUXTH |
3742 | 1.35M | 1636U, // t__brkdiv0 |
3743 | 1.35M | }; |
3744 | | |
3745 | 1.35M | static const uint32_t OpInfo1[] = { |
3746 | 1.35M | 0U, // PHI |
3747 | 1.35M | 0U, // INLINEASM |
3748 | 1.35M | 0U, // CFI_INSTRUCTION |
3749 | 1.35M | 0U, // EH_LABEL |
3750 | 1.35M | 0U, // GC_LABEL |
3751 | 1.35M | 0U, // ANNOTATION_LABEL |
3752 | 1.35M | 0U, // KILL |
3753 | 1.35M | 0U, // EXTRACT_SUBREG |
3754 | 1.35M | 0U, // INSERT_SUBREG |
3755 | 1.35M | 0U, // IMPLICIT_DEF |
3756 | 1.35M | 0U, // SUBREG_TO_REG |
3757 | 1.35M | 0U, // COPY_TO_REGCLASS |
3758 | 1.35M | 0U, // DBG_VALUE |
3759 | 1.35M | 0U, // DBG_LABEL |
3760 | 1.35M | 0U, // REG_SEQUENCE |
3761 | 1.35M | 0U, // COPY |
3762 | 1.35M | 0U, // BUNDLE |
3763 | 1.35M | 0U, // LIFETIME_START |
3764 | 1.35M | 0U, // LIFETIME_END |
3765 | 1.35M | 0U, // STACKMAP |
3766 | 1.35M | 0U, // FENTRY_CALL |
3767 | 1.35M | 0U, // PATCHPOINT |
3768 | 1.35M | 0U, // LOAD_STACK_GUARD |
3769 | 1.35M | 0U, // STATEPOINT |
3770 | 1.35M | 0U, // LOCAL_ESCAPE |
3771 | 1.35M | 0U, // FAULTING_OP |
3772 | 1.35M | 0U, // PATCHABLE_OP |
3773 | 1.35M | 0U, // PATCHABLE_FUNCTION_ENTER |
3774 | 1.35M | 0U, // PATCHABLE_RET |
3775 | 1.35M | 0U, // PATCHABLE_FUNCTION_EXIT |
3776 | 1.35M | 0U, // PATCHABLE_TAIL_CALL |
3777 | 1.35M | 0U, // PATCHABLE_EVENT_CALL |
3778 | 1.35M | 0U, // PATCHABLE_TYPED_EVENT_CALL |
3779 | 1.35M | 0U, // ICALL_BRANCH_FUNNEL |
3780 | 1.35M | 0U, // G_ADD |
3781 | 1.35M | 0U, // G_SUB |
3782 | 1.35M | 0U, // G_MUL |
3783 | 1.35M | 0U, // G_SDIV |
3784 | 1.35M | 0U, // G_UDIV |
3785 | 1.35M | 0U, // G_SREM |
3786 | 1.35M | 0U, // G_UREM |
3787 | 1.35M | 0U, // G_AND |
3788 | 1.35M | 0U, // G_OR |
3789 | 1.35M | 0U, // G_XOR |
3790 | 1.35M | 0U, // G_IMPLICIT_DEF |
3791 | 1.35M | 0U, // G_PHI |
3792 | 1.35M | 0U, // G_FRAME_INDEX |
3793 | 1.35M | 0U, // G_GLOBAL_VALUE |
3794 | 1.35M | 0U, // G_EXTRACT |
3795 | 1.35M | 0U, // G_UNMERGE_VALUES |
3796 | 1.35M | 0U, // G_INSERT |
3797 | 1.35M | 0U, // G_MERGE_VALUES |
3798 | 1.35M | 0U, // G_PTRTOINT |
3799 | 1.35M | 0U, // G_INTTOPTR |
3800 | 1.35M | 0U, // G_BITCAST |
3801 | 1.35M | 0U, // G_LOAD |
3802 | 1.35M | 0U, // G_SEXTLOAD |
3803 | 1.35M | 0U, // G_ZEXTLOAD |
3804 | 1.35M | 0U, // G_STORE |
3805 | 1.35M | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
3806 | 1.35M | 0U, // G_ATOMIC_CMPXCHG |
3807 | 1.35M | 0U, // G_ATOMICRMW_XCHG |
3808 | 1.35M | 0U, // G_ATOMICRMW_ADD |
3809 | 1.35M | 0U, // G_ATOMICRMW_SUB |
3810 | 1.35M | 0U, // G_ATOMICRMW_AND |
3811 | 1.35M | 0U, // G_ATOMICRMW_NAND |
3812 | 1.35M | 0U, // G_ATOMICRMW_OR |
3813 | 1.35M | 0U, // G_ATOMICRMW_XOR |
3814 | 1.35M | 0U, // G_ATOMICRMW_MAX |
3815 | 1.35M | 0U, // G_ATOMICRMW_MIN |
3816 | 1.35M | 0U, // G_ATOMICRMW_UMAX |
3817 | 1.35M | 0U, // G_ATOMICRMW_UMIN |
3818 | 1.35M | 0U, // G_BRCOND |
3819 | 1.35M | 0U, // G_BRINDIRECT |
3820 | 1.35M | 0U, // G_INTRINSIC |
3821 | 1.35M | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
3822 | 1.35M | 0U, // G_ANYEXT |
3823 | 1.35M | 0U, // G_TRUNC |
3824 | 1.35M | 0U, // G_CONSTANT |
3825 | 1.35M | 0U, // G_FCONSTANT |
3826 | 1.35M | 0U, // G_VASTART |
3827 | 1.35M | 0U, // G_VAARG |
3828 | 1.35M | 0U, // G_SEXT |
3829 | 1.35M | 0U, // G_ZEXT |
3830 | 1.35M | 0U, // G_SHL |
3831 | 1.35M | 0U, // G_LSHR |
3832 | 1.35M | 0U, // G_ASHR |
3833 | 1.35M | 0U, // G_ICMP |
3834 | 1.35M | 0U, // G_FCMP |
3835 | 1.35M | 0U, // G_SELECT |
3836 | 1.35M | 0U, // G_UADDE |
3837 | 1.35M | 0U, // G_USUBE |
3838 | 1.35M | 0U, // G_SADDO |
3839 | 1.35M | 0U, // G_SSUBO |
3840 | 1.35M | 0U, // G_UMULO |
3841 | 1.35M | 0U, // G_SMULO |
3842 | 1.35M | 0U, // G_UMULH |
3843 | 1.35M | 0U, // G_SMULH |
3844 | 1.35M | 0U, // G_FADD |
3845 | 1.35M | 0U, // G_FSUB |
3846 | 1.35M | 0U, // G_FMUL |
3847 | 1.35M | 0U, // G_FMA |
3848 | 1.35M | 0U, // G_FDIV |
3849 | 1.35M | 0U, // G_FREM |
3850 | 1.35M | 0U, // G_FPOW |
3851 | 1.35M | 0U, // G_FEXP |
3852 | 1.35M | 0U, // G_FEXP2 |
3853 | 1.35M | 0U, // G_FLOG |
3854 | 1.35M | 0U, // G_FLOG2 |
3855 | 1.35M | 0U, // G_FNEG |
3856 | 1.35M | 0U, // G_FPEXT |
3857 | 1.35M | 0U, // G_FPTRUNC |
3858 | 1.35M | 0U, // G_FPTOSI |
3859 | 1.35M | 0U, // G_FPTOUI |
3860 | 1.35M | 0U, // G_SITOFP |
3861 | 1.35M | 0U, // G_UITOFP |
3862 | 1.35M | 0U, // G_FABS |
3863 | 1.35M | 0U, // G_GEP |
3864 | 1.35M | 0U, // G_PTR_MASK |
3865 | 1.35M | 0U, // G_BR |
3866 | 1.35M | 0U, // G_INSERT_VECTOR_ELT |
3867 | 1.35M | 0U, // G_EXTRACT_VECTOR_ELT |
3868 | 1.35M | 0U, // G_SHUFFLE_VECTOR |
3869 | 1.35M | 0U, // G_BSWAP |
3870 | 1.35M | 0U, // G_ADDRSPACE_CAST |
3871 | 1.35M | 0U, // G_BLOCK_ADDR |
3872 | 1.35M | 0U, // ABS |
3873 | 1.35M | 0U, // ADDSri |
3874 | 1.35M | 0U, // ADDSrr |
3875 | 1.35M | 0U, // ADDSrsi |
3876 | 1.35M | 0U, // ADDSrsr |
3877 | 1.35M | 0U, // ADJCALLSTACKDOWN |
3878 | 1.35M | 0U, // ADJCALLSTACKUP |
3879 | 1.35M | 0U, // ASRi |
3880 | 1.35M | 0U, // ASRr |
3881 | 1.35M | 0U, // B |
3882 | 1.35M | 0U, // BCCZi64 |
3883 | 1.35M | 0U, // BCCi64 |
3884 | 1.35M | 0U, // BMOVPCB_CALL |
3885 | 1.35M | 0U, // BMOVPCRX_CALL |
3886 | 1.35M | 0U, // BR_JTadd |
3887 | 1.35M | 0U, // BR_JTm_i12 |
3888 | 1.35M | 0U, // BR_JTm_rs |
3889 | 1.35M | 0U, // BR_JTr |
3890 | 1.35M | 0U, // BX_CALL |
3891 | 1.35M | 0U, // CMP_SWAP_16 |
3892 | 1.35M | 0U, // CMP_SWAP_32 |
3893 | 1.35M | 0U, // CMP_SWAP_64 |
3894 | 1.35M | 0U, // CMP_SWAP_8 |
3895 | 1.35M | 0U, // CONSTPOOL_ENTRY |
3896 | 1.35M | 0U, // COPY_STRUCT_BYVAL_I32 |
3897 | 1.35M | 0U, // CompilerBarrier |
3898 | 1.35M | 0U, // ITasm |
3899 | 1.35M | 0U, // Int_eh_sjlj_dispatchsetup |
3900 | 1.35M | 0U, // Int_eh_sjlj_longjmp |
3901 | 1.35M | 0U, // Int_eh_sjlj_setjmp |
3902 | 1.35M | 0U, // Int_eh_sjlj_setjmp_nofp |
3903 | 1.35M | 0U, // Int_eh_sjlj_setup_dispatch |
3904 | 1.35M | 0U, // JUMPTABLE_ADDRS |
3905 | 1.35M | 0U, // JUMPTABLE_INSTS |
3906 | 1.35M | 0U, // JUMPTABLE_TBB |
3907 | 1.35M | 0U, // JUMPTABLE_TBH |
3908 | 1.35M | 0U, // LDMIA_RET |
3909 | 1.35M | 8U, // LDRBT_POST |
3910 | 1.35M | 1024U, // LDRConstPool |
3911 | 1.35M | 0U, // LDRLIT_ga_abs |
3912 | 1.35M | 0U, // LDRLIT_ga_pcrel |
3913 | 1.35M | 0U, // LDRLIT_ga_pcrel_ldr |
3914 | 1.35M | 8U, // LDRT_POST |
3915 | 1.35M | 0U, // LEApcrel |
3916 | 1.35M | 0U, // LEApcrelJT |
3917 | 1.35M | 0U, // LSLi |
3918 | 1.35M | 0U, // LSLr |
3919 | 1.35M | 0U, // LSRi |
3920 | 1.35M | 0U, // LSRr |
3921 | 1.35M | 0U, // MEMCPY |
3922 | 1.35M | 0U, // MLAv5 |
3923 | 1.35M | 0U, // MOVCCi |
3924 | 1.35M | 0U, // MOVCCi16 |
3925 | 1.35M | 0U, // MOVCCi32imm |
3926 | 1.35M | 0U, // MOVCCr |
3927 | 1.35M | 0U, // MOVCCsi |
3928 | 1.35M | 0U, // MOVCCsr |
3929 | 1.35M | 0U, // MOVPCRX |
3930 | 1.35M | 0U, // MOVTi16_ga_pcrel |
3931 | 1.35M | 0U, // MOV_ga_pcrel |
3932 | 1.35M | 0U, // MOV_ga_pcrel_ldr |
3933 | 1.35M | 0U, // MOVi16_ga_pcrel |
3934 | 1.35M | 0U, // MOVi32imm |
3935 | 1.35M | 0U, // MOVsra_flag |
3936 | 1.35M | 0U, // MOVsrl_flag |
3937 | 1.35M | 0U, // MULv5 |
3938 | 1.35M | 0U, // MVNCCi |
3939 | 1.35M | 0U, // PICADD |
3940 | 1.35M | 0U, // PICLDR |
3941 | 1.35M | 0U, // PICLDRB |
3942 | 1.35M | 0U, // PICLDRH |
3943 | 1.35M | 0U, // PICLDRSB |
3944 | 1.35M | 0U, // PICLDRSH |
3945 | 1.35M | 0U, // PICSTR |
3946 | 1.35M | 0U, // PICSTRB |
3947 | 1.35M | 0U, // PICSTRH |
3948 | 1.35M | 0U, // RORi |
3949 | 1.35M | 0U, // RORr |
3950 | 1.35M | 0U, // RRX |
3951 | 1.35M | 1024U, // RRXi |
3952 | 1.35M | 0U, // RSBSri |
3953 | 1.35M | 0U, // RSBSrsi |
3954 | 1.35M | 0U, // RSBSrsr |
3955 | 1.35M | 0U, // SMLALv5 |
3956 | 1.35M | 0U, // SMULLv5 |
3957 | 1.35M | 0U, // SPACE |
3958 | 1.35M | 8U, // STRBT_POST |
3959 | 1.35M | 0U, // STRBi_preidx |
3960 | 1.35M | 0U, // STRBr_preidx |
3961 | 1.35M | 0U, // STRH_preidx |
3962 | 1.35M | 8U, // STRT_POST |
3963 | 1.35M | 0U, // STRi_preidx |
3964 | 1.35M | 0U, // STRr_preidx |
3965 | 1.35M | 0U, // SUBS_PC_LR |
3966 | 1.35M | 0U, // SUBSri |
3967 | 1.35M | 0U, // SUBSrr |
3968 | 1.35M | 0U, // SUBSrsi |
3969 | 1.35M | 0U, // SUBSrsr |
3970 | 1.35M | 0U, // TAILJMPd |
3971 | 1.35M | 0U, // TAILJMPr |
3972 | 1.35M | 0U, // TAILJMPr4 |
3973 | 1.35M | 0U, // TCRETURNdi |
3974 | 1.35M | 0U, // TCRETURNri |
3975 | 1.35M | 0U, // TPsoft |
3976 | 1.35M | 0U, // UMLALv5 |
3977 | 1.35M | 0U, // UMULLv5 |
3978 | 1.35M | 1040U, // VLD1LNdAsm_16 |
3979 | 1.35M | 1040U, // VLD1LNdAsm_32 |
3980 | 1.35M | 1040U, // VLD1LNdAsm_8 |
3981 | 1.35M | 2064U, // VLD1LNdWB_fixed_Asm_16 |
3982 | 1.35M | 2064U, // VLD1LNdWB_fixed_Asm_32 |
3983 | 1.35M | 2064U, // VLD1LNdWB_fixed_Asm_8 |
3984 | 1.35M | 32784U, // VLD1LNdWB_register_Asm_16 |
3985 | 1.35M | 32784U, // VLD1LNdWB_register_Asm_32 |
3986 | 1.35M | 32784U, // VLD1LNdWB_register_Asm_8 |
3987 | 1.35M | 1040U, // VLD2LNdAsm_16 |
3988 | 1.35M | 1040U, // VLD2LNdAsm_32 |
3989 | 1.35M | 1040U, // VLD2LNdAsm_8 |
3990 | 1.35M | 2064U, // VLD2LNdWB_fixed_Asm_16 |
3991 | 1.35M | 2064U, // VLD2LNdWB_fixed_Asm_32 |
3992 | 1.35M | 2064U, // VLD2LNdWB_fixed_Asm_8 |
3993 | 1.35M | 32784U, // VLD2LNdWB_register_Asm_16 |
3994 | 1.35M | 32784U, // VLD2LNdWB_register_Asm_32 |
3995 | 1.35M | 32784U, // VLD2LNdWB_register_Asm_8 |
3996 | 1.35M | 1040U, // VLD2LNqAsm_16 |
3997 | 1.35M | 1040U, // VLD2LNqAsm_32 |
3998 | 1.35M | 2064U, // VLD2LNqWB_fixed_Asm_16 |
3999 | 1.35M | 2064U, // VLD2LNqWB_fixed_Asm_32 |
4000 | 1.35M | 32784U, // VLD2LNqWB_register_Asm_16 |
4001 | 1.35M | 32784U, // VLD2LNqWB_register_Asm_32 |
4002 | 1.35M | 0U, // VLD3DUPdAsm_16 |
4003 | 1.35M | 0U, // VLD3DUPdAsm_32 |
4004 | 1.35M | 0U, // VLD3DUPdAsm_8 |
4005 | 1.35M | 0U, // VLD3DUPdWB_fixed_Asm_16 |
4006 | 1.35M | 0U, // VLD3DUPdWB_fixed_Asm_32 |
4007 | 1.35M | 0U, // VLD3DUPdWB_fixed_Asm_8 |
4008 | 1.35M | 1048U, // VLD3DUPdWB_register_Asm_16 |
4009 | 1.35M | 1048U, // VLD3DUPdWB_register_Asm_32 |
4010 | 1.35M | 1048U, // VLD3DUPdWB_register_Asm_8 |
4011 | 1.35M | 0U, // VLD3DUPqAsm_16 |
4012 | 1.35M | 0U, // VLD3DUPqAsm_32 |
4013 | 1.35M | 0U, // VLD3DUPqAsm_8 |
4014 | 1.35M | 0U, // VLD3DUPqWB_fixed_Asm_16 |
4015 | 1.35M | 0U, // VLD3DUPqWB_fixed_Asm_32 |
4016 | 1.35M | 0U, // VLD3DUPqWB_fixed_Asm_8 |
4017 | 1.35M | 1048U, // VLD3DUPqWB_register_Asm_16 |
4018 | 1.35M | 1048U, // VLD3DUPqWB_register_Asm_32 |
4019 | 1.35M | 1048U, // VLD3DUPqWB_register_Asm_8 |
4020 | 1.35M | 1040U, // VLD3LNdAsm_16 |
4021 | 1.35M | 1040U, // VLD3LNdAsm_32 |
4022 | 1.35M | 1040U, // VLD3LNdAsm_8 |
4023 | 1.35M | 2064U, // VLD3LNdWB_fixed_Asm_16 |
4024 | 1.35M | 2064U, // VLD3LNdWB_fixed_Asm_32 |
4025 | 1.35M | 2064U, // VLD3LNdWB_fixed_Asm_8 |
4026 | 1.35M | 32784U, // VLD3LNdWB_register_Asm_16 |
4027 | 1.35M | 32784U, // VLD3LNdWB_register_Asm_32 |
4028 | 1.35M | 32784U, // VLD3LNdWB_register_Asm_8 |
4029 | 1.35M | 1040U, // VLD3LNqAsm_16 |
4030 | 1.35M | 1040U, // VLD3LNqAsm_32 |
4031 | 1.35M | 2064U, // VLD3LNqWB_fixed_Asm_16 |
4032 | 1.35M | 2064U, // VLD3LNqWB_fixed_Asm_32 |
4033 | 1.35M | 32784U, // VLD3LNqWB_register_Asm_16 |
4034 | 1.35M | 32784U, // VLD3LNqWB_register_Asm_32 |
4035 | 1.35M | 32U, // VLD3dAsm_16 |
4036 | 1.35M | 32U, // VLD3dAsm_32 |
4037 | 1.35M | 32U, // VLD3dAsm_8 |
4038 | 1.35M | 40U, // VLD3dWB_fixed_Asm_16 |
4039 | 1.35M | 40U, // VLD3dWB_fixed_Asm_32 |
4040 | 1.35M | 40U, // VLD3dWB_fixed_Asm_8 |
4041 | 1.35M | 68656U, // VLD3dWB_register_Asm_16 |
4042 | 1.35M | 68656U, // VLD3dWB_register_Asm_32 |
4043 | 1.35M | 68656U, // VLD3dWB_register_Asm_8 |
4044 | 1.35M | 0U, // VLD3qAsm_16 |
4045 | 1.35M | 0U, // VLD3qAsm_32 |
4046 | 1.35M | 0U, // VLD3qAsm_8 |
4047 | 1.35M | 0U, // VLD3qWB_fixed_Asm_16 |
4048 | 1.35M | 0U, // VLD3qWB_fixed_Asm_32 |
4049 | 1.35M | 0U, // VLD3qWB_fixed_Asm_8 |
4050 | 1.35M | 1048U, // VLD3qWB_register_Asm_16 |
4051 | 1.35M | 1048U, // VLD3qWB_register_Asm_32 |
4052 | 1.35M | 1048U, // VLD3qWB_register_Asm_8 |
4053 | 1.35M | 0U, // VLD4DUPdAsm_16 |
4054 | 1.35M | 0U, // VLD4DUPdAsm_32 |
4055 | 1.35M | 0U, // VLD4DUPdAsm_8 |
4056 | 1.35M | 0U, // VLD4DUPdWB_fixed_Asm_16 |
4057 | 1.35M | 0U, // VLD4DUPdWB_fixed_Asm_32 |
4058 | 1.35M | 0U, // VLD4DUPdWB_fixed_Asm_8 |
4059 | 1.35M | 1048U, // VLD4DUPdWB_register_Asm_16 |
4060 | 1.35M | 1048U, // VLD4DUPdWB_register_Asm_32 |
4061 | 1.35M | 1048U, // VLD4DUPdWB_register_Asm_8 |
4062 | 1.35M | 0U, // VLD4DUPqAsm_16 |
4063 | 1.35M | 0U, // VLD4DUPqAsm_32 |
4064 | 1.35M | 0U, // VLD4DUPqAsm_8 |
4065 | 1.35M | 0U, // VLD4DUPqWB_fixed_Asm_16 |
4066 | 1.35M | 0U, // VLD4DUPqWB_fixed_Asm_32 |
4067 | 1.35M | 0U, // VLD4DUPqWB_fixed_Asm_8 |
4068 | 1.35M | 1048U, // VLD4DUPqWB_register_Asm_16 |
4069 | 1.35M | 1048U, // VLD4DUPqWB_register_Asm_32 |
4070 | 1.35M | 1048U, // VLD4DUPqWB_register_Asm_8 |
4071 | 1.35M | 1040U, // VLD4LNdAsm_16 |
4072 | 1.35M | 1040U, // VLD4LNdAsm_32 |
4073 | 1.35M | 1040U, // VLD4LNdAsm_8 |
4074 | 1.35M | 2064U, // VLD4LNdWB_fixed_Asm_16 |
4075 | 1.35M | 2064U, // VLD4LNdWB_fixed_Asm_32 |
4076 | 1.35M | 2064U, // VLD4LNdWB_fixed_Asm_8 |
4077 | 1.35M | 32784U, // VLD4LNdWB_register_Asm_16 |
4078 | 1.35M | 32784U, // VLD4LNdWB_register_Asm_32 |
4079 | 1.35M | 32784U, // VLD4LNdWB_register_Asm_8 |
4080 | 1.35M | 1040U, // VLD4LNqAsm_16 |
4081 | 1.35M | 1040U, // VLD4LNqAsm_32 |
4082 | 1.35M | 2064U, // VLD4LNqWB_fixed_Asm_16 |
4083 | 1.35M | 2064U, // VLD4LNqWB_fixed_Asm_32 |
4084 | 1.35M | 32784U, // VLD4LNqWB_register_Asm_16 |
4085 | 1.35M | 32784U, // VLD4LNqWB_register_Asm_32 |
4086 | 1.35M | 32U, // VLD4dAsm_16 |
4087 | 1.35M | 32U, // VLD4dAsm_32 |
4088 | 1.35M | 32U, // VLD4dAsm_8 |
4089 | 1.35M | 40U, // VLD4dWB_fixed_Asm_16 |
4090 | 1.35M | 40U, // VLD4dWB_fixed_Asm_32 |
4091 | 1.35M | 40U, // VLD4dWB_fixed_Asm_8 |
4092 | 1.35M | 68656U, // VLD4dWB_register_Asm_16 |
4093 | 1.35M | 68656U, // VLD4dWB_register_Asm_32 |
4094 | 1.35M | 68656U, // VLD4dWB_register_Asm_8 |
4095 | 1.35M | 0U, // VLD4qAsm_16 |
4096 | 1.35M | 0U, // VLD4qAsm_32 |
4097 | 1.35M | 0U, // VLD4qAsm_8 |
4098 | 1.35M | 0U, // VLD4qWB_fixed_Asm_16 |
4099 | 1.35M | 0U, // VLD4qWB_fixed_Asm_32 |
4100 | 1.35M | 0U, // VLD4qWB_fixed_Asm_8 |
4101 | 1.35M | 1048U, // VLD4qWB_register_Asm_16 |
4102 | 1.35M | 1048U, // VLD4qWB_register_Asm_32 |
4103 | 1.35M | 1048U, // VLD4qWB_register_Asm_8 |
4104 | 1.35M | 0U, // VMOVD0 |
4105 | 1.35M | 0U, // VMOVDcc |
4106 | 1.35M | 0U, // VMOVQ0 |
4107 | 1.35M | 0U, // VMOVScc |
4108 | 1.35M | 1040U, // VST1LNdAsm_16 |
4109 | 1.35M | 1040U, // VST1LNdAsm_32 |
4110 | 1.35M | 1040U, // VST1LNdAsm_8 |
4111 | 1.35M | 2064U, // VST1LNdWB_fixed_Asm_16 |
4112 | 1.35M | 2064U, // VST1LNdWB_fixed_Asm_32 |
4113 | 1.35M | 2064U, // VST1LNdWB_fixed_Asm_8 |
4114 | 1.35M | 32784U, // VST1LNdWB_register_Asm_16 |
4115 | 1.35M | 32784U, // VST1LNdWB_register_Asm_32 |
4116 | 1.35M | 32784U, // VST1LNdWB_register_Asm_8 |
4117 | 1.35M | 1040U, // VST2LNdAsm_16 |
4118 | 1.35M | 1040U, // VST2LNdAsm_32 |
4119 | 1.35M | 1040U, // VST2LNdAsm_8 |
4120 | 1.35M | 2064U, // VST2LNdWB_fixed_Asm_16 |
4121 | 1.35M | 2064U, // VST2LNdWB_fixed_Asm_32 |
4122 | 1.35M | 2064U, // VST2LNdWB_fixed_Asm_8 |
4123 | 1.35M | 32784U, // VST2LNdWB_register_Asm_16 |
4124 | 1.35M | 32784U, // VST2LNdWB_register_Asm_32 |
4125 | 1.35M | 32784U, // VST2LNdWB_register_Asm_8 |
4126 | 1.35M | 1040U, // VST2LNqAsm_16 |
4127 | 1.35M | 1040U, // VST2LNqAsm_32 |
4128 | 1.35M | 2064U, // VST2LNqWB_fixed_Asm_16 |
4129 | 1.35M | 2064U, // VST2LNqWB_fixed_Asm_32 |
4130 | 1.35M | 32784U, // VST2LNqWB_register_Asm_16 |
4131 | 1.35M | 32784U, // VST2LNqWB_register_Asm_32 |
4132 | 1.35M | 1040U, // VST3LNdAsm_16 |
4133 | 1.35M | 1040U, // VST3LNdAsm_32 |
4134 | 1.35M | 1040U, // VST3LNdAsm_8 |
4135 | 1.35M | 2064U, // VST3LNdWB_fixed_Asm_16 |
4136 | 1.35M | 2064U, // VST3LNdWB_fixed_Asm_32 |
4137 | 1.35M | 2064U, // VST3LNdWB_fixed_Asm_8 |
4138 | 1.35M | 32784U, // VST3LNdWB_register_Asm_16 |
4139 | 1.35M | 32784U, // VST3LNdWB_register_Asm_32 |
4140 | 1.35M | 32784U, // VST3LNdWB_register_Asm_8 |
4141 | 1.35M | 1040U, // VST3LNqAsm_16 |
4142 | 1.35M | 1040U, // VST3LNqAsm_32 |
4143 | 1.35M | 2064U, // VST3LNqWB_fixed_Asm_16 |
4144 | 1.35M | 2064U, // VST3LNqWB_fixed_Asm_32 |
4145 | 1.35M | 32784U, // VST3LNqWB_register_Asm_16 |
4146 | 1.35M | 32784U, // VST3LNqWB_register_Asm_32 |
4147 | 1.35M | 32U, // VST3dAsm_16 |
4148 | 1.35M | 32U, // VST3dAsm_32 |
4149 | 1.35M | 32U, // VST3dAsm_8 |
4150 | 1.35M | 40U, // VST3dWB_fixed_Asm_16 |
4151 | 1.35M | 40U, // VST3dWB_fixed_Asm_32 |
4152 | 1.35M | 40U, // VST3dWB_fixed_Asm_8 |
4153 | 1.35M | 68656U, // VST3dWB_register_Asm_16 |
4154 | 1.35M | 68656U, // VST3dWB_register_Asm_32 |
4155 | 1.35M | 68656U, // VST3dWB_register_Asm_8 |
4156 | 1.35M | 0U, // VST3qAsm_16 |
4157 | 1.35M | 0U, // VST3qAsm_32 |
4158 | 1.35M | 0U, // VST3qAsm_8 |
4159 | 1.35M | 0U, // VST3qWB_fixed_Asm_16 |
4160 | 1.35M | 0U, // VST3qWB_fixed_Asm_32 |
4161 | 1.35M | 0U, // VST3qWB_fixed_Asm_8 |
4162 | 1.35M | 1048U, // VST3qWB_register_Asm_16 |
4163 | 1.35M | 1048U, // VST3qWB_register_Asm_32 |
4164 | 1.35M | 1048U, // VST3qWB_register_Asm_8 |
4165 | 1.35M | 1040U, // VST4LNdAsm_16 |
4166 | 1.35M | 1040U, // VST4LNdAsm_32 |
4167 | 1.35M | 1040U, // VST4LNdAsm_8 |
4168 | 1.35M | 2064U, // VST4LNdWB_fixed_Asm_16 |
4169 | 1.35M | 2064U, // VST4LNdWB_fixed_Asm_32 |
4170 | 1.35M | 2064U, // VST4LNdWB_fixed_Asm_8 |
4171 | 1.35M | 32784U, // VST4LNdWB_register_Asm_16 |
4172 | 1.35M | 32784U, // VST4LNdWB_register_Asm_32 |
4173 | 1.35M | 32784U, // VST4LNdWB_register_Asm_8 |
4174 | 1.35M | 1040U, // VST4LNqAsm_16 |
4175 | 1.35M | 1040U, // VST4LNqAsm_32 |
4176 | 1.35M | 2064U, // VST4LNqWB_fixed_Asm_16 |
4177 | 1.35M | 2064U, // VST4LNqWB_fixed_Asm_32 |
4178 | 1.35M | 32784U, // VST4LNqWB_register_Asm_16 |
4179 | 1.35M | 32784U, // VST4LNqWB_register_Asm_32 |
4180 | 1.35M | 32U, // VST4dAsm_16 |
4181 | 1.35M | 32U, // VST4dAsm_32 |
4182 | 1.35M | 32U, // VST4dAsm_8 |
4183 | 1.35M | 40U, // VST4dWB_fixed_Asm_16 |
4184 | 1.35M | 40U, // VST4dWB_fixed_Asm_32 |
4185 | 1.35M | 40U, // VST4dWB_fixed_Asm_8 |
4186 | 1.35M | 68656U, // VST4dWB_register_Asm_16 |
4187 | 1.35M | 68656U, // VST4dWB_register_Asm_32 |
4188 | 1.35M | 68656U, // VST4dWB_register_Asm_8 |
4189 | 1.35M | 0U, // VST4qAsm_16 |
4190 | 1.35M | 0U, // VST4qAsm_32 |
4191 | 1.35M | 0U, // VST4qAsm_8 |
4192 | 1.35M | 0U, // VST4qWB_fixed_Asm_16 |
4193 | 1.35M | 0U, // VST4qWB_fixed_Asm_32 |
4194 | 1.35M | 0U, // VST4qWB_fixed_Asm_8 |
4195 | 1.35M | 1048U, // VST4qWB_register_Asm_16 |
4196 | 1.35M | 1048U, // VST4qWB_register_Asm_32 |
4197 | 1.35M | 1048U, // VST4qWB_register_Asm_8 |
4198 | 1.35M | 0U, // WIN__CHKSTK |
4199 | 1.35M | 0U, // WIN__DBZCHK |
4200 | 1.35M | 0U, // t2ABS |
4201 | 1.35M | 0U, // t2ADDSri |
4202 | 1.35M | 0U, // t2ADDSrr |
4203 | 1.35M | 0U, // t2ADDSrs |
4204 | 1.35M | 0U, // t2BR_JT |
4205 | 1.35M | 0U, // t2LDMIA_RET |
4206 | 1.35M | 1024U, // t2LDRBpcrel |
4207 | 1.35M | 1024U, // t2LDRConstPool |
4208 | 1.35M | 1024U, // t2LDRHpcrel |
4209 | 1.35M | 1024U, // t2LDRSBpcrel |
4210 | 1.35M | 1024U, // t2LDRSHpcrel |
4211 | 1.35M | 0U, // t2LDRpci_pic |
4212 | 1.35M | 1024U, // t2LDRpcrel |
4213 | 1.35M | 0U, // t2LEApcrel |
4214 | 1.35M | 0U, // t2LEApcrelJT |
4215 | 1.35M | 0U, // t2MOVCCasr |
4216 | 1.35M | 0U, // t2MOVCCi |
4217 | 1.35M | 0U, // t2MOVCCi16 |
4218 | 1.35M | 0U, // t2MOVCCi32imm |
4219 | 1.35M | 0U, // t2MOVCClsl |
4220 | 1.35M | 0U, // t2MOVCClsr |
4221 | 1.35M | 0U, // t2MOVCCr |
4222 | 1.35M | 0U, // t2MOVCCror |
4223 | 1.35M | 56U, // t2MOVSsi |
4224 | 1.35M | 64U, // t2MOVSsr |
4225 | 1.35M | 0U, // t2MOVTi16_ga_pcrel |
4226 | 1.35M | 0U, // t2MOV_ga_pcrel |
4227 | 1.35M | 0U, // t2MOVi16_ga_pcrel |
4228 | 1.35M | 0U, // t2MOVi32imm |
4229 | 1.35M | 56U, // t2MOVsi |
4230 | 1.35M | 64U, // t2MOVsr |
4231 | 1.35M | 0U, // t2MVNCCi |
4232 | 1.35M | 0U, // t2RSBSri |
4233 | 1.35M | 0U, // t2RSBSrs |
4234 | 1.35M | 0U, // t2STRB_preidx |
4235 | 1.35M | 0U, // t2STRH_preidx |
4236 | 1.35M | 0U, // t2STR_preidx |
4237 | 1.35M | 0U, // t2SUBSri |
4238 | 1.35M | 0U, // t2SUBSrr |
4239 | 1.35M | 0U, // t2SUBSrs |
4240 | 1.35M | 0U, // t2TBB_JT |
4241 | 1.35M | 0U, // t2TBH_JT |
4242 | 1.35M | 0U, // tADCS |
4243 | 1.35M | 0U, // tADDSi3 |
4244 | 1.35M | 0U, // tADDSi8 |
4245 | 1.35M | 0U, // tADDSrr |
4246 | 1.35M | 0U, // tADDframe |
4247 | 1.35M | 0U, // tADJCALLSTACKDOWN |
4248 | 1.35M | 0U, // tADJCALLSTACKUP |
4249 | 1.35M | 0U, // tBRIND |
4250 | 1.35M | 0U, // tBR_JTr |
4251 | 1.35M | 0U, // tBX_CALL |
4252 | 1.35M | 0U, // tBX_RET |
4253 | 1.35M | 0U, // tBX_RET_vararg |
4254 | 1.35M | 0U, // tBfar |
4255 | 1.35M | 0U, // tLDMIA_UPD |
4256 | 1.35M | 1024U, // tLDRConstPool |
4257 | 1.35M | 0U, // tLDRLIT_ga_abs |
4258 | 1.35M | 0U, // tLDRLIT_ga_pcrel |
4259 | 1.35M | 0U, // tLDR_postidx |
4260 | 1.35M | 0U, // tLDRpci_pic |
4261 | 1.35M | 0U, // tLEApcrel |
4262 | 1.35M | 0U, // tLEApcrelJT |
4263 | 1.35M | 0U, // tMOVCCr_pseudo |
4264 | 1.35M | 0U, // tPOP_RET |
4265 | 1.35M | 0U, // tSBCS |
4266 | 1.35M | 0U, // tSUBSi3 |
4267 | 1.35M | 0U, // tSUBSi8 |
4268 | 1.35M | 0U, // tSUBSrr |
4269 | 1.35M | 0U, // tTAILJMPd |
4270 | 1.35M | 0U, // tTAILJMPdND |
4271 | 1.35M | 0U, // tTAILJMPr |
4272 | 1.35M | 0U, // tTBB_JT |
4273 | 1.35M | 0U, // tTBH_JT |
4274 | 1.35M | 0U, // tTPsoft |
4275 | 1.35M | 98304U, // ADCri |
4276 | 1.35M | 0U, // ADCrr |
4277 | 1.35M | 131072U, // ADCrsi |
4278 | 1.35M | 0U, // ADCrsr |
4279 | 1.35M | 98304U, // ADDri |
4280 | 1.35M | 0U, // ADDrr |
4281 | 1.35M | 131072U, // ADDrsi |
4282 | 1.35M | 0U, // ADDrsr |
4283 | 1.35M | 72U, // ADR |
4284 | 1.35M | 0U, // AESD |
4285 | 1.35M | 0U, // AESE |
4286 | 1.35M | 0U, // AESIMC |
4287 | 1.35M | 0U, // AESMC |
4288 | 1.35M | 98304U, // ANDri |
4289 | 1.35M | 0U, // ANDrr |
4290 | 1.35M | 131072U, // ANDrsi |
4291 | 1.35M | 0U, // ANDrsr |
4292 | 1.35M | 80U, // BFC |
4293 | 1.35M | 163928U, // BFI |
4294 | 1.35M | 98304U, // BICri |
4295 | 1.35M | 0U, // BICrr |
4296 | 1.35M | 131072U, // BICrsi |
4297 | 1.35M | 0U, // BICrsr |
4298 | 1.35M | 0U, // BKPT |
4299 | 1.35M | 0U, // BL |
4300 | 1.35M | 0U, // BLX |
4301 | 1.35M | 0U, // BLX_pred |
4302 | 1.35M | 0U, // BLXi |
4303 | 1.35M | 0U, // BL_pred |
4304 | 1.35M | 0U, // BX |
4305 | 1.35M | 0U, // BXJ |
4306 | 1.35M | 0U, // BX_RET |
4307 | 1.35M | 0U, // BX_pred |
4308 | 1.35M | 0U, // Bcc |
4309 | 1.35M | 4145U, // CDP |
4310 | 1.35M | 0U, // CDP2 |
4311 | 1.35M | 0U, // CLREX |
4312 | 1.35M | 1024U, // CLZ |
4313 | 1.35M | 96U, // CMNri |
4314 | 1.35M | 1024U, // CMNzrr |
4315 | 1.35M | 104U, // CMNzrsi |
4316 | 1.35M | 64U, // CMNzrsr |
4317 | 1.35M | 96U, // CMPri |
4318 | 1.35M | 1024U, // CMPrr |
4319 | 1.35M | 104U, // CMPrsi |
4320 | 1.35M | 64U, // CMPrsr |
4321 | 1.35M | 0U, // CPS1p |
4322 | 1.35M | 0U, // CPS2p |
4323 | 1.35M | 1112U, // CPS3p |
4324 | 1.35M | 1112U, // CRC32B |
4325 | 1.35M | 1112U, // CRC32CB |
4326 | 1.35M | 1112U, // CRC32CH |
4327 | 1.35M | 1112U, // CRC32CW |
4328 | 1.35M | 1112U, // CRC32H |
4329 | 1.35M | 1112U, // CRC32W |
4330 | 1.35M | 0U, // DBG |
4331 | 1.35M | 0U, // DMB |
4332 | 1.35M | 0U, // DSB |
4333 | 1.35M | 98304U, // EORri |
4334 | 1.35M | 0U, // EORrr |
4335 | 1.35M | 131072U, // EORrsi |
4336 | 1.35M | 0U, // EORrsr |
4337 | 1.35M | 0U, // ERET |
4338 | 1.35M | 1U, // FCONSTD |
4339 | 1.35M | 1U, // FCONSTH |
4340 | 1.35M | 1U, // FCONSTS |
4341 | 1.35M | 33U, // FLDMXDB_UPD |
4342 | 1.35M | 1136U, // FLDMXIA |
4343 | 1.35M | 33U, // FLDMXIA_UPD |
4344 | 1.35M | 0U, // FMSTAT |
4345 | 1.35M | 33U, // FSTMXDB_UPD |
4346 | 1.35M | 1136U, // FSTMXIA |
4347 | 1.35M | 33U, // FSTMXIA_UPD |
4348 | 1.35M | 0U, // HINT |
4349 | 1.35M | 0U, // HLT |
4350 | 1.35M | 0U, // HVC |
4351 | 1.35M | 0U, // ISB |
4352 | 1.35M | 8U, // LDA |
4353 | 1.35M | 8U, // LDAB |
4354 | 1.35M | 8U, // LDAEX |
4355 | 1.35M | 8U, // LDAEXB |
4356 | 1.35M | 0U, // LDAEXD |
4357 | 1.35M | 8U, // LDAEXH |
4358 | 1.35M | 8U, // LDAH |
4359 | 1.35M | 0U, // LDC2L_OFFSET |
4360 | 1.35M | 1U, // LDC2L_OPTION |
4361 | 1.35M | 2U, // LDC2L_POST |
4362 | 1.35M | 0U, // LDC2L_PRE |
4363 | 1.35M | 0U, // LDC2_OFFSET |
4364 | 1.35M | 1U, // LDC2_OPTION |
4365 | 1.35M | 2U, // LDC2_POST |
4366 | 1.35M | 0U, // LDC2_PRE |
4367 | 1.35M | 122U, // LDCL_OFFSET |
4368 | 1.35M | 196738U, // LDCL_OPTION |
4369 | 1.35M | 229506U, // LDCL_POST |
4370 | 1.35M | 138U, // LDCL_PRE |
4371 | 1.35M | 122U, // LDC_OFFSET |
4372 | 1.35M | 196738U, // LDC_OPTION |
4373 | 1.35M | 229506U, // LDC_POST |
4374 | 1.35M | 138U, // LDC_PRE |
4375 | 1.35M | 1136U, // LDMDA |
4376 | 1.35M | 33U, // LDMDA_UPD |
4377 | 1.35M | 1136U, // LDMDB |
4378 | 1.35M | 33U, // LDMDB_UPD |
4379 | 1.35M | 1136U, // LDMIA |
4380 | 1.35M | 33U, // LDMIA_UPD |
4381 | 1.35M | 1136U, // LDMIB |
4382 | 1.35M | 33U, // LDMIB_UPD |
4383 | 1.35M | 262272U, // LDRBT_POST_IMM |
4384 | 1.35M | 262272U, // LDRBT_POST_REG |
4385 | 1.35M | 262272U, // LDRB_POST_IMM |
4386 | 1.35M | 262272U, // LDRB_POST_REG |
4387 | 1.35M | 144U, // LDRB_PRE_IMM |
4388 | 1.35M | 152U, // LDRB_PRE_REG |
4389 | 1.35M | 160U, // LDRBi12 |
4390 | 1.35M | 168U, // LDRBrs |
4391 | 1.35M | 294912U, // LDRD |
4392 | 1.35M | 2424832U, // LDRD_POST |
4393 | 1.35M | 360448U, // LDRD_PRE |
4394 | 1.35M | 8U, // LDREX |
4395 | 1.35M | 8U, // LDREXB |
4396 | 1.35M | 0U, // LDREXD |
4397 | 1.35M | 8U, // LDREXH |
4398 | 1.35M | 176U, // LDRH |
4399 | 1.35M | 393344U, // LDRHTi |
4400 | 1.35M | 426112U, // LDRHTr |
4401 | 1.35M | 458880U, // LDRH_POST |
4402 | 1.35M | 184U, // LDRH_PRE |
4403 | 1.35M | 176U, // LDRSB |
4404 | 1.35M | 393344U, // LDRSBTi |
4405 | 1.35M | 426112U, // LDRSBTr |
4406 | 1.35M | 458880U, // LDRSB_POST |
4407 | 1.35M | 184U, // LDRSB_PRE |
4408 | 1.35M | 176U, // LDRSH |
4409 | 1.35M | 393344U, // LDRSHTi |
4410 | 1.35M | 426112U, // LDRSHTr |
4411 | 1.35M | 458880U, // LDRSH_POST |
4412 | 1.35M | 184U, // LDRSH_PRE |
4413 | 1.35M | 262272U, // LDRT_POST_IMM |
4414 | 1.35M | 262272U, // LDRT_POST_REG |
4415 | 1.35M | 262272U, // LDR_POST_IMM |
4416 | 1.35M | 262272U, // LDR_POST_REG |
4417 | 1.35M | 144U, // LDR_PRE_IMM |
4418 | 1.35M | 152U, // LDR_PRE_REG |
4419 | 1.35M | 160U, // LDRcp |
4420 | 1.35M | 160U, // LDRi12 |
4421 | 1.35M | 168U, // LDRrs |
4422 | 1.35M | 4690993U, // MCR |
4423 | 1.35M | 192U, // MCR2 |
4424 | 1.35M | 6788145U, // MCRR |
4425 | 1.35M | 524312U, // MCRR2 |
4426 | 1.35M | 35651584U, // MLA |
4427 | 1.35M | 35651584U, // MLS |
4428 | 1.35M | 0U, // MOVPCLR |
4429 | 1.35M | 1112U, // MOVTi16 |
4430 | 1.35M | 96U, // MOVi |
4431 | 1.35M | 1024U, // MOVi16 |
4432 | 1.35M | 1024U, // MOVr |
4433 | 1.35M | 1024U, // MOVr_TC |
4434 | 1.35M | 104U, // MOVsi |
4435 | 1.35M | 64U, // MOVsr |
4436 | 1.35M | 0U, // MRC |
4437 | 1.35M | 0U, // MRC2 |
4438 | 1.35M | 0U, // MRRC |
4439 | 1.35M | 0U, // MRRC2 |
4440 | 1.35M | 2U, // MRS |
4441 | 1.35M | 200U, // MRSbanked |
4442 | 1.35M | 2U, // MRSsys |
4443 | 1.35M | 33U, // MSR |
4444 | 1.35M | 0U, // MSRbanked |
4445 | 1.35M | 3U, // MSRi |
4446 | 1.35M | 0U, // MUL |
4447 | 1.35M | 96U, // MVNi |
4448 | 1.35M | 1024U, // MVNr |
4449 | 1.35M | 104U, // MVNsi |
4450 | 1.35M | 64U, // MVNsr |
4451 | 1.35M | 98304U, // ORRri |
4452 | 1.35M | 0U, // ORRrr |
4453 | 1.35M | 131072U, // ORRrsi |
4454 | 1.35M | 0U, // ORRrsr |
4455 | 1.35M | 8388608U, // PKHBT |
4456 | 1.35M | 10485760U, // PKHTB |
4457 | 1.35M | 0U, // PLDWi12 |
4458 | 1.35M | 0U, // PLDWrs |
4459 | 1.35M | 0U, // PLDi12 |
4460 | 1.35M | 0U, // PLDrs |
4461 | 1.35M | 0U, // PLIi12 |
4462 | 1.35M | 0U, // PLIrs |
4463 | 1.35M | 0U, // QADD |
4464 | 1.35M | 0U, // QADD16 |
4465 | 1.35M | 0U, // QADD8 |
4466 | 1.35M | 0U, // QASX |
4467 | 1.35M | 0U, // QDADD |
4468 | 1.35M | 0U, // QDSUB |
4469 | 1.35M | 0U, // QSAX |
4470 | 1.35M | 0U, // QSUB |
4471 | 1.35M | 0U, // QSUB16 |
4472 | 1.35M | 0U, // QSUB8 |
4473 | 1.35M | 1024U, // RBIT |
4474 | 1.35M | 1024U, // REV |
4475 | 1.35M | 1024U, // REV16 |
4476 | 1.35M | 1024U, // REVSH |
4477 | 1.35M | 0U, // RFEDA |
4478 | 1.35M | 0U, // RFEDA_UPD |
4479 | 1.35M | 0U, // RFEDB |
4480 | 1.35M | 0U, // RFEDB_UPD |
4481 | 1.35M | 0U, // RFEIA |
4482 | 1.35M | 0U, // RFEIA_UPD |
4483 | 1.35M | 0U, // RFEIB |
4484 | 1.35M | 0U, // RFEIB_UPD |
4485 | 1.35M | 98304U, // RSBri |
4486 | 1.35M | 0U, // RSBrr |
4487 | 1.35M | 131072U, // RSBrsi |
4488 | 1.35M | 0U, // RSBrsr |
4489 | 1.35M | 98304U, // RSCri |
4490 | 1.35M | 0U, // RSCrr |
4491 | 1.35M | 131072U, // RSCrsi |
4492 | 1.35M | 0U, // RSCrsr |
4493 | 1.35M | 0U, // SADD16 |
4494 | 1.35M | 0U, // SADD8 |
4495 | 1.35M | 0U, // SASX |
4496 | 1.35M | 98304U, // SBCri |
4497 | 1.35M | 0U, // SBCrr |
4498 | 1.35M | 131072U, // SBCrsi |
4499 | 1.35M | 0U, // SBCrsr |
4500 | 1.35M | 69206016U, // SBFX |
4501 | 1.35M | 0U, // SDIV |
4502 | 1.35M | 0U, // SEL |
4503 | 1.35M | 0U, // SETEND |
4504 | 1.35M | 0U, // SETPAN |
4505 | 1.35M | 1048U, // SHA1C |
4506 | 1.35M | 0U, // SHA1H |
4507 | 1.35M | 1048U, // SHA1M |
4508 | 1.35M | 1048U, // SHA1P |
4509 | 1.35M | 1048U, // SHA1SU0 |
4510 | 1.35M | 0U, // SHA1SU1 |
4511 | 1.35M | 1048U, // SHA256H |
4512 | 1.35M | 1048U, // SHA256H2 |
4513 | 1.35M | 0U, // SHA256SU0 |
4514 | 1.35M | 1048U, // SHA256SU1 |
4515 | 1.35M | 0U, // SHADD16 |
4516 | 1.35M | 0U, // SHADD8 |
4517 | 1.35M | 0U, // SHASX |
4518 | 1.35M | 0U, // SHSAX |
4519 | 1.35M | 0U, // SHSUB16 |
4520 | 1.35M | 0U, // SHSUB8 |
4521 | 1.35M | 0U, // SMC |
4522 | 1.35M | 35651584U, // SMLABB |
4523 | 1.35M | 35651584U, // SMLABT |
4524 | 1.35M | 35651584U, // SMLAD |
4525 | 1.35M | 35651584U, // SMLADX |
4526 | 1.35M | 0U, // SMLAL |
4527 | 1.35M | 35651584U, // SMLALBB |
4528 | 1.35M | 35651584U, // SMLALBT |
4529 | 1.35M | 35651584U, // SMLALD |
4530 | 1.35M | 35651584U, // SMLALDX |
4531 | 1.35M | 35651584U, // SMLALTB |
4532 | 1.35M | 35651584U, // SMLALTT |
4533 | 1.35M | 35651584U, // SMLATB |
4534 | 1.35M | 35651584U, // SMLATT |
4535 | 1.35M | 35651584U, // SMLAWB |
4536 | 1.35M | 35651584U, // SMLAWT |
4537 | 1.35M | 35651584U, // SMLSD |
4538 | 1.35M | 35651584U, // SMLSDX |
4539 | 1.35M | 35651584U, // SMLSLD |
4540 | 1.35M | 35651584U, // SMLSLDX |
4541 | 1.35M | 35651584U, // SMMLA |
4542 | 1.35M | 35651584U, // SMMLAR |
4543 | 1.35M | 35651584U, // SMMLS |
4544 | 1.35M | 35651584U, // SMMLSR |
4545 | 1.35M | 0U, // SMMUL |
4546 | 1.35M | 0U, // SMMULR |
4547 | 1.35M | 0U, // SMUAD |
4548 | 1.35M | 0U, // SMUADX |
4549 | 1.35M | 0U, // SMULBB |
4550 | 1.35M | 0U, // SMULBT |
4551 | 1.35M | 35651584U, // SMULL |
4552 | 1.35M | 0U, // SMULTB |
4553 | 1.35M | 0U, // SMULTT |
4554 | 1.35M | 0U, // SMULWB |
4555 | 1.35M | 0U, // SMULWT |
4556 | 1.35M | 0U, // SMUSD |
4557 | 1.35M | 0U, // SMUSDX |
4558 | 1.35M | 0U, // SRSDA |
4559 | 1.35M | 0U, // SRSDA_UPD |
4560 | 1.35M | 0U, // SRSDB |
4561 | 1.35M | 0U, // SRSDB_UPD |
4562 | 1.35M | 0U, // SRSIA |
4563 | 1.35M | 0U, // SRSIA_UPD |
4564 | 1.35M | 0U, // SRSIB |
4565 | 1.35M | 0U, // SRSIB_UPD |
4566 | 1.35M | 6352U, // SSAT |
4567 | 1.35M | 1232U, // SSAT16 |
4568 | 1.35M | 0U, // SSAX |
4569 | 1.35M | 0U, // SSUB16 |
4570 | 1.35M | 0U, // SSUB8 |
4571 | 1.35M | 0U, // STC2L_OFFSET |
4572 | 1.35M | 1U, // STC2L_OPTION |
4573 | 1.35M | 2U, // STC2L_POST |
4574 | 1.35M | 0U, // STC2L_PRE |
4575 | 1.35M | 0U, // STC2_OFFSET |
4576 | 1.35M | 1U, // STC2_OPTION |
4577 | 1.35M | 2U, // STC2_POST |
4578 | 1.35M | 0U, // STC2_PRE |
4579 | 1.35M | 122U, // STCL_OFFSET |
4580 | 1.35M | 196738U, // STCL_OPTION |
4581 | 1.35M | 229506U, // STCL_POST |
4582 | 1.35M | 138U, // STCL_PRE |
4583 | 1.35M | 122U, // STC_OFFSET |
4584 | 1.35M | 196738U, // STC_OPTION |
4585 | 1.35M | 229506U, // STC_POST |
4586 | 1.35M | 138U, // STC_PRE |
4587 | 1.35M | 8U, // STL |
4588 | 1.35M | 8U, // STLB |
4589 | 1.35M | 557056U, // STLEX |
4590 | 1.35M | 557056U, // STLEXB |
4591 | 1.35M | 216U, // STLEXD |
4592 | 1.35M | 557056U, // STLEXH |
4593 | 1.35M | 8U, // STLH |
4594 | 1.35M | 1136U, // STMDA |
4595 | 1.35M | 33U, // STMDA_UPD |
4596 | 1.35M | 1136U, // STMDB |
4597 | 1.35M | 33U, // STMDB_UPD |
4598 | 1.35M | 1136U, // STMIA |
4599 | 1.35M | 33U, // STMIA_UPD |
4600 | 1.35M | 1136U, // STMIB |
4601 | 1.35M | 33U, // STMIB_UPD |
4602 | 1.35M | 262272U, // STRBT_POST_IMM |
4603 | 1.35M | 262272U, // STRBT_POST_REG |
4604 | 1.35M | 262272U, // STRB_POST_IMM |
4605 | 1.35M | 262272U, // STRB_POST_REG |
4606 | 1.35M | 144U, // STRB_PRE_IMM |
4607 | 1.35M | 152U, // STRB_PRE_REG |
4608 | 1.35M | 160U, // STRBi12 |
4609 | 1.35M | 168U, // STRBrs |
4610 | 1.35M | 294912U, // STRD |
4611 | 1.35M | 2424920U, // STRD_POST |
4612 | 1.35M | 360536U, // STRD_PRE |
4613 | 1.35M | 557056U, // STREX |
4614 | 1.35M | 557056U, // STREXB |
4615 | 1.35M | 216U, // STREXD |
4616 | 1.35M | 557056U, // STREXH |
4617 | 1.35M | 176U, // STRH |
4618 | 1.35M | 393344U, // STRHTi |
4619 | 1.35M | 426112U, // STRHTr |
4620 | 1.35M | 458880U, // STRH_POST |
4621 | 1.35M | 184U, // STRH_PRE |
4622 | 1.35M | 262272U, // STRT_POST_IMM |
4623 | 1.35M | 262272U, // STRT_POST_REG |
4624 | 1.35M | 262272U, // STR_POST_IMM |
4625 | 1.35M | 262272U, // STR_POST_REG |
4626 | 1.35M | 144U, // STR_PRE_IMM |
4627 | 1.35M | 152U, // STR_PRE_REG |
4628 | 1.35M | 160U, // STRi12 |
4629 | 1.35M | 168U, // STRrs |
4630 | 1.35M | 98304U, // SUBri |
4631 | 1.35M | 0U, // SUBrr |
4632 | 1.35M | 131072U, // SUBrsi |
4633 | 1.35M | 0U, // SUBrsr |
4634 | 1.35M | 0U, // SVC |
4635 | 1.35M | 557056U, // SWP |
4636 | 1.35M | 557056U, // SWPB |
4637 | 1.35M | 12582912U, // SXTAB |
4638 | 1.35M | 12582912U, // SXTAB16 |
4639 | 1.35M | 12582912U, // SXTAH |
4640 | 1.35M | 7168U, // SXTB |
4641 | 1.35M | 7168U, // SXTB16 |
4642 | 1.35M | 7168U, // SXTH |
4643 | 1.35M | 96U, // TEQri |
4644 | 1.35M | 1024U, // TEQrr |
4645 | 1.35M | 104U, // TEQrsi |
4646 | 1.35M | 64U, // TEQrsr |
4647 | 1.35M | 0U, // TRAP |
4648 | 1.35M | 0U, // TRAPNaCl |
4649 | 1.35M | 0U, // TSB |
4650 | 1.35M | 96U, // TSTri |
4651 | 1.35M | 1024U, // TSTrr |
4652 | 1.35M | 104U, // TSTrsi |
4653 | 1.35M | 64U, // TSTrsr |
4654 | 1.35M | 0U, // UADD16 |
4655 | 1.35M | 0U, // UADD8 |
4656 | 1.35M | 0U, // UASX |
4657 | 1.35M | 69206016U, // UBFX |
4658 | 1.35M | 0U, // UDF |
4659 | 1.35M | 0U, // UDIV |
4660 | 1.35M | 0U, // UHADD16 |
4661 | 1.35M | 0U, // UHADD8 |
4662 | 1.35M | 0U, // UHASX |
4663 | 1.35M | 0U, // UHSAX |
4664 | 1.35M | 0U, // UHSUB16 |
4665 | 1.35M | 0U, // UHSUB8 |
4666 | 1.35M | 35651584U, // UMAAL |
4667 | 1.35M | 0U, // UMLAL |
4668 | 1.35M | 35651584U, // UMULL |
4669 | 1.35M | 0U, // UQADD16 |
4670 | 1.35M | 0U, // UQADD8 |
4671 | 1.35M | 0U, // UQASX |
4672 | 1.35M | 0U, // UQSAX |
4673 | 1.35M | 0U, // UQSUB16 |
4674 | 1.35M | 0U, // UQSUB8 |
4675 | 1.35M | 0U, // USAD8 |
4676 | 1.35M | 35651584U, // USADA8 |
4677 | 1.35M | 14680064U, // USAT |
4678 | 1.35M | 0U, // USAT16 |
4679 | 1.35M | 0U, // USAX |
4680 | 1.35M | 0U, // USUB16 |
4681 | 1.35M | 0U, // USUB8 |
4682 | 1.35M | 12582912U, // UXTAB |
4683 | 1.35M | 12582912U, // UXTAB16 |
4684 | 1.35M | 12582912U, // UXTAH |
4685 | 1.35M | 7168U, // UXTB |
4686 | 1.35M | 7168U, // UXTB16 |
4687 | 1.35M | 7168U, // UXTH |
4688 | 1.35M | 1048U, // VABALsv2i64 |
4689 | 1.35M | 1048U, // VABALsv4i32 |
4690 | 1.35M | 1048U, // VABALsv8i16 |
4691 | 1.35M | 1048U, // VABALuv2i64 |
4692 | 1.35M | 1048U, // VABALuv4i32 |
4693 | 1.35M | 1048U, // VABALuv8i16 |
4694 | 1.35M | 1048U, // VABAsv16i8 |
4695 | 1.35M | 1048U, // VABAsv2i32 |
4696 | 1.35M | 1048U, // VABAsv4i16 |
4697 | 1.35M | 1048U, // VABAsv4i32 |
4698 | 1.35M | 1048U, // VABAsv8i16 |
4699 | 1.35M | 1048U, // VABAsv8i8 |
4700 | 1.35M | 1048U, // VABAuv16i8 |
4701 | 1.35M | 1048U, // VABAuv2i32 |
4702 | 1.35M | 1048U, // VABAuv4i16 |
4703 | 1.35M | 1048U, // VABAuv4i32 |
4704 | 1.35M | 1048U, // VABAuv8i16 |
4705 | 1.35M | 1048U, // VABAuv8i8 |
4706 | 1.35M | 1112U, // VABDLsv2i64 |
4707 | 1.35M | 1112U, // VABDLsv4i32 |
4708 | 1.35M | 1112U, // VABDLsv8i16 |
4709 | 1.35M | 1112U, // VABDLuv2i64 |
4710 | 1.35M | 1112U, // VABDLuv4i32 |
4711 | 1.35M | 1112U, // VABDLuv8i16 |
4712 | 1.35M | 70705U, // VABDfd |
4713 | 1.35M | 70705U, // VABDfq |
4714 | 1.35M | 70705U, // VABDhd |
4715 | 1.35M | 70705U, // VABDhq |
4716 | 1.35M | 1112U, // VABDsv16i8 |
4717 | 1.35M | 1112U, // VABDsv2i32 |
4718 | 1.35M | 1112U, // VABDsv4i16 |
4719 | 1.35M | 1112U, // VABDsv4i32 |
4720 | 1.35M | 1112U, // VABDsv8i16 |
4721 | 1.35M | 1112U, // VABDsv8i8 |
4722 | 1.35M | 1112U, // VABDuv16i8 |
4723 | 1.35M | 1112U, // VABDuv2i32 |
4724 | 1.35M | 1112U, // VABDuv4i16 |
4725 | 1.35M | 1112U, // VABDuv4i32 |
4726 | 1.35M | 1112U, // VABDuv8i16 |
4727 | 1.35M | 1112U, // VABDuv8i8 |
4728 | 1.35M | 33U, // VABSD |
4729 | 1.35M | 33U, // VABSH |
4730 | 1.35M | 33U, // VABSS |
4731 | 1.35M | 33U, // VABSfd |
4732 | 1.35M | 33U, // VABSfq |
4733 | 1.35M | 33U, // VABShd |
4734 | 1.35M | 33U, // VABShq |
4735 | 1.35M | 0U, // VABSv16i8 |
4736 | 1.35M | 0U, // VABSv2i32 |
4737 | 1.35M | 0U, // VABSv4i16 |
4738 | 1.35M | 0U, // VABSv4i32 |
4739 | 1.35M | 0U, // VABSv8i16 |
4740 | 1.35M | 0U, // VABSv8i8 |
4741 | 1.35M | 70705U, // VACGEfd |
4742 | 1.35M | 70705U, // VACGEfq |
4743 | 1.35M | 70705U, // VACGEhd |
4744 | 1.35M | 70705U, // VACGEhq |
4745 | 1.35M | 70705U, // VACGTfd |
4746 | 1.35M | 70705U, // VACGTfq |
4747 | 1.35M | 70705U, // VACGThd |
4748 | 1.35M | 70705U, // VACGThq |
4749 | 1.35M | 70705U, // VADDD |
4750 | 1.35M | 70705U, // VADDH |
4751 | 1.35M | 1112U, // VADDHNv2i32 |
4752 | 1.35M | 1112U, // VADDHNv4i16 |
4753 | 1.35M | 1112U, // VADDHNv8i8 |
4754 | 1.35M | 1112U, // VADDLsv2i64 |
4755 | 1.35M | 1112U, // VADDLsv4i32 |
4756 | 1.35M | 1112U, // VADDLsv8i16 |
4757 | 1.35M | 1112U, // VADDLuv2i64 |
4758 | 1.35M | 1112U, // VADDLuv4i32 |
4759 | 1.35M | 1112U, // VADDLuv8i16 |
4760 | 1.35M | 70705U, // VADDS |
4761 | 1.35M | 1112U, // VADDWsv2i64 |
4762 | 1.35M | 1112U, // VADDWsv4i32 |
4763 | 1.35M | 1112U, // VADDWsv8i16 |
4764 | 1.35M | 1112U, // VADDWuv2i64 |
4765 | 1.35M | 1112U, // VADDWuv4i32 |
4766 | 1.35M | 1112U, // VADDWuv8i16 |
4767 | 1.35M | 70705U, // VADDfd |
4768 | 1.35M | 70705U, // VADDfq |
4769 | 1.35M | 70705U, // VADDhd |
4770 | 1.35M | 70705U, // VADDhq |
4771 | 1.35M | 1112U, // VADDv16i8 |
4772 | 1.35M | 1112U, // VADDv1i64 |
4773 | 1.35M | 1112U, // VADDv2i32 |
4774 | 1.35M | 1112U, // VADDv2i64 |
4775 | 1.35M | 1112U, // VADDv4i16 |
4776 | 1.35M | 1112U, // VADDv4i32 |
4777 | 1.35M | 1112U, // VADDv8i16 |
4778 | 1.35M | 1112U, // VADDv8i8 |
4779 | 1.35M | 0U, // VANDd |
4780 | 1.35M | 0U, // VANDq |
4781 | 1.35M | 0U, // VBICd |
4782 | 1.35M | 0U, // VBICiv2i32 |
4783 | 1.35M | 0U, // VBICiv4i16 |
4784 | 1.35M | 0U, // VBICiv4i32 |
4785 | 1.35M | 0U, // VBICiv8i16 |
4786 | 1.35M | 0U, // VBICq |
4787 | 1.35M | 589912U, // VBIFd |
4788 | 1.35M | 589912U, // VBIFq |
4789 | 1.35M | 589912U, // VBITd |
4790 | 1.35M | 589912U, // VBITq |
4791 | 1.35M | 589912U, // VBSLd |
4792 | 1.35M | 589912U, // VBSLq |
4793 | 1.35M | 622680U, // VCADDv2f32 |
4794 | 1.35M | 622680U, // VCADDv4f16 |
4795 | 1.35M | 622680U, // VCADDv4f32 |
4796 | 1.35M | 622680U, // VCADDv8f16 |
4797 | 1.35M | 70705U, // VCEQfd |
4798 | 1.35M | 70705U, // VCEQfq |
4799 | 1.35M | 70705U, // VCEQhd |
4800 | 1.35M | 70705U, // VCEQhq |
4801 | 1.35M | 1112U, // VCEQv16i8 |
4802 | 1.35M | 1112U, // VCEQv2i32 |
4803 | 1.35M | 1112U, // VCEQv4i16 |
4804 | 1.35M | 1112U, // VCEQv4i32 |
4805 | 1.35M | 1112U, // VCEQv8i16 |
4806 | 1.35M | 1112U, // VCEQv8i8 |
4807 | 1.35M | 3U, // VCEQzv16i8 |
4808 | 1.35M | 225U, // VCEQzv2f32 |
4809 | 1.35M | 3U, // VCEQzv2i32 |
4810 | 1.35M | 225U, // VCEQzv4f16 |
4811 | 1.35M | 225U, // VCEQzv4f32 |
4812 | 1.35M | 3U, // VCEQzv4i16 |
4813 | 1.35M | 3U, // VCEQzv4i32 |
4814 | 1.35M | 225U, // VCEQzv8f16 |
4815 | 1.35M | 3U, // VCEQzv8i16 |
4816 | 1.35M | 3U, // VCEQzv8i8 |
4817 | 1.35M | 70705U, // VCGEfd |
4818 | 1.35M | 70705U, // VCGEfq |
4819 | 1.35M | 70705U, // VCGEhd |
4820 | 1.35M | 70705U, // VCGEhq |
4821 | 1.35M | 1112U, // VCGEsv16i8 |
4822 | 1.35M | 1112U, // VCGEsv2i32 |
4823 | 1.35M | 1112U, // VCGEsv4i16 |
4824 | 1.35M | 1112U, // VCGEsv4i32 |
4825 | 1.35M | 1112U, // VCGEsv8i16 |
4826 | 1.35M | 1112U, // VCGEsv8i8 |
4827 | 1.35M | 1112U, // VCGEuv16i8 |
4828 | 1.35M | 1112U, // VCGEuv2i32 |
4829 | 1.35M | 1112U, // VCGEuv4i16 |
4830 | 1.35M | 1112U, // VCGEuv4i32 |
4831 | 1.35M | 1112U, // VCGEuv8i16 |
4832 | 1.35M | 1112U, // VCGEuv8i8 |
4833 | 1.35M | 3U, // VCGEzv16i8 |
4834 | 1.35M | 225U, // VCGEzv2f32 |
4835 | 1.35M | 3U, // VCGEzv2i32 |
4836 | 1.35M | 225U, // VCGEzv4f16 |
4837 | 1.35M | 225U, // VCGEzv4f32 |
4838 | 1.35M | 3U, // VCGEzv4i16 |
4839 | 1.35M | 3U, // VCGEzv4i32 |
4840 | 1.35M | 225U, // VCGEzv8f16 |
4841 | 1.35M | 3U, // VCGEzv8i16 |
4842 | 1.35M | 3U, // VCGEzv8i8 |
4843 | 1.35M | 70705U, // VCGTfd |
4844 | 1.35M | 70705U, // VCGTfq |
4845 | 1.35M | 70705U, // VCGThd |
4846 | 1.35M | 70705U, // VCGThq |
4847 | 1.35M | 1112U, // VCGTsv16i8 |
4848 | 1.35M | 1112U, // VCGTsv2i32 |
4849 | 1.35M | 1112U, // VCGTsv4i16 |
4850 | 1.35M | 1112U, // VCGTsv4i32 |
4851 | 1.35M | 1112U, // VCGTsv8i16 |
4852 | 1.35M | 1112U, // VCGTsv8i8 |
4853 | 1.35M | 1112U, // VCGTuv16i8 |
4854 | 1.35M | 1112U, // VCGTuv2i32 |
4855 | 1.35M | 1112U, // VCGTuv4i16 |
4856 | 1.35M | 1112U, // VCGTuv4i32 |
4857 | 1.35M | 1112U, // VCGTuv8i16 |
4858 | 1.35M | 1112U, // VCGTuv8i8 |
4859 | 1.35M | 3U, // VCGTzv16i8 |
4860 | 1.35M | 225U, // VCGTzv2f32 |
4861 | 1.35M | 3U, // VCGTzv2i32 |
4862 | 1.35M | 225U, // VCGTzv4f16 |
4863 | 1.35M | 225U, // VCGTzv4f32 |
4864 | 1.35M | 3U, // VCGTzv4i16 |
4865 | 1.35M | 3U, // VCGTzv4i32 |
4866 | 1.35M | 225U, // VCGTzv8f16 |
4867 | 1.35M | 3U, // VCGTzv8i16 |
4868 | 1.35M | 3U, // VCGTzv8i8 |
4869 | 1.35M | 3U, // VCLEzv16i8 |
4870 | 1.35M | 225U, // VCLEzv2f32 |
4871 | 1.35M | 3U, // VCLEzv2i32 |
4872 | 1.35M | 225U, // VCLEzv4f16 |
4873 | 1.35M | 225U, // VCLEzv4f32 |
4874 | 1.35M | 3U, // VCLEzv4i16 |
4875 | 1.35M | 3U, // VCLEzv4i32 |
4876 | 1.35M | 225U, // VCLEzv8f16 |
4877 | 1.35M | 3U, // VCLEzv8i16 |
4878 | 1.35M | 3U, // VCLEzv8i8 |
4879 | 1.35M | 0U, // VCLSv16i8 |
4880 | 1.35M | 0U, // VCLSv2i32 |
4881 | 1.35M | 0U, // VCLSv4i16 |
4882 | 1.35M | 0U, // VCLSv4i32 |
4883 | 1.35M | 0U, // VCLSv8i16 |
4884 | 1.35M | 0U, // VCLSv8i8 |
4885 | 1.35M | 3U, // VCLTzv16i8 |
4886 | 1.35M | 225U, // VCLTzv2f32 |
4887 | 1.35M | 3U, // VCLTzv2i32 |
4888 | 1.35M | 225U, // VCLTzv4f16 |
4889 | 1.35M | 225U, // VCLTzv4f32 |
4890 | 1.35M | 3U, // VCLTzv4i16 |
4891 | 1.35M | 3U, // VCLTzv4i32 |
4892 | 1.35M | 225U, // VCLTzv8f16 |
4893 | 1.35M | 3U, // VCLTzv8i16 |
4894 | 1.35M | 3U, // VCLTzv8i8 |
4895 | 1.35M | 0U, // VCLZv16i8 |
4896 | 1.35M | 0U, // VCLZv2i32 |
4897 | 1.35M | 0U, // VCLZv4i16 |
4898 | 1.35M | 0U, // VCLZv4i32 |
4899 | 1.35M | 0U, // VCLZv8i16 |
4900 | 1.35M | 0U, // VCLZv8i8 |
4901 | 1.35M | 655384U, // VCMLAv2f32 |
4902 | 1.35M | 17276952U, // VCMLAv2f32_indexed |
4903 | 1.35M | 655384U, // VCMLAv4f16 |
4904 | 1.35M | 17276952U, // VCMLAv4f16_indexed |
4905 | 1.35M | 655384U, // VCMLAv4f32 |
4906 | 1.35M | 17276952U, // VCMLAv4f32_indexed |
4907 | 1.35M | 655384U, // VCMLAv8f16 |
4908 | 1.35M | 17276952U, // VCMLAv8f16_indexed |
4909 | 1.35M | 33U, // VCMPD |
4910 | 1.35M | 33U, // VCMPED |
4911 | 1.35M | 33U, // VCMPEH |
4912 | 1.35M | 33U, // VCMPES |
4913 | 1.35M | 0U, // VCMPEZD |
4914 | 1.35M | 0U, // VCMPEZH |
4915 | 1.35M | 0U, // VCMPEZS |
4916 | 1.35M | 33U, // VCMPH |
4917 | 1.35M | 33U, // VCMPS |
4918 | 1.35M | 0U, // VCMPZD |
4919 | 1.35M | 0U, // VCMPZH |
4920 | 1.35M | 0U, // VCMPZS |
4921 | 1.35M | 1024U, // VCNTd |
4922 | 1.35M | 1024U, // VCNTq |
4923 | 1.35M | 0U, // VCVTANSDf |
4924 | 1.35M | 0U, // VCVTANSDh |
4925 | 1.35M | 0U, // VCVTANSQf |
4926 | 1.35M | 0U, // VCVTANSQh |
4927 | 1.35M | 0U, // VCVTANUDf |
4928 | 1.35M | 0U, // VCVTANUDh |
4929 | 1.35M | 0U, // VCVTANUQf |
4930 | 1.35M | 0U, // VCVTANUQh |
4931 | 1.35M | 0U, // VCVTASD |
4932 | 1.35M | 0U, // VCVTASH |
4933 | 1.35M | 0U, // VCVTASS |
4934 | 1.35M | 0U, // VCVTAUD |
4935 | 1.35M | 0U, // VCVTAUH |
4936 | 1.35M | 0U, // VCVTAUS |
4937 | 1.35M | 0U, // VCVTBDH |
4938 | 1.35M | 0U, // VCVTBHD |
4939 | 1.35M | 0U, // VCVTBHS |
4940 | 1.35M | 0U, // VCVTBSH |
4941 | 1.35M | 0U, // VCVTDS |
4942 | 1.35M | 0U, // VCVTMNSDf |
4943 | 1.35M | 0U, // VCVTMNSDh |
4944 | 1.35M | 0U, // VCVTMNSQf |
4945 | 1.35M | 0U, // VCVTMNSQh |
4946 | 1.35M | 0U, // VCVTMNUDf |
4947 | 1.35M | 0U, // VCVTMNUDh |
4948 | 1.35M | 0U, // VCVTMNUQf |
4949 | 1.35M | 0U, // VCVTMNUQh |
4950 | 1.35M | 0U, // VCVTMSD |
4951 | 1.35M | 0U, // VCVTMSH |
4952 | 1.35M | 0U, // VCVTMSS |
4953 | 1.35M | 0U, // VCVTMUD |
4954 | 1.35M | 0U, // VCVTMUH |
4955 | 1.35M | 0U, // VCVTMUS |
4956 | 1.35M | 0U, // VCVTNNSDf |
4957 | 1.35M | 0U, // VCVTNNSDh |
4958 | 1.35M | 0U, // VCVTNNSQf |
4959 | 1.35M | 0U, // VCVTNNSQh |
4960 | 1.35M | 0U, // VCVTNNUDf |
4961 | 1.35M | 0U, // VCVTNNUDh |
4962 | 1.35M | 0U, // VCVTNNUQf |
4963 | 1.35M | 0U, // VCVTNNUQh |
4964 | 1.35M | 0U, // VCVTNSD |
4965 | 1.35M | 0U, // VCVTNSH |
4966 | 1.35M | 0U, // VCVTNSS |
4967 | 1.35M | 0U, // VCVTNUD |
4968 | 1.35M | 0U, // VCVTNUH |
4969 | 1.35M | 0U, // VCVTNUS |
4970 | 1.35M | 0U, // VCVTPNSDf |
4971 | 1.35M | 0U, // VCVTPNSDh |
4972 | 1.35M | 0U, // VCVTPNSQf |
4973 | 1.35M | 0U, // VCVTPNSQh |
4974 | 1.35M | 0U, // VCVTPNUDf |
4975 | 1.35M | 0U, // VCVTPNUDh |
4976 | 1.35M | 0U, // VCVTPNUQf |
4977 | 1.35M | 0U, // VCVTPNUQh |
4978 | 1.35M | 0U, // VCVTPSD |
4979 | 1.35M | 0U, // VCVTPSH |
4980 | 1.35M | 0U, // VCVTPSS |
4981 | 1.35M | 0U, // VCVTPUD |
4982 | 1.35M | 0U, // VCVTPUH |
4983 | 1.35M | 0U, // VCVTPUS |
4984 | 1.35M | 0U, // VCVTSD |
4985 | 1.35M | 0U, // VCVTTDH |
4986 | 1.35M | 0U, // VCVTTHD |
4987 | 1.35M | 0U, // VCVTTHS |
4988 | 1.35M | 0U, // VCVTTSH |
4989 | 1.35M | 0U, // VCVTf2h |
4990 | 1.35M | 0U, // VCVTf2sd |
4991 | 1.35M | 0U, // VCVTf2sq |
4992 | 1.35M | 0U, // VCVTf2ud |
4993 | 1.35M | 0U, // VCVTf2uq |
4994 | 1.35M | 35U, // VCVTf2xsd |
4995 | 1.35M | 35U, // VCVTf2xsq |
4996 | 1.35M | 35U, // VCVTf2xud |
4997 | 1.35M | 35U, // VCVTf2xuq |
4998 | 1.35M | 0U, // VCVTh2f |
4999 | 1.35M | 0U, // VCVTh2sd |
5000 | 1.35M | 0U, // VCVTh2sq |
5001 | 1.35M | 0U, // VCVTh2ud |
5002 | 1.35M | 0U, // VCVTh2uq |
5003 | 1.35M | 35U, // VCVTh2xsd |
5004 | 1.35M | 35U, // VCVTh2xsq |
5005 | 1.35M | 35U, // VCVTh2xud |
5006 | 1.35M | 35U, // VCVTh2xuq |
5007 | 1.35M | 0U, // VCVTs2fd |
5008 | 1.35M | 0U, // VCVTs2fq |
5009 | 1.35M | 0U, // VCVTs2hd |
5010 | 1.35M | 0U, // VCVTs2hq |
5011 | 1.35M | 0U, // VCVTu2fd |
5012 | 1.35M | 0U, // VCVTu2fq |
5013 | 1.35M | 0U, // VCVTu2hd |
5014 | 1.35M | 0U, // VCVTu2hq |
5015 | 1.35M | 35U, // VCVTxs2fd |
5016 | 1.35M | 35U, // VCVTxs2fq |
5017 | 1.35M | 35U, // VCVTxs2hd |
5018 | 1.35M | 35U, // VCVTxs2hq |
5019 | 1.35M | 35U, // VCVTxu2fd |
5020 | 1.35M | 35U, // VCVTxu2fq |
5021 | 1.35M | 35U, // VCVTxu2hd |
5022 | 1.35M | 35U, // VCVTxu2hq |
5023 | 1.35M | 70705U, // VDIVD |
5024 | 1.35M | 70705U, // VDIVH |
5025 | 1.35M | 70705U, // VDIVS |
5026 | 1.35M | 1024U, // VDUP16d |
5027 | 1.35M | 1024U, // VDUP16q |
5028 | 1.35M | 1024U, // VDUP32d |
5029 | 1.35M | 1024U, // VDUP32q |
5030 | 1.35M | 1024U, // VDUP8d |
5031 | 1.35M | 1024U, // VDUP8q |
5032 | 1.35M | 9216U, // VDUPLN16d |
5033 | 1.35M | 9216U, // VDUPLN16q |
5034 | 1.35M | 9216U, // VDUPLN32d |
5035 | 1.35M | 9216U, // VDUPLN32q |
5036 | 1.35M | 9216U, // VDUPLN8d |
5037 | 1.35M | 9216U, // VDUPLN8q |
5038 | 1.35M | 0U, // VEORd |
5039 | 1.35M | 0U, // VEORq |
5040 | 1.35M | 35651584U, // VEXTd16 |
5041 | 1.35M | 35651584U, // VEXTd32 |
5042 | 1.35M | 35651584U, // VEXTd8 |
5043 | 1.35M | 35651584U, // VEXTq16 |
5044 | 1.35M | 35651584U, // VEXTq32 |
5045 | 1.35M | 35651584U, // VEXTq64 |
5046 | 1.35M | 35651584U, // VEXTq8 |
5047 | 1.35M | 68659U, // VFMAD |
5048 | 1.35M | 68659U, // VFMAH |
5049 | 1.35M | 68659U, // VFMAS |
5050 | 1.35M | 68659U, // VFMAfd |
5051 | 1.35M | 68659U, // VFMAfq |
5052 | 1.35M | 68659U, // VFMAhd |
5053 | 1.35M | 68659U, // VFMAhq |
5054 | 1.35M | 68659U, // VFMSD |
5055 | 1.35M | 68659U, // VFMSH |
5056 | 1.35M | 68659U, // VFMSS |
5057 | 1.35M | 68659U, // VFMSfd |
5058 | 1.35M | 68659U, // VFMSfq |
5059 | 1.35M | 68659U, // VFMShd |
5060 | 1.35M | 68659U, // VFMShq |
5061 | 1.35M | 68659U, // VFNMAD |
5062 | 1.35M | 68659U, // VFNMAH |
5063 | 1.35M | 68659U, // VFNMAS |
5064 | 1.35M | 68659U, // VFNMSD |
5065 | 1.35M | 68659U, // VFNMSH |
5066 | 1.35M | 68659U, // VFNMSS |
5067 | 1.35M | 9216U, // VGETLNi32 |
5068 | 1.35M | 3U, // VGETLNs16 |
5069 | 1.35M | 3U, // VGETLNs8 |
5070 | 1.35M | 3U, // VGETLNu16 |
5071 | 1.35M | 3U, // VGETLNu8 |
5072 | 1.35M | 1112U, // VHADDsv16i8 |
5073 | 1.35M | 1112U, // VHADDsv2i32 |
5074 | 1.35M | 1112U, // VHADDsv4i16 |
5075 | 1.35M | 1112U, // VHADDsv4i32 |
5076 | 1.35M | 1112U, // VHADDsv8i16 |
5077 | 1.35M | 1112U, // VHADDsv8i8 |
5078 | 1.35M | 1112U, // VHADDuv16i8 |
5079 | 1.35M | 1112U, // VHADDuv2i32 |
5080 | 1.35M | 1112U, // VHADDuv4i16 |
5081 | 1.35M | 1112U, // VHADDuv4i32 |
5082 | 1.35M | 1112U, // VHADDuv8i16 |
5083 | 1.35M | 1112U, // VHADDuv8i8 |
5084 | 1.35M | 1112U, // VHSUBsv16i8 |
5085 | 1.35M | 1112U, // VHSUBsv2i32 |
5086 | 1.35M | 1112U, // VHSUBsv4i16 |
5087 | 1.35M | 1112U, // VHSUBsv4i32 |
5088 | 1.35M | 1112U, // VHSUBsv8i16 |
5089 | 1.35M | 1112U, // VHSUBsv8i8 |
5090 | 1.35M | 1112U, // VHSUBuv16i8 |
5091 | 1.35M | 1112U, // VHSUBuv2i32 |
5092 | 1.35M | 1112U, // VHSUBuv4i16 |
5093 | 1.35M | 1112U, // VHSUBuv4i32 |
5094 | 1.35M | 1112U, // VHSUBuv8i16 |
5095 | 1.35M | 1112U, // VHSUBuv8i8 |
5096 | 1.35M | 0U, // VINSH |
5097 | 1.35M | 0U, // VJCVT |
5098 | 1.35M | 32U, // VLD1DUPd16 |
5099 | 1.35M | 44U, // VLD1DUPd16wb_fixed |
5100 | 1.35M | 10292U, // VLD1DUPd16wb_register |
5101 | 1.35M | 32U, // VLD1DUPd32 |
5102 | 1.35M | 44U, // VLD1DUPd32wb_fixed |
5103 | 1.35M | 10292U, // VLD1DUPd32wb_register |
5104 | 1.35M | 32U, // VLD1DUPd8 |
5105 | 1.35M | 44U, // VLD1DUPd8wb_fixed |
5106 | 1.35M | 10292U, // VLD1DUPd8wb_register |
5107 | 1.35M | 32U, // VLD1DUPq16 |
5108 | 1.35M | 44U, // VLD1DUPq16wb_fixed |
5109 | 1.35M | 10292U, // VLD1DUPq16wb_register |
5110 | 1.35M | 32U, // VLD1DUPq32 |
5111 | 1.35M | 44U, // VLD1DUPq32wb_fixed |
5112 | 1.35M | 10292U, // VLD1DUPq32wb_register |
5113 | 1.35M | 32U, // VLD1DUPq8 |
5114 | 1.35M | 44U, // VLD1DUPq8wb_fixed |
5115 | 1.35M | 10292U, // VLD1DUPq8wb_register |
5116 | 1.35M | 699628U, // VLD1LNd16 |
5117 | 1.35M | 732404U, // VLD1LNd16_UPD |
5118 | 1.35M | 699628U, // VLD1LNd32 |
5119 | 1.35M | 732404U, // VLD1LNd32_UPD |
5120 | 1.35M | 699628U, // VLD1LNd8 |
5121 | 1.35M | 732404U, // VLD1LNd8_UPD |
5122 | 1.35M | 0U, // VLD1LNq16Pseudo |
5123 | 1.35M | 0U, // VLD1LNq16Pseudo_UPD |
5124 | 1.35M | 0U, // VLD1LNq32Pseudo |
5125 | 1.35M | 0U, // VLD1LNq32Pseudo_UPD |
5126 | 1.35M | 0U, // VLD1LNq8Pseudo |
5127 | 1.35M | 0U, // VLD1LNq8Pseudo_UPD |
5128 | 1.35M | 32U, // VLD1d16 |
5129 | 1.35M | 32U, // VLD1d16Q |
5130 | 1.35M | 0U, // VLD1d16QPseudo |
5131 | 1.35M | 44U, // VLD1d16Qwb_fixed |
5132 | 1.35M | 10292U, // VLD1d16Qwb_register |
5133 | 1.35M | 32U, // VLD1d16T |
5134 | 1.35M | 0U, // VLD1d16TPseudo |
5135 | 1.35M | 44U, // VLD1d16Twb_fixed |
5136 | 1.35M | 10292U, // VLD1d16Twb_register |
5137 | 1.35M | 44U, // VLD1d16wb_fixed |
5138 | 1.35M | 10292U, // VLD1d16wb_register |
5139 | 1.35M | 32U, // VLD1d32 |
5140 | 1.35M | 32U, // VLD1d32Q |
5141 | 1.35M | 0U, // VLD1d32QPseudo |
5142 | 1.35M | 44U, // VLD1d32Qwb_fixed |
5143 | 1.35M | 10292U, // VLD1d32Qwb_register |
5144 | 1.35M | 32U, // VLD1d32T |
5145 | 1.35M | 0U, // VLD1d32TPseudo |
5146 | 1.35M | 44U, // VLD1d32Twb_fixed |
5147 | 1.35M | 10292U, // VLD1d32Twb_register |
5148 | 1.35M | 44U, // VLD1d32wb_fixed |
5149 | 1.35M | 10292U, // VLD1d32wb_register |
5150 | 1.35M | 32U, // VLD1d64 |
5151 | 1.35M | 32U, // VLD1d64Q |
5152 | 1.35M | 0U, // VLD1d64QPseudo |
5153 | 1.35M | 0U, // VLD1d64QPseudoWB_fixed |
5154 | 1.35M | 0U, // VLD1d64QPseudoWB_register |
5155 | 1.35M | 44U, // VLD1d64Qwb_fixed |
5156 | 1.35M | 10292U, // VLD1d64Qwb_register |
5157 | 1.35M | 32U, // VLD1d64T |
5158 | 1.35M | 0U, // VLD1d64TPseudo |
5159 | 1.35M | 0U, // VLD1d64TPseudoWB_fixed |
5160 | 1.35M | 0U, // VLD1d64TPseudoWB_register |
5161 | 1.35M | 44U, // VLD1d64Twb_fixed |
5162 | 1.35M | 10292U, // VLD1d64Twb_register |
5163 | 1.35M | 44U, // VLD1d64wb_fixed |
5164 | 1.35M | 10292U, // VLD1d64wb_register |
5165 | 1.35M | 32U, // VLD1d8 |
5166 | 1.35M | 32U, // VLD1d8Q |
5167 | 1.35M | 0U, // VLD1d8QPseudo |
5168 | 1.35M | 44U, // VLD1d8Qwb_fixed |
5169 | 1.35M | 10292U, // VLD1d8Qwb_register |
5170 | 1.35M | 32U, // VLD1d8T |
5171 | 1.35M | 0U, // VLD1d8TPseudo |
5172 | 1.35M | 44U, // VLD1d8Twb_fixed |
5173 | 1.35M | 10292U, // VLD1d8Twb_register |
5174 | 1.35M | 44U, // VLD1d8wb_fixed |
5175 | 1.35M | 10292U, // VLD1d8wb_register |
5176 | 1.35M | 32U, // VLD1q16 |
5177 | 1.35M | 0U, // VLD1q16HighQPseudo |
5178 | 1.35M | 0U, // VLD1q16HighTPseudo |
5179 | 1.35M | 0U, // VLD1q16LowQPseudo_UPD |
5180 | 1.35M | 0U, // VLD1q16LowTPseudo_UPD |
5181 | 1.35M | 44U, // VLD1q16wb_fixed |
5182 | 1.35M | 10292U, // VLD1q16wb_register |
5183 | 1.35M | 32U, // VLD1q32 |
5184 | 1.35M | 0U, // VLD1q32HighQPseudo |
5185 | 1.35M | 0U, // VLD1q32HighTPseudo |
5186 | 1.35M | 0U, // VLD1q32LowQPseudo_UPD |
5187 | 1.35M | 0U, // VLD1q32LowTPseudo_UPD |
5188 | 1.35M | 44U, // VLD1q32wb_fixed |
5189 | 1.35M | 10292U, // VLD1q32wb_register |
5190 | 1.35M | 32U, // VLD1q64 |
5191 | 1.35M | 0U, // VLD1q64HighQPseudo |
5192 | 1.35M | 0U, // VLD1q64HighTPseudo |
5193 | 1.35M | 0U, // VLD1q64LowQPseudo_UPD |
5194 | 1.35M | 0U, // VLD1q64LowTPseudo_UPD |
5195 | 1.35M | 44U, // VLD1q64wb_fixed |
5196 | 1.35M | 10292U, // VLD1q64wb_register |
5197 | 1.35M | 32U, // VLD1q8 |
5198 | 1.35M | 0U, // VLD1q8HighQPseudo |
5199 | 1.35M | 0U, // VLD1q8HighTPseudo |
5200 | 1.35M | 0U, // VLD1q8LowQPseudo_UPD |
5201 | 1.35M | 0U, // VLD1q8LowTPseudo_UPD |
5202 | 1.35M | 44U, // VLD1q8wb_fixed |
5203 | 1.35M | 10292U, // VLD1q8wb_register |
5204 | 1.35M | 32U, // VLD2DUPd16 |
5205 | 1.35M | 44U, // VLD2DUPd16wb_fixed |
5206 | 1.35M | 10292U, // VLD2DUPd16wb_register |
5207 | 1.35M | 32U, // VLD2DUPd16x2 |
5208 | 1.35M | 44U, // VLD2DUPd16x2wb_fixed |
5209 | 1.35M | 10292U, // VLD2DUPd16x2wb_register |
5210 | 1.35M | 32U, // VLD2DUPd32 |
5211 | 1.35M | 44U, // VLD2DUPd32wb_fixed |
5212 | 1.35M | 10292U, // VLD2DUPd32wb_register |
5213 | 1.35M | 32U, // VLD2DUPd32x2 |
5214 | 1.35M | 44U, // VLD2DUPd32x2wb_fixed |
5215 | 1.35M | 10292U, // VLD2DUPd32x2wb_register |
5216 | 1.35M | 32U, // VLD2DUPd8 |
5217 | 1.35M | 44U, // VLD2DUPd8wb_fixed |
5218 | 1.35M | 10292U, // VLD2DUPd8wb_register |
5219 | 1.35M | 32U, // VLD2DUPd8x2 |
5220 | 1.35M | 44U, // VLD2DUPd8x2wb_fixed |
5221 | 1.35M | 10292U, // VLD2DUPd8x2wb_register |
5222 | 1.35M | 0U, // VLD2DUPq16EvenPseudo |
5223 | 1.35M | 0U, // VLD2DUPq16OddPseudo |
5224 | 1.35M | 0U, // VLD2DUPq32EvenPseudo |
5225 | 1.35M | 0U, // VLD2DUPq32OddPseudo |
5226 | 1.35M | 0U, // VLD2DUPq8EvenPseudo |
5227 | 1.35M | 0U, // VLD2DUPq8OddPseudo |
5228 | 1.35M | 766196U, // VLD2LNd16 |
5229 | 1.35M | 0U, // VLD2LNd16Pseudo |
5230 | 1.35M | 0U, // VLD2LNd16Pseudo_UPD |
5231 | 1.35M | 799996U, // VLD2LNd16_UPD |
5232 | 1.35M | 766196U, // VLD2LNd32 |
5233 | 1.35M | 0U, // VLD2LNd32Pseudo |
5234 | 1.35M | 0U, // VLD2LNd32Pseudo_UPD |
5235 | 1.35M | 799996U, // VLD2LNd32_UPD |
5236 | 1.35M | 766196U, // VLD2LNd8 |
5237 | 1.35M | 0U, // VLD2LNd8Pseudo |
5238 | 1.35M | 0U, // VLD2LNd8Pseudo_UPD |
5239 | 1.35M | 799996U, // VLD2LNd8_UPD |
5240 | 1.35M | 766196U, // VLD2LNq16 |
5241 | 1.35M | 0U, // VLD2LNq16Pseudo |
5242 | 1.35M | 0U, // VLD2LNq16Pseudo_UPD |
5243 | 1.35M | 799996U, // VLD2LNq16_UPD |
5244 | 1.35M | 766196U, // VLD2LNq32 |
5245 | 1.35M | 0U, // VLD2LNq32Pseudo |
5246 | 1.35M | 0U, // VLD2LNq32Pseudo_UPD |
5247 | 1.35M | 799996U, // VLD2LNq32_UPD |
5248 | 1.35M | 32U, // VLD2b16 |
5249 | 1.35M | 44U, // VLD2b16wb_fixed |
5250 | 1.35M | 10292U, // VLD2b16wb_register |
5251 | 1.35M | 32U, // VLD2b32 |
5252 | 1.35M | 44U, // VLD2b32wb_fixed |
5253 | 1.35M | 10292U, // VLD2b32wb_register |
5254 | 1.35M | 32U, // VLD2b8 |
5255 | 1.35M | 44U, // VLD2b8wb_fixed |
5256 | 1.35M | 10292U, // VLD2b8wb_register |
5257 | 1.35M | 32U, // VLD2d16 |
5258 | 1.35M | 44U, // VLD2d16wb_fixed |
5259 | 1.35M | 10292U, // VLD2d16wb_register |
5260 | 1.35M | 32U, // VLD2d32 |
5261 | 1.35M | 44U, // VLD2d32wb_fixed |
5262 | 1.35M | 10292U, // VLD2d32wb_register |
5263 | 1.35M | 32U, // VLD2d8 |
5264 | 1.35M | 44U, // VLD2d8wb_fixed |
5265 | 1.35M | 10292U, // VLD2d8wb_register |
5266 | 1.35M | 32U, // VLD2q16 |
5267 | 1.35M | 0U, // VLD2q16Pseudo |
5268 | 1.35M | 0U, // VLD2q16PseudoWB_fixed |
5269 | 1.35M | 0U, // VLD2q16PseudoWB_register |
5270 | 1.35M | 44U, // VLD2q16wb_fixed |
5271 | 1.35M | 10292U, // VLD2q16wb_register |
5272 | 1.35M | 32U, // VLD2q32 |
5273 | 1.35M | 0U, // VLD2q32Pseudo |
5274 | 1.35M | 0U, // VLD2q32PseudoWB_fixed |
5275 | 1.35M | 0U, // VLD2q32PseudoWB_register |
5276 | 1.35M | 44U, // VLD2q32wb_fixed |
5277 | 1.35M | 10292U, // VLD2q32wb_register |
5278 | 1.35M | 32U, // VLD2q8 |
5279 | 1.35M | 0U, // VLD2q8Pseudo |
5280 | 1.35M | 0U, // VLD2q8PseudoWB_fixed |
5281 | 1.35M | 0U, // VLD2q8PseudoWB_register |
5282 | 1.35M | 44U, // VLD2q8wb_fixed |
5283 | 1.35M | 10292U, // VLD2q8wb_register |
5284 | 1.35M | 14596U, // VLD3DUPd16 |
5285 | 1.35M | 0U, // VLD3DUPd16Pseudo |
5286 | 1.35M | 0U, // VLD3DUPd16Pseudo_UPD |
5287 | 1.35M | 834820U, // VLD3DUPd16_UPD |
5288 | 1.35M | 14596U, // VLD3DUPd32 |
5289 | 1.35M | 0U, // VLD3DUPd32Pseudo |
5290 | 1.35M | 0U, // VLD3DUPd32Pseudo_UPD |
5291 | 1.35M | 834820U, // VLD3DUPd32_UPD |
5292 | 1.35M | 14596U, // VLD3DUPd8 |
5293 | 1.35M | 0U, // VLD3DUPd8Pseudo |
5294 | 1.35M | 0U, // VLD3DUPd8Pseudo_UPD |
5295 | 1.35M | 834820U, // VLD3DUPd8_UPD |
5296 | 1.35M | 14596U, // VLD3DUPq16 |
5297 | 1.35M | 0U, // VLD3DUPq16EvenPseudo |
5298 | 1.35M | 0U, // VLD3DUPq16OddPseudo |
5299 | 1.35M | 834820U, // VLD3DUPq16_UPD |
5300 | 1.35M | 14596U, // VLD3DUPq32 |
5301 | 1.35M | 0U, // VLD3DUPq32EvenPseudo |
5302 | 1.35M | 0U, // VLD3DUPq32OddPseudo |
5303 | 1.35M | 834820U, // VLD3DUPq32_UPD |
5304 | 1.35M | 14596U, // VLD3DUPq8 |
5305 | 1.35M | 0U, // VLD3DUPq8EvenPseudo |
5306 | 1.35M | 0U, // VLD3DUPq8OddPseudo |
5307 | 1.35M | 834820U, // VLD3DUPq8_UPD |
5308 | 1.35M | 865532U, // VLD3LNd16 |
5309 | 1.35M | 0U, // VLD3LNd16Pseudo |
5310 | 1.35M | 0U, // VLD3LNd16Pseudo_UPD |
5311 | 1.35M | 896268U, // VLD3LNd16_UPD |
5312 | 1.35M | 865532U, // VLD3LNd32 |
5313 | 1.35M | 0U, // VLD3LNd32Pseudo |
5314 | 1.35M | 0U, // VLD3LNd32Pseudo_UPD |
5315 | 1.35M | 896268U, // VLD3LNd32_UPD |
5316 | 1.35M | 865532U, // VLD3LNd8 |
5317 | 1.35M | 0U, // VLD3LNd8Pseudo |
5318 | 1.35M | 0U, // VLD3LNd8Pseudo_UPD |
5319 | 1.35M | 896268U, // VLD3LNd8_UPD |
5320 | 1.35M | 865532U, // VLD3LNq16 |
5321 | 1.35M | 0U, // VLD3LNq16Pseudo |
5322 | 1.35M | 0U, // VLD3LNq16Pseudo_UPD |
5323 | 1.35M | 896268U, // VLD3LNq16_UPD |
5324 | 1.35M | 865532U, // VLD3LNq32 |
5325 | 1.35M | 0U, // VLD3LNq32Pseudo |
5326 | 1.35M | 0U, // VLD3LNq32Pseudo_UPD |
5327 | 1.35M | 896268U, // VLD3LNq32_UPD |
5328 | 1.35M | 119537664U, // VLD3d16 |
5329 | 1.35M | 0U, // VLD3d16Pseudo |
5330 | 1.35M | 0U, // VLD3d16Pseudo_UPD |
5331 | 1.35M | 153092096U, // VLD3d16_UPD |
5332 | 1.35M | 119537664U, // VLD3d32 |
5333 | 1.35M | 0U, // VLD3d32Pseudo |
5334 | 1.35M | 0U, // VLD3d32Pseudo_UPD |
5335 | 1.35M | 153092096U, // VLD3d32_UPD |
5336 | 1.35M | 119537664U, // VLD3d8 |
5337 | 1.35M | 0U, // VLD3d8Pseudo |
5338 | 1.35M | 0U, // VLD3d8Pseudo_UPD |
5339 | 1.35M | 153092096U, // VLD3d8_UPD |
5340 | 1.35M | 119537664U, // VLD3q16 |
5341 | 1.35M | 0U, // VLD3q16Pseudo_UPD |
5342 | 1.35M | 153092096U, // VLD3q16_UPD |
5343 | 1.35M | 0U, // VLD3q16oddPseudo |
5344 | 1.35M | 0U, // VLD3q16oddPseudo_UPD |
5345 | 1.35M | 119537664U, // VLD3q32 |
5346 | 1.35M | 0U, // VLD3q32Pseudo_UPD |
5347 | 1.35M | 153092096U, // VLD3q32_UPD |
5348 | 1.35M | 0U, // VLD3q32oddPseudo |
5349 | 1.35M | 0U, // VLD3q32oddPseudo_UPD |
5350 | 1.35M | 119537664U, // VLD3q8 |
5351 | 1.35M | 0U, // VLD3q8Pseudo_UPD |
5352 | 1.35M | 153092096U, // VLD3q8_UPD |
5353 | 1.35M | 0U, // VLD3q8oddPseudo |
5354 | 1.35M | 0U, // VLD3q8oddPseudo_UPD |
5355 | 1.35M | 81172U, // VLD4DUPd16 |
5356 | 1.35M | 0U, // VLD4DUPd16Pseudo |
5357 | 1.35M | 0U, // VLD4DUPd16Pseudo_UPD |
5358 | 1.35M | 16660U, // VLD4DUPd16_UPD |
5359 | 1.35M | 81172U, // VLD4DUPd32 |
5360 | 1.35M | 0U, // VLD4DUPd32Pseudo |
5361 | 1.35M | 0U, // VLD4DUPd32Pseudo_UPD |
5362 | 1.35M | 16660U, // VLD4DUPd32_UPD |
5363 | 1.35M | 81172U, // VLD4DUPd8 |
5364 | 1.35M | 0U, // VLD4DUPd8Pseudo |
5365 | 1.35M | 0U, // VLD4DUPd8Pseudo_UPD |
5366 | 1.35M | 16660U, // VLD4DUPd8_UPD |
5367 | 1.35M | 81172U, // VLD4DUPq16 |
5368 | 1.35M | 0U, // VLD4DUPq16EvenPseudo |
5369 | 1.35M | 0U, // VLD4DUPq16OddPseudo |
5370 | 1.35M | 16660U, // VLD4DUPq16_UPD |
5371 | 1.35M | 81172U, // VLD4DUPq32 |
5372 | 1.35M | 0U, // VLD4DUPq32EvenPseudo |
5373 | 1.35M | 0U, // VLD4DUPq32OddPseudo |
5374 | 1.35M | 16660U, // VLD4DUPq32_UPD |
5375 | 1.35M | 81172U, // VLD4DUPq8 |
5376 | 1.35M | 0U, // VLD4DUPq8EvenPseudo |
5377 | 1.35M | 0U, // VLD4DUPq8OddPseudo |
5378 | 1.35M | 16660U, // VLD4DUPq8_UPD |
5379 | 1.35M | 189346060U, // VLD4LNd16 |
5380 | 1.35M | 0U, // VLD4LNd16Pseudo |
5381 | 1.35M | 0U, // VLD4LNd16Pseudo_UPD |
5382 | 1.35M | 284U, // VLD4LNd16_UPD |
5383 | 1.35M | 189346060U, // VLD4LNd32 |
5384 | 1.35M | 0U, // VLD4LNd32Pseudo |
5385 | 1.35M | 0U, // VLD4LNd32Pseudo_UPD |
5386 | 1.35M | 284U, // VLD4LNd32_UPD |
5387 | 1.35M | 189346060U, // VLD4LNd8 |
5388 | 1.35M | 0U, // VLD4LNd8Pseudo |
5389 | 1.35M | 0U, // VLD4LNd8Pseudo_UPD |
5390 | 1.35M | 284U, // VLD4LNd8_UPD |
5391 | 1.35M | 189346060U, // VLD4LNq16 |
5392 | 1.35M | 0U, // VLD4LNq16Pseudo |
5393 | 1.35M | 0U, // VLD4LNq16Pseudo_UPD |
5394 | 1.35M | 284U, // VLD4LNq16_UPD |
5395 | 1.35M | 189346060U, // VLD4LNq32 |
5396 | 1.35M | 0U, // VLD4LNq32Pseudo |
5397 | 1.35M | 0U, // VLD4LNq32Pseudo_UPD |
5398 | 1.35M | 284U, // VLD4LNq32_UPD |
5399 | 1.35M | 572522496U, // VLD4d16 |
5400 | 1.35M | 0U, // VLD4d16Pseudo |
5401 | 1.35M | 0U, // VLD4d16Pseudo_UPD |
5402 | 1.35M | 1646264320U, // VLD4d16_UPD |
5403 | 1.35M | 572522496U, // VLD4d32 |
5404 | 1.35M | 0U, // VLD4d32Pseudo |
5405 | 1.35M | 0U, // VLD4d32Pseudo_UPD |
5406 | 1.35M | 1646264320U, // VLD4d32_UPD |
5407 | 1.35M | 572522496U, // VLD4d8 |
5408 | 1.35M | 0U, // VLD4d8Pseudo |
5409 | 1.35M | 0U, // VLD4d8Pseudo_UPD |
5410 | 1.35M | 1646264320U, // VLD4d8_UPD |
5411 | 1.35M | 572522496U, // VLD4q16 |
5412 | 1.35M | 0U, // VLD4q16Pseudo_UPD |
5413 | 1.35M | 1646264320U, // VLD4q16_UPD |
5414 | 1.35M | 0U, // VLD4q16oddPseudo |
5415 | 1.35M | 0U, // VLD4q16oddPseudo_UPD |
5416 | 1.35M | 572522496U, // VLD4q32 |
5417 | 1.35M | 0U, // VLD4q32Pseudo_UPD |
5418 | 1.35M | 1646264320U, // VLD4q32_UPD |
5419 | 1.35M | 0U, // VLD4q32oddPseudo |
5420 | 1.35M | 0U, // VLD4q32oddPseudo_UPD |
5421 | 1.35M | 572522496U, // VLD4q8 |
5422 | 1.35M | 0U, // VLD4q8Pseudo_UPD |
5423 | 1.35M | 1646264320U, // VLD4q8_UPD |
5424 | 1.35M | 0U, // VLD4q8oddPseudo |
5425 | 1.35M | 0U, // VLD4q8oddPseudo_UPD |
5426 | 1.35M | 33U, // VLDMDDB_UPD |
5427 | 1.35M | 1136U, // VLDMDIA |
5428 | 1.35M | 33U, // VLDMDIA_UPD |
5429 | 1.35M | 0U, // VLDMQIA |
5430 | 1.35M | 33U, // VLDMSDB_UPD |
5431 | 1.35M | 1136U, // VLDMSIA |
5432 | 1.35M | 33U, // VLDMSIA_UPD |
5433 | 1.35M | 288U, // VLDRD |
5434 | 1.35M | 296U, // VLDRH |
5435 | 1.35M | 288U, // VLDRS |
5436 | 1.35M | 0U, // VLLDM |
5437 | 1.35M | 0U, // VLSTM |
5438 | 1.35M | 1112U, // VMAXNMD |
5439 | 1.35M | 1112U, // VMAXNMH |
5440 | 1.35M | 1112U, // VMAXNMNDf |
5441 | 1.35M | 1112U, // VMAXNMNDh |
5442 | 1.35M | 1112U, // VMAXNMNQf |
5443 | 1.35M | 1112U, // VMAXNMNQh |
5444 | 1.35M | 1112U, // VMAXNMS |
5445 | 1.35M | 70705U, // VMAXfd |
5446 | 1.35M | 70705U, // VMAXfq |
5447 | 1.35M | 70705U, // VMAXhd |
5448 | 1.35M | 70705U, // VMAXhq |
5449 | 1.35M | 1112U, // VMAXsv16i8 |
5450 | 1.35M | 1112U, // VMAXsv2i32 |
5451 | 1.35M | 1112U, // VMAXsv4i16 |
5452 | 1.35M | 1112U, // VMAXsv4i32 |
5453 | 1.35M | 1112U, // VMAXsv8i16 |
5454 | 1.35M | 1112U, // VMAXsv8i8 |
5455 | 1.35M | 1112U, // VMAXuv16i8 |
5456 | 1.35M | 1112U, // VMAXuv2i32 |
5457 | 1.35M | 1112U, // VMAXuv4i16 |
5458 | 1.35M | 1112U, // VMAXuv4i32 |
5459 | 1.35M | 1112U, // VMAXuv8i16 |
5460 | 1.35M | 1112U, // VMAXuv8i8 |
5461 | 1.35M | 1112U, // VMINNMD |
5462 | 1.35M | 1112U, // VMINNMH |
5463 | 1.35M | 1112U, // VMINNMNDf |
5464 | 1.35M | 1112U, // VMINNMNDh |
5465 | 1.35M | 1112U, // VMINNMNQf |
5466 | 1.35M | 1112U, // VMINNMNQh |
5467 | 1.35M | 1112U, // VMINNMS |
5468 | 1.35M | 70705U, // VMINfd |
5469 | 1.35M | 70705U, // VMINfq |
5470 | 1.35M | 70705U, // VMINhd |
5471 | 1.35M | 70705U, // VMINhq |
5472 | 1.35M | 1112U, // VMINsv16i8 |
5473 | 1.35M | 1112U, // VMINsv2i32 |
5474 | 1.35M | 1112U, // VMINsv4i16 |
5475 | 1.35M | 1112U, // VMINsv4i32 |
5476 | 1.35M | 1112U, // VMINsv8i16 |
5477 | 1.35M | 1112U, // VMINsv8i8 |
5478 | 1.35M | 1112U, // VMINuv16i8 |
5479 | 1.35M | 1112U, // VMINuv2i32 |
5480 | 1.35M | 1112U, // VMINuv4i16 |
5481 | 1.35M | 1112U, // VMINuv4i32 |
5482 | 1.35M | 1112U, // VMINuv8i16 |
5483 | 1.35M | 1112U, // VMINuv8i8 |
5484 | 1.35M | 68659U, // VMLAD |
5485 | 1.35M | 68659U, // VMLAH |
5486 | 1.35M | 73752U, // VMLALslsv2i32 |
5487 | 1.35M | 73752U, // VMLALslsv4i16 |
5488 | 1.35M | 73752U, // VMLALsluv2i32 |
5489 | 1.35M | 73752U, // VMLALsluv4i16 |
5490 | 1.35M | 1048U, // VMLALsv2i64 |
5491 | 1.35M | 1048U, // VMLALsv4i32 |
5492 | 1.35M | 1048U, // VMLALsv8i16 |
5493 | 1.35M | 1048U, // VMLALuv2i64 |
5494 | 1.35M | 1048U, // VMLALuv4i32 |
5495 | 1.35M | 1048U, // VMLALuv8i16 |
5496 | 1.35M | 68659U, // VMLAS |
5497 | 1.35M | 68659U, // VMLAfd |
5498 | 1.35M | 68659U, // VMLAfq |
5499 | 1.35M | 68659U, // VMLAhd |
5500 | 1.35M | 68659U, // VMLAhq |
5501 | 1.35M | 920627U, // VMLAslfd |
5502 | 1.35M | 920627U, // VMLAslfq |
5503 | 1.35M | 920627U, // VMLAslhd |
5504 | 1.35M | 920627U, // VMLAslhq |
5505 | 1.35M | 73752U, // VMLAslv2i32 |
5506 | 1.35M | 73752U, // VMLAslv4i16 |
5507 | 1.35M | 73752U, // VMLAslv4i32 |
5508 | 1.35M | 73752U, // VMLAslv8i16 |
5509 | 1.35M | 1048U, // VMLAv16i8 |
5510 | 1.35M | 1048U, // VMLAv2i32 |
5511 | 1.35M | 1048U, // VMLAv4i16 |
5512 | 1.35M | 1048U, // VMLAv4i32 |
5513 | 1.35M | 1048U, // VMLAv8i16 |
5514 | 1.35M | 1048U, // VMLAv8i8 |
5515 | 1.35M | 68659U, // VMLSD |
5516 | 1.35M | 68659U, // VMLSH |
5517 | 1.35M | 73752U, // VMLSLslsv2i32 |
5518 | 1.35M | 73752U, // VMLSLslsv4i16 |
5519 | 1.35M | 73752U, // VMLSLsluv2i32 |
5520 | 1.35M | 73752U, // VMLSLsluv4i16 |
5521 | 1.35M | 1048U, // VMLSLsv2i64 |
5522 | 1.35M | 1048U, // VMLSLsv4i32 |
5523 | 1.35M | 1048U, // VMLSLsv8i16 |
5524 | 1.35M | 1048U, // VMLSLuv2i64 |
5525 | 1.35M | 1048U, // VMLSLuv4i32 |
5526 | 1.35M | 1048U, // VMLSLuv8i16 |
5527 | 1.35M | 68659U, // VMLSS |
5528 | 1.35M | 68659U, // VMLSfd |
5529 | 1.35M | 68659U, // VMLSfq |
5530 | 1.35M | 68659U, // VMLShd |
5531 | 1.35M | 68659U, // VMLShq |
5532 | 1.35M | 920627U, // VMLSslfd |
5533 | 1.35M | 920627U, // VMLSslfq |
5534 | 1.35M | 920627U, // VMLSslhd |
5535 | 1.35M | 920627U, // VMLSslhq |
5536 | 1.35M | 73752U, // VMLSslv2i32 |
5537 | 1.35M | 73752U, // VMLSslv4i16 |
5538 | 1.35M | 73752U, // VMLSslv4i32 |
5539 | 1.35M | 73752U, // VMLSslv8i16 |
5540 | 1.35M | 1048U, // VMLSv16i8 |
5541 | 1.35M | 1048U, // VMLSv2i32 |
5542 | 1.35M | 1048U, // VMLSv4i16 |
5543 | 1.35M | 1048U, // VMLSv4i32 |
5544 | 1.35M | 1048U, // VMLSv8i16 |
5545 | 1.35M | 1048U, // VMLSv8i8 |
5546 | 1.35M | 33U, // VMOVD |
5547 | 1.35M | 0U, // VMOVDRR |
5548 | 1.35M | 0U, // VMOVH |
5549 | 1.35M | 33U, // VMOVHR |
5550 | 1.35M | 0U, // VMOVLsv2i64 |
5551 | 1.35M | 0U, // VMOVLsv4i32 |
5552 | 1.35M | 0U, // VMOVLsv8i16 |
5553 | 1.35M | 0U, // VMOVLuv2i64 |
5554 | 1.35M | 0U, // VMOVLuv4i32 |
5555 | 1.35M | 0U, // VMOVLuv8i16 |
5556 | 1.35M | 0U, // VMOVNv2i32 |
5557 | 1.35M | 0U, // VMOVNv4i16 |
5558 | 1.35M | 0U, // VMOVNv8i8 |
5559 | 1.35M | 33U, // VMOVRH |
5560 | 1.35M | 0U, // VMOVRRD |
5561 | 1.35M | 35651584U, // VMOVRRS |
5562 | 1.35M | 1024U, // VMOVRS |
5563 | 1.35M | 33U, // VMOVS |
5564 | 1.35M | 1024U, // VMOVSR |
5565 | 1.35M | 35651584U, // VMOVSRR |
5566 | 1.35M | 0U, // VMOVv16i8 |
5567 | 1.35M | 0U, // VMOVv1i64 |
5568 | 1.35M | 1U, // VMOVv2f32 |
5569 | 1.35M | 0U, // VMOVv2i32 |
5570 | 1.35M | 0U, // VMOVv2i64 |
5571 | 1.35M | 1U, // VMOVv4f32 |
5572 | 1.35M | 0U, // VMOVv4i16 |
5573 | 1.35M | 0U, // VMOVv4i32 |
5574 | 1.35M | 0U, // VMOVv8i16 |
5575 | 1.35M | 0U, // VMOVv8i8 |
5576 | 1.35M | 4U, // VMRS |
5577 | 1.35M | 5U, // VMRS_FPEXC |
5578 | 1.35M | 5U, // VMRS_FPINST |
5579 | 1.35M | 5U, // VMRS_FPINST2 |
5580 | 1.35M | 5U, // VMRS_FPSID |
5581 | 1.35M | 6U, // VMRS_MVFR0 |
5582 | 1.35M | 6U, // VMRS_MVFR1 |
5583 | 1.35M | 6U, // VMRS_MVFR2 |
5584 | 1.35M | 0U, // VMSR |
5585 | 1.35M | 0U, // VMSR_FPEXC |
5586 | 1.35M | 0U, // VMSR_FPINST |
5587 | 1.35M | 0U, // VMSR_FPINST2 |
5588 | 1.35M | 0U, // VMSR_FPSID |
5589 | 1.35M | 70705U, // VMULD |
5590 | 1.35M | 70705U, // VMULH |
5591 | 1.35M | 1112U, // VMULLp64 |
5592 | 1.35M | 0U, // VMULLp8 |
5593 | 1.35M | 17496U, // VMULLslsv2i32 |
5594 | 1.35M | 17496U, // VMULLslsv4i16 |
5595 | 1.35M | 17496U, // VMULLsluv2i32 |
5596 | 1.35M | 17496U, // VMULLsluv4i16 |
5597 | 1.35M | 1112U, // VMULLsv2i64 |
5598 | 1.35M | 1112U, // VMULLsv4i32 |
5599 | 1.35M | 1112U, // VMULLsv8i16 |
5600 | 1.35M | 1112U, // VMULLuv2i64 |
5601 | 1.35M | 1112U, // VMULLuv4i32 |
5602 | 1.35M | 1112U, // VMULLuv8i16 |
5603 | 1.35M | 70705U, // VMULS |
5604 | 1.35M | 70705U, // VMULfd |
5605 | 1.35M | 70705U, // VMULfq |
5606 | 1.35M | 70705U, // VMULhd |
5607 | 1.35M | 70705U, // VMULhq |
5608 | 1.35M | 0U, // VMULpd |
5609 | 1.35M | 0U, // VMULpq |
5610 | 1.35M | 955441U, // VMULslfd |
5611 | 1.35M | 955441U, // VMULslfq |
5612 | 1.35M | 955441U, // VMULslhd |
5613 | 1.35M | 955441U, // VMULslhq |
5614 | 1.35M | 17496U, // VMULslv2i32 |
5615 | 1.35M | 17496U, // VMULslv4i16 |
5616 | 1.35M | 17496U, // VMULslv4i32 |
5617 | 1.35M | 17496U, // VMULslv8i16 |
5618 | 1.35M | 1112U, // VMULv16i8 |
5619 | 1.35M | 1112U, // VMULv2i32 |
5620 | 1.35M | 1112U, // VMULv4i16 |
5621 | 1.35M | 1112U, // VMULv4i32 |
5622 | 1.35M | 1112U, // VMULv8i16 |
5623 | 1.35M | 1112U, // VMULv8i8 |
5624 | 1.35M | 1024U, // VMVNd |
5625 | 1.35M | 1024U, // VMVNq |
5626 | 1.35M | 0U, // VMVNv2i32 |
5627 | 1.35M | 0U, // VMVNv4i16 |
5628 | 1.35M | 0U, // VMVNv4i32 |
5629 | 1.35M | 0U, // VMVNv8i16 |
5630 | 1.35M | 33U, // VNEGD |
5631 | 1.35M | 33U, // VNEGH |
5632 | 1.35M | 33U, // VNEGS |
5633 | 1.35M | 33U, // VNEGf32q |
5634 | 1.35M | 33U, // VNEGfd |
5635 | 1.35M | 33U, // VNEGhd |
5636 | 1.35M | 33U, // VNEGhq |
5637 | 1.35M | 0U, // VNEGs16d |
5638 | 1.35M | 0U, // VNEGs16q |
5639 | 1.35M | 0U, // VNEGs32d |
5640 | 1.35M | 0U, // VNEGs32q |
5641 | 1.35M | 0U, // VNEGs8d |
5642 | 1.35M | 0U, // VNEGs8q |
5643 | 1.35M | 68659U, // VNMLAD |
5644 | 1.35M | 68659U, // VNMLAH |
5645 | 1.35M | 68659U, // VNMLAS |
5646 | 1.35M | 68659U, // VNMLSD |
5647 | 1.35M | 68659U, // VNMLSH |
5648 | 1.35M | 68659U, // VNMLSS |
5649 | 1.35M | 70705U, // VNMULD |
5650 | 1.35M | 70705U, // VNMULH |
5651 | 1.35M | 70705U, // VNMULS |
5652 | 1.35M | 0U, // VORNd |
5653 | 1.35M | 0U, // VORNq |
5654 | 1.35M | 0U, // VORRd |
5655 | 1.35M | 0U, // VORRiv2i32 |
5656 | 1.35M | 0U, // VORRiv4i16 |
5657 | 1.35M | 0U, // VORRiv4i32 |
5658 | 1.35M | 0U, // VORRiv8i16 |
5659 | 1.35M | 0U, // VORRq |
5660 | 1.35M | 0U, // VPADALsv16i8 |
5661 | 1.35M | 0U, // VPADALsv2i32 |
5662 | 1.35M | 0U, // VPADALsv4i16 |
5663 | 1.35M | 0U, // VPADALsv4i32 |
5664 | 1.35M | 0U, // VPADALsv8i16 |
5665 | 1.35M | 0U, // VPADALsv8i8 |
5666 | 1.35M | 0U, // VPADALuv16i8 |
5667 | 1.35M | 0U, // VPADALuv2i32 |
5668 | 1.35M | 0U, // VPADALuv4i16 |
5669 | 1.35M | 0U, // VPADALuv4i32 |
5670 | 1.35M | 0U, // VPADALuv8i16 |
5671 | 1.35M | 0U, // VPADALuv8i8 |
5672 | 1.35M | 0U, // VPADDLsv16i8 |
5673 | 1.35M | 0U, // VPADDLsv2i32 |
5674 | 1.35M | 0U, // VPADDLsv4i16 |
5675 | 1.35M | 0U, // VPADDLsv4i32 |
5676 | 1.35M | 0U, // VPADDLsv8i16 |
5677 | 1.35M | 0U, // VPADDLsv8i8 |
5678 | 1.35M | 0U, // VPADDLuv16i8 |
5679 | 1.35M | 0U, // VPADDLuv2i32 |
5680 | 1.35M | 0U, // VPADDLuv4i16 |
5681 | 1.35M | 0U, // VPADDLuv4i32 |
5682 | 1.35M | 0U, // VPADDLuv8i16 |
5683 | 1.35M | 0U, // VPADDLuv8i8 |
5684 | 1.35M | 70705U, // VPADDf |
5685 | 1.35M | 70705U, // VPADDh |
5686 | 1.35M | 1112U, // VPADDi16 |
5687 | 1.35M | 1112U, // VPADDi32 |
5688 | 1.35M | 1112U, // VPADDi8 |
5689 | 1.35M | 70705U, // VPMAXf |
5690 | 1.35M | 70705U, // VPMAXh |
5691 | 1.35M | 1112U, // VPMAXs16 |
5692 | 1.35M | 1112U, // VPMAXs32 |
5693 | 1.35M | 1112U, // VPMAXs8 |
5694 | 1.35M | 1112U, // VPMAXu16 |
5695 | 1.35M | 1112U, // VPMAXu32 |
5696 | 1.35M | 1112U, // VPMAXu8 |
5697 | 1.35M | 70705U, // VPMINf |
5698 | 1.35M | 70705U, // VPMINh |
5699 | 1.35M | 1112U, // VPMINs16 |
5700 | 1.35M | 1112U, // VPMINs32 |
5701 | 1.35M | 1112U, // VPMINs8 |
5702 | 1.35M | 1112U, // VPMINu16 |
5703 | 1.35M | 1112U, // VPMINu32 |
5704 | 1.35M | 1112U, // VPMINu8 |
5705 | 1.35M | 0U, // VQABSv16i8 |
5706 | 1.35M | 0U, // VQABSv2i32 |
5707 | 1.35M | 0U, // VQABSv4i16 |
5708 | 1.35M | 0U, // VQABSv4i32 |
5709 | 1.35M | 0U, // VQABSv8i16 |
5710 | 1.35M | 0U, // VQABSv8i8 |
5711 | 1.35M | 1112U, // VQADDsv16i8 |
5712 | 1.35M | 1112U, // VQADDsv1i64 |
5713 | 1.35M | 1112U, // VQADDsv2i32 |
5714 | 1.35M | 1112U, // VQADDsv2i64 |
5715 | 1.35M | 1112U, // VQADDsv4i16 |
5716 | 1.35M | 1112U, // VQADDsv4i32 |
5717 | 1.35M | 1112U, // VQADDsv8i16 |
5718 | 1.35M | 1112U, // VQADDsv8i8 |
5719 | 1.35M | 1112U, // VQADDuv16i8 |
5720 | 1.35M | 1112U, // VQADDuv1i64 |
5721 | 1.35M | 1112U, // VQADDuv2i32 |
5722 | 1.35M | 1112U, // VQADDuv2i64 |
5723 | 1.35M | 1112U, // VQADDuv4i16 |
5724 | 1.35M | 1112U, // VQADDuv4i32 |
5725 | 1.35M | 1112U, // VQADDuv8i16 |
5726 | 1.35M | 1112U, // VQADDuv8i8 |
5727 | 1.35M | 73752U, // VQDMLALslv2i32 |
5728 | 1.35M | 73752U, // VQDMLALslv4i16 |
5729 | 1.35M | 1048U, // VQDMLALv2i64 |
5730 | 1.35M | 1048U, // VQDMLALv4i32 |
5731 | 1.35M | 73752U, // VQDMLSLslv2i32 |
5732 | 1.35M | 73752U, // VQDMLSLslv4i16 |
5733 | 1.35M | 1048U, // VQDMLSLv2i64 |
5734 | 1.35M | 1048U, // VQDMLSLv4i32 |
5735 | 1.35M | 17496U, // VQDMULHslv2i32 |
5736 | 1.35M | 17496U, // VQDMULHslv4i16 |
5737 | 1.35M | 17496U, // VQDMULHslv4i32 |
5738 | 1.35M | 17496U, // VQDMULHslv8i16 |
5739 | 1.35M | 1112U, // VQDMULHv2i32 |
5740 | 1.35M | 1112U, // VQDMULHv4i16 |
5741 | 1.35M | 1112U, // VQDMULHv4i32 |
5742 | 1.35M | 1112U, // VQDMULHv8i16 |
5743 | 1.35M | 17496U, // VQDMULLslv2i32 |
5744 | 1.35M | 17496U, // VQDMULLslv4i16 |
5745 | 1.35M | 1112U, // VQDMULLv2i64 |
5746 | 1.35M | 1112U, // VQDMULLv4i32 |
5747 | 1.35M | 0U, // VQMOVNsuv2i32 |
5748 | 1.35M | 0U, // VQMOVNsuv4i16 |
5749 | 1.35M | 0U, // VQMOVNsuv8i8 |
5750 | 1.35M | 0U, // VQMOVNsv2i32 |
5751 | 1.35M | 0U, // VQMOVNsv4i16 |
5752 | 1.35M | 0U, // VQMOVNsv8i8 |
5753 | 1.35M | 0U, // VQMOVNuv2i32 |
5754 | 1.35M | 0U, // VQMOVNuv4i16 |
5755 | 1.35M | 0U, // VQMOVNuv8i8 |
5756 | 1.35M | 0U, // VQNEGv16i8 |
5757 | 1.35M | 0U, // VQNEGv2i32 |
5758 | 1.35M | 0U, // VQNEGv4i16 |
5759 | 1.35M | 0U, // VQNEGv4i32 |
5760 | 1.35M | 0U, // VQNEGv8i16 |
5761 | 1.35M | 0U, // VQNEGv8i8 |
5762 | 1.35M | 73752U, // VQRDMLAHslv2i32 |
5763 | 1.35M | 73752U, // VQRDMLAHslv4i16 |
5764 | 1.35M | 73752U, // VQRDMLAHslv4i32 |
5765 | 1.35M | 73752U, // VQRDMLAHslv8i16 |
5766 | 1.35M | 1048U, // VQRDMLAHv2i32 |
5767 | 1.35M | 1048U, // VQRDMLAHv4i16 |
5768 | 1.35M | 1048U, // VQRDMLAHv4i32 |
5769 | 1.35M | 1048U, // VQRDMLAHv8i16 |
5770 | 1.35M | 73752U, // VQRDMLSHslv2i32 |
5771 | 1.35M | 73752U, // VQRDMLSHslv4i16 |
5772 | 1.35M | 73752U, // VQRDMLSHslv4i32 |
5773 | 1.35M | 73752U, // VQRDMLSHslv8i16 |
5774 | 1.35M | 1048U, // VQRDMLSHv2i32 |
5775 | 1.35M | 1048U, // VQRDMLSHv4i16 |
5776 | 1.35M | 1048U, // VQRDMLSHv4i32 |
5777 | 1.35M | 1048U, // VQRDMLSHv8i16 |
5778 | 1.35M | 17496U, // VQRDMULHslv2i32 |
5779 | 1.35M | 17496U, // VQRDMULHslv4i16 |
5780 | 1.35M | 17496U, // VQRDMULHslv4i32 |
5781 | 1.35M | 17496U, // VQRDMULHslv8i16 |
5782 | 1.35M | 1112U, // VQRDMULHv2i32 |
5783 | 1.35M | 1112U, // VQRDMULHv4i16 |
5784 | 1.35M | 1112U, // VQRDMULHv4i32 |
5785 | 1.35M | 1112U, // VQRDMULHv8i16 |
5786 | 1.35M | 1112U, // VQRSHLsv16i8 |
5787 | 1.35M | 1112U, // VQRSHLsv1i64 |
5788 | 1.35M | 1112U, // VQRSHLsv2i32 |
5789 | 1.35M | 1112U, // VQRSHLsv2i64 |
5790 | 1.35M | 1112U, // VQRSHLsv4i16 |
5791 | 1.35M | 1112U, // VQRSHLsv4i32 |
5792 | 1.35M | 1112U, // VQRSHLsv8i16 |
5793 | 1.35M | 1112U, // VQRSHLsv8i8 |
5794 | 1.35M | 1112U, // VQRSHLuv16i8 |
5795 | 1.35M | 1112U, // VQRSHLuv1i64 |
5796 | 1.35M | 1112U, // VQRSHLuv2i32 |
5797 | 1.35M | 1112U, // VQRSHLuv2i64 |
5798 | 1.35M | 1112U, // VQRSHLuv4i16 |
5799 | 1.35M | 1112U, // VQRSHLuv4i32 |
5800 | 1.35M | 1112U, // VQRSHLuv8i16 |
5801 | 1.35M | 1112U, // VQRSHLuv8i8 |
5802 | 1.35M | 1112U, // VQRSHRNsv2i32 |
5803 | 1.35M | 1112U, // VQRSHRNsv4i16 |
5804 | 1.35M | 1112U, // VQRSHRNsv8i8 |
5805 | 1.35M | 1112U, // VQRSHRNuv2i32 |
5806 | 1.35M | 1112U, // VQRSHRNuv4i16 |
5807 | 1.35M | 1112U, // VQRSHRNuv8i8 |
5808 | 1.35M | 1112U, // VQRSHRUNv2i32 |
5809 | 1.35M | 1112U, // VQRSHRUNv4i16 |
5810 | 1.35M | 1112U, // VQRSHRUNv8i8 |
5811 | 1.35M | 1112U, // VQSHLsiv16i8 |
5812 | 1.35M | 1112U, // VQSHLsiv1i64 |
5813 | 1.35M | 1112U, // VQSHLsiv2i32 |
5814 | 1.35M | 1112U, // VQSHLsiv2i64 |
5815 | 1.35M | 1112U, // VQSHLsiv4i16 |
5816 | 1.35M | 1112U, // VQSHLsiv4i32 |
5817 | 1.35M | 1112U, // VQSHLsiv8i16 |
5818 | 1.35M | 1112U, // VQSHLsiv8i8 |
5819 | 1.35M | 1112U, // VQSHLsuv16i8 |
5820 | 1.35M | 1112U, // VQSHLsuv1i64 |
5821 | 1.35M | 1112U, // VQSHLsuv2i32 |
5822 | 1.35M | 1112U, // VQSHLsuv2i64 |
5823 | 1.35M | 1112U, // VQSHLsuv4i16 |
5824 | 1.35M | 1112U, // VQSHLsuv4i32 |
5825 | 1.35M | 1112U, // VQSHLsuv8i16 |
5826 | 1.35M | 1112U, // VQSHLsuv8i8 |
5827 | 1.35M | 1112U, // VQSHLsv16i8 |
5828 | 1.35M | 1112U, // VQSHLsv1i64 |
5829 | 1.35M | 1112U, // VQSHLsv2i32 |
5830 | 1.35M | 1112U, // VQSHLsv2i64 |
5831 | 1.35M | 1112U, // VQSHLsv4i16 |
5832 | 1.35M | 1112U, // VQSHLsv4i32 |
5833 | 1.35M | 1112U, // VQSHLsv8i16 |
5834 | 1.35M | 1112U, // VQSHLsv8i8 |
5835 | 1.35M | 1112U, // VQSHLuiv16i8 |
5836 | 1.35M | 1112U, // VQSHLuiv1i64 |
5837 | 1.35M | 1112U, // VQSHLuiv2i32 |
5838 | 1.35M | 1112U, // VQSHLuiv2i64 |
5839 | 1.35M | 1112U, // VQSHLuiv4i16 |
5840 | 1.35M | 1112U, // VQSHLuiv4i32 |
5841 | 1.35M | 1112U, // VQSHLuiv8i16 |
5842 | 1.35M | 1112U, // VQSHLuiv8i8 |
5843 | 1.35M | 1112U, // VQSHLuv16i8 |
5844 | 1.35M | 1112U, // VQSHLuv1i64 |
5845 | 1.35M | 1112U, // VQSHLuv2i32 |
5846 | 1.35M | 1112U, // VQSHLuv2i64 |
5847 | 1.35M | 1112U, // VQSHLuv4i16 |
5848 | 1.35M | 1112U, // VQSHLuv4i32 |
5849 | 1.35M | 1112U, // VQSHLuv8i16 |
5850 | 1.35M | 1112U, // VQSHLuv8i8 |
5851 | 1.35M | 1112U, // VQSHRNsv2i32 |
5852 | 1.35M | 1112U, // VQSHRNsv4i16 |
5853 | 1.35M | 1112U, // VQSHRNsv8i8 |
5854 | 1.35M | 1112U, // VQSHRNuv2i32 |
5855 | 1.35M | 1112U, // VQSHRNuv4i16 |
5856 | 1.35M | 1112U, // VQSHRNuv8i8 |
5857 | 1.35M | 1112U, // VQSHRUNv2i32 |
5858 | 1.35M | 1112U, // VQSHRUNv4i16 |
5859 | 1.35M | 1112U, // VQSHRUNv8i8 |
5860 | 1.35M | 1112U, // VQSUBsv16i8 |
5861 | 1.35M | 1112U, // VQSUBsv1i64 |
5862 | 1.35M | 1112U, // VQSUBsv2i32 |
5863 | 1.35M | 1112U, // VQSUBsv2i64 |
5864 | 1.35M | 1112U, // VQSUBsv4i16 |
5865 | 1.35M | 1112U, // VQSUBsv4i32 |
5866 | 1.35M | 1112U, // VQSUBsv8i16 |
5867 | 1.35M | 1112U, // VQSUBsv8i8 |
5868 | 1.35M | 1112U, // VQSUBuv16i8 |
5869 | 1.35M | 1112U, // VQSUBuv1i64 |
5870 | 1.35M | 1112U, // VQSUBuv2i32 |
5871 | 1.35M | 1112U, // VQSUBuv2i64 |
5872 | 1.35M | 1112U, // VQSUBuv4i16 |
5873 | 1.35M | 1112U, // VQSUBuv4i32 |
5874 | 1.35M | 1112U, // VQSUBuv8i16 |
5875 | 1.35M | 1112U, // VQSUBuv8i8 |
5876 | 1.35M | 1112U, // VRADDHNv2i32 |
5877 | 1.35M | 1112U, // VRADDHNv4i16 |
5878 | 1.35M | 1112U, // VRADDHNv8i8 |
5879 | 1.35M | 0U, // VRECPEd |
5880 | 1.35M | 33U, // VRECPEfd |
5881 | 1.35M | 33U, // VRECPEfq |
5882 | 1.35M | 33U, // VRECPEhd |
5883 | 1.35M | 33U, // VRECPEhq |
5884 | 1.35M | 0U, // VRECPEq |
5885 | 1.35M | 70705U, // VRECPSfd |
5886 | 1.35M | 70705U, // VRECPSfq |
5887 | 1.35M | 70705U, // VRECPShd |
5888 | 1.35M | 70705U, // VRECPShq |
5889 | 1.35M | 1024U, // VREV16d8 |
5890 | 1.35M | 1024U, // VREV16q8 |
5891 | 1.35M | 1024U, // VREV32d16 |
5892 | 1.35M | 1024U, // VREV32d8 |
5893 | 1.35M | 1024U, // VREV32q16 |
5894 | 1.35M | 1024U, // VREV32q8 |
5895 | 1.35M | 1024U, // VREV64d16 |
5896 | 1.35M | 1024U, // VREV64d32 |
5897 | 1.35M | 1024U, // VREV64d8 |
5898 | 1.35M | 1024U, // VREV64q16 |
5899 | 1.35M | 1024U, // VREV64q32 |
5900 | 1.35M | 1024U, // VREV64q8 |
5901 | 1.35M | 1112U, // VRHADDsv16i8 |
5902 | 1.35M | 1112U, // VRHADDsv2i32 |
5903 | 1.35M | 1112U, // VRHADDsv4i16 |
5904 | 1.35M | 1112U, // VRHADDsv4i32 |
5905 | 1.35M | 1112U, // VRHADDsv8i16 |
5906 | 1.35M | 1112U, // VRHADDsv8i8 |
5907 | 1.35M | 1112U, // VRHADDuv16i8 |
5908 | 1.35M | 1112U, // VRHADDuv2i32 |
5909 | 1.35M | 1112U, // VRHADDuv4i16 |
5910 | 1.35M | 1112U, // VRHADDuv4i32 |
5911 | 1.35M | 1112U, // VRHADDuv8i16 |
5912 | 1.35M | 1112U, // VRHADDuv8i8 |
5913 | 1.35M | 0U, // VRINTAD |
5914 | 1.35M | 0U, // VRINTAH |
5915 | 1.35M | 0U, // VRINTANDf |
5916 | 1.35M | 0U, // VRINTANDh |
5917 | 1.35M | 0U, // VRINTANQf |
5918 | 1.35M | 0U, // VRINTANQh |
5919 | 1.35M | 0U, // VRINTAS |
5920 | 1.35M | 0U, // VRINTMD |
5921 | 1.35M | 0U, // VRINTMH |
5922 | 1.35M | 0U, // VRINTMNDf |
5923 | 1.35M | 0U, // VRINTMNDh |
5924 | 1.35M | 0U, // VRINTMNQf |
5925 | 1.35M | 0U, // VRINTMNQh |
5926 | 1.35M | 0U, // VRINTMS |
5927 | 1.35M | 0U, // VRINTND |
5928 | 1.35M | 0U, // VRINTNH |
5929 | 1.35M | 0U, // VRINTNNDf |
5930 | 1.35M | 0U, // VRINTNNDh |
5931 | 1.35M | 0U, // VRINTNNQf |
5932 | 1.35M | 0U, // VRINTNNQh |
5933 | 1.35M | 0U, // VRINTNS |
5934 | 1.35M | 0U, // VRINTPD |
5935 | 1.35M | 0U, // VRINTPH |
5936 | 1.35M | 0U, // VRINTPNDf |
5937 | 1.35M | 0U, // VRINTPNDh |
5938 | 1.35M | 0U, // VRINTPNQf |
5939 | 1.35M | 0U, // VRINTPNQh |
5940 | 1.35M | 0U, // VRINTPS |
5941 | 1.35M | 33U, // VRINTRD |
5942 | 1.35M | 33U, // VRINTRH |
5943 | 1.35M | 33U, // VRINTRS |
5944 | 1.35M | 33U, // VRINTXD |
5945 | 1.35M | 33U, // VRINTXH |
5946 | 1.35M | 0U, // VRINTXNDf |
5947 | 1.35M | 0U, // VRINTXNDh |
5948 | 1.35M | 0U, // VRINTXNQf |
5949 | 1.35M | 0U, // VRINTXNQh |
5950 | 1.35M | 33U, // VRINTXS |
5951 | 1.35M | 33U, // VRINTZD |
5952 | 1.35M | 33U, // VRINTZH |
5953 | 1.35M | 0U, // VRINTZNDf |
5954 | 1.35M | 0U, // VRINTZNDh |
5955 | 1.35M | 0U, // VRINTZNQf |
5956 | 1.35M | 0U, // VRINTZNQh |
5957 | 1.35M | 33U, // VRINTZS |
5958 | 1.35M | 1112U, // VRSHLsv16i8 |
5959 | 1.35M | 1112U, // VRSHLsv1i64 |
5960 | 1.35M | 1112U, // VRSHLsv2i32 |
5961 | 1.35M | 1112U, // VRSHLsv2i64 |
5962 | 1.35M | 1112U, // VRSHLsv4i16 |
5963 | 1.35M | 1112U, // VRSHLsv4i32 |
5964 | 1.35M | 1112U, // VRSHLsv8i16 |
5965 | 1.35M | 1112U, // VRSHLsv8i8 |
5966 | 1.35M | 1112U, // VRSHLuv16i8 |
5967 | 1.35M | 1112U, // VRSHLuv1i64 |
5968 | 1.35M | 1112U, // VRSHLuv2i32 |
5969 | 1.35M | 1112U, // VRSHLuv2i64 |
5970 | 1.35M | 1112U, // VRSHLuv4i16 |
5971 | 1.35M | 1112U, // VRSHLuv4i32 |
5972 | 1.35M | 1112U, // VRSHLuv8i16 |
5973 | 1.35M | 1112U, // VRSHLuv8i8 |
5974 | 1.35M | 1112U, // VRSHRNv2i32 |
5975 | 1.35M | 1112U, // VRSHRNv4i16 |
5976 | 1.35M | 1112U, // VRSHRNv8i8 |
5977 | 1.35M | 1112U, // VRSHRsv16i8 |
5978 | 1.35M | 1112U, // VRSHRsv1i64 |
5979 | 1.35M | 1112U, // VRSHRsv2i32 |
5980 | 1.35M | 1112U, // VRSHRsv2i64 |
5981 | 1.35M | 1112U, // VRSHRsv4i16 |
5982 | 1.35M | 1112U, // VRSHRsv4i32 |
5983 | 1.35M | 1112U, // VRSHRsv8i16 |
5984 | 1.35M | 1112U, // VRSHRsv8i8 |
5985 | 1.35M | 1112U, // VRSHRuv16i8 |
5986 | 1.35M | 1112U, // VRSHRuv1i64 |
5987 | 1.35M | 1112U, // VRSHRuv2i32 |
5988 | 1.35M | 1112U, // VRSHRuv2i64 |
5989 | 1.35M | 1112U, // VRSHRuv4i16 |
5990 | 1.35M | 1112U, // VRSHRuv4i32 |
5991 | 1.35M | 1112U, // VRSHRuv8i16 |
5992 | 1.35M | 1112U, // VRSHRuv8i8 |
5993 | 1.35M | 0U, // VRSQRTEd |
5994 | 1.35M | 33U, // VRSQRTEfd |
5995 | 1.35M | 33U, // VRSQRTEfq |
5996 | 1.35M | 33U, // VRSQRTEhd |
5997 | 1.35M | 33U, // VRSQRTEhq |
5998 | 1.35M | 0U, // VRSQRTEq |
5999 | 1.35M | 70705U, // VRSQRTSfd |
6000 | 1.35M | 70705U, // VRSQRTSfq |
6001 | 1.35M | 70705U, // VRSQRTShd |
6002 | 1.35M | 70705U, // VRSQRTShq |
6003 | 1.35M | 1048U, // VRSRAsv16i8 |
6004 | 1.35M | 1048U, // VRSRAsv1i64 |
6005 | 1.35M | 1048U, // VRSRAsv2i32 |
6006 | 1.35M | 1048U, // VRSRAsv2i64 |
6007 | 1.35M | 1048U, // VRSRAsv4i16 |
6008 | 1.35M | 1048U, // VRSRAsv4i32 |
6009 | 1.35M | 1048U, // VRSRAsv8i16 |
6010 | 1.35M | 1048U, // VRSRAsv8i8 |
6011 | 1.35M | 1048U, // VRSRAuv16i8 |
6012 | 1.35M | 1048U, // VRSRAuv1i64 |
6013 | 1.35M | 1048U, // VRSRAuv2i32 |
6014 | 1.35M | 1048U, // VRSRAuv2i64 |
6015 | 1.35M | 1048U, // VRSRAuv4i16 |
6016 | 1.35M | 1048U, // VRSRAuv4i32 |
6017 | 1.35M | 1048U, // VRSRAuv8i16 |
6018 | 1.35M | 1048U, // VRSRAuv8i8 |
6019 | 1.35M | 1112U, // VRSUBHNv2i32 |
6020 | 1.35M | 1112U, // VRSUBHNv4i16 |
6021 | 1.35M | 1112U, // VRSUBHNv8i8 |
6022 | 1.35M | 0U, // VSDOTD |
6023 | 1.35M | 0U, // VSDOTDI |
6024 | 1.35M | 0U, // VSDOTQ |
6025 | 1.35M | 0U, // VSDOTQI |
6026 | 1.35M | 1112U, // VSELEQD |
6027 | 1.35M | 1112U, // VSELEQH |
6028 | 1.35M | 1112U, // VSELEQS |
6029 | 1.35M | 1112U, // VSELGED |
6030 | 1.35M | 1112U, // VSELGEH |
6031 | 1.35M | 1112U, // VSELGES |
6032 | 1.35M | 1112U, // VSELGTD |
6033 | 1.35M | 1112U, // VSELGTH |
6034 | 1.35M | 1112U, // VSELGTS |
6035 | 1.35M | 1112U, // VSELVSD |
6036 | 1.35M | 1112U, // VSELVSH |
6037 | 1.35M | 1112U, // VSELVSS |
6038 | 1.35M | 6U, // VSETLNi16 |
6039 | 1.35M | 6U, // VSETLNi32 |
6040 | 1.35M | 6U, // VSETLNi8 |
6041 | 1.35M | 1112U, // VSHLLi16 |
6042 | 1.35M | 1112U, // VSHLLi32 |
6043 | 1.35M | 1112U, // VSHLLi8 |
6044 | 1.35M | 1112U, // VSHLLsv2i64 |
6045 | 1.35M | 1112U, // VSHLLsv4i32 |
6046 | 1.35M | 1112U, // VSHLLsv8i16 |
6047 | 1.35M | 1112U, // VSHLLuv2i64 |
6048 | 1.35M | 1112U, // VSHLLuv4i32 |
6049 | 1.35M | 1112U, // VSHLLuv8i16 |
6050 | 1.35M | 1112U, // VSHLiv16i8 |
6051 | 1.35M | 1112U, // VSHLiv1i64 |
6052 | 1.35M | 1112U, // VSHLiv2i32 |
6053 | 1.35M | 1112U, // VSHLiv2i64 |
6054 | 1.35M | 1112U, // VSHLiv4i16 |
6055 | 1.35M | 1112U, // VSHLiv4i32 |
6056 | 1.35M | 1112U, // VSHLiv8i16 |
6057 | 1.35M | 1112U, // VSHLiv8i8 |
6058 | 1.35M | 1112U, // VSHLsv16i8 |
6059 | 1.35M | 1112U, // VSHLsv1i64 |
6060 | 1.35M | 1112U, // VSHLsv2i32 |
6061 | 1.35M | 1112U, // VSHLsv2i64 |
6062 | 1.35M | 1112U, // VSHLsv4i16 |
6063 | 1.35M | 1112U, // VSHLsv4i32 |
6064 | 1.35M | 1112U, // VSHLsv8i16 |
6065 | 1.35M | 1112U, // VSHLsv8i8 |
6066 | 1.35M | 1112U, // VSHLuv16i8 |
6067 | 1.35M | 1112U, // VSHLuv1i64 |
6068 | 1.35M | 1112U, // VSHLuv2i32 |
6069 | 1.35M | 1112U, // VSHLuv2i64 |
6070 | 1.35M | 1112U, // VSHLuv4i16 |
6071 | 1.35M | 1112U, // VSHLuv4i32 |
6072 | 1.35M | 1112U, // VSHLuv8i16 |
6073 | 1.35M | 1112U, // VSHLuv8i8 |
6074 | 1.35M | 1112U, // VSHRNv2i32 |
6075 | 1.35M | 1112U, // VSHRNv4i16 |
6076 | 1.35M | 1112U, // VSHRNv8i8 |
6077 | 1.35M | 1112U, // VSHRsv16i8 |
6078 | 1.35M | 1112U, // VSHRsv1i64 |
6079 | 1.35M | 1112U, // VSHRsv2i32 |
6080 | 1.35M | 1112U, // VSHRsv2i64 |
6081 | 1.35M | 1112U, // VSHRsv4i16 |
6082 | 1.35M | 1112U, // VSHRsv4i32 |
6083 | 1.35M | 1112U, // VSHRsv8i16 |
6084 | 1.35M | 1112U, // VSHRsv8i8 |
6085 | 1.35M | 1112U, // VSHRuv16i8 |
6086 | 1.35M | 1112U, // VSHRuv1i64 |
6087 | 1.35M | 1112U, // VSHRuv2i32 |
6088 | 1.35M | 1112U, // VSHRuv2i64 |
6089 | 1.35M | 1112U, // VSHRuv4i16 |
6090 | 1.35M | 1112U, // VSHRuv4i32 |
6091 | 1.35M | 1112U, // VSHRuv8i16 |
6092 | 1.35M | 1112U, // VSHRuv8i8 |
6093 | 1.35M | 0U, // VSHTOD |
6094 | 1.35M | 7U, // VSHTOH |
6095 | 1.35M | 0U, // VSHTOS |
6096 | 1.35M | 0U, // VSITOD |
6097 | 1.35M | 0U, // VSITOH |
6098 | 1.35M | 0U, // VSITOS |
6099 | 1.35M | 589912U, // VSLIv16i8 |
6100 | 1.35M | 589912U, // VSLIv1i64 |
6101 | 1.35M | 589912U, // VSLIv2i32 |
6102 | 1.35M | 589912U, // VSLIv2i64 |
6103 | 1.35M | 589912U, // VSLIv4i16 |
6104 | 1.35M | 589912U, // VSLIv4i32 |
6105 | 1.35M | 589912U, // VSLIv8i16 |
6106 | 1.35M | 589912U, // VSLIv8i8 |
6107 | 1.35M | 7U, // VSLTOD |
6108 | 1.35M | 7U, // VSLTOH |
6109 | 1.35M | 7U, // VSLTOS |
6110 | 1.35M | 33U, // VSQRTD |
6111 | 1.35M | 33U, // VSQRTH |
6112 | 1.35M | 33U, // VSQRTS |
6113 | 1.35M | 1048U, // VSRAsv16i8 |
6114 | 1.35M | 1048U, // VSRAsv1i64 |
6115 | 1.35M | 1048U, // VSRAsv2i32 |
6116 | 1.35M | 1048U, // VSRAsv2i64 |
6117 | 1.35M | 1048U, // VSRAsv4i16 |
6118 | 1.35M | 1048U, // VSRAsv4i32 |
6119 | 1.35M | 1048U, // VSRAsv8i16 |
6120 | 1.35M | 1048U, // VSRAsv8i8 |
6121 | 1.35M | 1048U, // VSRAuv16i8 |
6122 | 1.35M | 1048U, // VSRAuv1i64 |
6123 | 1.35M | 1048U, // VSRAuv2i32 |
6124 | 1.35M | 1048U, // VSRAuv2i64 |
6125 | 1.35M | 1048U, // VSRAuv4i16 |
6126 | 1.35M | 1048U, // VSRAuv4i32 |
6127 | 1.35M | 1048U, // VSRAuv8i16 |
6128 | 1.35M | 1048U, // VSRAuv8i8 |
6129 | 1.35M | 589912U, // VSRIv16i8 |
6130 | 1.35M | 589912U, // VSRIv1i64 |
6131 | 1.35M | 589912U, // VSRIv2i32 |
6132 | 1.35M | 589912U, // VSRIv2i64 |
6133 | 1.35M | 589912U, // VSRIv4i16 |
6134 | 1.35M | 589912U, // VSRIv4i32 |
6135 | 1.35M | 589912U, // VSRIv8i16 |
6136 | 1.35M | 589912U, // VSRIv8i8 |
6137 | 1.35M | 308U, // VST1LNd16 |
6138 | 1.35M | 23768380U, // VST1LNd16_UPD |
6139 | 1.35M | 308U, // VST1LNd32 |
6140 | 1.35M | 23768380U, // VST1LNd32_UPD |
6141 | 1.35M | 308U, // VST1LNd8 |
6142 | 1.35M | 23768380U, // VST1LNd8_UPD |
6143 | 1.35M | 0U, // VST1LNq16Pseudo |
6144 | 1.35M | 0U, // VST1LNq16Pseudo_UPD |
6145 | 1.35M | 0U, // VST1LNq32Pseudo |
6146 | 1.35M | 0U, // VST1LNq32Pseudo_UPD |
6147 | 1.35M | 0U, // VST1LNq8Pseudo |
6148 | 1.35M | 0U, // VST1LNq8Pseudo_UPD |
6149 | 1.35M | 0U, // VST1d16 |
6150 | 1.35M | 0U, // VST1d16Q |
6151 | 1.35M | 0U, // VST1d16QPseudo |
6152 | 1.35M | 0U, // VST1d16Qwb_fixed |
6153 | 1.35M | 0U, // VST1d16Qwb_register |
6154 | 1.35M | 0U, // VST1d16T |
6155 | 1.35M | 0U, // VST1d16TPseudo |
6156 | 1.35M | 0U, // VST1d16Twb_fixed |
6157 | 1.35M | 0U, // VST1d16Twb_register |
6158 | 1.35M | 0U, // VST1d16wb_fixed |
6159 | 1.35M | 0U, // VST1d16wb_register |
6160 | 1.35M | 0U, // VST1d32 |
6161 | 1.35M | 0U, // VST1d32Q |
6162 | 1.35M | 0U, // VST1d32QPseudo |
6163 | 1.35M | 0U, // VST1d32Qwb_fixed |
6164 | 1.35M | 0U, // VST1d32Qwb_register |
6165 | 1.35M | 0U, // VST1d32T |
6166 | 1.35M | 0U, // VST1d32TPseudo |
6167 | 1.35M | 0U, // VST1d32Twb_fixed |
6168 | 1.35M | 0U, // VST1d32Twb_register |
6169 | 1.35M | 0U, // VST1d32wb_fixed |
6170 | 1.35M | 0U, // VST1d32wb_register |
6171 | 1.35M | 0U, // VST1d64 |
6172 | 1.35M | 0U, // VST1d64Q |
6173 | 1.35M | 0U, // VST1d64QPseudo |
6174 | 1.35M | 0U, // VST1d64QPseudoWB_fixed |
6175 | 1.35M | 0U, // VST1d64QPseudoWB_register |
6176 | 1.35M | 0U, // VST1d64Qwb_fixed |
6177 | 1.35M | 0U, // VST1d64Qwb_register |
6178 | 1.35M | 0U, // VST1d64T |
6179 | 1.35M | 0U, // VST1d64TPseudo |
6180 | 1.35M | 0U, // VST1d64TPseudoWB_fixed |
6181 | 1.35M | 0U, // VST1d64TPseudoWB_register |
6182 | 1.35M | 0U, // VST1d64Twb_fixed |
6183 | 1.35M | 0U, // VST1d64Twb_register |
6184 | 1.35M | 0U, // VST1d64wb_fixed |
6185 | 1.35M | 0U, // VST1d64wb_register |
6186 | 1.35M | 0U, // VST1d8 |
6187 | 1.35M | 0U, // VST1d8Q |
6188 | 1.35M | 0U, // VST1d8QPseudo |
6189 | 1.35M | 0U, // VST1d8Qwb_fixed |
6190 | 1.35M | 0U, // VST1d8Qwb_register |
6191 | 1.35M | 0U, // VST1d8T |
6192 | 1.35M | 0U, // VST1d8TPseudo |
6193 | 1.35M | 0U, // VST1d8Twb_fixed |
6194 | 1.35M | 0U, // VST1d8Twb_register |
6195 | 1.35M | 0U, // VST1d8wb_fixed |
6196 | 1.35M | 0U, // VST1d8wb_register |
6197 | 1.35M | 0U, // VST1q16 |
6198 | 1.35M | 0U, // VST1q16HighQPseudo |
6199 | 1.35M | 0U, // VST1q16HighTPseudo |
6200 | 1.35M | 0U, // VST1q16LowQPseudo_UPD |
6201 | 1.35M | 0U, // VST1q16LowTPseudo_UPD |
6202 | 1.35M | 0U, // VST1q16wb_fixed |
6203 | 1.35M | 0U, // VST1q16wb_register |
6204 | 1.35M | 0U, // VST1q32 |
6205 | 1.35M | 0U, // VST1q32HighQPseudo |
6206 | 1.35M | 0U, // VST1q32HighTPseudo |
6207 | 1.35M | 0U, // VST1q32LowQPseudo_UPD |
6208 | 1.35M | 0U, // VST1q32LowTPseudo_UPD |
6209 | 1.35M | 0U, // VST1q32wb_fixed |
6210 | 1.35M | 0U, // VST1q32wb_register |
6211 | 1.35M | 0U, // VST1q64 |
6212 | 1.35M | 0U, // VST1q64HighQPseudo |
6213 | 1.35M | 0U, // VST1q64HighTPseudo |
6214 | 1.35M | 0U, // VST1q64LowQPseudo_UPD |
6215 | 1.35M | 0U, // VST1q64LowTPseudo_UPD |
6216 | 1.35M | 0U, // VST1q64wb_fixed |
6217 | 1.35M | 0U, // VST1q64wb_register |
6218 | 1.35M | 0U, // VST1q8 |
6219 | 1.35M | 0U, // VST1q8HighQPseudo |
6220 | 1.35M | 0U, // VST1q8HighTPseudo |
6221 | 1.35M | 0U, // VST1q8LowQPseudo_UPD |
6222 | 1.35M | 0U, // VST1q8LowTPseudo_UPD |
6223 | 1.35M | 0U, // VST1q8wb_fixed |
6224 | 1.35M | 0U, // VST1q8wb_register |
6225 | 1.35M | 222900460U, // VST2LNd16 |
6226 | 1.35M | 0U, // VST2LNd16Pseudo |
6227 | 1.35M | 0U, // VST2LNd16Pseudo_UPD |
6228 | 1.35M | 995572U, // VST2LNd16_UPD |
6229 | 1.35M | 222900460U, // VST2LNd32 |
6230 | 1.35M | 0U, // VST2LNd32Pseudo |
6231 | 1.35M | 0U, // VST2LNd32Pseudo_UPD |
6232 | 1.35M | 995572U, // VST2LNd32_UPD |
6233 | 1.35M | 222900460U, // VST2LNd8 |
6234 | 1.35M | 0U, // VST2LNd8Pseudo |
6235 | 1.35M | 0U, // VST2LNd8Pseudo_UPD |
6236 | 1.35M | 995572U, // VST2LNd8_UPD |
6237 | 1.35M | 222900460U, // VST2LNq16 |
6238 | 1.35M | 0U, // VST2LNq16Pseudo |
6239 | 1.35M | 0U, // VST2LNq16Pseudo_UPD |
6240 | 1.35M | 995572U, // VST2LNq16_UPD |
6241 | 1.35M | 222900460U, // VST2LNq32 |
6242 | 1.35M | 0U, // VST2LNq32Pseudo |
6243 | 1.35M | 0U, // VST2LNq32Pseudo_UPD |
6244 | 1.35M | 995572U, // VST2LNq32_UPD |
6245 | 1.35M | 0U, // VST2b16 |
6246 | 1.35M | 0U, // VST2b16wb_fixed |
6247 | 1.35M | 0U, // VST2b16wb_register |
6248 | 1.35M | 0U, // VST2b32 |
6249 | 1.35M | 0U, // VST2b32wb_fixed |
6250 | 1.35M | 0U, // VST2b32wb_register |
6251 | 1.35M | 0U, // VST2b8 |
6252 | 1.35M | 0U, // VST2b8wb_fixed |
6253 | 1.35M | 0U, // VST2b8wb_register |
6254 | 1.35M | 0U, // VST2d16 |
6255 | 1.35M | 0U, // VST2d16wb_fixed |
6256 | 1.35M | 0U, // VST2d16wb_register |
6257 | 1.35M | 0U, // VST2d32 |
6258 | 1.35M | 0U, // VST2d32wb_fixed |
6259 | 1.35M | 0U, // VST2d32wb_register |
6260 | 1.35M | 0U, // VST2d8 |
6261 | 1.35M | 0U, // VST2d8wb_fixed |
6262 | 1.35M | 0U, // VST2d8wb_register |
6263 | 1.35M | 0U, // VST2q16 |
6264 | 1.35M | 0U, // VST2q16Pseudo |
6265 | 1.35M | 0U, // VST2q16PseudoWB_fixed |
6266 | 1.35M | 0U, // VST2q16PseudoWB_register |
6267 | 1.35M | 0U, // VST2q16wb_fixed |
6268 | 1.35M | 0U, // VST2q16wb_register |
6269 | 1.35M | 0U, // VST2q32 |
6270 | 1.35M | 0U, // VST2q32Pseudo |
6271 | 1.35M | 0U, // VST2q32PseudoWB_fixed |
6272 | 1.35M | 0U, // VST2q32PseudoWB_register |
6273 | 1.35M | 0U, // VST2q32wb_fixed |
6274 | 1.35M | 0U, // VST2q32wb_register |
6275 | 1.35M | 0U, // VST2q8 |
6276 | 1.35M | 0U, // VST2q8Pseudo |
6277 | 1.35M | 0U, // VST2q8PseudoWB_fixed |
6278 | 1.35M | 0U, // VST2q8PseudoWB_register |
6279 | 1.35M | 0U, // VST2q8wb_fixed |
6280 | 1.35M | 0U, // VST2q8wb_register |
6281 | 1.35M | 256454972U, // VST3LNd16 |
6282 | 1.35M | 0U, // VST3LNd16Pseudo |
6283 | 1.35M | 0U, // VST3LNd16Pseudo_UPD |
6284 | 1.35M | 324U, // VST3LNd16_UPD |
6285 | 1.35M | 256454972U, // VST3LNd32 |
6286 | 1.35M | 0U, // VST3LNd32Pseudo |
6287 | 1.35M | 0U, // VST3LNd32Pseudo_UPD |
6288 | 1.35M | 324U, // VST3LNd32_UPD |
6289 | 1.35M | 256454972U, // VST3LNd8 |
6290 | 1.35M | 0U, // VST3LNd8Pseudo |
6291 | 1.35M | 0U, // VST3LNd8Pseudo_UPD |
6292 | 1.35M | 324U, // VST3LNd8_UPD |
6293 | 1.35M | 256454972U, // VST3LNq16 |
6294 | 1.35M | 0U, // VST3LNq16Pseudo |
6295 | 1.35M | 0U, // VST3LNq16Pseudo_UPD |
6296 | 1.35M | 324U, // VST3LNq16_UPD |
6297 | 1.35M | 256454972U, // VST3LNq32 |
6298 | 1.35M | 0U, // VST3LNq32Pseudo |
6299 | 1.35M | 0U, // VST3LNq32Pseudo_UPD |
6300 | 1.35M | 324U, // VST3LNq32_UPD |
6301 | 1.35M | 287342616U, // VST3d16 |
6302 | 1.35M | 0U, // VST3d16Pseudo |
6303 | 1.35M | 0U, // VST3d16Pseudo_UPD |
6304 | 1.35M | 18760U, // VST3d16_UPD |
6305 | 1.35M | 287342616U, // VST3d32 |
6306 | 1.35M | 0U, // VST3d32Pseudo |
6307 | 1.35M | 0U, // VST3d32Pseudo_UPD |
6308 | 1.35M | 18760U, // VST3d32_UPD |
6309 | 1.35M | 287342616U, // VST3d8 |
6310 | 1.35M | 0U, // VST3d8Pseudo |
6311 | 1.35M | 0U, // VST3d8Pseudo_UPD |
6312 | 1.35M | 18760U, // VST3d8_UPD |
6313 | 1.35M | 287342616U, // VST3q16 |
6314 | 1.35M | 0U, // VST3q16Pseudo_UPD |
6315 | 1.35M | 18760U, // VST3q16_UPD |
6316 | 1.35M | 0U, // VST3q16oddPseudo |
6317 | 1.35M | 0U, // VST3q16oddPseudo_UPD |
6318 | 1.35M | 287342616U, // VST3q32 |
6319 | 1.35M | 0U, // VST3q32Pseudo_UPD |
6320 | 1.35M | 18760U, // VST3q32_UPD |
6321 | 1.35M | 0U, // VST3q32oddPseudo |
6322 | 1.35M | 0U, // VST3q32oddPseudo_UPD |
6323 | 1.35M | 287342616U, // VST3q8 |
6324 | 1.35M | 0U, // VST3q8Pseudo_UPD |
6325 | 1.35M | 18760U, // VST3q8_UPD |
6326 | 1.35M | 0U, // VST3q8oddPseudo |
6327 | 1.35M | 0U, // VST3q8oddPseudo_UPD |
6328 | 1.35M | 323563764U, // VST4LNd16 |
6329 | 1.35M | 0U, // VST4LNd16Pseudo |
6330 | 1.35M | 0U, // VST4LNd16Pseudo_UPD |
6331 | 1.35M | 19708U, // VST4LNd16_UPD |
6332 | 1.35M | 323563764U, // VST4LNd32 |
6333 | 1.35M | 0U, // VST4LNd32Pseudo |
6334 | 1.35M | 0U, // VST4LNd32Pseudo_UPD |
6335 | 1.35M | 19708U, // VST4LNd32_UPD |
6336 | 1.35M | 323563764U, // VST4LNd8 |
6337 | 1.35M | 0U, // VST4LNd8Pseudo |
6338 | 1.35M | 0U, // VST4LNd8Pseudo_UPD |
6339 | 1.35M | 19708U, // VST4LNd8_UPD |
6340 | 1.35M | 323563764U, // VST4LNq16 |
6341 | 1.35M | 0U, // VST4LNq16Pseudo |
6342 | 1.35M | 0U, // VST4LNq16Pseudo_UPD |
6343 | 1.35M | 19708U, // VST4LNq16_UPD |
6344 | 1.35M | 323563764U, // VST4LNq32 |
6345 | 1.35M | 0U, // VST4LNq32Pseudo |
6346 | 1.35M | 0U, // VST4LNq32Pseudo_UPD |
6347 | 1.35M | 19708U, // VST4LNq32_UPD |
6348 | 1.35M | 337674264U, // VST4d16 |
6349 | 1.35M | 0U, // VST4d16Pseudo |
6350 | 1.35M | 0U, // VST4d16Pseudo_UPD |
6351 | 1.35M | 1016136U, // VST4d16_UPD |
6352 | 1.35M | 337674264U, // VST4d32 |
6353 | 1.35M | 0U, // VST4d32Pseudo |
6354 | 1.35M | 0U, // VST4d32Pseudo_UPD |
6355 | 1.35M | 1016136U, // VST4d32_UPD |
6356 | 1.35M | 337674264U, // VST4d8 |
6357 | 1.35M | 0U, // VST4d8Pseudo |
6358 | 1.35M | 0U, // VST4d8Pseudo_UPD |
6359 | 1.35M | 1016136U, // VST4d8_UPD |
6360 | 1.35M | 337674264U, // VST4q16 |
6361 | 1.35M | 0U, // VST4q16Pseudo_UPD |
6362 | 1.35M | 1016136U, // VST4q16_UPD |
6363 | 1.35M | 0U, // VST4q16oddPseudo |
6364 | 1.35M | 0U, // VST4q16oddPseudo_UPD |
6365 | 1.35M | 337674264U, // VST4q32 |
6366 | 1.35M | 0U, // VST4q32Pseudo_UPD |
6367 | 1.35M | 1016136U, // VST4q32_UPD |
6368 | 1.35M | 0U, // VST4q32oddPseudo |
6369 | 1.35M | 0U, // VST4q32oddPseudo_UPD |
6370 | 1.35M | 337674264U, // VST4q8 |
6371 | 1.35M | 0U, // VST4q8Pseudo_UPD |
6372 | 1.35M | 1016136U, // VST4q8_UPD |
6373 | 1.35M | 0U, // VST4q8oddPseudo |
6374 | 1.35M | 0U, // VST4q8oddPseudo_UPD |
6375 | 1.35M | 33U, // VSTMDDB_UPD |
6376 | 1.35M | 1136U, // VSTMDIA |
6377 | 1.35M | 33U, // VSTMDIA_UPD |
6378 | 1.35M | 0U, // VSTMQIA |
6379 | 1.35M | 33U, // VSTMSDB_UPD |
6380 | 1.35M | 1136U, // VSTMSIA |
6381 | 1.35M | 33U, // VSTMSIA_UPD |
6382 | 1.35M | 288U, // VSTRD |
6383 | 1.35M | 296U, // VSTRH |
6384 | 1.35M | 288U, // VSTRS |
6385 | 1.35M | 70705U, // VSUBD |
6386 | 1.35M | 70705U, // VSUBH |
6387 | 1.35M | 1112U, // VSUBHNv2i32 |
6388 | 1.35M | 1112U, // VSUBHNv4i16 |
6389 | 1.35M | 1112U, // VSUBHNv8i8 |
6390 | 1.35M | 1112U, // VSUBLsv2i64 |
6391 | 1.35M | 1112U, // VSUBLsv4i32 |
6392 | 1.35M | 1112U, // VSUBLsv8i16 |
6393 | 1.35M | 1112U, // VSUBLuv2i64 |
6394 | 1.35M | 1112U, // VSUBLuv4i32 |
6395 | 1.35M | 1112U, // VSUBLuv8i16 |
6396 | 1.35M | 70705U, // VSUBS |
6397 | 1.35M | 1112U, // VSUBWsv2i64 |
6398 | 1.35M | 1112U, // VSUBWsv4i32 |
6399 | 1.35M | 1112U, // VSUBWsv8i16 |
6400 | 1.35M | 1112U, // VSUBWuv2i64 |
6401 | 1.35M | 1112U, // VSUBWuv4i32 |
6402 | 1.35M | 1112U, // VSUBWuv8i16 |
6403 | 1.35M | 70705U, // VSUBfd |
6404 | 1.35M | 70705U, // VSUBfq |
6405 | 1.35M | 70705U, // VSUBhd |
6406 | 1.35M | 70705U, // VSUBhq |
6407 | 1.35M | 1112U, // VSUBv16i8 |
6408 | 1.35M | 1112U, // VSUBv1i64 |
6409 | 1.35M | 1112U, // VSUBv2i32 |
6410 | 1.35M | 1112U, // VSUBv2i64 |
6411 | 1.35M | 1112U, // VSUBv4i16 |
6412 | 1.35M | 1112U, // VSUBv4i32 |
6413 | 1.35M | 1112U, // VSUBv8i16 |
6414 | 1.35M | 1112U, // VSUBv8i8 |
6415 | 1.35M | 1024U, // VSWPd |
6416 | 1.35M | 1024U, // VSWPq |
6417 | 1.35M | 336U, // VTBL1 |
6418 | 1.35M | 344U, // VTBL2 |
6419 | 1.35M | 352U, // VTBL3 |
6420 | 1.35M | 0U, // VTBL3Pseudo |
6421 | 1.35M | 360U, // VTBL4 |
6422 | 1.35M | 0U, // VTBL4Pseudo |
6423 | 1.35M | 368U, // VTBX1 |
6424 | 1.35M | 376U, // VTBX2 |
6425 | 1.35M | 384U, // VTBX3 |
6426 | 1.35M | 0U, // VTBX3Pseudo |
6427 | 1.35M | 392U, // VTBX4 |
6428 | 1.35M | 0U, // VTBX4Pseudo |
6429 | 1.35M | 0U, // VTOSHD |
6430 | 1.35M | 7U, // VTOSHH |
6431 | 1.35M | 0U, // VTOSHS |
6432 | 1.35M | 0U, // VTOSIRD |
6433 | 1.35M | 0U, // VTOSIRH |
6434 | 1.35M | 0U, // VTOSIRS |
6435 | 1.35M | 0U, // VTOSIZD |
6436 | 1.35M | 0U, // VTOSIZH |
6437 | 1.35M | 0U, // VTOSIZS |
6438 | 1.35M | 7U, // VTOSLD |
6439 | 1.35M | 7U, // VTOSLH |
6440 | 1.35M | 7U, // VTOSLS |
6441 | 1.35M | 0U, // VTOUHD |
6442 | 1.35M | 7U, // VTOUHH |
6443 | 1.35M | 0U, // VTOUHS |
6444 | 1.35M | 0U, // VTOUIRD |
6445 | 1.35M | 0U, // VTOUIRH |
6446 | 1.35M | 0U, // VTOUIRS |
6447 | 1.35M | 0U, // VTOUIZD |
6448 | 1.35M | 0U, // VTOUIZH |
6449 | 1.35M | 0U, // VTOUIZS |
6450 | 1.35M | 7U, // VTOULD |
6451 | 1.35M | 7U, // VTOULH |
6452 | 1.35M | 7U, // VTOULS |
6453 | 1.35M | 1024U, // VTRNd16 |
6454 | 1.35M | 1024U, // VTRNd32 |
6455 | 1.35M | 1024U, // VTRNd8 |
6456 | 1.35M | 1024U, // VTRNq16 |
6457 | 1.35M | 1024U, // VTRNq32 |
6458 | 1.35M | 1024U, // VTRNq8 |
6459 | 1.35M | 0U, // VTSTv16i8 |
6460 | 1.35M | 0U, // VTSTv2i32 |
6461 | 1.35M | 0U, // VTSTv4i16 |
6462 | 1.35M | 0U, // VTSTv4i32 |
6463 | 1.35M | 0U, // VTSTv8i16 |
6464 | 1.35M | 0U, // VTSTv8i8 |
6465 | 1.35M | 0U, // VUDOTD |
6466 | 1.35M | 0U, // VUDOTDI |
6467 | 1.35M | 0U, // VUDOTQ |
6468 | 1.35M | 0U, // VUDOTQI |
6469 | 1.35M | 0U, // VUHTOD |
6470 | 1.35M | 7U, // VUHTOH |
6471 | 1.35M | 0U, // VUHTOS |
6472 | 1.35M | 0U, // VUITOD |
6473 | 1.35M | 0U, // VUITOH |
6474 | 1.35M | 0U, // VUITOS |
6475 | 1.35M | 7U, // VULTOD |
6476 | 1.35M | 7U, // VULTOH |
6477 | 1.35M | 7U, // VULTOS |
6478 | 1.35M | 1024U, // VUZPd16 |
6479 | 1.35M | 1024U, // VUZPd8 |
6480 | 1.35M | 1024U, // VUZPq16 |
6481 | 1.35M | 1024U, // VUZPq32 |
6482 | 1.35M | 1024U, // VUZPq8 |
6483 | 1.35M | 1024U, // VZIPd16 |
6484 | 1.35M | 1024U, // VZIPd8 |
6485 | 1.35M | 1024U, // VZIPq16 |
6486 | 1.35M | 1024U, // VZIPq32 |
6487 | 1.35M | 1024U, // VZIPq8 |
6488 | 1.35M | 20592U, // sysLDMDA |
6489 | 1.35M | 401U, // sysLDMDA_UPD |
6490 | 1.35M | 20592U, // sysLDMDB |
6491 | 1.35M | 401U, // sysLDMDB_UPD |
6492 | 1.35M | 20592U, // sysLDMIA |
6493 | 1.35M | 401U, // sysLDMIA_UPD |
6494 | 1.35M | 20592U, // sysLDMIB |
6495 | 1.35M | 401U, // sysLDMIB_UPD |
6496 | 1.35M | 20592U, // sysSTMDA |
6497 | 1.35M | 401U, // sysSTMDA_UPD |
6498 | 1.35M | 20592U, // sysSTMDB |
6499 | 1.35M | 401U, // sysSTMDB_UPD |
6500 | 1.35M | 20592U, // sysSTMIA |
6501 | 1.35M | 401U, // sysSTMIA_UPD |
6502 | 1.35M | 20592U, // sysSTMIB |
6503 | 1.35M | 401U, // sysSTMIB_UPD |
6504 | 1.35M | 0U, // t2ADCri |
6505 | 1.35M | 0U, // t2ADCrr |
6506 | 1.35M | 1048576U, // t2ADCrs |
6507 | 1.35M | 0U, // t2ADDri |
6508 | 1.35M | 0U, // t2ADDri12 |
6509 | 1.35M | 0U, // t2ADDrr |
6510 | 1.35M | 1048576U, // t2ADDrs |
6511 | 1.35M | 72U, // t2ADR |
6512 | 1.35M | 0U, // t2ANDri |
6513 | 1.35M | 0U, // t2ANDrr |
6514 | 1.35M | 1048576U, // t2ANDrs |
6515 | 1.35M | 1081344U, // t2ASRri |
6516 | 1.35M | 0U, // t2ASRrr |
6517 | 1.35M | 0U, // t2B |
6518 | 1.35M | 80U, // t2BFC |
6519 | 1.35M | 163928U, // t2BFI |
6520 | 1.35M | 0U, // t2BICri |
6521 | 1.35M | 0U, // t2BICrr |
6522 | 1.35M | 1048576U, // t2BICrs |
6523 | 1.35M | 0U, // t2BXJ |
6524 | 1.35M | 0U, // t2Bcc |
6525 | 1.35M | 4145U, // t2CDP |
6526 | 1.35M | 4145U, // t2CDP2 |
6527 | 1.35M | 0U, // t2CLREX |
6528 | 1.35M | 1024U, // t2CLZ |
6529 | 1.35M | 1024U, // t2CMNri |
6530 | 1.35M | 1024U, // t2CMNzrr |
6531 | 1.35M | 56U, // t2CMNzrs |
6532 | 1.35M | 1024U, // t2CMPri |
6533 | 1.35M | 1024U, // t2CMPrr |
6534 | 1.35M | 56U, // t2CMPrs |
6535 | 1.35M | 0U, // t2CPS1p |
6536 | 1.35M | 0U, // t2CPS2p |
6537 | 1.35M | 1112U, // t2CPS3p |
6538 | 1.35M | 1112U, // t2CRC32B |
6539 | 1.35M | 1112U, // t2CRC32CB |
6540 | 1.35M | 1112U, // t2CRC32CH |
6541 | 1.35M | 1112U, // t2CRC32CW |
6542 | 1.35M | 1112U, // t2CRC32H |
6543 | 1.35M | 1112U, // t2CRC32W |
6544 | 1.35M | 0U, // t2DBG |
6545 | 1.35M | 0U, // t2DCPS1 |
6546 | 1.35M | 0U, // t2DCPS2 |
6547 | 1.35M | 0U, // t2DCPS3 |
6548 | 1.35M | 0U, // t2DMB |
6549 | 1.35M | 0U, // t2DSB |
6550 | 1.35M | 0U, // t2EORri |
6551 | 1.35M | 0U, // t2EORrr |
6552 | 1.35M | 1048576U, // t2EORrs |
6553 | 1.35M | 0U, // t2HINT |
6554 | 1.35M | 0U, // t2HVC |
6555 | 1.35M | 0U, // t2ISB |
6556 | 1.35M | 0U, // t2IT |
6557 | 1.35M | 0U, // t2Int_eh_sjlj_setjmp |
6558 | 1.35M | 0U, // t2Int_eh_sjlj_setjmp_nofp |
6559 | 1.35M | 8U, // t2LDA |
6560 | 1.35M | 8U, // t2LDAB |
6561 | 1.35M | 8U, // t2LDAEX |
6562 | 1.35M | 8U, // t2LDAEXB |
6563 | 1.35M | 557056U, // t2LDAEXD |
6564 | 1.35M | 8U, // t2LDAEXH |
6565 | 1.35M | 8U, // t2LDAH |
6566 | 1.35M | 122U, // t2LDC2L_OFFSET |
6567 | 1.35M | 196738U, // t2LDC2L_OPTION |
6568 | 1.35M | 229506U, // t2LDC2L_POST |
6569 | 1.35M | 138U, // t2LDC2L_PRE |
6570 | 1.35M | 122U, // t2LDC2_OFFSET |
6571 | 1.35M | 196738U, // t2LDC2_OPTION |
6572 | 1.35M | 229506U, // t2LDC2_POST |
6573 | 1.35M | 138U, // t2LDC2_PRE |
6574 | 1.35M | 122U, // t2LDCL_OFFSET |
6575 | 1.35M | 196738U, // t2LDCL_OPTION |
6576 | 1.35M | 229506U, // t2LDCL_POST |
6577 | 1.35M | 138U, // t2LDCL_PRE |
6578 | 1.35M | 122U, // t2LDC_OFFSET |
6579 | 1.35M | 196738U, // t2LDC_OPTION |
6580 | 1.35M | 229506U, // t2LDC_POST |
6581 | 1.35M | 138U, // t2LDC_PRE |
6582 | 1.35M | 1136U, // t2LDMDB |
6583 | 1.35M | 33U, // t2LDMDB_UPD |
6584 | 1.35M | 1136U, // t2LDMIA |
6585 | 1.35M | 33U, // t2LDMIA_UPD |
6586 | 1.35M | 408U, // t2LDRBT |
6587 | 1.35M | 21632U, // t2LDRB_POST |
6588 | 1.35M | 416U, // t2LDRB_PRE |
6589 | 1.35M | 160U, // t2LDRBi12 |
6590 | 1.35M | 408U, // t2LDRBi8 |
6591 | 1.35M | 424U, // t2LDRBpci |
6592 | 1.35M | 432U, // t2LDRBs |
6593 | 1.35M | 25493504U, // t2LDRD_POST |
6594 | 1.35M | 1114112U, // t2LDRD_PRE |
6595 | 1.35M | 1146880U, // t2LDRDi8 |
6596 | 1.35M | 440U, // t2LDREX |
6597 | 1.35M | 8U, // t2LDREXB |
6598 | 1.35M | 557056U, // t2LDREXD |
6599 | 1.35M | 8U, // t2LDREXH |
6600 | 1.35M | 408U, // t2LDRHT |
6601 | 1.35M | 21632U, // t2LDRH_POST |
6602 | 1.35M | 416U, // t2LDRH_PRE |
6603 | 1.35M | 160U, // t2LDRHi12 |
6604 | 1.35M | 408U, // t2LDRHi8 |
6605 | 1.35M | 424U, // t2LDRHpci |
6606 | 1.35M | 432U, // t2LDRHs |
6607 | 1.35M | 408U, // t2LDRSBT |
6608 | 1.35M | 21632U, // t2LDRSB_POST |
6609 | 1.35M | 416U, // t2LDRSB_PRE |
6610 | 1.35M | 160U, // t2LDRSBi12 |
6611 | 1.35M | 408U, // t2LDRSBi8 |
6612 | 1.35M | 424U, // t2LDRSBpci |
6613 | 1.35M | 432U, // t2LDRSBs |
6614 | 1.35M | 408U, // t2LDRSHT |
6615 | 1.35M | 21632U, // t2LDRSH_POST |
6616 | 1.35M | 416U, // t2LDRSH_PRE |
6617 | 1.35M | 160U, // t2LDRSHi12 |
6618 | 1.35M | 408U, // t2LDRSHi8 |
6619 | 1.35M | 424U, // t2LDRSHpci |
6620 | 1.35M | 432U, // t2LDRSHs |
6621 | 1.35M | 408U, // t2LDRT |
6622 | 1.35M | 21632U, // t2LDR_POST |
6623 | 1.35M | 416U, // t2LDR_PRE |
6624 | 1.35M | 160U, // t2LDRi12 |
6625 | 1.35M | 408U, // t2LDRi8 |
6626 | 1.35M | 424U, // t2LDRpci |
6627 | 1.35M | 432U, // t2LDRs |
6628 | 1.35M | 0U, // t2LSLri |
6629 | 1.35M | 0U, // t2LSLrr |
6630 | 1.35M | 1081344U, // t2LSRri |
6631 | 1.35M | 0U, // t2LSRrr |
6632 | 1.35M | 4690993U, // t2MCR |
6633 | 1.35M | 4690993U, // t2MCR2 |
6634 | 1.35M | 6788145U, // t2MCRR |
6635 | 1.35M | 6788145U, // t2MCRR2 |
6636 | 1.35M | 35651584U, // t2MLA |
6637 | 1.35M | 35651584U, // t2MLS |
6638 | 1.35M | 1112U, // t2MOVTi16 |
6639 | 1.35M | 1024U, // t2MOVi |
6640 | 1.35M | 1024U, // t2MOVi16 |
6641 | 1.35M | 1024U, // t2MOVr |
6642 | 1.35M | 22528U, // t2MOVsra_flag |
6643 | 1.35M | 22528U, // t2MOVsrl_flag |
6644 | 1.35M | 0U, // t2MRC |
6645 | 1.35M | 0U, // t2MRC2 |
6646 | 1.35M | 0U, // t2MRRC |
6647 | 1.35M | 0U, // t2MRRC2 |
6648 | 1.35M | 2U, // t2MRS_AR |
6649 | 1.35M | 448U, // t2MRS_M |
6650 | 1.35M | 200U, // t2MRSbanked |
6651 | 1.35M | 2U, // t2MRSsys_AR |
6652 | 1.35M | 33U, // t2MSR_AR |
6653 | 1.35M | 33U, // t2MSR_M |
6654 | 1.35M | 0U, // t2MSRbanked |
6655 | 1.35M | 0U, // t2MUL |
6656 | 1.35M | 1024U, // t2MVNi |
6657 | 1.35M | 1024U, // t2MVNr |
6658 | 1.35M | 56U, // t2MVNs |
6659 | 1.35M | 0U, // t2ORNri |
6660 | 1.35M | 0U, // t2ORNrr |
6661 | 1.35M | 1048576U, // t2ORNrs |
6662 | 1.35M | 0U, // t2ORRri |
6663 | 1.35M | 0U, // t2ORRrr |
6664 | 1.35M | 1048576U, // t2ORRrs |
6665 | 1.35M | 8388608U, // t2PKHBT |
6666 | 1.35M | 10485760U, // t2PKHTB |
6667 | 1.35M | 0U, // t2PLDWi12 |
6668 | 1.35M | 0U, // t2PLDWi8 |
6669 | 1.35M | 0U, // t2PLDWs |
6670 | 1.35M | 0U, // t2PLDi12 |
6671 | 1.35M | 0U, // t2PLDi8 |
6672 | 1.35M | 0U, // t2PLDpci |
6673 | 1.35M | 0U, // t2PLDs |
6674 | 1.35M | 0U, // t2PLIi12 |
6675 | 1.35M | 0U, // t2PLIi8 |
6676 | 1.35M | 0U, // t2PLIpci |
6677 | 1.35M | 0U, // t2PLIs |
6678 | 1.35M | 0U, // t2QADD |
6679 | 1.35M | 0U, // t2QADD16 |
6680 | 1.35M | 0U, // t2QADD8 |
6681 | 1.35M | 0U, // t2QASX |
6682 | 1.35M | 0U, // t2QDADD |
6683 | 1.35M | 0U, // t2QDSUB |
6684 | 1.35M | 0U, // t2QSAX |
6685 | 1.35M | 0U, // t2QSUB |
6686 | 1.35M | 0U, // t2QSUB16 |
6687 | 1.35M | 0U, // t2QSUB8 |
6688 | 1.35M | 1024U, // t2RBIT |
6689 | 1.35M | 1024U, // t2REV |
6690 | 1.35M | 1024U, // t2REV16 |
6691 | 1.35M | 1024U, // t2REVSH |
6692 | 1.35M | 0U, // t2RFEDB |
6693 | 1.35M | 0U, // t2RFEDBW |
6694 | 1.35M | 0U, // t2RFEIA |
6695 | 1.35M | 0U, // t2RFEIAW |
6696 | 1.35M | 0U, // t2RORri |
6697 | 1.35M | 0U, // t2RORrr |
6698 | 1.35M | 1024U, // t2RRX |
6699 | 1.35M | 0U, // t2RSBri |
6700 | 1.35M | 0U, // t2RSBrr |
6701 | 1.35M | 1048576U, // t2RSBrs |
6702 | 1.35M | 0U, // t2SADD16 |
6703 | 1.35M | 0U, // t2SADD8 |
6704 | 1.35M | 0U, // t2SASX |
6705 | 1.35M | 0U, // t2SBCri |
6706 | 1.35M | 0U, // t2SBCrr |
6707 | 1.35M | 1048576U, // t2SBCrs |
6708 | 1.35M | 69206016U, // t2SBFX |
6709 | 1.35M | 0U, // t2SDIV |
6710 | 1.35M | 0U, // t2SEL |
6711 | 1.35M | 0U, // t2SETPAN |
6712 | 1.35M | 0U, // t2SG |
6713 | 1.35M | 0U, // t2SHADD16 |
6714 | 1.35M | 0U, // t2SHADD8 |
6715 | 1.35M | 0U, // t2SHASX |
6716 | 1.35M | 0U, // t2SHSAX |
6717 | 1.35M | 0U, // t2SHSUB16 |
6718 | 1.35M | 0U, // t2SHSUB8 |
6719 | 1.35M | 0U, // t2SMC |
6720 | 1.35M | 35651584U, // t2SMLABB |
6721 | 1.35M | 35651584U, // t2SMLABT |
6722 | 1.35M | 35651584U, // t2SMLAD |
6723 | 1.35M | 35651584U, // t2SMLADX |
6724 | 1.35M | 35651584U, // t2SMLAL |
6725 | 1.35M | 35651584U, // t2SMLALBB |
6726 | 1.35M | 35651584U, // t2SMLALBT |
6727 | 1.35M | 35651584U, // t2SMLALD |
6728 | 1.35M | 35651584U, // t2SMLALDX |
6729 | 1.35M | 35651584U, // t2SMLALTB |
6730 | 1.35M | 35651584U, // t2SMLALTT |
6731 | 1.35M | 35651584U, // t2SMLATB |
6732 | 1.35M | 35651584U, // t2SMLATT |
6733 | 1.35M | 35651584U, // t2SMLAWB |
6734 | 1.35M | 35651584U, // t2SMLAWT |
6735 | 1.35M | 35651584U, // t2SMLSD |
6736 | 1.35M | 35651584U, // t2SMLSDX |
6737 | 1.35M | 35651584U, // t2SMLSLD |
6738 | 1.35M | 35651584U, // t2SMLSLDX |
6739 | 1.35M | 35651584U, // t2SMMLA |
6740 | 1.35M | 35651584U, // t2SMMLAR |
6741 | 1.35M | 35651584U, // t2SMMLS |
6742 | 1.35M | 35651584U, // t2SMMLSR |
6743 | 1.35M | 0U, // t2SMMUL |
6744 | 1.35M | 0U, // t2SMMULR |
6745 | 1.35M | 0U, // t2SMUAD |
6746 | 1.35M | 0U, // t2SMUADX |
6747 | 1.35M | 0U, // t2SMULBB |
6748 | 1.35M | 0U, // t2SMULBT |
6749 | 1.35M | 35651584U, // t2SMULL |
6750 | 1.35M | 0U, // t2SMULTB |
6751 | 1.35M | 0U, // t2SMULTT |
6752 | 1.35M | 0U, // t2SMULWB |
6753 | 1.35M | 0U, // t2SMULWT |
6754 | 1.35M | 0U, // t2SMUSD |
6755 | 1.35M | 0U, // t2SMUSDX |
6756 | 1.35M | 0U, // t2SRSDB |
6757 | 1.35M | 0U, // t2SRSDB_UPD |
6758 | 1.35M | 0U, // t2SRSIA |
6759 | 1.35M | 0U, // t2SRSIA_UPD |
6760 | 1.35M | 6352U, // t2SSAT |
6761 | 1.35M | 1232U, // t2SSAT16 |
6762 | 1.35M | 0U, // t2SSAX |
6763 | 1.35M | 0U, // t2SSUB16 |
6764 | 1.35M | 0U, // t2SSUB8 |
6765 | 1.35M | 122U, // t2STC2L_OFFSET |
6766 | 1.35M | 196738U, // t2STC2L_OPTION |
6767 | 1.35M | 229506U, // t2STC2L_POST |
6768 | 1.35M | 138U, // t2STC2L_PRE |
6769 | 1.35M | 122U, // t2STC2_OFFSET |
6770 | 1.35M | 196738U, // t2STC2_OPTION |
6771 | 1.35M | 229506U, // t2STC2_POST |
6772 | 1.35M | 138U, // t2STC2_PRE |
6773 | 1.35M | 122U, // t2STCL_OFFSET |
6774 | 1.35M | 196738U, // t2STCL_OPTION |
6775 | 1.35M | 229506U, // t2STCL_POST |
6776 | 1.35M | 138U, // t2STCL_PRE |
6777 | 1.35M | 122U, // t2STC_OFFSET |
6778 | 1.35M | 196738U, // t2STC_OPTION |
6779 | 1.35M | 229506U, // t2STC_POST |
6780 | 1.35M | 138U, // t2STC_PRE |
6781 | 1.35M | 8U, // t2STL |
6782 | 1.35M | 8U, // t2STLB |
6783 | 1.35M | 557056U, // t2STLEX |
6784 | 1.35M | 557056U, // t2STLEXB |
6785 | 1.35M | 371195904U, // t2STLEXD |
6786 | 1.35M | 557056U, // t2STLEXH |
6787 | 1.35M | 8U, // t2STLH |
6788 | 1.35M | 1136U, // t2STMDB |
6789 | 1.35M | 33U, // t2STMDB_UPD |
6790 | 1.35M | 1136U, // t2STMIA |
6791 | 1.35M | 33U, // t2STMIA_UPD |
6792 | 1.35M | 408U, // t2STRBT |
6793 | 1.35M | 21632U, // t2STRB_POST |
6794 | 1.35M | 416U, // t2STRB_PRE |
6795 | 1.35M | 160U, // t2STRBi12 |
6796 | 1.35M | 408U, // t2STRBi8 |
6797 | 1.35M | 432U, // t2STRBs |
6798 | 1.35M | 25493592U, // t2STRD_POST |
6799 | 1.35M | 1114200U, // t2STRD_PRE |
6800 | 1.35M | 1146880U, // t2STRDi8 |
6801 | 1.35M | 1179648U, // t2STREX |
6802 | 1.35M | 557056U, // t2STREXB |
6803 | 1.35M | 371195904U, // t2STREXD |
6804 | 1.35M | 557056U, // t2STREXH |
6805 | 1.35M | 408U, // t2STRHT |
6806 | 1.35M | 21632U, // t2STRH_POST |
6807 | 1.35M | 416U, // t2STRH_PRE |
6808 | 1.35M | 160U, // t2STRHi12 |
6809 | 1.35M | 408U, // t2STRHi8 |
6810 | 1.35M | 432U, // t2STRHs |
6811 | 1.35M | 408U, // t2STRT |
6812 | 1.35M | 21632U, // t2STR_POST |
6813 | 1.35M | 416U, // t2STR_PRE |
6814 | 1.35M | 160U, // t2STRi12 |
6815 | 1.35M | 408U, // t2STRi8 |
6816 | 1.35M | 432U, // t2STRs |
6817 | 1.35M | 0U, // t2SUBS_PC_LR |
6818 | 1.35M | 0U, // t2SUBri |
6819 | 1.35M | 0U, // t2SUBri12 |
6820 | 1.35M | 0U, // t2SUBrr |
6821 | 1.35M | 1048576U, // t2SUBrs |
6822 | 1.35M | 12582912U, // t2SXTAB |
6823 | 1.35M | 12582912U, // t2SXTAB16 |
6824 | 1.35M | 12582912U, // t2SXTAH |
6825 | 1.35M | 7168U, // t2SXTB |
6826 | 1.35M | 7168U, // t2SXTB16 |
6827 | 1.35M | 7168U, // t2SXTH |
6828 | 1.35M | 0U, // t2TBB |
6829 | 1.35M | 0U, // t2TBH |
6830 | 1.35M | 1024U, // t2TEQri |
6831 | 1.35M | 1024U, // t2TEQrr |
6832 | 1.35M | 56U, // t2TEQrs |
6833 | 1.35M | 0U, // t2TSB |
6834 | 1.35M | 1024U, // t2TSTri |
6835 | 1.35M | 1024U, // t2TSTrr |
6836 | 1.35M | 56U, // t2TSTrs |
6837 | 1.35M | 1024U, // t2TT |
6838 | 1.35M | 1024U, // t2TTA |
6839 | 1.35M | 1024U, // t2TTAT |
6840 | 1.35M | 1024U, // t2TTT |
6841 | 1.35M | 0U, // t2UADD16 |
6842 | 1.35M | 0U, // t2UADD8 |
6843 | 1.35M | 0U, // t2UASX |
6844 | 1.35M | 69206016U, // t2UBFX |
6845 | 1.35M | 0U, // t2UDF |
6846 | 1.35M | 0U, // t2UDIV |
6847 | 1.35M | 0U, // t2UHADD16 |
6848 | 1.35M | 0U, // t2UHADD8 |
6849 | 1.35M | 0U, // t2UHASX |
6850 | 1.35M | 0U, // t2UHSAX |
6851 | 1.35M | 0U, // t2UHSUB16 |
6852 | 1.35M | 0U, // t2UHSUB8 |
6853 | 1.35M | 35651584U, // t2UMAAL |
6854 | 1.35M | 35651584U, // t2UMLAL |
6855 | 1.35M | 35651584U, // t2UMULL |
6856 | 1.35M | 0U, // t2UQADD16 |
6857 | 1.35M | 0U, // t2UQADD8 |
6858 | 1.35M | 0U, // t2UQASX |
6859 | 1.35M | 0U, // t2UQSAX |
6860 | 1.35M | 0U, // t2UQSUB16 |
6861 | 1.35M | 0U, // t2UQSUB8 |
6862 | 1.35M | 0U, // t2USAD8 |
6863 | 1.35M | 35651584U, // t2USADA8 |
6864 | 1.35M | 14680064U, // t2USAT |
6865 | 1.35M | 0U, // t2USAT16 |
6866 | 1.35M | 0U, // t2USAX |
6867 | 1.35M | 0U, // t2USUB16 |
6868 | 1.35M | 0U, // t2USUB8 |
6869 | 1.35M | 12582912U, // t2UXTAB |
6870 | 1.35M | 12582912U, // t2UXTAB16 |
6871 | 1.35M | 12582912U, // t2UXTAH |
6872 | 1.35M | 7168U, // t2UXTB |
6873 | 1.35M | 7168U, // t2UXTB16 |
6874 | 1.35M | 7168U, // t2UXTH |
6875 | 1.35M | 0U, // tADC |
6876 | 1.35M | 1112U, // tADDhirr |
6877 | 1.35M | 1048U, // tADDi3 |
6878 | 1.35M | 0U, // tADDi8 |
6879 | 1.35M | 0U, // tADDrSP |
6880 | 1.35M | 1212416U, // tADDrSPi |
6881 | 1.35M | 1048U, // tADDrr |
6882 | 1.35M | 456U, // tADDspi |
6883 | 1.35M | 1112U, // tADDspr |
6884 | 1.35M | 464U, // tADR |
6885 | 1.35M | 0U, // tAND |
6886 | 1.35M | 472U, // tASRri |
6887 | 1.35M | 0U, // tASRrr |
6888 | 1.35M | 0U, // tB |
6889 | 1.35M | 0U, // tBIC |
6890 | 1.35M | 0U, // tBKPT |
6891 | 1.35M | 0U, // tBL |
6892 | 1.35M | 0U, // tBLXNSr |
6893 | 1.35M | 0U, // tBLXi |
6894 | 1.35M | 0U, // tBLXr |
6895 | 1.35M | 0U, // tBX |
6896 | 1.35M | 0U, // tBXNS |
6897 | 1.35M | 0U, // tBcc |
6898 | 1.35M | 0U, // tCBNZ |
6899 | 1.35M | 0U, // tCBZ |
6900 | 1.35M | 1024U, // tCMNz |
6901 | 1.35M | 1024U, // tCMPhir |
6902 | 1.35M | 1024U, // tCMPi8 |
6903 | 1.35M | 1024U, // tCMPr |
6904 | 1.35M | 0U, // tCPS |
6905 | 1.35M | 0U, // tEOR |
6906 | 1.35M | 0U, // tHINT |
6907 | 1.35M | 0U, // tHLT |
6908 | 1.35M | 0U, // tInt_WIN_eh_sjlj_longjmp |
6909 | 1.35M | 0U, // tInt_eh_sjlj_longjmp |
6910 | 1.35M | 0U, // tInt_eh_sjlj_setjmp |
6911 | 1.35M | 1136U, // tLDMIA |
6912 | 1.35M | 480U, // tLDRBi |
6913 | 1.35M | 488U, // tLDRBr |
6914 | 1.35M | 496U, // tLDRHi |
6915 | 1.35M | 488U, // tLDRHr |
6916 | 1.35M | 488U, // tLDRSB |
6917 | 1.35M | 488U, // tLDRSH |
6918 | 1.35M | 504U, // tLDRi |
6919 | 1.35M | 424U, // tLDRpci |
6920 | 1.35M | 488U, // tLDRr |
6921 | 1.35M | 512U, // tLDRspi |
6922 | 1.35M | 1048U, // tLSLri |
6923 | 1.35M | 0U, // tLSLrr |
6924 | 1.35M | 472U, // tLSRri |
6925 | 1.35M | 0U, // tLSRrr |
6926 | 1.35M | 0U, // tMOVSr |
6927 | 1.35M | 0U, // tMOVi8 |
6928 | 1.35M | 1024U, // tMOVr |
6929 | 1.35M | 1048U, // tMUL |
6930 | 1.35M | 0U, // tMVN |
6931 | 1.35M | 0U, // tORR |
6932 | 1.35M | 0U, // tPICADD |
6933 | 1.35M | 0U, // tPOP |
6934 | 1.35M | 0U, // tPUSH |
6935 | 1.35M | 1024U, // tREV |
6936 | 1.35M | 1024U, // tREV16 |
6937 | 1.35M | 1024U, // tREVSH |
6938 | 1.35M | 0U, // tROR |
6939 | 1.35M | 0U, // tRSB |
6940 | 1.35M | 0U, // tSBC |
6941 | 1.35M | 0U, // tSETEND |
6942 | 1.35M | 33U, // tSTMIA_UPD |
6943 | 1.35M | 480U, // tSTRBi |
6944 | 1.35M | 488U, // tSTRBr |
6945 | 1.35M | 496U, // tSTRHi |
6946 | 1.35M | 488U, // tSTRHr |
6947 | 1.35M | 504U, // tSTRi |
6948 | 1.35M | 488U, // tSTRr |
6949 | 1.35M | 512U, // tSTRspi |
6950 | 1.35M | 1048U, // tSUBi3 |
6951 | 1.35M | 0U, // tSUBi8 |
6952 | 1.35M | 1048U, // tSUBrr |
6953 | 1.35M | 456U, // tSUBspi |
6954 | 1.35M | 0U, // tSVC |
6955 | 1.35M | 1024U, // tSXTB |
6956 | 1.35M | 1024U, // tSXTH |
6957 | 1.35M | 0U, // tTRAP |
6958 | 1.35M | 1024U, // tTST |
6959 | 1.35M | 0U, // tUDF |
6960 | 1.35M | 1024U, // tUXTB |
6961 | 1.35M | 1024U, // tUXTH |
6962 | 1.35M | 0U, // t__brkdiv0 |
6963 | 1.35M | }; |
6964 | | |
6965 | 1.35M | unsigned int opcode = MCInst_getOpcode(MI); |
6966 | | // printf("opcode = %u\n", opcode); |
6967 | | |
6968 | | // Emit the opcode for the instruction. |
6969 | 1.35M | uint64_t Bits = 0; |
6970 | 1.35M | Bits |= (uint64_t)OpInfo0[opcode] << 0; |
6971 | 1.35M | Bits |= (uint64_t)OpInfo1[opcode] << 32; |
6972 | 1.35M | #ifndef CAPSTONE_DIET |
6973 | 1.35M | SStream_concat0(O, AsmStrs+(Bits & 4095)-1); |
6974 | 1.35M | #endif |
6975 | | |
6976 | | |
6977 | | // Fragment 0 encoded into 5 bits for 32 unique commands. |
6978 | | // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 31)); |
6979 | 1.35M | switch ((Bits >> 12) & 31) { |
6980 | 0 | default: // unreachable |
6981 | 169 | case 0: |
6982 | | // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
6983 | 169 | return; |
6984 | 0 | break; |
6985 | 32.4k | case 1: |
6986 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... |
6987 | 32.4k | printSBitModifierOperand(MI, 5, O); |
6988 | 32.4k | printPredicateOperand(MI, 3, O); |
6989 | 32.4k | break; |
6990 | 20.6k | case 2: |
6991 | | // ITasm, t2IT |
6992 | 20.6k | printThumbITMask(MI, 1, O); |
6993 | 20.6k | break; |
6994 | 144k | case 3: |
6995 | | // LDRBT_POST, LDRConstPool, LDRT_POST, STRBT_POST, STRT_POST, t2LDRBpcre... |
6996 | 144k | printPredicateOperand(MI, 2, O); |
6997 | 144k | break; |
6998 | 2.18k | case 4: |
6999 | | // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... |
7000 | 2.18k | printSBitModifierOperand(MI, 4, O); |
7001 | 2.18k | printPredicateOperand(MI, 2, O); |
7002 | 2.18k | break; |
7003 | 85.0k | case 5: |
7004 | | // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... |
7005 | 85.0k | printPredicateOperand(MI, 4, O); |
7006 | 85.0k | break; |
7007 | 60.9k | case 6: |
7008 | | // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... |
7009 | 60.9k | printPredicateOperand(MI, 5, O); |
7010 | 60.9k | break; |
7011 | 346k | case 7: |
7012 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... |
7013 | 346k | printPredicateOperand(MI, 3, O); |
7014 | 346k | break; |
7015 | 21.9k | case 8: |
7016 | | // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... |
7017 | 21.9k | printSBitModifierOperand(MI, 6, O); |
7018 | 21.9k | printPredicateOperand(MI, 4, O); |
7019 | 21.9k | break; |
7020 | 8.37k | case 9: |
7021 | | // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... |
7022 | 8.37k | printSBitModifierOperand(MI, 7, O); |
7023 | 8.37k | printPredicateOperand(MI, 5, O); |
7024 | 8.37k | SStream_concat0(O, "\t"); |
7025 | 8.37k | printOperand(MI, 0, O); |
7026 | 8.37k | SStream_concat0(O, ", "); |
7027 | 8.37k | printOperand(MI, 1, O); |
7028 | 8.37k | SStream_concat0(O, ", "); |
7029 | 8.37k | printSORegRegOperand(MI, 2, O); |
7030 | 8.37k | return; |
7031 | 0 | break; |
7032 | 176k | case 10: |
7033 | | // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... |
7034 | 176k | printOperand(MI, 0, O); |
7035 | 176k | break; |
7036 | 102k | case 11: |
7037 | | // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... |
7038 | 102k | printPredicateOperand(MI, 1, O); |
7039 | 102k | break; |
7040 | 15.1k | case 12: |
7041 | | // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, t2S... |
7042 | 15.1k | printPredicateOperand(MI, 0, O); |
7043 | 15.1k | break; |
7044 | 21.6k | case 13: |
7045 | | // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, SMLALBB, SMLALBT, SMLALD, SMLALDX,... |
7046 | 21.6k | printPredicateOperand(MI, 6, O); |
7047 | 21.6k | break; |
7048 | 8.39k | case 14: |
7049 | | // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... |
7050 | 8.39k | printPImmediate(MI, 0, O); |
7051 | 8.39k | SStream_concat0(O, ", "); |
7052 | 8.39k | break; |
7053 | 489 | case 15: |
7054 | | // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS |
7055 | 489 | printCPSIMod(MI, 0, O); |
7056 | 489 | break; |
7057 | 99 | case 16: |
7058 | | // DMB, DSB |
7059 | 99 | printMemBOption(MI, 0, O); |
7060 | 99 | return; |
7061 | 0 | break; |
7062 | 157 | case 17: |
7063 | | // ISB |
7064 | 157 | printInstSyncBOption(MI, 0, O); |
7065 | 157 | return; |
7066 | 0 | break; |
7067 | 637 | case 18: |
7068 | | // MRC2 |
7069 | 637 | printPImmediate(MI, 1, O); |
7070 | 637 | SStream_concat0(O, ", "); |
7071 | 637 | printOperand(MI, 2, O); |
7072 | 637 | SStream_concat0(O, ", "); |
7073 | 637 | printOperand(MI, 0, O); |
7074 | 637 | SStream_concat0(O, ", "); |
7075 | 637 | printCImmediate(MI, 3, O); |
7076 | 637 | SStream_concat0(O, ", "); |
7077 | 637 | printCImmediate(MI, 4, O); |
7078 | 637 | SStream_concat0(O, ", "); |
7079 | 637 | printOperand(MI, 5, O); |
7080 | 637 | return; |
7081 | 0 | break; |
7082 | 176 | case 19: |
7083 | | // MRRC2 |
7084 | 176 | printPImmediate(MI, 2, O); |
7085 | 176 | SStream_concat0(O, ", "); |
7086 | 176 | printOperand(MI, 3, O); |
7087 | 176 | SStream_concat0(O, ", "); |
7088 | 176 | printOperand(MI, 0, O); |
7089 | 176 | SStream_concat0(O, ", "); |
7090 | 176 | printOperand(MI, 1, O); |
7091 | 176 | SStream_concat0(O, ", "); |
7092 | 176 | printCImmediate(MI, 4, O); |
7093 | 176 | return; |
7094 | 0 | break; |
7095 | 102 | case 20: |
7096 | | // PLDWi12, PLDi12, PLIi12 |
7097 | 102 | printAddrModeImm12Operand(MI, 0, O, false); |
7098 | 102 | return; |
7099 | 0 | break; |
7100 | 27 | case 21: |
7101 | | // PLDWrs, PLDrs, PLIrs |
7102 | 27 | printAddrMode2Operand(MI, 0, O); |
7103 | 27 | return; |
7104 | 0 | break; |
7105 | 169 | case 22: |
7106 | | // SETEND, tSETEND |
7107 | 169 | printSetendOperand(MI, 0, O); |
7108 | 169 | return; |
7109 | 0 | break; |
7110 | 267 | case 23: |
7111 | | // SMLAL, UMLAL |
7112 | 267 | printSBitModifierOperand(MI, 8, O); |
7113 | 267 | printPredicateOperand(MI, 6, O); |
7114 | 267 | SStream_concat0(O, "\t"); |
7115 | 267 | printOperand(MI, 0, O); |
7116 | 267 | SStream_concat0(O, ", "); |
7117 | 267 | printOperand(MI, 1, O); |
7118 | 267 | SStream_concat0(O, ", "); |
7119 | 267 | printOperand(MI, 2, O); |
7120 | 267 | SStream_concat0(O, ", "); |
7121 | 267 | printOperand(MI, 3, O); |
7122 | 267 | return; |
7123 | 0 | break; |
7124 | 0 | case 24: |
7125 | | // TSB |
7126 | 0 | printTraceSyncBOption(MI, 0, O); |
7127 | 0 | return; |
7128 | 0 | break; |
7129 | 3.39k | case 25: |
7130 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... |
7131 | 3.39k | printPredicateOperand(MI, 7, O); |
7132 | 3.39k | break; |
7133 | 3.21k | case 26: |
7134 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
7135 | 3.21k | printPredicateOperand(MI, 9, O); |
7136 | 3.21k | break; |
7137 | 1.19k | case 27: |
7138 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
7139 | 1.19k | printPredicateOperand(MI, 11, O); |
7140 | 1.19k | break; |
7141 | 6.28k | case 28: |
7142 | | // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... |
7143 | 6.28k | printPredicateOperand(MI, 8, O); |
7144 | 6.28k | break; |
7145 | 987 | case 29: |
7146 | | // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... |
7147 | 987 | printPredicateOperand(MI, 13, O); |
7148 | 987 | break; |
7149 | 293 | case 30: |
7150 | | // VSDOTD, VSDOTDI, VSDOTQ, VSDOTQI, VUDOTD, VUDOTDI, VUDOTQ, VUDOTQI |
7151 | 293 | printOperand(MI, 1, O); |
7152 | 293 | SStream_concat0(O, ", "); |
7153 | 293 | printOperand(MI, 2, O); |
7154 | 293 | SStream_concat0(O, ", "); |
7155 | 293 | printOperand(MI, 3, O); |
7156 | 293 | break; |
7157 | 290k | case 31: |
7158 | | // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... |
7159 | 290k | printSBitModifierOperand(MI, 1, O); |
7160 | 290k | break; |
7161 | 1.35M | } |
7162 | | |
7163 | | |
7164 | | // Fragment 1 encoded into 7 bits for 75 unique commands. |
7165 | | // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 17) & 127)); |
7166 | 1.34M | switch ((Bits >> 17) & 127) { |
7167 | 0 | default: // unreachable |
7168 | 90 | case 0: |
7169 | | // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LS... |
7170 | 90 | SStream_concat0(O, " "); |
7171 | 90 | break; |
7172 | 9.49k | case 1: |
7173 | | // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... |
7174 | 9.49k | SStream_concat0(O, ".16\t"); |
7175 | 9.49k | ARM_addVectorDataSize(MI, 16); |
7176 | 9.49k | break; |
7177 | 9.73k | case 2: |
7178 | | // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... |
7179 | 9.73k | SStream_concat0(O, ".32\t"); |
7180 | 9.73k | ARM_addVectorDataSize(MI, 32); |
7181 | 9.73k | break; |
7182 | 9.72k | case 3: |
7183 | | // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... |
7184 | 9.72k | SStream_concat0(O, ".8\t"); |
7185 | 9.72k | ARM_addVectorDataSize(MI, 8); |
7186 | 9.72k | break; |
7187 | 765k | case 4: |
7188 | | // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... |
7189 | 765k | SStream_concat0(O, "\t"); |
7190 | 765k | break; |
7191 | 168k | case 5: |
7192 | | // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... |
7193 | 168k | SStream_concat0(O, ", "); |
7194 | 168k | break; |
7195 | 8.05k | case 6: |
7196 | | // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... |
7197 | 8.05k | return; |
7198 | 0 | break; |
7199 | 107 | case 7: |
7200 | | // BX_RET |
7201 | 107 | SStream_concat0(O, "\tlr"); |
7202 | 107 | ARM_addReg(MI, ARM_REG_LR); |
7203 | 107 | return; |
7204 | 0 | break; |
7205 | 1.67k | case 8: |
7206 | | // CDP2, MCR2, MCRR2 |
7207 | 1.67k | printOperand(MI, 1, O); |
7208 | 1.67k | SStream_concat0(O, ", "); |
7209 | 1.67k | break; |
7210 | 801 | case 9: |
7211 | | // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... |
7212 | 801 | SStream_concat0(O, ".f64\t"); |
7213 | 801 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64); |
7214 | 801 | printOperand(MI, 0, O); |
7215 | 801 | break; |
7216 | 1.11k | case 10: |
7217 | | // FCONSTH, VABDhd, VABDhq, VABSH, VABShd, VABShq, VACGEhd, VACGEhq, VACG... |
7218 | 1.11k | SStream_concat0(O, ".f16\t"); |
7219 | 1.11k | ARM_addVectorDataType(MI, ARM_VECTORDATA_F16); |
7220 | 1.11k | printOperand(MI, 0, O); |
7221 | 1.11k | break; |
7222 | 2.83k | case 11: |
7223 | | // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEfd, VACGEfq, VACG... |
7224 | 2.83k | SStream_concat0(O, ".f32\t"); |
7225 | 2.83k | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32); |
7226 | 2.83k | printOperand(MI, 0, O); |
7227 | 2.83k | break; |
7228 | 22 | case 12: |
7229 | | // FMSTAT |
7230 | 22 | SStream_concat0(O, "\tapsr_nzcv, fpscr"); |
7231 | 22 | ARM_addReg(MI, ARM_REG_APSR_NZCV); |
7232 | 22 | ARM_addReg(MI, ARM_REG_FPSCR); |
7233 | 22 | return; |
7234 | 0 | break; |
7235 | 6.72k | case 13: |
7236 | | // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... |
7237 | 6.72k | printCImmediate(MI, 1, O); |
7238 | 6.72k | SStream_concat0(O, ", "); |
7239 | 6.72k | break; |
7240 | 69 | case 14: |
7241 | | // MOVPCLR |
7242 | 69 | SStream_concat0(O, "\tpc, lr"); |
7243 | 69 | ARM_addReg(MI, ARM_REG_PC); |
7244 | 69 | ARM_addReg(MI, ARM_REG_LR); |
7245 | 69 | return; |
7246 | 0 | break; |
7247 | 239 | case 15: |
7248 | | // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD |
7249 | 239 | SStream_concat0(O, "!"); |
7250 | 239 | return; |
7251 | 0 | break; |
7252 | 2.33k | case 16: |
7253 | | // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i... |
7254 | 2.33k | SStream_concat0(O, ".s32\t"); |
7255 | 2.33k | ARM_addVectorDataType(MI, ARM_VECTORDATA_S32); |
7256 | 2.33k | printOperand(MI, 0, O); |
7257 | 2.33k | SStream_concat0(O, ", "); |
7258 | 2.33k | break; |
7259 | 1.40k | case 17: |
7260 | | // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i... |
7261 | 1.40k | SStream_concat0(O, ".s16\t"); |
7262 | 1.40k | ARM_addVectorDataType(MI, ARM_VECTORDATA_S16); |
7263 | 1.40k | printOperand(MI, 0, O); |
7264 | 1.40k | SStream_concat0(O, ", "); |
7265 | 1.40k | break; |
7266 | 676 | case 18: |
7267 | | // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8... |
7268 | 676 | SStream_concat0(O, ".s8\t"); |
7269 | 676 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S8); |
7270 | 676 | printOperand(MI, 0, O); |
7271 | 676 | SStream_concat0(O, ", "); |
7272 | 676 | break; |
7273 | 2.03k | case 19: |
7274 | | // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i... |
7275 | 2.03k | SStream_concat0(O, ".u32\t"); |
7276 | 2.03k | ARM_addVectorDataType(MI, ARM_VECTORDATA_U32); |
7277 | 2.03k | printOperand(MI, 0, O); |
7278 | 2.03k | SStream_concat0(O, ", "); |
7279 | 2.03k | break; |
7280 | 1.12k | case 20: |
7281 | | // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i... |
7282 | 1.12k | SStream_concat0(O, ".u16\t"); |
7283 | 1.12k | ARM_addVectorDataType(MI, ARM_VECTORDATA_U16); |
7284 | 1.12k | printOperand(MI, 0, O); |
7285 | 1.12k | SStream_concat0(O, ", "); |
7286 | 1.12k | break; |
7287 | 1.64k | case 21: |
7288 | | // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8... |
7289 | 1.64k | SStream_concat0(O, ".u8\t"); |
7290 | 1.64k | ARM_addVectorDataType(MI, ARM_VECTORDATA_U8); |
7291 | 1.64k | printOperand(MI, 0, O); |
7292 | 1.64k | SStream_concat0(O, ", "); |
7293 | 1.64k | break; |
7294 | 515 | case 22: |
7295 | | // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V... |
7296 | 515 | SStream_concat0(O, ".i64\t"); |
7297 | 515 | ARM_addVectorDataType(MI, ARM_VECTORDATA_I64); |
7298 | 515 | printOperand(MI, 0, O); |
7299 | 515 | SStream_concat0(O, ", "); |
7300 | 515 | break; |
7301 | 1.82k | case 23: |
7302 | | // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ... |
7303 | 1.82k | SStream_concat0(O, ".i32\t"); |
7304 | 1.82k | ARM_addVectorDataType(MI, ARM_VECTORDATA_I32); |
7305 | 1.82k | printOperand(MI, 0, O); |
7306 | 1.82k | SStream_concat0(O, ", "); |
7307 | 1.82k | break; |
7308 | 871 | case 24: |
7309 | | // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V... |
7310 | 871 | SStream_concat0(O, ".i16\t"); |
7311 | 871 | ARM_addVectorDataType(MI, ARM_VECTORDATA_I16); |
7312 | 871 | printOperand(MI, 0, O); |
7313 | 871 | SStream_concat0(O, ", "); |
7314 | 871 | break; |
7315 | 309 | case 25: |
7316 | | // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv... |
7317 | 309 | SStream_concat0(O, ".i8\t"); |
7318 | 309 | ARM_addVectorDataType(MI, ARM_VECTORDATA_I8); |
7319 | 309 | printOperand(MI, 0, O); |
7320 | 309 | SStream_concat0(O, ", "); |
7321 | 309 | break; |
7322 | 70 | case 26: |
7323 | | // VCVTBDH, VCVTTDH |
7324 | 70 | SStream_concat0(O, ".f16.f64\t"); |
7325 | 70 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64); |
7326 | 70 | printOperand(MI, 0, O); |
7327 | 70 | SStream_concat0(O, ", "); |
7328 | 70 | printOperand(MI, 1, O); |
7329 | 70 | return; |
7330 | 0 | break; |
7331 | 28 | case 27: |
7332 | | // VCVTBHD, VCVTTHD |
7333 | 28 | SStream_concat0(O, ".f64.f16\t"); |
7334 | 28 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16); |
7335 | 28 | printOperand(MI, 0, O); |
7336 | 28 | SStream_concat0(O, ", "); |
7337 | 28 | printOperand(MI, 1, O); |
7338 | 28 | return; |
7339 | 0 | break; |
7340 | 21 | case 28: |
7341 | | // VCVTBHS, VCVTTHS, VCVTh2f |
7342 | 21 | SStream_concat0(O, ".f32.f16\t"); |
7343 | 21 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16); |
7344 | 21 | printOperand(MI, 0, O); |
7345 | 21 | SStream_concat0(O, ", "); |
7346 | 21 | printOperand(MI, 1, O); |
7347 | 21 | return; |
7348 | 0 | break; |
7349 | 134 | case 29: |
7350 | | // VCVTBSH, VCVTTSH, VCVTf2h |
7351 | 134 | SStream_concat0(O, ".f16.f32\t"); |
7352 | 134 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32); |
7353 | 134 | printOperand(MI, 0, O); |
7354 | 134 | SStream_concat0(O, ", "); |
7355 | 134 | printOperand(MI, 1, O); |
7356 | 134 | return; |
7357 | 0 | break; |
7358 | 60 | case 30: |
7359 | | // VCVTDS |
7360 | 60 | SStream_concat0(O, ".f64.f32\t"); |
7361 | 60 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32); |
7362 | 60 | printOperand(MI, 0, O); |
7363 | 60 | SStream_concat0(O, ", "); |
7364 | 60 | printOperand(MI, 1, O); |
7365 | 60 | return; |
7366 | 0 | break; |
7367 | 301 | case 31: |
7368 | | // VCVTSD |
7369 | 301 | SStream_concat0(O, ".f32.f64\t"); |
7370 | 301 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64); |
7371 | 301 | printOperand(MI, 0, O); |
7372 | 301 | SStream_concat0(O, ", "); |
7373 | 301 | printOperand(MI, 1, O); |
7374 | 301 | return; |
7375 | 0 | break; |
7376 | 56 | case 32: |
7377 | | // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS |
7378 | 56 | SStream_concat0(O, ".s32.f32\t"); |
7379 | 56 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32); |
7380 | 56 | printOperand(MI, 0, O); |
7381 | 56 | SStream_concat0(O, ", "); |
7382 | 56 | printOperand(MI, 1, O); |
7383 | 56 | break; |
7384 | 108 | case 33: |
7385 | | // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS |
7386 | 108 | SStream_concat0(O, ".u32.f32\t"); |
7387 | 108 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32); |
7388 | 108 | printOperand(MI, 0, O); |
7389 | 108 | SStream_concat0(O, ", "); |
7390 | 108 | printOperand(MI, 1, O); |
7391 | 108 | break; |
7392 | 247 | case 34: |
7393 | | // VCVTh2sd, VCVTh2sq, VCVTh2xsd, VCVTh2xsq, VTOSHH |
7394 | 247 | SStream_concat0(O, ".s16.f16\t"); |
7395 | 247 | printOperand(MI, 0, O); |
7396 | 247 | SStream_concat0(O, ", "); |
7397 | 247 | printOperand(MI, 1, O); |
7398 | 247 | break; |
7399 | 113 | case 35: |
7400 | | // VCVTh2ud, VCVTh2uq, VCVTh2xud, VCVTh2xuq, VTOUHH |
7401 | 113 | SStream_concat0(O, ".u16.f16\t"); |
7402 | 113 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16); |
7403 | 113 | printOperand(MI, 0, O); |
7404 | 113 | SStream_concat0(O, ", "); |
7405 | 113 | printOperand(MI, 1, O); |
7406 | 113 | break; |
7407 | 16 | case 36: |
7408 | | // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS |
7409 | 16 | SStream_concat0(O, ".f32.s32\t"); |
7410 | 16 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32); |
7411 | 16 | printOperand(MI, 0, O); |
7412 | 16 | SStream_concat0(O, ", "); |
7413 | 16 | printOperand(MI, 1, O); |
7414 | 16 | break; |
7415 | 175 | case 37: |
7416 | | // VCVTs2hd, VCVTs2hq, VCVTxs2hd, VCVTxs2hq, VSHTOH |
7417 | 175 | SStream_concat0(O, ".f16.s16\t"); |
7418 | 175 | printOperand(MI, 0, O); |
7419 | 175 | SStream_concat0(O, ", "); |
7420 | 175 | printOperand(MI, 1, O); |
7421 | 175 | break; |
7422 | 38 | case 38: |
7423 | | // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS |
7424 | 38 | SStream_concat0(O, ".f32.u32\t"); |
7425 | 38 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32); |
7426 | 38 | printOperand(MI, 0, O); |
7427 | 38 | SStream_concat0(O, ", "); |
7428 | 38 | printOperand(MI, 1, O); |
7429 | 38 | break; |
7430 | 145 | case 39: |
7431 | | // VCVTu2hd, VCVTu2hq, VCVTxu2hd, VCVTxu2hq, VUHTOH |
7432 | 145 | SStream_concat0(O, ".f16.u16\t"); |
7433 | 145 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16); |
7434 | 145 | printOperand(MI, 0, O); |
7435 | 145 | SStream_concat0(O, ", "); |
7436 | 145 | printOperand(MI, 1, O); |
7437 | 145 | break; |
7438 | 3.71k | case 40: |
7439 | | // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD... |
7440 | 3.71k | SStream_concat0(O, ".64\t"); |
7441 | 3.71k | ARM_addVectorDataSize(MI, 64); |
7442 | 3.71k | break; |
7443 | 949 | case 41: |
7444 | | // VJCVT, VTOSIRD, VTOSIZD, VTOSLD |
7445 | 949 | SStream_concat0(O, ".s32.f64\t"); |
7446 | 949 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64); |
7447 | 949 | printOperand(MI, 0, O); |
7448 | 949 | SStream_concat0(O, ", "); |
7449 | 949 | printOperand(MI, 1, O); |
7450 | 949 | break; |
7451 | 6.08k | case 42: |
7452 | | // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... |
7453 | 6.08k | SStream_concat0(O, ".16\t{"); |
7454 | 6.08k | ARM_addVectorDataSize(MI, 16); |
7455 | 6.08k | break; |
7456 | 6.95k | case 43: |
7457 | | // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... |
7458 | 6.95k | SStream_concat0(O, ".32\t{"); |
7459 | 6.95k | ARM_addVectorDataSize(MI, 32); |
7460 | 6.95k | break; |
7461 | 7.62k | case 44: |
7462 | | // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... |
7463 | 7.62k | SStream_concat0(O, ".8\t{"); |
7464 | 7.62k | ARM_addVectorDataSize(MI, 8); |
7465 | 7.62k | break; |
7466 | 87 | case 45: |
7467 | | // VMSR |
7468 | 87 | SStream_concat0(O, "\tfpscr, "); |
7469 | 87 | ARM_addReg(MI, ARM_REG_FPSCR); |
7470 | 87 | printOperand(MI, 0, O); |
7471 | 87 | return; |
7472 | 0 | break; |
7473 | 1.38k | case 46: |
7474 | | // VMSR_FPEXC |
7475 | 1.38k | SStream_concat0(O, "\tfpexc, "); |
7476 | 1.38k | ARM_addReg(MI, ARM_REG_FPEXC); |
7477 | 1.38k | printOperand(MI, 0, O); |
7478 | 1.38k | return; |
7479 | 0 | break; |
7480 | 69 | case 47: |
7481 | | // VMSR_FPINST |
7482 | 69 | SStream_concat0(O, "\tfpinst, "); |
7483 | 69 | ARM_addReg(MI, ARM_REG_FPINST); |
7484 | 69 | printOperand(MI, 0, O); |
7485 | 69 | return; |
7486 | 0 | break; |
7487 | 129 | case 48: |
7488 | | // VMSR_FPINST2 |
7489 | 129 | SStream_concat0(O, "\tfpinst2, "); |
7490 | 129 | ARM_addReg(MI, ARM_REG_FPINST2); |
7491 | 129 | printOperand(MI, 0, O); |
7492 | 129 | return; |
7493 | 0 | break; |
7494 | 58 | case 49: |
7495 | | // VMSR_FPSID |
7496 | 58 | SStream_concat0(O, "\tfpsid, "); |
7497 | 58 | ARM_addReg(MI, ARM_REG_FPSID); |
7498 | 58 | printOperand(MI, 0, O); |
7499 | 58 | return; |
7500 | 0 | break; |
7501 | 34 | case 50: |
7502 | | // VMULLp8, VMULpd, VMULpq |
7503 | 34 | SStream_concat0(O, ".p8\t"); |
7504 | 34 | ARM_addVectorDataType(MI, ARM_VECTORDATA_P8); |
7505 | 34 | printOperand(MI, 0, O); |
7506 | 34 | SStream_concat0(O, ", "); |
7507 | 34 | printOperand(MI, 1, O); |
7508 | 34 | SStream_concat0(O, ", "); |
7509 | 34 | printOperand(MI, 2, O); |
7510 | 34 | return; |
7511 | 0 | break; |
7512 | 746 | case 51: |
7513 | | // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... |
7514 | 746 | SStream_concat0(O, ".s64\t"); |
7515 | 746 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S64); |
7516 | 746 | printOperand(MI, 0, O); |
7517 | 746 | SStream_concat0(O, ", "); |
7518 | 746 | break; |
7519 | 870 | case 52: |
7520 | | // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ... |
7521 | 870 | SStream_concat0(O, ".u64\t"); |
7522 | 870 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U64); |
7523 | 870 | printOperand(MI, 0, O); |
7524 | 870 | SStream_concat0(O, ", "); |
7525 | 870 | break; |
7526 | 67 | case 53: |
7527 | | // VSDOTDI, VSDOTQI, VUDOTDI, VUDOTQI |
7528 | 67 | printVectorIndex(MI, 4, O); |
7529 | 67 | return; |
7530 | 0 | break; |
7531 | 68 | case 54: |
7532 | | // VSHTOD |
7533 | 68 | SStream_concat0(O, ".f64.s16\t"); |
7534 | 68 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16); |
7535 | 68 | printOperand(MI, 0, O); |
7536 | 68 | SStream_concat0(O, ", "); |
7537 | 68 | printOperand(MI, 1, O); |
7538 | 68 | SStream_concat0(O, ", "); |
7539 | 68 | printFBits16(MI, 2, O); |
7540 | 68 | return; |
7541 | 0 | break; |
7542 | 109 | case 55: |
7543 | | // VSHTOS |
7544 | 109 | SStream_concat0(O, ".f32.s16\t"); |
7545 | 109 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16); |
7546 | 109 | printOperand(MI, 0, O); |
7547 | 109 | SStream_concat0(O, ", "); |
7548 | 109 | printOperand(MI, 1, O); |
7549 | 109 | SStream_concat0(O, ", "); |
7550 | 109 | printFBits16(MI, 2, O); |
7551 | 109 | return; |
7552 | 0 | break; |
7553 | 106 | case 56: |
7554 | | // VSITOD, VSLTOD |
7555 | 106 | SStream_concat0(O, ".f64.s32\t"); |
7556 | 106 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32); |
7557 | 106 | printOperand(MI, 0, O); |
7558 | 106 | SStream_concat0(O, ", "); |
7559 | 106 | printOperand(MI, 1, O); |
7560 | 106 | break; |
7561 | 13 | case 57: |
7562 | | // VSITOH, VSLTOH |
7563 | 13 | SStream_concat0(O, ".f16.s32\t"); |
7564 | 13 | printOperand(MI, 0, O); |
7565 | 13 | SStream_concat0(O, ", "); |
7566 | 13 | printOperand(MI, 1, O); |
7567 | 13 | break; |
7568 | 12 | case 58: |
7569 | | // VTOSHD |
7570 | 12 | SStream_concat0(O, ".s16.f64\t"); |
7571 | 12 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64); |
7572 | 12 | printOperand(MI, 0, O); |
7573 | 12 | SStream_concat0(O, ", "); |
7574 | 12 | printOperand(MI, 1, O); |
7575 | 12 | SStream_concat0(O, ", "); |
7576 | 12 | printFBits16(MI, 2, O); |
7577 | 12 | return; |
7578 | 0 | break; |
7579 | 29 | case 59: |
7580 | | // VTOSHS |
7581 | 29 | SStream_concat0(O, ".s16.f32\t"); |
7582 | 29 | ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32); |
7583 | 29 | printOperand(MI, 0, O); |
7584 | 29 | SStream_concat0(O, ", "); |
7585 | 29 | printOperand(MI, 1, O); |
7586 | 29 | SStream_concat0(O, ", "); |
7587 | 29 | printFBits16(MI, 2, O); |
7588 | 29 | return; |
7589 | 0 | break; |
7590 | 76 | case 60: |
7591 | | // VTOSIRH, VTOSIZH, VTOSLH |
7592 | 76 | SStream_concat0(O, ".s32.f16\t"); |
7593 | 76 | printOperand(MI, 0, O); |
7594 | 76 | SStream_concat0(O, ", "); |
7595 | 76 | printOperand(MI, 1, O); |
7596 | 76 | break; |
7597 | 21 | case 61: |
7598 | | // VTOUHD |
7599 | 21 | SStream_concat0(O, ".u16.f64\t"); |
7600 | 21 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64); |
7601 | 21 | printOperand(MI, 0, O); |
7602 | 21 | SStream_concat0(O, ", "); |
7603 | 21 | printOperand(MI, 1, O); |
7604 | 21 | SStream_concat0(O, ", "); |
7605 | 21 | printFBits16(MI, 2, O); |
7606 | 21 | return; |
7607 | 0 | break; |
7608 | 118 | case 62: |
7609 | | // VTOUHS |
7610 | 118 | SStream_concat0(O, ".u16.f32\t"); |
7611 | 118 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32); |
7612 | 118 | printOperand(MI, 0, O); |
7613 | 118 | SStream_concat0(O, ", "); |
7614 | 118 | printOperand(MI, 1, O); |
7615 | 118 | SStream_concat0(O, ", "); |
7616 | 118 | printFBits16(MI, 2, O); |
7617 | 118 | return; |
7618 | 0 | break; |
7619 | 125 | case 63: |
7620 | | // VTOUIRD, VTOUIZD, VTOULD |
7621 | 125 | SStream_concat0(O, ".u32.f64\t"); |
7622 | 125 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64); |
7623 | 125 | printOperand(MI, 0, O); |
7624 | 125 | SStream_concat0(O, ", "); |
7625 | 125 | printOperand(MI, 1, O); |
7626 | 125 | break; |
7627 | 28 | case 64: |
7628 | | // VTOUIRH, VTOUIZH, VTOULH |
7629 | 28 | SStream_concat0(O, ".u32.f16\t"); |
7630 | 28 | ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16); |
7631 | 28 | printOperand(MI, 0, O); |
7632 | 28 | SStream_concat0(O, ", "); |
7633 | 28 | printOperand(MI, 1, O); |
7634 | 28 | break; |
7635 | 178 | case 65: |
7636 | | // VUHTOD |
7637 | 178 | SStream_concat0(O, ".f64.u16\t"); |
7638 | 178 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16); |
7639 | 178 | printOperand(MI, 0, O); |
7640 | 178 | SStream_concat0(O, ", "); |
7641 | 178 | printOperand(MI, 1, O); |
7642 | 178 | SStream_concat0(O, ", "); |
7643 | 178 | printFBits16(MI, 2, O); |
7644 | 178 | return; |
7645 | 0 | break; |
7646 | 452 | case 66: |
7647 | | // VUHTOS |
7648 | 452 | SStream_concat0(O, ".f32.u16\t"); |
7649 | 452 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16); |
7650 | 452 | printOperand(MI, 0, O); |
7651 | 452 | SStream_concat0(O, ", "); |
7652 | 452 | printOperand(MI, 1, O); |
7653 | 452 | SStream_concat0(O, ", "); |
7654 | 452 | printFBits16(MI, 2, O); |
7655 | 452 | return; |
7656 | 0 | break; |
7657 | 238 | case 67: |
7658 | | // VUITOD, VULTOD |
7659 | 238 | SStream_concat0(O, ".f64.u32\t"); |
7660 | 238 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32); |
7661 | 238 | printOperand(MI, 0, O); |
7662 | 238 | SStream_concat0(O, ", "); |
7663 | 238 | printOperand(MI, 1, O); |
7664 | 238 | break; |
7665 | 34 | case 68: |
7666 | | // VUITOH, VULTOH |
7667 | 34 | SStream_concat0(O, ".f16.u32\t"); |
7668 | 34 | ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32); |
7669 | 34 | printOperand(MI, 0, O); |
7670 | 34 | SStream_concat0(O, ", "); |
7671 | 34 | printOperand(MI, 1, O); |
7672 | 34 | break; |
7673 | 25.1k | case 69: |
7674 | | // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ... |
7675 | 25.1k | SStream_concat0(O, ".w\t"); |
7676 | 25.1k | break; |
7677 | 250 | case 70: |
7678 | | // t2SRSDB, t2SRSIA |
7679 | 250 | SStream_concat0(O, "\tsp, "); |
7680 | 250 | ARM_addReg(MI, ARM_REG_SP); |
7681 | 250 | printOperand(MI, 0, O); |
7682 | 250 | return; |
7683 | 0 | break; |
7684 | 114 | case 71: |
7685 | | // t2SRSDB_UPD, t2SRSIA_UPD |
7686 | 114 | SStream_concat0(O, "\tsp!, "); |
7687 | 114 | ARM_addReg(MI, ARM_REG_SP); |
7688 | 114 | printOperand(MI, 0, O); |
7689 | 114 | return; |
7690 | 0 | break; |
7691 | 87 | case 72: |
7692 | | // t2SUBS_PC_LR |
7693 | 87 | SStream_concat0(O, "\tpc, lr, "); |
7694 | 87 | printOperand(MI, 0, O); |
7695 | 87 | return; |
7696 | 0 | break; |
7697 | 260k | case 73: |
7698 | | // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... |
7699 | 260k | printPredicateOperand(MI, 4, O); |
7700 | 260k | SStream_concat0(O, "\t"); |
7701 | 260k | printOperand(MI, 0, O); |
7702 | 260k | SStream_concat0(O, ", "); |
7703 | 260k | break; |
7704 | 30.6k | case 74: |
7705 | | // tMOVi8, tMVN, tRSB |
7706 | 30.6k | printPredicateOperand(MI, 3, O); |
7707 | 30.6k | SStream_concat0(O, "\t"); |
7708 | 30.6k | printOperand(MI, 0, O); |
7709 | 30.6k | SStream_concat0(O, ", "); |
7710 | 30.6k | printOperand(MI, 2, O); |
7711 | 30.6k | break; |
7712 | 1.34M | } |
7713 | | |
7714 | | |
7715 | | // Fragment 2 encoded into 6 bits for 60 unique commands. |
7716 | | // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 63)); |
7717 | 1.33M | switch ((Bits >> 24) & 63) { |
7718 | 0 | default: // unreachable |
7719 | 652k | case 0: |
7720 | | // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... |
7721 | 652k | printOperand(MI, 0, O); |
7722 | 652k | break; |
7723 | 20.6k | case 1: |
7724 | | // ITasm, t2IT |
7725 | 20.6k | printMandatoryPredicateOperand(MI, 0, O); |
7726 | 20.6k | return; |
7727 | 0 | break; |
7728 | 0 | case 2: |
7729 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... |
7730 | 0 | printVectorListThreeAllLanes(MI, 0, O); |
7731 | 0 | SStream_concat0(O, ", "); |
7732 | 0 | printAddrMode6Operand(MI, 1, O); |
7733 | 0 | break; |
7734 | 0 | case 3: |
7735 | | // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... |
7736 | 0 | printVectorListThreeSpacedAllLanes(MI, 0, O); |
7737 | 0 | SStream_concat0(O, ", "); |
7738 | 0 | printAddrMode6Operand(MI, 1, O); |
7739 | 0 | break; |
7740 | 1.00k | case 4: |
7741 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... |
7742 | 1.00k | printVectorListThree(MI, 0, O); |
7743 | 1.00k | SStream_concat0(O, ", "); |
7744 | 1.00k | break; |
7745 | 0 | case 5: |
7746 | | // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... |
7747 | 0 | printVectorListThreeSpaced(MI, 0, O); |
7748 | 0 | SStream_concat0(O, ", "); |
7749 | 0 | printAddrMode6Operand(MI, 1, O); |
7750 | 0 | break; |
7751 | 0 | case 6: |
7752 | | // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... |
7753 | 0 | printVectorListFourAllLanes(MI, 0, O); |
7754 | 0 | SStream_concat0(O, ", "); |
7755 | 0 | printAddrMode6Operand(MI, 1, O); |
7756 | 0 | break; |
7757 | 0 | case 7: |
7758 | | // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... |
7759 | 0 | printVectorListFourSpacedAllLanes(MI, 0, O); |
7760 | 0 | SStream_concat0(O, ", "); |
7761 | 0 | printAddrMode6Operand(MI, 1, O); |
7762 | 0 | break; |
7763 | 2.25k | case 8: |
7764 | | // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... |
7765 | 2.25k | printVectorListFour(MI, 0, O); |
7766 | 2.25k | SStream_concat0(O, ", "); |
7767 | 2.25k | break; |
7768 | 0 | case 9: |
7769 | | // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... |
7770 | 0 | printVectorListFourSpaced(MI, 0, O); |
7771 | 0 | SStream_concat0(O, ", "); |
7772 | 0 | printAddrMode6Operand(MI, 1, O); |
7773 | 0 | break; |
7774 | 200k | case 10: |
7775 | | // AESD, AESE, MCR2, MCRR2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1, SHA256... |
7776 | 200k | printOperand(MI, 2, O); |
7777 | 200k | break; |
7778 | 231k | case 11: |
7779 | | // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM... |
7780 | 231k | printOperand(MI, 1, O); |
7781 | 231k | break; |
7782 | 47.4k | case 12: |
7783 | | // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... |
7784 | 47.4k | printPImmediate(MI, 0, O); |
7785 | 47.4k | SStream_concat0(O, ", "); |
7786 | 47.4k | break; |
7787 | 1.00k | case 13: |
7788 | | // CDP2 |
7789 | 1.00k | printCImmediate(MI, 2, O); |
7790 | 1.00k | SStream_concat0(O, ", "); |
7791 | 1.00k | printCImmediate(MI, 3, O); |
7792 | 1.00k | SStream_concat0(O, ", "); |
7793 | 1.00k | printCImmediate(MI, 4, O); |
7794 | 1.00k | SStream_concat0(O, ", "); |
7795 | 1.00k | printOperand(MI, 5, O); |
7796 | 1.00k | return; |
7797 | 0 | break; |
7798 | 489 | case 14: |
7799 | | // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS |
7800 | 489 | printCPSIFlag(MI, 1, O); |
7801 | 489 | break; |
7802 | 5.91k | case 15: |
7803 | | // FCONSTD, FCONSTH, FCONSTS, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABS... |
7804 | 5.91k | SStream_concat0(O, ", "); |
7805 | 5.91k | break; |
7806 | 94 | case 16: |
7807 | | // LDAEXD, LDREXD |
7808 | 94 | printGPRPairOperand(MI, 0, O); |
7809 | 94 | SStream_concat0(O, ", "); |
7810 | 94 | printAddrMode7Operand(MI, 1, O); |
7811 | 94 | return; |
7812 | 0 | break; |
7813 | 3.09k | case 17: |
7814 | | // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET |
7815 | 3.09k | printAddrMode5Operand(MI, 2, O, false); |
7816 | 3.09k | return; |
7817 | 0 | break; |
7818 | 1.92k | case 18: |
7819 | | // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... |
7820 | 1.92k | printAddrMode7Operand(MI, 2, O); |
7821 | 1.92k | SStream_concat0(O, ", "); |
7822 | 1.92k | break; |
7823 | 1.70k | case 19: |
7824 | | // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE |
7825 | 1.70k | printAddrMode5Operand(MI, 2, O, true); |
7826 | 1.70k | SStream_concat0(O, "!"); |
7827 | 1.70k | return; |
7828 | 0 | break; |
7829 | 3.71k | case 20: |
7830 | | // MRC, t2MRC, t2MRC2 |
7831 | 3.71k | printPImmediate(MI, 1, O); |
7832 | 3.71k | SStream_concat0(O, ", "); |
7833 | 3.71k | printOperand(MI, 2, O); |
7834 | 3.71k | SStream_concat0(O, ", "); |
7835 | 3.71k | printOperand(MI, 0, O); |
7836 | 3.71k | SStream_concat0(O, ", "); |
7837 | 3.71k | printCImmediate(MI, 3, O); |
7838 | 3.71k | SStream_concat0(O, ", "); |
7839 | 3.71k | printCImmediate(MI, 4, O); |
7840 | 3.71k | SStream_concat0(O, ", "); |
7841 | 3.71k | printOperand(MI, 5, O); |
7842 | 3.71k | return; |
7843 | 0 | break; |
7844 | 1.04k | case 21: |
7845 | | // MRRC, t2MRRC, t2MRRC2 |
7846 | 1.04k | printPImmediate(MI, 2, O); |
7847 | 1.04k | SStream_concat0(O, ", "); |
7848 | 1.04k | printOperand(MI, 3, O); |
7849 | 1.04k | SStream_concat0(O, ", "); |
7850 | 1.04k | printOperand(MI, 0, O); |
7851 | 1.04k | SStream_concat0(O, ", "); |
7852 | 1.04k | printOperand(MI, 1, O); |
7853 | 1.04k | SStream_concat0(O, ", "); |
7854 | 1.04k | printCImmediate(MI, 4, O); |
7855 | 1.04k | return; |
7856 | 0 | break; |
7857 | 6.22k | case 22: |
7858 | | // MSR, MSRi, t2MSR_AR, t2MSR_M |
7859 | 6.22k | printMSRMaskOperand(MI, 0, O); |
7860 | 6.22k | SStream_concat0(O, ", "); |
7861 | 6.22k | break; |
7862 | 495 | case 23: |
7863 | | // MSRbanked, t2MSRbanked |
7864 | 495 | printBankedRegOperand(MI, 0, O); |
7865 | 495 | SStream_concat0(O, ", "); |
7866 | 495 | printOperand(MI, 1, O); |
7867 | 495 | return; |
7868 | 0 | break; |
7869 | 2.30k | case 24: |
7870 | | // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ... |
7871 | 2.30k | printNEONModImmOperand(MI, 1, O); |
7872 | 2.30k | return; |
7873 | 0 | break; |
7874 | 1.49k | case 25: |
7875 | | // VCMPEZD, VCMPEZH, VCMPEZS, VCMPZD, VCMPZH, VCMPZS, tRSB |
7876 | 1.49k | SStream_concat0(O, ", #0"); |
7877 | 1.49k | op_addImm(MI, 0); |
7878 | 1.49k | return; |
7879 | 0 | break; |
7880 | 30.5k | case 26: |
7881 | | // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTh2sd, VCVTh2sq, VCVTh2ud, ... |
7882 | 30.5k | return; |
7883 | 0 | break; |
7884 | 226 | case 27: |
7885 | | // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... |
7886 | 226 | printVectorListOneAllLanes(MI, 0, O); |
7887 | 226 | SStream_concat0(O, ", "); |
7888 | 226 | break; |
7889 | 1.40k | case 28: |
7890 | | // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... |
7891 | 1.40k | printVectorListTwoAllLanes(MI, 0, O); |
7892 | 1.40k | SStream_concat0(O, ", "); |
7893 | 1.40k | break; |
7894 | 1.46k | case 29: |
7895 | | // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... |
7896 | 1.46k | printVectorListOne(MI, 0, O); |
7897 | 1.46k | SStream_concat0(O, ", "); |
7898 | 1.46k | break; |
7899 | 3.41k | case 30: |
7900 | | // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... |
7901 | 3.41k | printVectorListTwo(MI, 0, O); |
7902 | 3.41k | SStream_concat0(O, ", "); |
7903 | 3.41k | break; |
7904 | 1.14k | case 31: |
7905 | | // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... |
7906 | 1.14k | printVectorListTwoSpacedAllLanes(MI, 0, O); |
7907 | 1.14k | SStream_concat0(O, ", "); |
7908 | 1.14k | break; |
7909 | 1.92k | case 32: |
7910 | | // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... |
7911 | 1.92k | printVectorListTwoSpaced(MI, 0, O); |
7912 | 1.92k | SStream_concat0(O, ", "); |
7913 | 1.92k | break; |
7914 | 7.26k | case 33: |
7915 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... |
7916 | 7.26k | printOperand(MI, 4, O); |
7917 | 7.26k | break; |
7918 | 222 | case 34: |
7919 | | // VST1d16, VST1d32, VST1d64, VST1d8 |
7920 | 222 | printVectorListOne(MI, 2, O); |
7921 | 222 | SStream_concat0(O, ", "); |
7922 | 222 | printAddrMode6Operand(MI, 0, O); |
7923 | 222 | return; |
7924 | 0 | break; |
7925 | 382 | case 35: |
7926 | | // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 |
7927 | 382 | printVectorListFour(MI, 2, O); |
7928 | 382 | SStream_concat0(O, ", "); |
7929 | 382 | printAddrMode6Operand(MI, 0, O); |
7930 | 382 | return; |
7931 | 0 | break; |
7932 | 1.63k | case 36: |
7933 | | // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... |
7934 | 1.63k | printVectorListFour(MI, 3, O); |
7935 | 1.63k | SStream_concat0(O, ", "); |
7936 | 1.63k | printAddrMode6Operand(MI, 1, O); |
7937 | 1.63k | SStream_concat0(O, "!"); |
7938 | 1.63k | return; |
7939 | 0 | break; |
7940 | 1.72k | case 37: |
7941 | | // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... |
7942 | 1.72k | printVectorListFour(MI, 4, O); |
7943 | 1.72k | SStream_concat0(O, ", "); |
7944 | 1.72k | printAddrMode6Operand(MI, 1, O); |
7945 | 1.72k | SStream_concat0(O, ", "); |
7946 | 1.72k | printOperand(MI, 3, O); |
7947 | 1.72k | return; |
7948 | 0 | break; |
7949 | 110 | case 38: |
7950 | | // VST1d16T, VST1d32T, VST1d64T, VST1d8T |
7951 | 110 | printVectorListThree(MI, 2, O); |
7952 | 110 | SStream_concat0(O, ", "); |
7953 | 110 | printAddrMode6Operand(MI, 0, O); |
7954 | 110 | return; |
7955 | 0 | break; |
7956 | 892 | case 39: |
7957 | | // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed |
7958 | 892 | printVectorListThree(MI, 3, O); |
7959 | 892 | SStream_concat0(O, ", "); |
7960 | 892 | printAddrMode6Operand(MI, 1, O); |
7961 | 892 | SStream_concat0(O, "!"); |
7962 | 892 | return; |
7963 | 0 | break; |
7964 | 708 | case 40: |
7965 | | // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... |
7966 | 708 | printVectorListThree(MI, 4, O); |
7967 | 708 | SStream_concat0(O, ", "); |
7968 | 708 | printAddrMode6Operand(MI, 1, O); |
7969 | 708 | SStream_concat0(O, ", "); |
7970 | 708 | printOperand(MI, 3, O); |
7971 | 708 | return; |
7972 | 0 | break; |
7973 | 411 | case 41: |
7974 | | // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed |
7975 | 411 | printVectorListOne(MI, 3, O); |
7976 | 411 | SStream_concat0(O, ", "); |
7977 | 411 | printAddrMode6Operand(MI, 1, O); |
7978 | 411 | SStream_concat0(O, "!"); |
7979 | 411 | return; |
7980 | 0 | break; |
7981 | 737 | case 42: |
7982 | | // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... |
7983 | 737 | printVectorListOne(MI, 4, O); |
7984 | 737 | SStream_concat0(O, ", "); |
7985 | 737 | printAddrMode6Operand(MI, 1, O); |
7986 | 737 | SStream_concat0(O, ", "); |
7987 | 737 | printOperand(MI, 3, O); |
7988 | 737 | return; |
7989 | 0 | break; |
7990 | 1.95k | case 43: |
7991 | | // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 |
7992 | 1.95k | printVectorListTwo(MI, 2, O); |
7993 | 1.95k | SStream_concat0(O, ", "); |
7994 | 1.95k | printAddrMode6Operand(MI, 0, O); |
7995 | 1.95k | return; |
7996 | 0 | break; |
7997 | 1.02k | case 44: |
7998 | | // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... |
7999 | 1.02k | printVectorListTwo(MI, 3, O); |
8000 | 1.02k | SStream_concat0(O, ", "); |
8001 | 1.02k | printAddrMode6Operand(MI, 1, O); |
8002 | 1.02k | SStream_concat0(O, "!"); |
8003 | 1.02k | return; |
8004 | 0 | break; |
8005 | 2.23k | case 45: |
8006 | | // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... |
8007 | 2.23k | printVectorListTwo(MI, 4, O); |
8008 | 2.23k | SStream_concat0(O, ", "); |
8009 | 2.23k | printAddrMode6Operand(MI, 1, O); |
8010 | 2.23k | SStream_concat0(O, ", "); |
8011 | 2.23k | printOperand(MI, 3, O); |
8012 | 2.23k | return; |
8013 | 0 | break; |
8014 | 820 | case 46: |
8015 | | // VST2b16, VST2b32, VST2b8 |
8016 | 820 | printVectorListTwoSpaced(MI, 2, O); |
8017 | 820 | SStream_concat0(O, ", "); |
8018 | 820 | printAddrMode6Operand(MI, 0, O); |
8019 | 820 | return; |
8020 | 0 | break; |
8021 | 591 | case 47: |
8022 | | // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed |
8023 | 591 | printVectorListTwoSpaced(MI, 3, O); |
8024 | 591 | SStream_concat0(O, ", "); |
8025 | 591 | printAddrMode6Operand(MI, 1, O); |
8026 | 591 | SStream_concat0(O, "!"); |
8027 | 591 | return; |
8028 | 0 | break; |
8029 | 966 | case 48: |
8030 | | // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register |
8031 | 966 | printVectorListTwoSpaced(MI, 4, O); |
8032 | 966 | SStream_concat0(O, ", "); |
8033 | 966 | printAddrMode6Operand(MI, 1, O); |
8034 | 966 | SStream_concat0(O, ", "); |
8035 | 966 | printOperand(MI, 3, O); |
8036 | 966 | return; |
8037 | 0 | break; |
8038 | 1.29k | case 49: |
8039 | | // t2DMB, t2DSB |
8040 | 1.29k | printMemBOption(MI, 0, O); |
8041 | 1.29k | return; |
8042 | 0 | break; |
8043 | 568 | case 50: |
8044 | | // t2ISB |
8045 | 568 | printInstSyncBOption(MI, 0, O); |
8046 | 568 | return; |
8047 | 0 | break; |
8048 | 314 | case 51: |
8049 | | // t2PLDWi12, t2PLDi12, t2PLIi12 |
8050 | 314 | printAddrModeImm12Operand(MI, 0, O, false); |
8051 | 314 | return; |
8052 | 0 | break; |
8053 | 523 | case 52: |
8054 | | // t2PLDWi8, t2PLDi8, t2PLIi8 |
8055 | 523 | printT2AddrModeImm8Operand(MI, 0, O, false); |
8056 | 523 | return; |
8057 | 0 | break; |
8058 | 353 | case 53: |
8059 | | // t2PLDWs, t2PLDs, t2PLIs |
8060 | 353 | printT2AddrModeSoRegOperand(MI, 0, O); |
8061 | 353 | return; |
8062 | 0 | break; |
8063 | 1.69k | case 54: |
8064 | | // t2PLDpci, t2PLIpci |
8065 | 1.69k | printThumbLdrLabelOperand(MI, 0, O); |
8066 | 1.69k | return; |
8067 | 0 | break; |
8068 | 63 | case 55: |
8069 | | // t2TBB |
8070 | 63 | printAddrModeTBB(MI, 0, O); |
8071 | 63 | return; |
8072 | 0 | break; |
8073 | 395 | case 56: |
8074 | | // t2TBH |
8075 | 395 | printAddrModeTBH(MI, 0, O); |
8076 | 395 | return; |
8077 | 0 | break; |
8078 | 0 | case 57: |
8079 | | // t2TSB |
8080 | 0 | printTraceSyncBOption(MI, 0, O); |
8081 | 0 | return; |
8082 | 0 | break; |
8083 | 71.5k | case 58: |
8084 | | // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS... |
8085 | 71.5k | printOperand(MI, 3, O); |
8086 | 71.5k | return; |
8087 | 0 | break; |
8088 | 9.26k | case 59: |
8089 | | // tPOP, tPUSH |
8090 | 9.26k | printRegisterList(MI, 2, O); |
8091 | 9.26k | return; |
8092 | 0 | break; |
8093 | 1.33M | } |
8094 | | |
8095 | | |
8096 | | // Fragment 3 encoded into 5 bits for 30 unique commands. |
8097 | | // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 30) & 31)); |
8098 | 1.16M | switch ((Bits >> 30) & 31) { |
8099 | 0 | default: // unreachable |
8100 | 791k | case 0: |
8101 | | // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... |
8102 | 791k | SStream_concat0(O, ", "); |
8103 | 791k | break; |
8104 | 260k | case 1: |
8105 | | // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... |
8106 | 260k | return; |
8107 | 0 | break; |
8108 | 14 | case 2: |
8109 | | // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... |
8110 | 14 | SStream_concat0(O, "!"); |
8111 | 14 | return; |
8112 | 0 | break; |
8113 | 3.23k | case 3: |
8114 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... |
8115 | 3.23k | printAddrMode6Operand(MI, 1, O); |
8116 | 3.23k | break; |
8117 | 19.5k | case 4: |
8118 | | // CDP, MCR, MCRR, MSR, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABSH, VAB... |
8119 | 19.5k | printOperand(MI, 1, O); |
8120 | 19.5k | break; |
8121 | 573 | case 5: |
8122 | | // FCONSTD, FCONSTH, FCONSTS, VMOVv2f32, VMOVv4f32 |
8123 | 573 | printFPImmOperand(MI, 1, O); |
8124 | 573 | return; |
8125 | 0 | break; |
8126 | 25.9k | case 6: |
8127 | | // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... |
8128 | 25.9k | SStream_concat0(O, "!, "); |
8129 | 25.9k | printRegisterList(MI, 4, O); |
8130 | 25.9k | break; |
8131 | 675 | case 7: |
8132 | | // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION |
8133 | 675 | printCoprocOptionImm(MI, 3, O); |
8134 | 675 | return; |
8135 | 0 | break; |
8136 | 1.24k | case 8: |
8137 | | // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST |
8138 | 1.24k | printPostIdxImm8s4Operand(MI, 3, O); |
8139 | 1.24k | return; |
8140 | 0 | break; |
8141 | 35.2k | case 9: |
8142 | | // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... |
8143 | 35.2k | printCImmediate(MI, 1, O); |
8144 | 35.2k | SStream_concat0(O, ", "); |
8145 | 35.2k | break; |
8146 | 884 | case 10: |
8147 | | // MRS, t2MRS_AR |
8148 | 884 | SStream_concat0(O, ", apsr"); |
8149 | 884 | ARM_addReg(MI, ARM_REG_APSR); |
8150 | 884 | return; |
8151 | 0 | break; |
8152 | 30 | case 11: |
8153 | | // MRSsys, t2MRSsys_AR |
8154 | 30 | SStream_concat0(O, ", spsr"); |
8155 | 30 | ARM_addReg(MI, ARM_REG_SPSR); |
8156 | 30 | return; |
8157 | 0 | break; |
8158 | 309 | case 12: |
8159 | | // MSRi |
8160 | 309 | printModImmOperand(MI, 1, O); |
8161 | 309 | return; |
8162 | 0 | break; |
8163 | 293 | case 13: |
8164 | | // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,... |
8165 | 293 | SStream_concat0(O, ", #0"); |
8166 | 293 | op_addImm(MI, 0); |
8167 | 293 | return; |
8168 | 0 | break; |
8169 | 3.27k | case 14: |
8170 | | // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTh2xsd, VCVTh2xsq, VCVT... |
8171 | 3.27k | printOperand(MI, 2, O); |
8172 | 3.27k | break; |
8173 | 213 | case 15: |
8174 | | // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8 |
8175 | 213 | printVectorIndex(MI, 2, O); |
8176 | 213 | return; |
8177 | 0 | break; |
8178 | 9.60k | case 16: |
8179 | | // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... |
8180 | 9.60k | printAddrMode6Operand(MI, 2, O); |
8181 | 9.60k | break; |
8182 | 10.4k | case 17: |
8183 | | // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... |
8184 | 10.4k | SStream_concat0(O, "["); |
8185 | 10.4k | set_mem_access(MI, true); |
8186 | 10.4k | break; |
8187 | 1.38k | case 18: |
8188 | | // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... |
8189 | 1.38k | SStream_concat0(O, "[], "); |
8190 | 1.38k | printOperand(MI, 1, O); |
8191 | 1.38k | SStream_concat0(O, "[], "); |
8192 | 1.38k | printOperand(MI, 2, O); |
8193 | 1.38k | break; |
8194 | 32 | case 19: |
8195 | | // VMRS |
8196 | 32 | SStream_concat0(O, ", fpscr"); |
8197 | 32 | ARM_addReg(MI, ARM_REG_FPSCR); |
8198 | 32 | return; |
8199 | 0 | break; |
8200 | 96 | case 20: |
8201 | | // VMRS_FPEXC |
8202 | 96 | SStream_concat0(O, ", fpexc"); |
8203 | 96 | ARM_addReg(MI, ARM_REG_FPEXC); |
8204 | 96 | return; |
8205 | 0 | break; |
8206 | 16 | case 21: |
8207 | | // VMRS_FPINST |
8208 | 16 | SStream_concat0(O, ", fpinst"); |
8209 | 16 | ARM_addReg(MI, ARM_REG_FPINST); |
8210 | 16 | return; |
8211 | 0 | break; |
8212 | 30 | case 22: |
8213 | | // VMRS_FPINST2 |
8214 | 30 | SStream_concat0(O, ", fpinst2"); |
8215 | 30 | ARM_addReg(MI, ARM_REG_FPINST2); |
8216 | 30 | return; |
8217 | 0 | break; |
8218 | 132 | case 23: |
8219 | | // VMRS_FPSID |
8220 | 132 | SStream_concat0(O, ", fpsid"); |
8221 | 132 | ARM_addReg(MI, ARM_REG_FPSID); |
8222 | 132 | return; |
8223 | 0 | break; |
8224 | 141 | case 24: |
8225 | | // VMRS_MVFR0 |
8226 | 141 | SStream_concat0(O, ", mvfr0"); |
8227 | 141 | ARM_addReg(MI, ARM_REG_MVFR0); |
8228 | 141 | return; |
8229 | 0 | break; |
8230 | 1.19k | case 25: |
8231 | | // VMRS_MVFR1 |
8232 | 1.19k | SStream_concat0(O, ", mvfr1"); |
8233 | 1.19k | ARM_addReg(MI, ARM_REG_MVFR1); |
8234 | 1.19k | return; |
8235 | 0 | break; |
8236 | 215 | case 26: |
8237 | | // VMRS_MVFR2 |
8238 | 215 | SStream_concat0(O, ", mvfr2"); |
8239 | 215 | ARM_addReg(MI, ARM_REG_MVFR2); |
8240 | 215 | return; |
8241 | 0 | break; |
8242 | 743 | case 27: |
8243 | | // VSETLNi16, VSETLNi32, VSETLNi8 |
8244 | 743 | printVectorIndex(MI, 3, O); |
8245 | 743 | SStream_concat0(O, ", "); |
8246 | 743 | printOperand(MI, 2, O); |
8247 | 743 | return; |
8248 | 0 | break; |
8249 | 88 | case 28: |
8250 | | // VSHTOH, VTOSHH, VTOUHH, VUHTOH |
8251 | 88 | printFBits16(MI, 2, O); |
8252 | 88 | return; |
8253 | 0 | break; |
8254 | 445 | case 29: |
8255 | | // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... |
8256 | 445 | printFBits32(MI, 2, O); |
8257 | 445 | return; |
8258 | 0 | break; |
8259 | 1.16M | } |
8260 | | |
8261 | | |
8262 | | // Fragment 4 encoded into 7 bits for 65 unique commands. |
8263 | | // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 35) & 127)); |
8264 | 899k | switch ((Bits >> 35) & 127) { |
8265 | 0 | default: // unreachable |
8266 | 167k | case 0: |
8267 | | // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... |
8268 | 167k | printOperand(MI, 1, O); |
8269 | 167k | break; |
8270 | 389 | case 1: |
8271 | | // LDRBT_POST, LDRT_POST, STRBT_POST, STRT_POST, LDA, LDAB, LDAEX, LDAEXB... |
8272 | 389 | printAddrMode7Operand(MI, 1, O); |
8273 | 389 | return; |
8274 | 0 | break; |
8275 | 0 | case 2: |
8276 | | // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... |
8277 | 0 | printAddrMode6Operand(MI, 2, O); |
8278 | 0 | break; |
8279 | 126k | case 3: |
8280 | | // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... |
8281 | 126k | printOperand(MI, 3, O); |
8282 | 126k | break; |
8283 | 31.0k | case 4: |
8284 | | // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... |
8285 | 31.0k | return; |
8286 | 0 | break; |
8287 | 4.70k | case 5: |
8288 | | // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... |
8289 | 4.70k | SStream_concat0(O, "!"); |
8290 | 4.70k | return; |
8291 | 0 | break; |
8292 | 20.5k | case 6: |
8293 | | // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... |
8294 | 20.5k | SStream_concat0(O, ", "); |
8295 | 20.5k | break; |
8296 | 1.13k | case 7: |
8297 | | // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs |
8298 | 1.13k | printT2SOOperand(MI, 1, O); |
8299 | 1.13k | return; |
8300 | 0 | break; |
8301 | 1.95k | case 8: |
8302 | | // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr |
8303 | 1.95k | printSORegRegOperand(MI, 1, O); |
8304 | 1.95k | return; |
8305 | 0 | break; |
8306 | 0 | case 9: |
8307 | | // ADR, t2ADR |
8308 | 0 | printAdrLabelOperand(MI, 1, O, 0); |
8309 | 0 | return; |
8310 | 0 | break; |
8311 | 490 | case 10: |
8312 | | // BFC, t2BFC |
8313 | 490 | printBitfieldInvMaskImmOperand(MI, 2, O); |
8314 | 490 | return; |
8315 | 0 | break; |
8316 | 25.2k | case 11: |
8317 | | // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16... |
8318 | 25.2k | printOperand(MI, 2, O); |
8319 | 25.2k | break; |
8320 | 2.89k | case 12: |
8321 | | // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri |
8322 | 2.89k | printModImmOperand(MI, 1, O); |
8323 | 2.89k | return; |
8324 | 0 | break; |
8325 | 2.80k | case 13: |
8326 | | // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi |
8327 | 2.80k | printSORegImmOperand(MI, 1, O); |
8328 | 2.80k | return; |
8329 | 0 | break; |
8330 | 7.63k | case 14: |
8331 | | // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... |
8332 | 7.63k | printRegisterList(MI, 3, O); |
8333 | 7.63k | break; |
8334 | 10.8k | case 15: |
8335 | | // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... |
8336 | 10.8k | printAddrMode5Operand(MI, 2, O, false); |
8337 | 10.8k | return; |
8338 | 0 | break; |
8339 | 40.8k | case 16: |
8340 | | // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... |
8341 | 40.8k | printAddrMode7Operand(MI, 2, O); |
8342 | 40.8k | break; |
8343 | 9.70k | case 17: |
8344 | | // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... |
8345 | 9.70k | printAddrMode5Operand(MI, 2, O, true); |
8346 | 9.70k | SStream_concat0(O, "!"); |
8347 | 9.70k | return; |
8348 | 0 | break; |
8349 | 5.54k | case 18: |
8350 | | // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM |
8351 | 5.54k | printAddrModeImm12Operand(MI, 2, O, true); |
8352 | 5.54k | SStream_concat0(O, "!"); |
8353 | 5.54k | return; |
8354 | 0 | break; |
8355 | 2.70k | case 19: |
8356 | | // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG |
8357 | 2.70k | printAddrMode2Operand(MI, 2, O); |
8358 | 2.70k | SStream_concat0(O, "!"); |
8359 | 2.70k | return; |
8360 | 0 | break; |
8361 | 6.71k | case 20: |
8362 | | // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... |
8363 | 6.71k | printAddrModeImm12Operand(MI, 1, O, false); |
8364 | 6.71k | return; |
8365 | 0 | break; |
8366 | 2.53k | case 21: |
8367 | | // LDRBrs, LDRrs, STRBrs, STRrs |
8368 | 2.53k | printAddrMode2Operand(MI, 1, O); |
8369 | 2.53k | return; |
8370 | 0 | break; |
8371 | 1.78k | case 22: |
8372 | | // LDRH, LDRSB, LDRSH, STRH |
8373 | 1.78k | printAddrMode3Operand(MI, 1, O, false); |
8374 | 1.78k | return; |
8375 | 0 | break; |
8376 | 2.33k | case 23: |
8377 | | // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE |
8378 | 2.33k | printAddrMode3Operand(MI, 2, O, true); |
8379 | 2.33k | SStream_concat0(O, "!"); |
8380 | 2.33k | return; |
8381 | 0 | break; |
8382 | 306 | case 24: |
8383 | | // MCR2 |
8384 | 306 | printCImmediate(MI, 3, O); |
8385 | 306 | SStream_concat0(O, ", "); |
8386 | 306 | printCImmediate(MI, 4, O); |
8387 | 306 | SStream_concat0(O, ", "); |
8388 | 306 | printOperand(MI, 5, O); |
8389 | 306 | return; |
8390 | 0 | break; |
8391 | 236 | case 25: |
8392 | | // MRSbanked, t2MRSbanked |
8393 | 236 | printBankedRegOperand(MI, 1, O); |
8394 | 236 | return; |
8395 | 0 | break; |
8396 | 1.23k | case 26: |
8397 | | // SSAT, SSAT16, t2SSAT, t2SSAT16 |
8398 | 1.23k | printImmPlusOneOperand(MI, 1, O); |
8399 | 1.23k | SStream_concat0(O, ", "); |
8400 | 1.23k | printOperand(MI, 2, O); |
8401 | 1.23k | break; |
8402 | 580 | case 27: |
8403 | | // STLEXD, STREXD |
8404 | 580 | printGPRPairOperand(MI, 1, O); |
8405 | 580 | SStream_concat0(O, ", "); |
8406 | 580 | printAddrMode7Operand(MI, 2, O); |
8407 | 580 | return; |
8408 | 0 | break; |
8409 | 207 | case 28: |
8410 | | // VCEQzv2f32, VCEQzv4f16, VCEQzv4f32, VCEQzv8f16, VCGEzv2f32, VCGEzv4f16... |
8411 | 207 | SStream_concat0(O, ", #0"); |
8412 | 207 | op_addImm(MI, 0); |
8413 | 207 | return; |
8414 | 0 | break; |
8415 | 309 | case 29: |
8416 | | // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... |
8417 | 309 | printNoHashImmediate(MI, 4, O); |
8418 | 309 | break; |
8419 | 2.00k | case 30: |
8420 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... |
8421 | 2.00k | printNoHashImmediate(MI, 6, O); |
8422 | 2.00k | break; |
8423 | 3.21k | case 31: |
8424 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
8425 | 3.21k | printNoHashImmediate(MI, 8, O); |
8426 | 3.21k | SStream_concat0(O, "], "); |
8427 | 3.21k | set_mem_access(MI, false); |
8428 | 3.21k | break; |
8429 | 317 | case 32: |
8430 | | // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... |
8431 | 317 | SStream_concat0(O, "[]}, "); |
8432 | 317 | break; |
8433 | 1.19k | case 33: |
8434 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
8435 | 1.19k | printNoHashImmediate(MI, 10, O); |
8436 | 1.19k | SStream_concat0(O, "], "); |
8437 | 1.19k | set_mem_access(MI, false); |
8438 | 1.19k | printOperand(MI, 1, O); |
8439 | 1.19k | SStream_concat0(O, "["); |
8440 | 1.19k | set_mem_access(MI, true); |
8441 | 1.19k | printNoHashImmediate(MI, 10, O); |
8442 | 1.19k | SStream_concat0(O, "], "); |
8443 | 1.19k | set_mem_access(MI, false); |
8444 | 1.19k | printOperand(MI, 2, O); |
8445 | 1.19k | SStream_concat0(O, "["); |
8446 | 1.19k | set_mem_access(MI, true); |
8447 | 1.19k | printNoHashImmediate(MI, 10, O); |
8448 | 1.19k | break; |
8449 | 1.06k | case 34: |
8450 | | // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... |
8451 | 1.06k | SStream_concat0(O, "[], "); |
8452 | 1.06k | printOperand(MI, 3, O); |
8453 | 1.06k | SStream_concat0(O, "[]}, "); |
8454 | 1.06k | break; |
8455 | 987 | case 35: |
8456 | | // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... |
8457 | 987 | printNoHashImmediate(MI, 12, O); |
8458 | 987 | SStream_concat0(O, "], "); |
8459 | 987 | set_mem_access(MI, false); |
8460 | 987 | printOperand(MI, 1, O); |
8461 | 987 | SStream_concat0(O, "["); |
8462 | 987 | set_mem_access(MI, true); |
8463 | 987 | printNoHashImmediate(MI, 12, O); |
8464 | 987 | SStream_concat0(O, "], "); |
8465 | 987 | set_mem_access(MI, false); |
8466 | 987 | printOperand(MI, 2, O); |
8467 | 987 | SStream_concat0(O, "["); |
8468 | 987 | set_mem_access(MI, true); |
8469 | 987 | printNoHashImmediate(MI, 12, O); |
8470 | 987 | SStream_concat0(O, "], "); |
8471 | 987 | set_mem_access(MI, false); |
8472 | 987 | printOperand(MI, 3, O); |
8473 | 987 | SStream_concat0(O, "["); |
8474 | 987 | set_mem_access(MI, true); |
8475 | 987 | printNoHashImmediate(MI, 12, O); |
8476 | 987 | SStream_concat0(O, "]}, "); |
8477 | 987 | set_mem_access(MI, false); |
8478 | 987 | printAddrMode6Operand(MI, 5, O); |
8479 | 987 | printAddrMode6OffsetOperand(MI, 7, O); |
8480 | 987 | return; |
8481 | 0 | break; |
8482 | 477 | case 36: |
8483 | | // VLDRD, VLDRS, VSTRD, VSTRS |
8484 | 477 | printAddrMode5Operand(MI, 1, O, false); |
8485 | 477 | return; |
8486 | 0 | break; |
8487 | 317 | case 37: |
8488 | | // VLDRH, VSTRH |
8489 | 317 | printAddrMode5FP16Operand(MI, 1, O, false); |
8490 | 317 | return; |
8491 | 0 | break; |
8492 | 504 | case 38: |
8493 | | // VST1LNd16, VST1LNd32, VST1LNd8 |
8494 | 504 | printNoHashImmediate(MI, 3, O); |
8495 | 504 | SStream_concat0(O, "]}, "); |
8496 | 504 | set_mem_access(MI, false); |
8497 | 504 | printAddrMode6Operand(MI, 0, O); |
8498 | 504 | return; |
8499 | 0 | break; |
8500 | 875 | case 39: |
8501 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... |
8502 | 875 | printNoHashImmediate(MI, 5, O); |
8503 | 875 | break; |
8504 | 1.40k | case 40: |
8505 | | // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... |
8506 | 1.40k | printNoHashImmediate(MI, 7, O); |
8507 | 1.40k | SStream_concat0(O, "], "); |
8508 | 1.40k | set_mem_access(MI, false); |
8509 | 1.40k | printOperand(MI, 5, O); |
8510 | 1.40k | SStream_concat0(O, "["); |
8511 | 1.40k | set_mem_access(MI, true); |
8512 | 1.40k | printNoHashImmediate(MI, 7, O); |
8513 | 1.40k | SStream_concat0(O, "], "); |
8514 | 1.40k | set_mem_access(MI, false); |
8515 | 1.40k | printOperand(MI, 6, O); |
8516 | 1.40k | SStream_concat0(O, "["); |
8517 | 1.40k | set_mem_access(MI, true); |
8518 | 1.40k | printNoHashImmediate(MI, 7, O); |
8519 | 1.40k | SStream_concat0(O, "]}, "); |
8520 | 1.40k | set_mem_access(MI, false); |
8521 | 1.40k | printAddrMode6Operand(MI, 1, O); |
8522 | 1.40k | printAddrMode6OffsetOperand(MI, 3, O); |
8523 | 1.40k | return; |
8524 | 0 | break; |
8525 | 2.99k | case 41: |
8526 | | // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... |
8527 | 2.99k | printOperand(MI, 5, O); |
8528 | 2.99k | SStream_concat0(O, ", "); |
8529 | 2.99k | printOperand(MI, 6, O); |
8530 | 2.99k | break; |
8531 | 67 | case 42: |
8532 | | // VTBL1 |
8533 | 67 | printVectorListOne(MI, 1, O); |
8534 | 67 | SStream_concat0(O, ", "); |
8535 | 67 | printOperand(MI, 2, O); |
8536 | 67 | return; |
8537 | 0 | break; |
8538 | 135 | case 43: |
8539 | | // VTBL2 |
8540 | 135 | printVectorListTwo(MI, 1, O); |
8541 | 135 | SStream_concat0(O, ", "); |
8542 | 135 | printOperand(MI, 2, O); |
8543 | 135 | return; |
8544 | 0 | break; |
8545 | 207 | case 44: |
8546 | | // VTBL3 |
8547 | 207 | printVectorListThree(MI, 1, O); |
8548 | 207 | SStream_concat0(O, ", "); |
8549 | 207 | printOperand(MI, 2, O); |
8550 | 207 | return; |
8551 | 0 | break; |
8552 | 66 | case 45: |
8553 | | // VTBL4 |
8554 | 66 | printVectorListFour(MI, 1, O); |
8555 | 66 | SStream_concat0(O, ", "); |
8556 | 66 | printOperand(MI, 2, O); |
8557 | 66 | return; |
8558 | 0 | break; |
8559 | 87 | case 46: |
8560 | | // VTBX1 |
8561 | 87 | printVectorListOne(MI, 2, O); |
8562 | 87 | SStream_concat0(O, ", "); |
8563 | 87 | printOperand(MI, 3, O); |
8564 | 87 | return; |
8565 | 0 | break; |
8566 | 125 | case 47: |
8567 | | // VTBX2 |
8568 | 125 | printVectorListTwo(MI, 2, O); |
8569 | 125 | SStream_concat0(O, ", "); |
8570 | 125 | printOperand(MI, 3, O); |
8571 | 125 | return; |
8572 | 0 | break; |
8573 | 162 | case 48: |
8574 | | // VTBX3 |
8575 | 162 | printVectorListThree(MI, 2, O); |
8576 | 162 | SStream_concat0(O, ", "); |
8577 | 162 | printOperand(MI, 3, O); |
8578 | 162 | return; |
8579 | 0 | break; |
8580 | 194 | case 49: |
8581 | | // VTBX4 |
8582 | 194 | printVectorListFour(MI, 2, O); |
8583 | 194 | SStream_concat0(O, ", "); |
8584 | 194 | printOperand(MI, 3, O); |
8585 | 194 | return; |
8586 | 0 | break; |
8587 | 5.15k | case 50: |
8588 | | // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... |
8589 | 5.15k | SStream_concat0(O, " ^"); |
8590 | 5.15k | ARM_addUserMode(MI); |
8591 | 5.15k | return; |
8592 | 0 | break; |
8593 | 3.26k | case 51: |
8594 | | // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t... |
8595 | 3.26k | printT2AddrModeImm8Operand(MI, 1, O, false); |
8596 | 3.26k | return; |
8597 | 0 | break; |
8598 | 495 | case 52: |
8599 | | // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR... |
8600 | 495 | printT2AddrModeImm8Operand(MI, 2, O, true); |
8601 | 495 | SStream_concat0(O, "!"); |
8602 | 495 | return; |
8603 | 0 | break; |
8604 | 30.2k | case 53: |
8605 | | // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci |
8606 | 30.2k | printThumbLdrLabelOperand(MI, 1, O); |
8607 | 30.2k | return; |
8608 | 0 | break; |
8609 | 929 | case 54: |
8610 | | // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs |
8611 | 929 | printT2AddrModeSoRegOperand(MI, 1, O); |
8612 | 929 | return; |
8613 | 0 | break; |
8614 | 258 | case 55: |
8615 | | // t2LDREX |
8616 | 258 | printT2AddrModeImm0_1020s4Operand(MI, 1, O); |
8617 | 258 | return; |
8618 | 0 | break; |
8619 | 1.28k | case 56: |
8620 | | // t2MRS_M |
8621 | 1.28k | printMSRMaskOperand(MI, 1, O); |
8622 | 1.28k | return; |
8623 | 0 | break; |
8624 | 2.20k | case 57: |
8625 | | // tADDspi, tSUBspi |
8626 | 2.20k | printThumbS4ImmOperand(MI, 2, O); |
8627 | 2.20k | return; |
8628 | 0 | break; |
8629 | 24.3k | case 58: |
8630 | | // tADR |
8631 | 24.3k | printAdrLabelOperand(MI, 1, O, 2); |
8632 | 24.3k | return; |
8633 | 0 | break; |
8634 | 67.5k | case 59: |
8635 | | // tASRri, tLSRri |
8636 | 67.5k | printThumbSRImm(MI, 3, O); |
8637 | 67.5k | return; |
8638 | 0 | break; |
8639 | 57.3k | case 60: |
8640 | | // tLDRBi, tSTRBi |
8641 | 57.3k | printThumbAddrModeImm5S1Operand(MI, 1, O); |
8642 | 57.3k | return; |
8643 | 0 | break; |
8644 | 37.4k | case 61: |
8645 | | // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr |
8646 | 37.4k | printThumbAddrModeRROperand(MI, 1, O); |
8647 | 37.4k | return; |
8648 | 0 | break; |
8649 | 57.5k | case 62: |
8650 | | // tLDRHi, tSTRHi |
8651 | 57.5k | printThumbAddrModeImm5S2Operand(MI, 1, O); |
8652 | 57.5k | return; |
8653 | 0 | break; |
8654 | 79.2k | case 63: |
8655 | | // tLDRi, tSTRi |
8656 | 79.2k | printThumbAddrModeImm5S4Operand(MI, 1, O); |
8657 | 79.2k | return; |
8658 | 0 | break; |
8659 | 37.6k | case 64: |
8660 | | // tLDRspi, tSTRspi |
8661 | 37.6k | printThumbAddrModeSPOperand(MI, 1, O); |
8662 | 37.6k | return; |
8663 | 0 | break; |
8664 | 899k | } |
8665 | | |
8666 | | |
8667 | | // Fragment 5 encoded into 5 bits for 23 unique commands. |
8668 | | // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 31)); |
8669 | 401k | switch ((Bits >> 42) & 31) { |
8670 | 0 | default: // unreachable |
8671 | 173k | case 0: |
8672 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... |
8673 | 173k | SStream_concat0(O, ", "); |
8674 | 173k | break; |
8675 | 188k | case 1: |
8676 | | // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... |
8677 | 188k | return; |
8678 | 0 | break; |
8679 | 0 | case 2: |
8680 | | // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... |
8681 | 0 | SStream_concat0(O, "!"); |
8682 | 0 | return; |
8683 | 0 | break; |
8684 | 2.48k | case 3: |
8685 | | // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... |
8686 | 2.48k | printOperand(MI, 3, O); |
8687 | 2.48k | break; |
8688 | 7.60k | case 4: |
8689 | | // CDP, t2CDP, t2CDP2 |
8690 | 7.60k | printCImmediate(MI, 2, O); |
8691 | 7.60k | SStream_concat0(O, ", "); |
8692 | 7.60k | printCImmediate(MI, 3, O); |
8693 | 7.60k | SStream_concat0(O, ", "); |
8694 | 7.60k | printCImmediate(MI, 4, O); |
8695 | 7.60k | SStream_concat0(O, ", "); |
8696 | 7.60k | printOperand(MI, 5, O); |
8697 | 7.60k | return; |
8698 | 0 | break; |
8699 | 5.52k | case 5: |
8700 | | // MCR, MCRR, VABDfd, VABDfq, VABDhd, VABDhq, VACGEfd, VACGEfq, VACGEhd, ... |
8701 | 5.52k | printOperand(MI, 2, O); |
8702 | 5.52k | break; |
8703 | 811 | case 6: |
8704 | | // SSAT, t2SSAT |
8705 | 811 | printShiftImmOperand(MI, 3, O); |
8706 | 811 | return; |
8707 | 0 | break; |
8708 | 1.10k | case 7: |
8709 | | // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... |
8710 | 1.10k | printRotImmOperand(MI, 2, O); |
8711 | 1.10k | return; |
8712 | 0 | break; |
8713 | 1.10k | case 8: |
8714 | | // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... |
8715 | 1.10k | printVectorIndex(MI, 4, O); |
8716 | 1.10k | break; |
8717 | 451 | case 9: |
8718 | | // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN... |
8719 | 451 | printVectorIndex(MI, 2, O); |
8720 | 451 | return; |
8721 | 0 | break; |
8722 | 4.90k | case 10: |
8723 | | // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL... |
8724 | 4.90k | printOperand(MI, 4, O); |
8725 | 4.90k | return; |
8726 | 0 | break; |
8727 | 2.53k | case 11: |
8728 | | // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... |
8729 | 2.53k | SStream_concat0(O, "]}, "); |
8730 | 2.53k | set_mem_access(MI, false); |
8731 | 2.53k | break; |
8732 | 1.84k | case 12: |
8733 | | // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... |
8734 | 1.84k | SStream_concat0(O, "], "); |
8735 | 1.84k | set_mem_access(MI, false); |
8736 | 1.84k | break; |
8737 | 2.00k | case 13: |
8738 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
8739 | 2.00k | printOperand(MI, 1, O); |
8740 | 2.00k | SStream_concat0(O, "["); |
8741 | 2.00k | set_mem_access(MI, true); |
8742 | 2.00k | printNoHashImmediate(MI, 8, O); |
8743 | 2.00k | break; |
8744 | 143 | case 14: |
8745 | | // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 |
8746 | 143 | printAddrMode6Operand(MI, 3, O); |
8747 | 143 | return; |
8748 | 0 | break; |
8749 | 405 | case 15: |
8750 | | // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... |
8751 | 405 | printAddrMode6Operand(MI, 4, O); |
8752 | 405 | break; |
8753 | 835 | case 16: |
8754 | | // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... |
8755 | 835 | printAddrMode6Operand(MI, 5, O); |
8756 | 835 | printAddrMode6OffsetOperand(MI, 7, O); |
8757 | 835 | return; |
8758 | 0 | break; |
8759 | 1.16k | case 17: |
8760 | | // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3... |
8761 | 1.16k | printVectorIndex(MI, 3, O); |
8762 | 1.16k | return; |
8763 | 0 | break; |
8764 | 634 | case 18: |
8765 | | // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... |
8766 | 634 | SStream_concat0(O, "}, "); |
8767 | 634 | printAddrMode6Operand(MI, 1, O); |
8768 | 634 | printAddrMode6OffsetOperand(MI, 3, O); |
8769 | 634 | return; |
8770 | 0 | break; |
8771 | 1.21k | case 19: |
8772 | | // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... |
8773 | 1.21k | printOperand(MI, 5, O); |
8774 | 1.21k | SStream_concat0(O, "["); |
8775 | 1.21k | set_mem_access(MI, true); |
8776 | 1.21k | printNoHashImmediate(MI, 8, O); |
8777 | 1.21k | SStream_concat0(O, "], "); |
8778 | 1.21k | set_mem_access(MI, false); |
8779 | 1.21k | printOperand(MI, 6, O); |
8780 | 1.21k | SStream_concat0(O, "["); |
8781 | 1.21k | set_mem_access(MI, true); |
8782 | 1.21k | printNoHashImmediate(MI, 8, O); |
8783 | 1.21k | SStream_concat0(O, "], "); |
8784 | 1.21k | set_mem_access(MI, false); |
8785 | 1.21k | printOperand(MI, 7, O); |
8786 | 1.21k | SStream_concat0(O, "["); |
8787 | 1.21k | set_mem_access(MI, true); |
8788 | 1.21k | printNoHashImmediate(MI, 8, O); |
8789 | 1.21k | SStream_concat0(O, "]}, "); |
8790 | 1.21k | set_mem_access(MI, false); |
8791 | 1.21k | printAddrMode6Operand(MI, 1, O); |
8792 | 1.21k | printAddrMode6OffsetOperand(MI, 3, O); |
8793 | 1.21k | return; |
8794 | 0 | break; |
8795 | 2.85k | case 20: |
8796 | | // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... |
8797 | 2.85k | SStream_concat0(O, " ^"); |
8798 | 2.85k | ARM_addUserMode(MI); |
8799 | 2.85k | return; |
8800 | 0 | break; |
8801 | 1.30k | case 21: |
8802 | | // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST... |
8803 | 1.30k | printT2AddrModeImm8OffsetOperand(MI, 3, O); |
8804 | 1.30k | return; |
8805 | 0 | break; |
8806 | 0 | case 22: |
8807 | | // t2MOVsra_flag, t2MOVsrl_flag |
8808 | 0 | SStream_concat0(O, ", #1"); |
8809 | 0 | op_addImm(MI, 1); |
8810 | 0 | return; |
8811 | 0 | break; |
8812 | 401k | } |
8813 | | |
8814 | | |
8815 | | // Fragment 6 encoded into 6 bits for 38 unique commands. |
8816 | | // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 63)); |
8817 | 189k | switch ((Bits >> 47) & 63) { |
8818 | 0 | default: // unreachable |
8819 | 43.9k | case 0: |
8820 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... |
8821 | 43.9k | printOperand(MI, 2, O); |
8822 | 43.9k | break; |
8823 | 1.87k | case 1: |
8824 | | // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... |
8825 | 1.87k | printOperand(MI, 4, O); |
8826 | 1.87k | break; |
8827 | 3.61k | case 2: |
8828 | | // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... |
8829 | 3.61k | return; |
8830 | 0 | break; |
8831 | 10.7k | case 3: |
8832 | | // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri |
8833 | 10.7k | printModImmOperand(MI, 2, O); |
8834 | 10.7k | return; |
8835 | 0 | break; |
8836 | 15.9k | case 4: |
8837 | | // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... |
8838 | 15.9k | printSORegImmOperand(MI, 2, O); |
8839 | 15.9k | return; |
8840 | 0 | break; |
8841 | 863 | case 5: |
8842 | | // BFI, t2BFI |
8843 | 863 | printBitfieldInvMaskImmOperand(MI, 3, O); |
8844 | 863 | return; |
8845 | 0 | break; |
8846 | 4.41k | case 6: |
8847 | | // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... |
8848 | 4.41k | printCoprocOptionImm(MI, 3, O); |
8849 | 4.41k | return; |
8850 | 0 | break; |
8851 | 10.2k | case 7: |
8852 | | // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... |
8853 | 10.2k | printPostIdxImm8s4Operand(MI, 3, O); |
8854 | 10.2k | return; |
8855 | 0 | break; |
8856 | 18.1k | case 8: |
8857 | | // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... |
8858 | 18.1k | printAddrMode2OffsetOperand(MI, 3, O); |
8859 | 18.1k | return; |
8860 | 0 | break; |
8861 | 949 | case 9: |
8862 | | // LDRD, STRD |
8863 | 949 | printAddrMode3Operand(MI, 2, O, false); |
8864 | 949 | return; |
8865 | 0 | break; |
8866 | 4.67k | case 10: |
8867 | | // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST |
8868 | 4.67k | printAddrMode7Operand(MI, 3, O); |
8869 | 4.67k | break; |
8870 | 793 | case 11: |
8871 | | // LDRD_PRE, STRD_PRE |
8872 | 793 | printAddrMode3Operand(MI, 3, O, true); |
8873 | 793 | SStream_concat0(O, "!"); |
8874 | 793 | return; |
8875 | 0 | break; |
8876 | 1.29k | case 12: |
8877 | | // LDRHTi, LDRSBTi, LDRSHTi, STRHTi |
8878 | 1.29k | printPostIdxImm8Operand(MI, 3, O); |
8879 | 1.29k | return; |
8880 | 0 | break; |
8881 | 2.41k | case 13: |
8882 | | // LDRHTr, LDRSBTr, LDRSHTr, STRHTr |
8883 | 2.41k | printPostIdxRegOperand(MI, 3, O); |
8884 | 2.41k | return; |
8885 | 0 | break; |
8886 | 3.01k | case 14: |
8887 | | // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST |
8888 | 3.01k | printAddrMode3OffsetOperand(MI, 3, O); |
8889 | 3.01k | return; |
8890 | 0 | break; |
8891 | 4.72k | case 15: |
8892 | | // MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed,... |
8893 | 4.72k | SStream_concat0(O, ", "); |
8894 | 4.72k | break; |
8895 | 362 | case 16: |
8896 | | // MCRR2 |
8897 | 362 | printCImmediate(MI, 4, O); |
8898 | 362 | return; |
8899 | 0 | break; |
8900 | 1.43k | case 17: |
8901 | | // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... |
8902 | 1.43k | printAddrMode7Operand(MI, 2, O); |
8903 | 1.43k | return; |
8904 | 0 | break; |
8905 | 2.68k | case 18: |
8906 | | // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN... |
8907 | 2.68k | printOperand(MI, 3, O); |
8908 | 2.68k | break; |
8909 | 23 | case 19: |
8910 | | // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 |
8911 | 23 | printComplexRotationOp(MI, 3, O, 180, 90); |
8912 | 23 | return; |
8913 | 0 | break; |
8914 | 130 | case 20: |
8915 | | // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 |
8916 | 130 | printComplexRotationOp(MI, 4, O, 90, 0); |
8917 | 130 | return; |
8918 | 0 | break; |
8919 | 1.01k | case 21: |
8920 | | // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... |
8921 | 1.01k | printAddrMode6Operand(MI, 1, O); |
8922 | 1.01k | break; |
8923 | 739 | case 22: |
8924 | | // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD |
8925 | 739 | printAddrMode6Operand(MI, 2, O); |
8926 | 739 | printAddrMode6OffsetOperand(MI, 4, O); |
8927 | 739 | return; |
8928 | 0 | break; |
8929 | 275 | case 23: |
8930 | | // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 |
8931 | 275 | printOperand(MI, 1, O); |
8932 | 275 | SStream_concat0(O, "["); |
8933 | 275 | set_mem_access(MI, true); |
8934 | 275 | printNoHashImmediate(MI, 6, O); |
8935 | 275 | SStream_concat0(O, "]}, "); |
8936 | 275 | set_mem_access(MI, false); |
8937 | 275 | printAddrMode6Operand(MI, 2, O); |
8938 | 275 | return; |
8939 | 0 | break; |
8940 | 1.77k | case 24: |
8941 | | // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... |
8942 | 1.77k | SStream_concat0(O, "]}, "); |
8943 | 1.77k | set_mem_access(MI, false); |
8944 | 1.77k | printAddrMode6Operand(MI, 3, O); |
8945 | 1.77k | printAddrMode6OffsetOperand(MI, 5, O); |
8946 | 1.77k | return; |
8947 | 0 | break; |
8948 | 174 | case 25: |
8949 | | // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... |
8950 | 174 | printAddrMode6OffsetOperand(MI, 6, O); |
8951 | 174 | return; |
8952 | 0 | break; |
8953 | 222 | case 26: |
8954 | | // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 |
8955 | 222 | SStream_concat0(O, "], "); |
8956 | 222 | set_mem_access(MI, false); |
8957 | 222 | printOperand(MI, 2, O); |
8958 | 222 | SStream_concat0(O, "["); |
8959 | 222 | set_mem_access(MI, true); |
8960 | 222 | printNoHashImmediate(MI, 8, O); |
8961 | 222 | SStream_concat0(O, "]}, "); |
8962 | 222 | set_mem_access(MI, false); |
8963 | 222 | printAddrMode6Operand(MI, 3, O); |
8964 | 222 | return; |
8965 | 0 | break; |
8966 | 782 | case 27: |
8967 | | // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... |
8968 | 782 | printAddrMode6Operand(MI, 4, O); |
8969 | 782 | printAddrMode6OffsetOperand(MI, 6, O); |
8970 | 782 | return; |
8971 | 0 | break; |
8972 | 973 | case 28: |
8973 | | // VMLAslfd, VMLAslfq, VMLAslhd, VMLAslhq, VMLSslfd, VMLSslfq, VMLSslhd, ... |
8974 | 973 | printVectorIndex(MI, 4, O); |
8975 | 973 | return; |
8976 | 0 | break; |
8977 | 46 | case 29: |
8978 | | // VMULslfd, VMULslfq, VMULslhd, VMULslhq |
8979 | 46 | printVectorIndex(MI, 3, O); |
8980 | 46 | return; |
8981 | 0 | break; |
8982 | 880 | case 30: |
8983 | | // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U... |
8984 | 880 | printOperand(MI, 5, O); |
8985 | 880 | SStream_concat0(O, "["); |
8986 | 880 | set_mem_access(MI, true); |
8987 | 880 | printNoHashImmediate(MI, 6, O); |
8988 | 880 | SStream_concat0(O, "]}, "); |
8989 | 880 | set_mem_access(MI, false); |
8990 | 880 | printAddrMode6Operand(MI, 1, O); |
8991 | 880 | printAddrMode6OffsetOperand(MI, 3, O); |
8992 | 880 | return; |
8993 | 0 | break; |
8994 | 2.35k | case 31: |
8995 | | // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... |
8996 | 2.35k | printOperand(MI, 7, O); |
8997 | 2.35k | SStream_concat0(O, "}, "); |
8998 | 2.35k | printAddrMode6Operand(MI, 1, O); |
8999 | 2.35k | printAddrMode6OffsetOperand(MI, 3, O); |
9000 | 2.35k | return; |
9001 | 0 | break; |
9002 | 4.20k | case 32: |
9003 | | // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... |
9004 | 4.20k | printT2SOOperand(MI, 2, O); |
9005 | 4.20k | return; |
9006 | 0 | break; |
9007 | 470 | case 33: |
9008 | | // t2ASRri, t2LSRri |
9009 | 470 | printThumbSRImm(MI, 2, O); |
9010 | 470 | return; |
9011 | 0 | break; |
9012 | 10.5k | case 34: |
9013 | | // t2LDRD_PRE, t2STRD_PRE |
9014 | 10.5k | printT2AddrModeImm8s4Operand(MI, 3, O, true); |
9015 | 10.5k | SStream_concat0(O, "!"); |
9016 | 10.5k | return; |
9017 | 0 | break; |
9018 | 2.71k | case 35: |
9019 | | // t2LDRDi8, t2STRDi8 |
9020 | 2.71k | printT2AddrModeImm8s4Operand(MI, 2, O, false); |
9021 | 2.71k | return; |
9022 | 0 | break; |
9023 | 1.06k | case 36: |
9024 | | // t2STREX |
9025 | 1.06k | printT2AddrModeImm0_1020s4Operand(MI, 2, O); |
9026 | 1.06k | return; |
9027 | 0 | break; |
9028 | 28.8k | case 37: |
9029 | | // tADDrSPi |
9030 | 28.8k | printThumbS4ImmOperand(MI, 2, O); |
9031 | 28.8k | return; |
9032 | 0 | break; |
9033 | 189k | } |
9034 | | |
9035 | | |
9036 | | // Fragment 7 encoded into 4 bits for 13 unique commands. |
9037 | | // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 53) & 15)); |
9038 | 58.9k | switch ((Bits >> 53) & 15) { |
9039 | 0 | default: // unreachable |
9040 | 27.6k | case 0: |
9041 | | // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... |
9042 | 27.6k | return; |
9043 | 0 | break; |
9044 | 14.5k | case 1: |
9045 | | // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML... |
9046 | 14.5k | SStream_concat0(O, ", "); |
9047 | 14.5k | break; |
9048 | 3.42k | case 2: |
9049 | | // MCR, t2MCR, t2MCR2 |
9050 | 3.42k | printCImmediate(MI, 3, O); |
9051 | 3.42k | SStream_concat0(O, ", "); |
9052 | 3.42k | printCImmediate(MI, 4, O); |
9053 | 3.42k | SStream_concat0(O, ", "); |
9054 | 3.42k | printOperand(MI, 5, O); |
9055 | 3.42k | return; |
9056 | 0 | break; |
9057 | 1.10k | case 3: |
9058 | | // MCRR, t2MCRR, t2MCRR2 |
9059 | 1.10k | printOperand(MI, 3, O); |
9060 | 1.10k | SStream_concat0(O, ", "); |
9061 | 1.10k | printCImmediate(MI, 4, O); |
9062 | 1.10k | return; |
9063 | 0 | break; |
9064 | 1.00k | case 4: |
9065 | | // PKHBT, t2PKHBT |
9066 | 1.00k | printPKHLSLShiftImm(MI, 3, O); |
9067 | 1.00k | return; |
9068 | 0 | break; |
9069 | 465 | case 5: |
9070 | | // PKHTB, t2PKHTB |
9071 | 465 | printPKHASRShiftImm(MI, 3, O); |
9072 | 465 | return; |
9073 | 0 | break; |
9074 | 1.78k | case 6: |
9075 | | // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... |
9076 | 1.78k | printRotImmOperand(MI, 3, O); |
9077 | 1.78k | return; |
9078 | 0 | break; |
9079 | 1.62k | case 7: |
9080 | | // USAT, t2USAT |
9081 | 1.62k | printShiftImmOperand(MI, 3, O); |
9082 | 1.62k | return; |
9083 | 0 | break; |
9084 | 196 | case 8: |
9085 | | // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... |
9086 | 196 | printComplexRotationOp(MI, 5, O, 90, 0); |
9087 | 196 | return; |
9088 | 0 | break; |
9089 | 2.62k | case 9: |
9090 | | // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... |
9091 | 2.62k | SStream_concat0(O, "}, "); |
9092 | 2.62k | break; |
9093 | 686 | case 10: |
9094 | | // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... |
9095 | 686 | SStream_concat0(O, "["); |
9096 | 686 | set_mem_access(MI, true); |
9097 | 686 | break; |
9098 | 774 | case 11: |
9099 | | // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD |
9100 | 774 | printAddrMode6OffsetOperand(MI, 3, O); |
9101 | 774 | return; |
9102 | 0 | break; |
9103 | 3.04k | case 12: |
9104 | | // t2LDRD_POST, t2STRD_POST |
9105 | 3.04k | printT2AddrModeImm8s4OffsetOperand(MI, 4, O); |
9106 | 3.04k | return; |
9107 | 0 | break; |
9108 | 58.9k | } |
9109 | | |
9110 | | |
9111 | | // Fragment 8 encoded into 4 bits for 12 unique commands. |
9112 | | // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 57) & 15)); |
9113 | 17.8k | switch ((Bits >> 57) & 15) { |
9114 | 0 | default: // unreachable |
9115 | 1.62k | case 0: |
9116 | | // LDRD_POST, STRD_POST |
9117 | 1.62k | printAddrMode3OffsetOperand(MI, 4, O); |
9118 | 1.62k | return; |
9119 | 0 | break; |
9120 | 11.1k | case 1: |
9121 | | // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... |
9122 | 11.1k | printOperand(MI, 3, O); |
9123 | 11.1k | break; |
9124 | 460 | case 2: |
9125 | | // SBFX, UBFX, t2SBFX, t2UBFX |
9126 | 460 | printImmPlusOneOperand(MI, 3, O); |
9127 | 460 | return; |
9128 | 0 | break; |
9129 | 1.08k | case 3: |
9130 | | // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8 |
9131 | 1.08k | printAddrMode6Operand(MI, 3, O); |
9132 | 1.08k | return; |
9133 | 0 | break; |
9134 | 582 | case 4: |
9135 | | // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8... |
9136 | 582 | printAddrMode6Operand(MI, 4, O); |
9137 | 582 | printAddrMode6OffsetOperand(MI, 6, O); |
9138 | 582 | return; |
9139 | 0 | break; |
9140 | 409 | case 5: |
9141 | | // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32 |
9142 | 409 | printNoHashImmediate(MI, 10, O); |
9143 | 409 | SStream_concat0(O, "]}, "); |
9144 | 409 | set_mem_access(MI, false); |
9145 | 409 | printAddrMode6Operand(MI, 4, O); |
9146 | 409 | return; |
9147 | 0 | break; |
9148 | 67 | case 6: |
9149 | | // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32 |
9150 | 67 | printNoHashImmediate(MI, 4, O); |
9151 | 67 | SStream_concat0(O, "]}, "); |
9152 | 67 | set_mem_access(MI, false); |
9153 | 67 | printAddrMode6Operand(MI, 0, O); |
9154 | 67 | return; |
9155 | 0 | break; |
9156 | 101 | case 7: |
9157 | | // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32 |
9158 | 101 | printNoHashImmediate(MI, 5, O); |
9159 | 101 | SStream_concat0(O, "], "); |
9160 | 101 | set_mem_access(MI, false); |
9161 | 101 | printOperand(MI, 4, O); |
9162 | 101 | SStream_concat0(O, "["); |
9163 | 101 | set_mem_access(MI, true); |
9164 | 101 | printNoHashImmediate(MI, 5, O); |
9165 | 101 | SStream_concat0(O, "]}, "); |
9166 | 101 | set_mem_access(MI, false); |
9167 | 101 | printAddrMode6Operand(MI, 0, O); |
9168 | 101 | return; |
9169 | 0 | break; |
9170 | 954 | case 8: |
9171 | | // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8 |
9172 | 954 | printAddrMode6Operand(MI, 0, O); |
9173 | 954 | return; |
9174 | 0 | break; |
9175 | 109 | case 9: |
9176 | | // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32 |
9177 | 109 | printNoHashImmediate(MI, 6, O); |
9178 | 109 | SStream_concat0(O, "], "); |
9179 | 109 | set_mem_access(MI, false); |
9180 | 109 | printOperand(MI, 4, O); |
9181 | 109 | SStream_concat0(O, "["); |
9182 | 109 | set_mem_access(MI, true); |
9183 | 109 | printNoHashImmediate(MI, 6, O); |
9184 | 109 | SStream_concat0(O, "], "); |
9185 | 109 | set_mem_access(MI, false); |
9186 | 109 | printOperand(MI, 5, O); |
9187 | 109 | SStream_concat0(O, "["); |
9188 | 109 | set_mem_access(MI, true); |
9189 | 109 | printNoHashImmediate(MI, 6, O); |
9190 | 109 | SStream_concat0(O, "]}, "); |
9191 | 109 | set_mem_access(MI, false); |
9192 | 109 | printAddrMode6Operand(MI, 0, O); |
9193 | 109 | return; |
9194 | 0 | break; |
9195 | 920 | case 10: |
9196 | | // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8 |
9197 | 920 | printOperand(MI, 5, O); |
9198 | 920 | SStream_concat0(O, "}, "); |
9199 | 920 | printAddrMode6Operand(MI, 0, O); |
9200 | 920 | return; |
9201 | 0 | break; |
9202 | 376 | case 11: |
9203 | | // t2STLEXD, t2STREXD |
9204 | 376 | printAddrMode7Operand(MI, 3, O); |
9205 | 376 | return; |
9206 | 0 | break; |
9207 | 17.8k | } |
9208 | | |
9209 | | |
9210 | | // Fragment 9 encoded into 1 bits for 2 unique commands. |
9211 | | // printf("Fragment 9: %"PRIu64"\n", ((Bits >> 61) & 1)); |
9212 | 11.1k | if ((Bits >> 61) & 1) { |
9213 | | // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1... |
9214 | 2.26k | SStream_concat0(O, "}, "); |
9215 | 8.88k | } else { |
9216 | | // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... |
9217 | 8.88k | return; |
9218 | 8.88k | } |
9219 | | |
9220 | | |
9221 | | // Fragment 10 encoded into 1 bits for 2 unique commands. |
9222 | | // printf("Fragment 10: %"PRIu64"\n", ((Bits >> 62) & 1)); |
9223 | 2.26k | if ((Bits >> 62) & 1) { |
9224 | | // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8... |
9225 | 1.68k | printAddrMode6Operand(MI, 5, O); |
9226 | 1.68k | printAddrMode6OffsetOperand(MI, 7, O); |
9227 | 1.68k | return; |
9228 | 1.68k | } else { |
9229 | | // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8 |
9230 | 578 | printAddrMode6Operand(MI, 4, O); |
9231 | 578 | return; |
9232 | 578 | } |
9233 | | |
9234 | 2.26k | } |
9235 | | |
9236 | | |
9237 | | |
9238 | | #ifdef PRINT_ALIAS_INSTR |
9239 | | #undef PRINT_ALIAS_INSTR |
9240 | | |
9241 | | static bool printAliasInstr(MCInst *MI, SStream *OS) |
9242 | 1.36M | { |
9243 | 1.36M | unsigned int I = 0, OpIdx, PrintMethodIdx; |
9244 | 1.36M | char *tmpString; |
9245 | 1.36M | const char *AsmString; |
9246 | 1.36M | switch (MCInst_getOpcode(MI)) { |
9247 | 1.35M | default: return false; |
9248 | 89 | case ARM_DSB: |
9249 | 89 | if (MCInst_getNumOperands(MI) == 1 && |
9250 | 89 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9251 | 89 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && |
9252 | 89 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9253 | 89 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { |
9254 | | // (DSB 12) |
9255 | 10 | AsmString = "dfb"; |
9256 | 10 | break; |
9257 | 10 | } |
9258 | 79 | return false; |
9259 | 817 | case ARM_HINT: |
9260 | 817 | if (MCInst_getNumOperands(MI) == 3 && |
9261 | 817 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9262 | 817 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && |
9263 | 817 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9264 | 817 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9265 | | // (HINT 0, pred:$p) |
9266 | 40 | AsmString = "nop$\xFF\x02\x01"; |
9267 | 40 | break; |
9268 | 40 | } |
9269 | 777 | if (MCInst_getNumOperands(MI) == 3 && |
9270 | 777 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9271 | 777 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && |
9272 | 777 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9273 | 777 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9274 | | // (HINT 1, pred:$p) |
9275 | 278 | AsmString = "yield$\xFF\x02\x01"; |
9276 | 278 | break; |
9277 | 278 | } |
9278 | 499 | if (MCInst_getNumOperands(MI) == 3 && |
9279 | 499 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9280 | 499 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && |
9281 | 499 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9282 | 499 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9283 | | // (HINT 2, pred:$p) |
9284 | 16 | AsmString = "wfe$\xFF\x02\x01"; |
9285 | 16 | break; |
9286 | 16 | } |
9287 | 483 | if (MCInst_getNumOperands(MI) == 3 && |
9288 | 483 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9289 | 483 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && |
9290 | 483 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9291 | 483 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9292 | | // (HINT 3, pred:$p) |
9293 | 140 | AsmString = "wfi$\xFF\x02\x01"; |
9294 | 140 | break; |
9295 | 140 | } |
9296 | 343 | if (MCInst_getNumOperands(MI) == 3 && |
9297 | 343 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9298 | 343 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && |
9299 | 343 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9300 | 343 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9301 | | // (HINT 4, pred:$p) |
9302 | 18 | AsmString = "sev$\xFF\x02\x01"; |
9303 | 18 | break; |
9304 | 18 | } |
9305 | 325 | if (MCInst_getNumOperands(MI) == 3 && |
9306 | 325 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9307 | 325 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && |
9308 | 325 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9309 | 325 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { |
9310 | | // (HINT 5, pred:$p) |
9311 | 17 | AsmString = "sevl$\xFF\x02\x01"; |
9312 | 17 | break; |
9313 | 17 | } |
9314 | 308 | if (MCInst_getNumOperands(MI) == 3 && |
9315 | 308 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9316 | 308 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && |
9317 | 308 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9318 | 308 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { |
9319 | | // (HINT 16, pred:$p) |
9320 | 158 | AsmString = "esb$\xFF\x02\x01"; |
9321 | 158 | break; |
9322 | 158 | } |
9323 | 150 | if (MCInst_getNumOperands(MI) == 3 && |
9324 | 150 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9325 | 150 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && |
9326 | 150 | !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9327 | 150 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { |
9328 | | // (HINT 20, pred:$p) |
9329 | 29 | AsmString = "csdb$\xFF\x02\x01"; |
9330 | 29 | break; |
9331 | 29 | } |
9332 | 121 | return false; |
9333 | 1.49k | case ARM_t2DSB: |
9334 | 1.49k | if (MCInst_getNumOperands(MI) == 3 && |
9335 | 1.49k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9336 | 1.49k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && |
9337 | 1.49k | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { |
9338 | | // (t2DSB 12, pred:$p) |
9339 | 327 | AsmString = "dfb$\xFF\x02\x01"; |
9340 | 327 | break; |
9341 | 327 | } |
9342 | 1.16k | return false; |
9343 | 2.57k | case ARM_t2HINT: |
9344 | 2.57k | if (MCInst_getNumOperands(MI) == 3 && |
9345 | 2.57k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9346 | 2.57k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && |
9347 | 2.57k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9348 | 2.57k | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9349 | | // (t2HINT 0, pred:$p) |
9350 | 25 | AsmString = "nop$\xFF\x02\x01.w"; |
9351 | 25 | break; |
9352 | 25 | } |
9353 | 2.54k | if (MCInst_getNumOperands(MI) == 3 && |
9354 | 2.54k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9355 | 2.54k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && |
9356 | 2.54k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9357 | 2.54k | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9358 | | // (t2HINT 1, pred:$p) |
9359 | 1.31k | AsmString = "yield$\xFF\x02\x01.w"; |
9360 | 1.31k | break; |
9361 | 1.31k | } |
9362 | 1.23k | if (MCInst_getNumOperands(MI) == 3 && |
9363 | 1.23k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9364 | 1.23k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && |
9365 | 1.23k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9366 | 1.23k | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9367 | | // (t2HINT 2, pred:$p) |
9368 | 269 | AsmString = "wfe$\xFF\x02\x01.w"; |
9369 | 269 | break; |
9370 | 269 | } |
9371 | 961 | if (MCInst_getNumOperands(MI) == 3 && |
9372 | 961 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9373 | 961 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && |
9374 | 961 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9375 | 961 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9376 | | // (t2HINT 3, pred:$p) |
9377 | 111 | AsmString = "wfi$\xFF\x02\x01.w"; |
9378 | 111 | break; |
9379 | 111 | } |
9380 | 850 | if (MCInst_getNumOperands(MI) == 3 && |
9381 | 850 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9382 | 850 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && |
9383 | 850 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9384 | 850 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9385 | | // (t2HINT 4, pred:$p) |
9386 | 121 | AsmString = "sev$\xFF\x02\x01.w"; |
9387 | 121 | break; |
9388 | 121 | } |
9389 | 729 | if (MCInst_getNumOperands(MI) == 3 && |
9390 | 729 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9391 | 729 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && |
9392 | 729 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9393 | 729 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && |
9394 | 729 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { |
9395 | | // (t2HINT 5, pred:$p) |
9396 | 190 | AsmString = "sevl$\xFF\x02\x01.w"; |
9397 | 190 | break; |
9398 | 190 | } |
9399 | 539 | if (MCInst_getNumOperands(MI) == 3 && |
9400 | 539 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9401 | 539 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && |
9402 | 539 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9403 | 539 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && |
9404 | 539 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { |
9405 | | // (t2HINT 16, pred:$p) |
9406 | 75 | AsmString = "esb$\xFF\x02\x01.w"; |
9407 | 75 | break; |
9408 | 75 | } |
9409 | 464 | if (MCInst_getNumOperands(MI) == 3 && |
9410 | 464 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9411 | 464 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && |
9412 | 464 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9413 | 464 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { |
9414 | | // (t2HINT 20, pred:$p) |
9415 | 140 | AsmString = "csdb$\xFF\x02\x01"; |
9416 | 140 | break; |
9417 | 140 | } |
9418 | 324 | return false; |
9419 | 131 | case ARM_t2SUBS_PC_LR: |
9420 | 131 | if (MCInst_getNumOperands(MI) == 3 && |
9421 | 131 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9422 | 131 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && |
9423 | 131 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9424 | 131 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && |
9425 | 131 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)) { |
9426 | | // (t2SUBS_PC_LR 0, pred:$p) |
9427 | 44 | AsmString = "eret$\xFF\x02\x01"; |
9428 | 44 | break; |
9429 | 44 | } |
9430 | 87 | return false; |
9431 | 3.77k | case ARM_tHINT: |
9432 | 3.77k | if (MCInst_getNumOperands(MI) == 3 && |
9433 | 3.77k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9434 | 3.77k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && |
9435 | 3.77k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9436 | 3.77k | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { |
9437 | | // (tHINT 0, pred:$p) |
9438 | 1.09k | AsmString = "nop$\xFF\x02\x01"; |
9439 | 1.09k | break; |
9440 | 1.09k | } |
9441 | 2.68k | if (MCInst_getNumOperands(MI) == 3 && |
9442 | 2.68k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9443 | 2.68k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && |
9444 | 2.68k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9445 | 2.68k | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { |
9446 | | // (tHINT 1, pred:$p) |
9447 | 357 | AsmString = "yield$\xFF\x02\x01"; |
9448 | 357 | break; |
9449 | 357 | } |
9450 | 2.32k | if (MCInst_getNumOperands(MI) == 3 && |
9451 | 2.32k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9452 | 2.32k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && |
9453 | 2.32k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9454 | 2.32k | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { |
9455 | | // (tHINT 2, pred:$p) |
9456 | 650 | AsmString = "wfe$\xFF\x02\x01"; |
9457 | 650 | break; |
9458 | 650 | } |
9459 | 1.67k | if (MCInst_getNumOperands(MI) == 3 && |
9460 | 1.67k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9461 | 1.67k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && |
9462 | 1.67k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9463 | 1.67k | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { |
9464 | | // (tHINT 3, pred:$p) |
9465 | 512 | AsmString = "wfi$\xFF\x02\x01"; |
9466 | 512 | break; |
9467 | 512 | } |
9468 | 1.16k | if (MCInst_getNumOperands(MI) == 3 && |
9469 | 1.16k | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9470 | 1.16k | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && |
9471 | 1.16k | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9472 | 1.16k | ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { |
9473 | | // (tHINT 4, pred:$p) |
9474 | 224 | AsmString = "sev$\xFF\x02\x01"; |
9475 | 224 | break; |
9476 | 224 | } |
9477 | 940 | if (MCInst_getNumOperands(MI) == 3 && |
9478 | 940 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
9479 | 940 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && |
9480 | 940 | ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && |
9481 | 940 | ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && |
9482 | 940 | ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { |
9483 | | // (tHINT 5, pred:$p) |
9484 | 85 | AsmString = "sevl$\xFF\x02\x01"; |
9485 | 85 | break; |
9486 | 85 | } |
9487 | 855 | return false; |
9488 | 1.36M | } |
9489 | | |
9490 | | |
9491 | 6.24k | tmpString = cs_strdup(AsmString); |
9492 | | |
9493 | 29.3k | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
9494 | 29.3k | AsmString[I] != '$' && AsmString[I] != '\0') |
9495 | 23.1k | ++I; |
9496 | | |
9497 | 6.24k | tmpString[I] = 0; |
9498 | 6.24k | SStream_concat0(OS, tmpString); |
9499 | 6.24k | cs_mem_free(tmpString); |
9500 | | |
9501 | 6.24k | if (AsmString[I] != '\0') { |
9502 | 6.23k | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
9503 | 0 | SStream_concat0(OS, " "); |
9504 | 0 | ++I; |
9505 | 0 | } |
9506 | | |
9507 | 10.4k | do { |
9508 | 10.4k | if (AsmString[I] == '$') { |
9509 | 6.23k | ++I; |
9510 | 6.23k | if (AsmString[I] == (char)0xff) { |
9511 | 6.23k | ++I; |
9512 | 6.23k | OpIdx = AsmString[I++] - 1; |
9513 | 6.23k | PrintMethodIdx = AsmString[I++] - 1; |
9514 | 6.23k | printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); |
9515 | 6.23k | } else |
9516 | 0 | printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); |
9517 | 6.23k | } else { |
9518 | 4.21k | if (AsmString[I] == '[') { |
9519 | 0 | set_mem_access(MI, true); |
9520 | 4.21k | } else if (AsmString[I] == ']') { |
9521 | 0 | set_mem_access(MI, false); |
9522 | 0 | } |
9523 | 4.21k | SStream_concat1(OS, AsmString[I++]); |
9524 | 4.21k | } |
9525 | 10.4k | } while (AsmString[I] != '\0'); |
9526 | 6.23k | } |
9527 | | |
9528 | 6.24k | return true; |
9529 | 1.36M | } |
9530 | | |
9531 | | static void printCustomAliasOperand( |
9532 | | MCInst *MI, unsigned OpIdx, |
9533 | | unsigned PrintMethodIdx, |
9534 | | SStream *OS) |
9535 | 6.23k | { |
9536 | 6.23k | switch (PrintMethodIdx) { |
9537 | 0 | default: |
9538 | 0 | break; |
9539 | 6.23k | case 0: |
9540 | 6.23k | printPredicateOperand(MI, OpIdx, OS); |
9541 | 6.23k | break; |
9542 | 6.23k | } |
9543 | 6.23k | } |
9544 | | |
9545 | | #endif // PRINT_ALIAS_INSTR |