Coverage Report

Created: 2024-09-08 06:22

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
94.8k
{
20
94.8k
  static const uint32_t OpInfo[] = {
21
94.8k
    0U, // PHI
22
94.8k
    0U, // INLINEASM
23
94.8k
    0U, // CFI_INSTRUCTION
24
94.8k
    0U, // EH_LABEL
25
94.8k
    0U, // GC_LABEL
26
94.8k
    0U, // KILL
27
94.8k
    0U, // EXTRACT_SUBREG
28
94.8k
    0U, // INSERT_SUBREG
29
94.8k
    0U, // IMPLICIT_DEF
30
94.8k
    0U, // SUBREG_TO_REG
31
94.8k
    0U, // COPY_TO_REGCLASS
32
94.8k
    2452U,  // DBG_VALUE
33
94.8k
    0U, // REG_SEQUENCE
34
94.8k
    0U, // COPY
35
94.8k
    2445U,  // BUNDLE
36
94.8k
    2462U,  // LIFETIME_START
37
94.8k
    2432U,  // LIFETIME_END
38
94.8k
    0U, // STACKMAP
39
94.8k
    0U, // PATCHPOINT
40
94.8k
    0U, // LOAD_STACK_GUARD
41
94.8k
    0U, // STATEPOINT
42
94.8k
    0U, // FRAME_ALLOC
43
94.8k
    4688U,  // ADDCCri
44
94.8k
    4688U,  // ADDCCrr
45
94.8k
    5925U,  // ADDCri
46
94.8k
    5925U,  // ADDCrr
47
94.8k
    4772U,  // ADDEri
48
94.8k
    4772U,  // ADDErr
49
94.8k
    4786U,  // ADDXC
50
94.8k
    4678U,  // ADDXCCC
51
94.8k
    4808U,  // ADDXri
52
94.8k
    4808U,  // ADDXrr
53
94.8k
    4808U,  // ADDri
54
94.8k
    4808U,  // ADDrr
55
94.8k
    74166U, // ADJCALLSTACKDOWN
56
94.8k
    74185U, // ADJCALLSTACKUP
57
94.8k
    5497U,  // ALIGNADDR
58
94.8k
    5127U,  // ALIGNADDRL
59
94.8k
    4695U,  // ANDCCri
60
94.8k
    4695U,  // ANDCCrr
61
94.8k
    4718U,  // ANDNCCri
62
94.8k
    4718U,  // ANDNCCrr
63
94.8k
    5182U,  // ANDNri
64
94.8k
    5182U,  // ANDNrr
65
94.8k
    5182U,  // ANDXNrr
66
94.8k
    4876U,  // ANDXri
67
94.8k
    4876U,  // ANDXrr
68
94.8k
    4876U,  // ANDri
69
94.8k
    4876U,  // ANDrr
70
94.8k
    4502U,  // ARRAY16
71
94.8k
    4255U,  // ARRAY32
72
94.8k
    4526U,  // ARRAY8
73
94.8k
    0U, // ATOMIC_LOAD_ADD_32
74
94.8k
    0U, // ATOMIC_LOAD_ADD_64
75
94.8k
    0U, // ATOMIC_LOAD_AND_32
76
94.8k
    0U, // ATOMIC_LOAD_AND_64
77
94.8k
    0U, // ATOMIC_LOAD_MAX_32
78
94.8k
    0U, // ATOMIC_LOAD_MAX_64
79
94.8k
    0U, // ATOMIC_LOAD_MIN_32
80
94.8k
    0U, // ATOMIC_LOAD_MIN_64
81
94.8k
    0U, // ATOMIC_LOAD_NAND_32
82
94.8k
    0U, // ATOMIC_LOAD_NAND_64
83
94.8k
    0U, // ATOMIC_LOAD_OR_32
84
94.8k
    0U, // ATOMIC_LOAD_OR_64
85
94.8k
    0U, // ATOMIC_LOAD_SUB_32
86
94.8k
    0U, // ATOMIC_LOAD_SUB_64
87
94.8k
    0U, // ATOMIC_LOAD_UMAX_32
88
94.8k
    0U, // ATOMIC_LOAD_UMAX_64
89
94.8k
    0U, // ATOMIC_LOAD_UMIN_32
90
94.8k
    0U, // ATOMIC_LOAD_UMIN_64
91
94.8k
    0U, // ATOMIC_LOAD_XOR_32
92
94.8k
    0U, // ATOMIC_LOAD_XOR_64
93
94.8k
    0U, // ATOMIC_SWAP_64
94
94.8k
    74271U, // BA
95
94.8k
    1194492U, // BCOND
96
94.8k
    1260028U, // BCONDA
97
94.8k
    17659U, // BINDri
98
94.8k
    17659U, // BINDrr
99
94.8k
    5065U,  // BMASK
100
94.8k
    145915U,  // BPFCC
101
94.8k
    211451U,  // BPFCCA
102
94.8k
    276987U,  // BPFCCANT
103
94.8k
    342523U,  // BPFCCNT
104
94.8k
    2106465U, // BPGEZapn
105
94.8k
    2105838U, // BPGEZapt
106
94.8k
    2106532U, // BPGEZnapn
107
94.8k
    2107288U, // BPGEZnapt
108
94.8k
    2106489U, // BPGZapn
109
94.8k
    2105856U, // BPGZapt
110
94.8k
    2106552U, // BPGZnapn
111
94.8k
    2107384U, // BPGZnapt
112
94.8k
    1456636U, // BPICC
113
94.8k
    473596U,  // BPICCA
114
94.8k
    539132U,  // BPICCANT
115
94.8k
    604668U,  // BPICCNT
116
94.8k
    2106477U, // BPLEZapn
117
94.8k
    2105847U, // BPLEZapt
118
94.8k
    2106542U, // BPLEZnapn
119
94.8k
    2107337U, // BPLEZnapt
120
94.8k
    2106500U, // BPLZapn
121
94.8k
    2105864U, // BPLZapt
122
94.8k
    2106561U, // BPLZnapn
123
94.8k
    2107428U, // BPLZnapt
124
94.8k
    2106511U, // BPNZapn
125
94.8k
    2105872U, // BPNZapt
126
94.8k
    2106570U, // BPNZnapn
127
94.8k
    2107472U, // BPNZnapt
128
94.8k
    1718780U, // BPXCC
129
94.8k
    735740U,  // BPXCCA
130
94.8k
    801276U,  // BPXCCANT
131
94.8k
    866812U,  // BPXCCNT
132
94.8k
    2106522U, // BPZapn
133
94.8k
    2105880U, // BPZapt
134
94.8k
    2106579U, // BPZnapn
135
94.8k
    2107505U, // BPZnapt
136
94.8k
    4983U,  // BSHUFFLE
137
94.8k
    74742U, // CALL
138
94.8k
    17398U, // CALLri
139
94.8k
    17398U, // CALLrr
140
94.8k
    924148U,  // CASXrr
141
94.8k
    924129U,  // CASrr
142
94.8k
    74001U, // CMASK16
143
94.8k
    73833U, // CMASK32
144
94.8k
    74150U, // CMASK8
145
94.8k
    2106607U, // CMPri
146
94.8k
    2106607U, // CMPrr
147
94.8k
    4332U,  // EDGE16
148
94.8k
    5081U,  // EDGE16L
149
94.8k
    5198U,  // EDGE16LN
150
94.8k
    5165U,  // EDGE16N
151
94.8k
    4164U,  // EDGE32
152
94.8k
    5072U,  // EDGE32L
153
94.8k
    5188U,  // EDGE32LN
154
94.8k
    5156U,  // EDGE32N
155
94.8k
    4511U,  // EDGE8
156
94.8k
    5090U,  // EDGE8L
157
94.8k
    5208U,  // EDGE8LN
158
94.8k
    5174U,  // EDGE8N
159
94.8k
    1053516U, // FABSD
160
94.8k
    1054031U, // FABSQ
161
94.8k
    1054376U, // FABSS
162
94.8k
    4813U,  // FADDD
163
94.8k
    5383U,  // FADDQ
164
94.8k
    5645U,  // FADDS
165
94.8k
    4648U,  // FALIGNADATA
166
94.8k
    4875U,  // FAND
167
94.8k
    4112U,  // FANDNOT1
168
94.8k
    5544U,  // FANDNOT1S
169
94.8k
    4271U,  // FANDNOT2
170
94.8k
    5591U,  // FANDNOT2S
171
94.8k
    5677U,  // FANDS
172
94.8k
    1194491U, // FBCOND
173
94.8k
    1260027U, // FBCONDA
174
94.8k
    4394U,  // FCHKSM16
175
94.8k
    2106173U, // FCMPD
176
94.8k
    4413U,  // FCMPEQ16
177
94.8k
    4226U,  // FCMPEQ32
178
94.8k
    4432U,  // FCMPGT16
179
94.8k
    4245U,  // FCMPGT32
180
94.8k
    4340U,  // FCMPLE16
181
94.8k
    4172U,  // FCMPLE32
182
94.8k
    4350U,  // FCMPNE16
183
94.8k
    4182U,  // FCMPNE32
184
94.8k
    2106696U, // FCMPQ
185
94.8k
    2107005U, // FCMPS
186
94.8k
    4960U,  // FDIVD
187
94.8k
    5475U,  // FDIVQ
188
94.8k
    5815U,  // FDIVS
189
94.8k
    5405U,  // FDMULQ
190
94.8k
    1053620U, // FDTOI
191
94.8k
    1053996U, // FDTOQ
192
94.8k
    1054305U, // FDTOS
193
94.8k
    1054536U, // FDTOX
194
94.8k
    1053464U, // FEXPAND
195
94.8k
    4820U,  // FHADDD
196
94.8k
    5652U,  // FHADDS
197
94.8k
    4800U,  // FHSUBD
198
94.8k
    5637U,  // FHSUBS
199
94.8k
    1053473U, // FITOD
200
94.8k
    1054003U, // FITOQ
201
94.8k
    1054312U, // FITOS
202
94.8k
    6300484U, // FLCMPD
203
94.8k
    6301316U, // FLCMPS
204
94.8k
    2606U,  // FLUSHW
205
94.8k
    4404U,  // FMEAN16
206
94.8k
    1053543U, // FMOVD
207
94.8k
    1006078U, // FMOVD_FCC
208
94.8k
    23484926U,  // FMOVD_ICC
209
94.8k
    23747070U,  // FMOVD_XCC
210
94.8k
    1054058U, // FMOVQ
211
94.8k
    1006102U, // FMOVQ_FCC
212
94.8k
    23484950U,  // FMOVQ_ICC
213
94.8k
    23747094U,  // FMOVQ_XCC
214
94.8k
    6018U,  // FMOVRGEZD
215
94.8k
    6029U,  // FMOVRGEZQ
216
94.8k
    6056U,  // FMOVRGEZS
217
94.8k
    6116U,  // FMOVRGZD
218
94.8k
    6126U,  // FMOVRGZQ
219
94.8k
    6150U,  // FMOVRGZS
220
94.8k
    6067U,  // FMOVRLEZD
221
94.8k
    6078U,  // FMOVRLEZQ
222
94.8k
    6105U,  // FMOVRLEZS
223
94.8k
    6160U,  // FMOVRLZD
224
94.8k
    6170U,  // FMOVRLZQ
225
94.8k
    6194U,  // FMOVRLZS
226
94.8k
    6204U,  // FMOVRNZD
227
94.8k
    6214U,  // FMOVRNZQ
228
94.8k
    6238U,  // FMOVRNZS
229
94.8k
    6009U,  // FMOVRZD
230
94.8k
    6248U,  // FMOVRZQ
231
94.8k
    6269U,  // FMOVRZS
232
94.8k
    1054398U, // FMOVS
233
94.8k
    1006114U, // FMOVS_FCC
234
94.8k
    23484962U,  // FMOVS_ICC
235
94.8k
    23747106U,  // FMOVS_XCC
236
94.8k
    4490U,  // FMUL8SUX16
237
94.8k
    4465U,  // FMUL8ULX16
238
94.8k
    4442U,  // FMUL8X16
239
94.8k
    5098U,  // FMUL8X16AL
240
94.8k
    5849U,  // FMUL8X16AU
241
94.8k
    4860U,  // FMULD
242
94.8k
    4477U,  // FMULD8SUX16
243
94.8k
    4452U,  // FMULD8ULX16
244
94.8k
    5413U,  // FMULQ
245
94.8k
    5714U,  // FMULS
246
94.8k
    4837U,  // FNADDD
247
94.8k
    5669U,  // FNADDS
248
94.8k
    4881U,  // FNAND
249
94.8k
    5684U,  // FNANDS
250
94.8k
    1053429U, // FNEGD
251
94.8k
    1053974U, // FNEGQ
252
94.8k
    1054283U, // FNEGS
253
94.8k
    4828U,  // FNHADDD
254
94.8k
    5660U,  // FNHADDS
255
94.8k
    4828U,  // FNMULD
256
94.8k
    5660U,  // FNMULS
257
94.8k
    5513U,  // FNOR
258
94.8k
    5778U,  // FNORS
259
94.8k
    1052698U, // FNOT1
260
94.8k
    1054131U, // FNOT1S
261
94.8k
    1052857U, // FNOT2
262
94.8k
    1054178U, // FNOT2S
263
94.8k
    5660U,  // FNSMULD
264
94.8k
    74625U, // FONE
265
94.8k
    75324U, // FONES
266
94.8k
    5508U,  // FOR
267
94.8k
    4129U,  // FORNOT1
268
94.8k
    5563U,  // FORNOT1S
269
94.8k
    4288U,  // FORNOT2
270
94.8k
    5610U,  // FORNOT2S
271
94.8k
    5772U,  // FORS
272
94.8k
    1052936U, // FPACK16
273
94.8k
    4192U,  // FPACK32
274
94.8k
    1054507U, // FPACKFIX
275
94.8k
    4323U,  // FPADD16
276
94.8k
    5620U,  // FPADD16S
277
94.8k
    4155U,  // FPADD32
278
94.8k
    5573U,  // FPADD32S
279
94.8k
    4297U,  // FPADD64
280
94.8k
    4974U,  // FPMERGE
281
94.8k
    4314U,  // FPSUB16
282
94.8k
    4580U,  // FPSUB16S
283
94.8k
    4146U,  // FPSUB32
284
94.8k
    4570U,  // FPSUB32S
285
94.8k
    1053480U, // FQTOD
286
94.8k
    1053627U, // FQTOI
287
94.8k
    1054319U, // FQTOS
288
94.8k
    1054552U, // FQTOX
289
94.8k
    4423U,  // FSLAS16
290
94.8k
    4236U,  // FSLAS32
291
94.8k
    4378U,  // FSLL16
292
94.8k
    4210U,  // FSLL32
293
94.8k
    4867U,  // FSMULD
294
94.8k
    1053523U, // FSQRTD
295
94.8k
    1054038U, // FSQRTQ
296
94.8k
    1054383U, // FSQRTS
297
94.8k
    4306U,  // FSRA16
298
94.8k
    4138U,  // FSRA32
299
94.8k
    1052681U, // FSRC1
300
94.8k
    1054112U, // FSRC1S
301
94.8k
    1052840U, // FSRC2
302
94.8k
    1054159U, // FSRC2S
303
94.8k
    4386U,  // FSRL16
304
94.8k
    4218U,  // FSRL32
305
94.8k
    1053487U, // FSTOD
306
94.8k
    1053634U, // FSTOI
307
94.8k
    1054010U, // FSTOQ
308
94.8k
    1054559U, // FSTOX
309
94.8k
    4793U,  // FSUBD
310
94.8k
    5376U,  // FSUBQ
311
94.8k
    5630U,  // FSUBS
312
94.8k
    5519U,  // FXNOR
313
94.8k
    5785U,  // FXNORS
314
94.8k
    5526U,  // FXOR
315
94.8k
    5793U,  // FXORS
316
94.8k
    1053494U, // FXTOD
317
94.8k
    1054017U, // FXTOQ
318
94.8k
    1054326U, // FXTOS
319
94.8k
    74984U, // FZERO
320
94.8k
    75353U, // FZEROS
321
94.8k
    24584U, // GETPCX
322
94.8k
    1078273U, // JMPLri
323
94.8k
    1078273U, // JMPLrr
324
94.8k
    1997243U, // LDDFri
325
94.8k
    1997243U, // LDDFrr
326
94.8k
    1997249U, // LDFri
327
94.8k
    1997249U, // LDFrr
328
94.8k
    1997275U, // LDQFri
329
94.8k
    1997275U, // LDQFrr
330
94.8k
    1997229U, // LDSBri
331
94.8k
    1997229U, // LDSBrr
332
94.8k
    1997254U, // LDSHri
333
94.8k
    1997254U, // LDSHrr
334
94.8k
    1997287U, // LDSWri
335
94.8k
    1997287U, // LDSWrr
336
94.8k
    1997236U, // LDUBri
337
94.8k
    1997236U, // LDUBrr
338
94.8k
    1997261U, // LDUHri
339
94.8k
    1997261U, // LDUHrr
340
94.8k
    1997294U, // LDXri
341
94.8k
    1997294U, // LDXrr
342
94.8k
    1997249U, // LDri
343
94.8k
    1997249U, // LDrr
344
94.8k
    33480U, // LEAX_ADDri
345
94.8k
    33480U, // LEA_ADDri
346
94.8k
    1054405U, // LZCNT
347
94.8k
    75121U, // MEMBARi
348
94.8k
    1054543U, // MOVDTOX
349
94.8k
    1006122U, // MOVFCCri
350
94.8k
    1006122U, // MOVFCCrr
351
94.8k
    23484970U,  // MOVICCri
352
94.8k
    23484970U,  // MOVICCrr
353
94.8k
    6047U,  // MOVRGEZri
354
94.8k
    6047U,  // MOVRGEZrr
355
94.8k
    6142U,  // MOVRGZri
356
94.8k
    6142U,  // MOVRGZrr
357
94.8k
    6096U,  // MOVRLEZri
358
94.8k
    6096U,  // MOVRLEZrr
359
94.8k
    6186U,  // MOVRLZri
360
94.8k
    6186U,  // MOVRLZrr
361
94.8k
    6230U,  // MOVRNZri
362
94.8k
    6230U,  // MOVRNZrr
363
94.8k
    6262U,  // MOVRRZri
364
94.8k
    6262U,  // MOVRRZrr
365
94.8k
    1054469U, // MOVSTOSW
366
94.8k
    1054479U, // MOVSTOUW
367
94.8k
    1054543U, // MOVWTOS
368
94.8k
    23747114U,  // MOVXCCri
369
94.8k
    23747114U,  // MOVXCCrr
370
94.8k
    1054543U, // MOVXTOD
371
94.8k
    5954U,  // MULXri
372
94.8k
    5954U,  // MULXrr
373
94.8k
    2578U,  // NOP
374
94.8k
    4735U,  // ORCCri
375
94.8k
    4735U,  // ORCCrr
376
94.8k
    4726U,  // ORNCCri
377
94.8k
    4726U,  // ORNCCrr
378
94.8k
    5339U,  // ORNri
379
94.8k
    5339U,  // ORNrr
380
94.8k
    5339U,  // ORXNrr
381
94.8k
    5509U,  // ORXri
382
94.8k
    5509U,  // ORXrr
383
94.8k
    5509U,  // ORri
384
94.8k
    5509U,  // ORrr
385
94.8k
    5836U,  // PDIST
386
94.8k
    5344U,  // PDISTN
387
94.8k
    1053356U, // POPCrr
388
94.8k
    73729U, // RDY
389
94.8k
    4999U,  // RESTOREri
390
94.8k
    4999U,  // RESTORErr
391
94.8k
    76132U, // RET
392
94.8k
    76141U, // RETL
393
94.8k
    18131U, // RETTri
394
94.8k
    18131U, // RETTrr
395
94.8k
    5008U,  // SAVEri
396
94.8k
    5008U,  // SAVErr
397
94.8k
    4748U,  // SDIVCCri
398
94.8k
    4748U,  // SDIVCCrr
399
94.8k
    5995U,  // SDIVXri
400
94.8k
    5995U,  // SDIVXrr
401
94.8k
    5861U,  // SDIVri
402
94.8k
    5861U,  // SDIVrr
403
94.8k
    2182U,  // SELECT_CC_DFP_FCC
404
94.8k
    2293U,  // SELECT_CC_DFP_ICC
405
94.8k
    2238U,  // SELECT_CC_FP_FCC
406
94.8k
    2349U,  // SELECT_CC_FP_ICC
407
94.8k
    2265U,  // SELECT_CC_Int_FCC
408
94.8k
    2376U,  // SELECT_CC_Int_ICC
409
94.8k
    2210U,  // SELECT_CC_QFP_FCC
410
94.8k
    2321U,  // SELECT_CC_QFP_ICC
411
94.8k
    1053595U, // SETHIXi
412
94.8k
    1053595U, // SETHIi
413
94.8k
    2569U,  // SHUTDOWN
414
94.8k
    2564U,  // SIAM
415
94.8k
    5941U,  // SLLXri
416
94.8k
    5941U,  // SLLXrr
417
94.8k
    5116U,  // SLLri
418
94.8k
    5116U,  // SLLrr
419
94.8k
    4702U,  // SMULCCri
420
94.8k
    4702U,  // SMULCCrr
421
94.8k
    5144U,  // SMULri
422
94.8k
    5144U,  // SMULrr
423
94.8k
    5913U,  // SRAXri
424
94.8k
    5913U,  // SRAXrr
425
94.8k
    4643U,  // SRAri
426
94.8k
    4643U,  // SRArr
427
94.8k
    5947U,  // SRLXri
428
94.8k
    5947U,  // SRLXrr
429
94.8k
    5139U,  // SRLri
430
94.8k
    5139U,  // SRLrr
431
94.8k
    2588U,  // STBAR
432
94.8k
    37428U, // STBri
433
94.8k
    37428U, // STBrr
434
94.8k
    37723U, // STDFri
435
94.8k
    37723U, // STDFrr
436
94.8k
    38607U, // STFri
437
94.8k
    38607U, // STFrr
438
94.8k
    37782U, // STHri
439
94.8k
    37782U, // STHrr
440
94.8k
    38238U, // STQFri
441
94.8k
    38238U, // STQFrr
442
94.8k
    38758U, // STXri
443
94.8k
    38758U, // STXrr
444
94.8k
    38607U, // STri
445
94.8k
    38607U, // STrr
446
94.8k
    4671U,  // SUBCCri
447
94.8k
    4671U,  // SUBCCrr
448
94.8k
    5919U,  // SUBCri
449
94.8k
    5919U,  // SUBCrr
450
94.8k
    4764U,  // SUBEri
451
94.8k
    4764U,  // SUBErr
452
94.8k
    4665U,  // SUBXri
453
94.8k
    4665U,  // SUBXrr
454
94.8k
    4665U,  // SUBri
455
94.8k
    4665U,  // SUBrr
456
94.8k
    1997268U, // SWAPri
457
94.8k
    1997268U, // SWAPrr
458
94.8k
    2422U,  // TA3
459
94.8k
    2427U,  // TA5
460
94.8k
    5883U,  // TADDCCTVri
461
94.8k
    5883U,  // TADDCCTVrr
462
94.8k
    4687U,  // TADDCCri
463
94.8k
    4687U,  // TADDCCrr
464
94.8k
    9873960U, // TICCri
465
94.8k
    9873960U, // TICCrr
466
94.8k
    37753544U,  // TLS_ADDXrr
467
94.8k
    37753544U,  // TLS_ADDrr
468
94.8k
    2106358U, // TLS_CALL
469
94.8k
    39746030U,  // TLS_LDXrr
470
94.8k
    39745985U,  // TLS_LDrr
471
94.8k
    5873U,  // TSUBCCTVri
472
94.8k
    5873U,  // TSUBCCTVrr
473
94.8k
    4670U,  // TSUBCCri
474
94.8k
    4670U,  // TSUBCCrr
475
94.8k
    10136104U,  // TXCCri
476
94.8k
    10136104U,  // TXCCrr
477
94.8k
    4756U,  // UDIVCCri
478
94.8k
    4756U,  // UDIVCCrr
479
94.8k
    6002U,  // UDIVXri
480
94.8k
    6002U,  // UDIVXrr
481
94.8k
    5867U,  // UDIVri
482
94.8k
    5867U,  // UDIVrr
483
94.8k
    4710U,  // UMULCCri
484
94.8k
    4710U,  // UMULCCrr
485
94.8k
    5026U,  // UMULXHI
486
94.8k
    5150U,  // UMULri
487
94.8k
    5150U,  // UMULrr
488
94.8k
    74996U, // UNIMP
489
94.8k
    6300477U, // V9FCMPD
490
94.8k
    6300397U, // V9FCMPED
491
94.8k
    6300942U, // V9FCMPEQ
492
94.8k
    6301251U, // V9FCMPES
493
94.8k
    6301000U, // V9FCMPQ
494
94.8k
    6301309U, // V9FCMPS
495
94.8k
    47614U, // V9FMOVD_FCC
496
94.8k
    47638U, // V9FMOVQ_FCC
497
94.8k
    47650U, // V9FMOVS_FCC
498
94.8k
    47658U, // V9MOVFCCri
499
94.8k
    47658U, // V9MOVFCCrr
500
94.8k
    14689692U,  // WRYri
501
94.8k
    14689692U,  // WRYrr
502
94.8k
    5953U,  // XMULX
503
94.8k
    5035U,  // XMULXHI
504
94.8k
    4733U,  // XNORCCri
505
94.8k
    4733U,  // XNORCCrr
506
94.8k
    5520U,  // XNORXrr
507
94.8k
    5520U,  // XNORri
508
94.8k
    5520U,  // XNORrr
509
94.8k
    4741U,  // XORCCri
510
94.8k
    4741U,  // XORCCrr
511
94.8k
    5527U,  // XORXri
512
94.8k
    5527U,  // XORXrr
513
94.8k
    5527U,  // XORri
514
94.8k
    5527U,  // XORrr
515
94.8k
    0U
516
94.8k
  };
517
518
94.8k
#ifndef CAPSTONE_DIET
519
94.8k
  static const char AsmStrs[] = {
520
94.8k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
94.8k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
94.8k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
94.8k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
94.8k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
94.8k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
94.8k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
94.8k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
94.8k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
94.8k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
94.8k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
94.8k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
94.8k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
94.8k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
94.8k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
94.8k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
94.8k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
94.8k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
94.8k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
94.8k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
94.8k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
94.8k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
94.8k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
94.8k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
94.8k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
94.8k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
94.8k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
94.8k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
94.8k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
94.8k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
94.8k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
94.8k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
94.8k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
94.8k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
94.8k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
94.8k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
94.8k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
94.8k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
94.8k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
94.8k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
94.8k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
94.8k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
94.8k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
94.8k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
94.8k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
94.8k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
94.8k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
94.8k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
94.8k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
94.8k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
94.8k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
94.8k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
94.8k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
94.8k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
94.8k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
94.8k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
94.8k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
94.8k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
94.8k
  /* 542 */ 'b', 'a', 32, 0,
579
94.8k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
94.8k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
94.8k
  /* 563 */ 's', 't', 'b', 32, 0,
582
94.8k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
94.8k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
94.8k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
94.8k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
94.8k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
94.8k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
94.8k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
94.8k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
94.8k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
94.8k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
94.8k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
94.8k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
94.8k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
94.8k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
94.8k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
94.8k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
94.8k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
94.8k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
94.8k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
94.8k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
94.8k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
94.8k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
94.8k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
94.8k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
94.8k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
94.8k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
94.8k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
94.8k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
94.8k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
94.8k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
94.8k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
94.8k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
94.8k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
94.8k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
94.8k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
94.8k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
94.8k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
94.8k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
94.8k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
94.8k
  /* 858 */ 's', 't', 'd', 32, 0,
622
94.8k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
94.8k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
94.8k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
94.8k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
94.8k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
94.8k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
94.8k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
94.8k
  /* 917 */ 's', 't', 'h', 32, 0,
630
94.8k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
94.8k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
94.8k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
94.8k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
94.8k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
94.8k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
94.8k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
94.8k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
94.8k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
94.8k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
94.8k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
94.8k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
94.8k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
94.8k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
94.8k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
94.8k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
94.8k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
94.8k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
94.8k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
94.8k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
94.8k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
94.8k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
94.8k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
94.8k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
94.8k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
94.8k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
94.8k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
94.8k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
94.8k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
94.8k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
94.8k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
94.8k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
94.8k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
94.8k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
94.8k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
94.8k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
94.8k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
94.8k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
94.8k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
94.8k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
94.8k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
94.8k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
94.8k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
94.8k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
94.8k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
94.8k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
94.8k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
94.8k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
94.8k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
94.8k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
94.8k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
94.8k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
94.8k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
94.8k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
94.8k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
94.8k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
94.8k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
94.8k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
94.8k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
94.8k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
94.8k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
94.8k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
94.8k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
94.8k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
94.8k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
94.8k
  /* 1435 */ 'w', 'r', 32, 0,
696
94.8k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
94.8k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
94.8k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
94.8k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
94.8k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
94.8k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
94.8k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
94.8k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
94.8k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
94.8k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
94.8k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
94.8k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
94.8k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
94.8k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
94.8k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
94.8k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
94.8k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
94.8k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
94.8k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
94.8k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
94.8k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
94.8k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
94.8k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
94.8k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
94.8k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
94.8k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
94.8k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
94.8k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
94.8k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
94.8k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
94.8k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
94.8k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
94.8k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
94.8k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
94.8k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
94.8k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
94.8k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
94.8k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
94.8k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
94.8k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
94.8k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
94.8k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
94.8k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
94.8k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
94.8k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
94.8k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
94.8k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
94.8k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
94.8k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
94.8k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
94.8k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
94.8k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
94.8k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
94.8k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
94.8k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
94.8k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
94.8k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
94.8k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
94.8k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
94.8k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
94.8k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
94.8k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
94.8k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
94.8k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
94.8k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
94.8k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
94.8k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
94.8k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
94.8k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
94.8k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
94.8k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
94.8k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
94.8k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
94.8k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
94.8k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
94.8k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
94.8k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
94.8k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
94.8k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
94.8k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
94.8k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
94.8k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
94.8k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
94.8k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
94.8k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
94.8k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
94.8k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
94.8k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
94.8k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
94.8k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
94.8k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
94.8k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
94.8k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
94.8k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
94.8k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
94.8k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
94.8k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
94.8k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
94.8k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
94.8k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
94.8k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
94.8k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
94.8k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
94.8k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
94.8k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
94.8k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
94.8k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
94.8k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
94.8k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
94.8k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
94.8k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
94.8k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
94.8k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
94.8k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
94.8k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
94.8k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
94.8k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
94.8k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
94.8k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
94.8k
  /* 2554 */ 'f', 'b', 0,
816
94.8k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
94.8k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
94.8k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
94.8k
  /* 2577 */ 'n', 'o', 'p', 0,
820
94.8k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
94.8k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
94.8k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
94.8k
  /* 2599 */ 't', 0,
824
94.8k
  /* 2601 */ 'm', 'o', 'v', 0,
825
94.8k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
94.8k
  };
827
94.8k
#endif
828
829
  // Emit the opcode for the instruction.
830
94.8k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
94.8k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
94.8k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
94.8k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
94.8k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
194
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
194
    return;
844
0
    break;
845
17.1k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
17.1k
    printOperand(MI, 1, O); 
848
17.1k
    break;
849
57.9k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
57.9k
    printOperand(MI, 0, O); 
852
57.9k
    break;
853
6.28k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
6.28k
    printCCOperand(MI, 1, O); 
856
6.28k
    break;
857
1.01k
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
1.01k
    printMemOperand(MI, 0, O, NULL); 
860
1.01k
    return;
861
0
    break;
862
5.79k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
5.79k
    printCCOperand(MI, 3, O); 
865
5.79k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.98k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.98k
    printMemOperand(MI, 1, O, NULL); 
874
2.98k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.95k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.95k
    printOperand(MI, 2, O); 
885
1.95k
    SStream_concat0(O, ", ["); 
886
1.95k
    printMemOperand(MI, 0, O, NULL); 
887
1.95k
    SStream_concat0(O, "]"); 
888
1.95k
    return;
889
0
    break;
890
386
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
386
    printCCOperand(MI, 2, O); 
893
386
    break;
894
1.05k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.05k
    printCCOperand(MI, 4, O); 
897
1.05k
    SStream_concat0(O, " "); 
898
1.05k
    printOperand(MI, 1, O); 
899
1.05k
    SStream_concat0(O, ", "); 
900
1.05k
    printOperand(MI, 2, O); 
901
1.05k
    SStream_concat0(O, ", "); 
902
1.05k
    printOperand(MI, 0, O); 
903
1.05k
    return;
904
0
    break;
905
94.8k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
90.6k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
22.4k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
22.4k
    SStream_concat0(O, ", "); 
915
22.4k
    break;
916
52.8k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
52.8k
    return;
919
0
    break;
920
1.90k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.90k
    SStream_concat0(O, " "); 
923
1.90k
    break;
924
1.76k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.76k
    SStream_concat0(O, ",a ");
927
1.76k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.76k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
4.80k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
4.80k
    SStream_concat0(O, " %icc, ");
950
4.80k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
4.80k
    break;
952
457
  case 7:
953
    // BPICCA
954
457
    SStream_concat0(O, ",a %icc, ");
955
457
  Sparc_add_hint(MI, SPARC_HINT_A);
956
457
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
457
    printOperand(MI, 0, O); 
958
457
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.77k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.77k
    SStream_concat0(O, " %xcc, ");
979
1.77k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.77k
    break;
981
531
  case 11:
982
    // BPXCCA
983
531
    SStream_concat0(O, ",a %xcc, ");
984
531
  Sparc_add_hint(MI, SPARC_HINT_A);
985
531
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
531
    printOperand(MI, 0, O); 
987
531
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.90k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.90k
    SStream_concat0(O, "], "); 
1008
2.90k
    break;
1009
1.22k
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
1.22k
    SStream_concat0(O, " %fcc0, ");
1012
1.22k
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
1.22k
    printOperand(MI, 1, O); 
1014
1.22k
    SStream_concat0(O, ", "); 
1015
1.22k
    printOperand(MI, 0, O); 
1016
1.22k
    return;
1017
0
    break;
1018
90.6k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
35.6k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
9.06k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
9.06k
    printOperand(MI, 2, O); 
1028
9.06k
    SStream_concat0(O, ", "); 
1029
9.06k
    printOperand(MI, 0, O); 
1030
9.06k
    break;
1031
16.7k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
16.7k
    printOperand(MI, 0, O); 
1034
16.7k
    break;
1035
9.75k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
9.75k
    printOperand(MI, 1, O); 
1038
9.75k
    break;
1039
35.6k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
35.6k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
29.0k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
29.0k
    return;
1049
0
    break;
1050
5.56k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
5.56k
    SStream_concat0(O, ", "); 
1053
5.56k
    break;
1054
386
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
386
    SStream_concat0(O, " + ");  // qq
1057
386
    printOperand(MI, 1, O); 
1058
386
    return;
1059
0
    break;
1060
634
  case 3:
1061
    // WRYri, WRYrr
1062
634
    SStream_concat0(O, ", %y");
1063
634
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
634
    return;
1065
0
    break;
1066
35.6k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
5.56k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.00k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.00k
    printOperand(MI, 2, O); 
1076
1.00k
    return;
1077
0
    break;
1078
4.56k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
4.56k
    printOperand(MI, 0, O); 
1081
4.56k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
5.56k
  }
1089
5.56k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
86.6k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
86.6k
#ifndef CAPSTONE_DIET
1100
86.6k
  static const char AsmStrs[] = {
1101
86.6k
  /* 0 */ 'f', '1', '0', 0,
1102
86.6k
  /* 4 */ 'f', '2', '0', 0,
1103
86.6k
  /* 8 */ 'f', '3', '0', 0,
1104
86.6k
  /* 12 */ 'f', '4', '0', 0,
1105
86.6k
  /* 16 */ 'f', '5', '0', 0,
1106
86.6k
  /* 20 */ 'f', '6', '0', 0,
1107
86.6k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
86.6k
  /* 29 */ 'f', '0', 0,
1109
86.6k
  /* 32 */ 'g', '0', 0,
1110
86.6k
  /* 35 */ 'i', '0', 0,
1111
86.6k
  /* 38 */ 'l', '0', 0,
1112
86.6k
  /* 41 */ 'o', '0', 0,
1113
86.6k
  /* 44 */ 'f', '1', '1', 0,
1114
86.6k
  /* 48 */ 'f', '2', '1', 0,
1115
86.6k
  /* 52 */ 'f', '3', '1', 0,
1116
86.6k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
86.6k
  /* 61 */ 'f', '1', 0,
1118
86.6k
  /* 64 */ 'g', '1', 0,
1119
86.6k
  /* 67 */ 'i', '1', 0,
1120
86.6k
  /* 70 */ 'l', '1', 0,
1121
86.6k
  /* 73 */ 'o', '1', 0,
1122
86.6k
  /* 76 */ 'f', '1', '2', 0,
1123
86.6k
  /* 80 */ 'f', '2', '2', 0,
1124
86.6k
  /* 84 */ 'f', '3', '2', 0,
1125
86.6k
  /* 88 */ 'f', '4', '2', 0,
1126
86.6k
  /* 92 */ 'f', '5', '2', 0,
1127
86.6k
  /* 96 */ 'f', '6', '2', 0,
1128
86.6k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
86.6k
  /* 105 */ 'f', '2', 0,
1130
86.6k
  /* 108 */ 'g', '2', 0,
1131
86.6k
  /* 111 */ 'i', '2', 0,
1132
86.6k
  /* 114 */ 'l', '2', 0,
1133
86.6k
  /* 117 */ 'o', '2', 0,
1134
86.6k
  /* 120 */ 'f', '1', '3', 0,
1135
86.6k
  /* 124 */ 'f', '2', '3', 0,
1136
86.6k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
86.6k
  /* 133 */ 'f', '3', 0,
1138
86.6k
  /* 136 */ 'g', '3', 0,
1139
86.6k
  /* 139 */ 'i', '3', 0,
1140
86.6k
  /* 142 */ 'l', '3', 0,
1141
86.6k
  /* 145 */ 'o', '3', 0,
1142
86.6k
  /* 148 */ 'f', '1', '4', 0,
1143
86.6k
  /* 152 */ 'f', '2', '4', 0,
1144
86.6k
  /* 156 */ 'f', '3', '4', 0,
1145
86.6k
  /* 160 */ 'f', '4', '4', 0,
1146
86.6k
  /* 164 */ 'f', '5', '4', 0,
1147
86.6k
  /* 168 */ 'f', '4', 0,
1148
86.6k
  /* 171 */ 'g', '4', 0,
1149
86.6k
  /* 174 */ 'i', '4', 0,
1150
86.6k
  /* 177 */ 'l', '4', 0,
1151
86.6k
  /* 180 */ 'o', '4', 0,
1152
86.6k
  /* 183 */ 'f', '1', '5', 0,
1153
86.6k
  /* 187 */ 'f', '2', '5', 0,
1154
86.6k
  /* 191 */ 'f', '5', 0,
1155
86.6k
  /* 194 */ 'g', '5', 0,
1156
86.6k
  /* 197 */ 'i', '5', 0,
1157
86.6k
  /* 200 */ 'l', '5', 0,
1158
86.6k
  /* 203 */ 'o', '5', 0,
1159
86.6k
  /* 206 */ 'f', '1', '6', 0,
1160
86.6k
  /* 210 */ 'f', '2', '6', 0,
1161
86.6k
  /* 214 */ 'f', '3', '6', 0,
1162
86.6k
  /* 218 */ 'f', '4', '6', 0,
1163
86.6k
  /* 222 */ 'f', '5', '6', 0,
1164
86.6k
  /* 226 */ 'f', '6', 0,
1165
86.6k
  /* 229 */ 'g', '6', 0,
1166
86.6k
  /* 232 */ 'l', '6', 0,
1167
86.6k
  /* 235 */ 'f', '1', '7', 0,
1168
86.6k
  /* 239 */ 'f', '2', '7', 0,
1169
86.6k
  /* 243 */ 'f', '7', 0,
1170
86.6k
  /* 246 */ 'g', '7', 0,
1171
86.6k
  /* 249 */ 'i', '7', 0,
1172
86.6k
  /* 252 */ 'l', '7', 0,
1173
86.6k
  /* 255 */ 'o', '7', 0,
1174
86.6k
  /* 258 */ 'f', '1', '8', 0,
1175
86.6k
  /* 262 */ 'f', '2', '8', 0,
1176
86.6k
  /* 266 */ 'f', '3', '8', 0,
1177
86.6k
  /* 270 */ 'f', '4', '8', 0,
1178
86.6k
  /* 274 */ 'f', '5', '8', 0,
1179
86.6k
  /* 278 */ 'f', '8', 0,
1180
86.6k
  /* 281 */ 'f', '1', '9', 0,
1181
86.6k
  /* 285 */ 'f', '2', '9', 0,
1182
86.6k
  /* 289 */ 'f', '9', 0,
1183
86.6k
  /* 292 */ 'i', 'c', 'c', 0,
1184
86.6k
  /* 296 */ 'f', 'p', 0,
1185
86.6k
  /* 299 */ 's', 'p', 0,
1186
86.6k
  /* 302 */ 'y', 0,
1187
86.6k
  };
1188
1189
86.6k
  static const uint16_t RegAsmOffset[] = {
1190
86.6k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
86.6k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
86.6k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
86.6k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
86.6k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
86.6k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
86.6k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
86.6k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
86.6k
    12, 160, 270, 92, 222, 20, 
1199
86.6k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
86.6k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
86.6k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
137k
{
1221
497k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
137k
  const char *AsmString;
1223
137k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
137k
  int OpIdx, PrintMethodIdx;
1225
137k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
137k
  switch (MCInst_getOpcode(MI)) {
1227
88.3k
  default: return NULL;
1228
5.69k
  case SP_BCOND:
1229
5.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
5.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
5.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
5.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
5.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
5.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
1.18k
      AsmString = "bn $\x01";
1241
1.18k
      break;
1242
1.18k
    }
1243
4.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
4.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
4.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
47
      AsmString = "bne $\x01";
1248
47
      break;
1249
47
    }
1250
4.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
4.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
4.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
311
      AsmString = "be $\x01";
1255
311
      break;
1256
311
    }
1257
4.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
4.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
4.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
123
      AsmString = "bg $\x01";
1262
123
      break;
1263
123
    }
1264
4.02k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
4.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
4.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
125
      AsmString = "ble $\x01";
1269
125
      break;
1270
125
    }
1271
3.90k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
3.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
3.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
139
      AsmString = "bge $\x01";
1276
139
      break;
1277
139
    }
1278
3.76k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
3.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
3.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
89
      AsmString = "bl $\x01";
1283
89
      break;
1284
89
    }
1285
3.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
3.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
3.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
221
      AsmString = "bgu $\x01";
1290
221
      break;
1291
221
    }
1292
3.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
3.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
3.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
195
      AsmString = "bleu $\x01";
1297
195
      break;
1298
195
    }
1299
3.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
3.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
3.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
107
      AsmString = "bcc $\x01";
1304
107
      break;
1305
107
    }
1306
3.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
3.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
3.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
1.27k
      AsmString = "bcs $\x01";
1311
1.27k
      break;
1312
1.27k
    }
1313
1.87k
    if (MCInst_getNumOperands(MI) == 2 &&
1314
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
375
      AsmString = "bpos $\x01";
1318
375
      break;
1319
375
    }
1320
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1321
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
732
      AsmString = "bneg $\x01";
1325
732
      break;
1326
732
    }
1327
769
    if (MCInst_getNumOperands(MI) == 2 &&
1328
769
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
769
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
348
      AsmString = "bvc $\x01";
1332
348
      break;
1333
348
    }
1334
421
    if (MCInst_getNumOperands(MI) == 2 &&
1335
421
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
421
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
421
      AsmString = "bvs $\x01";
1339
421
      break;
1340
421
    }
1341
0
    return NULL;
1342
3.12k
  case SP_BCONDA:
1343
3.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
3.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
3.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
120
      AsmString = "ba,a $\x01";
1348
120
      break;
1349
120
    }
1350
3.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
3.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
3.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
125
      AsmString = "bn,a $\x01";
1355
125
      break;
1356
125
    }
1357
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
163
      AsmString = "bne,a $\x01";
1362
163
      break;
1363
163
    }
1364
2.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
44
      AsmString = "be,a $\x01";
1369
44
      break;
1370
44
    }
1371
2.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
38
      AsmString = "bg,a $\x01";
1376
38
      break;
1377
38
    }
1378
2.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
2.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
2.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
202
      AsmString = "ble,a $\x01";
1383
202
      break;
1384
202
    }
1385
2.43k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
2.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
2.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
111
      AsmString = "bge,a $\x01";
1390
111
      break;
1391
111
    }
1392
2.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
2.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
2.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
75
      AsmString = "bl,a $\x01";
1397
75
      break;
1398
75
    }
1399
2.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
2.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
2.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
134
      AsmString = "bgu,a $\x01";
1404
134
      break;
1405
134
    }
1406
2.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
2.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
2.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
214
      AsmString = "bleu,a $\x01";
1411
214
      break;
1412
214
    }
1413
1.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1414
1.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
1.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
269
      AsmString = "bcc,a $\x01";
1418
269
      break;
1419
269
    }
1420
1.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1421
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
310
      AsmString = "bcs,a $\x01";
1425
310
      break;
1426
310
    }
1427
1.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1428
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
302
      AsmString = "bpos,a $\x01";
1432
302
      break;
1433
302
    }
1434
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1435
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
229
      AsmString = "bneg,a $\x01";
1439
229
      break;
1440
229
    }
1441
789
    if (MCInst_getNumOperands(MI) == 2 &&
1442
789
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
789
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
358
      AsmString = "bvc,a $\x01";
1446
358
      break;
1447
358
    }
1448
431
    if (MCInst_getNumOperands(MI) == 2 &&
1449
431
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
431
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
431
      AsmString = "bvs,a $\x01";
1453
431
      break;
1454
431
    }
1455
0
    return NULL;
1456
5.25k
  case SP_BPFCCANT:
1457
5.25k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
5.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
5.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
5.25k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
5.25k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
1.01k
      AsmString = "fba,a,pn $\x03, $\x01";
1464
1.01k
      break;
1465
1.01k
    }
1466
4.23k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
4.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
4.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
4.23k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
4.23k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
449
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
449
      break;
1474
449
    }
1475
3.78k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.78k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.78k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
289
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
289
      break;
1483
289
    }
1484
3.49k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
3.49k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
3.49k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
165
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
165
      break;
1492
165
    }
1493
3.32k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
3.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
3.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
3.32k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
3.32k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
245
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
245
      break;
1501
245
    }
1502
3.08k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
3.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
3.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
3.08k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
3.08k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
132
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
132
      break;
1510
132
    }
1511
2.95k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
2.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
2.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
2.95k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
2.95k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
180
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
180
      break;
1519
180
    }
1520
2.77k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.77k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.77k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
745
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
745
      break;
1528
745
    }
1529
2.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
2.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
2.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
2.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
2.02k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
289
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
289
      break;
1537
289
    }
1538
1.73k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.73k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
110
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
110
      break;
1546
110
    }
1547
1.62k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.62k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.62k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
295
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
295
      break;
1555
295
    }
1556
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.33k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
157
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
157
      break;
1564
157
    }
1565
1.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1566
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
1.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
275
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
275
      break;
1573
275
    }
1574
900
    if (MCInst_getNumOperands(MI) == 3 &&
1575
900
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
900
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
900
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
900
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
220
      AsmString = "fble,a,pn $\x03, $\x01";
1581
220
      break;
1582
220
    }
1583
680
    if (MCInst_getNumOperands(MI) == 3 &&
1584
680
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
680
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
680
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
680
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
263
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
263
      break;
1591
263
    }
1592
417
    if (MCInst_getNumOperands(MI) == 3 &&
1593
417
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
417
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
417
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
417
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
417
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
417
      break;
1600
417
    }
1601
0
    return NULL;
1602
6.14k
  case SP_BPFCCNT:
1603
6.14k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
6.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
6.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
6.14k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
6.14k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
207
      AsmString = "fba,pn $\x03, $\x01";
1610
207
      break;
1611
207
    }
1612
5.94k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
5.94k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
5.94k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
5.94k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
5.94k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
279
      AsmString = "fbn,pn $\x03, $\x01";
1619
279
      break;
1620
279
    }
1621
5.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
5.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
5.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
5.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
5.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
147
      AsmString = "fbu,pn $\x03, $\x01";
1628
147
      break;
1629
147
    }
1630
5.51k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
5.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
5.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
5.51k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
5.51k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
536
      AsmString = "fbg,pn $\x03, $\x01";
1637
536
      break;
1638
536
    }
1639
4.98k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
4.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
4.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
4.98k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
4.98k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
125
      AsmString = "fbug,pn $\x03, $\x01";
1646
125
      break;
1647
125
    }
1648
4.85k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
4.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
4.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
4.85k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
4.85k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
91
      AsmString = "fbl,pn $\x03, $\x01";
1655
91
      break;
1656
91
    }
1657
4.76k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
4.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
4.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
4.76k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
4.76k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
335
      AsmString = "fbul,pn $\x03, $\x01";
1664
335
      break;
1665
335
    }
1666
4.42k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
4.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
4.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
4.42k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
4.42k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
305
      AsmString = "fblg,pn $\x03, $\x01";
1673
305
      break;
1674
305
    }
1675
4.12k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
4.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
4.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
4.12k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
4.12k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
156
      AsmString = "fbne,pn $\x03, $\x01";
1682
156
      break;
1683
156
    }
1684
3.96k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
3.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
3.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
3.96k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
3.96k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
443
      AsmString = "fbe,pn $\x03, $\x01";
1691
443
      break;
1692
443
    }
1693
3.52k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
3.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
3.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
3.52k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
3.52k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
1.86k
      AsmString = "fbue,pn $\x03, $\x01";
1700
1.86k
      break;
1701
1.86k
    }
1702
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
1.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
439
      AsmString = "fbge,pn $\x03, $\x01";
1709
439
      break;
1710
439
    }
1711
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1712
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
1.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
202
      AsmString = "fbuge,pn $\x03, $\x01";
1718
202
      break;
1719
202
    }
1720
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1721
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
1.02k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
118
      AsmString = "fble,pn $\x03, $\x01";
1727
118
      break;
1728
118
    }
1729
905
    if (MCInst_getNumOperands(MI) == 3 &&
1730
905
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
905
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
905
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
905
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
52
      AsmString = "fbule,pn $\x03, $\x01";
1736
52
      break;
1737
52
    }
1738
853
    if (MCInst_getNumOperands(MI) == 3 &&
1739
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
853
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
853
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
853
      AsmString = "fbo,pn $\x03, $\x01";
1745
853
      break;
1746
853
    }
1747
0
    return NULL;
1748
3.50k
  case SP_BPICCANT:
1749
3.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
140
      AsmString = "ba,a,pn %icc, $\x01";
1754
140
      break;
1755
140
    }
1756
3.36k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
3.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
3.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
127
      AsmString = "bn,a,pn %icc, $\x01";
1761
127
      break;
1762
127
    }
1763
3.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
3.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
3.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
77
      AsmString = "bne,a,pn %icc, $\x01";
1768
77
      break;
1769
77
    }
1770
3.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
3.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
3.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
76
      AsmString = "be,a,pn %icc, $\x01";
1775
76
      break;
1776
76
    }
1777
3.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
3.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
3.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
119
      AsmString = "bg,a,pn %icc, $\x01";
1782
119
      break;
1783
119
    }
1784
2.97k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
116
      AsmString = "ble,a,pn %icc, $\x01";
1789
116
      break;
1790
116
    }
1791
2.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
2.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
2.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
182
      AsmString = "bge,a,pn %icc, $\x01";
1796
182
      break;
1797
182
    }
1798
2.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
36
      AsmString = "bl,a,pn %icc, $\x01";
1803
36
      break;
1804
36
    }
1805
2.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
2.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
2.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
186
      AsmString = "bgu,a,pn %icc, $\x01";
1810
186
      break;
1811
186
    }
1812
2.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
2.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
2.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
278
      AsmString = "bleu,a,pn %icc, $\x01";
1817
278
      break;
1818
278
    }
1819
2.17k
    if (MCInst_getNumOperands(MI) == 2 &&
1820
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
396
      AsmString = "bcc,a,pn %icc, $\x01";
1824
396
      break;
1825
396
    }
1826
1.77k
    if (MCInst_getNumOperands(MI) == 2 &&
1827
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
728
      AsmString = "bcs,a,pn %icc, $\x01";
1831
728
      break;
1832
728
    }
1833
1.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1834
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
29
      AsmString = "bpos,a,pn %icc, $\x01";
1838
29
      break;
1839
29
    }
1840
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1841
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
283
      AsmString = "bneg,a,pn %icc, $\x01";
1845
283
      break;
1846
283
    }
1847
736
    if (MCInst_getNumOperands(MI) == 2 &&
1848
736
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
736
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
556
      AsmString = "bvc,a,pn %icc, $\x01";
1852
556
      break;
1853
556
    }
1854
180
    if (MCInst_getNumOperands(MI) == 2 &&
1855
180
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
180
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
180
      AsmString = "bvs,a,pn %icc, $\x01";
1859
180
      break;
1860
180
    }
1861
0
    return NULL;
1862
4.23k
  case SP_BPICCNT:
1863
4.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
4.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
4.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
178
      AsmString = "ba,pn %icc, $\x01";
1868
178
      break;
1869
178
    }
1870
4.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
4.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
4.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
667
      AsmString = "bn,pn %icc, $\x01";
1875
667
      break;
1876
667
    }
1877
3.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
3.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
3.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
238
      AsmString = "bne,pn %icc, $\x01";
1882
238
      break;
1883
238
    }
1884
3.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
3.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
3.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
180
      AsmString = "be,pn %icc, $\x01";
1889
180
      break;
1890
180
    }
1891
2.97k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
653
      AsmString = "bg,pn %icc, $\x01";
1896
653
      break;
1897
653
    }
1898
2.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
165
      AsmString = "ble,pn %icc, $\x01";
1903
165
      break;
1904
165
    }
1905
2.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
2.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
2.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
201
      AsmString = "bge,pn %icc, $\x01";
1910
201
      break;
1911
201
    }
1912
1.95k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
247
      AsmString = "bl,pn %icc, $\x01";
1917
247
      break;
1918
247
    }
1919
1.70k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
210
      AsmString = "bgu,pn %icc, $\x01";
1924
210
      break;
1925
210
    }
1926
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
52
      AsmString = "bleu,pn %icc, $\x01";
1931
52
      break;
1932
52
    }
1933
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
56
      AsmString = "bcc,pn %icc, $\x01";
1938
56
      break;
1939
56
    }
1940
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1941
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
153
      AsmString = "bcs,pn %icc, $\x01";
1945
153
      break;
1946
153
    }
1947
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1948
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
140
      AsmString = "bpos,pn %icc, $\x01";
1952
140
      break;
1953
140
    }
1954
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1955
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
415
      AsmString = "bneg,pn %icc, $\x01";
1959
415
      break;
1960
415
    }
1961
678
    if (MCInst_getNumOperands(MI) == 2 &&
1962
678
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
678
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
429
      AsmString = "bvc,pn %icc, $\x01";
1966
429
      break;
1967
429
    }
1968
249
    if (MCInst_getNumOperands(MI) == 2 &&
1969
249
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
249
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
249
      AsmString = "bvs,pn %icc, $\x01";
1973
249
      break;
1974
249
    }
1975
0
    return NULL;
1976
3.25k
  case SP_BPXCCANT:
1977
3.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
3.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
3.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
146
      AsmString = "ba,a,pn %xcc, $\x01";
1982
146
      break;
1983
146
    }
1984
3.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
3.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
3.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
212
      AsmString = "bn,a,pn %xcc, $\x01";
1989
212
      break;
1990
212
    }
1991
2.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
52
      AsmString = "bne,a,pn %xcc, $\x01";
1996
52
      break;
1997
52
    }
1998
2.84k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
2.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
2.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
110
      AsmString = "be,a,pn %xcc, $\x01";
2003
110
      break;
2004
110
    }
2005
2.73k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
2.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
2.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
66
      AsmString = "bg,a,pn %xcc, $\x01";
2010
66
      break;
2011
66
    }
2012
2.67k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
48
      AsmString = "ble,a,pn %xcc, $\x01";
2017
48
      break;
2018
48
    }
2019
2.62k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
27
      AsmString = "bge,a,pn %xcc, $\x01";
2024
27
      break;
2025
27
    }
2026
2.59k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
120
      AsmString = "bl,a,pn %xcc, $\x01";
2031
120
      break;
2032
120
    }
2033
2.47k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
2.47k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
2.47k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
120
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
120
      break;
2039
120
    }
2040
2.35k
    if (MCInst_getNumOperands(MI) == 2 &&
2041
2.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
2.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
419
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
419
      break;
2046
419
    }
2047
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
2048
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
51
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
51
      break;
2053
51
    }
2054
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
2055
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
99
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
99
      break;
2060
99
    }
2061
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
2062
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
111
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
111
      break;
2067
111
    }
2068
1.67k
    if (MCInst_getNumOperands(MI) == 2 &&
2069
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
181
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
181
      break;
2074
181
    }
2075
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
2076
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
591
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
591
      break;
2081
591
    }
2082
904
    if (MCInst_getNumOperands(MI) == 2 &&
2083
904
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
904
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
904
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
904
      break;
2088
904
    }
2089
0
    return NULL;
2090
4.48k
  case SP_BPXCCNT:
2091
4.48k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
4.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
4.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
208
      AsmString = "ba,pn %xcc, $\x01";
2096
208
      break;
2097
208
    }
2098
4.27k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
4.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
4.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
580
      AsmString = "bn,pn %xcc, $\x01";
2103
580
      break;
2104
580
    }
2105
3.69k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
3.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
3.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
183
      AsmString = "bne,pn %xcc, $\x01";
2110
183
      break;
2111
183
    }
2112
3.50k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
220
      AsmString = "be,pn %xcc, $\x01";
2117
220
      break;
2118
220
    }
2119
3.28k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
145
      AsmString = "bg,pn %xcc, $\x01";
2124
145
      break;
2125
145
    }
2126
3.14k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
3.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
3.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
97
      AsmString = "ble,pn %xcc, $\x01";
2131
97
      break;
2132
97
    }
2133
3.04k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
3.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
3.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
76
      AsmString = "bge,pn %xcc, $\x01";
2138
76
      break;
2139
76
    }
2140
2.97k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
98
      AsmString = "bl,pn %xcc, $\x01";
2145
98
      break;
2146
98
    }
2147
2.87k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
2.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
2.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
1.19k
      AsmString = "bgu,pn %xcc, $\x01";
2152
1.19k
      break;
2153
1.19k
    }
2154
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
2155
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
288
      AsmString = "bleu,pn %xcc, $\x01";
2159
288
      break;
2160
288
    }
2161
1.39k
    if (MCInst_getNumOperands(MI) == 2 &&
2162
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
30
      AsmString = "bcc,pn %xcc, $\x01";
2166
30
      break;
2167
30
    }
2168
1.36k
    if (MCInst_getNumOperands(MI) == 2 &&
2169
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
105
      AsmString = "bcs,pn %xcc, $\x01";
2173
105
      break;
2174
105
    }
2175
1.25k
    if (MCInst_getNumOperands(MI) == 2 &&
2176
1.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
1.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
271
      AsmString = "bpos,pn %xcc, $\x01";
2180
271
      break;
2181
271
    }
2182
986
    if (MCInst_getNumOperands(MI) == 2 &&
2183
986
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
986
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
130
      AsmString = "bneg,pn %xcc, $\x01";
2187
130
      break;
2188
130
    }
2189
856
    if (MCInst_getNumOperands(MI) == 2 &&
2190
856
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
856
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
740
      AsmString = "bvc,pn %xcc, $\x01";
2194
740
      break;
2195
740
    }
2196
116
    if (MCInst_getNumOperands(MI) == 2 &&
2197
116
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
116
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
116
      AsmString = "bvs,pn %xcc, $\x01";
2201
116
      break;
2202
116
    }
2203
0
    return NULL;
2204
1.69k
  case SP_FMOVD_ICC:
2205
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2206
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2217
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2228
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2239
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2250
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2261
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2272
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2283
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2294
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2305
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2316
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2327
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2338
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2349
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2360
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
2371
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
1.69k
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
1.69k
    return NULL;
2382
338
  case SP_FMOVD_XCC:
2383
338
    if (MCInst_getNumOperands(MI) == 3 &&
2384
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
338
    if (MCInst_getNumOperands(MI) == 3 &&
2395
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
338
    if (MCInst_getNumOperands(MI) == 3 &&
2406
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
338
    if (MCInst_getNumOperands(MI) == 3 &&
2417
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
338
    if (MCInst_getNumOperands(MI) == 3 &&
2428
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
338
    if (MCInst_getNumOperands(MI) == 3 &&
2439
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
338
    if (MCInst_getNumOperands(MI) == 3 &&
2450
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
338
    if (MCInst_getNumOperands(MI) == 3 &&
2461
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
338
    if (MCInst_getNumOperands(MI) == 3 &&
2472
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
338
    if (MCInst_getNumOperands(MI) == 3 &&
2483
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
338
    if (MCInst_getNumOperands(MI) == 3 &&
2494
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
338
    if (MCInst_getNumOperands(MI) == 3 &&
2505
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
338
    if (MCInst_getNumOperands(MI) == 3 &&
2516
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
338
    if (MCInst_getNumOperands(MI) == 3 &&
2527
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
338
    if (MCInst_getNumOperands(MI) == 3 &&
2538
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
338
    if (MCInst_getNumOperands(MI) == 3 &&
2549
338
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
338
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
338
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
338
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
338
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
338
    return NULL;
2560
173
  case SP_FMOVQ_ICC:
2561
173
    if (MCInst_getNumOperands(MI) == 3 &&
2562
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
173
    if (MCInst_getNumOperands(MI) == 3 &&
2573
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
173
    if (MCInst_getNumOperands(MI) == 3 &&
2584
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
173
    if (MCInst_getNumOperands(MI) == 3 &&
2595
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
173
    if (MCInst_getNumOperands(MI) == 3 &&
2606
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
173
    if (MCInst_getNumOperands(MI) == 3 &&
2617
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
173
    if (MCInst_getNumOperands(MI) == 3 &&
2628
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
173
    if (MCInst_getNumOperands(MI) == 3 &&
2639
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
173
    if (MCInst_getNumOperands(MI) == 3 &&
2650
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
173
    if (MCInst_getNumOperands(MI) == 3 &&
2661
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
173
    if (MCInst_getNumOperands(MI) == 3 &&
2672
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
173
    if (MCInst_getNumOperands(MI) == 3 &&
2683
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
173
    if (MCInst_getNumOperands(MI) == 3 &&
2694
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
173
    if (MCInst_getNumOperands(MI) == 3 &&
2705
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
173
    if (MCInst_getNumOperands(MI) == 3 &&
2716
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
173
    if (MCInst_getNumOperands(MI) == 3 &&
2727
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
173
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
173
    return NULL;
2738
110
  case SP_FMOVQ_XCC:
2739
110
    if (MCInst_getNumOperands(MI) == 3 &&
2740
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
110
    if (MCInst_getNumOperands(MI) == 3 &&
2751
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
110
    if (MCInst_getNumOperands(MI) == 3 &&
2762
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
110
    if (MCInst_getNumOperands(MI) == 3 &&
2773
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
110
    if (MCInst_getNumOperands(MI) == 3 &&
2784
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
110
    if (MCInst_getNumOperands(MI) == 3 &&
2795
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
110
    if (MCInst_getNumOperands(MI) == 3 &&
2806
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
110
    if (MCInst_getNumOperands(MI) == 3 &&
2817
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
110
    if (MCInst_getNumOperands(MI) == 3 &&
2828
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
110
    if (MCInst_getNumOperands(MI) == 3 &&
2839
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
110
    if (MCInst_getNumOperands(MI) == 3 &&
2850
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
110
    if (MCInst_getNumOperands(MI) == 3 &&
2861
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
110
    if (MCInst_getNumOperands(MI) == 3 &&
2872
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
110
    if (MCInst_getNumOperands(MI) == 3 &&
2883
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
110
    if (MCInst_getNumOperands(MI) == 3 &&
2894
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
110
    if (MCInst_getNumOperands(MI) == 3 &&
2905
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
110
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
110
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
110
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
110
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
110
    return NULL;
2916
429
  case SP_FMOVS_ICC:
2917
429
    if (MCInst_getNumOperands(MI) == 3 &&
2918
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
429
    if (MCInst_getNumOperands(MI) == 3 &&
2929
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
429
    if (MCInst_getNumOperands(MI) == 3 &&
2940
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
429
    if (MCInst_getNumOperands(MI) == 3 &&
2951
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
429
    if (MCInst_getNumOperands(MI) == 3 &&
2962
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
429
    if (MCInst_getNumOperands(MI) == 3 &&
2973
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
429
    if (MCInst_getNumOperands(MI) == 3 &&
2984
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
429
    if (MCInst_getNumOperands(MI) == 3 &&
2995
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
429
    if (MCInst_getNumOperands(MI) == 3 &&
3006
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
429
    if (MCInst_getNumOperands(MI) == 3 &&
3017
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
429
    if (MCInst_getNumOperands(MI) == 3 &&
3028
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
429
    if (MCInst_getNumOperands(MI) == 3 &&
3039
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
429
    if (MCInst_getNumOperands(MI) == 3 &&
3050
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
429
    if (MCInst_getNumOperands(MI) == 3 &&
3061
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
429
    if (MCInst_getNumOperands(MI) == 3 &&
3072
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
429
    if (MCInst_getNumOperands(MI) == 3 &&
3083
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
429
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
429
    return NULL;
3094
22
  case SP_FMOVS_XCC:
3095
22
    if (MCInst_getNumOperands(MI) == 3 &&
3096
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
22
    if (MCInst_getNumOperands(MI) == 3 &&
3107
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
22
    if (MCInst_getNumOperands(MI) == 3 &&
3118
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
22
    if (MCInst_getNumOperands(MI) == 3 &&
3129
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
22
    if (MCInst_getNumOperands(MI) == 3 &&
3140
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
22
    if (MCInst_getNumOperands(MI) == 3 &&
3151
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
22
    if (MCInst_getNumOperands(MI) == 3 &&
3162
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
22
    if (MCInst_getNumOperands(MI) == 3 &&
3173
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
22
    if (MCInst_getNumOperands(MI) == 3 &&
3184
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
22
    if (MCInst_getNumOperands(MI) == 3 &&
3195
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
22
    if (MCInst_getNumOperands(MI) == 3 &&
3206
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
22
    if (MCInst_getNumOperands(MI) == 3 &&
3217
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
22
    if (MCInst_getNumOperands(MI) == 3 &&
3228
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
22
    if (MCInst_getNumOperands(MI) == 3 &&
3239
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
22
    if (MCInst_getNumOperands(MI) == 3 &&
3250
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
22
    if (MCInst_getNumOperands(MI) == 3 &&
3261
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
22
    return NULL;
3272
763
  case SP_MOVICCri:
3273
763
    if (MCInst_getNumOperands(MI) == 3 &&
3274
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
763
    if (MCInst_getNumOperands(MI) == 3 &&
3283
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
763
    if (MCInst_getNumOperands(MI) == 3 &&
3292
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
763
    if (MCInst_getNumOperands(MI) == 3 &&
3301
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
763
    if (MCInst_getNumOperands(MI) == 3 &&
3310
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
763
    if (MCInst_getNumOperands(MI) == 3 &&
3319
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
763
    if (MCInst_getNumOperands(MI) == 3 &&
3328
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
763
    if (MCInst_getNumOperands(MI) == 3 &&
3337
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
763
    if (MCInst_getNumOperands(MI) == 3 &&
3346
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
763
    if (MCInst_getNumOperands(MI) == 3 &&
3355
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
763
    if (MCInst_getNumOperands(MI) == 3 &&
3364
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
763
    if (MCInst_getNumOperands(MI) == 3 &&
3373
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
763
    if (MCInst_getNumOperands(MI) == 3 &&
3382
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
763
    if (MCInst_getNumOperands(MI) == 3 &&
3391
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
763
    if (MCInst_getNumOperands(MI) == 3 &&
3400
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
763
    if (MCInst_getNumOperands(MI) == 3 &&
3409
763
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
763
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
763
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
763
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
763
    return NULL;
3418
720
  case SP_MOVICCrr:
3419
720
    if (MCInst_getNumOperands(MI) == 3 &&
3420
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
720
    if (MCInst_getNumOperands(MI) == 3 &&
3431
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
720
    if (MCInst_getNumOperands(MI) == 3 &&
3442
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
720
    if (MCInst_getNumOperands(MI) == 3 &&
3453
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
720
    if (MCInst_getNumOperands(MI) == 3 &&
3464
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
720
    if (MCInst_getNumOperands(MI) == 3 &&
3475
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
720
    if (MCInst_getNumOperands(MI) == 3 &&
3486
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
720
    if (MCInst_getNumOperands(MI) == 3 &&
3497
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
720
    if (MCInst_getNumOperands(MI) == 3 &&
3508
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
720
    if (MCInst_getNumOperands(MI) == 3 &&
3519
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
720
    if (MCInst_getNumOperands(MI) == 3 &&
3530
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
720
    if (MCInst_getNumOperands(MI) == 3 &&
3541
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
720
    if (MCInst_getNumOperands(MI) == 3 &&
3552
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
720
    if (MCInst_getNumOperands(MI) == 3 &&
3563
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
720
    if (MCInst_getNumOperands(MI) == 3 &&
3574
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
720
    if (MCInst_getNumOperands(MI) == 3 &&
3585
720
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
720
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
720
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
720
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
720
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
720
    return NULL;
3596
217
  case SP_MOVXCCri:
3597
217
    if (MCInst_getNumOperands(MI) == 3 &&
3598
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
217
    if (MCInst_getNumOperands(MI) == 3 &&
3607
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
217
    if (MCInst_getNumOperands(MI) == 3 &&
3616
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
217
    if (MCInst_getNumOperands(MI) == 3 &&
3625
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
217
    if (MCInst_getNumOperands(MI) == 3 &&
3634
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
217
    if (MCInst_getNumOperands(MI) == 3 &&
3643
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
217
    if (MCInst_getNumOperands(MI) == 3 &&
3652
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
217
    if (MCInst_getNumOperands(MI) == 3 &&
3661
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
217
    if (MCInst_getNumOperands(MI) == 3 &&
3670
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
217
    if (MCInst_getNumOperands(MI) == 3 &&
3679
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
217
    if (MCInst_getNumOperands(MI) == 3 &&
3688
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
217
    if (MCInst_getNumOperands(MI) == 3 &&
3697
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
217
    if (MCInst_getNumOperands(MI) == 3 &&
3706
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
217
    if (MCInst_getNumOperands(MI) == 3 &&
3715
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
217
    if (MCInst_getNumOperands(MI) == 3 &&
3724
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
217
    if (MCInst_getNumOperands(MI) == 3 &&
3733
217
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
217
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
217
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
217
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
217
    return NULL;
3742
95
  case SP_MOVXCCrr:
3743
95
    if (MCInst_getNumOperands(MI) == 3 &&
3744
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
95
    if (MCInst_getNumOperands(MI) == 3 &&
3755
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
95
    if (MCInst_getNumOperands(MI) == 3 &&
3766
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
95
    if (MCInst_getNumOperands(MI) == 3 &&
3777
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
95
    if (MCInst_getNumOperands(MI) == 3 &&
3788
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
95
    if (MCInst_getNumOperands(MI) == 3 &&
3799
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
95
    if (MCInst_getNumOperands(MI) == 3 &&
3810
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
95
    if (MCInst_getNumOperands(MI) == 3 &&
3821
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
95
    if (MCInst_getNumOperands(MI) == 3 &&
3832
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
95
    if (MCInst_getNumOperands(MI) == 3 &&
3843
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
95
    if (MCInst_getNumOperands(MI) == 3 &&
3854
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
95
    if (MCInst_getNumOperands(MI) == 3 &&
3865
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
95
    if (MCInst_getNumOperands(MI) == 3 &&
3876
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
95
    if (MCInst_getNumOperands(MI) == 3 &&
3887
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
95
    if (MCInst_getNumOperands(MI) == 3 &&
3898
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
95
    if (MCInst_getNumOperands(MI) == 3 &&
3909
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
95
    return NULL;
3920
199
  case SP_ORri:
3921
199
    if (MCInst_getNumOperands(MI) == 3 &&
3922
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
199
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
63
      AsmString = "mov $\x03, $\x01";
3927
63
      break;
3928
63
    }
3929
136
    return NULL;
3930
152
  case SP_ORrr:
3931
152
    if (MCInst_getNumOperands(MI) == 3 &&
3932
152
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
152
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
152
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
152
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
152
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
43
      AsmString = "mov $\x03, $\x01";
3939
43
      break;
3940
43
    }
3941
109
    return NULL;
3942
488
  case SP_RESTORErr:
3943
488
    if (MCInst_getNumOperands(MI) == 3 &&
3944
488
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
488
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
488
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
149
      AsmString = "restore";
3949
149
      break;
3950
149
    }
3951
339
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
1.43k
  case SP_TXCCri:
3971
1.43k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
1.43k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
1.43k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
1.43k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
1.43k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
70
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
70
      break;
3979
70
    }
3980
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
1.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
117
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
117
      break;
3996
117
    }
3997
1.24k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
1.24k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
1.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
1.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
1.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
83
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
83
      break;
4013
83
    }
4014
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
1.16k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
80
      AsmString = "te %xcc, $\x01 + $\x02";
4029
80
      break;
4030
80
    }
4031
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
1.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
32
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
32
      break;
4047
32
    }
4048
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
1.05k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
37
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
37
      break;
4064
37
    }
4065
1.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.01k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.01k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
29
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
29
      break;
4081
29
    }
4082
986
    if (MCInst_getNumOperands(MI) == 3 &&
4083
986
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
986
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
986
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
986
    if (MCInst_getNumOperands(MI) == 3 &&
4091
986
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
986
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
986
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
986
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
182
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
182
      break;
4098
182
    }
4099
804
    if (MCInst_getNumOperands(MI) == 3 &&
4100
804
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
804
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
804
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
804
    if (MCInst_getNumOperands(MI) == 3 &&
4108
804
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
804
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
804
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
804
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
36
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
36
      break;
4115
36
    }
4116
768
    if (MCInst_getNumOperands(MI) == 3 &&
4117
768
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
768
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
768
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
768
    if (MCInst_getNumOperands(MI) == 3 &&
4125
768
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
768
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
768
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
768
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
57
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
57
      break;
4132
57
    }
4133
711
    if (MCInst_getNumOperands(MI) == 3 &&
4134
711
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
711
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
711
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
711
    if (MCInst_getNumOperands(MI) == 3 &&
4142
711
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
711
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
711
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
711
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
91
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
91
      break;
4149
91
    }
4150
620
    if (MCInst_getNumOperands(MI) == 3 &&
4151
620
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
620
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
620
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
620
    if (MCInst_getNumOperands(MI) == 3 &&
4159
620
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
620
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
620
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
620
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
155
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
155
      break;
4166
155
    }
4167
465
    if (MCInst_getNumOperands(MI) == 3 &&
4168
465
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
465
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
465
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
465
    if (MCInst_getNumOperands(MI) == 3 &&
4176
465
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
465
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
465
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
465
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
70
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
70
      break;
4183
70
    }
4184
395
    if (MCInst_getNumOperands(MI) == 3 &&
4185
395
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
395
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
395
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
395
    if (MCInst_getNumOperands(MI) == 3 &&
4193
395
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
395
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
395
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
395
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
66
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
66
      break;
4200
66
    }
4201
329
    if (MCInst_getNumOperands(MI) == 3 &&
4202
329
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
329
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
329
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
329
    if (MCInst_getNumOperands(MI) == 3 &&
4210
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
329
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
329
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
329
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
148
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
148
      break;
4217
148
    }
4218
181
    if (MCInst_getNumOperands(MI) == 3 &&
4219
181
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
181
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
181
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
181
    if (MCInst_getNumOperands(MI) == 3 &&
4227
181
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
181
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
181
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
181
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
181
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
181
      break;
4234
181
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
4.51k
  case SP_TXCCrr:
4245
4.51k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
4.51k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
4.51k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
4.51k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
4.51k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
4.51k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
4.51k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
93
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
93
      break;
4255
93
    }
4256
4.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
4.41k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
4.41k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
4.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
4.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
4.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
4.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
4.41k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
4.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
4.41k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
4.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
4.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
4.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
87
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
87
      break;
4276
87
    }
4277
4.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
4.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
4.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
4.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
4.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
4.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
4.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
4.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
4.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
4.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
4.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
4.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
4.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
341
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
341
      break;
4297
341
    }
4298
3.99k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
3.99k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
3.99k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
3.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
3.99k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
3.99k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
3.99k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
3.99k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
3.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
3.99k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
3.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
3.99k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
3.99k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
76
      AsmString = "te %xcc, $\x01 + $\x02";
4317
76
      break;
4318
76
    }
4319
3.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
3.91k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
3.91k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
3.91k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
3.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
3.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
3.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
3.91k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
3.91k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
3.91k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
3.91k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
3.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
3.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
74
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
74
      break;
4339
74
    }
4340
3.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
3.84k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
3.84k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
3.84k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
3.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
3.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
3.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
3.84k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
3.84k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
3.84k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
3.84k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
3.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
3.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
303
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
303
      break;
4360
303
    }
4361
3.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
3.53k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
3.53k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
3.53k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
3.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
3.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
3.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
3.53k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
3.53k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
3.53k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
3.53k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
3.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
3.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
59
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
59
      break;
4381
59
    }
4382
3.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
3.47k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
3.47k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
3.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
3.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
3.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
3.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
3.47k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
3.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
3.47k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
3.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
3.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
3.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
833
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
833
      break;
4402
833
    }
4403
2.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
2.64k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
2.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
2.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
2.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
2.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
2.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
2.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
2.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
2.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
2.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
2.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
2.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
23
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
23
      break;
4423
23
    }
4424
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
2.62k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
16
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
16
      break;
4444
16
    }
4445
2.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
2.60k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
2.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
53
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
53
      break;
4465
53
    }
4466
2.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
2.55k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
2.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
156
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
156
      break;
4486
156
    }
4487
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
2.39k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
2.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
2.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
2.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
339
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
339
      break;
4507
339
    }
4508
2.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4509
2.05k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
2.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
2.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
2.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4519
2.05k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
2.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
2.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
2.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
427
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
427
      break;
4528
427
    }
4529
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4530
1.63k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4540
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
440
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
440
      break;
4549
440
    }
4550
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4551
1.19k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4561
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
1.19k
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
1.19k
      break;
4570
1.19k
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
201
  case SP_V9FCMPD:
4583
201
    if (MCInst_getNumOperands(MI) == 3 &&
4584
201
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
201
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
201
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
201
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
201
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
52
      AsmString = "fcmpd $\x02, $\x03";
4591
52
      break;
4592
52
    }
4593
149
    return NULL;
4594
45
  case SP_V9FCMPED:
4595
45
    if (MCInst_getNumOperands(MI) == 3 &&
4596
45
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
45
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
45
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
45
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
45
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
15
      AsmString = "fcmped $\x02, $\x03";
4603
15
      break;
4604
15
    }
4605
30
    return NULL;
4606
71
  case SP_V9FCMPEQ:
4607
71
    if (MCInst_getNumOperands(MI) == 3 &&
4608
71
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
71
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
71
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
71
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
47
      AsmString = "fcmpeq $\x02, $\x03";
4615
47
      break;
4616
47
    }
4617
24
    return NULL;
4618
704
  case SP_V9FCMPES:
4619
704
    if (MCInst_getNumOperands(MI) == 3 &&
4620
704
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
704
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
704
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
704
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
704
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
109
      AsmString = "fcmpes $\x02, $\x03";
4627
109
      break;
4628
109
    }
4629
595
    return NULL;
4630
183
  case SP_V9FCMPQ:
4631
183
    if (MCInst_getNumOperands(MI) == 3 &&
4632
183
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
30
      AsmString = "fcmpq $\x02, $\x03";
4639
30
      break;
4640
30
    }
4641
153
    return NULL;
4642
123
  case SP_V9FCMPS:
4643
123
    if (MCInst_getNumOperands(MI) == 3 &&
4644
123
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
123
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
123
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
123
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
123
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
74
      AsmString = "fcmps $\x02, $\x03";
4651
74
      break;
4652
74
    }
4653
49
    return NULL;
4654
457
  case SP_V9FMOVD_FCC:
4655
457
    if (MCInst_getNumOperands(MI) == 4 &&
4656
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
457
    if (MCInst_getNumOperands(MI) == 4 &&
4669
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
457
    if (MCInst_getNumOperands(MI) == 4 &&
4682
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
457
    if (MCInst_getNumOperands(MI) == 4 &&
4695
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
457
    if (MCInst_getNumOperands(MI) == 4 &&
4708
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
457
    if (MCInst_getNumOperands(MI) == 4 &&
4721
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
457
    if (MCInst_getNumOperands(MI) == 4 &&
4734
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
457
    if (MCInst_getNumOperands(MI) == 4 &&
4747
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
457
    if (MCInst_getNumOperands(MI) == 4 &&
4760
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
457
    if (MCInst_getNumOperands(MI) == 4 &&
4773
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
457
    if (MCInst_getNumOperands(MI) == 4 &&
4786
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
457
    if (MCInst_getNumOperands(MI) == 4 &&
4799
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
457
    if (MCInst_getNumOperands(MI) == 4 &&
4812
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
457
    if (MCInst_getNumOperands(MI) == 4 &&
4825
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
457
    if (MCInst_getNumOperands(MI) == 4 &&
4838
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
457
    if (MCInst_getNumOperands(MI) == 4 &&
4851
457
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
457
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
457
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
457
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
457
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
457
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
457
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
457
    return NULL;
4864
56
  case SP_V9FMOVQ_FCC:
4865
56
    if (MCInst_getNumOperands(MI) == 4 &&
4866
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
56
    if (MCInst_getNumOperands(MI) == 4 &&
4879
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
56
    if (MCInst_getNumOperands(MI) == 4 &&
4892
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
56
    if (MCInst_getNumOperands(MI) == 4 &&
4905
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
56
    if (MCInst_getNumOperands(MI) == 4 &&
4918
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
56
    if (MCInst_getNumOperands(MI) == 4 &&
4931
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
56
    if (MCInst_getNumOperands(MI) == 4 &&
4944
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
56
    if (MCInst_getNumOperands(MI) == 4 &&
4957
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
56
    if (MCInst_getNumOperands(MI) == 4 &&
4970
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
56
    if (MCInst_getNumOperands(MI) == 4 &&
4983
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
56
    if (MCInst_getNumOperands(MI) == 4 &&
4996
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
56
    if (MCInst_getNumOperands(MI) == 4 &&
5009
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
56
    if (MCInst_getNumOperands(MI) == 4 &&
5022
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
56
    if (MCInst_getNumOperands(MI) == 4 &&
5035
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
56
    if (MCInst_getNumOperands(MI) == 4 &&
5048
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
56
    if (MCInst_getNumOperands(MI) == 4 &&
5061
56
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
56
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
56
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
56
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
56
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
56
    return NULL;
5074
46
  case SP_V9FMOVS_FCC:
5075
46
    if (MCInst_getNumOperands(MI) == 4 &&
5076
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
46
    if (MCInst_getNumOperands(MI) == 4 &&
5089
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
46
    if (MCInst_getNumOperands(MI) == 4 &&
5102
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
46
    if (MCInst_getNumOperands(MI) == 4 &&
5115
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
46
    if (MCInst_getNumOperands(MI) == 4 &&
5128
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
46
    if (MCInst_getNumOperands(MI) == 4 &&
5141
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
46
    if (MCInst_getNumOperands(MI) == 4 &&
5154
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
46
    if (MCInst_getNumOperands(MI) == 4 &&
5167
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
46
    if (MCInst_getNumOperands(MI) == 4 &&
5180
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
46
    if (MCInst_getNumOperands(MI) == 4 &&
5193
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
46
    if (MCInst_getNumOperands(MI) == 4 &&
5206
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
46
    if (MCInst_getNumOperands(MI) == 4 &&
5219
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
46
    if (MCInst_getNumOperands(MI) == 4 &&
5232
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
46
    if (MCInst_getNumOperands(MI) == 4 &&
5245
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
46
    if (MCInst_getNumOperands(MI) == 4 &&
5258
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
46
    if (MCInst_getNumOperands(MI) == 4 &&
5271
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
46
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
46
    return NULL;
5284
367
  case SP_V9MOVFCCri:
5285
367
    if (MCInst_getNumOperands(MI) == 4 &&
5286
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
367
    if (MCInst_getNumOperands(MI) == 4 &&
5297
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
367
    if (MCInst_getNumOperands(MI) == 4 &&
5308
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
367
    if (MCInst_getNumOperands(MI) == 4 &&
5319
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
367
    if (MCInst_getNumOperands(MI) == 4 &&
5330
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
367
    if (MCInst_getNumOperands(MI) == 4 &&
5341
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
367
    if (MCInst_getNumOperands(MI) == 4 &&
5352
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
367
    if (MCInst_getNumOperands(MI) == 4 &&
5363
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
367
    if (MCInst_getNumOperands(MI) == 4 &&
5374
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
367
    if (MCInst_getNumOperands(MI) == 4 &&
5385
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
367
    if (MCInst_getNumOperands(MI) == 4 &&
5396
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
367
    if (MCInst_getNumOperands(MI) == 4 &&
5407
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
367
    if (MCInst_getNumOperands(MI) == 4 &&
5418
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
367
    if (MCInst_getNumOperands(MI) == 4 &&
5429
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
367
    if (MCInst_getNumOperands(MI) == 4 &&
5440
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
367
    if (MCInst_getNumOperands(MI) == 4 &&
5451
367
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
367
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
367
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
367
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
367
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
367
    return NULL;
5462
128
  case SP_V9MOVFCCrr:
5463
128
    if (MCInst_getNumOperands(MI) == 4 &&
5464
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
128
    if (MCInst_getNumOperands(MI) == 4 &&
5477
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
128
    if (MCInst_getNumOperands(MI) == 4 &&
5490
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
128
    if (MCInst_getNumOperands(MI) == 4 &&
5503
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
128
    if (MCInst_getNumOperands(MI) == 4 &&
5516
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
128
    if (MCInst_getNumOperands(MI) == 4 &&
5529
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
128
    if (MCInst_getNumOperands(MI) == 4 &&
5542
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
128
    if (MCInst_getNumOperands(MI) == 4 &&
5555
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
128
    if (MCInst_getNumOperands(MI) == 4 &&
5568
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
128
    if (MCInst_getNumOperands(MI) == 4 &&
5581
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
128
    if (MCInst_getNumOperands(MI) == 4 &&
5594
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
128
    if (MCInst_getNumOperands(MI) == 4 &&
5607
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
128
    if (MCInst_getNumOperands(MI) == 4 &&
5620
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
128
    if (MCInst_getNumOperands(MI) == 4 &&
5633
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
128
    if (MCInst_getNumOperands(MI) == 4 &&
5646
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
128
    if (MCInst_getNumOperands(MI) == 4 &&
5659
128
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
128
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
128
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
128
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
128
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
128
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
128
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
128
    return NULL;
5672
137k
  }
5673
5674
42.2k
  tmp = cs_strdup(AsmString);
5675
42.2k
  AsmMnem = tmp;
5676
285k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
285k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
42.0k
      *AsmOps = '\0';
5679
42.0k
      AsmOps++;
5680
42.0k
      break;
5681
42.0k
    }
5682
285k
  }
5683
42.2k
  SStream_concat0(OS, AsmMnem);
5684
42.2k
  if (*AsmOps) {
5685
42.0k
    SStream_concat0(OS, "\t");
5686
42.0k
    if (strstr(AsmOps, "icc"))
5687
7.74k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
42.0k
    if (strstr(AsmOps, "xcc"))
5689
13.6k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
271k
    for (c = AsmOps; *c; c++) {
5691
229k
      if (*c == '$') {
5692
59.8k
        c += 1;
5693
59.8k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
59.8k
          printOperand(MI, *c - 1, OS);
5701
170k
      } else {
5702
170k
        SStream_concat(OS, "%c", *c);
5703
170k
      }
5704
229k
    }
5705
42.0k
  }
5706
42.2k
  return tmp;
5707
137k
}
5708
5709
#endif // PRINT_ALIAS_INSTR