/src/capstonenext/arch/ARM/ARMBaseInfo.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //===-- ARMBaseInfo.cpp - ARM Base encoding information------------===// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This file provides basic encoding and assembly information for ARM. |
24 | | // |
25 | | //===----------------------------------------------------------------------===// |
26 | | |
27 | | #include <capstone/platform.h> |
28 | | |
29 | | #include "ARMBaseInfo.h" |
30 | | #include "../../utils.h" |
31 | | |
32 | | #define CONCAT(a, b) CONCAT_(a, b) |
33 | | #define CONCAT_(a, b) a##_##b |
34 | | |
35 | | // CS namespace begin: ARMSysReg |
36 | | |
37 | | // lookup system register using 12-bit SYSm value. |
38 | | // Note: the search is uniqued using M1 mask |
39 | | const char *get_pred_mask(ARM_PredBlockMask pred_mask) |
40 | 0 | { |
41 | 0 | switch (pred_mask) { |
42 | 0 | default: |
43 | 0 | CS_ASSERT_RET_VAL(0 && "pred_mask not handled.", NULL); |
44 | 0 | case ARM_T: |
45 | 0 | return "T"; |
46 | 0 | case ARM_TT: |
47 | 0 | return "TT"; |
48 | 0 | case ARM_TE: |
49 | 0 | return "TE"; |
50 | 0 | case ARM_TTT: |
51 | 0 | return "TTT"; |
52 | 0 | case ARM_TTE: |
53 | 0 | return "TTE"; |
54 | 0 | case ARM_TEE: |
55 | 0 | return "TEE"; |
56 | 0 | case ARM_TET: |
57 | 0 | return "TET"; |
58 | 0 | case ARM_TTTT: |
59 | 0 | return "TTTT"; |
60 | 0 | case ARM_TTTE: |
61 | 0 | return "TTTE"; |
62 | 0 | case ARM_TTEE: |
63 | 0 | return "TTEE"; |
64 | 0 | case ARM_TTET: |
65 | 0 | return "TTET"; |
66 | 0 | case ARM_TEEE: |
67 | 0 | return "TEEE"; |
68 | 0 | case ARM_TEET: |
69 | 0 | return "TEET"; |
70 | 0 | case ARM_TETT: |
71 | 0 | return "TETT"; |
72 | 0 | case ARM_TETE: |
73 | 0 | return "TETE"; |
74 | 0 | } |
75 | 0 | } |
76 | | |
77 | | #define GET_MCLASSSYSREG_IMPL |
78 | | #include "ARMGenSystemRegister.inc" |
79 | | |
80 | | const ARMSysReg_MClassSysReg * |
81 | | ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) |
82 | 7.79k | { |
83 | 7.79k | return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm); |
84 | 7.79k | } |
85 | | |
86 | | // returns APSR with _<bits> qualifier. |
87 | | // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier |
88 | | const ARMSysReg_MClassSysReg * |
89 | | ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) |
90 | 7.22k | { |
91 | 7.22k | return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) | |
92 | 7.22k | (SYSm & 0xFF)); |
93 | 7.22k | } |
94 | | |
95 | | // lookup system registers using 8-bit SYSm value |
96 | | const ARMSysReg_MClassSysReg * |
97 | | ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) |
98 | 7.39k | { |
99 | 7.39k | return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) | |
100 | 7.39k | (SYSm & 0xFF)); |
101 | 7.39k | } |