Coverage Report

Created: 2025-07-01 07:03

/src/capstonenext/arch/HPPA/HPPADisassembler.c
Line
Count
Source (jump to first uncovered line)
1
/* Capstone Disassembly Engine */
2
/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
3
4
#ifdef CAPSTONE_HAS_HPPA
5
6
#include <string.h>
7
#include <stddef.h> // offsetof macro
8
#include <stdio.h>
9
#include "HPPADisassembler.h"
10
#include "HPPAConstants.h"
11
12
#include "../../Mapping.h"
13
#include "../../MathExtras.h"
14
#include "../../utils.h"
15
16
0
#define CMPLT_HAS_MODIFY_BIT(CMPLT) (((CMPLT)&1) == 1)
17
18
0
#define HPPA_EXT_REF(MI) (&MI->hppa_ext)
19
20
static const char *const compare_cond_names[] = {
21
  "",   "=",  "<",  "<=", "<<",  "<<=", "sv",  "od",
22
  "tr", "<>", ">=", ">",  ">>=", ">>",  "nsv", "ev"
23
};
24
static const char *const compare_cond_64_names[] = {
25
  "*",   "*=",  "*<",  "*<=", "*<<",  "*<<=", "*sv",  "*od",
26
  "*tr", "*<>", "*>=", "*>",  "*>>=", "*>>",  "*nsv", "*ev"
27
};
28
static const char *const cmpib_cond_64_names[] = { "*<<",  "*=",  "*<",  "*<=",
29
               "*>>=", "*<>", "*>=", "*>" };
30
static const char *const add_cond_names[] = {
31
  "",   "=",  "<",  "<=", "nuv", "znv", "sv",  "od",
32
  "tr", "<>", ">=", ">",  "uv",  "vnz", "nsv", "ev"
33
};
34
static const char *const add_cond_64_names[] = {
35
  "*",   "*=",  "*<",  "*<=", "*nuv", "*znv", "*sv",  "*od",
36
  "*tr", "*<>", "*>=", "*>",  "*uv",  "*vnz", "*nsv", "*ev"
37
};
38
static const char *const wide_add_cond_names[] = {
39
  "*",  "=",  "<",  "<=", "nuv", "*=",  "*<",  "*<=",
40
  "tr", "<>", ">=", ">",  "uv",  "*<>", "*>=", "*>"
41
};
42
static const char *const logical_cond_names[] = {
43
  "",   "=",  "<",  "<=", "", "", "", "od",
44
  "tr", "<>", ">=", ">",  "", "", "", "ev"
45
};
46
static const char *const logical_cond_64_names[] = {
47
  "*",   "*=",  "*<",  "*<=", "", "", "", "*od",
48
  "*tr", "*<>", "*>=", "*>",  "", "", "", "*ev"
49
};
50
static const char *const unit_cond_names[] = { "",    "swz", "sbz", "shz",
51
                 "sdc", "swc", "sbc", "shc",
52
                 "tr",  "nwz", "nbz", "nhz",
53
                 "ndc", "nwc", "nbc", "nhc" };
54
static const char *const unit_cond_64_names[] = {
55
  "*",   "*swz", "*sbz", "*shz", "*sdc", "*swc", "*sbc", "*shc",
56
  "*tr", "*nwz", "*nbz", "*nhz", "*ndc", "*nwc", "*nbc", "*nhc"
57
};
58
static const char *const shift_cond_names[] = { "",   "=",  "<",  "od",
59
            "tr", "<>", ">=", "ev" };
60
static const char *const shift_cond_64_names[] = { "*",   "*=",  "*<",  "*od",
61
               "*tr", "*<>", "*>=", "*ev" };
62
static const char *const index_compl_names[] = { "", "m", "s", "sm" };
63
static const char *const short_ldst_compl_names[] = { "", "ma", "", "mb" };
64
static const char *const short_bytes_compl_names[] = { "", "b,m", "e", "e,m" };
65
static const char *const float_format_names[] = { "sgl", "dbl", "", "quad" };
66
static const char *const float_cond_names[] = {
67
  "", "acc", "rej",  "", "", "acc8", "rej8", "", "", "acc6", "",
68
  "", "",    "acc4", "", "", "",     "acc2", "", "", "",     "",
69
  "", "",    "",     "", "", "",     "",     "", "", ""
70
};
71
static const char *const fcnv_fixed_names[] = { "w", "dw", "", "qw" };
72
static const char *const fcnv_ufixed_names[] = { "uw", "udw", "", "uqw" };
73
static const char *const float_comp_names[] = {
74
  "false?", "false", "?",  "!<=>", "=", "=t",  "?=",  "!<>",
75
  "!?>=",   "<",     "?<", "!>=",  "!?>", "<=",  "?<=", "!>",
76
  "!?<=",   ">",     "?>", "!<=",  "!?<", ">=",  "?>=", "!<",
77
  "!?=",    "<>",    "!=", "!=t",  "!?",  "<=>", "true?", "true"
78
};
79
static const char *const signed_unsigned_names[] = { "u", "s" };
80
static const char *const saturation_names[] = { "us", "ss", "", "" };
81
static const char *const add_compl_names[] = { "", "", "l", "tsv" };
82
83
0
#define CREATE_GR_REG(MI, gr) MCOperand_CreateReg0(MI, gr + HPPA_REG_GR0)
84
0
#define CREATE_SR_REG(MI, sr) MCOperand_CreateReg0(MI, sr + HPPA_REG_SR0)
85
0
#define CREATE_CR_REG(MI, cr) MCOperand_CreateReg0(MI, cr + HPPA_REG_CR0)
86
0
#define CREATE_FPR_REG(MI, fpr) MCOperand_CreateReg0(MI, fpr + HPPA_REG_FPR0)
87
0
#define CREATE_FPE_REG(MI, fpe) MCOperand_CreateReg0(MI, fpe + HPPA_REG_FPE0)
88
#define CREATE_SP_FPR_REG(MI, fpr) \
89
0
  MCOperand_CreateReg0(MI, fpr + HPPA_REG_SP_FPR0)
90
91
static void create_float_reg_spec(MCInst *MI, uint32_t reg, uint32_t fpe_flag)
92
0
{
93
0
  if (fpe_flag == 1) {
94
0
    CREATE_FPE_REG(MI, reg);
95
0
  } else {
96
0
    CREATE_FPR_REG(MI, reg);
97
0
  }
98
0
}
99
100
/* Get at various relevant fields of an instruction word.  */
101
102
0
#define MASK_5 0x1f
103
#define MASK_10 0x3ff
104
0
#define MASK_11 0x7ff
105
0
#define MASK_14 0x3fff
106
#define MASK_16 0xffff
107
0
#define MASK_21 0x1fffff
108
109
/* Routines to extract various sized constants out of hppa
110
   instructions.  */
111
112
/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp.  */
113
static int extract_3(unsigned word)
114
0
{
115
0
  return get_insn_field(word, 18, 18) << 2 | get_insn_field(word, 16, 17);
116
0
}
117
118
static int extract_5_load(unsigned word)
119
0
{
120
0
  return LowSignExtend64(word >> 16 & MASK_5, 5);
121
0
}
122
123
/* Extract the immediate field from a st{bhw}s instruction.  */
124
125
static int extract_5_store(unsigned word)
126
0
{
127
0
  return LowSignExtend64(word & MASK_5, 5);
128
0
}
129
130
/* Extract an 11 bit immediate field.  */
131
132
static int extract_11(unsigned word)
133
0
{
134
0
  return LowSignExtend64(word & MASK_11, 11);
135
0
}
136
137
/* Extract a 14 bit immediate field.  */
138
139
static int extract_14(unsigned word)
140
0
{
141
0
  return LowSignExtend64(word & MASK_14, 14);
142
0
}
143
144
/* Extract a 16 bit immediate field. */
145
146
static int extract_16(unsigned word, bool wide)
147
0
{
148
0
  int m15, m0, m1;
149
150
0
  m0 = get_insn_bit(word, 16);
151
0
  m1 = get_insn_bit(word, 17);
152
0
  m15 = get_insn_bit(word, 31);
153
0
  word = (word >> 1) & 0x1fff;
154
0
  if (wide) {
155
0
    word = word | (m15 << 15) | ((m15 ^ m0) << 14) |
156
0
           ((m15 ^ m1) << 13);
157
0
  } else {
158
0
    word = word | (m15 << 15) | (m15 << 14) | (m15 << 13);
159
0
  }
160
0
  return SignExtend32(word, 16);
161
0
}
162
163
/* Extract a 21 bit constant.  */
164
165
static int32_t extract_21(unsigned word)
166
0
{
167
0
  int val;
168
169
0
  word &= MASK_21;
170
0
  word <<= 11;
171
0
  val = get_insn_field(word, 20, 20);
172
0
  val <<= 11;
173
0
  val |= get_insn_field(word, 9, 19);
174
0
  val <<= 2;
175
0
  val |= get_insn_field(word, 5, 6);
176
0
  val <<= 5;
177
0
  val |= get_insn_field(word, 0, 4);
178
0
  val <<= 2;
179
0
  val |= get_insn_field(word, 7, 8);
180
0
  return (uint32_t) SignExtend32(val, 21) << 11;
181
0
}
182
183
/* Extract a 12 bit constant from branch instructions.  */
184
185
static int32_t extract_12(unsigned word)
186
0
{
187
0
  return (uint32_t) SignExtend32(get_insn_field(word, 19, 28) |
188
0
            get_insn_field(word, 29, 29) << 10 |
189
0
            (word & 0x1) << 11,
190
0
          12)
191
0
         << 2;
192
0
}
193
194
/* Extract a 17 bit constant from branch instructions, returning the
195
   19 bit signed value.  */
196
197
static int32_t extract_17(unsigned word)
198
0
{
199
0
  return (uint32_t) SignExtend32(get_insn_field(word, 19, 28) |
200
0
            get_insn_field(word, 29, 29) << 10 |
201
0
            get_insn_field(word, 11, 15) << 11 |
202
0
            (word & 0x1) << 16,
203
0
          17)
204
0
         << 2;
205
0
}
206
207
static int32_t extract_22(unsigned word)
208
0
{
209
0
  return (uint32_t) SignExtend32(get_insn_field(word, 19, 28) |
210
0
            get_insn_field(word, 29, 29) << 10 |
211
0
            get_insn_field(word, 11, 15) << 11 |
212
0
            get_insn_field(word, 6, 10) << 16 |
213
0
            (word & 0x1) << 21,
214
0
          22)
215
0
         << 2;
216
0
}
217
218
static void push_str_modifier(hppa_ext *hppa, const char *modifier)
219
0
{
220
0
  if (strcmp(modifier, "")) {
221
0
    hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++];
222
0
    CS_ASSERT_RET(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN);
223
0
    mod->type = HPPA_MOD_STR;
224
0
    CS_ASSERT_RET(strlen(modifier) < HPPA_STR_MODIFIER_LEN);
225
0
    strncpy(mod->str_mod, modifier, HPPA_STR_MODIFIER_LEN - 1);
226
0
  }
227
0
}
228
229
static void push_int_modifier(hppa_ext *hppa, uint64_t modifier)
230
0
{
231
0
  hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++];
232
0
  CS_ASSERT_RET(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN);
233
0
  mod->type = HPPA_MOD_INT;
234
0
  mod->int_mod = modifier;
235
0
}
236
237
static void fill_sysop_insn_name(MCInst *MI, uint32_t insn)
238
0
{
239
0
  uint32_t ext8 = get_insn_field(insn, 19, 26);
240
0
  uint32_t ext5 = get_insn_field(insn, 11, 15);
241
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
242
0
    switch (ext8) {
243
0
    case 0xa5:
244
0
      MCInst_setOpcode(MI, HPPA_INS_MFIA);
245
0
      return;
246
0
    case 0xc6:
247
0
      MCInst_setOpcode(MI, HPPA_INS_MTSARCM);
248
0
      return;
249
0
    case 0x65:
250
0
      push_str_modifier(HPPA_EXT_REF(MI), "r");
251
      // fallthrough
252
0
    case 0x60:
253
0
      MCInst_setOpcode(MI, HPPA_INS_RFI);
254
0
      return;
255
0
    default:
256
0
      break;
257
0
    }
258
0
  }
259
260
0
  switch (ext8) {
261
0
  case 0x00:
262
0
    MCInst_setOpcode(MI, HPPA_INS_BREAK);
263
0
    break;
264
0
  case 0x20:
265
0
    if (ext5 == 0x00) {
266
0
      MCInst_setOpcode(MI, HPPA_INS_SYNC);
267
0
    } else if (ext5 == 0x10) {
268
0
      MCInst_setOpcode(MI, HPPA_INS_SYNCDMA);
269
0
    }
270
0
    break;
271
0
  case 0x60:
272
0
    MCInst_setOpcode(MI, HPPA_INS_RFI);
273
0
    break;
274
0
  case 0x65:
275
0
    MCInst_setOpcode(MI, HPPA_INS_RFIR);
276
0
    break;
277
0
  case 0x6b:
278
0
    MCInst_setOpcode(MI, HPPA_INS_SSM);
279
0
    break;
280
0
  case 0x73:
281
0
    MCInst_setOpcode(MI, HPPA_INS_RSM);
282
0
    break;
283
0
  case 0xc3:
284
0
    MCInst_setOpcode(MI, HPPA_INS_MTSM);
285
0
    break;
286
0
  case 0x85:
287
0
    MCInst_setOpcode(MI, HPPA_INS_LDSID);
288
0
    break;
289
0
  case 0xc1:
290
0
    MCInst_setOpcode(MI, HPPA_INS_MTSP);
291
0
    break;
292
0
  case 0x25:
293
0
    MCInst_setOpcode(MI, HPPA_INS_MFSP);
294
0
    break;
295
0
  case 0xc2:
296
0
    MCInst_setOpcode(MI, HPPA_INS_MTCTL);
297
0
    break;
298
0
  case 0x45:
299
0
    MCInst_setOpcode(MI, HPPA_INS_MFCTL);
300
0
    if (get_insn_bit(insn, 17) == 1 &&
301
0
        MODE_IS_HPPA_20(MI->csh->mode)) {
302
0
      push_str_modifier(HPPA_EXT_REF(MI), "w");
303
0
    }
304
0
    break;
305
0
  default:
306
0
    break;
307
0
  }
308
0
}
309
310
static bool decode_sysop(const cs_struct *ud, MCInst *MI, uint32_t insn)
311
0
{
312
0
  uint32_t ext8 = get_insn_field(insn, 19, 26);
313
0
  uint32_t ext5 = get_insn_field(insn, 11, 15);
314
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
315
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
316
0
  uint32_t t = get_insn_field(insn, 27, 31);
317
0
  uint32_t s = extract_3(insn);
318
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
319
0
    switch (ext8) {
320
0
    case 0xa5:
321
0
      if (ext5 != 0) {
322
0
        return false;
323
0
      }
324
0
      CREATE_GR_REG(MI, t);
325
0
      return true;
326
0
    case 0xc6:
327
0
      CREATE_GR_REG(MI, r2);
328
0
      return true;
329
0
    default:
330
0
      break;
331
0
    }
332
0
  }
333
334
0
  switch (ext8) {
335
0
  case 0x00:
336
0
    MCOperand_CreateImm0(MI, t);
337
0
    MCOperand_CreateImm0(MI, get_insn_field(insn, 6, 18));
338
0
    return true;
339
0
  case 0x20:
340
0
    if (ext5 != 0x00 && ext5 != 0x10) {
341
0
      return false;
342
0
    }
343
    // fallthrough
344
0
  case 0x60:
345
0
  case 0x65:
346
0
    return true;
347
0
  case 0x6b:
348
0
  case 0x73:
349
0
    MCOperand_CreateImm0(MI, get_insn_field(insn, 9, 15));
350
0
    CREATE_GR_REG(MI, t);
351
0
    return true;
352
0
  case 0xc3:
353
0
    CREATE_GR_REG(MI, r2);
354
0
    return true;
355
0
  case 0x85:
356
0
    CREATE_SR_REG(MI, s);
357
0
    CREATE_GR_REG(MI, r1);
358
0
    CREATE_GR_REG(MI, t);
359
0
    return true;
360
0
  case 0xc1:
361
0
    CREATE_GR_REG(MI, r2);
362
0
    CREATE_SR_REG(MI, s);
363
0
    return true;
364
0
  case 0x25:
365
0
    if (ext5 != 0) {
366
0
      return false;
367
0
    }
368
0
    CREATE_SR_REG(MI, s);
369
0
    CREATE_GR_REG(MI, t);
370
0
    return true;
371
0
  case 0xc2:
372
0
    CREATE_GR_REG(MI, r2);
373
0
    CREATE_CR_REG(MI, r1);
374
0
    return true;
375
0
  case 0x45:
376
0
    if (ext5 != 0) {
377
0
      return false;
378
0
    }
379
0
    if (get_insn_bit(insn, 17) == 1 && MODE_IS_HPPA_20(ud->mode) &&
380
0
        r1 != 11) {
381
0
      return false;
382
0
    }
383
0
    CREATE_CR_REG(MI, r1);
384
0
    CREATE_GR_REG(MI, t);
385
0
    return true;
386
0
  default:
387
0
    return false;
388
0
  }
389
0
}
390
391
static void fill_memmgmt_insn_name(MCInst *MI, uint32_t insn)
392
0
{
393
0
  uint32_t ext = get_insn_field(insn, 19, 25);
394
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
395
0
    switch (ext) {
396
0
    case 0x20:
397
0
      MCInst_setOpcode(MI, HPPA_INS_IITLBT);
398
0
      return;
399
0
    case 0x18:
400
0
      MCInst_setOpcode(MI, HPPA_INS_PITLB);
401
0
      push_str_modifier(HPPA_EXT_REF(MI), "l");
402
0
      return;
403
0
    case 0x60:
404
0
      MCInst_setOpcode(MI, HPPA_INS_IDTLBT);
405
0
      return;
406
0
    case 0x58:
407
0
      MCInst_setOpcode(MI, HPPA_INS_PDTLB);
408
0
      push_str_modifier(HPPA_EXT_REF(MI), "l");
409
0
      return;
410
0
    case 0x4f:
411
0
      MCInst_setOpcode(MI, HPPA_INS_FIC);
412
0
      return;
413
0
    case 0x46:
414
0
      if (get_insn_bit(insn, 18) == 0) {
415
0
        MCInst_setOpcode(MI, HPPA_INS_PROBE);
416
0
      } else {
417
0
        MCInst_setOpcode(MI, HPPA_INS_PROBEI);
418
0
      };
419
0
      push_str_modifier(HPPA_EXT_REF(MI), "r");
420
0
      return;
421
0
    case 0x47:
422
0
      if (get_insn_bit(insn, 18) == 0) {
423
0
        MCInst_setOpcode(MI, HPPA_INS_PROBE);
424
0
      } else {
425
0
        MCInst_setOpcode(MI, HPPA_INS_PROBEI);
426
0
      };
427
0
      push_str_modifier(HPPA_EXT_REF(MI), "w");
428
0
      return;
429
0
    default:
430
0
      break;
431
0
    }
432
0
  }
433
434
0
  switch (ext) {
435
0
  case 0x00:
436
0
    MCInst_setOpcode(MI, HPPA_INS_IITLBP);
437
0
    break;
438
0
  case 0x01:
439
0
    MCInst_setOpcode(MI, HPPA_INS_IITLBA);
440
0
    break;
441
0
  case 0x08:
442
0
    MCInst_setOpcode(MI, HPPA_INS_PITLB);
443
0
    break;
444
0
  case 0x09:
445
0
    MCInst_setOpcode(MI, HPPA_INS_PITLBE);
446
0
    break;
447
0
  case 0x0a:
448
0
    MCInst_setOpcode(MI, HPPA_INS_FIC);
449
0
    break;
450
0
  case 0x0b:
451
0
    MCInst_setOpcode(MI, HPPA_INS_FICE);
452
0
    break;
453
0
  case 0x40:
454
0
    MCInst_setOpcode(MI, HPPA_INS_IDTLBP);
455
0
    break;
456
0
  case 0x41:
457
0
    MCInst_setOpcode(MI, HPPA_INS_IDTLBA);
458
0
    break;
459
0
  case 0x48:
460
0
    MCInst_setOpcode(MI, HPPA_INS_PDTLB);
461
0
    break;
462
0
  case 0x49:
463
0
    MCInst_setOpcode(MI, HPPA_INS_PDTLBE);
464
0
    break;
465
0
  case 0x4a:
466
0
    MCInst_setOpcode(MI, HPPA_INS_FDC);
467
0
    break;
468
0
  case 0x4b:
469
0
    MCInst_setOpcode(MI, HPPA_INS_FDCE);
470
0
    break;
471
0
  case 0x4e:
472
0
    MCInst_setOpcode(MI, HPPA_INS_PDC);
473
0
    break;
474
0
  case 0x46:
475
0
    if (get_insn_bit(insn, 18) == 0) {
476
0
      MCInst_setOpcode(MI, HPPA_INS_PROBER);
477
0
    } else {
478
0
      MCInst_setOpcode(MI, HPPA_INS_PROBERI);
479
0
    };
480
0
    break;
481
0
  case 0x47:
482
0
    if (get_insn_bit(insn, 18) == 0) {
483
0
      MCInst_setOpcode(MI, HPPA_INS_PROBEW);
484
0
    } else {
485
0
      MCInst_setOpcode(MI, HPPA_INS_PROBEWI);
486
0
    };
487
0
    break;
488
0
  case 0x4d:
489
0
    MCInst_setOpcode(MI, HPPA_INS_LPA);
490
0
    break;
491
0
  case 0x4c:
492
0
    MCInst_setOpcode(MI, HPPA_INS_LCI);
493
0
    break;
494
0
  default:
495
0
    break;
496
0
  }
497
0
}
498
499
static void fill_memmgmt_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
500
0
{
501
0
  uint8_t cmplt = get_insn_bit(insn, 26);
502
0
  uint32_t ext = get_insn_field(insn, 19, 25);
503
0
  if (MODE_IS_HPPA_20(mode)) {
504
0
    switch (ext) {
505
0
    case 0x18:
506
0
    case 0x58:
507
0
    case 0x4f:
508
0
      goto success;
509
0
    default:
510
0
      break;
511
0
    }
512
0
  }
513
514
0
  switch (ext) {
515
0
  case 0x08:
516
0
  case 0x09:
517
0
  case 0x0a:
518
0
  case 0x0b:
519
0
  case 0x48:
520
0
  case 0x49:
521
0
  case 0x4a:
522
0
  case 0x4b:
523
0
  case 0x4e:
524
0
  case 0x4d:
525
0
    break;
526
0
  default:
527
0
    return;
528
0
  }
529
0
success:
530
0
  if (CMPLT_HAS_MODIFY_BIT(cmplt)) {
531
0
    hppa_ext->b_writeble = true;
532
0
  }
533
0
  push_str_modifier(hppa_ext, index_compl_names[cmplt]);
534
0
}
535
536
static bool decode_memmgmt(const cs_struct *ud, MCInst *MI, uint32_t insn)
537
0
{
538
0
  uint32_t ext = get_insn_field(insn, 19, 25);
539
0
  uint32_t b = get_insn_field(insn, 6, 10);
540
0
  uint32_t r = get_insn_field(insn, 11, 15);
541
0
  uint32_t s3 = extract_3(insn);
542
0
  uint32_t s2 = get_insn_field(insn, 16, 17);
543
0
  uint32_t t = get_insn_field(insn, 27, 31);
544
0
  if (ext > 0x20 && get_insn_bit(insn, 18) == 1 &&
545
0
      (ext != 0x46 && ext != 0x47)) {
546
0
    if (MODE_IS_HPPA_20(ud->mode)) {
547
0
      if (ext != 0x4a) {
548
0
        return false;
549
0
      }
550
0
    } else {
551
0
      return false;
552
0
    }
553
0
  }
554
0
  if (MODE_IS_HPPA_20(ud->mode)) {
555
0
    switch (ext) {
556
0
    case 0x20:
557
0
    case 0x60:
558
0
      CREATE_GR_REG(MI, r);
559
0
      CREATE_GR_REG(MI, b);
560
0
      goto success;
561
0
    case 0x58:
562
0
    case 0x4f:
563
0
      CREATE_GR_REG(MI, r);
564
0
      CREATE_SR_REG(MI, s2);
565
0
      CREATE_GR_REG(MI, b);
566
0
      goto success;
567
0
    case 0x18:
568
0
      CREATE_GR_REG(MI, r);
569
0
      CREATE_SR_REG(MI, s3);
570
0
      CREATE_GR_REG(MI, b);
571
0
      goto success;
572
0
    case 0x4a:
573
0
      if (get_insn_bit(insn, 18) == 1) {
574
0
        MCOperand_CreateImm0(MI, LowSignExtend64(r, 5));
575
0
      } else {
576
0
        CREATE_GR_REG(MI, r);
577
0
      }
578
0
      CREATE_SR_REG(MI, s2);
579
0
      CREATE_GR_REG(MI, b);
580
0
      goto success;
581
0
    default:
582
0
      break;
583
0
    }
584
0
  }
585
586
0
  switch (ext) {
587
0
  case 0x00:
588
0
  case 0x01:
589
0
  case 0x08:
590
0
  case 0x09:
591
0
  case 0x0a:
592
0
  case 0x0b:
593
0
    CREATE_GR_REG(MI, r);
594
0
    CREATE_SR_REG(MI, s3);
595
0
    CREATE_GR_REG(MI, b);
596
0
    break;
597
0
  case 0x40:
598
0
  case 0x41:
599
0
  case 0x48:
600
0
  case 0x49:
601
0
  case 0x4a:
602
0
  case 0x4b:
603
0
  case 0x4e:
604
0
    CREATE_GR_REG(MI, r);
605
0
    CREATE_SR_REG(MI, s2);
606
0
    CREATE_GR_REG(MI, b);
607
0
    break;
608
0
  case 0x46:
609
0
  case 0x47:
610
0
    CREATE_SR_REG(MI, s2);
611
0
    CREATE_GR_REG(MI, b);
612
0
    if (get_insn_bit(insn, 18) == 0) {
613
0
      CREATE_GR_REG(MI, r);
614
0
    } else {
615
0
      MCOperand_CreateImm0(MI, r);
616
0
    }
617
0
    CREATE_GR_REG(MI, t);
618
0
    break;
619
0
  case 0x4d:
620
0
  case 0x4c:
621
0
    CREATE_GR_REG(MI, r);
622
0
    CREATE_SR_REG(MI, s2);
623
0
    CREATE_GR_REG(MI, b);
624
0
    CREATE_GR_REG(MI, t);
625
0
    break;
626
0
  default:
627
0
    return false;
628
0
  }
629
0
success:
630
0
  fill_memmgmt_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode);
631
0
  return true;
632
0
}
633
634
static void fill_alu_insn_name(MCInst *MI, uint32_t insn)
635
0
{
636
0
  uint32_t ext = get_insn_field(insn, 20, 25);
637
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
638
0
    switch (ext) {
639
0
    case 0x28:
640
0
    case 0x38:
641
0
    case 0x1c:
642
0
    case 0x3c:
643
0
      MCInst_setOpcode(MI, HPPA_INS_ADD);
644
0
      return;
645
0
    case 0x19:
646
0
    case 0x29:
647
0
    case 0x39:
648
0
    case 0x1a:
649
0
    case 0x2a:
650
0
    case 0x3a:
651
0
    case 0x1b:
652
0
    case 0x2b:
653
0
    case 0x3b:
654
0
      MCInst_setOpcode(MI, HPPA_INS_SHLADD);
655
0
      return;
656
0
    case 0x30:
657
0
    case 0x13:
658
0
    case 0x33:
659
0
    case 0x14:
660
0
    case 0x34:
661
0
      MCInst_setOpcode(MI, HPPA_INS_SUB);
662
0
      return;
663
0
    case 0x22:
664
0
      MCInst_setOpcode(MI, HPPA_INS_CMPCLR);
665
0
      return;
666
0
    case 0x27:
667
0
      MCInst_setOpcode(MI, HPPA_INS_UADDCM);
668
0
      return;
669
0
    case 0x2f:
670
0
      MCInst_setOpcode(MI, HPPA_INS_DCOR);
671
0
      return;
672
0
    case 0x0f:
673
0
    case 0x0d:
674
0
    case 0x0c:
675
0
      MCInst_setOpcode(MI, HPPA_INS_HADD);
676
0
      return;
677
0
    case 0x07:
678
0
    case 0x05:
679
0
    case 0x04:
680
0
      MCInst_setOpcode(MI, HPPA_INS_HSUB);
681
0
      return;
682
0
    case 0x0b:
683
0
      MCInst_setOpcode(MI, HPPA_INS_HAVG);
684
0
      return;
685
0
    case 0x1d:
686
0
    case 0x1e:
687
0
    case 0x1f:
688
0
      MCInst_setOpcode(MI, HPPA_INS_HSHLADD);
689
0
      return;
690
0
    case 0x15:
691
0
    case 0x16:
692
0
    case 0x17:
693
0
      MCInst_setOpcode(MI, HPPA_INS_HSHRADD);
694
0
      return;
695
0
    default:
696
0
      break;
697
0
    }
698
0
  }
699
700
0
  switch (ext) {
701
0
  case 0x18:
702
0
    MCInst_setOpcode(MI, HPPA_INS_ADD);
703
0
    break;
704
0
  case 0x38:
705
0
    MCInst_setOpcode(MI, HPPA_INS_ADDO);
706
0
    break;
707
0
  case 0x1c:
708
0
    MCInst_setOpcode(MI, HPPA_INS_ADDC);
709
0
    break;
710
0
  case 0x3c:
711
0
    MCInst_setOpcode(MI, HPPA_INS_ADDCO);
712
0
    break;
713
0
  case 0x19:
714
0
    MCInst_setOpcode(MI, HPPA_INS_SH1ADD);
715
0
    break;
716
0
  case 0x39:
717
0
    MCInst_setOpcode(MI, HPPA_INS_SH1ADDO);
718
0
    break;
719
0
  case 0x1a:
720
0
    MCInst_setOpcode(MI, HPPA_INS_SH2ADD);
721
0
    break;
722
0
  case 0x3a:
723
0
    MCInst_setOpcode(MI, HPPA_INS_SH2ADDO);
724
0
    break;
725
0
  case 0x1b:
726
0
    MCInst_setOpcode(MI, HPPA_INS_SH3ADD);
727
0
    break;
728
0
  case 0x3b:
729
0
    MCInst_setOpcode(MI, HPPA_INS_SH3ADDO);
730
0
    break;
731
0
  case 0x10:
732
0
    MCInst_setOpcode(MI, HPPA_INS_SUB);
733
0
    break;
734
0
  case 0x30:
735
0
    MCInst_setOpcode(MI, HPPA_INS_SUBO);
736
0
    break;
737
0
  case 0x13:
738
0
    MCInst_setOpcode(MI, HPPA_INS_SUBT);
739
0
    break;
740
0
  case 0x33:
741
0
    MCInst_setOpcode(MI, HPPA_INS_SUBTO);
742
0
    break;
743
0
  case 0x14:
744
0
    MCInst_setOpcode(MI, HPPA_INS_SUBB);
745
0
    break;
746
0
  case 0x34:
747
0
    MCInst_setOpcode(MI, HPPA_INS_SUBBO);
748
0
    break;
749
0
  case 0x11:
750
0
    MCInst_setOpcode(MI, HPPA_INS_DS);
751
0
    break;
752
0
  case 0x00:
753
0
    MCInst_setOpcode(MI, HPPA_INS_ANDCM);
754
0
    break;
755
0
  case 0x08:
756
0
    MCInst_setOpcode(MI, HPPA_INS_AND);
757
0
    break;
758
0
  case 0x09:
759
0
    MCInst_setOpcode(MI, HPPA_INS_OR);
760
0
    break;
761
0
  case 0x0a:
762
0
    MCInst_setOpcode(MI, HPPA_INS_XOR);
763
0
    break;
764
0
  case 0x0e:
765
0
    MCInst_setOpcode(MI, HPPA_INS_UXOR);
766
0
    break;
767
0
  case 0x22:
768
0
    MCInst_setOpcode(MI, HPPA_INS_COMCLR);
769
0
    break;
770
0
  case 0x26:
771
0
    MCInst_setOpcode(MI, HPPA_INS_UADDCM);
772
0
    break;
773
0
  case 0x27:
774
0
    MCInst_setOpcode(MI, HPPA_INS_UADDCMT);
775
0
    break;
776
0
  case 0x28:
777
0
    MCInst_setOpcode(MI, HPPA_INS_ADDL);
778
0
    break;
779
0
  case 0x29:
780
0
    MCInst_setOpcode(MI, HPPA_INS_SH1ADDL);
781
0
    break;
782
0
  case 0x2a:
783
0
    MCInst_setOpcode(MI, HPPA_INS_SH2ADDL);
784
0
    break;
785
0
  case 0x2b:
786
0
    MCInst_setOpcode(MI, HPPA_INS_SH3ADDL);
787
0
    break;
788
0
  case 0x2e:
789
0
    MCInst_setOpcode(MI, HPPA_INS_DCOR);
790
0
    break;
791
0
  case 0x2f:
792
0
    MCInst_setOpcode(MI, HPPA_INS_IDCOR);
793
0
    break;
794
0
  default:
795
0
    break;
796
0
  }
797
0
}
798
799
static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
800
0
{
801
0
  uint32_t cond = (get_insn_field(insn, 19, 19) << 3) |
802
0
      get_insn_field(insn, 16, 18);
803
0
  uint32_t ext = get_insn_field(insn, 20, 25);
804
0
  if (MODE_IS_HPPA_20(mode)) {
805
0
    uint32_t e1 = get_insn_field(insn, 20, 21);
806
0
    uint32_t e2 = get_insn_bit(insn, 23);
807
0
    uint32_t e3 = get_insn_field(insn, 24, 25);
808
0
    uint32_t d = get_insn_bit(insn, 26);
809
0
    switch (ext) {
810
0
    case 0x18:
811
0
    case 0x28:
812
0
    case 0x38:
813
0
    case 0x1c:
814
0
    case 0x3c:
815
0
      if (e2 == 1) {
816
0
        if (d == 1) {
817
0
          push_str_modifier(hppa_ext, "dc");
818
0
        } else {
819
0
          push_str_modifier(hppa_ext, "c");
820
0
        }
821
0
      }
822
      // fallthrough
823
0
    case 0x19:
824
0
    case 0x29:
825
0
    case 0x39:
826
0
    case 0x1a:
827
0
    case 0x2a:
828
0
    case 0x3a:
829
0
    case 0x1b:
830
0
    case 0x2b:
831
0
    case 0x3b:
832
0
      push_str_modifier(hppa_ext, add_compl_names[e1]);
833
0
      if (d == 1) {
834
0
        push_str_modifier(hppa_ext,
835
0
              add_cond_64_names[cond]);
836
0
      } else {
837
0
        push_str_modifier(hppa_ext,
838
0
              add_cond_names[cond]);
839
0
      }
840
0
      return;
841
0
    case 0x10:
842
0
    case 0x30:
843
0
    case 0x13:
844
0
    case 0x33:
845
0
    case 0x14:
846
0
    case 0x34:
847
0
      if (e2 == 1) {
848
0
        if (d == 1) {
849
0
          push_str_modifier(hppa_ext, "db");
850
0
        } else {
851
0
          push_str_modifier(hppa_ext, "b");
852
0
        }
853
0
      }
854
0
      if (e1 == 3) {
855
0
        push_str_modifier(hppa_ext, "tsv");
856
0
      }
857
0
      if (e3 == 3) {
858
0
        push_str_modifier(hppa_ext, "tc");
859
0
      }
860
      // fallthrough
861
0
    case 0x22:
862
0
      if (d == 1) {
863
0
        push_str_modifier(hppa_ext,
864
0
              compare_cond_64_names[cond]);
865
0
      } else {
866
0
        push_str_modifier(hppa_ext,
867
0
              compare_cond_names[cond]);
868
0
      }
869
0
      return;
870
0
    case 0x00:
871
0
    case 0x08:
872
0
    case 0x09:
873
0
    case 0x0a:
874
0
      if (d == 1) {
875
0
        push_str_modifier(hppa_ext,
876
0
              logical_cond_64_names[cond]);
877
0
      } else {
878
0
        push_str_modifier(hppa_ext,
879
0
              logical_cond_names[cond]);
880
0
      }
881
0
      return;
882
0
    case 0x27:
883
0
      push_str_modifier(hppa_ext, "tc");
884
0
      goto unit_cond;
885
0
    case 0x2f:
886
0
      push_str_modifier(hppa_ext, "i");
887
      // fallthrough
888
0
    case 0x26:
889
0
    case 0x0e:
890
0
    case 0x2e:
891
0
unit_cond:
892
0
      if (d == 1) {
893
0
        push_str_modifier(hppa_ext,
894
0
              unit_cond_64_names[cond]);
895
0
      } else {
896
0
        push_str_modifier(hppa_ext,
897
0
              unit_cond_names[cond]);
898
0
      }
899
0
      return;
900
0
    case 0x0d:
901
0
    case 0x0c:
902
0
    case 0x05:
903
0
    case 0x04:
904
0
      push_str_modifier(hppa_ext, saturation_names[e3]);
905
0
      return;
906
0
    default:
907
0
      break;
908
0
    }
909
0
  }
910
911
0
  switch (ext) {
912
0
  case 0x18:
913
0
  case 0x38:
914
0
  case 0x1c:
915
0
  case 0x3c:
916
0
  case 0x19:
917
0
  case 0x39:
918
0
  case 0x1a:
919
0
  case 0x3a:
920
0
  case 0x3b:
921
0
  case 0x28:
922
0
  case 0x29:
923
0
  case 0x2a:
924
0
  case 0x2b:
925
0
    push_str_modifier(hppa_ext, add_cond_names[cond]);
926
0
    break;
927
0
  case 0x10:
928
0
  case 0x30:
929
0
  case 0x13:
930
0
  case 0x33:
931
0
  case 0x14:
932
0
  case 0x34:
933
0
  case 0x11:
934
0
  case 0x22:
935
0
    push_str_modifier(hppa_ext, compare_cond_names[cond]);
936
0
    break;
937
0
  case 0x00:
938
0
  case 0x08:
939
0
  case 0x09:
940
0
  case 0x0a:
941
0
    push_str_modifier(hppa_ext, logical_cond_names[cond]);
942
0
    break;
943
0
  case 0x0e:
944
0
  case 0x26:
945
0
  case 0x27:
946
0
  case 0x2e:
947
0
  case 0x2f:
948
0
    push_str_modifier(hppa_ext, unit_cond_names[cond]);
949
0
    break;
950
0
  default:
951
0
    break;
952
0
  }
953
0
}
954
955
static bool decode_alu(const cs_struct *ud, MCInst *MI, uint32_t insn)
956
0
{
957
0
  uint32_t ext = get_insn_field(insn, 20, 25);
958
0
  uint32_t r1 = get_insn_field(insn, 11, 15);
959
0
  uint32_t r2 = get_insn_field(insn, 6, 10);
960
0
  uint32_t t = get_insn_field(insn, 27, 31);
961
0
  if (MODE_IS_HPPA_20(ud->mode)) {
962
0
    switch (ext) {
963
0
    case 0x19:
964
0
    case 0x29:
965
0
    case 0x39:
966
0
    case 0x1a:
967
0
    case 0x2a:
968
0
    case 0x3a:
969
0
    case 0x1b:
970
0
    case 0x2b:
971
0
    case 0x3b:
972
0
    case 0x1d:
973
0
    case 0x1e:
974
0
    case 0x1f:
975
0
    case 0x15:
976
0
    case 0x16:
977
0
    case 0x17:
978
0
    case 0x0f:
979
0
    case 0x0d:
980
0
    case 0x0c:
981
0
    case 0x07:
982
0
    case 0x05:
983
0
    case 0x04:
984
0
    case 0x0b:
985
0
      CREATE_GR_REG(MI, r1);
986
0
      if (ext > 0x10) {
987
0
        MCOperand_CreateImm0(
988
0
          MI, get_insn_field(insn, 24, 25));
989
0
      }
990
0
      CREATE_GR_REG(MI, r2);
991
0
      CREATE_GR_REG(MI, t);
992
0
      goto success;
993
0
    default:
994
0
      break;
995
0
    }
996
0
  }
997
0
  switch (ext) {
998
0
  case 0x18:
999
0
  case 0x38:
1000
0
  case 0x1c:
1001
0
  case 0x3c:
1002
0
  case 0x19:
1003
0
  case 0x39:
1004
0
  case 0x1a:
1005
0
  case 0x3a:
1006
0
  case 0x1b:
1007
0
  case 0x3b:
1008
0
  case 0x10:
1009
0
  case 0x30:
1010
0
  case 0x13:
1011
0
  case 0x33:
1012
0
  case 0x14:
1013
0
  case 0x34:
1014
0
  case 0x11:
1015
0
  case 0x00:
1016
0
  case 0x08:
1017
0
  case 0x09:
1018
0
  case 0x0a:
1019
0
  case 0x0e:
1020
0
  case 0x22:
1021
0
  case 0x26:
1022
0
  case 0x27:
1023
0
  case 0x28:
1024
0
  case 0x29:
1025
0
  case 0x2a:
1026
0
  case 0x2b:
1027
0
    CREATE_GR_REG(MI, r1);
1028
    // fallthrough
1029
0
  case 0x2e:
1030
0
  case 0x2f:
1031
0
    CREATE_GR_REG(MI, r2);
1032
0
    CREATE_GR_REG(MI, t);
1033
0
    break;
1034
0
  default:
1035
0
    return false;
1036
0
  }
1037
0
success:
1038
0
  fill_alu_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode);
1039
0
  return true;
1040
0
}
1041
1042
static void fill_idxmem_insn_name(MCInst *MI, uint32_t insn)
1043
0
{
1044
0
  uint32_t ext = get_insn_field(insn, 22, 25);
1045
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
1046
0
    switch (ext) {
1047
0
    case 0x00:
1048
0
      MCInst_setOpcode(MI, HPPA_INS_LDB);
1049
0
      return;
1050
0
    case 0x01:
1051
0
      MCInst_setOpcode(MI, HPPA_INS_LDH);
1052
0
      return;
1053
0
    case 0x02:
1054
0
      MCInst_setOpcode(MI, HPPA_INS_LDW);
1055
0
      return;
1056
0
    case 0x03:
1057
0
      MCInst_setOpcode(MI, HPPA_INS_LDD);
1058
0
      return;
1059
0
    case 0x04:
1060
0
      MCInst_setOpcode(MI, HPPA_INS_LDDA);
1061
0
      return;
1062
0
    case 0x05:
1063
0
      MCInst_setOpcode(MI, HPPA_INS_LDCD);
1064
0
      return;
1065
0
    case 0x06:
1066
0
      MCInst_setOpcode(MI, HPPA_INS_LDWA);
1067
0
      return;
1068
0
    case 0x07:
1069
0
      MCInst_setOpcode(MI, HPPA_INS_LDCW);
1070
0
      return;
1071
0
    default:
1072
0
      break;
1073
0
    }
1074
0
    if (get_insn_bit(insn, 19) == 1) {
1075
0
      switch (ext) {
1076
0
      case 0x08:
1077
0
        MCInst_setOpcode(MI, HPPA_INS_STB);
1078
0
        return;
1079
0
      case 0x09:
1080
0
        MCInst_setOpcode(MI, HPPA_INS_STH);
1081
0
        return;
1082
0
      case 0x0a:
1083
0
        MCInst_setOpcode(MI, HPPA_INS_STW);
1084
0
        return;
1085
0
      case 0x0b:
1086
0
        MCInst_setOpcode(MI, HPPA_INS_STD);
1087
0
        return;
1088
0
      case 0x0c:
1089
0
        MCInst_setOpcode(MI, HPPA_INS_STBY);
1090
0
        return;
1091
0
      case 0x0d:
1092
0
        MCInst_setOpcode(MI, HPPA_INS_STDBY);
1093
0
        return;
1094
0
      case 0x0e:
1095
0
        MCInst_setOpcode(MI, HPPA_INS_STWA);
1096
0
        return;
1097
0
      case 0x0f:
1098
0
        MCInst_setOpcode(MI, HPPA_INS_STDA);
1099
0
        return;
1100
0
      default:
1101
0
        break;
1102
0
      }
1103
0
    }
1104
0
  }
1105
0
  if (get_insn_bit(insn, 19) == 0) {
1106
0
    switch (ext) {
1107
0
    case 0x00:
1108
0
      MCInst_setOpcode(MI, HPPA_INS_LDBX);
1109
0
      break;
1110
0
    case 0x01:
1111
0
      MCInst_setOpcode(MI, HPPA_INS_LDHX);
1112
0
      break;
1113
0
    case 0x02:
1114
0
      MCInst_setOpcode(MI, HPPA_INS_LDWX);
1115
0
      break;
1116
0
    case 0x07:
1117
0
      MCInst_setOpcode(MI, HPPA_INS_LDCWX);
1118
0
      break;
1119
0
    case 0x06:
1120
0
      MCInst_setOpcode(MI, HPPA_INS_LDWAX);
1121
0
      break;
1122
0
    default:
1123
0
      break;
1124
0
    }
1125
0
  } else {
1126
0
    switch (ext) {
1127
0
    case 0x00:
1128
0
      MCInst_setOpcode(MI, HPPA_INS_LDBS);
1129
0
      break;
1130
0
    case 0x01:
1131
0
      MCInst_setOpcode(MI, HPPA_INS_LDHS);
1132
0
      break;
1133
0
    case 0x02:
1134
0
      MCInst_setOpcode(MI, HPPA_INS_LDWS);
1135
0
      break;
1136
0
    case 0x07:
1137
0
      MCInst_setOpcode(MI, HPPA_INS_LDCWS);
1138
0
      break;
1139
0
    case 0x06:
1140
0
      MCInst_setOpcode(MI, HPPA_INS_LDWAS);
1141
0
      break;
1142
0
    case 0x08:
1143
0
      MCInst_setOpcode(MI, HPPA_INS_STBS);
1144
0
      break;
1145
0
    case 0x09:
1146
0
      MCInst_setOpcode(MI, HPPA_INS_STHS);
1147
0
      break;
1148
0
    case 0x0a:
1149
0
      MCInst_setOpcode(MI, HPPA_INS_STWS);
1150
0
      break;
1151
0
    case 0x0c:
1152
0
      MCInst_setOpcode(MI, HPPA_INS_STBYS);
1153
0
      break;
1154
0
    case 0x0e:
1155
0
      MCInst_setOpcode(MI, HPPA_INS_STWAS);
1156
0
      break;
1157
0
    default:
1158
0
      break;
1159
0
    }
1160
0
  }
1161
0
}
1162
1163
static void fill_idxmem_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode,
1164
           uint32_t im5)
1165
0
{
1166
0
  uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26);
1167
0
  uint32_t cc = get_insn_field(insn, 20, 21);
1168
0
  uint32_t ext = get_insn_field(insn, 22, 25);
1169
0
  if (CMPLT_HAS_MODIFY_BIT(cmplt)) {
1170
0
    hppa_ext->b_writeble = true;
1171
0
  }
1172
0
  if (get_insn_bit(insn, 19) == 0) {
1173
0
    switch (ext) {
1174
0
    case 0x00:
1175
0
    case 0x01:
1176
0
    case 0x02:
1177
0
    case 0x03:
1178
0
    case 0x04:
1179
0
    case 0x06:
1180
0
      push_str_modifier(hppa_ext, index_compl_names[cmplt]);
1181
0
      if (cc == 2) {
1182
0
        push_str_modifier(hppa_ext, "sl");
1183
0
      }
1184
0
      break;
1185
0
    case 0x05:
1186
0
    case 0x07:
1187
0
      push_str_modifier(hppa_ext, index_compl_names[cmplt]);
1188
0
      if (cc == 1) {
1189
0
        push_str_modifier(hppa_ext, "co");
1190
0
      }
1191
0
      break;
1192
0
    default:
1193
0
      break;
1194
0
    }
1195
0
  } else {
1196
0
    switch (ext) {
1197
0
    case 0x00:
1198
0
    case 0x01:
1199
0
    case 0x02:
1200
0
    case 0x03:
1201
0
    case 0x04:
1202
0
    case 0x06:
1203
0
      if (cmplt == 1 && im5 == 0) {
1204
0
        push_str_modifier(hppa_ext, "o");
1205
0
      } else {
1206
0
        push_str_modifier(
1207
0
          hppa_ext,
1208
0
          short_ldst_compl_names[cmplt]);
1209
0
      }
1210
0
      if (cc == 2) {
1211
0
        push_str_modifier(hppa_ext, "sl");
1212
0
      }
1213
0
      break;
1214
0
    case 0x05:
1215
0
    case 0x07:
1216
0
      if (cmplt == 1 && im5 == 0) {
1217
0
        push_str_modifier(hppa_ext, "o");
1218
0
      } else {
1219
0
        push_str_modifier(
1220
0
          hppa_ext,
1221
0
          short_ldst_compl_names[cmplt]);
1222
0
      }
1223
0
      if (cc == 1) {
1224
0
        push_str_modifier(hppa_ext, "co");
1225
0
      }
1226
0
      break;
1227
0
    case 0x08:
1228
0
    case 0x09:
1229
0
    case 0x0a:
1230
0
    case 0x0b:
1231
0
    case 0x0e:
1232
0
    case 0x0f:
1233
0
      if (cmplt == 1 && im5 == 0) {
1234
0
        push_str_modifier(hppa_ext, "o");
1235
0
      } else {
1236
0
        push_str_modifier(
1237
0
          hppa_ext,
1238
0
          short_ldst_compl_names[cmplt]);
1239
0
      }
1240
0
      if (cc == 1) {
1241
0
        push_str_modifier(hppa_ext, "bc");
1242
0
      } else if (cc == 2) {
1243
0
        push_str_modifier(hppa_ext, "sl");
1244
0
      }
1245
0
      break;
1246
0
    case 0x0c:
1247
0
    case 0x0d:
1248
0
      push_str_modifier(hppa_ext,
1249
0
            short_bytes_compl_names[cmplt]);
1250
0
      if (cc == 1) {
1251
0
        push_str_modifier(hppa_ext, "bc");
1252
0
      } else if (cc == 2) {
1253
0
        push_str_modifier(hppa_ext, "sl");
1254
0
      }
1255
0
      break;
1256
0
    default:
1257
0
      break;
1258
0
    }
1259
0
  }
1260
0
}
1261
1262
static bool decode_idxmem(const cs_struct *ud, MCInst *MI, uint32_t insn)
1263
0
{
1264
0
  uint32_t ext = get_insn_field(insn, 22, 25);
1265
0
  uint32_t im5;
1266
0
  uint32_t r = get_insn_field(insn, 11, 15);
1267
0
  uint32_t b = get_insn_field(insn, 6, 10);
1268
0
  uint32_t t = get_insn_field(insn, 27, 31);
1269
0
  uint32_t s = get_insn_field(insn, 16, 17);
1270
0
  if (MODE_IS_HPPA_20(ud->mode)) {
1271
0
    if (get_insn_bit(insn, 19) == 0) {
1272
0
      switch (ext) {
1273
0
      case 0x03:
1274
0
      case 0x05:
1275
0
      case 0x04:
1276
0
        CREATE_GR_REG(MI, r);
1277
0
        if (ext != 0x04) {
1278
0
          CREATE_SR_REG(MI, s);
1279
0
        }
1280
0
        CREATE_GR_REG(MI, b);
1281
0
        CREATE_GR_REG(MI, t);
1282
0
        fill_idxmem_mods(insn, HPPA_EXT_REF(MI),
1283
0
             ud->mode, -1);
1284
0
        return true;
1285
0
      default:
1286
0
        break;
1287
0
      }
1288
0
    } else {
1289
0
      switch (ext) {
1290
0
      case 0x03:
1291
0
      case 0x05:
1292
0
      case 0x04:
1293
0
        im5 = extract_5_load(insn);
1294
0
        MCOperand_CreateImm0(MI, im5);
1295
0
        if (ext != 0x04) {
1296
0
          CREATE_SR_REG(MI, s);
1297
0
        }
1298
0
        CREATE_GR_REG(MI, b);
1299
0
        CREATE_GR_REG(MI, t);
1300
0
        fill_idxmem_mods(insn, HPPA_EXT_REF(MI),
1301
0
             ud->mode, im5);
1302
0
        return true;
1303
0
      case 0x0b:
1304
0
      case 0x0d:
1305
0
      case 0x0f:
1306
0
        im5 = extract_5_store(insn);
1307
0
        CREATE_GR_REG(MI, r);
1308
0
        MCOperand_CreateImm0(MI, im5);
1309
0
        if (ext != 0x0f) {
1310
0
          CREATE_SR_REG(MI, s);
1311
0
        }
1312
0
        CREATE_GR_REG(MI, b);
1313
0
        fill_idxmem_mods(insn, HPPA_EXT_REF(MI),
1314
0
             ud->mode, im5);
1315
0
        return true;
1316
0
      default:
1317
0
        break;
1318
0
      }
1319
0
    }
1320
0
  }
1321
0
  if (get_insn_bit(insn, 19) == 0) {
1322
0
    switch (ext) {
1323
0
    case 0x00:
1324
0
    case 0x01:
1325
0
    case 0x02:
1326
0
    case 0x07:
1327
0
    case 0x06:
1328
0
      CREATE_GR_REG(MI, r);
1329
0
      if (ext != 0x06) {
1330
0
        CREATE_SR_REG(MI, s);
1331
0
      }
1332
0
      CREATE_GR_REG(MI, b);
1333
0
      CREATE_GR_REG(MI, t);
1334
0
      break;
1335
0
    default:
1336
0
      return false;
1337
0
    }
1338
0
    fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1);
1339
0
    return true;
1340
0
  } else {
1341
0
    switch (ext) {
1342
0
    case 0x00:
1343
0
    case 0x01:
1344
0
    case 0x02:
1345
0
    case 0x07:
1346
0
    case 0x06:
1347
0
      im5 = extract_5_load(insn);
1348
0
      MCOperand_CreateImm0(MI, im5);
1349
0
      if (ext != 0x06) {
1350
0
        CREATE_SR_REG(MI, s);
1351
0
      }
1352
0
      CREATE_GR_REG(MI, b);
1353
0
      CREATE_GR_REG(MI, t);
1354
0
      break;
1355
0
    case 0x08:
1356
0
    case 0x09:
1357
0
    case 0x0a:
1358
0
    case 0x0c:
1359
0
    case 0x0e:
1360
0
      im5 = extract_5_store(insn);
1361
0
      CREATE_GR_REG(MI, r);
1362
0
      MCOperand_CreateImm0(MI, im5);
1363
0
      if (ext != 0x0e) {
1364
0
        CREATE_SR_REG(MI, s);
1365
0
      }
1366
0
      CREATE_GR_REG(MI, b);
1367
0
      break;
1368
0
    default:
1369
0
      return false;
1370
0
    }
1371
0
    if (MODE_IS_HPPA_20(ud->mode)) {
1372
0
      fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, im5);
1373
0
    } else {
1374
0
      fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1);
1375
0
    }
1376
0
    return true;
1377
0
  }
1378
0
}
1379
1380
static void fill_ldst_dw_insn_name(MCInst *MI, uint32_t insn)
1381
0
{
1382
0
  uint32_t opcode = insn >> 26;
1383
0
  uint32_t ext = get_insn_bit(insn, 30);
1384
0
  if (opcode == 0x14) {
1385
0
    if (ext == 0) {
1386
0
      MCInst_setOpcode(MI, HPPA_INS_LDD);
1387
0
    } else {
1388
0
      MCInst_setOpcode(MI, HPPA_INS_FLDD);
1389
0
    }
1390
0
  } else {
1391
0
    if (ext == 0) {
1392
0
      MCInst_setOpcode(MI, HPPA_INS_STD);
1393
0
    } else {
1394
0
      MCInst_setOpcode(MI, HPPA_INS_FSTD);
1395
0
    }
1396
0
  }
1397
0
}
1398
1399
static void fill_ldst_dw_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im)
1400
0
{
1401
0
  uint32_t cmplt = (get_insn_bit(insn, 29) << 1) | get_insn_bit(insn, 28);
1402
0
  if (cmplt == 1 && im == 0) {
1403
0
    push_str_modifier(hppa_ext, "o");
1404
0
  } else {
1405
0
    push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]);
1406
0
  }
1407
0
}
1408
1409
static bool decode_ldst_dw(const cs_struct *ud, MCInst *MI, uint32_t insn)
1410
0
{
1411
0
  uint32_t opcode = insn >> 26;
1412
0
  uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode));
1413
0
  im &= ~7;
1414
0
  uint32_t ext = get_insn_bit(insn, 30);
1415
0
  uint32_t r = get_insn_field(insn, 11, 15);
1416
0
  uint32_t b = get_insn_field(insn, 6, 10);
1417
0
  uint32_t s = get_insn_field(insn, 16, 17);
1418
0
  if (opcode == HPPA_OP_TYPE_LOADDW) {
1419
0
    MCOperand_CreateImm0(MI, im);
1420
0
    CREATE_SR_REG(MI, s);
1421
0
    CREATE_GR_REG(MI, b);
1422
0
    if (ext == 0) {
1423
0
      CREATE_GR_REG(MI, r);
1424
0
    } else {
1425
0
      CREATE_FPR_REG(MI, r);
1426
0
    }
1427
0
  } else {
1428
0
    if (ext == 0) {
1429
0
      CREATE_GR_REG(MI, r);
1430
0
    } else {
1431
0
      CREATE_FPR_REG(MI, r);
1432
0
    }
1433
0
    MCOperand_CreateImm0(MI, im);
1434
0
    CREATE_SR_REG(MI, s);
1435
0
    CREATE_GR_REG(MI, b);
1436
0
  }
1437
0
  fill_ldst_dw_mods(insn, HPPA_EXT_REF(MI), im);
1438
0
  return true;
1439
0
}
1440
1441
static void fill_ldst_w_insn_name(MCInst *MI, uint32_t insn)
1442
0
{
1443
0
  uint32_t opcode = insn >> 26;
1444
0
  uint32_t ext = get_insn_bit(insn, 29);
1445
0
  if (opcode == 0x17) {
1446
0
    if (ext == 0) {
1447
0
      MCInst_setOpcode(MI, HPPA_INS_FLDW);
1448
0
    } else {
1449
0
      MCInst_setOpcode(MI, HPPA_INS_LDW);
1450
0
    }
1451
0
  } else {
1452
0
    if (ext == 0) {
1453
0
      MCInst_setOpcode(MI, HPPA_INS_FSTW);
1454
0
    } else {
1455
0
      MCInst_setOpcode(MI, HPPA_INS_STW);
1456
0
    }
1457
0
  }
1458
0
}
1459
1460
static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, int32_t im)
1461
0
{
1462
0
  if (im >= 0) {
1463
0
    push_str_modifier(hppa_ext, "mb");
1464
0
  } else {
1465
0
    push_str_modifier(hppa_ext, "ma");
1466
0
  }
1467
0
}
1468
1469
static bool decode_ldst_w(const cs_struct *ud, MCInst *MI, uint32_t insn)
1470
0
{
1471
0
  uint32_t opcode = insn >> 26;
1472
0
  uint32_t ext = get_insn_bit(insn, 29);
1473
0
  int32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode));
1474
0
  im &= ~3;
1475
0
  uint32_t r = get_insn_field(insn, 11, 15);
1476
0
  uint32_t b = get_insn_field(insn, 6, 10);
1477
0
  uint32_t s = get_insn_field(insn, 16, 17);
1478
0
  if (opcode == 0x17) {
1479
0
    MCOperand_CreateImm0(MI, im);
1480
0
    CREATE_SR_REG(MI, s);
1481
0
    CREATE_GR_REG(MI, b);
1482
0
    if (ext == 1) {
1483
0
      CREATE_GR_REG(MI, r);
1484
0
    } else {
1485
0
      CREATE_FPR_REG(MI, r);
1486
0
    }
1487
0
  } else {
1488
0
    if (ext == 1) {
1489
0
      CREATE_GR_REG(MI, r);
1490
0
    } else {
1491
0
      CREATE_FPR_REG(MI, r);
1492
0
    }
1493
0
    MCOperand_CreateImm0(MI, im);
1494
0
    CREATE_SR_REG(MI, s);
1495
0
    CREATE_GR_REG(MI, b);
1496
0
  }
1497
0
  if (ext == 1) {
1498
0
    fill_ldst_w_mods(insn, HPPA_EXT_REF(MI), im);
1499
0
  }
1500
0
  return true;
1501
0
}
1502
1503
static void fill_arith_imm_insn_name(MCInst *MI, uint32_t insn)
1504
0
{
1505
0
  uint32_t opcode = insn >> 26;
1506
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
1507
0
    switch (opcode) {
1508
0
    case 0x2d:
1509
0
    case 0x2c:
1510
0
      MCInst_setOpcode(MI, HPPA_INS_ADDI);
1511
0
      return;
1512
0
    case 0x25:
1513
0
      MCInst_setOpcode(MI, HPPA_INS_SUBI);
1514
0
      return;
1515
0
    default:
1516
0
      break;
1517
0
    }
1518
0
  }
1519
0
  if (get_insn_bit(insn, 20) == 0) {
1520
0
    switch (opcode) {
1521
0
    case 0x2d:
1522
0
      MCInst_setOpcode(MI, HPPA_INS_ADDI);
1523
0
      break;
1524
0
    case 0x2c:
1525
0
      MCInst_setOpcode(MI, HPPA_INS_ADDIT);
1526
0
      break;
1527
0
    case 0x25:
1528
0
      MCInst_setOpcode(MI, HPPA_INS_SUBI);
1529
0
      break;
1530
0
    default:
1531
0
      break;
1532
0
    }
1533
0
  } else {
1534
0
    switch (opcode) {
1535
0
    case 0x2d:
1536
0
      MCInst_setOpcode(MI, HPPA_INS_ADDIO);
1537
0
      break;
1538
0
    case 0x2c:
1539
0
      MCInst_setOpcode(MI, HPPA_INS_ADDITO);
1540
0
      break;
1541
0
    case 0x25:
1542
0
      MCInst_setOpcode(MI, HPPA_INS_SUBIO);
1543
0
      break;
1544
0
    default:
1545
0
      break;
1546
0
    }
1547
0
  }
1548
0
}
1549
1550
static void fill_arith_imm_insn_mods(uint32_t insn, hppa_ext *hppa_ext,
1551
             cs_mode mode)
1552
0
{
1553
0
  uint32_t opcode = insn >> 26;
1554
0
  uint32_t cond = (get_insn_bit(insn, 19) << 3) |
1555
0
      get_insn_field(insn, 16, 18);
1556
0
  uint32_t cmplt = get_insn_bit(insn, 20);
1557
0
  if (MODE_IS_HPPA_20(mode)) {
1558
0
    if (cmplt == 1) {
1559
0
      push_str_modifier(hppa_ext, "tsv");
1560
0
    }
1561
0
    if (opcode == 0x2c) {
1562
0
      push_str_modifier(hppa_ext, "tc");
1563
0
    }
1564
0
  }
1565
0
  switch (opcode) {
1566
0
  case 0x2d:
1567
0
  case 0x2c:
1568
0
    push_str_modifier(hppa_ext, add_cond_names[cond]);
1569
0
    break;
1570
0
  case 0x25:
1571
0
    push_str_modifier(hppa_ext, compare_cond_names[cond]);
1572
0
    break;
1573
0
  default:
1574
0
    break;
1575
0
  }
1576
0
}
1577
1578
static bool decode_arith_imm(const cs_struct *ud, MCInst *MI, uint32_t insn)
1579
0
{
1580
0
  MCOperand_CreateImm0(MI, extract_11(insn));
1581
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
1582
0
  CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
1583
0
  fill_arith_imm_insn_mods(insn, HPPA_EXT_REF(MI), ud->mode);
1584
0
  return true;
1585
0
}
1586
1587
static void fill_shexdep0_insn_name(MCInst *MI, uint32_t insn)
1588
0
{
1589
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1590
0
  uint32_t d = get_insn_bit(insn, 22);
1591
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
1592
0
    switch (ext) {
1593
0
    case 0x01:
1594
0
    case 0x03:
1595
0
      MCInst_setOpcode(MI, HPPA_INS_SHRPD);
1596
0
      return;
1597
0
    case 0x02:
1598
0
      MCInst_setOpcode(MI, HPPA_INS_SHRPW);
1599
0
      return;
1600
0
    case 0x06:
1601
0
    case 0x07:
1602
0
      MCInst_setOpcode(MI, HPPA_INS_EXTRW);
1603
0
      return;
1604
0
    case 0x00:
1605
0
      if (d == 0) {
1606
0
        MCInst_setOpcode(MI, HPPA_INS_SHRPW);
1607
0
      } else {
1608
0
        MCInst_setOpcode(MI, HPPA_INS_SHRPD);
1609
0
      }
1610
0
      return;
1611
0
    case 0x04:
1612
0
    case 0x05:
1613
0
      if (d == 0) {
1614
0
        MCInst_setOpcode(MI, HPPA_INS_EXTRW);
1615
0
      } else {
1616
0
        MCInst_setOpcode(MI, HPPA_INS_EXTRD);
1617
0
      }
1618
0
      return;
1619
0
    default:
1620
0
      break;
1621
0
    }
1622
0
  }
1623
0
  switch (ext) {
1624
0
  case 0x00:
1625
0
    MCInst_setOpcode(MI, HPPA_INS_VSHD);
1626
0
    break;
1627
0
  case 0x02:
1628
0
    MCInst_setOpcode(MI, HPPA_INS_SHD);
1629
0
    break;
1630
0
  case 0x04:
1631
0
    MCInst_setOpcode(MI, HPPA_INS_VEXTRU);
1632
0
    break;
1633
0
  case 0x05:
1634
0
    MCInst_setOpcode(MI, HPPA_INS_VEXTRS);
1635
0
    break;
1636
0
  case 0x06:
1637
0
    MCInst_setOpcode(MI, HPPA_INS_EXTRU);
1638
0
    break;
1639
0
  case 0x07:
1640
0
    MCInst_setOpcode(MI, HPPA_INS_EXTRS);
1641
0
    break;
1642
0
  default:
1643
0
    break;
1644
0
  }
1645
0
}
1646
1647
static void fill_shexdep0_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
1648
0
{
1649
0
  uint32_t cond = get_insn_field(insn, 16, 18);
1650
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1651
0
  uint32_t d = get_insn_bit(insn, 22);
1652
1653
0
  if (ext >= 0x04 && MODE_IS_HPPA_20(mode)) {
1654
0
    push_str_modifier(hppa_ext, signed_unsigned_names[ext & 1]);
1655
0
  }
1656
1657
0
  if (MODE_IS_HPPA_20(mode)) {
1658
0
    switch (ext) {
1659
0
    case 0x00:
1660
0
    case 0x04:
1661
0
    case 0x05:
1662
0
      if (d == 0) {
1663
0
        break;
1664
0
      }
1665
      // fallthrough
1666
0
    case 0x01:
1667
0
    case 0x03:
1668
0
      push_str_modifier(hppa_ext, shift_cond_64_names[cond]);
1669
0
      return;
1670
0
    default:
1671
0
      break;
1672
0
    }
1673
0
  }
1674
0
  push_str_modifier(hppa_ext, shift_cond_names[cond]);
1675
0
}
1676
1677
static bool decode_shexdep0(const cs_struct *ud, MCInst *MI, uint32_t insn)
1678
0
{
1679
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1680
0
  uint32_t cp = get_insn_bit(insn, 20);
1681
0
  uint32_t cpos = get_insn_field(insn, 22, 26);
1682
0
  uint32_t sa = 63 - ((cp << 5) | cpos);
1683
0
  uint32_t r1 = get_insn_field(insn, 11, 15);
1684
0
  uint32_t r2 = get_insn_field(insn, 6, 10);
1685
0
  uint32_t clen_t = get_insn_field(insn, 27, 31);
1686
0
  if (MODE_IS_HPPA_20(ud->mode)) {
1687
0
    switch (ext) {
1688
0
    case 0x01:
1689
0
    case 0x00:
1690
0
    case 0x03:
1691
0
    case 0x02:
1692
0
      CREATE_GR_REG(MI, r1);
1693
0
      CREATE_GR_REG(MI, r2);
1694
0
      if (ext <= 0x01) {
1695
0
        CREATE_CR_REG(MI, 11);
1696
0
        HPPA_EXT_REF(MI)->is_alternative = true;
1697
0
      } else {
1698
0
        MCOperand_CreateImm0(MI, sa);
1699
0
      }
1700
0
      CREATE_GR_REG(MI, clen_t);
1701
0
      break;
1702
0
    case 0x06:
1703
0
    case 0x07:
1704
0
    case 0x04:
1705
0
    case 0x05:
1706
0
      CREATE_GR_REG(MI, r2);
1707
0
      if (ext >= 0x06) {
1708
0
        MCOperand_CreateImm0(MI, cpos);
1709
0
      } else {
1710
0
        CREATE_CR_REG(MI, 11);
1711
0
        HPPA_EXT_REF(MI)->is_alternative = true;
1712
0
      }
1713
0
      MCOperand_CreateImm0(MI, 32 - clen_t);
1714
0
      CREATE_GR_REG(MI, r1);
1715
0
      break;
1716
0
    default:
1717
0
      return false;
1718
0
    }
1719
0
  } else {
1720
0
    switch (ext) {
1721
0
    case 0x00:
1722
0
    case 0x02:
1723
0
      CREATE_GR_REG(MI, r1);
1724
0
      CREATE_GR_REG(MI, r2);
1725
0
      if (ext == 0x02) {
1726
0
        MCOperand_CreateImm0(MI, 31 - cpos);
1727
0
      }
1728
0
      CREATE_GR_REG(MI, clen_t);
1729
0
      break;
1730
0
    case 0x04:
1731
0
    case 0x05:
1732
0
    case 0x06:
1733
0
    case 0x07:
1734
0
      CREATE_GR_REG(MI, r2);
1735
0
      if (ext >= 0x06) {
1736
0
        MCOperand_CreateImm0(MI, cpos);
1737
0
      }
1738
0
      MCOperand_CreateImm0(MI, 32 - clen_t);
1739
0
      CREATE_GR_REG(MI, r1);
1740
0
      break;
1741
0
    default:
1742
0
      return false;
1743
0
    }
1744
0
  }
1745
0
  fill_shexdep0_mods(insn, HPPA_EXT_REF(MI), ud->mode);
1746
0
  return true;
1747
0
}
1748
1749
static void fill_shexdep1_insn_name(MCInst *MI, uint32_t insn)
1750
0
{
1751
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1752
0
  uint32_t d = get_insn_bit(insn, 22);
1753
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
1754
0
    switch (ext) {
1755
0
    case 0x02:
1756
0
    case 0x03:
1757
0
      MCInst_setOpcode(MI, HPPA_INS_DEPW);
1758
0
      break;
1759
0
    case 0x06:
1760
0
    case 0x07:
1761
0
      MCInst_setOpcode(MI, HPPA_INS_DEPWI);
1762
0
      break;
1763
0
    case 0x00:
1764
0
    case 0x01:
1765
0
      if (d == 0) {
1766
0
        MCInst_setOpcode(MI, HPPA_INS_DEPW);
1767
0
      } else {
1768
0
        MCInst_setOpcode(MI, HPPA_INS_DEPD);
1769
0
      }
1770
0
      break;
1771
0
    case 0x04:
1772
0
    case 0x05:
1773
0
      if (d == 0) {
1774
0
        MCInst_setOpcode(MI, HPPA_INS_DEPWI);
1775
0
      } else {
1776
0
        MCInst_setOpcode(MI, HPPA_INS_DEPDI);
1777
0
      }
1778
0
      break;
1779
0
    default:
1780
0
      break;
1781
0
    }
1782
0
  } else {
1783
0
    switch (ext) {
1784
0
    case 0x00:
1785
0
      MCInst_setOpcode(MI, HPPA_INS_ZVDEP);
1786
0
      break;
1787
0
    case 0x01:
1788
0
      MCInst_setOpcode(MI, HPPA_INS_VDEP);
1789
0
      break;
1790
0
    case 0x02:
1791
0
      MCInst_setOpcode(MI, HPPA_INS_ZDEP);
1792
0
      break;
1793
0
    case 0x03:
1794
0
      MCInst_setOpcode(MI, HPPA_INS_DEP);
1795
0
      break;
1796
0
    case 0x04:
1797
0
      MCInst_setOpcode(MI, HPPA_INS_ZVDEPI);
1798
0
      break;
1799
0
    case 0x05:
1800
0
      MCInst_setOpcode(MI, HPPA_INS_VDEPI);
1801
0
      break;
1802
0
    case 0x06:
1803
0
      MCInst_setOpcode(MI, HPPA_INS_ZDEPI);
1804
0
      break;
1805
0
    case 0x07:
1806
0
      MCInst_setOpcode(MI, HPPA_INS_DEPI);
1807
0
      break;
1808
0
    default:
1809
0
      break;
1810
0
    }
1811
0
  }
1812
0
}
1813
1814
static void fill_shexdep1_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
1815
0
{
1816
0
  uint32_t cond = get_insn_field(insn, 16, 18);
1817
0
  uint32_t cmplt = get_insn_bit(insn, 21);
1818
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1819
0
  if (MODE_IS_HPPA_20(mode)) {
1820
0
    if (cmplt == 0) {
1821
0
      push_str_modifier(hppa_ext, "z");
1822
0
    }
1823
0
    switch (ext) {
1824
0
    case 0x00:
1825
0
    case 0x01:
1826
0
    case 0x04:
1827
0
    case 0x05:
1828
0
      push_str_modifier(hppa_ext, shift_cond_64_names[cond]);
1829
0
      return;
1830
0
    default:
1831
0
      break;
1832
0
    }
1833
0
  }
1834
0
  push_str_modifier(hppa_ext, shift_cond_names[cond]);
1835
0
}
1836
1837
static bool decode_shexdep1(const cs_struct *ud, MCInst *MI, uint32_t insn)
1838
0
{
1839
0
  uint32_t ext = get_insn_field(insn, 19, 21);
1840
0
  uint32_t cl = get_insn_bit(insn, 23);
1841
0
  uint32_t clen = get_insn_field(insn, 27, 31);
1842
0
  uint32_t len = (cl + 1) * 32 - clen;
1843
0
  uint32_t r = get_insn_field(insn, 11, 15);
1844
0
  uint32_t t = get_insn_field(insn, 6, 10);
1845
0
  uint32_t cpos = get_insn_field(insn, 22, 26);
1846
0
  if (MODE_IS_HPPA_20(ud->mode)) {
1847
0
    switch (ext) {
1848
0
    case 0x02:
1849
0
    case 0x03:
1850
0
    case 0x06:
1851
0
    case 0x07:
1852
0
      if (ext >= 0x06) {
1853
0
        MCOperand_CreateImm0(MI, LowSignExtend64(r, 5));
1854
0
      } else {
1855
0
        CREATE_GR_REG(MI, r);
1856
0
      }
1857
0
      MCOperand_CreateImm0(MI, 31 - cpos);
1858
0
      MCOperand_CreateImm0(MI, 32 - clen);
1859
0
      CREATE_GR_REG(MI, t);
1860
0
      break;
1861
0
    case 0x00:
1862
0
    case 0x01:
1863
0
    case 0x04:
1864
0
    case 0x05:
1865
0
      if (ext >= 0x04) {
1866
0
        MCOperand_CreateImm0(MI, LowSignExtend64(r, 5));
1867
0
      } else {
1868
0
        CREATE_GR_REG(MI, r);
1869
0
      }
1870
0
      CREATE_CR_REG(MI, 11);
1871
0
      HPPA_EXT_REF(MI)->is_alternative = true;
1872
0
      MCOperand_CreateImm0(MI, len);
1873
0
      CREATE_GR_REG(MI, t);
1874
0
      break;
1875
0
    default:
1876
0
      break;
1877
0
    }
1878
0
  } else {
1879
0
    switch (ext) {
1880
0
    case 0x00:
1881
0
    case 0x01:
1882
0
    case 0x02:
1883
0
    case 0x03:
1884
0
      CREATE_GR_REG(MI, r);
1885
0
      if (ext >= 0x02) {
1886
0
        MCOperand_CreateImm0(MI, 31 - cpos);
1887
0
      }
1888
0
      MCOperand_CreateImm0(MI, 32 - clen);
1889
0
      CREATE_GR_REG(MI, t);
1890
0
      break;
1891
0
    case 0x04:
1892
0
    case 0x05:
1893
0
    case 0x06:
1894
0
    case 0x07:
1895
0
      MCOperand_CreateImm0(MI, LowSignExtend64(r, 5));
1896
0
      if (ext >= 0x06) {
1897
0
        MCOperand_CreateImm0(MI, 31 - cpos);
1898
0
      }
1899
0
      MCOperand_CreateImm0(MI, 32 - clen);
1900
0
      CREATE_GR_REG(MI, t);
1901
0
      break;
1902
0
    default:
1903
0
      break;
1904
0
    }
1905
0
  }
1906
0
  fill_shexdep1_mods(insn, HPPA_EXT_REF(MI), ud->mode);
1907
0
  return true;
1908
0
}
1909
1910
static void fill_shexdep2_mods(uint32_t insn, hppa_ext *hppa_ext)
1911
0
{
1912
0
  uint32_t cmplt = get_insn_bit(insn, 21);
1913
0
  uint32_t cond = get_insn_field(insn, 16, 18);
1914
0
  push_str_modifier(hppa_ext, signed_unsigned_names[cmplt]);
1915
0
  push_str_modifier(hppa_ext, shift_cond_64_names[cond]);
1916
0
}
1917
1918
static bool decode_shexdep2(MCInst *MI, uint32_t insn)
1919
0
{
1920
0
  uint32_t pos = (get_insn_bit(insn, 20) << 5) |
1921
0
           get_insn_field(insn, 22, 26);
1922
0
  uint32_t cl = get_insn_bit(insn, 19);
1923
0
  uint32_t clen = get_insn_field(insn, 27, 31);
1924
0
  uint32_t len = (cl + 1) * 32 - clen;
1925
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
1926
0
  MCOperand_CreateImm0(MI, pos);
1927
0
  MCOperand_CreateImm0(MI, len);
1928
0
  CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
1929
0
  fill_shexdep2_mods(insn, HPPA_EXT_REF(MI));
1930
0
  return true;
1931
0
}
1932
1933
static void fill_shexdep3_mods(uint32_t insn, hppa_ext *hppa_ext)
1934
0
{
1935
0
  uint32_t cmplt = get_insn_bit(insn, 21);
1936
0
  uint32_t cond = get_insn_field(insn, 16, 18);
1937
0
  if (cmplt == 0) {
1938
0
    push_str_modifier(hppa_ext, "z");
1939
0
  }
1940
0
  push_str_modifier(hppa_ext, shift_cond_64_names[cond]);
1941
0
}
1942
1943
static bool decode_shexdep3(const cs_struct *ud, MCInst *MI, uint32_t insn)
1944
0
{
1945
0
  uint32_t opcode = insn >> 26;
1946
0
  if (opcode == HPPA_OP_TYPE_SHEXDEP3) {
1947
0
    MCInst_setOpcode(MI, HPPA_INS_DEPD);
1948
0
  } else {
1949
0
    MCInst_setOpcode(MI, HPPA_INS_DEPDI);
1950
0
  }
1951
0
  uint32_t pos = 63 - ((get_insn_bit(insn, 20) << 5) |
1952
0
           get_insn_field(insn, 22, 26));
1953
0
  uint32_t cl = get_insn_bit(insn, 19);
1954
0
  uint32_t clen = get_insn_field(insn, 27, 31);
1955
0
  uint32_t len = (cl + 1) * 32 - clen;
1956
0
  if (opcode == HPPA_OP_TYPE_SHEXDEP3) {
1957
0
    CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
1958
0
  } else {
1959
0
    MCOperand_CreateImm0(
1960
0
      MI, LowSignExtend64(get_insn_field(insn, 11, 15), 5));
1961
0
  }
1962
0
  MCOperand_CreateImm0(MI, pos);
1963
0
  MCOperand_CreateImm0(MI, len);
1964
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
1965
0
  fill_shexdep3_mods(insn, HPPA_EXT_REF(MI));
1966
0
  return true;
1967
0
}
1968
1969
static void fill_multmed_insn_name(MCInst *MI, uint32_t insn)
1970
0
{
1971
0
  uint32_t bit_16 = get_insn_bit(insn, 16);
1972
0
  uint32_t ext = (get_insn_field(insn, 17, 18) << 2) |
1973
0
           get_insn_field(insn, 20, 21);
1974
0
  if (bit_16 == 0) {
1975
0
    MCInst_setOpcode(MI, HPPA_INS_PERMH);
1976
0
    return;
1977
0
  }
1978
0
  switch (ext) {
1979
0
  case 0x02:
1980
0
    MCInst_setOpcode(MI, HPPA_INS_HSHL);
1981
0
    break;
1982
0
  case 0x0a:
1983
0
  case 0x0b:
1984
0
    MCInst_setOpcode(MI, HPPA_INS_HSHR);
1985
0
    break;
1986
0
  case 0x00:
1987
0
  case 0x08:
1988
0
    MCInst_setOpcode(MI, HPPA_INS_MIXW);
1989
0
    break;
1990
0
  case 0x01:
1991
0
  case 0x09:
1992
0
    MCInst_setOpcode(MI, HPPA_INS_MIXH);
1993
0
    break;
1994
0
  default:
1995
0
    break;
1996
0
  }
1997
0
}
1998
1999
static void fill_multmed_mods(uint32_t insn, hppa_ext *hppa_ext)
2000
0
{
2001
0
  uint32_t bit_16 = get_insn_bit(insn, 16);
2002
0
  uint32_t ext = (get_insn_field(insn, 17, 18) << 2) |
2003
0
           get_insn_field(insn, 20, 21);
2004
0
  uint32_t eb = get_insn_field(insn, 20, 21);
2005
0
  uint32_t ea = get_insn_field(insn, 17, 18);
2006
0
  if (bit_16 == 0) {
2007
0
    char c[5];
2008
0
    snprintf(c, sizeof(c), "%d%d%d%d", get_insn_field(insn, 17, 18),
2009
0
       get_insn_field(insn, 20, 21),
2010
0
       get_insn_field(insn, 22, 23),
2011
0
       get_insn_field(insn, 24, 25));
2012
0
    push_str_modifier(hppa_ext, c);
2013
0
    return;
2014
0
  }
2015
0
  switch (ext) {
2016
0
  case 0x0a:
2017
0
  case 0x0b:
2018
0
    if (eb >= 2) {
2019
0
      push_str_modifier(hppa_ext,
2020
0
            signed_unsigned_names[eb - 2]);
2021
0
    }
2022
0
    break;
2023
0
  case 0x00:
2024
0
  case 0x08:
2025
0
  case 0x01:
2026
0
  case 0x09:
2027
0
    if (ea == 2) {
2028
0
      push_str_modifier(hppa_ext, "l");
2029
0
    } else if (ea == 0) {
2030
0
      push_str_modifier(hppa_ext, "r");
2031
0
    }
2032
0
    break;
2033
0
  default:
2034
0
    break;
2035
0
  }
2036
0
}
2037
2038
static bool decode_multmed(MCInst *MI, uint32_t insn)
2039
0
{
2040
0
  uint32_t bit_16 = get_insn_bit(insn, 16);
2041
0
  uint32_t ext = (get_insn_field(insn, 17, 18) << 2) |
2042
0
           get_insn_field(insn, 20, 21);
2043
0
  uint32_t r1 = get_insn_field(insn, 11, 15);
2044
0
  uint32_t r2 = get_insn_field(insn, 6, 10);
2045
0
  uint32_t t = get_insn_field(insn, 27, 31);
2046
0
  uint32_t sa = get_insn_field(insn, 22, 25);
2047
0
  if (bit_16 == 0) {
2048
0
    CREATE_GR_REG(MI, r2);
2049
0
    CREATE_GR_REG(MI, t);
2050
0
    goto success;
2051
0
  }
2052
0
  switch (ext) {
2053
0
  case 0x02:
2054
0
  case 0x0a:
2055
0
  case 0x0b:
2056
0
    if (ext >= 0x0a) {
2057
0
      CREATE_GR_REG(MI, r2);
2058
0
    } else {
2059
0
      CREATE_GR_REG(MI, r1);
2060
0
    }
2061
0
    MCOperand_CreateImm0(MI, sa);
2062
0
    CREATE_GR_REG(MI, t);
2063
0
    break;
2064
0
  case 0x00:
2065
0
  case 0x08:
2066
0
  case 0x01:
2067
0
  case 0x09:
2068
0
    CREATE_GR_REG(MI, r1);
2069
0
    CREATE_GR_REG(MI, r2);
2070
0
    CREATE_GR_REG(MI, t);
2071
0
    break;
2072
0
  default:
2073
0
    return false;
2074
0
  }
2075
0
success:
2076
0
  fill_multmed_mods(insn, HPPA_EXT_REF(MI));
2077
0
  return true;
2078
0
}
2079
2080
static void fill_branch_insn_name(MCInst *MI, uint32_t insn)
2081
0
{
2082
0
  uint32_t ext = get_insn_field(insn, 16, 18);
2083
0
  uint32_t bit_19 = get_insn_bit(insn, 19);
2084
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
2085
0
    if (insn == 0xe8004005) {
2086
0
      MCInst_setOpcode(MI, HPPA_INS_CLRBTS);
2087
0
      return;
2088
0
    } else if (insn == 0xe8004001) {
2089
0
      MCInst_setOpcode(MI, HPPA_INS_PUSHNOM);
2090
0
      return;
2091
0
    }
2092
2093
0
    switch (ext) {
2094
0
    case 0x00:
2095
0
    case 0x01:
2096
0
    case 0x04:
2097
0
    case 0x05:
2098
0
      MCInst_setOpcode(MI, HPPA_INS_B);
2099
0
      return;
2100
0
    case 0x06:
2101
0
      if (bit_19 == 0) {
2102
0
        MCInst_setOpcode(MI, HPPA_INS_BV);
2103
0
      } else {
2104
0
        MCInst_setOpcode(MI, HPPA_INS_BVE);
2105
0
      }
2106
0
      return;
2107
0
    case 0x07:
2108
0
      if (bit_19 == 1) {
2109
0
        MCInst_setOpcode(MI, HPPA_INS_BVE);
2110
0
      }
2111
0
      return;
2112
0
    case 0x02:
2113
0
      if (get_insn_field(insn, 19, 29) == 0 &&
2114
0
          get_insn_bit(insn, 31) == 0) {
2115
0
        MCInst_setOpcode(MI, HPPA_INS_BLR);
2116
0
        return;
2117
0
      }
2118
0
      if (get_insn_field(insn, 19, 31) == 1) {
2119
0
        MCInst_setOpcode(MI, HPPA_INS_PUSHBTS);
2120
0
        return;
2121
0
      }
2122
0
      if (bit_19 == 0 &&
2123
0
          get_insn_field(insn, 29, 31) == 0x5) {
2124
0
        MCInst_setOpcode(MI, HPPA_INS_POPBTS);
2125
0
        return;
2126
0
      }
2127
0
      return;
2128
0
    default:
2129
0
      return;
2130
0
    }
2131
0
  }
2132
0
  switch (ext) {
2133
0
  case 0x00:
2134
0
    MCInst_setOpcode(MI, HPPA_INS_BL);
2135
0
    break;
2136
0
  case 0x01:
2137
0
    MCInst_setOpcode(MI, HPPA_INS_GATE);
2138
0
    break;
2139
0
  case 0x02:
2140
0
    MCInst_setOpcode(MI, HPPA_INS_BLR);
2141
0
    break;
2142
0
  case 0x06:
2143
0
    MCInst_setOpcode(MI, HPPA_INS_BV);
2144
0
    break;
2145
0
  default:
2146
0
    break;
2147
0
  }
2148
0
}
2149
2150
static void fill_branch_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
2151
0
{
2152
0
  uint32_t ext = get_insn_field(insn, 16, 18);
2153
0
  uint32_t n = get_insn_bit(insn, 30);
2154
0
  uint32_t p = get_insn_bit(insn, 31);
2155
0
  if (MODE_IS_HPPA_20(mode)) {
2156
0
    switch (ext) {
2157
0
    case 0x00:
2158
0
    case 0x05:
2159
0
      push_str_modifier(hppa_ext, "l");
2160
      // fallthrough
2161
0
    case 0x02:
2162
0
      break;
2163
0
    case 0x01:
2164
0
      push_str_modifier(hppa_ext, "gate");
2165
0
      break;
2166
0
    case 0x04:
2167
0
      push_str_modifier(hppa_ext, "l");
2168
0
      push_str_modifier(hppa_ext, "push");
2169
0
      break;
2170
0
    case 0x06:
2171
0
    case 0x07:
2172
0
      if (get_insn_bit(insn, 19) == 0) {
2173
0
        break;
2174
0
      }
2175
0
      if (ext == 7) {
2176
0
        push_str_modifier(hppa_ext, "l");
2177
0
        hppa_ext->is_alternative = true;
2178
0
        if (p == 1) {
2179
0
          push_str_modifier(hppa_ext, "push");
2180
0
        }
2181
0
      } else {
2182
0
        if (p == 1) {
2183
0
          push_str_modifier(hppa_ext, "pop");
2184
0
        }
2185
0
      }
2186
0
      break;
2187
0
    default:
2188
0
      return;
2189
0
    }
2190
0
  }
2191
0
  if (n == 1) {
2192
0
    push_str_modifier(hppa_ext, "n");
2193
0
  }
2194
0
}
2195
2196
static bool decode_branch(const cs_struct *ud, MCInst *MI, uint32_t insn)
2197
0
{
2198
0
  uint32_t ext = get_insn_field(insn, 16, 18);
2199
0
  uint32_t t = get_insn_field(insn, 6, 10);
2200
0
  uint32_t i = get_insn_field(insn, 20, 28);
2201
0
  uint32_t r = get_insn_field(insn, 11, 15);
2202
0
  uint32_t bit_19 = get_insn_bit(insn, 19);
2203
0
  if (MODE_IS_HPPA_20(ud->mode)) {
2204
0
    if (insn == 0xe8004005 || insn == 0xe8004001) {
2205
0
      return true;
2206
0
    }
2207
2208
0
    switch (ext) {
2209
0
    case 0x01:
2210
0
    case 0x00:
2211
0
      MCOperand_CreateImm0(MI, extract_17(insn));
2212
0
      CREATE_GR_REG(MI, t);
2213
0
      break;
2214
0
    case 0x04:
2215
0
    case 0x05:
2216
0
      MCOperand_CreateImm0(MI, extract_22(insn));
2217
0
      CREATE_GR_REG(MI, t);
2218
0
      break;
2219
0
    case 0x02:
2220
0
      if (bit_19 == 1) {
2221
0
        return false;
2222
0
      }
2223
0
      if (get_insn_field(insn, 20, 31) == 1 && t == 0) {
2224
0
        CREATE_GR_REG(MI, r);
2225
0
        break;
2226
0
      }
2227
0
      if (r == 0 && t == 0 &&
2228
0
          get_insn_field(insn, 29, 31) == 0x5) {
2229
0
        MCOperand_CreateImm0(MI, i);
2230
0
        break;
2231
0
      }
2232
0
      if (get_insn_bit(insn, 31) == 0 &&
2233
0
          get_insn_field(insn, 19, 29) == 0) {
2234
0
        CREATE_GR_REG(MI, r);
2235
0
        CREATE_GR_REG(MI, t);
2236
0
        break;
2237
0
      }
2238
0
      return false;
2239
0
    case 0x06:
2240
0
      if (bit_19 == 0) {
2241
0
        CREATE_GR_REG(MI, r);
2242
0
      }
2243
0
      CREATE_GR_REG(MI, t);
2244
0
      break;
2245
0
    case 0x07:
2246
0
      if (bit_19 == 1) {
2247
0
        CREATE_GR_REG(MI, t);
2248
0
        CREATE_GR_REG(MI, 2);
2249
0
        break;
2250
0
      }
2251
      // fallthrough
2252
0
    default:
2253
0
      return false;
2254
0
    }
2255
0
    fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode);
2256
0
    return true;
2257
0
  } else {
2258
0
    switch (ext) {
2259
0
    case 0x00:
2260
0
    case 0x01:
2261
0
      MCOperand_CreateImm0(MI, extract_17(insn));
2262
0
      CREATE_GR_REG(MI, t);
2263
0
      break;
2264
0
    case 0x02:
2265
0
    case 0x06:
2266
0
      CREATE_GR_REG(MI, r);
2267
0
      CREATE_GR_REG(MI, t);
2268
0
      break;
2269
0
    default:
2270
0
      return false;
2271
0
    }
2272
0
    fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode);
2273
0
    return true;
2274
0
  }
2275
0
}
2276
2277
static void fill_corpdw_insn_name(MCInst *MI, uint32_t insn)
2278
0
{
2279
0
  uint32_t ext = (get_insn_field(insn, 19, 19) << 1) |
2280
0
           get_insn_field(insn, 22, 22);
2281
0
  uint32_t opcode = insn >> 26;
2282
0
  uint32_t uid = get_insn_field(insn, 23, 25);
2283
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
2284
0
    if (opcode == 0x09) {
2285
0
      switch (ext) {
2286
0
      case 0x00:
2287
0
      case 0x02:
2288
0
        if (uid <= 0x01) {
2289
0
          MCInst_setOpcode(MI, HPPA_INS_FLDW);
2290
0
        } else {
2291
0
          MCInst_setOpcode(MI, HPPA_INS_CLDW);
2292
0
        }
2293
0
        return;
2294
0
      case 0x01:
2295
0
      case 0x03:
2296
0
        if (uid <= 0x01) {
2297
0
          MCInst_setOpcode(MI, HPPA_INS_FSTW);
2298
0
        } else {
2299
0
          MCInst_setOpcode(MI, HPPA_INS_CSTW);
2300
0
        }
2301
0
        return;
2302
0
      default:
2303
0
        break;
2304
0
      }
2305
0
    } else {
2306
0
      switch (ext) {
2307
0
      case 0x00:
2308
0
      case 0x02:
2309
0
        if (uid == 0x00) {
2310
0
          MCInst_setOpcode(MI, HPPA_INS_FLDD);
2311
0
        } else {
2312
0
          MCInst_setOpcode(MI, HPPA_INS_CLDD);
2313
0
        }
2314
0
        return;
2315
0
      case 0x01:
2316
0
      case 0x03:
2317
0
        if (uid == 0x00) {
2318
0
          MCInst_setOpcode(MI, HPPA_INS_FSTD);
2319
0
        } else {
2320
0
          MCInst_setOpcode(MI, HPPA_INS_CSTD);
2321
0
        }
2322
0
        return;
2323
0
      default:
2324
0
        break;
2325
0
      }
2326
0
    }
2327
0
  }
2328
0
  if (opcode == 0x09) {
2329
0
    switch (ext) {
2330
0
    case 0x00:
2331
0
      MCInst_setOpcode(MI, HPPA_INS_CLDWX);
2332
0
      break;
2333
0
    case 0x01:
2334
0
      MCInst_setOpcode(MI, HPPA_INS_CSTWX);
2335
0
      break;
2336
0
    case 0x02:
2337
0
      MCInst_setOpcode(MI, HPPA_INS_CLDWS);
2338
0
      break;
2339
0
    case 0x03:
2340
0
      MCInst_setOpcode(MI, HPPA_INS_CSTWS);
2341
0
      break;
2342
0
    default:
2343
0
      break;
2344
0
    }
2345
0
  } else {
2346
0
    switch (ext) {
2347
0
    case 0x00:
2348
0
      MCInst_setOpcode(MI, HPPA_INS_CLDDX);
2349
0
      break;
2350
0
    case 0x01:
2351
0
      MCInst_setOpcode(MI, HPPA_INS_CSTDX);
2352
0
      break;
2353
0
    case 0x02:
2354
0
      MCInst_setOpcode(MI, HPPA_INS_CLDDS);
2355
0
      break;
2356
0
    case 0x03:
2357
0
      MCInst_setOpcode(MI, HPPA_INS_CSTDS);
2358
0
      break;
2359
0
    default:
2360
0
      break;
2361
0
    }
2362
0
  }
2363
0
}
2364
2365
static inline bool coprdw_has_uid_mod(uint32_t opcode, uint32_t uid)
2366
0
{
2367
0
  return !((opcode == HPPA_OP_TYPE_COPRW && uid <= 0x01) ||
2368
0
     (opcode == HPPA_OP_TYPE_COPRDW && uid == 0x00));
2369
0
}
2370
2371
static void fill_corpdw_mods(uint32_t insn, uint32_t im, hppa_ext *hppa_ext,
2372
           cs_mode mode)
2373
0
{
2374
0
  uint32_t uid = get_insn_field(insn, 23, 25);
2375
0
  uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26);
2376
0
  uint32_t cc = get_insn_field(insn, 20, 21);
2377
0
  uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22);
2378
0
  uint32_t opcode = insn >> 26;
2379
2380
0
  if (coprdw_has_uid_mod(opcode, uid)) {
2381
0
    push_int_modifier(hppa_ext, uid);
2382
0
  }
2383
0
  if (CMPLT_HAS_MODIFY_BIT(cmplt)) {
2384
0
    hppa_ext->b_writeble = true;
2385
0
  }
2386
2387
0
  switch (ext) {
2388
0
  case 0x00:
2389
0
  case 0x01:
2390
0
    push_str_modifier(hppa_ext, index_compl_names[cmplt]);
2391
0
    break;
2392
0
  case 0x02:
2393
0
  case 0x03:
2394
0
    if (MODE_IS_HPPA_20(mode)) {
2395
0
      if (cmplt == 1 && im == 0) {
2396
0
        push_str_modifier(hppa_ext, "o");
2397
0
        break;
2398
0
      }
2399
0
    }
2400
0
    push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]);
2401
0
    break;
2402
0
  default:
2403
0
    break;
2404
0
  }
2405
0
  if ((ext & 1) == 1 && cc == 1) {
2406
0
    push_str_modifier(hppa_ext, "bc");
2407
0
  }
2408
0
  if (cc == 2) {
2409
0
    push_str_modifier(hppa_ext, "sl");
2410
0
  }
2411
0
}
2412
2413
static bool decode_corpdw(const cs_struct *ud, MCInst *MI, uint32_t insn)
2414
0
{
2415
0
  uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22);
2416
0
  uint32_t x = get_insn_field(insn, 11, 15);
2417
0
  uint32_t b = get_insn_field(insn, 6, 10);
2418
0
  uint32_t s = get_insn_field(insn, 16, 17);
2419
0
  uint32_t t = get_insn_field(insn, 27, 31);
2420
0
  uint32_t opcode = MCInst_getOpcode(MI);
2421
0
  switch (ext) {
2422
0
  case 0x00:
2423
0
  case 0x02:
2424
0
    if (ext == 0x02) {
2425
0
      x = LowSignExtend64(x, 5);
2426
0
      MCOperand_CreateImm0(MI, x);
2427
0
    } else {
2428
0
      CREATE_GR_REG(MI, x);
2429
0
    }
2430
0
    CREATE_SR_REG(MI, s);
2431
0
    CREATE_GR_REG(MI, b);
2432
0
    if (opcode == HPPA_INS_FLDW || opcode == HPPA_INS_FLDD) {
2433
0
      CREATE_FPR_REG(MI, t);
2434
0
    } else {
2435
0
      CREATE_GR_REG(MI, t);
2436
0
    }
2437
0
    break;
2438
0
  case 0x01:
2439
0
  case 0x03:
2440
0
    if (opcode == HPPA_INS_FSTW || opcode == HPPA_INS_FSTD) {
2441
0
      CREATE_FPR_REG(MI, t);
2442
0
    } else {
2443
0
      CREATE_GR_REG(MI, t);
2444
0
    }
2445
0
    if (ext == 0x03) {
2446
0
      x = LowSignExtend64(x, 5);
2447
0
      MCOperand_CreateImm0(MI, x);
2448
0
    } else {
2449
0
      CREATE_GR_REG(MI, x);
2450
0
    }
2451
0
    CREATE_SR_REG(MI, s);
2452
0
    CREATE_GR_REG(MI, b);
2453
0
    break;
2454
0
  default:
2455
0
    break;
2456
0
  }
2457
0
  fill_corpdw_mods(insn, x, HPPA_EXT_REF(MI), ud->mode);
2458
0
  return true;
2459
0
}
2460
2461
static void fill_spop_insn_name(MCInst *MI, uint32_t insn)
2462
0
{
2463
0
  uint32_t ext = get_insn_field(insn, 21, 22);
2464
0
  switch (ext) {
2465
0
  case 0x00:
2466
0
    MCInst_setOpcode(MI, HPPA_INS_SPOP0);
2467
0
    break;
2468
0
  case 0x01:
2469
0
    MCInst_setOpcode(MI, HPPA_INS_SPOP1);
2470
0
    break;
2471
0
  case 0x02:
2472
0
    MCInst_setOpcode(MI, HPPA_INS_SPOP2);
2473
0
    break;
2474
0
  case 0x03:
2475
0
    MCInst_setOpcode(MI, HPPA_INS_SPOP3);
2476
0
    break;
2477
0
  default:
2478
0
    break;
2479
0
  }
2480
0
}
2481
2482
static void fill_spop_mods(uint32_t insn, uint32_t ext, hppa_ext *hppa_ext)
2483
0
{
2484
0
  uint32_t sfu = get_insn_field(insn, 23, 25);
2485
0
  uint32_t n = get_insn_field(insn, 26, 26);
2486
0
  uint32_t sop;
2487
2488
0
  push_int_modifier(hppa_ext, sfu);
2489
0
  switch (ext) {
2490
0
  case 0x00:
2491
0
    sop = (get_insn_field(insn, 6, 20) << 5) |
2492
0
          get_insn_field(insn, 27, 31);
2493
0
    break;
2494
0
  case 0x01:
2495
0
    sop = get_insn_field(insn, 6, 20);
2496
0
    break;
2497
0
  case 0x02:
2498
0
    sop = (get_insn_field(insn, 11, 20) << 5) |
2499
0
          get_insn_field(insn, 27, 31);
2500
0
    break;
2501
0
  case 0x03:
2502
0
    sop = (get_insn_field(insn, 16, 20) << 5) |
2503
0
          get_insn_field(insn, 27, 31);
2504
0
    break;
2505
0
  default:
2506
0
    return;
2507
0
  }
2508
0
  push_int_modifier(hppa_ext, sop);
2509
0
  if (n == 1) {
2510
0
    push_str_modifier(hppa_ext, "n");
2511
0
  }
2512
0
}
2513
2514
static bool decode_spop(const cs_struct *ud, MCInst *MI, uint32_t insn)
2515
0
{
2516
0
  uint32_t ext = get_insn_field(insn, 21, 22);
2517
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
2518
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
2519
0
  uint32_t t = get_insn_field(insn, 27, 31);
2520
0
  switch (ext) {
2521
0
  case 0x00:
2522
0
    break;
2523
0
  case 0x01:
2524
0
    CREATE_GR_REG(MI, t);
2525
0
    break;
2526
0
  case 0x02:
2527
0
    CREATE_GR_REG(MI, r1);
2528
0
    break;
2529
0
  case 0x03:
2530
0
    CREATE_GR_REG(MI, r2);
2531
0
    CREATE_GR_REG(MI, r1);
2532
0
    break;
2533
0
  default:
2534
0
    return false;
2535
0
  }
2536
0
  fill_spop_mods(insn, ext, HPPA_EXT_REF(MI));
2537
0
  return true;
2538
0
}
2539
2540
static void fill_copr_insn_name(MCInst *MI, uint32_t insn)
2541
0
{
2542
0
  uint32_t class = get_insn_field(insn, 21, 22);
2543
0
  uint32_t uid = get_insn_field(insn, 23, 25);
2544
0
  uint32_t subop;
2545
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
2546
0
    if (uid == 0) {
2547
0
      if (class == 0) {
2548
0
        subop = get_insn_field(insn, 16, 18);
2549
0
        switch (subop) {
2550
0
        case 0x00:
2551
0
          MCInst_setOpcode(MI, HPPA_INS_FID);
2552
0
          return;
2553
0
        case 0x06:
2554
0
          MCInst_setOpcode(MI, HPPA_INS_FNEG);
2555
0
          return;
2556
0
        case 0x07:
2557
0
          MCInst_setOpcode(MI, HPPA_INS_FNEGABS);
2558
0
          return;
2559
0
        default:
2560
0
          break;
2561
0
        }
2562
0
      } else if (class == 1) {
2563
0
        subop = get_insn_field(insn, 14, 16);
2564
0
        if (subop != 4) {
2565
0
          MCInst_setOpcode(MI, HPPA_INS_FCNV);
2566
0
          return;
2567
0
        }
2568
0
      } else if (class == 2) {
2569
0
        if (get_insn_bit(insn, 26) == 0) {
2570
0
          MCInst_setOpcode(MI, HPPA_INS_FCMP);
2571
0
        } else {
2572
0
          MCInst_setOpcode(MI, HPPA_INS_FTEST);
2573
0
        }
2574
0
        return;
2575
0
      }
2576
0
    }
2577
0
  }
2578
2579
0
  if (uid == 0) {
2580
0
    if (class == 0) {
2581
0
      subop = get_insn_field(insn, 16, 18);
2582
0
      switch (subop) {
2583
0
      case 0x00:
2584
0
        MCInst_setOpcode(MI, HPPA_INS_COPR);
2585
0
        return;
2586
0
      case 0x02:
2587
0
        MCInst_setOpcode(MI, HPPA_INS_FCPY);
2588
0
        return;
2589
0
      case 0x03:
2590
0
        MCInst_setOpcode(MI, HPPA_INS_FABS);
2591
0
        return;
2592
0
      case 0x04:
2593
0
        MCInst_setOpcode(MI, HPPA_INS_FSQRT);
2594
0
        return;
2595
0
      case 0x05:
2596
0
        MCInst_setOpcode(MI, HPPA_INS_FRND);
2597
0
        return;
2598
0
      default:
2599
0
        break;
2600
0
      }
2601
0
    } else if (class == 1) {
2602
0
      subop = get_insn_field(insn, 15, 16);
2603
0
      switch (subop) {
2604
0
      case 0x00:
2605
0
        MCInst_setOpcode(MI, HPPA_INS_FCNVFF);
2606
0
        return;
2607
0
      case 0x01:
2608
0
        MCInst_setOpcode(MI, HPPA_INS_FCNVXF);
2609
0
        return;
2610
0
      case 0x02:
2611
0
        MCInst_setOpcode(MI, HPPA_INS_FCNVFX);
2612
0
        return;
2613
0
      case 0x03:
2614
0
        MCInst_setOpcode(MI, HPPA_INS_FCNVFXT);
2615
0
        return;
2616
0
      default:
2617
0
        break;
2618
0
      }
2619
0
    } else if (class == 2) {
2620
0
      subop = get_insn_field(insn, 16, 18);
2621
0
      switch (subop) {
2622
0
      case 0x00:
2623
0
        MCInst_setOpcode(MI, HPPA_INS_FCMP);
2624
0
        return;
2625
0
      case 0x01:
2626
0
        MCInst_setOpcode(MI, HPPA_INS_FTEST);
2627
0
        return;
2628
0
      default:
2629
0
        break;
2630
0
      }
2631
0
    } else if (class == 3) {
2632
0
      subop = get_insn_field(insn, 16, 18);
2633
0
      switch (subop) {
2634
0
      case 0x00:
2635
0
        MCInst_setOpcode(MI, HPPA_INS_FADD);
2636
0
        return;
2637
0
      case 0x01:
2638
0
        MCInst_setOpcode(MI, HPPA_INS_FSUB);
2639
0
        return;
2640
0
      case 0x02:
2641
0
        MCInst_setOpcode(MI, HPPA_INS_FMPY);
2642
0
        return;
2643
0
      case 0x03:
2644
0
        MCInst_setOpcode(MI, HPPA_INS_FDIV);
2645
0
        return;
2646
0
      default:
2647
0
        break;
2648
0
      }
2649
0
    }
2650
0
  } else if (uid == 2) {
2651
0
    subop = get_insn_field(insn, 18, 22);
2652
0
    switch (subop) {
2653
0
    case 0x01:
2654
0
      MCInst_setOpcode(MI, HPPA_INS_PMDIS);
2655
0
      return;
2656
0
    case 0x03:
2657
0
      MCInst_setOpcode(MI, HPPA_INS_PMENB);
2658
0
      return;
2659
0
    default:
2660
0
      break;
2661
0
    }
2662
0
  }
2663
0
  MCInst_setOpcode(MI, HPPA_INS_COPR);
2664
0
}
2665
2666
static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class,
2667
         hppa_ext *hppa_ext, uint32_t subop, cs_mode mode)
2668
0
{
2669
0
  uint32_t n = get_insn_field(insn, 26, 26);
2670
0
  uint32_t sf = get_insn_field(insn, 19, 20);
2671
0
  uint32_t df = get_insn_field(insn, 17, 18);
2672
0
  if (MODE_IS_HPPA_20(mode)) {
2673
0
    if (uid == 0) {
2674
0
      if (class == 0) {
2675
0
        switch (subop) {
2676
0
        case 0x00:
2677
0
          return;
2678
0
        default:
2679
0
          break;
2680
0
        }
2681
0
      } else if (class == 1) {
2682
0
        switch (subop) {
2683
0
        case 0x00:
2684
0
          push_str_modifier(
2685
0
            hppa_ext,
2686
0
            float_format_names[sf]);
2687
0
          push_str_modifier(
2688
0
            hppa_ext,
2689
0
            float_format_names[df]);
2690
0
          return;
2691
0
        case 0x01:
2692
0
          push_str_modifier(hppa_ext,
2693
0
                fcnv_fixed_names[sf]);
2694
0
          push_str_modifier(
2695
0
            hppa_ext,
2696
0
            float_format_names[df]);
2697
0
          return;
2698
0
        case 0x03:
2699
0
          push_str_modifier(hppa_ext, "t");
2700
          // fallthrough
2701
0
        case 0x02:
2702
0
          push_str_modifier(
2703
0
            hppa_ext,
2704
0
            float_format_names[sf]);
2705
0
          push_str_modifier(hppa_ext,
2706
0
                fcnv_fixed_names[df]);
2707
0
          return;
2708
0
        case 0x05:
2709
0
          push_str_modifier(
2710
0
            hppa_ext,
2711
0
            fcnv_ufixed_names[sf]);
2712
0
          push_str_modifier(
2713
0
            hppa_ext,
2714
0
            float_format_names[df]);
2715
0
          return;
2716
0
        case 0x07:
2717
0
          push_str_modifier(hppa_ext, "t");
2718
          // fallthrough
2719
0
        case 0x06:
2720
0
          push_str_modifier(
2721
0
            hppa_ext,
2722
0
            float_format_names[sf]);
2723
0
          push_str_modifier(
2724
0
            hppa_ext,
2725
0
            fcnv_ufixed_names[df]);
2726
0
          return;
2727
0
        default:
2728
0
          break;
2729
0
        }
2730
0
      }
2731
0
    }
2732
0
  }
2733
2734
0
  if (uid == 0) {
2735
0
    if (class == 0) {
2736
0
      switch (subop) {
2737
0
      case 0x00:
2738
0
        push_int_modifier(hppa_ext, 0);
2739
0
        push_int_modifier(hppa_ext, 0);
2740
0
        if (n == 1) {
2741
0
          push_str_modifier(hppa_ext, "n");
2742
0
        }
2743
0
        break;
2744
0
      case 0x02:
2745
0
      case 0x03:
2746
0
      case 0x04:
2747
0
      case 0x05:
2748
0
      case 0x06:
2749
0
      case 0x07:
2750
0
        push_str_modifier(hppa_ext,
2751
0
              float_format_names[sf]);
2752
0
        break;
2753
0
      default:
2754
0
        break;
2755
0
      }
2756
0
    } else if (class == 1) {
2757
0
      push_str_modifier(hppa_ext, float_format_names[sf]);
2758
0
      push_str_modifier(hppa_ext, float_format_names[df]);
2759
0
    } else if (class == 2) {
2760
0
      uint32_t cond = get_insn_field(insn, 27, 31);
2761
0
      if (n == 1 && subop == 1) {
2762
0
        push_str_modifier(hppa_ext,
2763
0
              float_cond_names[cond]);
2764
0
      }
2765
0
      if (n == 0) {
2766
0
        push_str_modifier(hppa_ext,
2767
0
              float_format_names[sf]);
2768
0
        push_str_modifier(hppa_ext,
2769
0
              float_comp_names[cond]);
2770
0
      }
2771
0
    } else if (class == 3) {
2772
0
      push_str_modifier(hppa_ext, float_format_names[sf]);
2773
0
    }
2774
0
  } else if (uid == 2) {
2775
0
    if (n == 1) {
2776
0
      push_str_modifier(hppa_ext, "n");
2777
0
    }
2778
0
  } else {
2779
0
    uid = get_insn_field(insn, 23, 25);
2780
0
    uint32_t sop = (get_insn_field(insn, 6, 22) << 5) |
2781
0
             get_insn_field(insn, 27, 31);
2782
0
    push_int_modifier(hppa_ext, uid);
2783
0
    push_int_modifier(hppa_ext, sop);
2784
0
    if (n == 1) {
2785
0
      push_str_modifier(hppa_ext, "n");
2786
0
    }
2787
0
  }
2788
0
}
2789
2790
static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn)
2791
0
{
2792
0
  uint32_t class = get_insn_field(insn, 21, 22);
2793
0
  uint32_t uid = get_insn_field(insn, 23, 25);
2794
0
  uint32_t subop;
2795
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
2796
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
2797
0
  uint32_t t = get_insn_field(insn, 27, 31);
2798
0
  if (MODE_IS_HPPA_20(ud->mode)) {
2799
0
    if (uid == 0) {
2800
0
      if (class == 0) {
2801
0
        subop = get_insn_field(insn, 16, 18);
2802
0
        if (subop == 0x01) {
2803
0
          return false;
2804
0
        }
2805
0
        if (subop >= 0x02) {
2806
0
          CREATE_FPR_REG(MI, r1);
2807
0
          CREATE_FPR_REG(MI, t);
2808
0
        }
2809
0
      } else if (class == 1) {
2810
0
        subop = get_insn_field(insn, 14, 16);
2811
0
        if (subop == 0x04) {
2812
0
          return false;
2813
0
        }
2814
0
        CREATE_FPR_REG(MI, r1);
2815
0
        CREATE_FPR_REG(MI, t);
2816
0
      } else if (class == 2) {
2817
0
        uint32_t n = get_insn_bit(insn, 26);
2818
0
        subop = get_insn_field(insn, 16, 18);
2819
0
        if (n == 0) {
2820
0
          CREATE_FPR_REG(MI, r1);
2821
0
          CREATE_FPR_REG(MI, r2);
2822
0
          if (subop != 0) {
2823
0
            MCOperand_CreateImm0(MI,
2824
0
                     subop - 1);
2825
0
            HPPA_EXT_REF(MI)
2826
0
              ->is_alternative = true;
2827
0
          }
2828
0
        } else {
2829
0
          if (subop != 1) {
2830
0
            MCOperand_CreateImm0(
2831
0
              MI, (subop ^ 1) - 1);
2832
0
            HPPA_EXT_REF(MI)
2833
0
              ->is_alternative = true;
2834
0
          }
2835
0
        }
2836
0
      } else {
2837
0
        subop = get_insn_field(insn, 16, 18);
2838
0
        if (subop >= 4) {
2839
0
          return false;
2840
0
        }
2841
0
        CREATE_FPR_REG(MI, r1);
2842
0
        CREATE_FPR_REG(MI, r2);
2843
0
        CREATE_FPR_REG(MI, t);
2844
0
      }
2845
0
      fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI),
2846
0
               subop, ud->mode);
2847
0
      return true;
2848
0
    }
2849
0
  }
2850
0
  if (uid == 0) {
2851
0
    if (class == 0) {
2852
0
      subop = get_insn_field(insn, 16, 18);
2853
0
      switch (subop) {
2854
0
      case 0x02:
2855
0
      case 0x03:
2856
0
      case 0x04:
2857
0
      case 0x05:
2858
0
        CREATE_FPR_REG(MI, r1);
2859
0
        CREATE_FPR_REG(MI, t);
2860
        // fallthrough
2861
0
      case 0x00:
2862
0
        break;
2863
0
      default:
2864
0
        return false;
2865
0
      }
2866
0
    } else if (class == 1) {
2867
0
      subop = get_insn_field(insn, 15, 16);
2868
0
      switch (subop) {
2869
0
      case 0x00:
2870
0
      case 0x01:
2871
0
      case 0x02:
2872
0
      case 0x03:
2873
0
        CREATE_FPR_REG(MI, r1);
2874
0
        CREATE_FPR_REG(MI, t);
2875
0
        break;
2876
0
      default:
2877
0
        return false;
2878
0
      }
2879
0
    } else if (class == 2) {
2880
0
      subop = get_insn_field(insn, 16, 18);
2881
0
      switch (subop) {
2882
0
      case 0x00:
2883
0
        CREATE_FPR_REG(MI, r1);
2884
0
        CREATE_FPR_REG(MI, r2);
2885
        // fallthrough
2886
0
      case 0x01:
2887
0
        break;
2888
0
      default:
2889
0
        return false;
2890
0
      }
2891
0
    } else  {
2892
0
      subop = get_insn_field(insn, 16, 18);
2893
0
      switch (subop) {
2894
0
      case 0x00:
2895
0
      case 0x01:
2896
0
      case 0x02:
2897
0
      case 0x03:
2898
0
        CREATE_FPR_REG(MI, r1);
2899
0
        CREATE_FPR_REG(MI, r2);
2900
0
        CREATE_FPR_REG(MI, t);
2901
0
        break;
2902
0
      default:
2903
0
        return false;
2904
0
      }
2905
0
    }
2906
0
    fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), subop,
2907
0
             ud->mode);
2908
0
    return true;
2909
0
  } else if (uid == 2) {
2910
0
    subop = get_insn_field(insn, 18, 22);
2911
0
    switch (subop) {
2912
0
    case 0x01:
2913
0
    case 0x03:
2914
0
      break;
2915
0
    default:
2916
0
      return false;
2917
0
    }
2918
0
  }
2919
0
  fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), -1, ud->mode);
2920
0
  return true;
2921
0
}
2922
2923
static void fill_float_insn_name(MCInst *MI, uint32_t insn)
2924
0
{
2925
0
  uint32_t class = get_insn_field(insn, 21, 22);
2926
0
  uint32_t subop;
2927
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
2928
0
    if (class == 0) {
2929
0
      subop = get_insn_field(insn, 16, 18);
2930
0
      switch (subop) {
2931
0
      case 0x06:
2932
0
        MCInst_setOpcode(MI, HPPA_INS_FNEG);
2933
0
        return;
2934
0
      case 0x07:
2935
0
        MCInst_setOpcode(MI, HPPA_INS_FNEGABS);
2936
0
        return;
2937
0
      default:
2938
0
        break;
2939
0
      }
2940
0
    } else if (class == 1) {
2941
0
      subop = get_insn_field(insn, 14, 16);
2942
0
      if (subop == 0x04) {
2943
0
        return;
2944
0
      }
2945
0
      MCInst_setOpcode(MI, HPPA_INS_FCNV);
2946
0
      return;
2947
0
    } else if (class == 2) {
2948
0
      MCInst_setOpcode(MI, HPPA_INS_FCMP);
2949
0
      return;
2950
0
    }
2951
0
  }
2952
0
  if (class == 0) {
2953
0
    subop = get_insn_field(insn, 16, 18);
2954
0
    switch (subop) {
2955
0
    case 0x02:
2956
0
      MCInst_setOpcode(MI, HPPA_INS_FCPY);
2957
0
      break;
2958
0
    case 0x03:
2959
0
      MCInst_setOpcode(MI, HPPA_INS_FABS);
2960
0
      break;
2961
0
    case 0x04:
2962
0
      MCInst_setOpcode(MI, HPPA_INS_FSQRT);
2963
0
      break;
2964
0
    case 0x05:
2965
0
      MCInst_setOpcode(MI, HPPA_INS_FRND);
2966
0
      break;
2967
0
    default:
2968
0
      break;
2969
0
    }
2970
0
  } else if (class == 1) {
2971
0
    subop = get_insn_field(insn, 15, 16);
2972
0
    switch (subop) {
2973
0
    case 0x00:
2974
0
      MCInst_setOpcode(MI, HPPA_INS_FCNVFF);
2975
0
      break;
2976
0
    case 0x01:
2977
0
      MCInst_setOpcode(MI, HPPA_INS_FCNVXF);
2978
0
      break;
2979
0
    case 0x02:
2980
0
      MCInst_setOpcode(MI, HPPA_INS_FCNVFX);
2981
0
      break;
2982
0
    case 0x03:
2983
0
      MCInst_setOpcode(MI, HPPA_INS_FCNVFXT);
2984
0
      break;
2985
0
    default:
2986
0
      break;
2987
0
    }
2988
0
  } else if (class == 2) {
2989
0
    subop = get_insn_field(insn, 16, 18);
2990
0
    if (subop == 0x00) {
2991
0
      MCInst_setOpcode(MI, HPPA_INS_FCMP);
2992
0
    }
2993
0
  } else if (class == 3) {
2994
0
    subop = get_insn_field(insn, 16, 18);
2995
0
    uint32_t fixed = get_insn_field(insn, 23, 23);
2996
0
    if (fixed == 0) {
2997
0
      switch (subop) {
2998
0
      case 0x00:
2999
0
        MCInst_setOpcode(MI, HPPA_INS_FADD);
3000
0
        break;
3001
0
      case 0x01:
3002
0
        MCInst_setOpcode(MI, HPPA_INS_FSUB);
3003
0
        break;
3004
0
      case 0x02:
3005
0
        MCInst_setOpcode(MI, HPPA_INS_FMPY);
3006
0
        break;
3007
0
      case 0x03:
3008
0
        MCInst_setOpcode(MI, HPPA_INS_FDIV);
3009
0
        break;
3010
0
      default:
3011
0
        break;
3012
0
      }
3013
0
    } else {
3014
0
      if (subop == 0x02) {
3015
0
        MCInst_setOpcode(MI, HPPA_INS_XMPYU);
3016
0
      }
3017
0
    }
3018
0
  }
3019
0
}
3020
3021
static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext,
3022
          uint32_t subop, cs_mode mode)
3023
0
{
3024
0
  uint32_t sf = get_insn_field(insn, 19, 20);
3025
0
  uint32_t df = get_insn_field(insn, 17, 18);
3026
3027
0
  if (MODE_IS_HPPA_20(mode)) {
3028
0
    if (class == 1) {
3029
0
      switch (subop) {
3030
0
      case 0x00:
3031
0
        push_str_modifier(hppa_ext,
3032
0
              float_format_names[sf]);
3033
0
        push_str_modifier(hppa_ext,
3034
0
              float_format_names[df]);
3035
0
        return;
3036
0
      case 0x01:
3037
0
        push_str_modifier(hppa_ext,
3038
0
              fcnv_fixed_names[sf]);
3039
0
        push_str_modifier(hppa_ext,
3040
0
              float_format_names[df]);
3041
0
        return;
3042
0
      case 0x03:
3043
0
        push_str_modifier(hppa_ext, "t");
3044
        // fallthrough
3045
0
      case 0x02:
3046
0
        push_str_modifier(hppa_ext,
3047
0
              float_format_names[sf]);
3048
0
        push_str_modifier(hppa_ext,
3049
0
              fcnv_fixed_names[df]);
3050
0
        return;
3051
0
      case 0x05:
3052
0
        push_str_modifier(hppa_ext,
3053
0
              fcnv_ufixed_names[sf]);
3054
0
        push_str_modifier(hppa_ext,
3055
0
              float_format_names[df]);
3056
0
        return;
3057
0
      case 0x07:
3058
0
        push_str_modifier(hppa_ext, "t");
3059
        // fallthrough
3060
0
      case 0x06:
3061
0
        push_str_modifier(hppa_ext,
3062
0
              float_format_names[sf]);
3063
0
        push_str_modifier(hppa_ext,
3064
0
              fcnv_ufixed_names[df]);
3065
0
        return;
3066
0
      default:
3067
0
        return;
3068
0
      }
3069
0
    }
3070
0
  }
3071
3072
0
  if (class == 0) {
3073
0
    uint32_t fmt = get_insn_field(insn, 19, 20);
3074
0
    push_str_modifier(hppa_ext, float_format_names[fmt]);
3075
0
  } else if (class == 1) {
3076
0
    push_str_modifier(hppa_ext, float_format_names[sf]);
3077
0
    push_str_modifier(hppa_ext, float_format_names[df]);
3078
0
  } else if (class == 2) {
3079
0
    uint32_t fmt = get_insn_field(insn, 20, 20);
3080
0
    uint32_t cond = get_insn_field(insn, 27, 31);
3081
0
    push_str_modifier(hppa_ext, float_format_names[fmt]);
3082
0
    push_str_modifier(hppa_ext, float_cond_names[cond]);
3083
0
  } else if (class == 3) {
3084
0
    if (get_insn_field(insn, 23, 23) == 0) {
3085
0
      uint32_t fmt = get_insn_field(insn, 20, 20);
3086
0
      push_str_modifier(hppa_ext, float_format_names[fmt]);
3087
0
    }
3088
0
  }
3089
0
}
3090
3091
static bool decode_float(const cs_struct *ud, MCInst *MI, uint32_t insn)
3092
0
{
3093
0
  uint32_t class = get_insn_field(insn, 21, 22);
3094
0
  uint32_t subop;
3095
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
3096
0
  uint32_t r1_fpe = get_insn_bit(insn, 24);
3097
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
3098
0
  uint32_t r2_fpe = get_insn_bit(insn, 19);
3099
0
  uint32_t t = get_insn_field(insn, 27, 31);
3100
0
  uint32_t t_fpe = get_insn_bit(insn, 25);
3101
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3102
0
    if (class == 0) {
3103
0
      subop = get_insn_field(insn, 16, 18);
3104
0
      if (subop >= 0x02) {
3105
0
        create_float_reg_spec(MI, r1, r1_fpe);
3106
0
        create_float_reg_spec(MI, t, t_fpe);
3107
0
        fill_float_mods(insn, class, HPPA_EXT_REF(MI),
3108
0
            subop, ud->mode);
3109
0
        return true;
3110
0
      }
3111
0
    } else if (class == 1) {
3112
0
      subop = get_insn_field(insn, 14, 16);
3113
0
      if (subop == 0x04) {
3114
0
        return false;
3115
0
      }
3116
0
      create_float_reg_spec(MI, r1, r1_fpe);
3117
0
      create_float_reg_spec(MI, t, t_fpe);
3118
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3119
0
          ud->mode);
3120
0
      return true;
3121
0
    } else if (class == 2) {
3122
0
      subop = get_insn_field(insn, 16, 18);
3123
0
      create_float_reg_spec(MI, r1, r1_fpe);
3124
0
      create_float_reg_spec(MI, r2, r2_fpe);
3125
0
      if (subop != 0) {
3126
0
        MCOperand_CreateImm0(MI, subop - 1);
3127
0
      }
3128
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3129
0
          ud->mode);
3130
0
      return true;
3131
0
    }
3132
0
  }
3133
0
  if (class == 0) {
3134
0
    subop = get_insn_field(insn, 16, 18);
3135
0
    switch (subop) {
3136
0
    case 0x02:
3137
0
    case 0x03:
3138
0
    case 0x04:
3139
0
    case 0x05:
3140
0
      create_float_reg_spec(MI, r1, r1_fpe);
3141
0
      create_float_reg_spec(MI, t, t_fpe);
3142
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3143
0
          ud->mode);
3144
0
      return true;
3145
0
    default:
3146
0
      return false;
3147
0
    }
3148
0
  } else if (class == 1) {
3149
0
    subop = get_insn_field(insn, 15, 16);
3150
0
    if (subop <= 0x03) {
3151
0
      create_float_reg_spec(MI, r1, r1_fpe);
3152
0
      create_float_reg_spec(MI, t, t_fpe);
3153
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3154
0
          ud->mode);
3155
0
      return true;
3156
0
    }
3157
0
  } else if (class == 2) {
3158
0
    subop = get_insn_field(insn, 16, 18);
3159
0
    switch (subop) {
3160
0
    case 0x00:
3161
0
      create_float_reg_spec(MI, r1, r1_fpe);
3162
0
      create_float_reg_spec(MI, r2, r2_fpe);
3163
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3164
0
          ud->mode);
3165
0
      return true;
3166
0
    default:
3167
0
      return false;
3168
0
    }
3169
0
  } else if (class == 3) {
3170
0
    subop = get_insn_field(insn, 16, 18);
3171
0
    uint32_t fixed = get_insn_field(insn, 23, 23);
3172
0
    if ((fixed == 0 && subop <= 0x03) ||
3173
0
        (fixed == 1 && subop == 0x02)) {
3174
0
      create_float_reg_spec(MI, r1, r1_fpe);
3175
0
      create_float_reg_spec(MI, r2, r2_fpe);
3176
0
      create_float_reg_spec(MI, t, t_fpe);
3177
0
      fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop,
3178
0
          ud->mode);
3179
0
      return true;
3180
0
    }
3181
0
    return false;
3182
0
  }
3183
0
  return false;
3184
0
}
3185
3186
static void fill_fpfused_insn_name(MCInst *MI, uint32_t insn)
3187
0
{
3188
0
  uint32_t subop = get_insn_bit(insn, 26);
3189
0
  if (subop == 0x00) {
3190
0
    MCInst_setOpcode(MI, HPPA_INS_FMPYFADD);
3191
0
  } else {
3192
0
    MCInst_setOpcode(MI, HPPA_INS_FMPYNFADD);
3193
0
  }
3194
0
}
3195
3196
static void fill_fpfused_mods(uint32_t insn, hppa_ext *hppa_ext)
3197
0
{
3198
0
  uint32_t fmt = get_insn_bit(insn, 20);
3199
0
  push_str_modifier(hppa_ext, float_format_names[fmt]);
3200
0
}
3201
3202
static bool decode_fpfused(const cs_struct *ud, MCInst *MI, uint32_t insn)
3203
0
{
3204
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
3205
0
  uint32_t r1_fpe = get_insn_bit(insn, 24);
3206
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
3207
0
  uint32_t r2_fpe = get_insn_bit(insn, 19);
3208
0
  uint32_t ra = (get_insn_field(insn, 16, 18) << 2) |
3209
0
          get_insn_field(insn, 21, 22);
3210
0
  uint32_t ra_fpe = get_insn_bit(insn, 23);
3211
0
  uint32_t t = get_insn_field(insn, 27, 31);
3212
0
  uint32_t t_fpe = get_insn_bit(insn, 25);
3213
0
  create_float_reg_spec(MI, r1, r1_fpe);
3214
0
  create_float_reg_spec(MI, r2, r2_fpe);
3215
0
  create_float_reg_spec(MI, ra, ra_fpe);
3216
0
  create_float_reg_spec(MI, t, t_fpe);
3217
0
  fill_fpfused_mods(insn, HPPA_EXT_REF(MI));
3218
0
  return true;
3219
0
}
3220
3221
static void fill_action_and_branch_insn_name(MCInst *MI, uint32_t opcode)
3222
0
{
3223
0
  if (MODE_IS_HPPA_20(MI->csh->mode)) {
3224
0
    switch (opcode) {
3225
0
    case HPPA_OP_TYPE_CMPBT:
3226
0
    case HPPA_OP_TYPE_CMPBF:
3227
0
    case HPPA_OP_TYPE_CMPBDWT:
3228
0
    case HPPA_OP_TYPE_CMPBDWF:
3229
0
      MCInst_setOpcode(MI, HPPA_INS_CMPB);
3230
0
      return;
3231
0
    case HPPA_OP_TYPE_CMPIBT:
3232
0
    case HPPA_OP_TYPE_CMPIBF:
3233
0
    case HPPA_OP_TYPE_CMPIBDW:
3234
0
      MCInst_setOpcode(MI, HPPA_INS_CMPIB);
3235
0
      return;
3236
0
    case HPPA_OP_TYPE_ADDBT:
3237
0
    case HPPA_OP_TYPE_ADDBF:
3238
0
      MCInst_setOpcode(MI, HPPA_INS_ADDB);
3239
0
      return;
3240
0
    case HPPA_OP_TYPE_ADDIBT:
3241
0
    case HPPA_OP_TYPE_ADDIBF:
3242
0
      MCInst_setOpcode(MI, HPPA_INS_ADDIB);
3243
0
      return;
3244
0
    case HPPA_OP_TYPE_BBS:
3245
0
      MCInst_setOpcode(MI, HPPA_INS_BB);
3246
0
      return;
3247
0
    default:
3248
0
      break;
3249
0
    }
3250
0
  }
3251
0
  switch (opcode) {
3252
0
  case HPPA_OP_TYPE_CMPBT:
3253
0
    MCInst_setOpcode(MI, HPPA_INS_COMBT);
3254
0
    break;
3255
0
  case HPPA_OP_TYPE_CMPBF:
3256
0
    MCInst_setOpcode(MI, HPPA_INS_COMBF);
3257
0
    break;
3258
0
  case HPPA_OP_TYPE_CMPIBT:
3259
0
    MCInst_setOpcode(MI, HPPA_INS_COMIBT);
3260
0
    break;
3261
0
  case HPPA_OP_TYPE_CMPIBF:
3262
0
    MCInst_setOpcode(MI, HPPA_INS_COMIBF);
3263
0
    break;
3264
0
  case HPPA_OP_TYPE_ADDBT:
3265
0
    MCInst_setOpcode(MI, HPPA_INS_ADDBT);
3266
0
    break;
3267
0
  case HPPA_OP_TYPE_ADDBF:
3268
0
    MCInst_setOpcode(MI, HPPA_INS_ADDBF);
3269
0
    break;
3270
0
  case HPPA_OP_TYPE_ADDIBT:
3271
0
    MCInst_setOpcode(MI, HPPA_INS_ADDIBT);
3272
0
    break;
3273
0
  case HPPA_OP_TYPE_ADDIBF:
3274
0
    MCInst_setOpcode(MI, HPPA_INS_ADDIBF);
3275
0
    break;
3276
0
  case HPPA_OP_TYPE_MOVB:
3277
0
    MCInst_setOpcode(MI, HPPA_INS_MOVB);
3278
0
    break;
3279
0
  case HPPA_OP_TYPE_MOVIB:
3280
0
    MCInst_setOpcode(MI, HPPA_INS_MOVIB);
3281
0
    break;
3282
0
  case HPPA_OP_TYPE_BBS:
3283
0
    MCInst_setOpcode(MI, HPPA_INS_BVB);
3284
0
    break;
3285
0
  case HPPA_OP_TYPE_BB:
3286
0
    MCInst_setOpcode(MI, HPPA_INS_BB);
3287
0
    break;
3288
0
  default:
3289
0
    break;
3290
0
  }
3291
0
}
3292
3293
static void fill_action_and_branch_mods(uint32_t insn, uint32_t opcode,
3294
          hppa_ext *hppa_ext, cs_mode mode)
3295
0
{
3296
0
  uint32_t cond = get_insn_field(insn, 16, 18);
3297
0
  uint32_t n = get_insn_bit(insn, 30);
3298
0
  uint32_t d = get_insn_bit(insn, 18);
3299
3300
0
  if (MODE_IS_HPPA_20(mode)) {
3301
0
    switch (opcode) {
3302
0
    case HPPA_OP_TYPE_CMPBT:
3303
0
    case HPPA_OP_TYPE_CMPIBT:
3304
0
      push_str_modifier(hppa_ext, compare_cond_names[cond]);
3305
0
      break;
3306
0
    case HPPA_OP_TYPE_CMPBF:
3307
0
    case HPPA_OP_TYPE_CMPIBF:
3308
0
      push_str_modifier(hppa_ext,
3309
0
            compare_cond_names[cond + 8]);
3310
0
      break;
3311
0
    case HPPA_OP_TYPE_CMPBDWT:
3312
0
      push_str_modifier(hppa_ext,
3313
0
            compare_cond_64_names[cond]);
3314
0
      break;
3315
0
    case HPPA_OP_TYPE_CMPBDWF:
3316
0
      push_str_modifier(hppa_ext,
3317
0
            compare_cond_64_names[cond + 8]);
3318
0
      break;
3319
0
    case HPPA_OP_TYPE_CMPIBDW:
3320
0
      push_str_modifier(hppa_ext, cmpib_cond_64_names[cond]);
3321
0
      break;
3322
0
    case HPPA_OP_TYPE_ADDBT:
3323
0
    case HPPA_OP_TYPE_ADDIBT:
3324
0
      if (MODE_IS_HPPA_20W(mode)) {
3325
0
        push_str_modifier(hppa_ext,
3326
0
              wide_add_cond_names[cond]);
3327
0
      } else {
3328
0
        push_str_modifier(hppa_ext,
3329
0
              add_cond_names[cond]);
3330
0
      }
3331
0
      break;
3332
0
    case HPPA_OP_TYPE_ADDBF:
3333
0
    case HPPA_OP_TYPE_ADDIBF:
3334
0
      if (MODE_IS_HPPA_20W(mode)) {
3335
0
        push_str_modifier(
3336
0
          hppa_ext,
3337
0
          wide_add_cond_names[cond + 8]);
3338
0
      } else {
3339
0
        push_str_modifier(hppa_ext,
3340
0
              add_cond_names[cond + 8]);
3341
0
      }
3342
0
      break;
3343
0
    case HPPA_OP_TYPE_BBS:
3344
0
    case HPPA_OP_TYPE_BB:
3345
0
      if (d == 0) {
3346
0
        push_str_modifier(hppa_ext,
3347
0
              shift_cond_names[cond]);
3348
0
      } else {
3349
0
        push_str_modifier(hppa_ext,
3350
0
              shift_cond_64_names[cond]);
3351
0
      }
3352
0
      break;
3353
0
    case HPPA_OP_TYPE_MOVB:
3354
0
    case HPPA_OP_TYPE_MOVIB:
3355
0
      push_str_modifier(hppa_ext, shift_cond_names[cond]);
3356
0
      break;
3357
0
    default:
3358
0
      break;
3359
0
    }
3360
0
    if (n == 1) {
3361
0
      push_str_modifier(hppa_ext, "n");
3362
0
    }
3363
0
    return;
3364
0
  }
3365
0
  switch (opcode) {
3366
0
  case HPPA_OP_TYPE_CMPBT:
3367
0
  case HPPA_OP_TYPE_CMPBF:
3368
0
  case HPPA_OP_TYPE_CMPIBT:
3369
0
  case HPPA_OP_TYPE_CMPIBF:
3370
0
    push_str_modifier(hppa_ext, compare_cond_names[cond]);
3371
0
    break;
3372
0
  case HPPA_OP_TYPE_ADDBT:
3373
0
  case HPPA_OP_TYPE_ADDBF:
3374
0
  case HPPA_OP_TYPE_ADDIBT:
3375
0
  case HPPA_OP_TYPE_ADDIBF:
3376
0
    push_str_modifier(hppa_ext, add_cond_names[cond]);
3377
0
    break;
3378
0
  case HPPA_OP_TYPE_MOVB:
3379
0
  case HPPA_OP_TYPE_MOVIB:
3380
0
  case HPPA_OP_TYPE_BBS:
3381
0
  case HPPA_OP_TYPE_BB:
3382
0
    push_str_modifier(hppa_ext, shift_cond_names[cond]);
3383
0
    break;
3384
0
  default:
3385
0
    break;
3386
0
  }
3387
0
  if (n == 1) {
3388
0
    push_str_modifier(hppa_ext, "n");
3389
0
  }
3390
0
}
3391
3392
static bool fill_action_and_branch(const cs_struct *ud, MCInst *MI,
3393
           uint32_t insn)
3394
0
{
3395
0
  uint32_t opcode = insn >> 26;
3396
0
  uint32_t r1 = get_insn_field(insn, 6, 10);
3397
0
  uint32_t r2 = get_insn_field(insn, 11, 15);
3398
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3399
0
    switch (opcode) {
3400
0
    case HPPA_OP_TYPE_CMPBT:
3401
0
    case HPPA_OP_TYPE_CMPBF:
3402
0
    case HPPA_OP_TYPE_CMPBDWT:
3403
0
    case HPPA_OP_TYPE_CMPBDWF:
3404
0
    case HPPA_OP_TYPE_ADDBT:
3405
0
    case HPPA_OP_TYPE_ADDBF:
3406
0
    case HPPA_OP_TYPE_MOVB:
3407
0
      CREATE_GR_REG(MI, r2);
3408
0
      CREATE_GR_REG(MI, r1);
3409
0
      MCOperand_CreateImm0(MI, extract_12(insn));
3410
0
      break;
3411
0
    case HPPA_OP_TYPE_CMPIBT:
3412
0
    case HPPA_OP_TYPE_CMPIBF:
3413
0
    case HPPA_OP_TYPE_CMPIBDW:
3414
0
    case HPPA_OP_TYPE_ADDIBT:
3415
0
    case HPPA_OP_TYPE_ADDIBF:
3416
0
    case HPPA_OP_TYPE_MOVIB:
3417
0
      MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5));
3418
0
      CREATE_GR_REG(MI, r1);
3419
0
      MCOperand_CreateImm0(MI, extract_12(insn));
3420
0
      break;
3421
0
    case HPPA_OP_TYPE_BBS:
3422
0
    case HPPA_OP_TYPE_BB:
3423
0
      CREATE_GR_REG(MI, r2);
3424
0
      if ((opcode & 1) == 1) {
3425
0
        MCOperand_CreateImm0(MI, r1);
3426
0
      } else {
3427
0
        CREATE_CR_REG(MI, 11);
3428
0
      }
3429
0
      MCOperand_CreateImm0(MI, extract_12(insn));
3430
0
      break;
3431
0
    default:
3432
0
      return false;
3433
0
    }
3434
0
    fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI),
3435
0
              ud->mode);
3436
0
    return true;
3437
0
  }
3438
0
  if ((opcode & 1) == 0 || opcode == HPPA_OP_TYPE_BB) {
3439
0
    CREATE_GR_REG(MI, r2);
3440
0
  } else {
3441
0
    MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5));
3442
0
  }
3443
0
  if (opcode == HPPA_OP_TYPE_BB) {
3444
0
    MCOperand_CreateImm0(MI, r1);
3445
0
  } else if (opcode != HPPA_OP_TYPE_BBS) {
3446
0
    CREATE_GR_REG(MI, r1);
3447
0
  }
3448
0
  MCOperand_CreateImm0(MI, extract_12(insn));
3449
0
  fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), ud->mode);
3450
0
  return true;
3451
0
}
3452
3453
static void fill_load_insn_name(MCInst *MI, uint32_t opcode)
3454
0
{
3455
0
  switch (opcode) {
3456
0
  case HPPA_OP_TYPE_LDB:
3457
0
    MCInst_setOpcode(MI, HPPA_INS_LDB);
3458
0
    break;
3459
0
  case HPPA_OP_TYPE_LDH:
3460
0
    MCInst_setOpcode(MI, HPPA_INS_LDH);
3461
0
    break;
3462
0
  case HPPA_OP_TYPE_LDW:
3463
0
    MCInst_setOpcode(MI, HPPA_INS_LDW);
3464
0
    break;
3465
0
  case HPPA_OP_TYPE_LDWM:
3466
0
    if (MODE_IS_HPPA_20(MI->csh->mode)) {
3467
0
      MCInst_setOpcode(MI, HPPA_INS_LDW);
3468
0
    } else {
3469
0
      MCInst_setOpcode(MI, HPPA_INS_LDWM);
3470
0
    }
3471
0
    break;
3472
0
  default:
3473
0
    break;
3474
0
  }
3475
0
}
3476
3477
static void fill_store_insn_name(MCInst *MI, uint32_t opcode)
3478
0
{
3479
0
  switch (opcode) {
3480
0
  case HPPA_OP_TYPE_STB:
3481
0
    MCInst_setOpcode(MI, HPPA_INS_STB);
3482
0
    break;
3483
0
  case HPPA_OP_TYPE_STH:
3484
0
    MCInst_setOpcode(MI, HPPA_INS_STH);
3485
0
    break;
3486
0
  case HPPA_OP_TYPE_STW:
3487
0
    MCInst_setOpcode(MI, HPPA_INS_STW);
3488
0
    break;
3489
0
  case HPPA_OP_TYPE_STWM:
3490
0
    if (MODE_IS_HPPA_20(MI->csh->mode)) {
3491
0
      MCInst_setOpcode(MI, HPPA_INS_STW);
3492
0
    } else {
3493
0
      MCInst_setOpcode(MI, HPPA_INS_STWM);
3494
0
    }
3495
0
    break;
3496
0
  default:
3497
0
    break;
3498
0
  }
3499
0
}
3500
3501
static bool decode_cmpclr(const cs_struct *ud, MCInst *MI, uint32_t insn)
3502
0
{
3503
0
  uint32_t cond = (get_insn_bit(insn, 19) << 3) |
3504
0
      get_insn_field(insn, 16, 18);
3505
0
  uint32_t d = get_insn_bit(insn, 20);
3506
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3507
0
    MCInst_setOpcode(MI, HPPA_INS_CMPICLR);
3508
0
  } else {
3509
0
    MCInst_setOpcode(MI, HPPA_INS_COMICLR);
3510
0
  }
3511
3512
0
  MCOperand_CreateImm0(MI,
3513
0
           LowSignExtend64(get_insn_field(insn, 21, 31), 11));
3514
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3515
0
  CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
3516
3517
0
  if (d == 0) {
3518
0
    push_str_modifier(HPPA_EXT_REF(MI), compare_cond_names[cond]);
3519
0
  } else {
3520
0
    push_str_modifier(HPPA_EXT_REF(MI),
3521
0
          compare_cond_64_names[cond]);
3522
0
  }
3523
0
  return true;
3524
0
}
3525
3526
static bool decode_be(const cs_struct *ud, MCInst *MI, uint32_t insn)
3527
0
{
3528
0
  uint32_t opcode = insn >> 26;
3529
0
  uint32_t n = get_insn_bit(insn, 30);
3530
0
  bool mode = MODE_IS_HPPA_20(ud->mode);
3531
0
  if (opcode == HPPA_OP_TYPE_BLE) {
3532
0
    if (!mode) {
3533
0
      MCInst_setOpcode(MI, HPPA_INS_BLE);
3534
0
    } else {
3535
0
      MCInst_setOpcode(MI, HPPA_INS_BE);
3536
0
      push_str_modifier(HPPA_EXT_REF(MI), "l");
3537
0
      HPPA_EXT_REF(MI)->is_alternative = true;
3538
0
    }
3539
0
  } else {
3540
0
    MCInst_setOpcode(MI, HPPA_INS_BE);
3541
0
  }
3542
3543
0
  MCOperand_CreateImm0(MI, extract_17(insn));
3544
0
  CREATE_SR_REG(MI, extract_3(insn));
3545
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3546
0
  if (opcode == HPPA_OP_TYPE_BLE && mode) {
3547
0
    CREATE_SR_REG(MI, 0);
3548
0
    CREATE_GR_REG(MI, 31);
3549
0
  }
3550
0
  if (n == 1) {
3551
0
    push_str_modifier(HPPA_EXT_REF(MI), "n");
3552
0
  }
3553
0
  return true;
3554
0
}
3555
3556
static bool decode_float_ldst(const cs_struct *ud, MCInst *MI, uint32_t insn)
3557
0
{
3558
0
  uint32_t opcode = insn >> 26;
3559
0
  uint32_t a = get_insn_bit(insn, 29);
3560
0
  uint32_t disp = extract_16(insn, MODE_IS_HPPA_20W(ud->mode));
3561
0
  disp &= ~3;
3562
3563
0
  if (opcode == HPPA_OP_TYPE_FLDW) {
3564
0
    MCInst_setOpcode(MI, HPPA_INS_FLDW);
3565
0
    MCOperand_CreateImm0(MI, disp);
3566
0
    CREATE_SR_REG(MI, get_insn_field(insn, 16, 17));
3567
0
    CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3568
0
    CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15));
3569
0
  } else {
3570
0
    MCInst_setOpcode(MI, HPPA_INS_FSTW);
3571
0
    CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15));
3572
0
    MCOperand_CreateImm0(MI, disp);
3573
0
    CREATE_SR_REG(MI, get_insn_field(insn, 16, 17));
3574
0
    CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3575
0
  }
3576
3577
0
  if (a == 0) {
3578
0
    push_str_modifier(HPPA_EXT_REF(MI), "ma");
3579
0
  } else {
3580
0
    push_str_modifier(HPPA_EXT_REF(MI), "mb");
3581
0
  }
3582
0
  return true;
3583
0
}
3584
3585
static bool decode_fmpy(const cs_struct *ud, MCInst *MI, uint32_t insn)
3586
0
{
3587
0
  uint32_t opcode = insn >> 26;
3588
0
  uint32_t rm1 = get_insn_field(insn, 6, 10);
3589
0
  uint32_t rm2 = get_insn_field(insn, 11, 15);
3590
0
  uint32_t ta = get_insn_field(insn, 16, 20);
3591
0
  uint32_t ra = get_insn_field(insn, 21, 25);
3592
0
  uint32_t tm = get_insn_field(insn, 27, 31);
3593
0
  uint32_t fmt = get_insn_field(insn, 26, 26);
3594
3595
0
  if (opcode == HPPA_OP_TYPE_FMPYADD) {
3596
0
    MCInst_setOpcode(MI, HPPA_INS_FMPYADD);
3597
0
  } else {
3598
0
    MCInst_setOpcode(MI, HPPA_INS_FMPYSUB);
3599
0
  }
3600
3601
0
  if (fmt == 0) {
3602
0
    push_str_modifier(HPPA_EXT_REF(MI), "dbl");
3603
0
    CREATE_FPR_REG(MI, rm1);
3604
0
    CREATE_FPR_REG(MI, rm2);
3605
0
    CREATE_FPR_REG(MI, tm);
3606
0
    CREATE_FPR_REG(MI, ra);
3607
0
    CREATE_FPR_REG(MI, ta);
3608
0
  } else {
3609
0
    push_str_modifier(HPPA_EXT_REF(MI), "sgl");
3610
0
    CREATE_SP_FPR_REG(MI, rm1);
3611
0
    CREATE_SP_FPR_REG(MI, rm2);
3612
0
    CREATE_SP_FPR_REG(MI, tm);
3613
0
    CREATE_SP_FPR_REG(MI, ra);
3614
0
    CREATE_SP_FPR_REG(MI, ta);
3615
0
  }
3616
3617
0
  return true;
3618
0
}
3619
3620
static bool decode_load(const cs_struct *ud, MCInst *MI, uint32_t insn)
3621
0
{
3622
0
  uint32_t opcode = insn >> 26;
3623
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3624
0
    int32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode));
3625
0
    if (opcode == HPPA_OP_TYPE_LDWM) {
3626
0
      if (d < 0) {
3627
0
        push_str_modifier(HPPA_EXT_REF(MI), "mb");
3628
0
      } else {
3629
0
        push_str_modifier(HPPA_EXT_REF(MI), "ma");
3630
0
      }
3631
0
    }
3632
0
    MCOperand_CreateImm0(MI, d);
3633
0
  } else {
3634
0
    MCOperand_CreateImm0(MI, extract_14(insn));
3635
0
  }
3636
0
  CREATE_SR_REG(MI, get_insn_field(insn, 16, 17));
3637
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3638
0
  CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
3639
0
  return true;
3640
0
}
3641
3642
static bool decode_store(const cs_struct *ud, MCInst *MI, uint32_t insn)
3643
0
{
3644
0
  uint32_t opcode = insn >> 26;
3645
0
  CREATE_GR_REG(MI, get_insn_field(insn, 11, 15));
3646
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3647
0
    int d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode));
3648
0
    if (opcode == HPPA_OP_TYPE_STWM) {
3649
0
      if (d < 0) {
3650
0
        push_str_modifier(HPPA_EXT_REF(MI), "mb");
3651
0
      } else {
3652
0
        push_str_modifier(HPPA_EXT_REF(MI), "ma");
3653
0
      }
3654
0
    }
3655
0
    MCOperand_CreateImm0(MI, d);
3656
0
  } else {
3657
0
    MCOperand_CreateImm0(MI, extract_14(insn));
3658
0
  }
3659
0
  CREATE_SR_REG(MI, get_insn_field(insn, 16, 17));
3660
0
  CREATE_GR_REG(MI, get_insn_field(insn, 6, 10));
3661
0
  return true;
3662
0
}
3663
3664
static bool getInstruction(const cs_struct *ud, const uint8_t *code,
3665
         size_t code_len, MCInst *MI)
3666
0
{
3667
0
  if (code_len < 4)
3668
0
    return false;
3669
3670
0
  MCInst_clear(MI);
3671
3672
0
  uint32_t full_insn = readBytes32(MI, code);
3673
0
  uint8_t opcode = full_insn >> 26;
3674
3675
0
  if (MODE_IS_HPPA_20(ud->mode)) {
3676
0
    switch (opcode) {
3677
0
    case HPPA_OP_TYPE_LOADDW:
3678
0
    case HPPA_OP_TYPE_STOREDW:
3679
0
      fill_ldst_dw_insn_name(MI, full_insn);
3680
0
      return decode_ldst_dw(ud, MI, full_insn);
3681
0
    case HPPA_OP_TYPE_LOADW:
3682
0
    case HPPA_OP_TYPE_STOREW:
3683
0
      fill_ldst_w_insn_name(MI, full_insn);
3684
0
      return decode_ldst_w(ud, MI, full_insn);
3685
0
    case HPPA_OP_TYPE_SHEXDEP2:
3686
0
      MCInst_setOpcode(MI, HPPA_INS_EXTRD);
3687
0
      return decode_shexdep2(MI, full_insn);
3688
0
    case HPPA_OP_TYPE_SHEXDEP3:
3689
0
    case HPPA_OP_TYPE_SHEXDEP4:
3690
0
      return decode_shexdep3(ud, MI, full_insn);
3691
0
    case HPPA_OP_TYPE_MULTMED:
3692
0
      fill_multmed_insn_name(MI, full_insn);
3693
0
      return decode_multmed(MI, full_insn);
3694
0
    case HPPA_OP_TYPE_FPFUSED:
3695
0
      fill_fpfused_insn_name(MI, full_insn);
3696
0
      return decode_fpfused(ud, MI, full_insn);
3697
0
    case HPPA_OP_TYPE_FLDW:
3698
0
    case HPPA_OP_TYPE_FSTW:
3699
0
      return decode_float_ldst(ud, MI, full_insn);
3700
0
    case HPPA_OP_TYPE_CMPBDWT:
3701
0
    case HPPA_OP_TYPE_CMPBDWF:
3702
0
    case HPPA_OP_TYPE_CMPIBDW:
3703
0
      fill_action_and_branch_insn_name(MI, opcode);
3704
0
      return fill_action_and_branch(ud, MI, full_insn);
3705
0
    default:
3706
0
      break;
3707
0
    }
3708
0
  }
3709
3710
0
  switch (opcode) {
3711
0
  case HPPA_OP_TYPE_SYSOP:
3712
0
    fill_sysop_insn_name(MI, full_insn);
3713
0
    return decode_sysop(ud, MI, full_insn);
3714
0
  case HPPA_OP_TYPE_MEMMGMT:
3715
0
    fill_memmgmt_insn_name(MI, full_insn);
3716
0
    return decode_memmgmt(ud, MI, full_insn);
3717
0
  case HPPA_OP_TYPE_ALU:
3718
0
    fill_alu_insn_name(MI, full_insn);
3719
0
    return decode_alu(ud, MI, full_insn);
3720
0
  case HPPA_OP_TYPE_IDXMEM:
3721
0
    fill_idxmem_insn_name(MI, full_insn);
3722
0
    return decode_idxmem(ud, MI, full_insn);
3723
0
  case HPPA_OP_TYPE_ADDIT:
3724
0
  case HPPA_OP_TYPE_ADDI:
3725
0
  case HPPA_OP_TYPE_SUBI:
3726
0
    fill_arith_imm_insn_name(MI, full_insn);
3727
0
    return decode_arith_imm(ud, MI, full_insn);
3728
0
  case HPPA_OP_TYPE_SHEXDEP0:
3729
0
    fill_shexdep0_insn_name(MI, full_insn);
3730
0
    return decode_shexdep0(ud, MI, full_insn);
3731
0
  case HPPA_OP_TYPE_SHEXDEP1:
3732
0
    fill_shexdep1_insn_name(MI, full_insn);
3733
0
    return decode_shexdep1(ud, MI, full_insn);
3734
0
  case HPPA_OP_TYPE_BRANCH:
3735
0
    fill_branch_insn_name(MI, full_insn);
3736
0
    return decode_branch(ud, MI, full_insn);
3737
0
  case HPPA_OP_TYPE_COPRW:
3738
0
  case HPPA_OP_TYPE_COPRDW:
3739
0
    fill_corpdw_insn_name(MI, full_insn);
3740
0
    return decode_corpdw(ud, MI, full_insn);
3741
0
  case HPPA_OP_TYPE_SPOP:
3742
0
    fill_spop_insn_name(MI, full_insn);
3743
0
    return decode_spop(ud, MI, full_insn);
3744
0
  case HPPA_OP_TYPE_COPR:
3745
0
    fill_copr_insn_name(MI, full_insn);
3746
0
    return decode_copr(ud, MI, full_insn);
3747
0
  case HPPA_OP_TYPE_FLOAT:
3748
0
    fill_float_insn_name(MI, full_insn);
3749
0
    return decode_float(ud, MI, full_insn);
3750
0
  case HPPA_OP_TYPE_DIAG:
3751
0
    MCInst_setOpcode(MI, HPPA_INS_DIAG);
3752
0
    MCOperand_CreateImm0(MI, get_insn_field(full_insn, 6, 31));
3753
0
    return true;
3754
0
  case HPPA_OP_TYPE_FMPYADD:
3755
0
  case HPPA_OP_TYPE_FMPYSUB:
3756
0
    return decode_fmpy(ud, MI, full_insn);
3757
0
  case HPPA_OP_TYPE_LDIL:
3758
0
  case HPPA_OP_TYPE_ADDIL:
3759
0
    if (opcode == HPPA_OP_TYPE_LDIL) {
3760
0
      MCInst_setOpcode(MI, HPPA_INS_LDIL);
3761
0
    } else {
3762
0
      MCInst_setOpcode(MI, HPPA_INS_ADDIL);
3763
0
    }
3764
0
    MCOperand_CreateImm0(MI, extract_21(full_insn));
3765
0
    CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10));
3766
0
    return true;
3767
0
  case HPPA_OP_TYPE_LDO:
3768
0
    MCInst_setOpcode(MI, HPPA_INS_LDO);
3769
0
    if (MODE_IS_HPPA_20(ud->mode)) {
3770
0
      MCOperand_CreateImm0(
3771
0
        MI, extract_16(full_insn,
3772
0
                 MODE_IS_HPPA_20W(ud->mode)));
3773
0
    } else {
3774
0
      MCOperand_CreateImm0(MI, extract_14(full_insn));
3775
0
    }
3776
0
    CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10));
3777
0
    CREATE_GR_REG(MI, get_insn_field(full_insn, 11, 15));
3778
0
    return true;
3779
0
  case HPPA_OP_TYPE_LDB:
3780
0
  case HPPA_OP_TYPE_LDH:
3781
0
  case HPPA_OP_TYPE_LDW:
3782
0
  case HPPA_OP_TYPE_LDWM:
3783
0
    fill_load_insn_name(MI, opcode);
3784
0
    return decode_load(ud, MI, full_insn);
3785
0
  case HPPA_OP_TYPE_STB:
3786
0
  case HPPA_OP_TYPE_STH:
3787
0
  case HPPA_OP_TYPE_STW:
3788
0
  case HPPA_OP_TYPE_STWM:
3789
0
    fill_store_insn_name(MI, opcode);
3790
0
    return decode_store(ud, MI, full_insn);
3791
0
  case HPPA_OP_TYPE_CMPBT:
3792
0
  case HPPA_OP_TYPE_CMPBF:
3793
0
  case HPPA_OP_TYPE_ADDBT:
3794
0
  case HPPA_OP_TYPE_ADDBF:
3795
0
  case HPPA_OP_TYPE_MOVB:
3796
0
  case HPPA_OP_TYPE_CMPIBT:
3797
0
  case HPPA_OP_TYPE_CMPIBF:
3798
0
  case HPPA_OP_TYPE_ADDIBT:
3799
0
  case HPPA_OP_TYPE_ADDIBF:
3800
0
  case HPPA_OP_TYPE_MOVIB:
3801
0
  case HPPA_OP_TYPE_BBS:
3802
0
  case HPPA_OP_TYPE_BB:
3803
0
    fill_action_and_branch_insn_name(MI, opcode);
3804
0
    return fill_action_and_branch(ud, MI, full_insn);
3805
0
  case HPPA_OP_TYPE_CMPICLR:
3806
0
    return decode_cmpclr(ud, MI, full_insn);
3807
0
  case HPPA_OP_TYPE_BE:
3808
0
  case HPPA_OP_TYPE_BLE:
3809
0
    return decode_be(ud, MI, full_insn);
3810
0
  default:
3811
0
    return false;
3812
0
  }
3813
0
}
3814
3815
void init_details(MCInst *MI)
3816
0
{
3817
0
  cs_detail *detail = get_detail(MI);
3818
0
  if (detail) {
3819
0
    memset(detail, 0, offsetof(cs_detail, hppa) + sizeof(cs_hppa));
3820
0
  }
3821
0
}
3822
3823
bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len,
3824
       MCInst *instr, uint16_t *size, uint64_t address,
3825
       void *info)
3826
0
{
3827
0
  cs_struct *cs = (cs_struct *)ud;
3828
0
  init_details(instr);
3829
0
  if (!getInstruction(cs, code, code_len, instr)) {
3830
0
    *size = 0;
3831
0
    return false;
3832
0
  }
3833
0
  *size = 4;
3834
0
  return true;
3835
0
}
3836
3837
#endif