Coverage Report

Created: 2025-07-04 06:11

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
39.8k
{
20
39.8k
  static const uint32_t OpInfo[] = {
21
39.8k
    0U, // PHI
22
39.8k
    0U, // INLINEASM
23
39.8k
    0U, // CFI_INSTRUCTION
24
39.8k
    0U, // EH_LABEL
25
39.8k
    0U, // GC_LABEL
26
39.8k
    0U, // KILL
27
39.8k
    0U, // EXTRACT_SUBREG
28
39.8k
    0U, // INSERT_SUBREG
29
39.8k
    0U, // IMPLICIT_DEF
30
39.8k
    0U, // SUBREG_TO_REG
31
39.8k
    0U, // COPY_TO_REGCLASS
32
39.8k
    2452U,  // DBG_VALUE
33
39.8k
    0U, // REG_SEQUENCE
34
39.8k
    0U, // COPY
35
39.8k
    2445U,  // BUNDLE
36
39.8k
    2462U,  // LIFETIME_START
37
39.8k
    2432U,  // LIFETIME_END
38
39.8k
    0U, // STACKMAP
39
39.8k
    0U, // PATCHPOINT
40
39.8k
    0U, // LOAD_STACK_GUARD
41
39.8k
    0U, // STATEPOINT
42
39.8k
    0U, // FRAME_ALLOC
43
39.8k
    4688U,  // ADDCCri
44
39.8k
    4688U,  // ADDCCrr
45
39.8k
    5925U,  // ADDCri
46
39.8k
    5925U,  // ADDCrr
47
39.8k
    4772U,  // ADDEri
48
39.8k
    4772U,  // ADDErr
49
39.8k
    4786U,  // ADDXC
50
39.8k
    4678U,  // ADDXCCC
51
39.8k
    4808U,  // ADDXri
52
39.8k
    4808U,  // ADDXrr
53
39.8k
    4808U,  // ADDri
54
39.8k
    4808U,  // ADDrr
55
39.8k
    74166U, // ADJCALLSTACKDOWN
56
39.8k
    74185U, // ADJCALLSTACKUP
57
39.8k
    5497U,  // ALIGNADDR
58
39.8k
    5127U,  // ALIGNADDRL
59
39.8k
    4695U,  // ANDCCri
60
39.8k
    4695U,  // ANDCCrr
61
39.8k
    4718U,  // ANDNCCri
62
39.8k
    4718U,  // ANDNCCrr
63
39.8k
    5182U,  // ANDNri
64
39.8k
    5182U,  // ANDNrr
65
39.8k
    5182U,  // ANDXNrr
66
39.8k
    4876U,  // ANDXri
67
39.8k
    4876U,  // ANDXrr
68
39.8k
    4876U,  // ANDri
69
39.8k
    4876U,  // ANDrr
70
39.8k
    4502U,  // ARRAY16
71
39.8k
    4255U,  // ARRAY32
72
39.8k
    4526U,  // ARRAY8
73
39.8k
    0U, // ATOMIC_LOAD_ADD_32
74
39.8k
    0U, // ATOMIC_LOAD_ADD_64
75
39.8k
    0U, // ATOMIC_LOAD_AND_32
76
39.8k
    0U, // ATOMIC_LOAD_AND_64
77
39.8k
    0U, // ATOMIC_LOAD_MAX_32
78
39.8k
    0U, // ATOMIC_LOAD_MAX_64
79
39.8k
    0U, // ATOMIC_LOAD_MIN_32
80
39.8k
    0U, // ATOMIC_LOAD_MIN_64
81
39.8k
    0U, // ATOMIC_LOAD_NAND_32
82
39.8k
    0U, // ATOMIC_LOAD_NAND_64
83
39.8k
    0U, // ATOMIC_LOAD_OR_32
84
39.8k
    0U, // ATOMIC_LOAD_OR_64
85
39.8k
    0U, // ATOMIC_LOAD_SUB_32
86
39.8k
    0U, // ATOMIC_LOAD_SUB_64
87
39.8k
    0U, // ATOMIC_LOAD_UMAX_32
88
39.8k
    0U, // ATOMIC_LOAD_UMAX_64
89
39.8k
    0U, // ATOMIC_LOAD_UMIN_32
90
39.8k
    0U, // ATOMIC_LOAD_UMIN_64
91
39.8k
    0U, // ATOMIC_LOAD_XOR_32
92
39.8k
    0U, // ATOMIC_LOAD_XOR_64
93
39.8k
    0U, // ATOMIC_SWAP_64
94
39.8k
    74271U, // BA
95
39.8k
    1194492U, // BCOND
96
39.8k
    1260028U, // BCONDA
97
39.8k
    17659U, // BINDri
98
39.8k
    17659U, // BINDrr
99
39.8k
    5065U,  // BMASK
100
39.8k
    145915U,  // BPFCC
101
39.8k
    211451U,  // BPFCCA
102
39.8k
    276987U,  // BPFCCANT
103
39.8k
    342523U,  // BPFCCNT
104
39.8k
    2106465U, // BPGEZapn
105
39.8k
    2105838U, // BPGEZapt
106
39.8k
    2106532U, // BPGEZnapn
107
39.8k
    2107288U, // BPGEZnapt
108
39.8k
    2106489U, // BPGZapn
109
39.8k
    2105856U, // BPGZapt
110
39.8k
    2106552U, // BPGZnapn
111
39.8k
    2107384U, // BPGZnapt
112
39.8k
    1456636U, // BPICC
113
39.8k
    473596U,  // BPICCA
114
39.8k
    539132U,  // BPICCANT
115
39.8k
    604668U,  // BPICCNT
116
39.8k
    2106477U, // BPLEZapn
117
39.8k
    2105847U, // BPLEZapt
118
39.8k
    2106542U, // BPLEZnapn
119
39.8k
    2107337U, // BPLEZnapt
120
39.8k
    2106500U, // BPLZapn
121
39.8k
    2105864U, // BPLZapt
122
39.8k
    2106561U, // BPLZnapn
123
39.8k
    2107428U, // BPLZnapt
124
39.8k
    2106511U, // BPNZapn
125
39.8k
    2105872U, // BPNZapt
126
39.8k
    2106570U, // BPNZnapn
127
39.8k
    2107472U, // BPNZnapt
128
39.8k
    1718780U, // BPXCC
129
39.8k
    735740U,  // BPXCCA
130
39.8k
    801276U,  // BPXCCANT
131
39.8k
    866812U,  // BPXCCNT
132
39.8k
    2106522U, // BPZapn
133
39.8k
    2105880U, // BPZapt
134
39.8k
    2106579U, // BPZnapn
135
39.8k
    2107505U, // BPZnapt
136
39.8k
    4983U,  // BSHUFFLE
137
39.8k
    74742U, // CALL
138
39.8k
    17398U, // CALLri
139
39.8k
    17398U, // CALLrr
140
39.8k
    924148U,  // CASXrr
141
39.8k
    924129U,  // CASrr
142
39.8k
    74001U, // CMASK16
143
39.8k
    73833U, // CMASK32
144
39.8k
    74150U, // CMASK8
145
39.8k
    2106607U, // CMPri
146
39.8k
    2106607U, // CMPrr
147
39.8k
    4332U,  // EDGE16
148
39.8k
    5081U,  // EDGE16L
149
39.8k
    5198U,  // EDGE16LN
150
39.8k
    5165U,  // EDGE16N
151
39.8k
    4164U,  // EDGE32
152
39.8k
    5072U,  // EDGE32L
153
39.8k
    5188U,  // EDGE32LN
154
39.8k
    5156U,  // EDGE32N
155
39.8k
    4511U,  // EDGE8
156
39.8k
    5090U,  // EDGE8L
157
39.8k
    5208U,  // EDGE8LN
158
39.8k
    5174U,  // EDGE8N
159
39.8k
    1053516U, // FABSD
160
39.8k
    1054031U, // FABSQ
161
39.8k
    1054376U, // FABSS
162
39.8k
    4813U,  // FADDD
163
39.8k
    5383U,  // FADDQ
164
39.8k
    5645U,  // FADDS
165
39.8k
    4648U,  // FALIGNADATA
166
39.8k
    4875U,  // FAND
167
39.8k
    4112U,  // FANDNOT1
168
39.8k
    5544U,  // FANDNOT1S
169
39.8k
    4271U,  // FANDNOT2
170
39.8k
    5591U,  // FANDNOT2S
171
39.8k
    5677U,  // FANDS
172
39.8k
    1194491U, // FBCOND
173
39.8k
    1260027U, // FBCONDA
174
39.8k
    4394U,  // FCHKSM16
175
39.8k
    2106173U, // FCMPD
176
39.8k
    4413U,  // FCMPEQ16
177
39.8k
    4226U,  // FCMPEQ32
178
39.8k
    4432U,  // FCMPGT16
179
39.8k
    4245U,  // FCMPGT32
180
39.8k
    4340U,  // FCMPLE16
181
39.8k
    4172U,  // FCMPLE32
182
39.8k
    4350U,  // FCMPNE16
183
39.8k
    4182U,  // FCMPNE32
184
39.8k
    2106696U, // FCMPQ
185
39.8k
    2107005U, // FCMPS
186
39.8k
    4960U,  // FDIVD
187
39.8k
    5475U,  // FDIVQ
188
39.8k
    5815U,  // FDIVS
189
39.8k
    5405U,  // FDMULQ
190
39.8k
    1053620U, // FDTOI
191
39.8k
    1053996U, // FDTOQ
192
39.8k
    1054305U, // FDTOS
193
39.8k
    1054536U, // FDTOX
194
39.8k
    1053464U, // FEXPAND
195
39.8k
    4820U,  // FHADDD
196
39.8k
    5652U,  // FHADDS
197
39.8k
    4800U,  // FHSUBD
198
39.8k
    5637U,  // FHSUBS
199
39.8k
    1053473U, // FITOD
200
39.8k
    1054003U, // FITOQ
201
39.8k
    1054312U, // FITOS
202
39.8k
    6300484U, // FLCMPD
203
39.8k
    6301316U, // FLCMPS
204
39.8k
    2606U,  // FLUSHW
205
39.8k
    4404U,  // FMEAN16
206
39.8k
    1053543U, // FMOVD
207
39.8k
    1006078U, // FMOVD_FCC
208
39.8k
    23484926U,  // FMOVD_ICC
209
39.8k
    23747070U,  // FMOVD_XCC
210
39.8k
    1054058U, // FMOVQ
211
39.8k
    1006102U, // FMOVQ_FCC
212
39.8k
    23484950U,  // FMOVQ_ICC
213
39.8k
    23747094U,  // FMOVQ_XCC
214
39.8k
    6018U,  // FMOVRGEZD
215
39.8k
    6029U,  // FMOVRGEZQ
216
39.8k
    6056U,  // FMOVRGEZS
217
39.8k
    6116U,  // FMOVRGZD
218
39.8k
    6126U,  // FMOVRGZQ
219
39.8k
    6150U,  // FMOVRGZS
220
39.8k
    6067U,  // FMOVRLEZD
221
39.8k
    6078U,  // FMOVRLEZQ
222
39.8k
    6105U,  // FMOVRLEZS
223
39.8k
    6160U,  // FMOVRLZD
224
39.8k
    6170U,  // FMOVRLZQ
225
39.8k
    6194U,  // FMOVRLZS
226
39.8k
    6204U,  // FMOVRNZD
227
39.8k
    6214U,  // FMOVRNZQ
228
39.8k
    6238U,  // FMOVRNZS
229
39.8k
    6009U,  // FMOVRZD
230
39.8k
    6248U,  // FMOVRZQ
231
39.8k
    6269U,  // FMOVRZS
232
39.8k
    1054398U, // FMOVS
233
39.8k
    1006114U, // FMOVS_FCC
234
39.8k
    23484962U,  // FMOVS_ICC
235
39.8k
    23747106U,  // FMOVS_XCC
236
39.8k
    4490U,  // FMUL8SUX16
237
39.8k
    4465U,  // FMUL8ULX16
238
39.8k
    4442U,  // FMUL8X16
239
39.8k
    5098U,  // FMUL8X16AL
240
39.8k
    5849U,  // FMUL8X16AU
241
39.8k
    4860U,  // FMULD
242
39.8k
    4477U,  // FMULD8SUX16
243
39.8k
    4452U,  // FMULD8ULX16
244
39.8k
    5413U,  // FMULQ
245
39.8k
    5714U,  // FMULS
246
39.8k
    4837U,  // FNADDD
247
39.8k
    5669U,  // FNADDS
248
39.8k
    4881U,  // FNAND
249
39.8k
    5684U,  // FNANDS
250
39.8k
    1053429U, // FNEGD
251
39.8k
    1053974U, // FNEGQ
252
39.8k
    1054283U, // FNEGS
253
39.8k
    4828U,  // FNHADDD
254
39.8k
    5660U,  // FNHADDS
255
39.8k
    4828U,  // FNMULD
256
39.8k
    5660U,  // FNMULS
257
39.8k
    5513U,  // FNOR
258
39.8k
    5778U,  // FNORS
259
39.8k
    1052698U, // FNOT1
260
39.8k
    1054131U, // FNOT1S
261
39.8k
    1052857U, // FNOT2
262
39.8k
    1054178U, // FNOT2S
263
39.8k
    5660U,  // FNSMULD
264
39.8k
    74625U, // FONE
265
39.8k
    75324U, // FONES
266
39.8k
    5508U,  // FOR
267
39.8k
    4129U,  // FORNOT1
268
39.8k
    5563U,  // FORNOT1S
269
39.8k
    4288U,  // FORNOT2
270
39.8k
    5610U,  // FORNOT2S
271
39.8k
    5772U,  // FORS
272
39.8k
    1052936U, // FPACK16
273
39.8k
    4192U,  // FPACK32
274
39.8k
    1054507U, // FPACKFIX
275
39.8k
    4323U,  // FPADD16
276
39.8k
    5620U,  // FPADD16S
277
39.8k
    4155U,  // FPADD32
278
39.8k
    5573U,  // FPADD32S
279
39.8k
    4297U,  // FPADD64
280
39.8k
    4974U,  // FPMERGE
281
39.8k
    4314U,  // FPSUB16
282
39.8k
    4580U,  // FPSUB16S
283
39.8k
    4146U,  // FPSUB32
284
39.8k
    4570U,  // FPSUB32S
285
39.8k
    1053480U, // FQTOD
286
39.8k
    1053627U, // FQTOI
287
39.8k
    1054319U, // FQTOS
288
39.8k
    1054552U, // FQTOX
289
39.8k
    4423U,  // FSLAS16
290
39.8k
    4236U,  // FSLAS32
291
39.8k
    4378U,  // FSLL16
292
39.8k
    4210U,  // FSLL32
293
39.8k
    4867U,  // FSMULD
294
39.8k
    1053523U, // FSQRTD
295
39.8k
    1054038U, // FSQRTQ
296
39.8k
    1054383U, // FSQRTS
297
39.8k
    4306U,  // FSRA16
298
39.8k
    4138U,  // FSRA32
299
39.8k
    1052681U, // FSRC1
300
39.8k
    1054112U, // FSRC1S
301
39.8k
    1052840U, // FSRC2
302
39.8k
    1054159U, // FSRC2S
303
39.8k
    4386U,  // FSRL16
304
39.8k
    4218U,  // FSRL32
305
39.8k
    1053487U, // FSTOD
306
39.8k
    1053634U, // FSTOI
307
39.8k
    1054010U, // FSTOQ
308
39.8k
    1054559U, // FSTOX
309
39.8k
    4793U,  // FSUBD
310
39.8k
    5376U,  // FSUBQ
311
39.8k
    5630U,  // FSUBS
312
39.8k
    5519U,  // FXNOR
313
39.8k
    5785U,  // FXNORS
314
39.8k
    5526U,  // FXOR
315
39.8k
    5793U,  // FXORS
316
39.8k
    1053494U, // FXTOD
317
39.8k
    1054017U, // FXTOQ
318
39.8k
    1054326U, // FXTOS
319
39.8k
    74984U, // FZERO
320
39.8k
    75353U, // FZEROS
321
39.8k
    24584U, // GETPCX
322
39.8k
    1078273U, // JMPLri
323
39.8k
    1078273U, // JMPLrr
324
39.8k
    1997243U, // LDDFri
325
39.8k
    1997243U, // LDDFrr
326
39.8k
    1997249U, // LDFri
327
39.8k
    1997249U, // LDFrr
328
39.8k
    1997275U, // LDQFri
329
39.8k
    1997275U, // LDQFrr
330
39.8k
    1997229U, // LDSBri
331
39.8k
    1997229U, // LDSBrr
332
39.8k
    1997254U, // LDSHri
333
39.8k
    1997254U, // LDSHrr
334
39.8k
    1997287U, // LDSWri
335
39.8k
    1997287U, // LDSWrr
336
39.8k
    1997236U, // LDUBri
337
39.8k
    1997236U, // LDUBrr
338
39.8k
    1997261U, // LDUHri
339
39.8k
    1997261U, // LDUHrr
340
39.8k
    1997294U, // LDXri
341
39.8k
    1997294U, // LDXrr
342
39.8k
    1997249U, // LDri
343
39.8k
    1997249U, // LDrr
344
39.8k
    33480U, // LEAX_ADDri
345
39.8k
    33480U, // LEA_ADDri
346
39.8k
    1054405U, // LZCNT
347
39.8k
    75121U, // MEMBARi
348
39.8k
    1054543U, // MOVDTOX
349
39.8k
    1006122U, // MOVFCCri
350
39.8k
    1006122U, // MOVFCCrr
351
39.8k
    23484970U,  // MOVICCri
352
39.8k
    23484970U,  // MOVICCrr
353
39.8k
    6047U,  // MOVRGEZri
354
39.8k
    6047U,  // MOVRGEZrr
355
39.8k
    6142U,  // MOVRGZri
356
39.8k
    6142U,  // MOVRGZrr
357
39.8k
    6096U,  // MOVRLEZri
358
39.8k
    6096U,  // MOVRLEZrr
359
39.8k
    6186U,  // MOVRLZri
360
39.8k
    6186U,  // MOVRLZrr
361
39.8k
    6230U,  // MOVRNZri
362
39.8k
    6230U,  // MOVRNZrr
363
39.8k
    6262U,  // MOVRRZri
364
39.8k
    6262U,  // MOVRRZrr
365
39.8k
    1054469U, // MOVSTOSW
366
39.8k
    1054479U, // MOVSTOUW
367
39.8k
    1054543U, // MOVWTOS
368
39.8k
    23747114U,  // MOVXCCri
369
39.8k
    23747114U,  // MOVXCCrr
370
39.8k
    1054543U, // MOVXTOD
371
39.8k
    5954U,  // MULXri
372
39.8k
    5954U,  // MULXrr
373
39.8k
    2578U,  // NOP
374
39.8k
    4735U,  // ORCCri
375
39.8k
    4735U,  // ORCCrr
376
39.8k
    4726U,  // ORNCCri
377
39.8k
    4726U,  // ORNCCrr
378
39.8k
    5339U,  // ORNri
379
39.8k
    5339U,  // ORNrr
380
39.8k
    5339U,  // ORXNrr
381
39.8k
    5509U,  // ORXri
382
39.8k
    5509U,  // ORXrr
383
39.8k
    5509U,  // ORri
384
39.8k
    5509U,  // ORrr
385
39.8k
    5836U,  // PDIST
386
39.8k
    5344U,  // PDISTN
387
39.8k
    1053356U, // POPCrr
388
39.8k
    73729U, // RDY
389
39.8k
    4999U,  // RESTOREri
390
39.8k
    4999U,  // RESTORErr
391
39.8k
    76132U, // RET
392
39.8k
    76141U, // RETL
393
39.8k
    18131U, // RETTri
394
39.8k
    18131U, // RETTrr
395
39.8k
    5008U,  // SAVEri
396
39.8k
    5008U,  // SAVErr
397
39.8k
    4748U,  // SDIVCCri
398
39.8k
    4748U,  // SDIVCCrr
399
39.8k
    5995U,  // SDIVXri
400
39.8k
    5995U,  // SDIVXrr
401
39.8k
    5861U,  // SDIVri
402
39.8k
    5861U,  // SDIVrr
403
39.8k
    2182U,  // SELECT_CC_DFP_FCC
404
39.8k
    2293U,  // SELECT_CC_DFP_ICC
405
39.8k
    2238U,  // SELECT_CC_FP_FCC
406
39.8k
    2349U,  // SELECT_CC_FP_ICC
407
39.8k
    2265U,  // SELECT_CC_Int_FCC
408
39.8k
    2376U,  // SELECT_CC_Int_ICC
409
39.8k
    2210U,  // SELECT_CC_QFP_FCC
410
39.8k
    2321U,  // SELECT_CC_QFP_ICC
411
39.8k
    1053595U, // SETHIXi
412
39.8k
    1053595U, // SETHIi
413
39.8k
    2569U,  // SHUTDOWN
414
39.8k
    2564U,  // SIAM
415
39.8k
    5941U,  // SLLXri
416
39.8k
    5941U,  // SLLXrr
417
39.8k
    5116U,  // SLLri
418
39.8k
    5116U,  // SLLrr
419
39.8k
    4702U,  // SMULCCri
420
39.8k
    4702U,  // SMULCCrr
421
39.8k
    5144U,  // SMULri
422
39.8k
    5144U,  // SMULrr
423
39.8k
    5913U,  // SRAXri
424
39.8k
    5913U,  // SRAXrr
425
39.8k
    4643U,  // SRAri
426
39.8k
    4643U,  // SRArr
427
39.8k
    5947U,  // SRLXri
428
39.8k
    5947U,  // SRLXrr
429
39.8k
    5139U,  // SRLri
430
39.8k
    5139U,  // SRLrr
431
39.8k
    2588U,  // STBAR
432
39.8k
    37428U, // STBri
433
39.8k
    37428U, // STBrr
434
39.8k
    37723U, // STDFri
435
39.8k
    37723U, // STDFrr
436
39.8k
    38607U, // STFri
437
39.8k
    38607U, // STFrr
438
39.8k
    37782U, // STHri
439
39.8k
    37782U, // STHrr
440
39.8k
    38238U, // STQFri
441
39.8k
    38238U, // STQFrr
442
39.8k
    38758U, // STXri
443
39.8k
    38758U, // STXrr
444
39.8k
    38607U, // STri
445
39.8k
    38607U, // STrr
446
39.8k
    4671U,  // SUBCCri
447
39.8k
    4671U,  // SUBCCrr
448
39.8k
    5919U,  // SUBCri
449
39.8k
    5919U,  // SUBCrr
450
39.8k
    4764U,  // SUBEri
451
39.8k
    4764U,  // SUBErr
452
39.8k
    4665U,  // SUBXri
453
39.8k
    4665U,  // SUBXrr
454
39.8k
    4665U,  // SUBri
455
39.8k
    4665U,  // SUBrr
456
39.8k
    1997268U, // SWAPri
457
39.8k
    1997268U, // SWAPrr
458
39.8k
    2422U,  // TA3
459
39.8k
    2427U,  // TA5
460
39.8k
    5883U,  // TADDCCTVri
461
39.8k
    5883U,  // TADDCCTVrr
462
39.8k
    4687U,  // TADDCCri
463
39.8k
    4687U,  // TADDCCrr
464
39.8k
    9873960U, // TICCri
465
39.8k
    9873960U, // TICCrr
466
39.8k
    37753544U,  // TLS_ADDXrr
467
39.8k
    37753544U,  // TLS_ADDrr
468
39.8k
    2106358U, // TLS_CALL
469
39.8k
    39746030U,  // TLS_LDXrr
470
39.8k
    39745985U,  // TLS_LDrr
471
39.8k
    5873U,  // TSUBCCTVri
472
39.8k
    5873U,  // TSUBCCTVrr
473
39.8k
    4670U,  // TSUBCCri
474
39.8k
    4670U,  // TSUBCCrr
475
39.8k
    10136104U,  // TXCCri
476
39.8k
    10136104U,  // TXCCrr
477
39.8k
    4756U,  // UDIVCCri
478
39.8k
    4756U,  // UDIVCCrr
479
39.8k
    6002U,  // UDIVXri
480
39.8k
    6002U,  // UDIVXrr
481
39.8k
    5867U,  // UDIVri
482
39.8k
    5867U,  // UDIVrr
483
39.8k
    4710U,  // UMULCCri
484
39.8k
    4710U,  // UMULCCrr
485
39.8k
    5026U,  // UMULXHI
486
39.8k
    5150U,  // UMULri
487
39.8k
    5150U,  // UMULrr
488
39.8k
    74996U, // UNIMP
489
39.8k
    6300477U, // V9FCMPD
490
39.8k
    6300397U, // V9FCMPED
491
39.8k
    6300942U, // V9FCMPEQ
492
39.8k
    6301251U, // V9FCMPES
493
39.8k
    6301000U, // V9FCMPQ
494
39.8k
    6301309U, // V9FCMPS
495
39.8k
    47614U, // V9FMOVD_FCC
496
39.8k
    47638U, // V9FMOVQ_FCC
497
39.8k
    47650U, // V9FMOVS_FCC
498
39.8k
    47658U, // V9MOVFCCri
499
39.8k
    47658U, // V9MOVFCCrr
500
39.8k
    14689692U,  // WRYri
501
39.8k
    14689692U,  // WRYrr
502
39.8k
    5953U,  // XMULX
503
39.8k
    5035U,  // XMULXHI
504
39.8k
    4733U,  // XNORCCri
505
39.8k
    4733U,  // XNORCCrr
506
39.8k
    5520U,  // XNORXrr
507
39.8k
    5520U,  // XNORri
508
39.8k
    5520U,  // XNORrr
509
39.8k
    4741U,  // XORCCri
510
39.8k
    4741U,  // XORCCrr
511
39.8k
    5527U,  // XORXri
512
39.8k
    5527U,  // XORXrr
513
39.8k
    5527U,  // XORri
514
39.8k
    5527U,  // XORrr
515
39.8k
    0U
516
39.8k
  };
517
518
39.8k
#ifndef CAPSTONE_DIET
519
39.8k
  static const char AsmStrs[] = {
520
39.8k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
39.8k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
39.8k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
39.8k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
39.8k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
39.8k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
39.8k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
39.8k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
39.8k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
39.8k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
39.8k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
39.8k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
39.8k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
39.8k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
39.8k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
39.8k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
39.8k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
39.8k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
39.8k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
39.8k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
39.8k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
39.8k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
39.8k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
39.8k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
39.8k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
39.8k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
39.8k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
39.8k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
39.8k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
39.8k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
39.8k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
39.8k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
39.8k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
39.8k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
39.8k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
39.8k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
39.8k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
39.8k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
39.8k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
39.8k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
39.8k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
39.8k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
39.8k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
39.8k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
39.8k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
39.8k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
39.8k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
39.8k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
39.8k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
39.8k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
39.8k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
39.8k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
39.8k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
39.8k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
39.8k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
39.8k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
39.8k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
39.8k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
39.8k
  /* 542 */ 'b', 'a', 32, 0,
579
39.8k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
39.8k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
39.8k
  /* 563 */ 's', 't', 'b', 32, 0,
582
39.8k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
39.8k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
39.8k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
39.8k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
39.8k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
39.8k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
39.8k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
39.8k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
39.8k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
39.8k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
39.8k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
39.8k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
39.8k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
39.8k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
39.8k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
39.8k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
39.8k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
39.8k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
39.8k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
39.8k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
39.8k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
39.8k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
39.8k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
39.8k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
39.8k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
39.8k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
39.8k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
39.8k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
39.8k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
39.8k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
39.8k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
39.8k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
39.8k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
39.8k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
39.8k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
39.8k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
39.8k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
39.8k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
39.8k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
39.8k
  /* 858 */ 's', 't', 'd', 32, 0,
622
39.8k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
39.8k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
39.8k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
39.8k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
39.8k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
39.8k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
39.8k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
39.8k
  /* 917 */ 's', 't', 'h', 32, 0,
630
39.8k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
39.8k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
39.8k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
39.8k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
39.8k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
39.8k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
39.8k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
39.8k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
39.8k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
39.8k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
39.8k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
39.8k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
39.8k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
39.8k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
39.8k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
39.8k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
39.8k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
39.8k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
39.8k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
39.8k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
39.8k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
39.8k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
39.8k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
39.8k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
39.8k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
39.8k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
39.8k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
39.8k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
39.8k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
39.8k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
39.8k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
39.8k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
39.8k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
39.8k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
39.8k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
39.8k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
39.8k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
39.8k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
39.8k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
39.8k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
39.8k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
39.8k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
39.8k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
39.8k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
39.8k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
39.8k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
39.8k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
39.8k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
39.8k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
39.8k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
39.8k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
39.8k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
39.8k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
39.8k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
39.8k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
39.8k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
39.8k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
39.8k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
39.8k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
39.8k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
39.8k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
39.8k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
39.8k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
39.8k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
39.8k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
39.8k
  /* 1435 */ 'w', 'r', 32, 0,
696
39.8k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
39.8k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
39.8k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
39.8k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
39.8k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
39.8k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
39.8k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
39.8k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
39.8k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
39.8k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
39.8k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
39.8k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
39.8k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
39.8k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
39.8k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
39.8k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
39.8k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
39.8k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
39.8k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
39.8k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
39.8k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
39.8k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
39.8k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
39.8k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
39.8k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
39.8k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
39.8k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
39.8k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
39.8k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
39.8k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
39.8k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
39.8k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
39.8k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
39.8k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
39.8k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
39.8k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
39.8k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
39.8k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
39.8k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
39.8k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
39.8k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
39.8k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
39.8k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
39.8k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
39.8k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
39.8k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
39.8k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
39.8k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
39.8k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
39.8k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
39.8k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
39.8k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
39.8k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
39.8k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
39.8k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
39.8k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
39.8k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
39.8k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
39.8k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
39.8k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
39.8k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
39.8k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
39.8k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
39.8k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
39.8k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
39.8k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
39.8k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
39.8k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
39.8k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
39.8k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
39.8k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
39.8k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
39.8k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
39.8k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
39.8k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
39.8k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
39.8k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
39.8k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
39.8k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
39.8k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
39.8k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
39.8k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
39.8k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
39.8k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
39.8k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
39.8k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
39.8k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
39.8k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
39.8k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
39.8k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
39.8k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
39.8k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
39.8k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
39.8k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
39.8k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
39.8k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
39.8k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
39.8k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
39.8k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
39.8k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
39.8k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
39.8k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
39.8k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
39.8k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
39.8k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
39.8k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
39.8k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
39.8k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
39.8k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
39.8k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
39.8k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
39.8k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
39.8k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
39.8k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
39.8k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
39.8k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
39.8k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
39.8k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
39.8k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
39.8k
  /* 2554 */ 'f', 'b', 0,
816
39.8k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
39.8k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
39.8k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
39.8k
  /* 2577 */ 'n', 'o', 'p', 0,
820
39.8k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
39.8k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
39.8k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
39.8k
  /* 2599 */ 't', 0,
824
39.8k
  /* 2601 */ 'm', 'o', 'v', 0,
825
39.8k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
39.8k
  };
827
39.8k
#endif
828
829
  // Emit the opcode for the instruction.
830
39.8k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
39.8k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
39.8k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
39.8k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
39.8k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
63
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
63
    return;
844
0
    break;
845
7.18k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
7.18k
    printOperand(MI, 1, O); 
848
7.18k
    break;
849
21.6k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
21.6k
    printOperand(MI, 0, O); 
852
21.6k
    break;
853
3.28k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.28k
    printCCOperand(MI, 1, O); 
856
3.28k
    break;
857
1.07k
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
1.07k
    printMemOperand(MI, 0, O, NULL); 
860
1.07k
    return;
861
0
    break;
862
2.44k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.44k
    printCCOperand(MI, 3, O); 
865
2.44k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
1.58k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
1.58k
    printMemOperand(MI, 1, O, NULL); 
874
1.58k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.05k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.05k
    printOperand(MI, 2, O); 
885
1.05k
    SStream_concat0(O, ", ["); 
886
1.05k
    printMemOperand(MI, 0, O, NULL); 
887
1.05k
    SStream_concat0(O, "]"); 
888
1.05k
    return;
889
0
    break;
890
583
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
583
    printCCOperand(MI, 2, O); 
893
583
    break;
894
871
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
871
    printCCOperand(MI, 4, O); 
897
871
    SStream_concat0(O, " "); 
898
871
    printOperand(MI, 1, O); 
899
871
    SStream_concat0(O, ", "); 
900
871
    printOperand(MI, 2, O); 
901
871
    SStream_concat0(O, ", "); 
902
871
    printOperand(MI, 0, O); 
903
871
    return;
904
0
    break;
905
39.8k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
36.7k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
11.5k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
11.5k
    SStream_concat0(O, ", "); 
915
11.5k
    break;
916
17.2k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
17.2k
    return;
919
0
    break;
920
960
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
960
    SStream_concat0(O, " "); 
923
960
    break;
924
1.24k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.24k
    SStream_concat0(O, ",a ");
927
1.24k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.24k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.92k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.92k
    SStream_concat0(O, " %icc, ");
950
1.92k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.92k
    break;
952
264
  case 7:
953
    // BPICCA
954
264
    SStream_concat0(O, ",a %icc, ");
955
264
  Sparc_add_hint(MI, SPARC_HINT_A);
956
264
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
264
    printOperand(MI, 0, O); 
958
264
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
783
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
783
    SStream_concat0(O, " %xcc, ");
979
783
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
783
    break;
981
248
  case 11:
982
    // BPXCCA
983
248
    SStream_concat0(O, ",a %xcc, ");
984
248
  Sparc_add_hint(MI, SPARC_HINT_A);
985
248
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
248
    printOperand(MI, 0, O); 
987
248
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.62k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.62k
    SStream_concat0(O, "], "); 
1008
1.62k
    break;
1009
890
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
890
    SStream_concat0(O, " %fcc0, ");
1012
890
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
890
    printOperand(MI, 1, O); 
1014
890
    SStream_concat0(O, ", "); 
1015
890
    printOperand(MI, 0, O); 
1016
890
    return;
1017
0
    break;
1018
36.7k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
18.0k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.26k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.26k
    printOperand(MI, 2, O); 
1028
5.26k
    SStream_concat0(O, ", "); 
1029
5.26k
    printOperand(MI, 0, O); 
1030
5.26k
    break;
1031
6.85k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
6.85k
    printOperand(MI, 0, O); 
1034
6.85k
    break;
1035
5.96k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
5.96k
    printOperand(MI, 1, O); 
1038
5.96k
    break;
1039
18.0k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
18.0k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
14.5k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
14.5k
    return;
1049
0
    break;
1050
2.65k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.65k
    SStream_concat0(O, ", "); 
1053
2.65k
    break;
1054
583
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
583
    SStream_concat0(O, " + ");  // qq
1057
583
    printOperand(MI, 1, O); 
1058
583
    return;
1059
0
    break;
1060
253
  case 3:
1061
    // WRYri, WRYrr
1062
253
    SStream_concat0(O, ", %y");
1063
253
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
253
    return;
1065
0
    break;
1066
18.0k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.65k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.10k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.10k
    printOperand(MI, 2, O); 
1076
1.10k
    return;
1077
0
    break;
1078
1.55k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.55k
    printOperand(MI, 0, O); 
1081
1.55k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.65k
  }
1089
2.65k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
58.0k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
58.0k
#ifndef CAPSTONE_DIET
1100
58.0k
  static const char AsmStrs[] = {
1101
58.0k
  /* 0 */ 'f', '1', '0', 0,
1102
58.0k
  /* 4 */ 'f', '2', '0', 0,
1103
58.0k
  /* 8 */ 'f', '3', '0', 0,
1104
58.0k
  /* 12 */ 'f', '4', '0', 0,
1105
58.0k
  /* 16 */ 'f', '5', '0', 0,
1106
58.0k
  /* 20 */ 'f', '6', '0', 0,
1107
58.0k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
58.0k
  /* 29 */ 'f', '0', 0,
1109
58.0k
  /* 32 */ 'g', '0', 0,
1110
58.0k
  /* 35 */ 'i', '0', 0,
1111
58.0k
  /* 38 */ 'l', '0', 0,
1112
58.0k
  /* 41 */ 'o', '0', 0,
1113
58.0k
  /* 44 */ 'f', '1', '1', 0,
1114
58.0k
  /* 48 */ 'f', '2', '1', 0,
1115
58.0k
  /* 52 */ 'f', '3', '1', 0,
1116
58.0k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
58.0k
  /* 61 */ 'f', '1', 0,
1118
58.0k
  /* 64 */ 'g', '1', 0,
1119
58.0k
  /* 67 */ 'i', '1', 0,
1120
58.0k
  /* 70 */ 'l', '1', 0,
1121
58.0k
  /* 73 */ 'o', '1', 0,
1122
58.0k
  /* 76 */ 'f', '1', '2', 0,
1123
58.0k
  /* 80 */ 'f', '2', '2', 0,
1124
58.0k
  /* 84 */ 'f', '3', '2', 0,
1125
58.0k
  /* 88 */ 'f', '4', '2', 0,
1126
58.0k
  /* 92 */ 'f', '5', '2', 0,
1127
58.0k
  /* 96 */ 'f', '6', '2', 0,
1128
58.0k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
58.0k
  /* 105 */ 'f', '2', 0,
1130
58.0k
  /* 108 */ 'g', '2', 0,
1131
58.0k
  /* 111 */ 'i', '2', 0,
1132
58.0k
  /* 114 */ 'l', '2', 0,
1133
58.0k
  /* 117 */ 'o', '2', 0,
1134
58.0k
  /* 120 */ 'f', '1', '3', 0,
1135
58.0k
  /* 124 */ 'f', '2', '3', 0,
1136
58.0k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
58.0k
  /* 133 */ 'f', '3', 0,
1138
58.0k
  /* 136 */ 'g', '3', 0,
1139
58.0k
  /* 139 */ 'i', '3', 0,
1140
58.0k
  /* 142 */ 'l', '3', 0,
1141
58.0k
  /* 145 */ 'o', '3', 0,
1142
58.0k
  /* 148 */ 'f', '1', '4', 0,
1143
58.0k
  /* 152 */ 'f', '2', '4', 0,
1144
58.0k
  /* 156 */ 'f', '3', '4', 0,
1145
58.0k
  /* 160 */ 'f', '4', '4', 0,
1146
58.0k
  /* 164 */ 'f', '5', '4', 0,
1147
58.0k
  /* 168 */ 'f', '4', 0,
1148
58.0k
  /* 171 */ 'g', '4', 0,
1149
58.0k
  /* 174 */ 'i', '4', 0,
1150
58.0k
  /* 177 */ 'l', '4', 0,
1151
58.0k
  /* 180 */ 'o', '4', 0,
1152
58.0k
  /* 183 */ 'f', '1', '5', 0,
1153
58.0k
  /* 187 */ 'f', '2', '5', 0,
1154
58.0k
  /* 191 */ 'f', '5', 0,
1155
58.0k
  /* 194 */ 'g', '5', 0,
1156
58.0k
  /* 197 */ 'i', '5', 0,
1157
58.0k
  /* 200 */ 'l', '5', 0,
1158
58.0k
  /* 203 */ 'o', '5', 0,
1159
58.0k
  /* 206 */ 'f', '1', '6', 0,
1160
58.0k
  /* 210 */ 'f', '2', '6', 0,
1161
58.0k
  /* 214 */ 'f', '3', '6', 0,
1162
58.0k
  /* 218 */ 'f', '4', '6', 0,
1163
58.0k
  /* 222 */ 'f', '5', '6', 0,
1164
58.0k
  /* 226 */ 'f', '6', 0,
1165
58.0k
  /* 229 */ 'g', '6', 0,
1166
58.0k
  /* 232 */ 'l', '6', 0,
1167
58.0k
  /* 235 */ 'f', '1', '7', 0,
1168
58.0k
  /* 239 */ 'f', '2', '7', 0,
1169
58.0k
  /* 243 */ 'f', '7', 0,
1170
58.0k
  /* 246 */ 'g', '7', 0,
1171
58.0k
  /* 249 */ 'i', '7', 0,
1172
58.0k
  /* 252 */ 'l', '7', 0,
1173
58.0k
  /* 255 */ 'o', '7', 0,
1174
58.0k
  /* 258 */ 'f', '1', '8', 0,
1175
58.0k
  /* 262 */ 'f', '2', '8', 0,
1176
58.0k
  /* 266 */ 'f', '3', '8', 0,
1177
58.0k
  /* 270 */ 'f', '4', '8', 0,
1178
58.0k
  /* 274 */ 'f', '5', '8', 0,
1179
58.0k
  /* 278 */ 'f', '8', 0,
1180
58.0k
  /* 281 */ 'f', '1', '9', 0,
1181
58.0k
  /* 285 */ 'f', '2', '9', 0,
1182
58.0k
  /* 289 */ 'f', '9', 0,
1183
58.0k
  /* 292 */ 'i', 'c', 'c', 0,
1184
58.0k
  /* 296 */ 'f', 'p', 0,
1185
58.0k
  /* 299 */ 's', 'p', 0,
1186
58.0k
  /* 302 */ 'y', 0,
1187
58.0k
  };
1188
1189
58.0k
  static const uint16_t RegAsmOffset[] = {
1190
58.0k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
58.0k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
58.0k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
58.0k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
58.0k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
58.0k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
58.0k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
58.0k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
58.0k
    12, 160, 270, 92, 222, 20, 
1199
58.0k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
58.0k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
58.0k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
69.3k
{
1221
306k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
69.3k
  const char *AsmString;
1223
69.3k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
69.3k
  int OpIdx, PrintMethodIdx;
1225
69.3k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
69.3k
  switch (MCInst_getOpcode(MI)) {
1227
36.7k
  default: return NULL;
1228
2.88k
  case SP_BCOND:
1229
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
501
      AsmString = "bn $\x01";
1241
501
      break;
1242
501
    }
1243
2.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
75
      AsmString = "bne $\x01";
1248
75
      break;
1249
75
    }
1250
2.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
214
      AsmString = "be $\x01";
1255
214
      break;
1256
214
    }
1257
2.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
92
      AsmString = "bg $\x01";
1262
92
      break;
1263
92
    }
1264
1.99k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
243
      AsmString = "ble $\x01";
1269
243
      break;
1270
243
    }
1271
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
73
      AsmString = "bge $\x01";
1276
73
      break;
1277
73
    }
1278
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
211
      AsmString = "bl $\x01";
1283
211
      break;
1284
211
    }
1285
1.47k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
262
      AsmString = "bgu $\x01";
1290
262
      break;
1291
262
    }
1292
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
118
      AsmString = "bleu $\x01";
1297
118
      break;
1298
118
    }
1299
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
18
      AsmString = "bcc $\x01";
1304
18
      break;
1305
18
    }
1306
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
207
      AsmString = "bcs $\x01";
1311
207
      break;
1312
207
    }
1313
866
    if (MCInst_getNumOperands(MI) == 2 &&
1314
866
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
866
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
206
      AsmString = "bpos $\x01";
1318
206
      break;
1319
206
    }
1320
660
    if (MCInst_getNumOperands(MI) == 2 &&
1321
660
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
660
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
203
      AsmString = "bneg $\x01";
1325
203
      break;
1326
203
    }
1327
457
    if (MCInst_getNumOperands(MI) == 2 &&
1328
457
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
457
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
90
      AsmString = "bvc $\x01";
1332
90
      break;
1333
90
    }
1334
367
    if (MCInst_getNumOperands(MI) == 2 &&
1335
367
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
367
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
367
      AsmString = "bvs $\x01";
1339
367
      break;
1340
367
    }
1341
0
    return NULL;
1342
2.19k
  case SP_BCONDA:
1343
2.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
128
      AsmString = "ba,a $\x01";
1348
128
      break;
1349
128
    }
1350
2.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
205
      AsmString = "bn,a $\x01";
1355
205
      break;
1356
205
    }
1357
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
117
      AsmString = "bne,a $\x01";
1362
117
      break;
1363
117
    }
1364
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
73
      AsmString = "be,a $\x01";
1369
73
      break;
1370
73
    }
1371
1.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
74
      AsmString = "bg,a $\x01";
1376
74
      break;
1377
74
    }
1378
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
286
      AsmString = "ble,a $\x01";
1383
286
      break;
1384
286
    }
1385
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
187
      AsmString = "bge,a $\x01";
1390
187
      break;
1391
187
    }
1392
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
22
      AsmString = "bl,a $\x01";
1397
22
      break;
1398
22
    }
1399
1.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
71
      AsmString = "bgu,a $\x01";
1404
71
      break;
1405
71
    }
1406
1.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
242
      AsmString = "bleu,a $\x01";
1411
242
      break;
1412
242
    }
1413
791
    if (MCInst_getNumOperands(MI) == 2 &&
1414
791
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
791
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
58
      AsmString = "bcc,a $\x01";
1418
58
      break;
1419
58
    }
1420
733
    if (MCInst_getNumOperands(MI) == 2 &&
1421
733
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
733
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
102
      AsmString = "bcs,a $\x01";
1425
102
      break;
1426
102
    }
1427
631
    if (MCInst_getNumOperands(MI) == 2 &&
1428
631
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
631
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
272
      AsmString = "bpos,a $\x01";
1432
272
      break;
1433
272
    }
1434
359
    if (MCInst_getNumOperands(MI) == 2 &&
1435
359
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
359
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
199
      AsmString = "bneg,a $\x01";
1439
199
      break;
1440
199
    }
1441
160
    if (MCInst_getNumOperands(MI) == 2 &&
1442
160
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
160
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
80
      AsmString = "bvc,a $\x01";
1446
80
      break;
1447
80
    }
1448
80
    if (MCInst_getNumOperands(MI) == 2 &&
1449
80
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
80
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
80
      AsmString = "bvs,a $\x01";
1453
80
      break;
1454
80
    }
1455
0
    return NULL;
1456
3.25k
  case SP_BPFCCANT:
1457
3.25k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
3.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
3.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
3.25k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
3.25k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
71
      AsmString = "fba,a,pn $\x03, $\x01";
1464
71
      break;
1465
71
    }
1466
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
312
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
312
      break;
1474
312
    }
1475
2.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
2.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
2.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
2.86k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
2.86k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
432
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
432
      break;
1483
432
    }
1484
2.43k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.43k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.43k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
148
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
148
      break;
1492
148
    }
1493
2.28k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.28k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.28k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
245
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
245
      break;
1501
245
    }
1502
2.04k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.04k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
218
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
218
      break;
1510
218
    }
1511
1.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.82k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.82k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
206
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
206
      break;
1519
206
    }
1520
1.61k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
1.61k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
1.61k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
231
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
231
      break;
1528
231
    }
1529
1.38k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.38k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.38k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
219
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
219
      break;
1537
219
    }
1538
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.16k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
513
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
513
      break;
1546
513
    }
1547
655
    if (MCInst_getNumOperands(MI) == 3 &&
1548
655
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
655
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
655
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
655
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
42
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
42
      break;
1555
42
    }
1556
613
    if (MCInst_getNumOperands(MI) == 3 &&
1557
613
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
613
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
613
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
613
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
37
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
37
      break;
1564
37
    }
1565
576
    if (MCInst_getNumOperands(MI) == 3 &&
1566
576
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
576
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
576
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
576
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
102
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
102
      break;
1573
102
    }
1574
474
    if (MCInst_getNumOperands(MI) == 3 &&
1575
474
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
474
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
474
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
474
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
84
      AsmString = "fble,a,pn $\x03, $\x01";
1581
84
      break;
1582
84
    }
1583
390
    if (MCInst_getNumOperands(MI) == 3 &&
1584
390
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
390
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
390
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
390
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
115
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
115
      break;
1591
115
    }
1592
275
    if (MCInst_getNumOperands(MI) == 3 &&
1593
275
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
275
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
275
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
275
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
275
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
275
      break;
1600
275
    }
1601
0
    return NULL;
1602
2.97k
  case SP_BPFCCNT:
1603
2.97k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
2.97k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
2.97k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
294
      AsmString = "fba,pn $\x03, $\x01";
1610
294
      break;
1611
294
    }
1612
2.68k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
2.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
2.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
2.68k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
2.68k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
200
      AsmString = "fbn,pn $\x03, $\x01";
1619
200
      break;
1620
200
    }
1621
2.48k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
2.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
2.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
2.48k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
2.48k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
276
      AsmString = "fbu,pn $\x03, $\x01";
1628
276
      break;
1629
276
    }
1630
2.20k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.20k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.20k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
208
      AsmString = "fbg,pn $\x03, $\x01";
1637
208
      break;
1638
208
    }
1639
2.00k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.00k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.00k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
74
      AsmString = "fbug,pn $\x03, $\x01";
1646
74
      break;
1647
74
    }
1648
1.92k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.92k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.92k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
92
      AsmString = "fbl,pn $\x03, $\x01";
1655
92
      break;
1656
92
    }
1657
1.83k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.83k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
249
      AsmString = "fbul,pn $\x03, $\x01";
1664
249
      break;
1665
249
    }
1666
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
1.58k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
238
      AsmString = "fblg,pn $\x03, $\x01";
1673
238
      break;
1674
238
    }
1675
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.34k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
138
      AsmString = "fbne,pn $\x03, $\x01";
1682
138
      break;
1683
138
    }
1684
1.20k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.20k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.20k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
213
      AsmString = "fbe,pn $\x03, $\x01";
1691
213
      break;
1692
213
    }
1693
996
    if (MCInst_getNumOperands(MI) == 3 &&
1694
996
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
996
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
996
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
996
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
277
      AsmString = "fbue,pn $\x03, $\x01";
1700
277
      break;
1701
277
    }
1702
719
    if (MCInst_getNumOperands(MI) == 3 &&
1703
719
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
719
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
719
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
719
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
95
      AsmString = "fbge,pn $\x03, $\x01";
1709
95
      break;
1710
95
    }
1711
624
    if (MCInst_getNumOperands(MI) == 3 &&
1712
624
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
624
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
624
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
624
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
253
      AsmString = "fbuge,pn $\x03, $\x01";
1718
253
      break;
1719
253
    }
1720
371
    if (MCInst_getNumOperands(MI) == 3 &&
1721
371
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
371
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
371
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
371
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
69
      AsmString = "fble,pn $\x03, $\x01";
1727
69
      break;
1728
69
    }
1729
302
    if (MCInst_getNumOperands(MI) == 3 &&
1730
302
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
302
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
302
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
302
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
85
      AsmString = "fbule,pn $\x03, $\x01";
1736
85
      break;
1737
85
    }
1738
217
    if (MCInst_getNumOperands(MI) == 3 &&
1739
217
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
217
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
217
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
217
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
217
      AsmString = "fbo,pn $\x03, $\x01";
1745
217
      break;
1746
217
    }
1747
0
    return NULL;
1748
2.13k
  case SP_BPICCANT:
1749
2.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
46
      AsmString = "ba,a,pn %icc, $\x01";
1754
46
      break;
1755
46
    }
1756
2.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
202
      AsmString = "bn,a,pn %icc, $\x01";
1761
202
      break;
1762
202
    }
1763
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
145
      AsmString = "bne,a,pn %icc, $\x01";
1768
145
      break;
1769
145
    }
1770
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
139
      AsmString = "be,a,pn %icc, $\x01";
1775
139
      break;
1776
139
    }
1777
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
141
      AsmString = "bg,a,pn %icc, $\x01";
1782
141
      break;
1783
141
    }
1784
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
76
      AsmString = "ble,a,pn %icc, $\x01";
1789
76
      break;
1790
76
    }
1791
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
88
      AsmString = "bge,a,pn %icc, $\x01";
1796
88
      break;
1797
88
    }
1798
1.29k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
224
      AsmString = "bl,a,pn %icc, $\x01";
1803
224
      break;
1804
224
    }
1805
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
43
      AsmString = "bgu,a,pn %icc, $\x01";
1810
43
      break;
1811
43
    }
1812
1.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
227
      AsmString = "bleu,a,pn %icc, $\x01";
1817
227
      break;
1818
227
    }
1819
803
    if (MCInst_getNumOperands(MI) == 2 &&
1820
803
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
803
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
212
      AsmString = "bcc,a,pn %icc, $\x01";
1824
212
      break;
1825
212
    }
1826
591
    if (MCInst_getNumOperands(MI) == 2 &&
1827
591
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
591
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
125
      AsmString = "bcs,a,pn %icc, $\x01";
1831
125
      break;
1832
125
    }
1833
466
    if (MCInst_getNumOperands(MI) == 2 &&
1834
466
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
466
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
196
      AsmString = "bpos,a,pn %icc, $\x01";
1838
196
      break;
1839
196
    }
1840
270
    if (MCInst_getNumOperands(MI) == 2 &&
1841
270
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
270
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
78
      AsmString = "bneg,a,pn %icc, $\x01";
1845
78
      break;
1846
78
    }
1847
192
    if (MCInst_getNumOperands(MI) == 2 &&
1848
192
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
192
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
68
      AsmString = "bvc,a,pn %icc, $\x01";
1852
68
      break;
1853
68
    }
1854
124
    if (MCInst_getNumOperands(MI) == 2 &&
1855
124
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
124
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
124
      AsmString = "bvs,a,pn %icc, $\x01";
1859
124
      break;
1860
124
    }
1861
0
    return NULL;
1862
3.17k
  case SP_BPICCNT:
1863
3.17k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
85
      AsmString = "ba,pn %icc, $\x01";
1868
85
      break;
1869
85
    }
1870
3.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
3.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
3.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
390
      AsmString = "bn,pn %icc, $\x01";
1875
390
      break;
1876
390
    }
1877
2.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
197
      AsmString = "bne,pn %icc, $\x01";
1882
197
      break;
1883
197
    }
1884
2.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
838
      AsmString = "be,pn %icc, $\x01";
1889
838
      break;
1890
838
    }
1891
1.66k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
72
      AsmString = "bg,pn %icc, $\x01";
1896
72
      break;
1897
72
    }
1898
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
124
      AsmString = "ble,pn %icc, $\x01";
1903
124
      break;
1904
124
    }
1905
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
78
      AsmString = "bge,pn %icc, $\x01";
1910
78
      break;
1911
78
    }
1912
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
82
      AsmString = "bl,pn %icc, $\x01";
1917
82
      break;
1918
82
    }
1919
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
66
      AsmString = "bgu,pn %icc, $\x01";
1924
66
      break;
1925
66
    }
1926
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
205
      AsmString = "bleu,pn %icc, $\x01";
1931
205
      break;
1932
205
    }
1933
1.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
32
      AsmString = "bcc,pn %icc, $\x01";
1938
32
      break;
1939
32
    }
1940
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1941
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
169
      AsmString = "bcs,pn %icc, $\x01";
1945
169
      break;
1946
169
    }
1947
834
    if (MCInst_getNumOperands(MI) == 2 &&
1948
834
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
834
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
75
      AsmString = "bpos,pn %icc, $\x01";
1952
75
      break;
1953
75
    }
1954
759
    if (MCInst_getNumOperands(MI) == 2 &&
1955
759
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
759
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
196
      AsmString = "bneg,pn %icc, $\x01";
1959
196
      break;
1960
196
    }
1961
563
    if (MCInst_getNumOperands(MI) == 2 &&
1962
563
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
563
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
200
      AsmString = "bvc,pn %icc, $\x01";
1966
200
      break;
1967
200
    }
1968
363
    if (MCInst_getNumOperands(MI) == 2 &&
1969
363
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
363
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
363
      AsmString = "bvs,pn %icc, $\x01";
1973
363
      break;
1974
363
    }
1975
0
    return NULL;
1976
1.37k
  case SP_BPXCCANT:
1977
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
31
      AsmString = "ba,a,pn %xcc, $\x01";
1982
31
      break;
1983
31
    }
1984
1.34k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
73
      AsmString = "bn,a,pn %xcc, $\x01";
1989
73
      break;
1990
73
    }
1991
1.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
90
      AsmString = "bne,a,pn %xcc, $\x01";
1996
90
      break;
1997
90
    }
1998
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
35
      AsmString = "be,a,pn %xcc, $\x01";
2003
35
      break;
2004
35
    }
2005
1.15k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
84
      AsmString = "bg,a,pn %xcc, $\x01";
2010
84
      break;
2011
84
    }
2012
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
93
      AsmString = "ble,a,pn %xcc, $\x01";
2017
93
      break;
2018
93
    }
2019
973
    if (MCInst_getNumOperands(MI) == 2 &&
2020
973
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
973
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
80
      AsmString = "bge,a,pn %xcc, $\x01";
2024
80
      break;
2025
80
    }
2026
893
    if (MCInst_getNumOperands(MI) == 2 &&
2027
893
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
893
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
68
      AsmString = "bl,a,pn %xcc, $\x01";
2031
68
      break;
2032
68
    }
2033
825
    if (MCInst_getNumOperands(MI) == 2 &&
2034
825
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
825
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
83
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
83
      break;
2039
83
    }
2040
742
    if (MCInst_getNumOperands(MI) == 2 &&
2041
742
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
742
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
211
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
211
      break;
2046
211
    }
2047
531
    if (MCInst_getNumOperands(MI) == 2 &&
2048
531
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
531
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
80
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
80
      break;
2053
80
    }
2054
451
    if (MCInst_getNumOperands(MI) == 2 &&
2055
451
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
451
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
91
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
91
      break;
2060
91
    }
2061
360
    if (MCInst_getNumOperands(MI) == 2 &&
2062
360
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
360
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
77
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
77
      break;
2067
77
    }
2068
283
    if (MCInst_getNumOperands(MI) == 2 &&
2069
283
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
283
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
80
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
80
      break;
2074
80
    }
2075
203
    if (MCInst_getNumOperands(MI) == 2 &&
2076
203
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
203
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
117
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
117
      break;
2081
117
    }
2082
86
    if (MCInst_getNumOperands(MI) == 2 &&
2083
86
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
86
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
86
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
86
      break;
2088
86
    }
2089
0
    return NULL;
2090
1.93k
  case SP_BPXCCNT:
2091
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
67
      AsmString = "ba,pn %xcc, $\x01";
2096
67
      break;
2097
67
    }
2098
1.87k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
239
      AsmString = "bn,pn %xcc, $\x01";
2103
239
      break;
2104
239
    }
2105
1.63k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
52
      AsmString = "bne,pn %xcc, $\x01";
2110
52
      break;
2111
52
    }
2112
1.57k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
191
      AsmString = "be,pn %xcc, $\x01";
2117
191
      break;
2118
191
    }
2119
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
298
      AsmString = "bg,pn %xcc, $\x01";
2124
298
      break;
2125
298
    }
2126
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
80
      AsmString = "ble,pn %xcc, $\x01";
2131
80
      break;
2132
80
    }
2133
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
40
      AsmString = "bge,pn %xcc, $\x01";
2138
40
      break;
2139
40
    }
2140
970
    if (MCInst_getNumOperands(MI) == 2 &&
2141
970
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
970
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
69
      AsmString = "bl,pn %xcc, $\x01";
2145
69
      break;
2146
69
    }
2147
901
    if (MCInst_getNumOperands(MI) == 2 &&
2148
901
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
901
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
66
      AsmString = "bgu,pn %xcc, $\x01";
2152
66
      break;
2153
66
    }
2154
835
    if (MCInst_getNumOperands(MI) == 2 &&
2155
835
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
835
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
74
      AsmString = "bleu,pn %xcc, $\x01";
2159
74
      break;
2160
74
    }
2161
761
    if (MCInst_getNumOperands(MI) == 2 &&
2162
761
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
761
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
206
      AsmString = "bcc,pn %xcc, $\x01";
2166
206
      break;
2167
206
    }
2168
555
    if (MCInst_getNumOperands(MI) == 2 &&
2169
555
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
555
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
235
      AsmString = "bcs,pn %xcc, $\x01";
2173
235
      break;
2174
235
    }
2175
320
    if (MCInst_getNumOperands(MI) == 2 &&
2176
320
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
320
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
196
      AsmString = "bpos,pn %xcc, $\x01";
2180
196
      break;
2181
196
    }
2182
124
    if (MCInst_getNumOperands(MI) == 2 &&
2183
124
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
124
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
45
      AsmString = "bneg,pn %xcc, $\x01";
2187
45
      break;
2188
45
    }
2189
79
    if (MCInst_getNumOperands(MI) == 2 &&
2190
79
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
79
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
35
      AsmString = "bvc,pn %xcc, $\x01";
2194
35
      break;
2195
35
    }
2196
44
    if (MCInst_getNumOperands(MI) == 2 &&
2197
44
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
44
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
44
      AsmString = "bvs,pn %xcc, $\x01";
2201
44
      break;
2202
44
    }
2203
0
    return NULL;
2204
144
  case SP_FMOVD_ICC:
2205
144
    if (MCInst_getNumOperands(MI) == 3 &&
2206
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
144
    if (MCInst_getNumOperands(MI) == 3 &&
2217
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
144
    if (MCInst_getNumOperands(MI) == 3 &&
2228
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
144
    if (MCInst_getNumOperands(MI) == 3 &&
2239
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
144
    if (MCInst_getNumOperands(MI) == 3 &&
2250
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
144
    if (MCInst_getNumOperands(MI) == 3 &&
2261
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
144
    if (MCInst_getNumOperands(MI) == 3 &&
2272
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
144
    if (MCInst_getNumOperands(MI) == 3 &&
2283
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
144
    if (MCInst_getNumOperands(MI) == 3 &&
2294
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
144
    if (MCInst_getNumOperands(MI) == 3 &&
2305
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
144
    if (MCInst_getNumOperands(MI) == 3 &&
2316
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
144
    if (MCInst_getNumOperands(MI) == 3 &&
2327
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
144
    if (MCInst_getNumOperands(MI) == 3 &&
2338
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
144
    if (MCInst_getNumOperands(MI) == 3 &&
2349
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
144
    if (MCInst_getNumOperands(MI) == 3 &&
2360
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
144
    if (MCInst_getNumOperands(MI) == 3 &&
2371
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
144
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
144
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
144
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
144
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
144
    return NULL;
2382
162
  case SP_FMOVD_XCC:
2383
162
    if (MCInst_getNumOperands(MI) == 3 &&
2384
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
162
    if (MCInst_getNumOperands(MI) == 3 &&
2395
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
162
    if (MCInst_getNumOperands(MI) == 3 &&
2406
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
162
    if (MCInst_getNumOperands(MI) == 3 &&
2417
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
162
    if (MCInst_getNumOperands(MI) == 3 &&
2428
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
162
    if (MCInst_getNumOperands(MI) == 3 &&
2439
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
162
    if (MCInst_getNumOperands(MI) == 3 &&
2450
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
162
    if (MCInst_getNumOperands(MI) == 3 &&
2461
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
162
    if (MCInst_getNumOperands(MI) == 3 &&
2472
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
162
    if (MCInst_getNumOperands(MI) == 3 &&
2483
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
162
    if (MCInst_getNumOperands(MI) == 3 &&
2494
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
162
    if (MCInst_getNumOperands(MI) == 3 &&
2505
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
162
    if (MCInst_getNumOperands(MI) == 3 &&
2516
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
162
    if (MCInst_getNumOperands(MI) == 3 &&
2527
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
162
    if (MCInst_getNumOperands(MI) == 3 &&
2538
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
162
    if (MCInst_getNumOperands(MI) == 3 &&
2549
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
162
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
162
    return NULL;
2560
376
  case SP_FMOVQ_ICC:
2561
376
    if (MCInst_getNumOperands(MI) == 3 &&
2562
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
376
    if (MCInst_getNumOperands(MI) == 3 &&
2573
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
376
    if (MCInst_getNumOperands(MI) == 3 &&
2584
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
376
    if (MCInst_getNumOperands(MI) == 3 &&
2595
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
376
    if (MCInst_getNumOperands(MI) == 3 &&
2606
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
376
    if (MCInst_getNumOperands(MI) == 3 &&
2617
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
376
    if (MCInst_getNumOperands(MI) == 3 &&
2628
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
376
    if (MCInst_getNumOperands(MI) == 3 &&
2639
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
376
    if (MCInst_getNumOperands(MI) == 3 &&
2650
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
376
    if (MCInst_getNumOperands(MI) == 3 &&
2661
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
376
    if (MCInst_getNumOperands(MI) == 3 &&
2672
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
376
    if (MCInst_getNumOperands(MI) == 3 &&
2683
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
376
    if (MCInst_getNumOperands(MI) == 3 &&
2694
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
376
    if (MCInst_getNumOperands(MI) == 3 &&
2705
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
376
    if (MCInst_getNumOperands(MI) == 3 &&
2716
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
376
    if (MCInst_getNumOperands(MI) == 3 &&
2727
376
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
376
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
376
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
376
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
376
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
376
    return NULL;
2738
20
  case SP_FMOVQ_XCC:
2739
20
    if (MCInst_getNumOperands(MI) == 3 &&
2740
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
20
    if (MCInst_getNumOperands(MI) == 3 &&
2751
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
20
    if (MCInst_getNumOperands(MI) == 3 &&
2762
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
20
    if (MCInst_getNumOperands(MI) == 3 &&
2773
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
20
    if (MCInst_getNumOperands(MI) == 3 &&
2784
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
20
    if (MCInst_getNumOperands(MI) == 3 &&
2795
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
20
    if (MCInst_getNumOperands(MI) == 3 &&
2806
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
20
    if (MCInst_getNumOperands(MI) == 3 &&
2817
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
20
    if (MCInst_getNumOperands(MI) == 3 &&
2828
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
20
    if (MCInst_getNumOperands(MI) == 3 &&
2839
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
20
    if (MCInst_getNumOperands(MI) == 3 &&
2850
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
20
    if (MCInst_getNumOperands(MI) == 3 &&
2861
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
20
    if (MCInst_getNumOperands(MI) == 3 &&
2872
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
20
    if (MCInst_getNumOperands(MI) == 3 &&
2883
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
20
    if (MCInst_getNumOperands(MI) == 3 &&
2894
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
20
    if (MCInst_getNumOperands(MI) == 3 &&
2905
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
20
    return NULL;
2916
100
  case SP_FMOVS_ICC:
2917
100
    if (MCInst_getNumOperands(MI) == 3 &&
2918
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
100
    if (MCInst_getNumOperands(MI) == 3 &&
2929
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
100
    if (MCInst_getNumOperands(MI) == 3 &&
2940
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
100
    if (MCInst_getNumOperands(MI) == 3 &&
2951
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
100
    if (MCInst_getNumOperands(MI) == 3 &&
2962
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
100
    if (MCInst_getNumOperands(MI) == 3 &&
2973
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
100
    if (MCInst_getNumOperands(MI) == 3 &&
2984
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
100
    if (MCInst_getNumOperands(MI) == 3 &&
2995
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
100
    if (MCInst_getNumOperands(MI) == 3 &&
3006
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
100
    if (MCInst_getNumOperands(MI) == 3 &&
3017
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
100
    if (MCInst_getNumOperands(MI) == 3 &&
3028
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
100
    if (MCInst_getNumOperands(MI) == 3 &&
3039
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
100
    if (MCInst_getNumOperands(MI) == 3 &&
3050
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
100
    if (MCInst_getNumOperands(MI) == 3 &&
3061
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
100
    if (MCInst_getNumOperands(MI) == 3 &&
3072
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
100
    if (MCInst_getNumOperands(MI) == 3 &&
3083
100
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
100
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
100
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
100
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
100
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
100
    return NULL;
3094
34
  case SP_FMOVS_XCC:
3095
34
    if (MCInst_getNumOperands(MI) == 3 &&
3096
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
34
    if (MCInst_getNumOperands(MI) == 3 &&
3107
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
34
    if (MCInst_getNumOperands(MI) == 3 &&
3118
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
34
    if (MCInst_getNumOperands(MI) == 3 &&
3129
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
34
    if (MCInst_getNumOperands(MI) == 3 &&
3140
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
34
    if (MCInst_getNumOperands(MI) == 3 &&
3151
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
34
    if (MCInst_getNumOperands(MI) == 3 &&
3162
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
34
    if (MCInst_getNumOperands(MI) == 3 &&
3173
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
34
    if (MCInst_getNumOperands(MI) == 3 &&
3184
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
34
    if (MCInst_getNumOperands(MI) == 3 &&
3195
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
34
    if (MCInst_getNumOperands(MI) == 3 &&
3206
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
34
    if (MCInst_getNumOperands(MI) == 3 &&
3217
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
34
    if (MCInst_getNumOperands(MI) == 3 &&
3228
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
34
    if (MCInst_getNumOperands(MI) == 3 &&
3239
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
34
    if (MCInst_getNumOperands(MI) == 3 &&
3250
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
34
    if (MCInst_getNumOperands(MI) == 3 &&
3261
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
34
    return NULL;
3272
221
  case SP_MOVICCri:
3273
221
    if (MCInst_getNumOperands(MI) == 3 &&
3274
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
221
    if (MCInst_getNumOperands(MI) == 3 &&
3283
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
221
    if (MCInst_getNumOperands(MI) == 3 &&
3292
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
221
    if (MCInst_getNumOperands(MI) == 3 &&
3301
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
221
    if (MCInst_getNumOperands(MI) == 3 &&
3310
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
221
    if (MCInst_getNumOperands(MI) == 3 &&
3319
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
221
    if (MCInst_getNumOperands(MI) == 3 &&
3328
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
221
    if (MCInst_getNumOperands(MI) == 3 &&
3337
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
221
    if (MCInst_getNumOperands(MI) == 3 &&
3346
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
221
    if (MCInst_getNumOperands(MI) == 3 &&
3355
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
221
    if (MCInst_getNumOperands(MI) == 3 &&
3364
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
221
    if (MCInst_getNumOperands(MI) == 3 &&
3373
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
221
    if (MCInst_getNumOperands(MI) == 3 &&
3382
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
221
    if (MCInst_getNumOperands(MI) == 3 &&
3391
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
221
    if (MCInst_getNumOperands(MI) == 3 &&
3400
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
221
    if (MCInst_getNumOperands(MI) == 3 &&
3409
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
221
    return NULL;
3418
212
  case SP_MOVICCrr:
3419
212
    if (MCInst_getNumOperands(MI) == 3 &&
3420
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
212
    if (MCInst_getNumOperands(MI) == 3 &&
3431
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
212
    if (MCInst_getNumOperands(MI) == 3 &&
3442
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
212
    if (MCInst_getNumOperands(MI) == 3 &&
3453
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
212
    if (MCInst_getNumOperands(MI) == 3 &&
3464
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
212
    if (MCInst_getNumOperands(MI) == 3 &&
3475
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
212
    if (MCInst_getNumOperands(MI) == 3 &&
3486
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
212
    if (MCInst_getNumOperands(MI) == 3 &&
3497
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
212
    if (MCInst_getNumOperands(MI) == 3 &&
3508
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
212
    if (MCInst_getNumOperands(MI) == 3 &&
3519
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
212
    if (MCInst_getNumOperands(MI) == 3 &&
3530
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
212
    if (MCInst_getNumOperands(MI) == 3 &&
3541
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
212
    if (MCInst_getNumOperands(MI) == 3 &&
3552
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
212
    if (MCInst_getNumOperands(MI) == 3 &&
3563
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
212
    if (MCInst_getNumOperands(MI) == 3 &&
3574
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
212
    if (MCInst_getNumOperands(MI) == 3 &&
3585
212
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
212
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
212
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
212
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
212
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
212
    return NULL;
3596
73
  case SP_MOVXCCri:
3597
73
    if (MCInst_getNumOperands(MI) == 3 &&
3598
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
73
    if (MCInst_getNumOperands(MI) == 3 &&
3607
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
73
    if (MCInst_getNumOperands(MI) == 3 &&
3616
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
73
    if (MCInst_getNumOperands(MI) == 3 &&
3625
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
73
    if (MCInst_getNumOperands(MI) == 3 &&
3634
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
73
    if (MCInst_getNumOperands(MI) == 3 &&
3643
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
73
    if (MCInst_getNumOperands(MI) == 3 &&
3652
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
73
    if (MCInst_getNumOperands(MI) == 3 &&
3661
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
73
    if (MCInst_getNumOperands(MI) == 3 &&
3670
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
73
    if (MCInst_getNumOperands(MI) == 3 &&
3679
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
73
    if (MCInst_getNumOperands(MI) == 3 &&
3688
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
73
    if (MCInst_getNumOperands(MI) == 3 &&
3697
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
73
    if (MCInst_getNumOperands(MI) == 3 &&
3706
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
73
    if (MCInst_getNumOperands(MI) == 3 &&
3715
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
73
    if (MCInst_getNumOperands(MI) == 3 &&
3724
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
73
    if (MCInst_getNumOperands(MI) == 3 &&
3733
73
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
73
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
73
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
73
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
73
    return NULL;
3742
213
  case SP_MOVXCCrr:
3743
213
    if (MCInst_getNumOperands(MI) == 3 &&
3744
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
213
    if (MCInst_getNumOperands(MI) == 3 &&
3755
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
213
    if (MCInst_getNumOperands(MI) == 3 &&
3766
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
213
    if (MCInst_getNumOperands(MI) == 3 &&
3777
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
213
    if (MCInst_getNumOperands(MI) == 3 &&
3788
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
213
    if (MCInst_getNumOperands(MI) == 3 &&
3799
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
213
    if (MCInst_getNumOperands(MI) == 3 &&
3810
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
213
    if (MCInst_getNumOperands(MI) == 3 &&
3821
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
213
    if (MCInst_getNumOperands(MI) == 3 &&
3832
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
213
    if (MCInst_getNumOperands(MI) == 3 &&
3843
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
213
    if (MCInst_getNumOperands(MI) == 3 &&
3854
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
213
    if (MCInst_getNumOperands(MI) == 3 &&
3865
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
213
    if (MCInst_getNumOperands(MI) == 3 &&
3876
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
213
    if (MCInst_getNumOperands(MI) == 3 &&
3887
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
213
    if (MCInst_getNumOperands(MI) == 3 &&
3898
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
213
    if (MCInst_getNumOperands(MI) == 3 &&
3909
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
213
    return NULL;
3920
244
  case SP_ORri:
3921
244
    if (MCInst_getNumOperands(MI) == 3 &&
3922
244
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
244
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
244
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
18
      AsmString = "mov $\x03, $\x01";
3927
18
      break;
3928
18
    }
3929
226
    return NULL;
3930
183
  case SP_ORrr:
3931
183
    if (MCInst_getNumOperands(MI) == 3 &&
3932
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
183
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
183
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
183
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
70
      AsmString = "mov $\x03, $\x01";
3939
70
      break;
3940
70
    }
3941
113
    return NULL;
3942
413
  case SP_RESTORErr:
3943
413
    if (MCInst_getNumOperands(MI) == 3 &&
3944
413
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
413
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
413
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
93
      AsmString = "restore";
3949
93
      break;
3950
93
    }
3951
320
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
3.73k
  case SP_TXCCri:
3971
3.73k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
3.73k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
3.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
3.73k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
3.73k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
314
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
314
      break;
3979
314
    }
3980
3.41k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
3.41k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
3.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
3.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
3.41k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
3.41k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
3.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
3.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
3.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
242
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
242
      break;
3996
242
    }
3997
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
3.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
3.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
339
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
339
      break;
4013
339
    }
4014
2.83k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
2.83k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
2.83k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
2.83k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
2.83k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
2.83k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
2.83k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
2.83k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
2.83k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
72
      AsmString = "te %xcc, $\x01 + $\x02";
4029
72
      break;
4030
72
    }
4031
2.76k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
2.76k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
2.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
2.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
2.76k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
2.76k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
2.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
2.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
2.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
553
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
553
      break;
4047
553
    }
4048
2.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
2.21k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
2.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
2.21k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
2.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
1.14k
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
1.14k
      break;
4064
1.14k
    }
4065
1.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.07k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.07k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.07k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
118
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
118
      break;
4081
118
    }
4082
952
    if (MCInst_getNumOperands(MI) == 3 &&
4083
952
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
952
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
952
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
952
    if (MCInst_getNumOperands(MI) == 3 &&
4091
952
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
952
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
952
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
952
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
81
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
81
      break;
4098
81
    }
4099
871
    if (MCInst_getNumOperands(MI) == 3 &&
4100
871
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
871
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
871
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
871
    if (MCInst_getNumOperands(MI) == 3 &&
4108
871
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
871
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
871
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
871
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
79
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
79
      break;
4115
79
    }
4116
792
    if (MCInst_getNumOperands(MI) == 3 &&
4117
792
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
792
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
792
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
792
    if (MCInst_getNumOperands(MI) == 3 &&
4125
792
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
792
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
792
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
792
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
24
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
24
      break;
4132
24
    }
4133
768
    if (MCInst_getNumOperands(MI) == 3 &&
4134
768
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
768
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
768
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
768
    if (MCInst_getNumOperands(MI) == 3 &&
4142
768
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
768
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
768
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
768
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
232
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
232
      break;
4149
232
    }
4150
536
    if (MCInst_getNumOperands(MI) == 3 &&
4151
536
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
536
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
536
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
536
    if (MCInst_getNumOperands(MI) == 3 &&
4159
536
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
536
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
536
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
536
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
37
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
37
      break;
4166
37
    }
4167
499
    if (MCInst_getNumOperands(MI) == 3 &&
4168
499
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
499
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
499
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
499
    if (MCInst_getNumOperands(MI) == 3 &&
4176
499
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
499
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
499
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
499
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
15
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
15
      break;
4183
15
    }
4184
484
    if (MCInst_getNumOperands(MI) == 3 &&
4185
484
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
484
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
484
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
484
    if (MCInst_getNumOperands(MI) == 3 &&
4193
484
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
484
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
484
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
484
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
141
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
141
      break;
4200
141
    }
4201
343
    if (MCInst_getNumOperands(MI) == 3 &&
4202
343
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
343
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
343
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
343
    if (MCInst_getNumOperands(MI) == 3 &&
4210
343
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
343
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
343
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
343
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
77
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
77
      break;
4217
77
    }
4218
266
    if (MCInst_getNumOperands(MI) == 3 &&
4219
266
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
266
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
266
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
266
    if (MCInst_getNumOperands(MI) == 3 &&
4227
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
266
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
266
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
266
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
266
      break;
4234
266
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.71k
  case SP_TXCCrr:
4245
2.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
92
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
92
      break;
4255
92
    }
4256
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.62k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
34
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
34
      break;
4276
34
    }
4277
2.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.58k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
343
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
343
      break;
4297
343
    }
4298
2.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.24k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
36
      AsmString = "te %xcc, $\x01 + $\x02";
4317
36
      break;
4318
36
    }
4319
2.20k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.20k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.20k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.20k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.20k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.20k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.20k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
27
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
27
      break;
4339
27
    }
4340
2.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.18k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.18k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.18k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.18k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.18k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.18k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.18k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
37
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
37
      break;
4360
37
    }
4361
2.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.14k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.14k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.14k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.14k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
77
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
77
      break;
4381
77
    }
4382
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.06k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
476
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
476
      break;
4402
476
    }
4403
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.59k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
86
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
86
      break;
4423
86
    }
4424
1.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.50k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.50k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.50k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.50k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
19
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
19
      break;
4444
19
    }
4445
1.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.48k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
172
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
172
      break;
4465
172
    }
4466
1.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.31k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.31k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.31k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.31k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
34
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
34
      break;
4486
34
    }
4487
1.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.27k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.27k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.27k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.27k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
305
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
305
      break;
4507
305
    }
4508
974
    if (MCInst_getNumOperands(MI) == 3 &&
4509
974
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
974
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
974
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
974
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
974
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
974
    if (MCInst_getNumOperands(MI) == 3 &&
4519
974
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
974
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
974
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
974
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
974
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
974
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
83
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
83
      break;
4528
83
    }
4529
891
    if (MCInst_getNumOperands(MI) == 3 &&
4530
891
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
891
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
891
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
891
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
891
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
891
    if (MCInst_getNumOperands(MI) == 3 &&
4540
891
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
891
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
891
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
891
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
891
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
891
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
187
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
187
      break;
4549
187
    }
4550
704
    if (MCInst_getNumOperands(MI) == 3 &&
4551
704
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
704
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
704
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
704
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
704
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
704
    if (MCInst_getNumOperands(MI) == 3 &&
4561
704
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
704
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
704
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
704
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
704
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
704
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
704
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
704
      break;
4570
704
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
108
  case SP_V9FCMPD:
4583
108
    if (MCInst_getNumOperands(MI) == 3 &&
4584
108
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
108
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
38
      AsmString = "fcmpd $\x02, $\x03";
4591
38
      break;
4592
38
    }
4593
70
    return NULL;
4594
689
  case SP_V9FCMPED:
4595
689
    if (MCInst_getNumOperands(MI) == 3 &&
4596
689
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
689
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
689
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
689
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
689
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
653
      AsmString = "fcmped $\x02, $\x03";
4603
653
      break;
4604
653
    }
4605
36
    return NULL;
4606
517
  case SP_V9FCMPEQ:
4607
517
    if (MCInst_getNumOperands(MI) == 3 &&
4608
517
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
517
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
35
      AsmString = "fcmpeq $\x02, $\x03";
4615
35
      break;
4616
35
    }
4617
482
    return NULL;
4618
1.00k
  case SP_V9FCMPES:
4619
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4620
1.00k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
1.00k
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
1.00k
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
935
      AsmString = "fcmpes $\x02, $\x03";
4627
935
      break;
4628
935
    }
4629
65
    return NULL;
4630
183
  case SP_V9FCMPQ:
4631
183
    if (MCInst_getNumOperands(MI) == 3 &&
4632
183
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
96
      AsmString = "fcmpq $\x02, $\x03";
4639
96
      break;
4640
96
    }
4641
87
    return NULL;
4642
434
  case SP_V9FCMPS:
4643
434
    if (MCInst_getNumOperands(MI) == 3 &&
4644
434
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
434
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
434
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
434
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
434
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
70
      AsmString = "fcmps $\x02, $\x03";
4651
70
      break;
4652
70
    }
4653
364
    return NULL;
4654
69
  case SP_V9FMOVD_FCC:
4655
69
    if (MCInst_getNumOperands(MI) == 4 &&
4656
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
69
    if (MCInst_getNumOperands(MI) == 4 &&
4669
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
69
    if (MCInst_getNumOperands(MI) == 4 &&
4682
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
69
    if (MCInst_getNumOperands(MI) == 4 &&
4695
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
69
    if (MCInst_getNumOperands(MI) == 4 &&
4708
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
69
    if (MCInst_getNumOperands(MI) == 4 &&
4721
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
69
    if (MCInst_getNumOperands(MI) == 4 &&
4734
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
69
    if (MCInst_getNumOperands(MI) == 4 &&
4747
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
69
    if (MCInst_getNumOperands(MI) == 4 &&
4760
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
69
    if (MCInst_getNumOperands(MI) == 4 &&
4773
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
69
    if (MCInst_getNumOperands(MI) == 4 &&
4786
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
69
    if (MCInst_getNumOperands(MI) == 4 &&
4799
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
69
    if (MCInst_getNumOperands(MI) == 4 &&
4812
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
69
    if (MCInst_getNumOperands(MI) == 4 &&
4825
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
69
    if (MCInst_getNumOperands(MI) == 4 &&
4838
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
69
    if (MCInst_getNumOperands(MI) == 4 &&
4851
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
69
    return NULL;
4864
72
  case SP_V9FMOVQ_FCC:
4865
72
    if (MCInst_getNumOperands(MI) == 4 &&
4866
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
72
    if (MCInst_getNumOperands(MI) == 4 &&
4879
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
72
    if (MCInst_getNumOperands(MI) == 4 &&
4892
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
72
    if (MCInst_getNumOperands(MI) == 4 &&
4905
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
72
    if (MCInst_getNumOperands(MI) == 4 &&
4918
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
72
    if (MCInst_getNumOperands(MI) == 4 &&
4931
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
72
    if (MCInst_getNumOperands(MI) == 4 &&
4944
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
72
    if (MCInst_getNumOperands(MI) == 4 &&
4957
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
72
    if (MCInst_getNumOperands(MI) == 4 &&
4970
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
72
    if (MCInst_getNumOperands(MI) == 4 &&
4983
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
72
    if (MCInst_getNumOperands(MI) == 4 &&
4996
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
72
    if (MCInst_getNumOperands(MI) == 4 &&
5009
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
72
    if (MCInst_getNumOperands(MI) == 4 &&
5022
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
72
    if (MCInst_getNumOperands(MI) == 4 &&
5035
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
72
    if (MCInst_getNumOperands(MI) == 4 &&
5048
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
72
    if (MCInst_getNumOperands(MI) == 4 &&
5061
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
72
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
72
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
72
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
72
    return NULL;
5074
135
  case SP_V9FMOVS_FCC:
5075
135
    if (MCInst_getNumOperands(MI) == 4 &&
5076
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
135
    if (MCInst_getNumOperands(MI) == 4 &&
5089
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
135
    if (MCInst_getNumOperands(MI) == 4 &&
5102
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
135
    if (MCInst_getNumOperands(MI) == 4 &&
5115
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
135
    if (MCInst_getNumOperands(MI) == 4 &&
5128
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
135
    if (MCInst_getNumOperands(MI) == 4 &&
5141
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
135
    if (MCInst_getNumOperands(MI) == 4 &&
5154
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
135
    if (MCInst_getNumOperands(MI) == 4 &&
5167
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
135
    if (MCInst_getNumOperands(MI) == 4 &&
5180
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
135
    if (MCInst_getNumOperands(MI) == 4 &&
5193
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
135
    if (MCInst_getNumOperands(MI) == 4 &&
5206
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
135
    if (MCInst_getNumOperands(MI) == 4 &&
5219
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
135
    if (MCInst_getNumOperands(MI) == 4 &&
5232
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
135
    if (MCInst_getNumOperands(MI) == 4 &&
5245
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
135
    if (MCInst_getNumOperands(MI) == 4 &&
5258
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
135
    if (MCInst_getNumOperands(MI) == 4 &&
5271
135
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
135
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
135
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
135
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
135
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
135
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
135
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
135
    return NULL;
5284
216
  case SP_V9MOVFCCri:
5285
216
    if (MCInst_getNumOperands(MI) == 4 &&
5286
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
216
    if (MCInst_getNumOperands(MI) == 4 &&
5297
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
216
    if (MCInst_getNumOperands(MI) == 4 &&
5308
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
216
    if (MCInst_getNumOperands(MI) == 4 &&
5319
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
216
    if (MCInst_getNumOperands(MI) == 4 &&
5330
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
216
    if (MCInst_getNumOperands(MI) == 4 &&
5341
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
216
    if (MCInst_getNumOperands(MI) == 4 &&
5352
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
216
    if (MCInst_getNumOperands(MI) == 4 &&
5363
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
216
    if (MCInst_getNumOperands(MI) == 4 &&
5374
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
216
    if (MCInst_getNumOperands(MI) == 4 &&
5385
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
216
    if (MCInst_getNumOperands(MI) == 4 &&
5396
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
216
    if (MCInst_getNumOperands(MI) == 4 &&
5407
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
216
    if (MCInst_getNumOperands(MI) == 4 &&
5418
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
216
    if (MCInst_getNumOperands(MI) == 4 &&
5429
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
216
    if (MCInst_getNumOperands(MI) == 4 &&
5440
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
216
    if (MCInst_getNumOperands(MI) == 4 &&
5451
216
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
216
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
216
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
216
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
216
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
216
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
216
    return NULL;
5462
379
  case SP_V9MOVFCCrr:
5463
379
    if (MCInst_getNumOperands(MI) == 4 &&
5464
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
379
    if (MCInst_getNumOperands(MI) == 4 &&
5477
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
379
    if (MCInst_getNumOperands(MI) == 4 &&
5490
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
379
    if (MCInst_getNumOperands(MI) == 4 &&
5503
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
379
    if (MCInst_getNumOperands(MI) == 4 &&
5516
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
379
    if (MCInst_getNumOperands(MI) == 4 &&
5529
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
379
    if (MCInst_getNumOperands(MI) == 4 &&
5542
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
379
    if (MCInst_getNumOperands(MI) == 4 &&
5555
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
379
    if (MCInst_getNumOperands(MI) == 4 &&
5568
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
379
    if (MCInst_getNumOperands(MI) == 4 &&
5581
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
379
    if (MCInst_getNumOperands(MI) == 4 &&
5594
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
379
    if (MCInst_getNumOperands(MI) == 4 &&
5607
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
379
    if (MCInst_getNumOperands(MI) == 4 &&
5620
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
379
    if (MCInst_getNumOperands(MI) == 4 &&
5633
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
379
    if (MCInst_getNumOperands(MI) == 4 &&
5646
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
379
    if (MCInst_getNumOperands(MI) == 4 &&
5659
379
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
379
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
379
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
379
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
379
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
379
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
379
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
379
    return NULL;
5672
69.3k
  }
5673
5674
28.3k
  tmp = cs_strdup(AsmString);
5675
28.3k
  AsmMnem = tmp;
5676
181k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
181k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
28.2k
      *AsmOps = '\0';
5679
28.2k
      AsmOps++;
5680
28.2k
      break;
5681
28.2k
    }
5682
181k
  }
5683
28.3k
  SStream_concat0(OS, AsmMnem);
5684
28.3k
  if (*AsmOps) {
5685
28.2k
    SStream_concat0(OS, "\t");
5686
28.2k
    if (strstr(AsmOps, "icc"))
5687
5.30k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
28.2k
    if (strstr(AsmOps, "xcc"))
5689
9.76k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
197k
    for (c = AsmOps; *c; c++) {
5691
168k
      if (*c == '$') {
5692
42.8k
        c += 1;
5693
42.8k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
42.8k
          printOperand(MI, *c - 1, OS);
5701
126k
      } else {
5702
126k
        SStream_concat(OS, "%c", *c);
5703
126k
      }
5704
168k
    }
5705
28.2k
  }
5706
28.3k
  return tmp;
5707
69.3k
}
5708
5709
#endif // PRINT_ALIAS_INSTR