Coverage Report

Created: 2025-07-11 06:32

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
40.7k
{
20
40.7k
  static const uint32_t OpInfo[] = {
21
40.7k
    0U, // PHI
22
40.7k
    0U, // INLINEASM
23
40.7k
    0U, // CFI_INSTRUCTION
24
40.7k
    0U, // EH_LABEL
25
40.7k
    0U, // GC_LABEL
26
40.7k
    0U, // KILL
27
40.7k
    0U, // EXTRACT_SUBREG
28
40.7k
    0U, // INSERT_SUBREG
29
40.7k
    0U, // IMPLICIT_DEF
30
40.7k
    0U, // SUBREG_TO_REG
31
40.7k
    0U, // COPY_TO_REGCLASS
32
40.7k
    2452U,  // DBG_VALUE
33
40.7k
    0U, // REG_SEQUENCE
34
40.7k
    0U, // COPY
35
40.7k
    2445U,  // BUNDLE
36
40.7k
    2462U,  // LIFETIME_START
37
40.7k
    2432U,  // LIFETIME_END
38
40.7k
    0U, // STACKMAP
39
40.7k
    0U, // PATCHPOINT
40
40.7k
    0U, // LOAD_STACK_GUARD
41
40.7k
    0U, // STATEPOINT
42
40.7k
    0U, // FRAME_ALLOC
43
40.7k
    4688U,  // ADDCCri
44
40.7k
    4688U,  // ADDCCrr
45
40.7k
    5925U,  // ADDCri
46
40.7k
    5925U,  // ADDCrr
47
40.7k
    4772U,  // ADDEri
48
40.7k
    4772U,  // ADDErr
49
40.7k
    4786U,  // ADDXC
50
40.7k
    4678U,  // ADDXCCC
51
40.7k
    4808U,  // ADDXri
52
40.7k
    4808U,  // ADDXrr
53
40.7k
    4808U,  // ADDri
54
40.7k
    4808U,  // ADDrr
55
40.7k
    74166U, // ADJCALLSTACKDOWN
56
40.7k
    74185U, // ADJCALLSTACKUP
57
40.7k
    5497U,  // ALIGNADDR
58
40.7k
    5127U,  // ALIGNADDRL
59
40.7k
    4695U,  // ANDCCri
60
40.7k
    4695U,  // ANDCCrr
61
40.7k
    4718U,  // ANDNCCri
62
40.7k
    4718U,  // ANDNCCrr
63
40.7k
    5182U,  // ANDNri
64
40.7k
    5182U,  // ANDNrr
65
40.7k
    5182U,  // ANDXNrr
66
40.7k
    4876U,  // ANDXri
67
40.7k
    4876U,  // ANDXrr
68
40.7k
    4876U,  // ANDri
69
40.7k
    4876U,  // ANDrr
70
40.7k
    4502U,  // ARRAY16
71
40.7k
    4255U,  // ARRAY32
72
40.7k
    4526U,  // ARRAY8
73
40.7k
    0U, // ATOMIC_LOAD_ADD_32
74
40.7k
    0U, // ATOMIC_LOAD_ADD_64
75
40.7k
    0U, // ATOMIC_LOAD_AND_32
76
40.7k
    0U, // ATOMIC_LOAD_AND_64
77
40.7k
    0U, // ATOMIC_LOAD_MAX_32
78
40.7k
    0U, // ATOMIC_LOAD_MAX_64
79
40.7k
    0U, // ATOMIC_LOAD_MIN_32
80
40.7k
    0U, // ATOMIC_LOAD_MIN_64
81
40.7k
    0U, // ATOMIC_LOAD_NAND_32
82
40.7k
    0U, // ATOMIC_LOAD_NAND_64
83
40.7k
    0U, // ATOMIC_LOAD_OR_32
84
40.7k
    0U, // ATOMIC_LOAD_OR_64
85
40.7k
    0U, // ATOMIC_LOAD_SUB_32
86
40.7k
    0U, // ATOMIC_LOAD_SUB_64
87
40.7k
    0U, // ATOMIC_LOAD_UMAX_32
88
40.7k
    0U, // ATOMIC_LOAD_UMAX_64
89
40.7k
    0U, // ATOMIC_LOAD_UMIN_32
90
40.7k
    0U, // ATOMIC_LOAD_UMIN_64
91
40.7k
    0U, // ATOMIC_LOAD_XOR_32
92
40.7k
    0U, // ATOMIC_LOAD_XOR_64
93
40.7k
    0U, // ATOMIC_SWAP_64
94
40.7k
    74271U, // BA
95
40.7k
    1194492U, // BCOND
96
40.7k
    1260028U, // BCONDA
97
40.7k
    17659U, // BINDri
98
40.7k
    17659U, // BINDrr
99
40.7k
    5065U,  // BMASK
100
40.7k
    145915U,  // BPFCC
101
40.7k
    211451U,  // BPFCCA
102
40.7k
    276987U,  // BPFCCANT
103
40.7k
    342523U,  // BPFCCNT
104
40.7k
    2106465U, // BPGEZapn
105
40.7k
    2105838U, // BPGEZapt
106
40.7k
    2106532U, // BPGEZnapn
107
40.7k
    2107288U, // BPGEZnapt
108
40.7k
    2106489U, // BPGZapn
109
40.7k
    2105856U, // BPGZapt
110
40.7k
    2106552U, // BPGZnapn
111
40.7k
    2107384U, // BPGZnapt
112
40.7k
    1456636U, // BPICC
113
40.7k
    473596U,  // BPICCA
114
40.7k
    539132U,  // BPICCANT
115
40.7k
    604668U,  // BPICCNT
116
40.7k
    2106477U, // BPLEZapn
117
40.7k
    2105847U, // BPLEZapt
118
40.7k
    2106542U, // BPLEZnapn
119
40.7k
    2107337U, // BPLEZnapt
120
40.7k
    2106500U, // BPLZapn
121
40.7k
    2105864U, // BPLZapt
122
40.7k
    2106561U, // BPLZnapn
123
40.7k
    2107428U, // BPLZnapt
124
40.7k
    2106511U, // BPNZapn
125
40.7k
    2105872U, // BPNZapt
126
40.7k
    2106570U, // BPNZnapn
127
40.7k
    2107472U, // BPNZnapt
128
40.7k
    1718780U, // BPXCC
129
40.7k
    735740U,  // BPXCCA
130
40.7k
    801276U,  // BPXCCANT
131
40.7k
    866812U,  // BPXCCNT
132
40.7k
    2106522U, // BPZapn
133
40.7k
    2105880U, // BPZapt
134
40.7k
    2106579U, // BPZnapn
135
40.7k
    2107505U, // BPZnapt
136
40.7k
    4983U,  // BSHUFFLE
137
40.7k
    74742U, // CALL
138
40.7k
    17398U, // CALLri
139
40.7k
    17398U, // CALLrr
140
40.7k
    924148U,  // CASXrr
141
40.7k
    924129U,  // CASrr
142
40.7k
    74001U, // CMASK16
143
40.7k
    73833U, // CMASK32
144
40.7k
    74150U, // CMASK8
145
40.7k
    2106607U, // CMPri
146
40.7k
    2106607U, // CMPrr
147
40.7k
    4332U,  // EDGE16
148
40.7k
    5081U,  // EDGE16L
149
40.7k
    5198U,  // EDGE16LN
150
40.7k
    5165U,  // EDGE16N
151
40.7k
    4164U,  // EDGE32
152
40.7k
    5072U,  // EDGE32L
153
40.7k
    5188U,  // EDGE32LN
154
40.7k
    5156U,  // EDGE32N
155
40.7k
    4511U,  // EDGE8
156
40.7k
    5090U,  // EDGE8L
157
40.7k
    5208U,  // EDGE8LN
158
40.7k
    5174U,  // EDGE8N
159
40.7k
    1053516U, // FABSD
160
40.7k
    1054031U, // FABSQ
161
40.7k
    1054376U, // FABSS
162
40.7k
    4813U,  // FADDD
163
40.7k
    5383U,  // FADDQ
164
40.7k
    5645U,  // FADDS
165
40.7k
    4648U,  // FALIGNADATA
166
40.7k
    4875U,  // FAND
167
40.7k
    4112U,  // FANDNOT1
168
40.7k
    5544U,  // FANDNOT1S
169
40.7k
    4271U,  // FANDNOT2
170
40.7k
    5591U,  // FANDNOT2S
171
40.7k
    5677U,  // FANDS
172
40.7k
    1194491U, // FBCOND
173
40.7k
    1260027U, // FBCONDA
174
40.7k
    4394U,  // FCHKSM16
175
40.7k
    2106173U, // FCMPD
176
40.7k
    4413U,  // FCMPEQ16
177
40.7k
    4226U,  // FCMPEQ32
178
40.7k
    4432U,  // FCMPGT16
179
40.7k
    4245U,  // FCMPGT32
180
40.7k
    4340U,  // FCMPLE16
181
40.7k
    4172U,  // FCMPLE32
182
40.7k
    4350U,  // FCMPNE16
183
40.7k
    4182U,  // FCMPNE32
184
40.7k
    2106696U, // FCMPQ
185
40.7k
    2107005U, // FCMPS
186
40.7k
    4960U,  // FDIVD
187
40.7k
    5475U,  // FDIVQ
188
40.7k
    5815U,  // FDIVS
189
40.7k
    5405U,  // FDMULQ
190
40.7k
    1053620U, // FDTOI
191
40.7k
    1053996U, // FDTOQ
192
40.7k
    1054305U, // FDTOS
193
40.7k
    1054536U, // FDTOX
194
40.7k
    1053464U, // FEXPAND
195
40.7k
    4820U,  // FHADDD
196
40.7k
    5652U,  // FHADDS
197
40.7k
    4800U,  // FHSUBD
198
40.7k
    5637U,  // FHSUBS
199
40.7k
    1053473U, // FITOD
200
40.7k
    1054003U, // FITOQ
201
40.7k
    1054312U, // FITOS
202
40.7k
    6300484U, // FLCMPD
203
40.7k
    6301316U, // FLCMPS
204
40.7k
    2606U,  // FLUSHW
205
40.7k
    4404U,  // FMEAN16
206
40.7k
    1053543U, // FMOVD
207
40.7k
    1006078U, // FMOVD_FCC
208
40.7k
    23484926U,  // FMOVD_ICC
209
40.7k
    23747070U,  // FMOVD_XCC
210
40.7k
    1054058U, // FMOVQ
211
40.7k
    1006102U, // FMOVQ_FCC
212
40.7k
    23484950U,  // FMOVQ_ICC
213
40.7k
    23747094U,  // FMOVQ_XCC
214
40.7k
    6018U,  // FMOVRGEZD
215
40.7k
    6029U,  // FMOVRGEZQ
216
40.7k
    6056U,  // FMOVRGEZS
217
40.7k
    6116U,  // FMOVRGZD
218
40.7k
    6126U,  // FMOVRGZQ
219
40.7k
    6150U,  // FMOVRGZS
220
40.7k
    6067U,  // FMOVRLEZD
221
40.7k
    6078U,  // FMOVRLEZQ
222
40.7k
    6105U,  // FMOVRLEZS
223
40.7k
    6160U,  // FMOVRLZD
224
40.7k
    6170U,  // FMOVRLZQ
225
40.7k
    6194U,  // FMOVRLZS
226
40.7k
    6204U,  // FMOVRNZD
227
40.7k
    6214U,  // FMOVRNZQ
228
40.7k
    6238U,  // FMOVRNZS
229
40.7k
    6009U,  // FMOVRZD
230
40.7k
    6248U,  // FMOVRZQ
231
40.7k
    6269U,  // FMOVRZS
232
40.7k
    1054398U, // FMOVS
233
40.7k
    1006114U, // FMOVS_FCC
234
40.7k
    23484962U,  // FMOVS_ICC
235
40.7k
    23747106U,  // FMOVS_XCC
236
40.7k
    4490U,  // FMUL8SUX16
237
40.7k
    4465U,  // FMUL8ULX16
238
40.7k
    4442U,  // FMUL8X16
239
40.7k
    5098U,  // FMUL8X16AL
240
40.7k
    5849U,  // FMUL8X16AU
241
40.7k
    4860U,  // FMULD
242
40.7k
    4477U,  // FMULD8SUX16
243
40.7k
    4452U,  // FMULD8ULX16
244
40.7k
    5413U,  // FMULQ
245
40.7k
    5714U,  // FMULS
246
40.7k
    4837U,  // FNADDD
247
40.7k
    5669U,  // FNADDS
248
40.7k
    4881U,  // FNAND
249
40.7k
    5684U,  // FNANDS
250
40.7k
    1053429U, // FNEGD
251
40.7k
    1053974U, // FNEGQ
252
40.7k
    1054283U, // FNEGS
253
40.7k
    4828U,  // FNHADDD
254
40.7k
    5660U,  // FNHADDS
255
40.7k
    4828U,  // FNMULD
256
40.7k
    5660U,  // FNMULS
257
40.7k
    5513U,  // FNOR
258
40.7k
    5778U,  // FNORS
259
40.7k
    1052698U, // FNOT1
260
40.7k
    1054131U, // FNOT1S
261
40.7k
    1052857U, // FNOT2
262
40.7k
    1054178U, // FNOT2S
263
40.7k
    5660U,  // FNSMULD
264
40.7k
    74625U, // FONE
265
40.7k
    75324U, // FONES
266
40.7k
    5508U,  // FOR
267
40.7k
    4129U,  // FORNOT1
268
40.7k
    5563U,  // FORNOT1S
269
40.7k
    4288U,  // FORNOT2
270
40.7k
    5610U,  // FORNOT2S
271
40.7k
    5772U,  // FORS
272
40.7k
    1052936U, // FPACK16
273
40.7k
    4192U,  // FPACK32
274
40.7k
    1054507U, // FPACKFIX
275
40.7k
    4323U,  // FPADD16
276
40.7k
    5620U,  // FPADD16S
277
40.7k
    4155U,  // FPADD32
278
40.7k
    5573U,  // FPADD32S
279
40.7k
    4297U,  // FPADD64
280
40.7k
    4974U,  // FPMERGE
281
40.7k
    4314U,  // FPSUB16
282
40.7k
    4580U,  // FPSUB16S
283
40.7k
    4146U,  // FPSUB32
284
40.7k
    4570U,  // FPSUB32S
285
40.7k
    1053480U, // FQTOD
286
40.7k
    1053627U, // FQTOI
287
40.7k
    1054319U, // FQTOS
288
40.7k
    1054552U, // FQTOX
289
40.7k
    4423U,  // FSLAS16
290
40.7k
    4236U,  // FSLAS32
291
40.7k
    4378U,  // FSLL16
292
40.7k
    4210U,  // FSLL32
293
40.7k
    4867U,  // FSMULD
294
40.7k
    1053523U, // FSQRTD
295
40.7k
    1054038U, // FSQRTQ
296
40.7k
    1054383U, // FSQRTS
297
40.7k
    4306U,  // FSRA16
298
40.7k
    4138U,  // FSRA32
299
40.7k
    1052681U, // FSRC1
300
40.7k
    1054112U, // FSRC1S
301
40.7k
    1052840U, // FSRC2
302
40.7k
    1054159U, // FSRC2S
303
40.7k
    4386U,  // FSRL16
304
40.7k
    4218U,  // FSRL32
305
40.7k
    1053487U, // FSTOD
306
40.7k
    1053634U, // FSTOI
307
40.7k
    1054010U, // FSTOQ
308
40.7k
    1054559U, // FSTOX
309
40.7k
    4793U,  // FSUBD
310
40.7k
    5376U,  // FSUBQ
311
40.7k
    5630U,  // FSUBS
312
40.7k
    5519U,  // FXNOR
313
40.7k
    5785U,  // FXNORS
314
40.7k
    5526U,  // FXOR
315
40.7k
    5793U,  // FXORS
316
40.7k
    1053494U, // FXTOD
317
40.7k
    1054017U, // FXTOQ
318
40.7k
    1054326U, // FXTOS
319
40.7k
    74984U, // FZERO
320
40.7k
    75353U, // FZEROS
321
40.7k
    24584U, // GETPCX
322
40.7k
    1078273U, // JMPLri
323
40.7k
    1078273U, // JMPLrr
324
40.7k
    1997243U, // LDDFri
325
40.7k
    1997243U, // LDDFrr
326
40.7k
    1997249U, // LDFri
327
40.7k
    1997249U, // LDFrr
328
40.7k
    1997275U, // LDQFri
329
40.7k
    1997275U, // LDQFrr
330
40.7k
    1997229U, // LDSBri
331
40.7k
    1997229U, // LDSBrr
332
40.7k
    1997254U, // LDSHri
333
40.7k
    1997254U, // LDSHrr
334
40.7k
    1997287U, // LDSWri
335
40.7k
    1997287U, // LDSWrr
336
40.7k
    1997236U, // LDUBri
337
40.7k
    1997236U, // LDUBrr
338
40.7k
    1997261U, // LDUHri
339
40.7k
    1997261U, // LDUHrr
340
40.7k
    1997294U, // LDXri
341
40.7k
    1997294U, // LDXrr
342
40.7k
    1997249U, // LDri
343
40.7k
    1997249U, // LDrr
344
40.7k
    33480U, // LEAX_ADDri
345
40.7k
    33480U, // LEA_ADDri
346
40.7k
    1054405U, // LZCNT
347
40.7k
    75121U, // MEMBARi
348
40.7k
    1054543U, // MOVDTOX
349
40.7k
    1006122U, // MOVFCCri
350
40.7k
    1006122U, // MOVFCCrr
351
40.7k
    23484970U,  // MOVICCri
352
40.7k
    23484970U,  // MOVICCrr
353
40.7k
    6047U,  // MOVRGEZri
354
40.7k
    6047U,  // MOVRGEZrr
355
40.7k
    6142U,  // MOVRGZri
356
40.7k
    6142U,  // MOVRGZrr
357
40.7k
    6096U,  // MOVRLEZri
358
40.7k
    6096U,  // MOVRLEZrr
359
40.7k
    6186U,  // MOVRLZri
360
40.7k
    6186U,  // MOVRLZrr
361
40.7k
    6230U,  // MOVRNZri
362
40.7k
    6230U,  // MOVRNZrr
363
40.7k
    6262U,  // MOVRRZri
364
40.7k
    6262U,  // MOVRRZrr
365
40.7k
    1054469U, // MOVSTOSW
366
40.7k
    1054479U, // MOVSTOUW
367
40.7k
    1054543U, // MOVWTOS
368
40.7k
    23747114U,  // MOVXCCri
369
40.7k
    23747114U,  // MOVXCCrr
370
40.7k
    1054543U, // MOVXTOD
371
40.7k
    5954U,  // MULXri
372
40.7k
    5954U,  // MULXrr
373
40.7k
    2578U,  // NOP
374
40.7k
    4735U,  // ORCCri
375
40.7k
    4735U,  // ORCCrr
376
40.7k
    4726U,  // ORNCCri
377
40.7k
    4726U,  // ORNCCrr
378
40.7k
    5339U,  // ORNri
379
40.7k
    5339U,  // ORNrr
380
40.7k
    5339U,  // ORXNrr
381
40.7k
    5509U,  // ORXri
382
40.7k
    5509U,  // ORXrr
383
40.7k
    5509U,  // ORri
384
40.7k
    5509U,  // ORrr
385
40.7k
    5836U,  // PDIST
386
40.7k
    5344U,  // PDISTN
387
40.7k
    1053356U, // POPCrr
388
40.7k
    73729U, // RDY
389
40.7k
    4999U,  // RESTOREri
390
40.7k
    4999U,  // RESTORErr
391
40.7k
    76132U, // RET
392
40.7k
    76141U, // RETL
393
40.7k
    18131U, // RETTri
394
40.7k
    18131U, // RETTrr
395
40.7k
    5008U,  // SAVEri
396
40.7k
    5008U,  // SAVErr
397
40.7k
    4748U,  // SDIVCCri
398
40.7k
    4748U,  // SDIVCCrr
399
40.7k
    5995U,  // SDIVXri
400
40.7k
    5995U,  // SDIVXrr
401
40.7k
    5861U,  // SDIVri
402
40.7k
    5861U,  // SDIVrr
403
40.7k
    2182U,  // SELECT_CC_DFP_FCC
404
40.7k
    2293U,  // SELECT_CC_DFP_ICC
405
40.7k
    2238U,  // SELECT_CC_FP_FCC
406
40.7k
    2349U,  // SELECT_CC_FP_ICC
407
40.7k
    2265U,  // SELECT_CC_Int_FCC
408
40.7k
    2376U,  // SELECT_CC_Int_ICC
409
40.7k
    2210U,  // SELECT_CC_QFP_FCC
410
40.7k
    2321U,  // SELECT_CC_QFP_ICC
411
40.7k
    1053595U, // SETHIXi
412
40.7k
    1053595U, // SETHIi
413
40.7k
    2569U,  // SHUTDOWN
414
40.7k
    2564U,  // SIAM
415
40.7k
    5941U,  // SLLXri
416
40.7k
    5941U,  // SLLXrr
417
40.7k
    5116U,  // SLLri
418
40.7k
    5116U,  // SLLrr
419
40.7k
    4702U,  // SMULCCri
420
40.7k
    4702U,  // SMULCCrr
421
40.7k
    5144U,  // SMULri
422
40.7k
    5144U,  // SMULrr
423
40.7k
    5913U,  // SRAXri
424
40.7k
    5913U,  // SRAXrr
425
40.7k
    4643U,  // SRAri
426
40.7k
    4643U,  // SRArr
427
40.7k
    5947U,  // SRLXri
428
40.7k
    5947U,  // SRLXrr
429
40.7k
    5139U,  // SRLri
430
40.7k
    5139U,  // SRLrr
431
40.7k
    2588U,  // STBAR
432
40.7k
    37428U, // STBri
433
40.7k
    37428U, // STBrr
434
40.7k
    37723U, // STDFri
435
40.7k
    37723U, // STDFrr
436
40.7k
    38607U, // STFri
437
40.7k
    38607U, // STFrr
438
40.7k
    37782U, // STHri
439
40.7k
    37782U, // STHrr
440
40.7k
    38238U, // STQFri
441
40.7k
    38238U, // STQFrr
442
40.7k
    38758U, // STXri
443
40.7k
    38758U, // STXrr
444
40.7k
    38607U, // STri
445
40.7k
    38607U, // STrr
446
40.7k
    4671U,  // SUBCCri
447
40.7k
    4671U,  // SUBCCrr
448
40.7k
    5919U,  // SUBCri
449
40.7k
    5919U,  // SUBCrr
450
40.7k
    4764U,  // SUBEri
451
40.7k
    4764U,  // SUBErr
452
40.7k
    4665U,  // SUBXri
453
40.7k
    4665U,  // SUBXrr
454
40.7k
    4665U,  // SUBri
455
40.7k
    4665U,  // SUBrr
456
40.7k
    1997268U, // SWAPri
457
40.7k
    1997268U, // SWAPrr
458
40.7k
    2422U,  // TA3
459
40.7k
    2427U,  // TA5
460
40.7k
    5883U,  // TADDCCTVri
461
40.7k
    5883U,  // TADDCCTVrr
462
40.7k
    4687U,  // TADDCCri
463
40.7k
    4687U,  // TADDCCrr
464
40.7k
    9873960U, // TICCri
465
40.7k
    9873960U, // TICCrr
466
40.7k
    37753544U,  // TLS_ADDXrr
467
40.7k
    37753544U,  // TLS_ADDrr
468
40.7k
    2106358U, // TLS_CALL
469
40.7k
    39746030U,  // TLS_LDXrr
470
40.7k
    39745985U,  // TLS_LDrr
471
40.7k
    5873U,  // TSUBCCTVri
472
40.7k
    5873U,  // TSUBCCTVrr
473
40.7k
    4670U,  // TSUBCCri
474
40.7k
    4670U,  // TSUBCCrr
475
40.7k
    10136104U,  // TXCCri
476
40.7k
    10136104U,  // TXCCrr
477
40.7k
    4756U,  // UDIVCCri
478
40.7k
    4756U,  // UDIVCCrr
479
40.7k
    6002U,  // UDIVXri
480
40.7k
    6002U,  // UDIVXrr
481
40.7k
    5867U,  // UDIVri
482
40.7k
    5867U,  // UDIVrr
483
40.7k
    4710U,  // UMULCCri
484
40.7k
    4710U,  // UMULCCrr
485
40.7k
    5026U,  // UMULXHI
486
40.7k
    5150U,  // UMULri
487
40.7k
    5150U,  // UMULrr
488
40.7k
    74996U, // UNIMP
489
40.7k
    6300477U, // V9FCMPD
490
40.7k
    6300397U, // V9FCMPED
491
40.7k
    6300942U, // V9FCMPEQ
492
40.7k
    6301251U, // V9FCMPES
493
40.7k
    6301000U, // V9FCMPQ
494
40.7k
    6301309U, // V9FCMPS
495
40.7k
    47614U, // V9FMOVD_FCC
496
40.7k
    47638U, // V9FMOVQ_FCC
497
40.7k
    47650U, // V9FMOVS_FCC
498
40.7k
    47658U, // V9MOVFCCri
499
40.7k
    47658U, // V9MOVFCCrr
500
40.7k
    14689692U,  // WRYri
501
40.7k
    14689692U,  // WRYrr
502
40.7k
    5953U,  // XMULX
503
40.7k
    5035U,  // XMULXHI
504
40.7k
    4733U,  // XNORCCri
505
40.7k
    4733U,  // XNORCCrr
506
40.7k
    5520U,  // XNORXrr
507
40.7k
    5520U,  // XNORri
508
40.7k
    5520U,  // XNORrr
509
40.7k
    4741U,  // XORCCri
510
40.7k
    4741U,  // XORCCrr
511
40.7k
    5527U,  // XORXri
512
40.7k
    5527U,  // XORXrr
513
40.7k
    5527U,  // XORri
514
40.7k
    5527U,  // XORrr
515
40.7k
    0U
516
40.7k
  };
517
518
40.7k
#ifndef CAPSTONE_DIET
519
40.7k
  static const char AsmStrs[] = {
520
40.7k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
40.7k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
40.7k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
40.7k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
40.7k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
40.7k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
40.7k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
40.7k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
40.7k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
40.7k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
40.7k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
40.7k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
40.7k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
40.7k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
40.7k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
40.7k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
40.7k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
40.7k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
40.7k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
40.7k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
40.7k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
40.7k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
40.7k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
40.7k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
40.7k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
40.7k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
40.7k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
40.7k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
40.7k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
40.7k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
40.7k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
40.7k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
40.7k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
40.7k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
40.7k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
40.7k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
40.7k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
40.7k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
40.7k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
40.7k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
40.7k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
40.7k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
40.7k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
40.7k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
40.7k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
40.7k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
40.7k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
40.7k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
40.7k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
40.7k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
40.7k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
40.7k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
40.7k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
40.7k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
40.7k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
40.7k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
40.7k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
40.7k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
40.7k
  /* 542 */ 'b', 'a', 32, 0,
579
40.7k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
40.7k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
40.7k
  /* 563 */ 's', 't', 'b', 32, 0,
582
40.7k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
40.7k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
40.7k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
40.7k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
40.7k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
40.7k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
40.7k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
40.7k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
40.7k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
40.7k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
40.7k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
40.7k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
40.7k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
40.7k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
40.7k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
40.7k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
40.7k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
40.7k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
40.7k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
40.7k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
40.7k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
40.7k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
40.7k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
40.7k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
40.7k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
40.7k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
40.7k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
40.7k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
40.7k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
40.7k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
40.7k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
40.7k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
40.7k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
40.7k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
40.7k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
40.7k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
40.7k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
40.7k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
40.7k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
40.7k
  /* 858 */ 's', 't', 'd', 32, 0,
622
40.7k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
40.7k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
40.7k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
40.7k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
40.7k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
40.7k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
40.7k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
40.7k
  /* 917 */ 's', 't', 'h', 32, 0,
630
40.7k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
40.7k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
40.7k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
40.7k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
40.7k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
40.7k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
40.7k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
40.7k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
40.7k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
40.7k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
40.7k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
40.7k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
40.7k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
40.7k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
40.7k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
40.7k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
40.7k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
40.7k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
40.7k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
40.7k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
40.7k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
40.7k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
40.7k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
40.7k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
40.7k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
40.7k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
40.7k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
40.7k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
40.7k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
40.7k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
40.7k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
40.7k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
40.7k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
40.7k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
40.7k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
40.7k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
40.7k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
40.7k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
40.7k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
40.7k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
40.7k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
40.7k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
40.7k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
40.7k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
40.7k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
40.7k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
40.7k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
40.7k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
40.7k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
40.7k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
40.7k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
40.7k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
40.7k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
40.7k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
40.7k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
40.7k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
40.7k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
40.7k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
40.7k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
40.7k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
40.7k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
40.7k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
40.7k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
40.7k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
40.7k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
40.7k
  /* 1435 */ 'w', 'r', 32, 0,
696
40.7k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
40.7k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
40.7k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
40.7k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
40.7k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
40.7k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
40.7k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
40.7k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
40.7k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
40.7k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
40.7k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
40.7k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
40.7k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
40.7k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
40.7k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
40.7k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
40.7k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
40.7k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
40.7k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
40.7k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
40.7k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
40.7k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
40.7k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
40.7k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
40.7k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
40.7k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
40.7k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
40.7k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
40.7k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
40.7k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
40.7k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
40.7k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
40.7k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
40.7k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
40.7k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
40.7k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
40.7k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
40.7k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
40.7k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
40.7k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
40.7k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
40.7k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
40.7k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
40.7k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
40.7k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
40.7k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
40.7k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
40.7k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
40.7k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
40.7k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
40.7k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
40.7k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
40.7k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
40.7k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
40.7k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
40.7k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
40.7k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
40.7k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
40.7k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
40.7k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
40.7k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
40.7k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
40.7k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
40.7k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
40.7k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
40.7k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
40.7k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
40.7k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
40.7k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
40.7k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
40.7k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
40.7k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
40.7k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
40.7k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
40.7k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
40.7k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
40.7k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
40.7k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
40.7k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
40.7k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
40.7k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
40.7k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
40.7k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
40.7k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
40.7k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
40.7k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
40.7k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
40.7k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
40.7k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
40.7k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
40.7k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
40.7k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
40.7k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
40.7k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
40.7k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
40.7k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
40.7k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
40.7k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
40.7k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
40.7k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
40.7k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
40.7k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
40.7k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
40.7k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
40.7k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
40.7k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
40.7k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
40.7k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
40.7k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
40.7k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
40.7k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
40.7k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
40.7k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
40.7k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
40.7k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
40.7k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
40.7k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
40.7k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
40.7k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
40.7k
  /* 2554 */ 'f', 'b', 0,
816
40.7k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
40.7k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
40.7k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
40.7k
  /* 2577 */ 'n', 'o', 'p', 0,
820
40.7k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
40.7k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
40.7k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
40.7k
  /* 2599 */ 't', 0,
824
40.7k
  /* 2601 */ 'm', 'o', 'v', 0,
825
40.7k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
40.7k
  };
827
40.7k
#endif
828
829
  // Emit the opcode for the instruction.
830
40.7k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
40.7k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
40.7k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
40.7k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
40.7k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
95
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
95
    return;
844
0
    break;
845
7.15k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
7.15k
    printOperand(MI, 1, O); 
848
7.15k
    break;
849
21.9k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
21.9k
    printOperand(MI, 0, O); 
852
21.9k
    break;
853
3.27k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.27k
    printCCOperand(MI, 1, O); 
856
3.27k
    break;
857
1.09k
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
1.09k
    printMemOperand(MI, 0, O, NULL); 
860
1.09k
    return;
861
0
    break;
862
2.74k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.74k
    printCCOperand(MI, 3, O); 
865
2.74k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
1.67k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
1.67k
    printMemOperand(MI, 1, O, NULL); 
874
1.67k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.07k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.07k
    printOperand(MI, 2, O); 
885
1.07k
    SStream_concat0(O, ", ["); 
886
1.07k
    printMemOperand(MI, 0, O, NULL); 
887
1.07k
    SStream_concat0(O, "]"); 
888
1.07k
    return;
889
0
    break;
890
719
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
719
    printCCOperand(MI, 2, O); 
893
719
    break;
894
928
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
928
    printCCOperand(MI, 4, O); 
897
928
    SStream_concat0(O, " "); 
898
928
    printOperand(MI, 1, O); 
899
928
    SStream_concat0(O, ", "); 
900
928
    printOperand(MI, 2, O); 
901
928
    SStream_concat0(O, ", "); 
902
928
    printOperand(MI, 0, O); 
903
928
    return;
904
0
    break;
905
40.7k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
37.5k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
11.9k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
11.9k
    SStream_concat0(O, ", "); 
915
11.9k
    break;
916
17.1k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
17.1k
    return;
919
0
    break;
920
913
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
913
    SStream_concat0(O, " "); 
923
913
    break;
924
1.35k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.35k
    SStream_concat0(O, ",a ");
927
1.35k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.35k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.99k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.99k
    SStream_concat0(O, " %icc, ");
950
1.99k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.99k
    break;
952
233
  case 7:
953
    // BPICCA
954
233
    SStream_concat0(O, ",a %icc, ");
955
233
  Sparc_add_hint(MI, SPARC_HINT_A);
956
233
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
233
    printOperand(MI, 0, O); 
958
233
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.00k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.00k
    SStream_concat0(O, " %xcc, ");
979
1.00k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.00k
    break;
981
234
  case 11:
982
    // BPXCCA
983
234
    SStream_concat0(O, ",a %xcc, ");
984
234
  Sparc_add_hint(MI, SPARC_HINT_A);
985
234
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
234
    printOperand(MI, 0, O); 
987
234
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.70k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.70k
    SStream_concat0(O, "], "); 
1008
1.70k
    break;
1009
998
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
998
    SStream_concat0(O, " %fcc0, ");
1012
998
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
998
    printOperand(MI, 1, O); 
1014
998
    SStream_concat0(O, ", "); 
1015
998
    printOperand(MI, 0, O); 
1016
998
    return;
1017
0
    break;
1018
37.5k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
18.9k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.33k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.33k
    printOperand(MI, 2, O); 
1028
5.33k
    SStream_concat0(O, ", "); 
1029
5.33k
    printOperand(MI, 0, O); 
1030
5.33k
    break;
1031
7.02k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
7.02k
    printOperand(MI, 0, O); 
1034
7.02k
    break;
1035
6.54k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
6.54k
    printOperand(MI, 1, O); 
1038
6.54k
    break;
1039
18.9k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
18.9k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
15.0k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
15.0k
    return;
1049
0
    break;
1050
2.82k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.82k
    SStream_concat0(O, ", "); 
1053
2.82k
    break;
1054
719
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
719
    SStream_concat0(O, " + ");  // qq
1057
719
    printOperand(MI, 1, O); 
1058
719
    return;
1059
0
    break;
1060
259
  case 3:
1061
    // WRYri, WRYrr
1062
259
    SStream_concat0(O, ", %y");
1063
259
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
259
    return;
1065
0
    break;
1066
18.9k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.82k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.08k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.08k
    printOperand(MI, 2, O); 
1076
1.08k
    return;
1077
0
    break;
1078
1.74k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.74k
    printOperand(MI, 0, O); 
1081
1.74k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.82k
  }
1089
2.82k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
63.6k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
63.6k
#ifndef CAPSTONE_DIET
1100
63.6k
  static const char AsmStrs[] = {
1101
63.6k
  /* 0 */ 'f', '1', '0', 0,
1102
63.6k
  /* 4 */ 'f', '2', '0', 0,
1103
63.6k
  /* 8 */ 'f', '3', '0', 0,
1104
63.6k
  /* 12 */ 'f', '4', '0', 0,
1105
63.6k
  /* 16 */ 'f', '5', '0', 0,
1106
63.6k
  /* 20 */ 'f', '6', '0', 0,
1107
63.6k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
63.6k
  /* 29 */ 'f', '0', 0,
1109
63.6k
  /* 32 */ 'g', '0', 0,
1110
63.6k
  /* 35 */ 'i', '0', 0,
1111
63.6k
  /* 38 */ 'l', '0', 0,
1112
63.6k
  /* 41 */ 'o', '0', 0,
1113
63.6k
  /* 44 */ 'f', '1', '1', 0,
1114
63.6k
  /* 48 */ 'f', '2', '1', 0,
1115
63.6k
  /* 52 */ 'f', '3', '1', 0,
1116
63.6k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
63.6k
  /* 61 */ 'f', '1', 0,
1118
63.6k
  /* 64 */ 'g', '1', 0,
1119
63.6k
  /* 67 */ 'i', '1', 0,
1120
63.6k
  /* 70 */ 'l', '1', 0,
1121
63.6k
  /* 73 */ 'o', '1', 0,
1122
63.6k
  /* 76 */ 'f', '1', '2', 0,
1123
63.6k
  /* 80 */ 'f', '2', '2', 0,
1124
63.6k
  /* 84 */ 'f', '3', '2', 0,
1125
63.6k
  /* 88 */ 'f', '4', '2', 0,
1126
63.6k
  /* 92 */ 'f', '5', '2', 0,
1127
63.6k
  /* 96 */ 'f', '6', '2', 0,
1128
63.6k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
63.6k
  /* 105 */ 'f', '2', 0,
1130
63.6k
  /* 108 */ 'g', '2', 0,
1131
63.6k
  /* 111 */ 'i', '2', 0,
1132
63.6k
  /* 114 */ 'l', '2', 0,
1133
63.6k
  /* 117 */ 'o', '2', 0,
1134
63.6k
  /* 120 */ 'f', '1', '3', 0,
1135
63.6k
  /* 124 */ 'f', '2', '3', 0,
1136
63.6k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
63.6k
  /* 133 */ 'f', '3', 0,
1138
63.6k
  /* 136 */ 'g', '3', 0,
1139
63.6k
  /* 139 */ 'i', '3', 0,
1140
63.6k
  /* 142 */ 'l', '3', 0,
1141
63.6k
  /* 145 */ 'o', '3', 0,
1142
63.6k
  /* 148 */ 'f', '1', '4', 0,
1143
63.6k
  /* 152 */ 'f', '2', '4', 0,
1144
63.6k
  /* 156 */ 'f', '3', '4', 0,
1145
63.6k
  /* 160 */ 'f', '4', '4', 0,
1146
63.6k
  /* 164 */ 'f', '5', '4', 0,
1147
63.6k
  /* 168 */ 'f', '4', 0,
1148
63.6k
  /* 171 */ 'g', '4', 0,
1149
63.6k
  /* 174 */ 'i', '4', 0,
1150
63.6k
  /* 177 */ 'l', '4', 0,
1151
63.6k
  /* 180 */ 'o', '4', 0,
1152
63.6k
  /* 183 */ 'f', '1', '5', 0,
1153
63.6k
  /* 187 */ 'f', '2', '5', 0,
1154
63.6k
  /* 191 */ 'f', '5', 0,
1155
63.6k
  /* 194 */ 'g', '5', 0,
1156
63.6k
  /* 197 */ 'i', '5', 0,
1157
63.6k
  /* 200 */ 'l', '5', 0,
1158
63.6k
  /* 203 */ 'o', '5', 0,
1159
63.6k
  /* 206 */ 'f', '1', '6', 0,
1160
63.6k
  /* 210 */ 'f', '2', '6', 0,
1161
63.6k
  /* 214 */ 'f', '3', '6', 0,
1162
63.6k
  /* 218 */ 'f', '4', '6', 0,
1163
63.6k
  /* 222 */ 'f', '5', '6', 0,
1164
63.6k
  /* 226 */ 'f', '6', 0,
1165
63.6k
  /* 229 */ 'g', '6', 0,
1166
63.6k
  /* 232 */ 'l', '6', 0,
1167
63.6k
  /* 235 */ 'f', '1', '7', 0,
1168
63.6k
  /* 239 */ 'f', '2', '7', 0,
1169
63.6k
  /* 243 */ 'f', '7', 0,
1170
63.6k
  /* 246 */ 'g', '7', 0,
1171
63.6k
  /* 249 */ 'i', '7', 0,
1172
63.6k
  /* 252 */ 'l', '7', 0,
1173
63.6k
  /* 255 */ 'o', '7', 0,
1174
63.6k
  /* 258 */ 'f', '1', '8', 0,
1175
63.6k
  /* 262 */ 'f', '2', '8', 0,
1176
63.6k
  /* 266 */ 'f', '3', '8', 0,
1177
63.6k
  /* 270 */ 'f', '4', '8', 0,
1178
63.6k
  /* 274 */ 'f', '5', '8', 0,
1179
63.6k
  /* 278 */ 'f', '8', 0,
1180
63.6k
  /* 281 */ 'f', '1', '9', 0,
1181
63.6k
  /* 285 */ 'f', '2', '9', 0,
1182
63.6k
  /* 289 */ 'f', '9', 0,
1183
63.6k
  /* 292 */ 'i', 'c', 'c', 0,
1184
63.6k
  /* 296 */ 'f', 'p', 0,
1185
63.6k
  /* 299 */ 's', 'p', 0,
1186
63.6k
  /* 302 */ 'y', 0,
1187
63.6k
  };
1188
1189
63.6k
  static const uint16_t RegAsmOffset[] = {
1190
63.6k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
63.6k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
63.6k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
63.6k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
63.6k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
63.6k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
63.6k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
63.6k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
63.6k
    12, 160, 270, 92, 222, 20, 
1199
63.6k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
63.6k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
63.6k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
74.4k
{
1221
370k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
74.4k
  const char *AsmString;
1223
74.4k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
74.4k
  int OpIdx, PrintMethodIdx;
1225
74.4k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
74.4k
  switch (MCInst_getOpcode(MI)) {
1227
37.8k
  default: return NULL;
1228
2.89k
  case SP_BCOND:
1229
2.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
555
      AsmString = "bn $\x01";
1241
555
      break;
1242
555
    }
1243
2.34k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
71
      AsmString = "bne $\x01";
1248
71
      break;
1249
71
    }
1250
2.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
204
      AsmString = "be $\x01";
1255
204
      break;
1256
204
    }
1257
2.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
84
      AsmString = "bg $\x01";
1262
84
      break;
1263
84
    }
1264
1.98k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
204
      AsmString = "ble $\x01";
1269
204
      break;
1270
204
    }
1271
1.77k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
83
      AsmString = "bge $\x01";
1276
83
      break;
1277
83
    }
1278
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
231
      AsmString = "bl $\x01";
1283
231
      break;
1284
231
    }
1285
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
236
      AsmString = "bgu $\x01";
1290
236
      break;
1291
236
    }
1292
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
132
      AsmString = "bleu $\x01";
1297
132
      break;
1298
132
    }
1299
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
36
      AsmString = "bcc $\x01";
1304
36
      break;
1305
36
    }
1306
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
207
      AsmString = "bcs $\x01";
1311
207
      break;
1312
207
    }
1313
853
    if (MCInst_getNumOperands(MI) == 2 &&
1314
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
201
      AsmString = "bpos $\x01";
1318
201
      break;
1319
201
    }
1320
652
    if (MCInst_getNumOperands(MI) == 2 &&
1321
652
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
652
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
208
      AsmString = "bneg $\x01";
1325
208
      break;
1326
208
    }
1327
444
    if (MCInst_getNumOperands(MI) == 2 &&
1328
444
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
444
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
78
      AsmString = "bvc $\x01";
1332
78
      break;
1333
78
    }
1334
366
    if (MCInst_getNumOperands(MI) == 2 &&
1335
366
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
366
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
366
      AsmString = "bvs $\x01";
1339
366
      break;
1340
366
    }
1341
0
    return NULL;
1342
2.25k
  case SP_BCONDA:
1343
2.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
2.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
2.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
176
      AsmString = "ba,a $\x01";
1348
176
      break;
1349
176
    }
1350
2.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
202
      AsmString = "bn,a $\x01";
1355
202
      break;
1356
202
    }
1357
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
87
      AsmString = "bne,a $\x01";
1362
87
      break;
1363
87
    }
1364
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
70
      AsmString = "be,a $\x01";
1369
70
      break;
1370
70
    }
1371
1.72k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
201
      AsmString = "bg,a $\x01";
1376
201
      break;
1377
201
    }
1378
1.52k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
205
      AsmString = "ble,a $\x01";
1383
205
      break;
1384
205
    }
1385
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
201
      AsmString = "bge,a $\x01";
1390
201
      break;
1391
201
    }
1392
1.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
39
      AsmString = "bl,a $\x01";
1397
39
      break;
1398
39
    }
1399
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
80
      AsmString = "bgu,a $\x01";
1404
80
      break;
1405
80
    }
1406
998
    if (MCInst_getNumOperands(MI) == 2 &&
1407
998
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
998
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
206
      AsmString = "bleu,a $\x01";
1411
206
      break;
1412
206
    }
1413
792
    if (MCInst_getNumOperands(MI) == 2 &&
1414
792
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
792
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
53
      AsmString = "bcc,a $\x01";
1418
53
      break;
1419
53
    }
1420
739
    if (MCInst_getNumOperands(MI) == 2 &&
1421
739
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
739
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
136
      AsmString = "bcs,a $\x01";
1425
136
      break;
1426
136
    }
1427
603
    if (MCInst_getNumOperands(MI) == 2 &&
1428
603
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
603
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
196
      AsmString = "bpos,a $\x01";
1432
196
      break;
1433
196
    }
1434
407
    if (MCInst_getNumOperands(MI) == 2 &&
1435
407
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
407
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
294
      AsmString = "bneg,a $\x01";
1439
294
      break;
1440
294
    }
1441
113
    if (MCInst_getNumOperands(MI) == 2 &&
1442
113
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
113
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
38
      AsmString = "bvc,a $\x01";
1446
38
      break;
1447
38
    }
1448
75
    if (MCInst_getNumOperands(MI) == 2 &&
1449
75
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
75
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
75
      AsmString = "bvs,a $\x01";
1453
75
      break;
1454
75
    }
1455
0
    return NULL;
1456
3.45k
  case SP_BPFCCANT:
1457
3.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
3.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
3.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
3.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
3.45k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
68
      AsmString = "fba,a,pn $\x03, $\x01";
1464
68
      break;
1465
68
    }
1466
3.38k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.38k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.38k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
335
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
335
      break;
1474
335
    }
1475
3.05k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.05k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.05k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
380
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
380
      break;
1483
380
    }
1484
2.67k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.67k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.67k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
154
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
154
      break;
1492
154
    }
1493
2.51k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.51k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.51k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
288
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
288
      break;
1501
288
    }
1502
2.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
230
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
230
      break;
1510
230
    }
1511
1.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.99k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
205
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
205
      break;
1519
205
    }
1520
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
1.79k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
208
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
208
      break;
1528
208
    }
1529
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.58k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
241
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
241
      break;
1537
241
    }
1538
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.34k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
446
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
446
      break;
1546
446
    }
1547
899
    if (MCInst_getNumOperands(MI) == 3 &&
1548
899
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
899
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
899
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
899
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
39
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
39
      break;
1555
39
    }
1556
860
    if (MCInst_getNumOperands(MI) == 3 &&
1557
860
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
860
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
860
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
860
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
84
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
84
      break;
1564
84
    }
1565
776
    if (MCInst_getNumOperands(MI) == 3 &&
1566
776
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
776
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
776
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
776
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
82
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
82
      break;
1573
82
    }
1574
694
    if (MCInst_getNumOperands(MI) == 3 &&
1575
694
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
694
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
694
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
694
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
208
      AsmString = "fble,a,pn $\x03, $\x01";
1581
208
      break;
1582
208
    }
1583
486
    if (MCInst_getNumOperands(MI) == 3 &&
1584
486
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
486
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
486
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
486
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
281
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
281
      break;
1591
281
    }
1592
205
    if (MCInst_getNumOperands(MI) == 3 &&
1593
205
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
205
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
205
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
205
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
205
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
205
      break;
1600
205
    }
1601
0
    return NULL;
1602
3.31k
  case SP_BPFCCNT:
1603
3.31k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
3.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
3.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
3.31k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
3.31k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
242
      AsmString = "fba,pn $\x03, $\x01";
1610
242
      break;
1611
242
    }
1612
3.06k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
3.06k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
3.06k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
198
      AsmString = "fbn,pn $\x03, $\x01";
1619
198
      break;
1620
198
    }
1621
2.87k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
2.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
2.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
2.87k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
2.87k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
257
      AsmString = "fbu,pn $\x03, $\x01";
1628
257
      break;
1629
257
    }
1630
2.61k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.61k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.61k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
222
      AsmString = "fbg,pn $\x03, $\x01";
1637
222
      break;
1638
222
    }
1639
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
77
      AsmString = "fbug,pn $\x03, $\x01";
1646
77
      break;
1647
77
    }
1648
2.31k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
2.31k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
2.31k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
86
      AsmString = "fbl,pn $\x03, $\x01";
1655
86
      break;
1656
86
    }
1657
2.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
2.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
2.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
241
      AsmString = "fbul,pn $\x03, $\x01";
1664
241
      break;
1665
241
    }
1666
1.98k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
1.98k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
198
      AsmString = "fblg,pn $\x03, $\x01";
1673
198
      break;
1674
198
    }
1675
1.78k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.78k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.78k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
127
      AsmString = "fbne,pn $\x03, $\x01";
1682
127
      break;
1683
127
    }
1684
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
207
      AsmString = "fbe,pn $\x03, $\x01";
1691
207
      break;
1692
207
    }
1693
1.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
1.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
1.45k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
430
      AsmString = "fbue,pn $\x03, $\x01";
1700
430
      break;
1701
430
    }
1702
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
1.02k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
200
      AsmString = "fbge,pn $\x03, $\x01";
1709
200
      break;
1710
200
    }
1711
825
    if (MCInst_getNumOperands(MI) == 3 &&
1712
825
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
825
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
825
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
825
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
240
      AsmString = "fbuge,pn $\x03, $\x01";
1718
240
      break;
1719
240
    }
1720
585
    if (MCInst_getNumOperands(MI) == 3 &&
1721
585
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
585
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
585
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
585
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
199
      AsmString = "fble,pn $\x03, $\x01";
1727
199
      break;
1728
199
    }
1729
386
    if (MCInst_getNumOperands(MI) == 3 &&
1730
386
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
386
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
386
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
386
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
68
      AsmString = "fbule,pn $\x03, $\x01";
1736
68
      break;
1737
68
    }
1738
318
    if (MCInst_getNumOperands(MI) == 3 &&
1739
318
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
318
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
318
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
318
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
318
      AsmString = "fbo,pn $\x03, $\x01";
1745
318
      break;
1746
318
    }
1747
0
    return NULL;
1748
2.27k
  case SP_BPICCANT:
1749
2.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
61
      AsmString = "ba,a,pn %icc, $\x01";
1754
61
      break;
1755
61
    }
1756
2.21k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
198
      AsmString = "bn,a,pn %icc, $\x01";
1761
198
      break;
1762
198
    }
1763
2.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
139
      AsmString = "bne,a,pn %icc, $\x01";
1768
139
      break;
1769
139
    }
1770
1.87k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
135
      AsmString = "be,a,pn %icc, $\x01";
1775
135
      break;
1776
135
    }
1777
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
141
      AsmString = "bg,a,pn %icc, $\x01";
1782
141
      break;
1783
141
    }
1784
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
79
      AsmString = "ble,a,pn %icc, $\x01";
1789
79
      break;
1790
79
    }
1791
1.52k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
74
      AsmString = "bge,a,pn %icc, $\x01";
1796
74
      break;
1797
74
    }
1798
1.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
210
      AsmString = "bl,a,pn %icc, $\x01";
1803
210
      break;
1804
210
    }
1805
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
35
      AsmString = "bgu,a,pn %icc, $\x01";
1810
35
      break;
1811
35
    }
1812
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
216
      AsmString = "bleu,a,pn %icc, $\x01";
1817
216
      break;
1818
216
    }
1819
989
    if (MCInst_getNumOperands(MI) == 2 &&
1820
989
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
989
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
213
      AsmString = "bcc,a,pn %icc, $\x01";
1824
213
      break;
1825
213
    }
1826
776
    if (MCInst_getNumOperands(MI) == 2 &&
1827
776
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
776
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
161
      AsmString = "bcs,a,pn %icc, $\x01";
1831
161
      break;
1832
161
    }
1833
615
    if (MCInst_getNumOperands(MI) == 2 &&
1834
615
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
615
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
196
      AsmString = "bpos,a,pn %icc, $\x01";
1838
196
      break;
1839
196
    }
1840
419
    if (MCInst_getNumOperands(MI) == 2 &&
1841
419
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
419
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
75
      AsmString = "bneg,a,pn %icc, $\x01";
1845
75
      break;
1846
75
    }
1847
344
    if (MCInst_getNumOperands(MI) == 2 &&
1848
344
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
344
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
68
      AsmString = "bvc,a,pn %icc, $\x01";
1852
68
      break;
1853
68
    }
1854
276
    if (MCInst_getNumOperands(MI) == 2 &&
1855
276
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
276
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
276
      AsmString = "bvs,a,pn %icc, $\x01";
1859
276
      break;
1860
276
    }
1861
0
    return NULL;
1862
2.90k
  case SP_BPICCNT:
1863
2.90k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
81
      AsmString = "ba,pn %icc, $\x01";
1868
81
      break;
1869
81
    }
1870
2.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
2.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
2.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
420
      AsmString = "bn,pn %icc, $\x01";
1875
420
      break;
1876
420
    }
1877
2.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
197
      AsmString = "bne,pn %icc, $\x01";
1882
197
      break;
1883
197
    }
1884
2.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
610
      AsmString = "be,pn %icc, $\x01";
1889
610
      break;
1890
610
    }
1891
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
75
      AsmString = "bg,pn %icc, $\x01";
1896
75
      break;
1897
75
    }
1898
1.52k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
109
      AsmString = "ble,pn %icc, $\x01";
1903
109
      break;
1904
109
    }
1905
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
134
      AsmString = "bge,pn %icc, $\x01";
1910
134
      break;
1911
134
    }
1912
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
74
      AsmString = "bl,pn %icc, $\x01";
1917
74
      break;
1918
74
    }
1919
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
67
      AsmString = "bgu,pn %icc, $\x01";
1924
67
      break;
1925
67
    }
1926
1.14k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
202
      AsmString = "bleu,pn %icc, $\x01";
1931
202
      break;
1932
202
    }
1933
938
    if (MCInst_getNumOperands(MI) == 2 &&
1934
938
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
938
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
27
      AsmString = "bcc,pn %icc, $\x01";
1938
27
      break;
1939
27
    }
1940
911
    if (MCInst_getNumOperands(MI) == 2 &&
1941
911
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
911
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
161
      AsmString = "bcs,pn %icc, $\x01";
1945
161
      break;
1946
161
    }
1947
750
    if (MCInst_getNumOperands(MI) == 2 &&
1948
750
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
750
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
74
      AsmString = "bpos,pn %icc, $\x01";
1952
74
      break;
1953
74
    }
1954
676
    if (MCInst_getNumOperands(MI) == 2 &&
1955
676
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
676
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
196
      AsmString = "bneg,pn %icc, $\x01";
1959
196
      break;
1960
196
    }
1961
480
    if (MCInst_getNumOperands(MI) == 2 &&
1962
480
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
480
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
213
      AsmString = "bvc,pn %icc, $\x01";
1966
213
      break;
1967
213
    }
1968
267
    if (MCInst_getNumOperands(MI) == 2 &&
1969
267
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
267
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
267
      AsmString = "bvs,pn %icc, $\x01";
1973
267
      break;
1974
267
    }
1975
0
    return NULL;
1976
1.79k
  case SP_BPXCCANT:
1977
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
75
      AsmString = "ba,a,pn %xcc, $\x01";
1982
75
      break;
1983
75
    }
1984
1.72k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
75
      AsmString = "bn,a,pn %xcc, $\x01";
1989
75
      break;
1990
75
    }
1991
1.64k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
72
      AsmString = "bne,a,pn %xcc, $\x01";
1996
72
      break;
1997
72
    }
1998
1.57k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
71
      AsmString = "be,a,pn %xcc, $\x01";
2003
71
      break;
2004
71
    }
2005
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
72
      AsmString = "bg,a,pn %xcc, $\x01";
2010
72
      break;
2011
72
    }
2012
1.43k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
305
      AsmString = "ble,a,pn %xcc, $\x01";
2017
305
      break;
2018
305
    }
2019
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
66
      AsmString = "bge,a,pn %xcc, $\x01";
2024
66
      break;
2025
66
    }
2026
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
67
      AsmString = "bl,a,pn %xcc, $\x01";
2031
67
      break;
2032
67
    }
2033
995
    if (MCInst_getNumOperands(MI) == 2 &&
2034
995
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
995
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
79
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
79
      break;
2039
79
    }
2040
916
    if (MCInst_getNumOperands(MI) == 2 &&
2041
916
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
916
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
212
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
212
      break;
2046
212
    }
2047
704
    if (MCInst_getNumOperands(MI) == 2 &&
2048
704
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
704
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
75
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
75
      break;
2053
75
    }
2054
629
    if (MCInst_getNumOperands(MI) == 2 &&
2055
629
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
629
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
207
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
207
      break;
2060
207
    }
2061
422
    if (MCInst_getNumOperands(MI) == 2 &&
2062
422
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
422
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
76
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
76
      break;
2067
76
    }
2068
346
    if (MCInst_getNumOperands(MI) == 2 &&
2069
346
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
346
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
81
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
81
      break;
2074
81
    }
2075
265
    if (MCInst_getNumOperands(MI) == 2 &&
2076
265
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
265
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
147
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
147
      break;
2081
147
    }
2082
118
    if (MCInst_getNumOperands(MI) == 2 &&
2083
118
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
118
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
118
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
118
      break;
2088
118
    }
2089
0
    return NULL;
2090
2.20k
  case SP_BPXCCNT:
2091
2.20k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
69
      AsmString = "ba,pn %xcc, $\x01";
2096
69
      break;
2097
69
    }
2098
2.13k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
181
      AsmString = "bn,pn %xcc, $\x01";
2103
181
      break;
2104
181
    }
2105
1.95k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
67
      AsmString = "bne,pn %xcc, $\x01";
2110
67
      break;
2111
67
    }
2112
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
118
      AsmString = "be,pn %xcc, $\x01";
2117
118
      break;
2118
118
    }
2119
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
414
      AsmString = "bg,pn %xcc, $\x01";
2124
414
      break;
2125
414
    }
2126
1.35k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
85
      AsmString = "ble,pn %xcc, $\x01";
2131
85
      break;
2132
85
    }
2133
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
39
      AsmString = "bge,pn %xcc, $\x01";
2138
39
      break;
2139
39
    }
2140
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
67
      AsmString = "bl,pn %xcc, $\x01";
2145
67
      break;
2146
67
    }
2147
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
174
      AsmString = "bgu,pn %xcc, $\x01";
2152
174
      break;
2153
174
    }
2154
989
    if (MCInst_getNumOperands(MI) == 2 &&
2155
989
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
989
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
98
      AsmString = "bleu,pn %xcc, $\x01";
2159
98
      break;
2160
98
    }
2161
891
    if (MCInst_getNumOperands(MI) == 2 &&
2162
891
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
891
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
209
      AsmString = "bcc,pn %xcc, $\x01";
2166
209
      break;
2167
209
    }
2168
682
    if (MCInst_getNumOperands(MI) == 2 &&
2169
682
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
682
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
201
      AsmString = "bcs,pn %xcc, $\x01";
2173
201
      break;
2174
201
    }
2175
481
    if (MCInst_getNumOperands(MI) == 2 &&
2176
481
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
481
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
195
      AsmString = "bpos,pn %xcc, $\x01";
2180
195
      break;
2181
195
    }
2182
286
    if (MCInst_getNumOperands(MI) == 2 &&
2183
286
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
286
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
43
      AsmString = "bneg,pn %xcc, $\x01";
2187
43
      break;
2188
43
    }
2189
243
    if (MCInst_getNumOperands(MI) == 2 &&
2190
243
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
243
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
197
      AsmString = "bvc,pn %xcc, $\x01";
2194
197
      break;
2195
197
    }
2196
46
    if (MCInst_getNumOperands(MI) == 2 &&
2197
46
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
46
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
46
      AsmString = "bvs,pn %xcc, $\x01";
2201
46
      break;
2202
46
    }
2203
0
    return NULL;
2204
137
  case SP_FMOVD_ICC:
2205
137
    if (MCInst_getNumOperands(MI) == 3 &&
2206
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
137
    if (MCInst_getNumOperands(MI) == 3 &&
2217
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
137
    if (MCInst_getNumOperands(MI) == 3 &&
2228
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
137
    if (MCInst_getNumOperands(MI) == 3 &&
2239
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
137
    if (MCInst_getNumOperands(MI) == 3 &&
2250
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
137
    if (MCInst_getNumOperands(MI) == 3 &&
2261
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
137
    if (MCInst_getNumOperands(MI) == 3 &&
2272
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
137
    if (MCInst_getNumOperands(MI) == 3 &&
2283
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
137
    if (MCInst_getNumOperands(MI) == 3 &&
2294
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
137
    if (MCInst_getNumOperands(MI) == 3 &&
2305
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
137
    if (MCInst_getNumOperands(MI) == 3 &&
2316
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
137
    if (MCInst_getNumOperands(MI) == 3 &&
2327
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
137
    if (MCInst_getNumOperands(MI) == 3 &&
2338
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
137
    if (MCInst_getNumOperands(MI) == 3 &&
2349
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
137
    if (MCInst_getNumOperands(MI) == 3 &&
2360
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
137
    if (MCInst_getNumOperands(MI) == 3 &&
2371
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
137
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
137
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
137
    return NULL;
2382
268
  case SP_FMOVD_XCC:
2383
268
    if (MCInst_getNumOperands(MI) == 3 &&
2384
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
268
    if (MCInst_getNumOperands(MI) == 3 &&
2395
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
268
    if (MCInst_getNumOperands(MI) == 3 &&
2406
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
268
    if (MCInst_getNumOperands(MI) == 3 &&
2417
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
268
    if (MCInst_getNumOperands(MI) == 3 &&
2428
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
268
    if (MCInst_getNumOperands(MI) == 3 &&
2439
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
268
    if (MCInst_getNumOperands(MI) == 3 &&
2450
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
268
    if (MCInst_getNumOperands(MI) == 3 &&
2461
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
268
    if (MCInst_getNumOperands(MI) == 3 &&
2472
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
268
    if (MCInst_getNumOperands(MI) == 3 &&
2483
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
268
    if (MCInst_getNumOperands(MI) == 3 &&
2494
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
268
    if (MCInst_getNumOperands(MI) == 3 &&
2505
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
268
    if (MCInst_getNumOperands(MI) == 3 &&
2516
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
268
    if (MCInst_getNumOperands(MI) == 3 &&
2527
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
268
    if (MCInst_getNumOperands(MI) == 3 &&
2538
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
268
    if (MCInst_getNumOperands(MI) == 3 &&
2549
268
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
268
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
268
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
268
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
268
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
268
    return NULL;
2560
346
  case SP_FMOVQ_ICC:
2561
346
    if (MCInst_getNumOperands(MI) == 3 &&
2562
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
346
    if (MCInst_getNumOperands(MI) == 3 &&
2573
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
346
    if (MCInst_getNumOperands(MI) == 3 &&
2584
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
346
    if (MCInst_getNumOperands(MI) == 3 &&
2595
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
346
    if (MCInst_getNumOperands(MI) == 3 &&
2606
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
346
    if (MCInst_getNumOperands(MI) == 3 &&
2617
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
346
    if (MCInst_getNumOperands(MI) == 3 &&
2628
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
346
    if (MCInst_getNumOperands(MI) == 3 &&
2639
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
346
    if (MCInst_getNumOperands(MI) == 3 &&
2650
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
346
    if (MCInst_getNumOperands(MI) == 3 &&
2661
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
346
    if (MCInst_getNumOperands(MI) == 3 &&
2672
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
346
    if (MCInst_getNumOperands(MI) == 3 &&
2683
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
346
    if (MCInst_getNumOperands(MI) == 3 &&
2694
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
346
    if (MCInst_getNumOperands(MI) == 3 &&
2705
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
346
    if (MCInst_getNumOperands(MI) == 3 &&
2716
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
346
    if (MCInst_getNumOperands(MI) == 3 &&
2727
346
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
346
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
346
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
346
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
346
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
346
    return NULL;
2738
18
  case SP_FMOVQ_XCC:
2739
18
    if (MCInst_getNumOperands(MI) == 3 &&
2740
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
18
    if (MCInst_getNumOperands(MI) == 3 &&
2751
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
18
    if (MCInst_getNumOperands(MI) == 3 &&
2762
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
18
    if (MCInst_getNumOperands(MI) == 3 &&
2773
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
18
    if (MCInst_getNumOperands(MI) == 3 &&
2784
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
18
    if (MCInst_getNumOperands(MI) == 3 &&
2795
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
18
    if (MCInst_getNumOperands(MI) == 3 &&
2806
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
18
    if (MCInst_getNumOperands(MI) == 3 &&
2817
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
18
    if (MCInst_getNumOperands(MI) == 3 &&
2828
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
18
    if (MCInst_getNumOperands(MI) == 3 &&
2839
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
18
    if (MCInst_getNumOperands(MI) == 3 &&
2850
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
18
    if (MCInst_getNumOperands(MI) == 3 &&
2861
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
18
    if (MCInst_getNumOperands(MI) == 3 &&
2872
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
18
    if (MCInst_getNumOperands(MI) == 3 &&
2883
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
18
    if (MCInst_getNumOperands(MI) == 3 &&
2894
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
18
    if (MCInst_getNumOperands(MI) == 3 &&
2905
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
18
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
18
    return NULL;
2916
94
  case SP_FMOVS_ICC:
2917
94
    if (MCInst_getNumOperands(MI) == 3 &&
2918
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
94
    if (MCInst_getNumOperands(MI) == 3 &&
2929
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
94
    if (MCInst_getNumOperands(MI) == 3 &&
2940
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
94
    if (MCInst_getNumOperands(MI) == 3 &&
2951
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
94
    if (MCInst_getNumOperands(MI) == 3 &&
2962
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
94
    if (MCInst_getNumOperands(MI) == 3 &&
2973
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
94
    if (MCInst_getNumOperands(MI) == 3 &&
2984
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
94
    if (MCInst_getNumOperands(MI) == 3 &&
2995
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
94
    if (MCInst_getNumOperands(MI) == 3 &&
3006
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
94
    if (MCInst_getNumOperands(MI) == 3 &&
3017
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
94
    if (MCInst_getNumOperands(MI) == 3 &&
3028
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
94
    if (MCInst_getNumOperands(MI) == 3 &&
3039
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
94
    if (MCInst_getNumOperands(MI) == 3 &&
3050
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
94
    if (MCInst_getNumOperands(MI) == 3 &&
3061
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
94
    if (MCInst_getNumOperands(MI) == 3 &&
3072
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
94
    if (MCInst_getNumOperands(MI) == 3 &&
3083
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
94
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
94
    return NULL;
3094
36
  case SP_FMOVS_XCC:
3095
36
    if (MCInst_getNumOperands(MI) == 3 &&
3096
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
36
    if (MCInst_getNumOperands(MI) == 3 &&
3107
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
36
    if (MCInst_getNumOperands(MI) == 3 &&
3118
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
36
    if (MCInst_getNumOperands(MI) == 3 &&
3129
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
36
    if (MCInst_getNumOperands(MI) == 3 &&
3140
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
36
    if (MCInst_getNumOperands(MI) == 3 &&
3151
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
36
    if (MCInst_getNumOperands(MI) == 3 &&
3162
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
36
    if (MCInst_getNumOperands(MI) == 3 &&
3173
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
36
    if (MCInst_getNumOperands(MI) == 3 &&
3184
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
36
    if (MCInst_getNumOperands(MI) == 3 &&
3195
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
36
    if (MCInst_getNumOperands(MI) == 3 &&
3206
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
36
    if (MCInst_getNumOperands(MI) == 3 &&
3217
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
36
    if (MCInst_getNumOperands(MI) == 3 &&
3228
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
36
    if (MCInst_getNumOperands(MI) == 3 &&
3239
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
36
    if (MCInst_getNumOperands(MI) == 3 &&
3250
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
36
    if (MCInst_getNumOperands(MI) == 3 &&
3261
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
36
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
36
    return NULL;
3272
226
  case SP_MOVICCri:
3273
226
    if (MCInst_getNumOperands(MI) == 3 &&
3274
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
226
    if (MCInst_getNumOperands(MI) == 3 &&
3283
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
226
    if (MCInst_getNumOperands(MI) == 3 &&
3292
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
226
    if (MCInst_getNumOperands(MI) == 3 &&
3301
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
226
    if (MCInst_getNumOperands(MI) == 3 &&
3310
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
226
    if (MCInst_getNumOperands(MI) == 3 &&
3319
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
226
    if (MCInst_getNumOperands(MI) == 3 &&
3328
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
226
    if (MCInst_getNumOperands(MI) == 3 &&
3337
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
226
    if (MCInst_getNumOperands(MI) == 3 &&
3346
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
226
    if (MCInst_getNumOperands(MI) == 3 &&
3355
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
226
    if (MCInst_getNumOperands(MI) == 3 &&
3364
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
226
    if (MCInst_getNumOperands(MI) == 3 &&
3373
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
226
    if (MCInst_getNumOperands(MI) == 3 &&
3382
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
226
    if (MCInst_getNumOperands(MI) == 3 &&
3391
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
226
    if (MCInst_getNumOperands(MI) == 3 &&
3400
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
226
    if (MCInst_getNumOperands(MI) == 3 &&
3409
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
226
    return NULL;
3418
210
  case SP_MOVICCrr:
3419
210
    if (MCInst_getNumOperands(MI) == 3 &&
3420
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
210
    if (MCInst_getNumOperands(MI) == 3 &&
3431
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
210
    if (MCInst_getNumOperands(MI) == 3 &&
3442
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
210
    if (MCInst_getNumOperands(MI) == 3 &&
3453
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
210
    if (MCInst_getNumOperands(MI) == 3 &&
3464
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
210
    if (MCInst_getNumOperands(MI) == 3 &&
3475
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
210
    if (MCInst_getNumOperands(MI) == 3 &&
3486
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
210
    if (MCInst_getNumOperands(MI) == 3 &&
3497
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
210
    if (MCInst_getNumOperands(MI) == 3 &&
3508
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
210
    if (MCInst_getNumOperands(MI) == 3 &&
3519
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
210
    if (MCInst_getNumOperands(MI) == 3 &&
3530
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
210
    if (MCInst_getNumOperands(MI) == 3 &&
3541
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
210
    if (MCInst_getNumOperands(MI) == 3 &&
3552
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
210
    if (MCInst_getNumOperands(MI) == 3 &&
3563
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
210
    if (MCInst_getNumOperands(MI) == 3 &&
3574
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
210
    if (MCInst_getNumOperands(MI) == 3 &&
3585
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
210
    return NULL;
3596
199
  case SP_MOVXCCri:
3597
199
    if (MCInst_getNumOperands(MI) == 3 &&
3598
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
199
    if (MCInst_getNumOperands(MI) == 3 &&
3607
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
199
    if (MCInst_getNumOperands(MI) == 3 &&
3616
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
199
    if (MCInst_getNumOperands(MI) == 3 &&
3625
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
199
    if (MCInst_getNumOperands(MI) == 3 &&
3634
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
199
    if (MCInst_getNumOperands(MI) == 3 &&
3643
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
199
    if (MCInst_getNumOperands(MI) == 3 &&
3652
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
199
    if (MCInst_getNumOperands(MI) == 3 &&
3661
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
199
    if (MCInst_getNumOperands(MI) == 3 &&
3670
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
199
    if (MCInst_getNumOperands(MI) == 3 &&
3679
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
199
    if (MCInst_getNumOperands(MI) == 3 &&
3688
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
199
    if (MCInst_getNumOperands(MI) == 3 &&
3697
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
199
    if (MCInst_getNumOperands(MI) == 3 &&
3706
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
199
    if (MCInst_getNumOperands(MI) == 3 &&
3715
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
199
    if (MCInst_getNumOperands(MI) == 3 &&
3724
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
199
    if (MCInst_getNumOperands(MI) == 3 &&
3733
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
199
    return NULL;
3742
210
  case SP_MOVXCCrr:
3743
210
    if (MCInst_getNumOperands(MI) == 3 &&
3744
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
210
    if (MCInst_getNumOperands(MI) == 3 &&
3755
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
210
    if (MCInst_getNumOperands(MI) == 3 &&
3766
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
210
    if (MCInst_getNumOperands(MI) == 3 &&
3777
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
210
    if (MCInst_getNumOperands(MI) == 3 &&
3788
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
210
    if (MCInst_getNumOperands(MI) == 3 &&
3799
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
210
    if (MCInst_getNumOperands(MI) == 3 &&
3810
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
210
    if (MCInst_getNumOperands(MI) == 3 &&
3821
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
210
    if (MCInst_getNumOperands(MI) == 3 &&
3832
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
210
    if (MCInst_getNumOperands(MI) == 3 &&
3843
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
210
    if (MCInst_getNumOperands(MI) == 3 &&
3854
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
210
    if (MCInst_getNumOperands(MI) == 3 &&
3865
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
210
    if (MCInst_getNumOperands(MI) == 3 &&
3876
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
210
    if (MCInst_getNumOperands(MI) == 3 &&
3887
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
210
    if (MCInst_getNumOperands(MI) == 3 &&
3898
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
210
    if (MCInst_getNumOperands(MI) == 3 &&
3909
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
210
    return NULL;
3920
247
  case SP_ORri:
3921
247
    if (MCInst_getNumOperands(MI) == 3 &&
3922
247
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
247
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
247
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
18
      AsmString = "mov $\x03, $\x01";
3927
18
      break;
3928
18
    }
3929
229
    return NULL;
3930
148
  case SP_ORrr:
3931
148
    if (MCInst_getNumOperands(MI) == 3 &&
3932
148
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
148
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
148
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
148
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
148
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
71
      AsmString = "mov $\x03, $\x01";
3939
71
      break;
3940
71
    }
3941
77
    return NULL;
3942
406
  case SP_RESTORErr:
3943
406
    if (MCInst_getNumOperands(MI) == 3 &&
3944
406
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
406
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
406
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
93
      AsmString = "restore";
3949
93
      break;
3950
93
    }
3951
313
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
5.77k
  case SP_TXCCri:
3971
5.77k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
5.77k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
5.77k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
5.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
5.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
624
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
624
      break;
3979
624
    }
3980
5.15k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
5.15k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
5.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
5.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
5.15k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
5.15k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
5.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
5.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
5.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
503
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
503
      break;
3996
503
    }
3997
4.64k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
4.64k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
4.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
4.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
4.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
4.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
4.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
4.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
4.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
691
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
691
      break;
4013
691
    }
4014
3.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
3.95k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
3.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
3.95k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
3.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
3.95k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
3.95k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
3.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
3.95k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
69
      AsmString = "te %xcc, $\x01 + $\x02";
4029
69
      break;
4030
69
    }
4031
3.88k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
3.88k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
3.88k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
3.88k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
3.88k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
3.88k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
3.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
3.88k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
3.88k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
706
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
706
      break;
4047
706
    }
4048
3.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
3.18k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
3.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
3.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
3.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
3.18k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
3.18k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
3.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
3.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
1.49k
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
1.49k
      break;
4064
1.49k
    }
4065
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.69k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.69k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
148
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
148
      break;
4081
148
    }
4082
1.54k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
1.54k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
1.54k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
1.54k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
1.54k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
1.54k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
1.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
1.54k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
1.54k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
87
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
87
      break;
4098
87
    }
4099
1.45k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
1.45k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
1.45k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
1.45k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
1.45k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
77
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
77
      break;
4115
77
    }
4116
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
1.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
1.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
38
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
38
      break;
4132
38
    }
4133
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.34k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.34k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
460
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
460
      break;
4149
460
    }
4150
880
    if (MCInst_getNumOperands(MI) == 3 &&
4151
880
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
880
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
880
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
880
    if (MCInst_getNumOperands(MI) == 3 &&
4159
880
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
880
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
880
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
880
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
35
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
35
      break;
4166
35
    }
4167
845
    if (MCInst_getNumOperands(MI) == 3 &&
4168
845
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
845
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
845
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
845
    if (MCInst_getNumOperands(MI) == 3 &&
4176
845
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
845
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
845
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
845
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
37
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
37
      break;
4183
37
    }
4184
808
    if (MCInst_getNumOperands(MI) == 3 &&
4185
808
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
808
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
808
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
808
    if (MCInst_getNumOperands(MI) == 3 &&
4193
808
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
808
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
808
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
808
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
189
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
189
      break;
4200
189
    }
4201
619
    if (MCInst_getNumOperands(MI) == 3 &&
4202
619
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
619
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
619
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
619
    if (MCInst_getNumOperands(MI) == 3 &&
4210
619
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
619
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
619
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
619
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
88
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
88
      break;
4217
88
    }
4218
531
    if (MCInst_getNumOperands(MI) == 3 &&
4219
531
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
531
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
531
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
531
    if (MCInst_getNumOperands(MI) == 3 &&
4227
531
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
531
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
531
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
531
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
531
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
531
      break;
4234
531
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
3.28k
  case SP_TXCCrr:
4245
3.28k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
3.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
3.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
112
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
112
      break;
4255
112
    }
4256
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
3.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
3.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
3.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
3.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
34
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
34
      break;
4276
34
    }
4277
3.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
3.13k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
3.13k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
3.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
3.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
3.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
3.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
3.13k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
3.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
3.13k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
3.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
3.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
3.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
350
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
350
      break;
4297
350
    }
4298
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.78k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
78
      AsmString = "te %xcc, $\x01 + $\x02";
4317
78
      break;
4318
78
    }
4319
2.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.71k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
26
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
26
      break;
4339
26
    }
4340
2.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.68k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.68k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.68k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.68k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
76
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
76
      break;
4360
76
    }
4361
2.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.60k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
80
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
80
      break;
4381
80
    }
4382
2.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.52k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.52k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.52k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.52k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
556
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
556
      break;
4402
556
    }
4403
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.97k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
85
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
85
      break;
4423
85
    }
4424
1.88k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.88k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.88k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.88k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.88k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.88k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
18
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
18
      break;
4444
18
    }
4445
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.87k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
458
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
458
      break;
4465
458
    }
4466
1.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.41k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.41k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.41k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.41k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
34
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
34
      break;
4486
34
    }
4487
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
296
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
296
      break;
4507
296
    }
4508
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4509
1.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4519
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
75
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
75
      break;
4528
75
    }
4529
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4530
1.00k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4540
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
196
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
196
      break;
4549
196
    }
4550
811
    if (MCInst_getNumOperands(MI) == 3 &&
4551
811
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
811
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
811
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
811
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
811
    if (MCInst_getNumOperands(MI) == 3 &&
4561
811
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
811
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
811
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
811
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
811
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
811
      break;
4570
811
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
133
  case SP_V9FCMPD:
4583
133
    if (MCInst_getNumOperands(MI) == 3 &&
4584
133
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
133
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
133
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
133
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
133
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
67
      AsmString = "fcmpd $\x02, $\x03";
4591
67
      break;
4592
67
    }
4593
66
    return NULL;
4594
677
  case SP_V9FCMPED:
4595
677
    if (MCInst_getNumOperands(MI) == 3 &&
4596
677
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
677
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
677
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
677
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
677
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
642
      AsmString = "fcmped $\x02, $\x03";
4603
642
      break;
4604
642
    }
4605
35
    return NULL;
4606
519
  case SP_V9FCMPEQ:
4607
519
    if (MCInst_getNumOperands(MI) == 3 &&
4608
519
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
519
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
519
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
519
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
519
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
36
      AsmString = "fcmpeq $\x02, $\x03";
4615
36
      break;
4616
36
    }
4617
483
    return NULL;
4618
980
  case SP_V9FCMPES:
4619
980
    if (MCInst_getNumOperands(MI) == 3 &&
4620
980
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
980
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
980
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
980
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
980
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
911
      AsmString = "fcmpes $\x02, $\x03";
4627
911
      break;
4628
911
    }
4629
69
    return NULL;
4630
161
  case SP_V9FCMPQ:
4631
161
    if (MCInst_getNumOperands(MI) == 3 &&
4632
161
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
161
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
161
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
161
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
161
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
89
      AsmString = "fcmpq $\x02, $\x03";
4639
89
      break;
4640
89
    }
4641
72
    return NULL;
4642
431
  case SP_V9FCMPS:
4643
431
    if (MCInst_getNumOperands(MI) == 3 &&
4644
431
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
431
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
431
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
431
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
431
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
74
      AsmString = "fcmps $\x02, $\x03";
4651
74
      break;
4652
74
    }
4653
357
    return NULL;
4654
69
  case SP_V9FMOVD_FCC:
4655
69
    if (MCInst_getNumOperands(MI) == 4 &&
4656
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
69
    if (MCInst_getNumOperands(MI) == 4 &&
4669
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
69
    if (MCInst_getNumOperands(MI) == 4 &&
4682
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
69
    if (MCInst_getNumOperands(MI) == 4 &&
4695
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
69
    if (MCInst_getNumOperands(MI) == 4 &&
4708
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
69
    if (MCInst_getNumOperands(MI) == 4 &&
4721
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
69
    if (MCInst_getNumOperands(MI) == 4 &&
4734
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
69
    if (MCInst_getNumOperands(MI) == 4 &&
4747
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
69
    if (MCInst_getNumOperands(MI) == 4 &&
4760
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
69
    if (MCInst_getNumOperands(MI) == 4 &&
4773
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
69
    if (MCInst_getNumOperands(MI) == 4 &&
4786
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
69
    if (MCInst_getNumOperands(MI) == 4 &&
4799
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
69
    if (MCInst_getNumOperands(MI) == 4 &&
4812
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
69
    if (MCInst_getNumOperands(MI) == 4 &&
4825
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
69
    if (MCInst_getNumOperands(MI) == 4 &&
4838
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
69
    if (MCInst_getNumOperands(MI) == 4 &&
4851
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
69
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
69
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
69
    return NULL;
4864
104
  case SP_V9FMOVQ_FCC:
4865
104
    if (MCInst_getNumOperands(MI) == 4 &&
4866
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
104
    if (MCInst_getNumOperands(MI) == 4 &&
4879
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
104
    if (MCInst_getNumOperands(MI) == 4 &&
4892
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
104
    if (MCInst_getNumOperands(MI) == 4 &&
4905
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
104
    if (MCInst_getNumOperands(MI) == 4 &&
4918
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
104
    if (MCInst_getNumOperands(MI) == 4 &&
4931
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
104
    if (MCInst_getNumOperands(MI) == 4 &&
4944
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
104
    if (MCInst_getNumOperands(MI) == 4 &&
4957
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
104
    if (MCInst_getNumOperands(MI) == 4 &&
4970
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
104
    if (MCInst_getNumOperands(MI) == 4 &&
4983
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
104
    if (MCInst_getNumOperands(MI) == 4 &&
4996
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
104
    if (MCInst_getNumOperands(MI) == 4 &&
5009
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
104
    if (MCInst_getNumOperands(MI) == 4 &&
5022
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
104
    if (MCInst_getNumOperands(MI) == 4 &&
5035
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
104
    if (MCInst_getNumOperands(MI) == 4 &&
5048
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
104
    if (MCInst_getNumOperands(MI) == 4 &&
5061
104
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
104
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
104
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
104
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
104
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
104
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
104
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
104
    return NULL;
5074
186
  case SP_V9FMOVS_FCC:
5075
186
    if (MCInst_getNumOperands(MI) == 4 &&
5076
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
186
    if (MCInst_getNumOperands(MI) == 4 &&
5089
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
186
    if (MCInst_getNumOperands(MI) == 4 &&
5102
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
186
    if (MCInst_getNumOperands(MI) == 4 &&
5115
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
186
    if (MCInst_getNumOperands(MI) == 4 &&
5128
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
186
    if (MCInst_getNumOperands(MI) == 4 &&
5141
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
186
    if (MCInst_getNumOperands(MI) == 4 &&
5154
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
186
    if (MCInst_getNumOperands(MI) == 4 &&
5167
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
186
    if (MCInst_getNumOperands(MI) == 4 &&
5180
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
186
    if (MCInst_getNumOperands(MI) == 4 &&
5193
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
186
    if (MCInst_getNumOperands(MI) == 4 &&
5206
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
186
    if (MCInst_getNumOperands(MI) == 4 &&
5219
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
186
    if (MCInst_getNumOperands(MI) == 4 &&
5232
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
186
    if (MCInst_getNumOperands(MI) == 4 &&
5245
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
186
    if (MCInst_getNumOperands(MI) == 4 &&
5258
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
186
    if (MCInst_getNumOperands(MI) == 4 &&
5271
186
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
186
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
186
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
186
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
186
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
186
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
186
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
186
    return NULL;
5284
237
  case SP_V9MOVFCCri:
5285
237
    if (MCInst_getNumOperands(MI) == 4 &&
5286
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
237
    if (MCInst_getNumOperands(MI) == 4 &&
5297
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
237
    if (MCInst_getNumOperands(MI) == 4 &&
5308
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
237
    if (MCInst_getNumOperands(MI) == 4 &&
5319
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
237
    if (MCInst_getNumOperands(MI) == 4 &&
5330
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
237
    if (MCInst_getNumOperands(MI) == 4 &&
5341
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
237
    if (MCInst_getNumOperands(MI) == 4 &&
5352
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
237
    if (MCInst_getNumOperands(MI) == 4 &&
5363
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
237
    if (MCInst_getNumOperands(MI) == 4 &&
5374
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
237
    if (MCInst_getNumOperands(MI) == 4 &&
5385
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
237
    if (MCInst_getNumOperands(MI) == 4 &&
5396
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
237
    if (MCInst_getNumOperands(MI) == 4 &&
5407
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
237
    if (MCInst_getNumOperands(MI) == 4 &&
5418
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
237
    if (MCInst_getNumOperands(MI) == 4 &&
5429
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
237
    if (MCInst_getNumOperands(MI) == 4 &&
5440
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
237
    if (MCInst_getNumOperands(MI) == 4 &&
5451
237
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
237
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
237
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
237
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
237
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
237
    return NULL;
5462
332
  case SP_V9MOVFCCrr:
5463
332
    if (MCInst_getNumOperands(MI) == 4 &&
5464
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
332
    if (MCInst_getNumOperands(MI) == 4 &&
5477
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
332
    if (MCInst_getNumOperands(MI) == 4 &&
5490
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
332
    if (MCInst_getNumOperands(MI) == 4 &&
5503
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
332
    if (MCInst_getNumOperands(MI) == 4 &&
5516
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
332
    if (MCInst_getNumOperands(MI) == 4 &&
5529
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
332
    if (MCInst_getNumOperands(MI) == 4 &&
5542
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
332
    if (MCInst_getNumOperands(MI) == 4 &&
5555
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
332
    if (MCInst_getNumOperands(MI) == 4 &&
5568
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
332
    if (MCInst_getNumOperands(MI) == 4 &&
5581
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
332
    if (MCInst_getNumOperands(MI) == 4 &&
5594
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
332
    if (MCInst_getNumOperands(MI) == 4 &&
5607
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
332
    if (MCInst_getNumOperands(MI) == 4 &&
5620
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
332
    if (MCInst_getNumOperands(MI) == 4 &&
5633
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
332
    if (MCInst_getNumOperands(MI) == 4 &&
5646
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
332
    if (MCInst_getNumOperands(MI) == 4 &&
5659
332
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
332
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
332
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
332
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
332
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
332
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
332
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
332
    return NULL;
5672
74.4k
  }
5673
5674
32.1k
  tmp = cs_strdup(AsmString);
5675
32.1k
  AsmMnem = tmp;
5676
201k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
201k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
32.0k
      *AsmOps = '\0';
5679
32.0k
      AsmOps++;
5680
32.0k
      break;
5681
32.0k
    }
5682
201k
  }
5683
32.1k
  SStream_concat0(OS, AsmMnem);
5684
32.1k
  if (*AsmOps) {
5685
32.0k
    SStream_concat0(OS, "\t");
5686
32.0k
    if (strstr(AsmOps, "icc"))
5687
5.18k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
32.0k
    if (strstr(AsmOps, "xcc"))
5689
13.0k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
235k
    for (c = AsmOps; *c; c++) {
5691
203k
      if (*c == '$') {
5692
49.8k
        c += 1;
5693
49.8k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
49.8k
          printOperand(MI, *c - 1, OS);
5701
154k
      } else {
5702
154k
        SStream_concat(OS, "%c", *c);
5703
154k
      }
5704
203k
    }
5705
32.0k
  }
5706
32.1k
  return tmp;
5707
74.4k
}
5708
5709
#endif // PRINT_ALIAS_INSTR