Coverage Report

Created: 2025-07-18 06:43

/src/capstonev5/arch/AArch64/AArch64InstPrinter.c
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Count
Source (jump to first uncovered line)
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//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
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//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an AArch64 MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
16
17
#ifdef CAPSTONE_HAS_ARM64
18
19
#include <capstone/platform.h>
20
#include <stdio.h>
21
#include <stdlib.h>
22
23
#include "AArch64InstPrinter.h"
24
#include "AArch64Disassembler.h"
25
#include "AArch64BaseInfo.h"
26
#include "../../utils.h"
27
#include "../../MCInst.h"
28
#include "../../SStream.h"
29
#include "../../MCRegisterInfo.h"
30
#include "../../MathExtras.h"
31
32
#include "AArch64Mapping.h"
33
#include "AArch64AddressingModes.h"
34
35
#define GET_REGINFO_ENUM
36
#include "AArch64GenRegisterInfo.inc"
37
38
#define GET_INSTRINFO_ENUM
39
#include "AArch64GenInstrInfo.inc"
40
41
#include "AArch64GenSubtargetInfo.inc"
42
43
44
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
45
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
46
static bool printSysAlias(MCInst *MI, SStream *O);
47
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
48
static void printInstruction(MCInst *MI, SStream *O);
49
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
50
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
51
    unsigned PrintMethodIdx, SStream *OS);
52
53
54
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
55
1.01M
{
56
1.01M
#ifndef CAPSTONE_DIET
57
1.01M
  const uint8_t *arr = AArch64_get_op_access(h, id);
58
59
1.01M
  if (arr[index] == CS_AC_IGNORE)
60
0
    return 0;
61
62
1.01M
  return arr[index];
63
#else
64
  return 0;
65
#endif
66
1.01M
}
67
68
static void op_addImm(MCInst *MI, int v)
69
3.00k
{
70
3.00k
  if (MI->csh->detail) {
71
3.00k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
72
3.00k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v;
73
3.00k
    MI->flat_insn->detail->arm64.op_count++;
74
3.00k
  }
75
3.00k
}
76
77
static void set_sme_index(MCInst *MI, bool status)
78
13.6k
{
79
  // Doing SME Index operand
80
13.6k
  MI->csh->doing_SME_Index = status;
81
82
13.6k
  if (MI->csh->detail != CS_OPT_ON)
83
0
    return;
84
85
13.6k
  if (status) {
86
9.62k
    unsigned prevOpNum = MI->flat_insn->detail->arm64.op_count - 1; 
87
9.62k
    unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, prevOpNum));
88
    // Replace previous SME register operand with an OP_SME_INDEX operand
89
9.62k
    MI->flat_insn->detail->arm64.operands[prevOpNum].type = ARM64_OP_SME_INDEX;
90
9.62k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.reg = Reg;
91
9.62k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.base = ARM64_REG_INVALID;
92
9.62k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.disp = 0;
93
9.62k
  }
94
13.6k
}
95
96
static void set_mem_access(MCInst *MI, bool status)
97
347k
{
98
  // If status == false, check if this is meant for SME_index
99
347k
  if(!status && MI->csh->doing_SME_Index) {
100
5.57k
    MI->csh->doing_SME_Index = status;
101
5.57k
    return;
102
5.57k
  }
103
104
  // Doing Memory Operation
105
342k
  MI->csh->doing_mem = status;
106
107
108
342k
  if (MI->csh->detail != CS_OPT_ON)
109
0
    return;
110
111
342k
  if (status) {
112
170k
#ifndef CAPSTONE_DIET
113
170k
    uint8_t access;
114
170k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
115
170k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
116
170k
    MI->ac_idx++;
117
170k
#endif
118
170k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
119
170k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
120
170k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
121
170k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
122
171k
  } else {
123
    // done, create the next operand slot
124
171k
    MI->flat_insn->detail->arm64.op_count++;
125
171k
  }
126
342k
}
127
128
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
129
346k
{
130
  // Check for special encodings and print the canonical alias instead.
131
346k
  unsigned Opcode = MCInst_getOpcode(MI);
132
346k
  int LSB, Width;
133
346k
  char *mnem;
134
135
  // printf(">>> opcode = %u\n", MCInst_getOpcode(MI));
136
137
346k
  if (Opcode == AArch64_SYSxt && printSysAlias(MI, O))
138
1.08k
    return;
139
140
  // SBFM/UBFM should print to a nicer aliased form if possible.
141
345k
  if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri ||
142
345k
      Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) {
143
4.13k
    bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri);
144
4.13k
    bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
145
146
4.13k
    MCOperand *Op0 = MCInst_getOperand(MI, 0);
147
4.13k
    MCOperand *Op1 = MCInst_getOperand(MI, 1);
148
4.13k
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
149
4.13k
    MCOperand *Op3 = MCInst_getOperand(MI, 3);
150
151
4.13k
    if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
152
3.48k
      const char *AsmMnemonic = NULL;
153
154
3.48k
      switch (MCOperand_getImm(Op3)) {
155
587
        default:
156
587
          break;
157
158
1.68k
        case 7:
159
1.68k
          if (IsSigned)
160
1.38k
            AsmMnemonic = "sxtb";
161
298
          else if (!Is64Bit)
162
68
            AsmMnemonic = "uxtb";
163
1.68k
          break;
164
165
427
        case 15:
166
427
          if (IsSigned)
167
320
            AsmMnemonic = "sxth";
168
107
          else if (!Is64Bit)
169
72
            AsmMnemonic = "uxth";
170
427
          break;
171
172
787
        case 31:
173
          // *xtw is only valid for signed 64-bit operations.
174
787
          if (Is64Bit && IsSigned)
175
385
            AsmMnemonic = "sxtw";
176
787
          break;
177
3.48k
      }
178
179
3.48k
      if (AsmMnemonic) {
180
2.23k
        SStream_concat(O, "%s\t%s, %s", AsmMnemonic,
181
2.23k
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
182
2.23k
            getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));
183
184
2.23k
        if (MI->csh->detail) {
185
2.23k
#ifndef CAPSTONE_DIET
186
2.23k
          uint8_t access;
187
2.23k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
188
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
189
2.23k
          MI->ac_idx++;
190
2.23k
#endif
191
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
192
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
193
2.23k
          MI->flat_insn->detail->arm64.op_count++;
194
2.23k
#ifndef CAPSTONE_DIET
195
2.23k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
196
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
197
2.23k
          MI->ac_idx++;
198
2.23k
#endif
199
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
200
2.23k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1));
201
2.23k
          MI->flat_insn->detail->arm64.op_count++;
202
2.23k
        }
203
204
2.23k
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
205
206
2.23k
        return;
207
2.23k
      }
208
3.48k
    }
209
210
    // All immediate shifts are aliases, implemented using the Bitfield
211
    // instruction. In all cases the immediate shift amount shift must be in
212
    // the range 0 to (reg.size -1).
213
1.89k
    if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
214
1.89k
      const char *AsmMnemonic = NULL;
215
1.89k
      int shift = 0;
216
1.89k
      int immr = (int)MCOperand_getImm(Op2);
217
1.89k
      int imms = (int)MCOperand_getImm(Op3);
218
219
1.89k
      if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
220
19
        AsmMnemonic = "lsl";
221
19
        shift = 31 - imms;
222
1.87k
      } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
223
1.87k
          ((imms + 1 == immr))) {
224
26
        AsmMnemonic = "lsl";
225
26
        shift = 63 - imms;
226
1.85k
      } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
227
204
        AsmMnemonic = "lsr";
228
204
        shift = immr;
229
1.64k
      } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
230
10
        AsmMnemonic = "lsr";
231
10
        shift = immr;
232
1.63k
      } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) {
233
76
        AsmMnemonic = "asr";
234
76
        shift = immr;
235
1.56k
      } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) {
236
47
        AsmMnemonic = "asr";
237
47
        shift = immr;
238
47
      }
239
240
1.89k
      if (AsmMnemonic) {
241
382
        SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic,
242
382
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
243
382
            getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
244
245
382
        printInt32Bang(O, shift);
246
247
382
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
248
249
382
        if (MI->csh->detail) {
250
382
#ifndef CAPSTONE_DIET
251
382
          uint8_t access;
252
382
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
253
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
254
382
          MI->ac_idx++;
255
382
#endif
256
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
257
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
258
382
          MI->flat_insn->detail->arm64.op_count++;
259
382
#ifndef CAPSTONE_DIET
260
382
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
261
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
262
382
          MI->ac_idx++;
263
382
#endif
264
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
265
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
266
382
          MI->flat_insn->detail->arm64.op_count++;
267
382
#ifndef CAPSTONE_DIET
268
382
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
269
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
270
382
          MI->ac_idx++;
271
382
#endif
272
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
273
382
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift;
274
382
          MI->flat_insn->detail->arm64.op_count++;
275
382
        }
276
277
382
        return;
278
382
      }
279
1.89k
    }
280
281
    // SBFIZ/UBFIZ aliases
282
1.51k
    if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) {
283
371
      SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"),
284
371
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
285
371
          getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
286
287
371
      printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2)));
288
289
371
      SStream_concat0(O, ", ");
290
291
371
      printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1);
292
293
371
      MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));
294
295
371
      if (MI->csh->detail) {
296
371
#ifndef CAPSTONE_DIET
297
371
        uint8_t access;
298
371
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
299
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
300
371
        MI->ac_idx++;
301
371
#endif
302
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
303
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
304
371
        MI->flat_insn->detail->arm64.op_count++;
305
371
#ifndef CAPSTONE_DIET
306
371
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
307
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
308
371
        MI->ac_idx++;
309
371
#endif
310
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
311
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
312
371
        MI->flat_insn->detail->arm64.op_count++;
313
371
#ifndef CAPSTONE_DIET
314
371
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
315
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
316
371
        MI->ac_idx++;
317
371
#endif
318
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
319
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2);
320
371
        MI->flat_insn->detail->arm64.op_count++;
321
371
#ifndef CAPSTONE_DIET
322
371
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
323
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
324
371
        MI->ac_idx++;
325
371
#endif
326
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
327
371
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1;
328
371
        MI->flat_insn->detail->arm64.op_count++;
329
371
      }
330
331
371
      return;
332
371
    }
333
334
    // Otherwise SBFX/UBFX is the preferred form
335
1.14k
    SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"),
336
1.14k
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
337
1.14k
        getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
338
339
1.14k
    printInt32Bang(O, (int)MCOperand_getImm(Op2));
340
1.14k
    SStream_concat0(O, ", ");
341
1.14k
    printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1);
342
343
1.14k
    MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));
344
345
1.14k
    if (MI->csh->detail) {
346
1.14k
#ifndef CAPSTONE_DIET
347
1.14k
      uint8_t access;
348
1.14k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
349
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
350
1.14k
      MI->ac_idx++;
351
1.14k
#endif
352
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
353
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
354
1.14k
      MI->flat_insn->detail->arm64.op_count++;
355
1.14k
#ifndef CAPSTONE_DIET
356
1.14k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
357
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
358
1.14k
      MI->ac_idx++;
359
1.14k
#endif
360
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
361
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
362
1.14k
      MI->flat_insn->detail->arm64.op_count++;
363
1.14k
#ifndef CAPSTONE_DIET
364
1.14k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
365
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
366
1.14k
      MI->ac_idx++;
367
1.14k
#endif
368
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
369
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2);
370
1.14k
      MI->flat_insn->detail->arm64.op_count++;
371
1.14k
#ifndef CAPSTONE_DIET
372
1.14k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
373
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
374
1.14k
      MI->ac_idx++;
375
1.14k
#endif
376
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
377
1.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1;
378
1.14k
      MI->flat_insn->detail->arm64.op_count++;
379
1.14k
    }
380
381
1.14k
    return;
382
1.51k
  }
383
384
341k
  if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) {
385
1.02k
    MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0
386
1.02k
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
387
1.02k
    int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3));
388
1.02k
    int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4));
389
390
1.02k
    if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) &&
391
1.02k
        (ImmR == 0 || ImmS < ImmR)) {
392
      // BFC takes precedence over its entire range, sligtly differently to BFI.
393
375
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
394
375
      int LSB = (BitWidth - ImmR) % BitWidth;
395
375
      int Width = ImmS + 1;
396
397
375
      SStream_concat(O, "bfc\t%s, ",
398
375
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName));
399
400
375
      printInt32Bang(O, LSB);
401
375
      SStream_concat0(O, ", ");
402
375
      printInt32Bang(O, Width);
403
375
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfc"));
404
405
375
      if (MI->csh->detail) {
406
375
#ifndef CAPSTONE_DIET
407
375
        uint8_t access;
408
375
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
409
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
410
375
        MI->ac_idx++;
411
375
#endif
412
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
413
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
414
375
        MI->flat_insn->detail->arm64.op_count++;
415
416
375
#ifndef CAPSTONE_DIET
417
375
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
418
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
419
375
        MI->ac_idx++;
420
375
#endif
421
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
422
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
423
375
        MI->flat_insn->detail->arm64.op_count++;
424
375
#ifndef CAPSTONE_DIET
425
375
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
426
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
427
375
        MI->ac_idx++;
428
375
#endif
429
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
430
375
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
431
375
        MI->flat_insn->detail->arm64.op_count++;
432
375
      }
433
434
375
      return;
435
652
    } else if (ImmS < ImmR) {
436
      // BFI alias
437
175
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
438
175
      LSB = (BitWidth - ImmR) % BitWidth;
439
175
      Width = ImmS + 1;
440
441
175
      SStream_concat(O, "bfi\t%s, %s, ",
442
175
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
443
175
          getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
444
445
175
      printInt32Bang(O, LSB);
446
175
      SStream_concat0(O, ", ");
447
175
      printInt32Bang(O, Width);
448
449
175
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));
450
451
175
      if (MI->csh->detail) {
452
175
#ifndef CAPSTONE_DIET
453
175
        uint8_t access;
454
175
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
455
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
456
175
        MI->ac_idx++;
457
175
#endif
458
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
459
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
460
175
        MI->flat_insn->detail->arm64.op_count++;
461
175
#ifndef CAPSTONE_DIET
462
175
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
463
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
464
175
        MI->ac_idx++;
465
175
#endif
466
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
467
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
468
175
        MI->flat_insn->detail->arm64.op_count++;
469
175
#ifndef CAPSTONE_DIET
470
175
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
471
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
472
175
        MI->ac_idx++;
473
175
#endif
474
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
475
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
476
175
        MI->flat_insn->detail->arm64.op_count++;
477
175
#ifndef CAPSTONE_DIET
478
175
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
479
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
480
175
        MI->ac_idx++;
481
175
#endif
482
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
483
175
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
484
175
        MI->flat_insn->detail->arm64.op_count++;
485
175
      }
486
487
175
      return;
488
175
    }
489
490
477
    LSB = ImmR;
491
477
    Width = ImmS - ImmR + 1;
492
    // Otherwise BFXIL the preferred form
493
477
    SStream_concat(O, "bfxil\t%s, %s, ",
494
477
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
495
477
        getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
496
497
477
    printInt32Bang(O, LSB);
498
477
    SStream_concat0(O, ", ");
499
477
    printInt32Bang(O, Width);
500
501
477
    MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));
502
503
477
    if (MI->csh->detail) {
504
477
#ifndef CAPSTONE_DIET
505
477
      uint8_t access;
506
477
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
507
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
508
477
      MI->ac_idx++;
509
477
#endif
510
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
511
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
512
477
      MI->flat_insn->detail->arm64.op_count++;
513
477
#ifndef CAPSTONE_DIET
514
477
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
515
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
516
477
      MI->ac_idx++;
517
477
#endif
518
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
519
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
520
477
      MI->flat_insn->detail->arm64.op_count++;
521
477
#ifndef CAPSTONE_DIET
522
477
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
523
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
524
477
      MI->ac_idx++;
525
477
#endif
526
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
527
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
528
477
      MI->flat_insn->detail->arm64.op_count++;
529
477
#ifndef CAPSTONE_DIET
530
477
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
531
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
532
477
      MI->ac_idx++;
533
477
#endif
534
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
535
477
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
536
477
      MI->flat_insn->detail->arm64.op_count++;
537
477
    }
538
539
477
    return;
540
1.02k
  }
541
542
  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
543
  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
544
  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
545
  // that can represent the move is the MOV alias, and the rest get printed
546
  // normally.
547
340k
  if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) &&
548
340k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
549
521
    int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32;
550
521
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
551
521
    uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift;
552
553
521
    if (isMOVZMovAlias(Value, Shift,
554
521
          Opcode == AArch64_MOVZXi ? 64 : 32)) {
555
486
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
556
557
486
      printInt64Bang(O, SignExtend64(Value, RegWidth));
558
559
486
      if (MI->csh->detail) {
560
486
#ifndef CAPSTONE_DIET
561
486
        uint8_t access;
562
486
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
563
486
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
564
486
        MI->ac_idx++;
565
486
#endif
566
486
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
567
486
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
568
486
        MI->flat_insn->detail->arm64.op_count++;
569
570
486
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
571
486
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
572
486
        MI->flat_insn->detail->arm64.op_count++;
573
486
      }
574
575
486
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
576
577
486
      return;
578
486
    }
579
521
  }
580
581
339k
  if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&
582
339k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
583
1.33k
    int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32;
584
1.33k
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
585
1.33k
    uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift);
586
587
1.33k
    if (RegWidth == 32)
588
452
      Value = Value & 0xffffffff;
589
590
1.33k
    if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) {
591
1.15k
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
592
593
1.15k
      printInt64Bang(O, SignExtend64(Value, RegWidth));
594
595
1.15k
      if (MI->csh->detail) {
596
1.15k
#ifndef CAPSTONE_DIET
597
1.15k
        uint8_t access;
598
1.15k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
599
1.15k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
600
1.15k
        MI->ac_idx++;
601
1.15k
#endif
602
1.15k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
603
1.15k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
604
1.15k
        MI->flat_insn->detail->arm64.op_count++;
605
606
1.15k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
607
1.15k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
608
1.15k
        MI->flat_insn->detail->arm64.op_count++;
609
1.15k
      }
610
611
1.15k
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
612
613
1.15k
      return;
614
1.15k
    }
615
1.33k
  }
616
617
338k
  if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) &&
618
338k
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR ||
619
1.29k
       MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) &&
620
338k
      MCOperand_isImm(MCInst_getOperand(MI, 2))) {
621
530
    int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32;
622
530
    uint64_t Value = AArch64_AM_decodeLogicalImmediate(
623
530
        MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth);
624
530
    SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
625
626
530
    printInt64Bang(O, SignExtend64(Value, RegWidth));
627
628
530
    if (MI->csh->detail) {
629
530
#ifndef CAPSTONE_DIET
630
530
      uint8_t access;
631
530
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
632
530
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
633
530
      MI->ac_idx++;
634
530
#endif
635
530
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
636
530
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
637
530
      MI->flat_insn->detail->arm64.op_count++;
638
639
530
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
640
530
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
641
530
      MI->flat_insn->detail->arm64.op_count++;
642
530
    }
643
644
530
    MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
645
646
530
    return;
647
530
  }
648
649
  // Instruction TSB is specified as a one operand instruction, but 'csync' is
650
  // not encoded, so for printing it is treated as a special case here:
651
338k
  if (Opcode == AArch64_TSB) {
652
209
    SStream_concat0(O, "tsb\tcsync");
653
209
    MCInst_setOpcodePub(MI, AArch64_map_insn("tsb"));
654
209
    return;
655
209
  }
656
657
337k
  MI->MRI = Info;
658
659
337k
  mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info);
660
337k
  if (mnem) {
661
44.4k
    MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
662
44.4k
    cs_mem_free(mnem);
663
664
44.4k
    switch(MCInst_getOpcode(MI)) {
665
27.3k
      default: break;
666
27.3k
      case AArch64_LD1i8_POST:
667
532
        arm64_op_addImm(MI, 1);
668
532
        break;
669
148
      case AArch64_LD1i16_POST:
670
148
        arm64_op_addImm(MI, 2);
671
148
        break;
672
983
      case AArch64_LD1i32_POST:
673
983
        arm64_op_addImm(MI, 4);
674
983
        break;
675
70
      case AArch64_LD1Onev1d_POST:
676
296
      case AArch64_LD1Onev2s_POST:
677
397
      case AArch64_LD1Onev4h_POST:
678
594
      case AArch64_LD1Onev8b_POST:
679
1.06k
      case AArch64_LD1i64_POST:
680
1.06k
        arm64_op_addImm(MI, 8);
681
1.06k
        break;
682
38
      case AArch64_LD1Onev16b_POST:
683
123
      case AArch64_LD1Onev2d_POST:
684
244
      case AArch64_LD1Onev4s_POST:
685
264
      case AArch64_LD1Onev8h_POST:
686
333
      case AArch64_LD1Twov1d_POST:
687
353
      case AArch64_LD1Twov2s_POST:
688
636
      case AArch64_LD1Twov4h_POST:
689
1.17k
      case AArch64_LD1Twov8b_POST:
690
1.17k
        arm64_op_addImm(MI, 16);
691
1.17k
        break;
692
177
      case AArch64_LD1Threev1d_POST:
693
481
      case AArch64_LD1Threev2s_POST:
694
1.32k
      case AArch64_LD1Threev4h_POST:
695
1.80k
      case AArch64_LD1Threev8b_POST:
696
1.80k
        arm64_op_addImm(MI, 24);
697
1.80k
        break;
698
291
      case AArch64_LD1Fourv1d_POST:
699
377
      case AArch64_LD1Fourv2s_POST:
700
1.03k
      case AArch64_LD1Fourv4h_POST:
701
1.08k
      case AArch64_LD1Fourv8b_POST:
702
1.12k
      case AArch64_LD1Twov16b_POST:
703
1.21k
      case AArch64_LD1Twov2d_POST:
704
1.29k
      case AArch64_LD1Twov4s_POST:
705
1.32k
      case AArch64_LD1Twov8h_POST:
706
1.32k
        arm64_op_addImm(MI, 32);
707
1.32k
        break;
708
201
      case AArch64_LD1Threev16b_POST:
709
473
      case AArch64_LD1Threev2d_POST:
710
1.71k
      case AArch64_LD1Threev4s_POST:
711
1.97k
      case AArch64_LD1Threev8h_POST:
712
1.97k
         arm64_op_addImm(MI, 48);
713
1.97k
         break;
714
184
      case AArch64_LD1Fourv16b_POST:
715
268
      case AArch64_LD1Fourv2d_POST:
716
446
      case AArch64_LD1Fourv4s_POST:
717
1.66k
      case AArch64_LD1Fourv8h_POST:
718
1.66k
        arm64_op_addImm(MI, 64);
719
1.66k
        break;
720
34
      case AArch64_UMOVvi64:
721
34
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
722
34
        break;
723
18
      case AArch64_UMOVvi32:
724
18
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
725
18
        break;
726
74
      case AArch64_INSvi8gpr:
727
128
      case AArch64_DUP_ZI_B:
728
176
      case AArch64_CPY_ZPmI_B:
729
314
      case AArch64_CPY_ZPzI_B:
730
348
      case AArch64_CPY_ZPmV_B:
731
569
      case AArch64_CPY_ZPmR_B:
732
587
      case AArch64_DUP_ZR_B:
733
587
        if (MI->csh->detail) {
734
587
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
735
587
        }
736
587
        break;
737
21
      case AArch64_INSvi16gpr:
738
41
      case AArch64_DUP_ZI_H:
739
71
      case AArch64_CPY_ZPmI_H:
740
232
      case AArch64_CPY_ZPzI_H:
741
443
      case AArch64_CPY_ZPmV_H:
742
479
      case AArch64_CPY_ZPmR_H:
743
741
      case AArch64_DUP_ZR_H:
744
778
      case AArch64_FCPY_ZPmI_H:
745
1.12k
      case AArch64_FDUP_ZI_H:
746
1.12k
        if (MI->csh->detail) {
747
1.12k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
748
1.12k
        }
749
1.12k
        break;
750
41
      case AArch64_INSvi32gpr:
751
53
      case AArch64_DUP_ZI_S:
752
126
      case AArch64_CPY_ZPmI_S:
753
441
      case AArch64_CPY_ZPzI_S:
754
452
      case AArch64_CPY_ZPmV_S:
755
605
      case AArch64_CPY_ZPmR_S:
756
654
      case AArch64_DUP_ZR_S:
757
697
      case AArch64_FCPY_ZPmI_S:
758
731
      case AArch64_FDUP_ZI_S:
759
731
        if (MI->csh->detail) {
760
731
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
761
731
        }
762
731
        break;
763
30
      case AArch64_INSvi64gpr:
764
69
      case AArch64_DUP_ZI_D:
765
160
      case AArch64_CPY_ZPmI_D:
766
470
      case AArch64_CPY_ZPzI_D:
767
481
      case AArch64_CPY_ZPmV_D:
768
700
      case AArch64_CPY_ZPmR_D:
769
836
      case AArch64_DUP_ZR_D:
770
970
      case AArch64_FCPY_ZPmI_D:
771
1.07k
      case AArch64_FDUP_ZI_D:
772
1.07k
        if (MI->csh->detail) {
773
1.07k
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
774
1.07k
        }
775
1.07k
        break;
776
39
      case AArch64_INSvi8lane:
777
77
      case AArch64_ORR_PPzPP:
778
622
      case AArch64_ORRS_PPzPP:
779
622
        if (MI->csh->detail) {
780
622
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
781
622
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
782
622
        }
783
622
        break;
784
146
      case AArch64_INSvi16lane:
785
146
        if (MI->csh->detail) {
786
146
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
787
146
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
788
146
        }
789
146
         break;
790
78
      case AArch64_INSvi32lane:
791
78
        if (MI->csh->detail) {
792
78
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
793
78
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
794
78
        }
795
78
        break;
796
10
      case AArch64_INSvi64lane:
797
44
      case AArch64_ORR_ZZZ:
798
44
        if (MI->csh->detail) {
799
44
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
800
44
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
801
44
        }
802
44
        break;
803
154
      case AArch64_ORRv16i8:
804
226
      case AArch64_NOTv16i8:
805
226
        if (MI->csh->detail) {
806
226
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_16B;
807
226
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_16B;
808
226
        }
809
226
        break;
810
25
      case AArch64_ORRv8i8:
811
158
      case AArch64_NOTv8i8:
812
158
        if (MI->csh->detail) {
813
158
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_8B;
814
158
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_8B;
815
158
        }
816
158
        break;
817
20
      case AArch64_AND_PPzPP:
818
43
      case AArch64_ANDS_PPzPP:
819
53
      case AArch64_EOR_PPzPP:
820
72
      case AArch64_EORS_PPzPP:
821
583
      case AArch64_SEL_PPPP:
822
621
      case AArch64_SEL_ZPZZ_B:
823
621
        if (MI->csh->detail) {
824
621
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
825
621
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1B;
826
621
        }
827
621
        break;
828
31
      case AArch64_SEL_ZPZZ_D:
829
31
        if (MI->csh->detail) {
830
31
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
831
31
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1D;
832
31
        }
833
31
        break;
834
191
      case AArch64_SEL_ZPZZ_H:
835
191
        if (MI->csh->detail) {
836
191
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
837
191
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1H;
838
191
        }
839
191
        break;
840
49
      case AArch64_SEL_ZPZZ_S:
841
49
        if (MI->csh->detail) {
842
49
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
843
49
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1S;
844
49
        }
845
49
        break;
846
50
      case AArch64_DUP_ZZI_B:
847
50
        if (MI->csh->detail) {
848
50
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
849
50
          if (MI->flat_insn->detail->arm64.op_count == 1) {
850
0
            arm64_op_addReg(MI, ARM64_REG_B0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
851
50
          } else {
852
50
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
853
50
          }
854
50
        }
855
50
        break;
856
313
      case AArch64_DUP_ZZI_D:
857
313
        if (MI->csh->detail) {
858
313
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
859
313
          if (MI->flat_insn->detail->arm64.op_count == 1) {
860
0
            arm64_op_addReg(MI, ARM64_REG_D0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
861
313
          } else {
862
313
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
863
313
          }
864
313
        }
865
313
        break;
866
99
      case AArch64_DUP_ZZI_H:
867
99
        if (MI->csh->detail) {
868
99
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
869
99
          if (MI->flat_insn->detail->arm64.op_count == 1) {
870
0
            arm64_op_addReg(MI, ARM64_REG_H0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
871
99
          } else {
872
99
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
873
99
          }
874
99
        }
875
99
        break;
876
68
      case AArch64_DUP_ZZI_Q:
877
68
        if (MI->csh->detail) {
878
68
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1Q;
879
68
          if (MI->flat_insn->detail->arm64.op_count == 1) {
880
0
            arm64_op_addReg(MI, ARM64_REG_Q0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
881
68
          } else {
882
68
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1Q;
883
68
          }
884
68
         }
885
68
         break;
886
106
      case AArch64_DUP_ZZI_S:
887
106
        if (MI->csh->detail) {
888
106
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
889
106
          if (MI->flat_insn->detail->arm64.op_count == 1) {
890
0
            arm64_op_addReg(MI, ARM64_REG_S0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
891
106
          } else {
892
106
             MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
893
106
          }
894
106
        }
895
106
        break;
896
      // Hacky detail filling of SMSTART and SMSTOP alias'
897
34
      case AArch64_MSRpstatesvcrImm1:{
898
34
        if(MI->csh->detail){
899
34
          MI->flat_insn->detail->arm64.op_count = 2;
900
34
#ifndef CAPSTONE_DIET
901
34
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
902
34
          MI->ac_idx++;
903
34
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
904
34
          MI->ac_idx++;
905
34
#endif
906
34
          MI->flat_insn->detail->arm64.operands[0].type = ARM64_OP_SVCR;
907
34
          MI->flat_insn->detail->arm64.operands[0].sys = (unsigned)ARM64_SYSREG_SVCR;
908
34
          MI->flat_insn->detail->arm64.operands[0].svcr = lookupSVCRByEncoding(MCOperand_getImm(MCInst_getOperand(MI, 0)))->Encoding;
909
34
          MI->flat_insn->detail->arm64.operands[1].type = ARM64_OP_IMM;
910
34
          MI->flat_insn->detail->arm64.operands[1].imm = MCOperand_getImm(MCInst_getOperand(MI, 1));
911
34
        }
912
34
        break;
913
583
      }
914
44.4k
    }
915
293k
  } else {
916
293k
    printInstruction(MI, O);
917
293k
  }
918
337k
}
919
920
static bool printSysAlias(MCInst *MI, SStream *O)
921
4.46k
{
922
  // unsigned Opcode = MCInst_getOpcode(MI);
923
  //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!");
924
925
4.46k
  const char *Ins;
926
4.46k
  uint16_t Encoding;
927
4.46k
  bool NeedsReg;
928
4.46k
  char Name[64];
929
4.46k
  MCOperand *Op1 = MCInst_getOperand(MI, 0);
930
4.46k
  MCOperand *Cn = MCInst_getOperand(MI, 1);
931
4.46k
  MCOperand *Cm = MCInst_getOperand(MI, 2);
932
4.46k
  MCOperand *Op2 = MCInst_getOperand(MI, 3);
933
934
4.46k
  unsigned Op1Val = (unsigned)MCOperand_getImm(Op1);
935
4.46k
  unsigned CnVal = (unsigned)MCOperand_getImm(Cn);
936
4.46k
  unsigned CmVal = (unsigned)MCOperand_getImm(Cm);
937
4.46k
  unsigned Op2Val = (unsigned)MCOperand_getImm(Op2);
938
939
4.46k
  Encoding = Op2Val;
940
4.46k
  Encoding |= CmVal << 3;
941
4.46k
  Encoding |= CnVal << 7;
942
4.46k
  Encoding |= Op1Val << 11;
943
944
4.46k
  if (CnVal == 7) {
945
3.44k
    switch (CmVal) {
946
345
      default:
947
345
        return false;
948
949
      // IC aliases
950
753
      case 1: case 5: {
951
753
        const IC *IC = lookupICByEncoding(Encoding);
952
        // if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
953
753
        if (!IC)
954
646
          return false;
955
956
107
        NeedsReg = IC->NeedsReg;
957
107
        Ins = "ic";
958
107
        strncpy(Name, IC->Name, sizeof(Name) - 1);
959
107
      }
960
0
      break;
961
962
      // DC aliases
963
1.57k
      case 4: case 6: case 10: case 11: case 12: case 14: {
964
1.57k
        const DC *DC = lookupDCByEncoding(Encoding);
965
        // if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
966
1.57k
        if (!DC)
967
1.44k
          return false;
968
969
132
        NeedsReg = true;
970
132
        Ins = "dc";
971
132
        strncpy(Name, DC->Name, sizeof(Name) - 1);
972
132
      }
973
0
      break;
974
975
      // AT aliases
976
773
      case 8: case 9: {
977
773
        const AT *AT = lookupATByEncoding(Encoding);
978
        // if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
979
773
        if (!AT)
980
151
          return false;
981
982
622
        NeedsReg = true;
983
622
        Ins = "at";
984
622
        strncpy(Name, AT->Name, sizeof(Name) - 1);
985
622
      }
986
0
      break;
987
3.44k
    }
988
3.44k
  } else if (CnVal == 8) {
989
    // TLBI aliases
990
325
    const TLBI *TLBI = lookupTLBIByEncoding(Encoding);
991
    // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
992
325
    if (!TLBI)
993
98
      return false;
994
995
227
    NeedsReg = TLBI->NeedsReg;
996
227
    Ins = "tlbi";
997
227
    strncpy(Name, TLBI->Name, sizeof(Name) - 1);
998
227
  } else
999
691
    return false;
1000
1001
1.08k
  SStream_concat(O, "%s\t%s", Ins, Name);
1002
1003
1.08k
  if (NeedsReg) {
1004
956
    SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName));
1005
956
  }
1006
1007
1.08k
  MCInst_setOpcodePub(MI, AArch64_map_insn(Ins));
1008
1009
1.08k
  if (MI->csh->detail) {
1010
#if 0
1011
#ifndef CAPSTONE_DIET
1012
    uint8_t access;
1013
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1014
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1015
    MI->ac_idx++;
1016
#endif
1017
#endif
1018
1.08k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
1019
1.08k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = AArch64_map_sys_op(Name);
1020
1.08k
    MI->flat_insn->detail->arm64.op_count++;
1021
1022
1.08k
    if (NeedsReg) {
1023
956
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1024
956
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4));
1025
956
      MI->flat_insn->detail->arm64.op_count++;
1026
956
    }
1027
1.08k
  }
1028
1029
1.08k
  return true;
1030
4.46k
}
1031
1032
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
1033
479k
{
1034
479k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1035
1036
479k
  if (MCOperand_isReg(Op)) {
1037
409k
    unsigned Reg = MCOperand_getReg(Op);
1038
1039
409k
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1040
1041
409k
    if (MI->csh->detail) {
1042
409k
      if (MI->csh->doing_mem) {
1043
188k
        if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
1044
169k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
1045
169k
        }
1046
19.1k
        else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) {
1047
19.1k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
1048
19.1k
        }
1049
220k
      } else if (MI->csh->doing_SME_Index) {
1050
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1051
9.62k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.base = Reg;
1052
210k
      } else {
1053
210k
#ifndef CAPSTONE_DIET
1054
210k
        uint8_t access;
1055
1056
210k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1057
210k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1058
210k
        MI->ac_idx++;
1059
210k
#endif
1060
210k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1061
210k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1062
210k
        MI->flat_insn->detail->arm64.op_count++;
1063
210k
      }
1064
409k
    }
1065
409k
  } else if (MCOperand_isImm(Op)) {
1066
70.4k
    int64_t imm = MCOperand_getImm(Op);
1067
1068
70.4k
    if (MI->Opcode == AArch64_ADR) {
1069
3.66k
      imm += MI->address;
1070
3.66k
      printUInt64Bang(O, imm);
1071
66.7k
    } else {
1072
66.7k
      if (MI->csh->doing_mem) {
1073
16.8k
        if (MI->csh->imm_unsigned) {
1074
0
          printUInt64Bang(O, imm);
1075
16.8k
        } else {
1076
16.8k
          printInt64Bang(O, imm);
1077
16.8k
        }
1078
16.8k
      } else
1079
49.9k
        printUInt64Bang(O, imm);
1080
66.7k
    }
1081
1082
70.4k
    if (MI->csh->detail) {
1083
70.4k
      if (MI->csh->doing_mem) {
1084
16.8k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
1085
53.5k
      } else if (MI->csh->doing_SME_Index) {
1086
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1087
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = (int32_t)imm; 
1088
53.5k
      } else {
1089
53.5k
#ifndef CAPSTONE_DIET
1090
53.5k
        uint8_t access;
1091
1092
53.5k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1093
53.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1094
53.5k
#endif
1095
53.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1096
53.5k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
1097
53.5k
        MI->flat_insn->detail->arm64.op_count++;
1098
53.5k
      }
1099
70.4k
    }
1100
70.4k
  }
1101
479k
}
1102
1103
static void printImm(MCInst *MI, unsigned OpNum, SStream *O)
1104
6.68k
{
1105
6.68k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1106
6.68k
  printUInt64Bang(O, MCOperand_getImm(Op));
1107
1108
6.68k
  if (MI->csh->detail) {
1109
6.68k
#ifndef CAPSTONE_DIET
1110
6.68k
    uint8_t access;
1111
6.68k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1112
6.68k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1113
6.68k
    MI->ac_idx++;
1114
6.68k
#endif
1115
6.68k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1116
6.68k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1117
6.68k
    MI->flat_insn->detail->arm64.op_count++;
1118
6.68k
  }
1119
6.68k
}
1120
1121
static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O)
1122
104
{
1123
104
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1124
104
  printUInt64Bang(O, MCOperand_getImm(Op));
1125
1126
104
  if (MI->csh->detail) {
1127
104
#ifndef CAPSTONE_DIET
1128
104
    uint8_t access;
1129
104
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1130
104
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1131
104
    MI->ac_idx++;
1132
104
#endif
1133
104
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1134
104
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1135
104
    MI->flat_insn->detail->arm64.op_count++;
1136
104
  }
1137
104
}
1138
1139
1.22k
static void printSImm(MCInst *MI, unsigned OpNo, SStream *O, int Size) {
1140
1.22k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1141
1.22k
  if (Size == 8)
1142
626
  printInt64Bang(O, (signed char) MCOperand_getImm(Op));
1143
594
  else if (Size == 16)
1144
594
  printInt64Bang(O, (signed short) MCOperand_getImm(Op));
1145
0
  else
1146
0
    printInt64Bang(O, MCOperand_getImm(Op));
1147
1148
1.22k
  if (MI->csh->detail) {
1149
1.22k
#ifndef CAPSTONE_DIET
1150
1.22k
    uint8_t access;
1151
1.22k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1152
1.22k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1153
1.22k
    MI->ac_idx++;
1154
1.22k
#endif
1155
1.22k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1156
1.22k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1157
1.22k
    MI->flat_insn->detail->arm64.op_count++;
1158
1.22k
  }
1159
1.22k
}
1160
1161
static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O,
1162
    unsigned Imm)
1163
37.2k
{
1164
37.2k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1165
1166
37.2k
  if (MCOperand_isReg(Op)) {
1167
37.2k
    unsigned Reg = MCOperand_getReg(Op);
1168
37.2k
    if (Reg == AArch64_XZR) {
1169
0
      printInt32Bang(O, Imm);
1170
1171
0
      if (MI->csh->detail) {
1172
0
#ifndef CAPSTONE_DIET
1173
0
        uint8_t access;
1174
1175
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1176
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1177
0
        MI->ac_idx++;
1178
0
#endif
1179
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1180
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
1181
0
        MI->flat_insn->detail->arm64.op_count++;
1182
0
      }
1183
37.2k
    } else {
1184
37.2k
      SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1185
1186
37.2k
      if (MI->csh->detail) {
1187
37.2k
#ifndef CAPSTONE_DIET
1188
37.2k
        uint8_t access;
1189
1190
37.2k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1191
37.2k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1192
37.2k
        MI->ac_idx++;
1193
37.2k
#endif
1194
37.2k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1195
37.2k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1196
37.2k
        MI->flat_insn->detail->arm64.op_count++;
1197
37.2k
      }
1198
37.2k
    }
1199
37.2k
  }
1200
  //llvm_unreachable("unknown operand kind in printPostIncOperand64");
1201
37.2k
}
1202
1203
static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1204
56.5k
{
1205
56.5k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1206
  //assert(Op.isReg() && "Non-register vreg operand!");
1207
56.5k
  unsigned Reg = MCOperand_getReg(Op);
1208
1209
56.5k
  SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
1210
1211
56.5k
  if (MI->csh->detail) {
1212
56.5k
#ifndef CAPSTONE_DIET
1213
56.5k
    uint8_t access;
1214
56.5k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1215
56.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1216
56.5k
    MI->ac_idx++;
1217
56.5k
#endif
1218
56.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1219
56.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
1220
56.5k
    MI->flat_insn->detail->arm64.op_count++;
1221
56.5k
  }
1222
56.5k
}
1223
1224
static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O)
1225
7.10k
{
1226
7.10k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1227
  //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1228
7.10k
  SStream_concat(O, "c%u", MCOperand_getImm(Op));
1229
1230
7.10k
  if (MI->csh->detail) {
1231
7.10k
#ifndef CAPSTONE_DIET
1232
7.10k
    uint8_t access;
1233
1234
7.10k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1235
7.10k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1236
7.10k
    MI->ac_idx++;
1237
7.10k
#endif
1238
7.10k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
1239
7.10k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1240
7.10k
    MI->flat_insn->detail->arm64.op_count++;
1241
7.10k
  }
1242
7.10k
}
1243
1244
static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
1245
4.44k
{
1246
4.44k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1247
4.44k
  if (MCOperand_isImm(MO)) {
1248
4.44k
    unsigned Val = (MCOperand_getImm(MO) & 0xfff);
1249
    //assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1250
4.44k
    unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)));
1251
1252
4.44k
    printInt32Bang(O, Val);
1253
1254
4.44k
    if (MI->csh->detail) {
1255
4.44k
#ifndef CAPSTONE_DIET
1256
4.44k
      uint8_t access;
1257
1258
4.44k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1259
4.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1260
4.44k
      MI->ac_idx++;
1261
4.44k
#endif
1262
4.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1263
4.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1264
4.44k
      MI->flat_insn->detail->arm64.op_count++;
1265
4.44k
    }
1266
1267
4.44k
    if (Shift != 0)
1268
2.49k
      printShifter(MI, OpNum + 1, O);
1269
4.44k
  }
1270
4.44k
}
1271
1272
static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
1273
4.57k
{
1274
4.57k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1275
1276
4.57k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 32);
1277
4.57k
  printUInt32Bang(O, (int)Val);
1278
1279
4.57k
  if (MI->csh->detail) {
1280
4.57k
#ifndef CAPSTONE_DIET
1281
4.57k
    uint8_t access;
1282
1283
4.57k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1284
4.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1285
4.57k
    MI->ac_idx++;
1286
4.57k
#endif
1287
4.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1288
4.57k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1289
4.57k
    MI->flat_insn->detail->arm64.op_count++;
1290
4.57k
  }
1291
4.57k
}
1292
1293
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
1294
2.79k
{
1295
2.79k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1296
2.79k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
1297
1298
2.79k
  switch(MI->flat_insn->id) {
1299
1.24k
    default:
1300
1.24k
      printInt64Bang(O, Val);
1301
1.24k
      break;
1302
1303
338
    case ARM64_INS_ORR:
1304
828
    case ARM64_INS_AND:
1305
1.55k
    case ARM64_INS_EOR:
1306
1.55k
    case ARM64_INS_TST:
1307
      // do not print number in negative form
1308
1.55k
      if (Val >= 0 && Val <= HEX_THRESHOLD)
1309
19
        SStream_concat(O, "#%u", (int)Val);
1310
1.53k
      else
1311
1.53k
        SStream_concat(O, "#0x%"PRIx64, Val);
1312
1.55k
      break;
1313
2.79k
  }
1314
1315
2.79k
  if (MI->csh->detail) {
1316
2.79k
#ifndef CAPSTONE_DIET
1317
2.79k
    uint8_t access;
1318
1319
2.79k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1320
2.79k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1321
2.79k
    MI->ac_idx++;
1322
2.79k
#endif
1323
2.79k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1324
2.79k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val;
1325
2.79k
    MI->flat_insn->detail->arm64.op_count++;
1326
2.79k
  }
1327
2.79k
}
1328
1329
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
1330
15.1k
{
1331
15.1k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1332
1333
  // LSL #0 should not be printed.
1334
15.1k
  if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL &&
1335
15.1k
      AArch64_AM_getShiftValue(Val) == 0)
1336
1.37k
    return;
1337
1338
13.7k
  SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)));
1339
13.7k
  printInt32BangDec(O, AArch64_AM_getShiftValue(Val));
1340
1341
13.7k
  if (MI->csh->detail) {
1342
13.7k
    arm64_shifter shifter = ARM64_SFT_INVALID;
1343
1344
13.7k
    switch(AArch64_AM_getShiftType(Val)) {
1345
0
      default:  // never reach
1346
6.94k
      case AArch64_AM_LSL:
1347
6.94k
        shifter = ARM64_SFT_LSL;
1348
6.94k
        break;
1349
1350
2.61k
      case AArch64_AM_LSR:
1351
2.61k
        shifter = ARM64_SFT_LSR;
1352
2.61k
        break;
1353
1354
2.40k
      case AArch64_AM_ASR:
1355
2.40k
        shifter = ARM64_SFT_ASR;
1356
2.40k
        break;
1357
1358
846
      case AArch64_AM_ROR:
1359
846
        shifter = ARM64_SFT_ROR;
1360
846
        break;
1361
1362
949
      case AArch64_AM_MSL:
1363
949
        shifter = ARM64_SFT_MSL;
1364
949
        break;
1365
13.7k
    }
1366
1367
13.7k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter;
1368
13.7k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val);
1369
13.7k
  }
1370
13.7k
}
1371
1372
static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1373
7.75k
{
1374
7.75k
  SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1375
1376
7.75k
  if (MI->csh->detail) {
1377
7.75k
#ifndef CAPSTONE_DIET
1378
7.75k
    uint8_t access;
1379
7.75k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1380
7.75k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1381
7.75k
    MI->ac_idx++;
1382
7.75k
#endif
1383
7.75k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1384
7.75k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1385
7.75k
    MI->flat_insn->detail->arm64.op_count++;
1386
7.75k
  }
1387
1388
7.75k
  printShifter(MI, OpNum + 1, O);
1389
7.75k
}
1390
1391
static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
1392
5.12k
{
1393
5.12k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1394
5.12k
  AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
1395
5.12k
  unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
1396
1397
  // If the destination or first source register operand is [W]SP, print
1398
  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1399
  // all.
1400
5.12k
  if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) {
1401
2.93k
    unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0));
1402
2.93k
    unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
1403
1404
2.93k
    if (((Dest == AArch64_SP || Src1 == AArch64_SP) &&
1405
2.93k
          ExtType == AArch64_AM_UXTX) ||
1406
2.93k
        ((Dest == AArch64_WSP || Src1 == AArch64_WSP) &&
1407
2.51k
         ExtType == AArch64_AM_UXTW)) {
1408
503
      if (ShiftVal != 0) {
1409
503
        SStream_concat0(O, ", lsl ");
1410
503
        printInt32Bang(O, ShiftVal);
1411
1412
503
        if (MI->csh->detail) {
1413
503
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1414
503
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1415
503
        }
1416
503
      }
1417
1418
503
      return;
1419
503
    }
1420
2.93k
  }
1421
1422
4.62k
  SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
1423
1424
4.62k
  if (MI->csh->detail) {
1425
4.62k
    arm64_extender ext = ARM64_EXT_INVALID;
1426
4.62k
    switch(ExtType) {
1427
0
      default:  // never reach
1428
1429
100
      case AArch64_AM_UXTB:
1430
100
        ext = ARM64_EXT_UXTB;
1431
100
        break;
1432
1433
1.10k
      case AArch64_AM_UXTH:
1434
1.10k
        ext = ARM64_EXT_UXTH;
1435
1.10k
        break;
1436
1437
362
      case AArch64_AM_UXTW:
1438
362
        ext = ARM64_EXT_UXTW;
1439
362
        break;
1440
1441
2.06k
      case AArch64_AM_UXTX:
1442
2.06k
        ext = ARM64_EXT_UXTX;
1443
2.06k
        break;
1444
1445
261
      case AArch64_AM_SXTB:
1446
261
        ext = ARM64_EXT_SXTB;
1447
261
        break;
1448
1449
334
      case AArch64_AM_SXTH:
1450
334
        ext = ARM64_EXT_SXTH;
1451
334
        break;
1452
1453
170
      case AArch64_AM_SXTW:
1454
170
        ext = ARM64_EXT_SXTW;
1455
170
        break;
1456
1457
226
      case AArch64_AM_SXTX:
1458
226
        ext = ARM64_EXT_SXTX;
1459
226
        break;
1460
4.62k
    }
1461
1462
4.62k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext;
1463
4.62k
  }
1464
1465
4.62k
  if (ShiftVal != 0) {
1466
3.96k
    SStream_concat0(O, " ");
1467
3.96k
    printInt32Bang(O, ShiftVal);
1468
1469
3.96k
    if (MI->csh->detail) {
1470
3.96k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1471
3.96k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1472
3.96k
    }
1473
3.96k
  }
1474
4.62k
}
1475
1476
static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1477
2.94k
{
1478
2.94k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1479
1480
2.94k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1481
1482
2.94k
  if (MI->csh->detail) {
1483
2.94k
#ifndef CAPSTONE_DIET
1484
2.94k
    uint8_t access;
1485
2.94k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1486
2.94k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1487
2.94k
    MI->ac_idx++;
1488
2.94k
#endif
1489
2.94k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1490
2.94k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1491
2.94k
    MI->flat_insn->detail->arm64.op_count++;
1492
2.94k
  }
1493
1494
2.94k
  printArithExtend(MI, OpNum + 1, O);
1495
2.94k
}
1496
1497
static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width,
1498
             char SrcRegKind, SStream *O)
1499
17.0k
{
1500
  // sxtw, sxtx, uxtw or lsl (== uxtx)
1501
17.0k
  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1502
17.0k
  if (IsLSL) {
1503
7.07k
    SStream_concat0(O, "lsl");
1504
1505
7.07k
    if (MI->csh->detail) {
1506
7.07k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1507
7.07k
    }
1508
9.93k
  } else {
1509
9.93k
    SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind);
1510
1511
9.93k
    if (MI->csh->detail) {
1512
9.93k
      if (!SignExtend) {
1513
5.93k
        switch(SrcRegKind) {
1514
0
          default: break;
1515
0
          case 'b':
1516
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB;
1517
0
               break;
1518
0
          case 'h':
1519
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH;
1520
0
               break;
1521
5.93k
          case 'w':
1522
5.93k
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW;
1523
5.93k
               break;
1524
5.93k
        }
1525
5.93k
      } else {
1526
4.00k
          switch(SrcRegKind) {
1527
0
            default: break;
1528
0
            case 'b':
1529
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB;
1530
0
              break;
1531
0
            case 'h':
1532
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH;
1533
0
              break;
1534
3.57k
            case 'w':
1535
3.57k
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW;
1536
3.57k
              break;
1537
424
            case 'x':
1538
424
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX;
1539
424
              break;
1540
4.00k
          }
1541
4.00k
      }
1542
9.93k
    }
1543
9.93k
  }
1544
1545
17.0k
  if (DoShift || IsLSL) {
1546
13.7k
    SStream_concat(O, " #%u", Log2_32(Width / 8));
1547
1548
13.7k
    if (MI->csh->detail) {
1549
13.7k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1550
13.7k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8);
1551
13.7k
    }
1552
13.7k
  }
1553
17.0k
}
1554
1555
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
1556
2.57k
{
1557
2.57k
  unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1558
2.57k
  unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
1559
1560
2.57k
  printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O);
1561
2.57k
}
1562
1563
static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O,
1564
            bool SignExtend, int ExtWidth,
1565
            char SrcRegKind, char Suffix)
1566
18.6k
{
1567
18.6k
  bool DoShift;
1568
1569
18.6k
  printOperand(MI, OpNum, O);
1570
1571
18.6k
  if (Suffix == 's' || Suffix == 'd')
1572
11.2k
    SStream_concat(O, ".%c", Suffix);
1573
1574
18.6k
  DoShift = ExtWidth != 8;
1575
18.6k
  if (SignExtend || DoShift || SrcRegKind == 'w') {
1576
14.4k
    SStream_concat0(O, ", ");
1577
14.4k
    printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1578
14.4k
  }
1579
18.6k
}
1580
1581
static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1582
2.84k
{
1583
2.84k
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1584
2.84k
  SStream_concat0(O, getCondCodeName(CC));
1585
1586
2.84k
  if (MI->csh->detail)
1587
2.84k
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1);
1588
2.84k
}
1589
1590
static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1591
127
{
1592
127
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1593
127
  SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC)));
1594
1595
127
  if (MI->csh->detail) {
1596
127
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1);
1597
127
  }
1598
127
}
1599
1600
static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
1601
24.4k
{
1602
24.4k
  int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1603
1604
24.4k
  printInt64Bang(O, val);
1605
1606
24.4k
  if (MI->csh->detail) {
1607
24.4k
    if (MI->csh->doing_mem) {
1608
19.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1609
19.4k
    } else {
1610
4.99k
#ifndef CAPSTONE_DIET
1611
4.99k
      uint8_t access;
1612
1613
4.99k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1614
4.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1615
4.99k
      MI->ac_idx++;
1616
4.99k
#endif
1617
4.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1618
4.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
1619
4.99k
      MI->flat_insn->detail->arm64.op_count++;
1620
4.99k
    }
1621
24.4k
  }
1622
24.4k
}
1623
1624
static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale)
1625
9.45k
{
1626
9.45k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1627
1628
9.45k
  if (MCOperand_isImm(MO)) {
1629
9.45k
    int64_t val = Scale * MCOperand_getImm(MO);
1630
9.45k
    printInt64Bang(O, val);
1631
1632
9.45k
    if (MI->csh->detail) {
1633
9.45k
      if (MI->csh->doing_mem) {
1634
9.45k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1635
9.45k
      } else {
1636
0
#ifndef CAPSTONE_DIET
1637
0
        uint8_t access;
1638
1639
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1640
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1641
0
        MI->ac_idx++;
1642
0
#endif
1643
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1644
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
1645
0
        MI->flat_insn->detail->arm64.op_count++;
1646
0
      }
1647
9.45k
    }
1648
9.45k
  }
1649
9.45k
}
1650
1651
#if 0
1652
static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale)
1653
{
1654
  MCOperand *MO = MCInst_getOperand(MI, OpNum + 1);
1655
1656
  SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1657
1658
  if (MCOperand_isImm(MO)) {
1659
    int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1660
    printInt64Bang(O, val);
1661
  // } else {
1662
  //   // assert(MO1.isExpr() && "Unexpected operand type!");
1663
  //   SStream_concat0(O, ", ");
1664
  //   MO1.getExpr()->print(O, &MAI);
1665
  }
1666
1667
  SStream_concat0(O, "]");
1668
}
1669
#endif
1670
1671
// IsSVEPrefetch = false
1672
static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch)
1673
6.76k
{
1674
6.76k
  unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1675
1676
6.76k
  if (IsSVEPrefetch) {
1677
5.63k
    const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop);
1678
5.63k
    if (PRFM)
1679
4.37k
      SStream_concat0(O, PRFM->Name);
1680
1681
5.63k
    return;
1682
5.63k
  } else {
1683
1.13k
    const PRFM *PRFM = lookupPRFMByEncoding(prfop);
1684
1.13k
    if (PRFM)
1685
697
      SStream_concat0(O, PRFM->Name);
1686
1687
1.13k
    return;
1688
1.13k
  }
1689
1690
  // FIXME: set OpcodePub?
1691
1692
0
  printInt32Bang(O, prfop);
1693
1694
0
  if (MI->csh->detail) {
1695
0
#ifndef CAPSTONE_DIET
1696
0
    uint8_t access;
1697
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1698
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1699
0
    MI->ac_idx++;
1700
0
#endif
1701
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1702
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop;
1703
0
    MI->flat_insn->detail->arm64.op_count++;
1704
0
  }
1705
0
}
1706
1707
static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
1708
995
{
1709
995
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1710
995
  unsigned int psbhintop = MCOperand_getImm(Op);
1711
1712
995
  const PSB *PSB = lookupPSBByEncoding(psbhintop);
1713
995
  if (PSB)
1714
995
    SStream_concat0(O, PSB->Name);
1715
0
  else
1716
0
    printUInt32Bang(O, psbhintop);
1717
995
}
1718
1719
788
static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) {
1720
788
  unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) ^ 32;
1721
1722
788
  const BTI *BTI = lookupBTIByEncoding(btihintop);
1723
788
  if (BTI)
1724
788
  SStream_concat0(O, BTI->Name);
1725
0
  else
1726
0
  printUInt32Bang(O, btihintop);
1727
788
}
1728
1729
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1730
1.02k
{
1731
1.02k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1732
1.02k
  float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO));
1733
1734
  // 8 decimal places are enough to perfectly represent permitted floats.
1735
#if defined(_KERNEL_MODE)
1736
  // Issue #681: Windows kernel does not support formatting float point
1737
  SStream_concat0(O, "#<float_point_unsupported>");
1738
#else
1739
1.02k
  SStream_concat(O, "#%.8f", FPImm);
1740
1.02k
#endif
1741
1742
1.02k
  if (MI->csh->detail) {
1743
1.02k
#ifndef CAPSTONE_DIET
1744
1.02k
    uint8_t access;
1745
1746
1.02k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1747
1.02k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1748
1.02k
    MI->ac_idx++;
1749
1.02k
#endif
1750
1.02k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
1751
1.02k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm;
1752
1.02k
    MI->flat_insn->detail->arm64.op_count++;
1753
1.02k
  }
1754
1.02k
}
1755
1756
//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1)
1757
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride)
1758
240k
{
1759
481k
  while (Stride--) {
1760
240k
    if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30
1761
203k
      Reg += 1;
1762
37.1k
    else if (Reg == AArch64_Q31) // Vector lists can wrap around.
1763
9.36k
      Reg = AArch64_Q0;
1764
27.7k
    else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30
1765
27.0k
      Reg += 1;
1766
730
    else if (Reg == AArch64_Z31) // Vector lists can wrap around.
1767
730
      Reg = AArch64_Z0;
1768
240k
  }
1769
1770
240k
  return Reg;
1771
240k
}
1772
1773
static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size)
1774
1.36k
{
1775
  // static_assert(size == 64 || size == 32,
1776
  //    "Template parameter must be either 32 or 64");
1777
1.36k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1778
1.36k
  unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64;
1779
1.36k
  unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64;
1780
1.36k
  unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube);
1781
1.36k
  unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo);
1782
1783
1.36k
  SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName),
1784
1.36k
      getRegisterName(Odd, AArch64_NoRegAltName));
1785
1786
1.36k
  if (MI->csh->detail) {
1787
1.36k
#ifndef CAPSTONE_DIET
1788
1.36k
    uint8_t access;
1789
1790
1.36k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1791
1.36k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1792
1.36k
    MI->ac_idx++;
1793
1.36k
#endif
1794
1795
1.36k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1796
1.36k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Even;
1797
1.36k
    MI->flat_insn->detail->arm64.op_count++;
1798
1799
1.36k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1800
1.36k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Odd;
1801
1.36k
    MI->flat_insn->detail->arm64.op_count++;
1802
1.36k
  }
1803
1.36k
}
1804
1805
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
1806
    char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas)
1807
98.3k
{
1808
1.43M
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
1809
98.3k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1810
98.3k
  unsigned NumRegs = 1, FirstReg, i;
1811
1812
98.3k
  SStream_concat0(O, "{");
1813
1814
  // Work out how many registers there are in the list (if there is an actual
1815
  // list).
1816
98.3k
  if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) ||
1817
98.3k
      GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) ||
1818
98.3k
      GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg))
1819
19.5k
    NumRegs = 2;
1820
78.8k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) ||
1821
78.8k
      GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) ||
1822
78.8k
      GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg))
1823
29.3k
    NumRegs = 3;
1824
49.5k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) ||
1825
49.5k
      GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) ||
1826
49.5k
      GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg))
1827
21.3k
    NumRegs = 4;
1828
1829
  // Now forget about the list and find out what the first register is.
1830
98.3k
  if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0)))
1831
14.3k
    Reg = FirstReg;
1832
84.0k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0)))
1833
50.7k
    Reg = FirstReg;
1834
33.3k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0)))
1835
5.10k
    Reg = FirstReg;
1836
1837
  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1838
  // printing (otherwise getRegisterName fails).
1839
98.3k
  if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
1840
16.5k
    const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
1841
16.5k
    Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
1842
16.5k
  }
1843
1844
338k
  for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) {
1845
240k
    bool isZReg = GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg);
1846
240k
    if (isZReg)
1847
27.7k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix);
1848
212k
    else
1849
212k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
1850
1851
240k
    if (MI->csh->detail) {
1852
240k
#ifndef CAPSTONE_DIET
1853
240k
      uint8_t access;
1854
1855
240k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1856
240k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1857
240k
      MI->ac_idx++;
1858
240k
#endif
1859
240k
      unsigned regForDetail = isZReg ? Reg : AArch64_map_vregister(Reg);
1860
240k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1861
240k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = regForDetail;
1862
240k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
1863
240k
      MI->flat_insn->detail->arm64.op_count++;
1864
240k
    }
1865
1866
240k
    if (i + 1 != NumRegs)
1867
142k
      SStream_concat0(O, ", ");
1868
240k
  }
1869
1870
98.3k
  SStream_concat0(O, "}");
1871
98.3k
}
1872
1873
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind)
1874
98.3k
{
1875
98.3k
  char Suffix[32];
1876
98.3k
  arm64_vas vas = 0;
1877
1878
98.3k
  if (NumLanes) {
1879
40.6k
    cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind);
1880
1881
40.6k
    switch(LaneKind) {
1882
0
      default: break;
1883
11.4k
      case 'b':
1884
11.4k
        switch(NumLanes) {
1885
0
          default: break;
1886
0
          case 1:
1887
0
               vas = ARM64_VAS_1B;
1888
0
               break;
1889
0
          case 4:
1890
0
               vas = ARM64_VAS_4B;
1891
0
               break;
1892
4.46k
          case 8:
1893
4.46k
               vas = ARM64_VAS_8B;
1894
4.46k
               break;
1895
7.01k
          case 16:
1896
7.01k
               vas = ARM64_VAS_16B;
1897
7.01k
               break;
1898
11.4k
        }
1899
11.4k
        break;
1900
11.4k
      case 'h':
1901
10.8k
        switch(NumLanes) {
1902
0
          default: break;
1903
0
          case 1:
1904
0
               vas = ARM64_VAS_1H;
1905
0
               break;
1906
0
          case 2:
1907
0
               vas = ARM64_VAS_2H;
1908
0
               break;
1909
5.18k
          case 4:
1910
5.18k
               vas = ARM64_VAS_4H;
1911
5.18k
               break;
1912
5.69k
          case 8:
1913
5.69k
               vas = ARM64_VAS_8H;
1914
5.69k
               break;
1915
10.8k
        }
1916
10.8k
        break;
1917
10.8k
      case 's':
1918
10.8k
        switch(NumLanes) {
1919
0
          default: break;
1920
0
          case 1:
1921
0
               vas = ARM64_VAS_1S;
1922
0
               break;
1923
3.67k
          case 2:
1924
3.67k
               vas = ARM64_VAS_2S;
1925
3.67k
               break;
1926
7.21k
          case 4:
1927
7.21k
               vas = ARM64_VAS_4S;
1928
7.21k
               break;
1929
10.8k
        }
1930
10.8k
        break;
1931
10.8k
      case 'd':
1932
7.43k
        switch(NumLanes) {
1933
0
          default: break;
1934
3.22k
          case 1:
1935
3.22k
               vas = ARM64_VAS_1D;
1936
3.22k
               break;
1937
4.20k
          case 2:
1938
4.20k
               vas = ARM64_VAS_2D;
1939
4.20k
               break;
1940
7.43k
        }
1941
7.43k
        break;
1942
7.43k
      case 'q':
1943
0
        switch(NumLanes) {
1944
0
          default: break;
1945
0
          case 1:
1946
0
               vas = ARM64_VAS_1Q;
1947
0
               break;
1948
0
        }
1949
0
        break;
1950
40.6k
    }
1951
57.7k
  } else {
1952
57.7k
    cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind);
1953
1954
57.7k
    switch(LaneKind) {
1955
0
      default: break;
1956
13.9k
      case 'b':
1957
13.9k
           vas = ARM64_VAS_1B;
1958
13.9k
           break;
1959
11.4k
      case 'h':
1960
11.4k
           vas = ARM64_VAS_1H;
1961
11.4k
           break;
1962
15.9k
      case 's':
1963
15.9k
           vas = ARM64_VAS_1S;
1964
15.9k
           break;
1965
16.4k
      case 'd':
1966
16.4k
           vas = ARM64_VAS_1D;
1967
16.4k
           break;
1968
0
      case 'q':
1969
0
           vas = ARM64_VAS_1Q;
1970
0
           break;
1971
57.7k
    }
1972
57.7k
  }
1973
1974
98.3k
  printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas);
1975
98.3k
}
1976
1977
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
1978
48.4k
{
1979
48.4k
  SStream_concat0(O, "[");
1980
48.4k
  printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
1981
48.4k
  SStream_concat0(O, "]");
1982
1983
48.4k
  if (MI->csh->detail) {
1984
48.4k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1985
48.4k
  }
1986
48.4k
}
1987
1988
static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
1989
15.4k
{
1990
15.4k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1991
1992
  // If the label has already been resolved to an immediate offset (say, when
1993
  // we're running the disassembler), just print the immediate.
1994
15.4k
  if (MCOperand_isImm(Op)) {
1995
15.4k
    uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address;
1996
15.4k
    printUInt64Bang(O, imm);
1997
1998
15.4k
    if (MI->csh->detail) {
1999
15.4k
#ifndef CAPSTONE_DIET
2000
15.4k
      uint8_t access;
2001
2002
15.4k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2003
15.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2004
15.4k
      MI->ac_idx++;
2005
15.4k
#endif
2006
15.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2007
15.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2008
15.4k
      MI->flat_insn->detail->arm64.op_count++;
2009
15.4k
    }
2010
15.4k
  }
2011
15.4k
}
2012
2013
static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
2014
1.99k
{
2015
1.99k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
2016
2017
1.99k
  if (MCOperand_isImm(Op)) {
2018
    // ADRP sign extends a 21-bit offset, shifts it left by 12
2019
    // and adds it to the value of the PC with its bottom 12 bits cleared
2020
1.99k
    uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff);
2021
1.99k
    printUInt64Bang(O, imm);
2022
2023
1.99k
    if (MI->csh->detail) {
2024
1.99k
#ifndef CAPSTONE_DIET
2025
1.99k
      uint8_t access;
2026
2027
1.99k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2028
1.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2029
1.99k
      MI->ac_idx++;
2030
1.99k
#endif
2031
1.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2032
1.99k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2033
1.99k
      MI->flat_insn->detail->arm64.op_count++;
2034
1.99k
    }
2035
1.99k
  }
2036
1.99k
}
2037
2038
static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
2039
1.05k
{
2040
1.05k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2041
1.05k
  unsigned Opcode = MCInst_getOpcode(MI);
2042
1.05k
  const char *Name = NULL;
2043
2044
1.05k
  if (Opcode == AArch64_ISB) {
2045
52
    const ISB *ISB = lookupISBByEncoding(Val);
2046
52
    Name = ISB ? ISB->Name : NULL;
2047
1.00k
  } else if (Opcode == AArch64_TSB) {
2048
0
    const TSB *TSB = lookupTSBByEncoding(Val);
2049
0
    Name = TSB ? TSB->Name : NULL;
2050
1.00k
  } else {
2051
1.00k
    const DB *DB = lookupDBByEncoding(Val);
2052
1.00k
    Name = DB ? DB->Name : NULL;
2053
1.00k
  }
2054
2055
1.05k
  if (Name) {
2056
407
    SStream_concat0(O, Name);
2057
2058
407
    if (MI->csh->detail) {
2059
407
#ifndef CAPSTONE_DIET
2060
407
      uint8_t access;
2061
2062
407
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2063
407
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2064
407
      MI->ac_idx++;
2065
407
#endif
2066
407
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2067
407
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2068
407
      MI->flat_insn->detail->arm64.op_count++;
2069
407
    }
2070
646
  } else {
2071
646
    printUInt32Bang(O, Val);
2072
2073
646
    if (MI->csh->detail) {
2074
646
#ifndef CAPSTONE_DIET
2075
646
      uint8_t access;
2076
2077
646
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2078
646
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2079
646
      MI->ac_idx++;
2080
646
#endif
2081
646
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2082
646
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2083
646
      MI->flat_insn->detail->arm64.op_count++;
2084
646
    }
2085
646
  }
2086
1.05k
}
2087
2088
22
static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) {
2089
22
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
2090
  // assert(MI->getOpcode() == AArch64::DSBnXS);
2091
2092
22
  const char *Name = NULL;
2093
22
  const DBnXS *DB = lookupDBnXSByEncoding(Val);
2094
22
  Name = DB ? DB->Name : NULL;
2095
2096
22
  if (Name) {
2097
22
    SStream_concat0(O, Name);
2098
2099
22
    if (MI->csh->detail) {
2100
22
#ifndef CAPSTONE_DIET
2101
22
      uint8_t access;
2102
2103
22
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2104
22
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2105
22
      MI->ac_idx++;
2106
22
#endif
2107
22
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2108
22
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2109
22
      MI->flat_insn->detail->arm64.op_count++;
2110
22
    }
2111
22
  }
2112
0
  else {
2113
0
    printUInt32Bang(O, Val);
2114
2115
0
    if (MI->csh->detail) {
2116
0
#ifndef CAPSTONE_DIET
2117
0
      uint8_t access;
2118
2119
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2120
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2121
0
      MI->ac_idx++;
2122
0
#endif
2123
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2124
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2125
0
      MI->flat_insn->detail->arm64.op_count++;
2126
0
    }
2127
0
  }
2128
22
}
2129
2130
static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2131
3.34k
{
2132
3.34k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2133
3.34k
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2134
2135
  // Horrible hack for the one register that has identical encodings but
2136
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2137
  // going to get the wrong entry
2138
3.34k
  if (Val == ARM64_SYSREG_DBGDTRRX_EL0) {
2139
36
    SStream_concat0(O, "dbgdtrrx_el0");
2140
2141
36
    if (MI->csh->detail) {
2142
36
#ifndef CAPSTONE_DIET
2143
36
      uint8_t access;
2144
2145
36
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2146
36
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2147
36
      MI->ac_idx++;
2148
36
#endif
2149
2150
36
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2151
36
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2152
36
      MI->flat_insn->detail->arm64.op_count++;
2153
36
    }
2154
2155
36
    return;
2156
36
  }
2157
2158
  // Another hack for a register which has an alternative name which is not an alias,
2159
  // and is not in the Armv9-A documentation.
2160
3.31k
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2161
18
    SStream_concat0(O, "ttbr0_el2");
2162
2163
18
    if (MI->csh->detail) {
2164
18
#ifndef CAPSTONE_DIET
2165
18
      uint8_t access;
2166
2167
18
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2168
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2169
18
      MI->ac_idx++;
2170
18
#endif
2171
2172
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2173
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2174
18
      MI->flat_insn->detail->arm64.op_count++;
2175
18
    }
2176
2177
18
    return;
2178
18
  }
2179
2180
  // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
2181
3.29k
  if (Reg && Reg->Readable) {
2182
626
    SStream_concat0(O, Reg->Name);
2183
2184
626
    if (MI->csh->detail) {
2185
626
#ifndef CAPSTONE_DIET
2186
626
      uint8_t access;
2187
2188
626
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2189
626
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2190
626
      MI->ac_idx++;
2191
626
#endif
2192
2193
626
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2194
626
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2195
626
      MI->flat_insn->detail->arm64.op_count++;
2196
626
    }
2197
2.66k
  } else {
2198
2.66k
    char result[128];
2199
2200
2.66k
    AArch64SysReg_genericRegisterString(Val, result);
2201
2.66k
    SStream_concat0(O, result);
2202
2203
2.66k
    if (MI->csh->detail) {
2204
2.66k
#ifndef CAPSTONE_DIET
2205
2.66k
      uint8_t access;
2206
2.66k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2207
2.66k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2208
2.66k
      MI->ac_idx++;
2209
2.66k
#endif
2210
2.66k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2211
2.66k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2212
2.66k
      MI->flat_insn->detail->arm64.op_count++;
2213
2.66k
    }
2214
2.66k
  }
2215
3.29k
}
2216
2217
static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2218
3.40k
{
2219
3.40k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2220
3.40k
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2221
2222
  // Horrible hack for the one register that has identical encodings but
2223
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2224
  // going to get the wrong entry
2225
3.40k
  if (Val == ARM64_SYSREG_DBGDTRTX_EL0) {
2226
18
    SStream_concat0(O, "dbgdtrtx_el0");
2227
2228
18
    if (MI->csh->detail) {
2229
18
#ifndef CAPSTONE_DIET
2230
18
      uint8_t access;
2231
2232
18
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2233
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2234
18
      MI->ac_idx++;
2235
18
#endif
2236
2237
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2238
18
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2239
18
      MI->flat_insn->detail->arm64.op_count++;
2240
18
    }
2241
2242
18
    return;
2243
18
  }
2244
2245
  // Another hack for a register which has an alternative name which is not an alias,
2246
  // and is not in the Armv9-A documentation.
2247
3.38k
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2248
23
    SStream_concat0(O, "ttbr0_el2");
2249
2250
23
    if (MI->csh->detail) {
2251
23
#ifndef CAPSTONE_DIET
2252
23
      uint8_t access;
2253
2254
23
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2255
23
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2256
23
      MI->ac_idx++;
2257
23
#endif
2258
2259
23
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2260
23
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2261
23
      MI->flat_insn->detail->arm64.op_count++;
2262
23
    }
2263
2264
23
    return;
2265
23
  }
2266
2267
  // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
2268
3.36k
  if (Reg && Reg->Writeable) {
2269
214
    SStream_concat0(O, Reg->Name);
2270
2271
214
    if (MI->csh->detail) {
2272
214
#ifndef CAPSTONE_DIET
2273
214
      uint8_t access;
2274
2275
214
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2276
214
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2277
214
      MI->ac_idx++;
2278
214
#endif
2279
2280
214
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2281
214
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2282
214
      MI->flat_insn->detail->arm64.op_count++;
2283
214
    }
2284
3.14k
  } else {
2285
3.14k
    char result[128];
2286
2287
3.14k
    AArch64SysReg_genericRegisterString(Val, result);
2288
3.14k
    SStream_concat0(O, result);
2289
2290
3.14k
    if (MI->csh->detail) {
2291
3.14k
#ifndef CAPSTONE_DIET
2292
3.14k
      uint8_t access;
2293
3.14k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2294
3.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2295
3.14k
      MI->ac_idx++;
2296
3.14k
#endif
2297
3.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2298
3.14k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2299
3.14k
      MI->flat_insn->detail->arm64.op_count++;
2300
3.14k
    }
2301
3.14k
  }
2302
3.36k
}
2303
2304
static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
2305
305
{
2306
305
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2307
2308
305
  const PState *PState = lookupPStateByEncoding(Val);
2309
2310
305
  if (PState) {
2311
305
    SStream_concat0(O, PState->Name);
2312
2313
305
    if (MI->csh->detail) {
2314
305
#ifndef CAPSTONE_DIET
2315
305
      uint8_t access;
2316
305
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2317
305
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2318
305
      MI->ac_idx++;
2319
305
#endif
2320
305
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE;
2321
305
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val;
2322
305
      MI->flat_insn->detail->arm64.op_count++;
2323
305
    }
2324
305
  } else {
2325
0
    printUInt32Bang(O, Val);
2326
2327
0
    if (MI->csh->detail) {
2328
0
#ifndef CAPSTONE_DIET
2329
0
      unsigned char access;
2330
2331
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2332
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2333
0
      MI->ac_idx++;
2334
0
#endif
2335
2336
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2337
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2338
0
      MI->flat_insn->detail->arm64.op_count++;
2339
0
    }
2340
0
  }
2341
305
}
2342
2343
static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O)
2344
1.19k
{
2345
1.19k
  uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2346
1.19k
  uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
2347
2348
1.19k
  SStream_concat(O, "#%#016llx", Val);
2349
2350
1.19k
  if (MI->csh->detail) {
2351
1.19k
#ifndef CAPSTONE_DIET
2352
1.19k
    unsigned char access;
2353
2354
1.19k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2355
1.19k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2356
1.19k
    MI->ac_idx++;
2357
1.19k
#endif
2358
1.19k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2359
1.19k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2360
1.19k
    MI->flat_insn->detail->arm64.op_count++;
2361
1.19k
  }
2362
1.19k
}
2363
2364
static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder)
2365
2.93k
{
2366
2.93k
  unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2367
2.93k
  printInt64Bang(O, (Val * Angle) + Remainder);
2368
2.93k
  op_addImm(MI, (Val * Angle) + Remainder);
2369
2.93k
}
2370
2371
static void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
2372
0
{
2373
0
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
2374
    // assert(MCOperand_isImm(MO) && "Unexpected operand type!");
2375
0
    unsigned svcrop = MCOperand_getImm(MO);
2376
0
  const SVCR *svcr = lookupSVCRByEncoding(svcrop);
2377
    // assert(svcr && "Unexpected SVCR operand!");
2378
0
  SStream_concat0(O, svcr->Name);
2379
2380
0
  if (MI->csh->detail) {
2381
0
#ifndef CAPSTONE_DIET
2382
0
    uint8_t access;
2383
2384
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2385
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2386
0
    MI->ac_idx++;
2387
0
#endif
2388
2389
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SVCR;
2390
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = (unsigned)ARM64_SYSREG_SVCR;
2391
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].svcr = svcr->Encoding;
2392
0
    MI->flat_insn->detail->arm64.op_count++;
2393
0
  }
2394
0
}
2395
2396
static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize)
2397
258
{
2398
258
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2399
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2400
258
  unsigned Reg = MCOperand_getReg(RegOp);
2401
2402
258
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2403
258
  const char *sizeStr = "";
2404
258
    switch (EltSize) {
2405
258
    case 0:
2406
258
    sizeStr = "";
2407
258
      break;
2408
0
    case 8:
2409
0
      sizeStr = ".b";
2410
0
      break;
2411
0
    case 16:
2412
0
      sizeStr = ".h";
2413
0
      break;
2414
0
    case 32:
2415
0
      sizeStr = ".s";
2416
0
      break;
2417
0
    case 64:
2418
0
      sizeStr = ".d";
2419
0
      break;
2420
0
    case 128:
2421
0
      sizeStr = ".q";
2422
0
      break;
2423
0
    default:
2424
0
    break;
2425
    //   llvm_unreachable("Unsupported element size");
2426
258
    }
2427
258
  SStream_concat0(O, sizeStr);
2428
2429
258
  if (MI->csh->detail) {
2430
258
#ifndef CAPSTONE_DIET
2431
258
    uint8_t access;
2432
2433
258
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2434
258
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2435
258
    MI->ac_idx++;
2436
258
#endif
2437
2438
258
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2439
258
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2440
258
    MI->flat_insn->detail->arm64.op_count++;
2441
258
  }
2442
258
}
2443
2444
static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O)
2445
9.62k
{
2446
9.62k
  int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2447
9.62k
  printInt64(O, imm);
2448
2449
9.62k
  if (MI->csh->detail) {
2450
9.62k
    if (MI->csh->doing_SME_Index) {
2451
      // Access op_count-1 as We want to add info to previous operand, not create a new one
2452
9.62k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = imm;
2453
9.62k
    }
2454
9.62k
  }
2455
9.62k
}
2456
2457
static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
2458
1.60k
{
2459
1.60k
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2460
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2461
1.60k
  unsigned Reg = MCOperand_getReg(RegOp);
2462
1.60k
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2463
2464
1.60k
  if (MI->csh->detail) {
2465
1.60k
#ifndef CAPSTONE_DIET
2466
1.60k
    uint8_t access;
2467
2468
1.60k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2469
1.60k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2470
1.60k
    MI->ac_idx++;
2471
1.60k
#endif
2472
2473
1.60k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2474
1.60k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2475
1.60k
    MI->flat_insn->detail->arm64.op_count++;
2476
1.60k
  }
2477
1.60k
}
2478
2479
static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool IsVertical)
2480
8.17k
{
2481
8.17k
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2482
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2483
8.17k
  unsigned Reg = MCOperand_getReg(RegOp);
2484
8.17k
#ifndef CAPSTONE_DIET
2485
8.17k
  const char *RegName = getRegisterName(Reg, AArch64_NoRegAltName);
2486
2487
8.17k
  const size_t strLn = strlen(RegName);
2488
  // +2 for extra chars, + 1 for null char \0
2489
8.17k
  char *RegNameNew = cs_mem_malloc(sizeof(char) * (strLn + 2 + 1));
2490
8.17k
  int index = 0, i;
2491
66.1k
  for (i = 0; i < (strLn + 2); i++){
2492
57.9k
    if(RegName[i] != '.'){
2493
49.7k
      RegNameNew[index] = RegName[i];
2494
49.7k
      index++;
2495
49.7k
    }
2496
8.17k
    else{
2497
8.17k
      RegNameNew[index] = IsVertical ? 'v' : 'h';
2498
8.17k
      RegNameNew[index + 1] = '.';
2499
8.17k
      index += 2;
2500
8.17k
    }
2501
57.9k
  }
2502
8.17k
  SStream_concat0(O, RegNameNew);
2503
8.17k
#endif
2504
2505
8.17k
  if (MI->csh->detail) {
2506
8.17k
#ifndef CAPSTONE_DIET
2507
8.17k
    uint8_t access;
2508
2509
8.17k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2510
8.17k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2511
8.17k
    MI->ac_idx++;
2512
8.17k
#endif
2513
2514
8.17k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2515
8.17k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2516
8.17k
    MI->flat_insn->detail->arm64.op_count++;
2517
8.17k
  }
2518
8.17k
#ifndef CAPSTONE_DIET
2519
8.17k
  cs_mem_free(RegNameNew);
2520
8.17k
#endif
2521
8.17k
}
2522
2523
static const unsigned MatrixZADRegisterTable[] = {
2524
  AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3,
2525
  AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7
2526
};
2527
2528
439
static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
2529
439
  unsigned MaxRegs = 8;
2530
439
  unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2531
2532
439
  unsigned NumRegs = 0, I;
2533
3.95k
  for (I = 0; I < MaxRegs; ++I)
2534
3.51k
    if ((RegMask & (1 << I)) != 0)
2535
963
      ++NumRegs;
2536
2537
439
  SStream_concat0(O, "{");
2538
439
  unsigned Printed = 0, J;
2539
3.95k
  for (J = 0; J < MaxRegs; ++J) {
2540
3.51k
    unsigned Reg = RegMask & (1 << J);
2541
3.51k
    if (Reg == 0)
2542
2.54k
      continue;
2543
963
    SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName));
2544
2545
963
    if (MI->csh->detail) {
2546
963
#ifndef CAPSTONE_DIET
2547
963
      uint8_t access;
2548
2549
963
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2550
963
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2551
963
      MI->ac_idx++;
2552
963
#endif
2553
2554
963
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2555
963
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[J];
2556
963
      MI->flat_insn->detail->arm64.op_count++;
2557
963
    }
2558
2559
963
    if (Printed + 1 != NumRegs)
2560
524
      SStream_concat0(O, ", ");
2561
963
    ++Printed;
2562
963
  }
2563
439
  SStream_concat0(O, "}");
2564
439
}
2565
2566
static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
2567
2.89k
{
2568
2.89k
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2569
2570
2.89k
  const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val);
2571
2.89k
  if (Pat)
2572
1.12k
    SStream_concat0(O, Pat->Name);
2573
1.77k
  else
2574
1.77k
    printUInt32Bang(O, Val);
2575
2.89k
}
2576
2577
// default suffix = 0
2578
static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix)
2579
142k
{
2580
142k
  unsigned int Reg;
2581
2582
#if 0
2583
  switch (suffix) {
2584
    case 0:
2585
    case 'b':
2586
    case 'h':
2587
    case 's':
2588
    case 'd':
2589
    case 'q':
2590
      break;
2591
    default:
2592
      // llvm_unreachable("Invalid kind specifier.");
2593
  }
2594
#endif
2595
2596
142k
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2597
2598
142k
  if (MI->csh->detail) {
2599
142k
#ifndef CAPSTONE_DIET
2600
142k
      uint8_t access;
2601
2602
142k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2603
142k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2604
142k
      MI->ac_idx++;
2605
142k
#endif
2606
142k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2607
142k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2608
142k
    MI->flat_insn->detail->arm64.op_count++;
2609
142k
  }
2610
2611
142k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2612
2613
142k
  if (suffix != '\0')
2614
90.5k
    SStream_concat(O, ".%c", suffix);
2615
142k
}
2616
2617
static void printImmSVE16(int16_t Val, SStream *O)
2618
740
{
2619
740
  printUInt32Bang(O, Val);
2620
740
}
2621
2622
static void printImmSVE32(int32_t Val, SStream *O)
2623
1.42k
{
2624
1.42k
  printUInt32Bang(O, Val);
2625
1.42k
}
2626
2627
static void printImmSVE64(int64_t Val, SStream *O)
2628
1.28k
{
2629
1.28k
  printUInt64Bang(O, Val);
2630
1.28k
}
2631
2632
static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O)
2633
1.44k
{
2634
1.44k
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2635
1.44k
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2636
1.44k
  uint32_t Val;
2637
2638
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2639
  //  "Unexepected shift type!");
2640
2641
  // #0 lsl #8 is never pretty printed
2642
1.44k
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2643
14
    printUInt32Bang(O, UnscaledVal);
2644
14
    printShifter(MI, OpNum + 1, O);
2645
14
    return;
2646
14
  }
2647
2648
1.42k
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2649
1.42k
  printImmSVE32(Val, O);
2650
1.42k
}
2651
2652
static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O)
2653
481
{
2654
481
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2655
481
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2656
481
  uint64_t Val;
2657
2658
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2659
  //  "Unexepected shift type!");
2660
2661
  // #0 lsl #8 is never pretty printed
2662
481
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2663
58
    printUInt32Bang(O, UnscaledVal);
2664
58
    printShifter(MI, OpNum + 1, O);
2665
58
    return;
2666
58
  }
2667
2668
423
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2669
423
  printImmSVE64(Val, O);
2670
423
}
2671
2672
static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O)
2673
218
{
2674
218
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2675
218
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2676
2677
  // Prefer the default format for 16bit values, hex otherwise.
2678
218
  printImmSVE16(PrintVal, O);
2679
218
}
2680
2681
static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
2682
1.20k
{
2683
1.20k
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2684
1.20k
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2685
2686
  // Prefer the default format for 16bit values, hex otherwise.
2687
1.20k
  if ((uint16_t)PrintVal == (uint32_t)PrintVal)
2688
522
    printImmSVE16(PrintVal, O);
2689
685
  else
2690
685
    printUInt64Bang(O, PrintVal);
2691
1.20k
}
2692
2693
static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
2694
861
{
2695
861
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2696
861
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2697
2698
861
  printImmSVE64(PrintVal, O);
2699
861
}
2700
2701
static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width)
2702
1.81k
{
2703
1.81k
  unsigned int Base, Reg;
2704
2705
1.81k
  switch (Width) {
2706
0
    default: // llvm_unreachable("Unsupported width");
2707
62
    case 8:   Base = AArch64_B0; break;
2708
459
    case 16:  Base = AArch64_H0; break;
2709
811
    case 32:  Base = AArch64_S0; break;
2710
417
    case 64:  Base = AArch64_D0; break;
2711
67
    case 128: Base = AArch64_Q0; break;
2712
1.81k
  }
2713
2714
1.81k
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) - AArch64_Z0 + Base;
2715
2716
1.81k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2717
2718
1.81k
  if (MI->csh->detail) {
2719
1.81k
#ifndef CAPSTONE_DIET
2720
1.81k
    uint8_t access;
2721
2722
1.81k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2723
1.81k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2724
1.81k
    MI->ac_idx++;
2725
1.81k
#endif
2726
1.81k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2727
1.81k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2728
1.81k
    MI->flat_insn->detail->arm64.op_count++;
2729
1.81k
  }
2730
1.81k
}
2731
2732
static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1)
2733
518
{
2734
518
  const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0);
2735
518
  const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1);
2736
518
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2737
2738
518
  SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2739
518
}
2740
2741
static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O)
2742
4.51k
{
2743
4.51k
  unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2744
2745
4.51k
  SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName));
2746
4.51k
}
2747
2748
static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) 
2749
996
{
2750
996
    unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2751
2752
996
    SStream_concat0(O, getRegisterName(MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0), AArch64_NoRegAltName));
2753
996
}
2754
2755
#define PRINT_ALIAS_INSTR
2756
#include "AArch64GenAsmWriter.inc"
2757
#include "AArch64GenRegisterName.inc"
2758
2759
void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci)
2760
346k
{
2761
346k
  if (((cs_struct *)handle)->detail != CS_OPT_ON)
2762
0
    return;
2763
2764
346k
  if (mci->csh->detail) {
2765
346k
    unsigned opcode = MCInst_getOpcode(mci);
2766
2767
346k
    switch (opcode) {
2768
275k
      default:
2769
275k
        break;
2770
275k
      case AArch64_LD1Fourv16b_POST:
2771
1.07k
      case AArch64_LD1Fourv1d_POST:
2772
1.17k
      case AArch64_LD1Fourv2d_POST:
2773
1.28k
      case AArch64_LD1Fourv2s_POST:
2774
1.97k
      case AArch64_LD1Fourv4h_POST:
2775
2.15k
      case AArch64_LD1Fourv4s_POST:
2776
2.26k
      case AArch64_LD1Fourv8b_POST:
2777
3.48k
      case AArch64_LD1Fourv8h_POST:
2778
3.52k
      case AArch64_LD1Onev16b_POST:
2779
3.59k
      case AArch64_LD1Onev1d_POST:
2780
3.68k
      case AArch64_LD1Onev2d_POST:
2781
3.91k
      case AArch64_LD1Onev2s_POST:
2782
4.02k
      case AArch64_LD1Onev4h_POST:
2783
4.14k
      case AArch64_LD1Onev4s_POST:
2784
4.34k
      case AArch64_LD1Onev8b_POST:
2785
4.36k
      case AArch64_LD1Onev8h_POST:
2786
4.53k
      case AArch64_LD1Rv16b_POST:
2787
4.73k
      case AArch64_LD1Rv1d_POST:
2788
4.88k
      case AArch64_LD1Rv2d_POST:
2789
4.90k
      case AArch64_LD1Rv2s_POST:
2790
5.06k
      case AArch64_LD1Rv4h_POST:
2791
5.21k
      case AArch64_LD1Rv4s_POST:
2792
5.22k
      case AArch64_LD1Rv8b_POST:
2793
5.24k
      case AArch64_LD1Rv8h_POST:
2794
5.47k
      case AArch64_LD1Threev16b_POST:
2795
5.65k
      case AArch64_LD1Threev1d_POST:
2796
5.97k
      case AArch64_LD1Threev2d_POST:
2797
6.40k
      case AArch64_LD1Threev2s_POST:
2798
7.35k
      case AArch64_LD1Threev4h_POST:
2799
9.06k
      case AArch64_LD1Threev4s_POST:
2800
9.57k
      case AArch64_LD1Threev8b_POST:
2801
10.0k
      case AArch64_LD1Threev8h_POST:
2802
10.2k
      case AArch64_LD1Twov16b_POST:
2803
10.3k
      case AArch64_LD1Twov1d_POST:
2804
10.4k
      case AArch64_LD1Twov2d_POST:
2805
10.4k
      case AArch64_LD1Twov2s_POST:
2806
11.0k
      case AArch64_LD1Twov4h_POST:
2807
11.1k
      case AArch64_LD1Twov4s_POST:
2808
11.6k
      case AArch64_LD1Twov8b_POST:
2809
11.7k
      case AArch64_LD1Twov8h_POST:
2810
12.0k
      case AArch64_LD1i16_POST:
2811
13.9k
      case AArch64_LD1i32_POST:
2812
14.6k
      case AArch64_LD1i64_POST:
2813
15.8k
      case AArch64_LD1i8_POST:
2814
16.2k
      case AArch64_LD2Rv16b_POST:
2815
16.3k
      case AArch64_LD2Rv1d_POST:
2816
16.4k
      case AArch64_LD2Rv2d_POST:
2817
16.5k
      case AArch64_LD2Rv2s_POST:
2818
16.6k
      case AArch64_LD2Rv4h_POST:
2819
17.0k
      case AArch64_LD2Rv4s_POST:
2820
17.3k
      case AArch64_LD2Rv8b_POST:
2821
17.4k
      case AArch64_LD2Rv8h_POST:
2822
17.5k
      case AArch64_LD2Twov16b_POST:
2823
17.6k
      case AArch64_LD2Twov2d_POST:
2824
17.6k
      case AArch64_LD2Twov2s_POST:
2825
17.8k
      case AArch64_LD2Twov4h_POST:
2826
18.3k
      case AArch64_LD2Twov4s_POST:
2827
18.6k
      case AArch64_LD2Twov8b_POST:
2828
18.6k
      case AArch64_LD2Twov8h_POST:
2829
18.8k
      case AArch64_LD2i16_POST:
2830
19.7k
      case AArch64_LD2i32_POST:
2831
20.9k
      case AArch64_LD2i64_POST:
2832
22.2k
      case AArch64_LD2i8_POST:
2833
22.3k
      case AArch64_LD3Rv16b_POST:
2834
22.4k
      case AArch64_LD3Rv1d_POST:
2835
22.8k
      case AArch64_LD3Rv2d_POST:
2836
22.9k
      case AArch64_LD3Rv2s_POST:
2837
23.0k
      case AArch64_LD3Rv4h_POST:
2838
23.4k
      case AArch64_LD3Rv4s_POST:
2839
23.5k
      case AArch64_LD3Rv8b_POST:
2840
24.4k
      case AArch64_LD3Rv8h_POST:
2841
24.4k
      case AArch64_LD3Threev16b_POST:
2842
24.9k
      case AArch64_LD3Threev2d_POST:
2843
25.5k
      case AArch64_LD3Threev2s_POST:
2844
25.9k
      case AArch64_LD3Threev4h_POST:
2845
26.0k
      case AArch64_LD3Threev4s_POST:
2846
26.1k
      case AArch64_LD3Threev8b_POST:
2847
26.4k
      case AArch64_LD3Threev8h_POST:
2848
27.1k
      case AArch64_LD3i16_POST:
2849
27.8k
      case AArch64_LD3i32_POST:
2850
29.3k
      case AArch64_LD3i64_POST:
2851
29.8k
      case AArch64_LD3i8_POST:
2852
29.9k
      case AArch64_LD4Fourv16b_POST:
2853
30.1k
      case AArch64_LD4Fourv2d_POST:
2854
30.2k
      case AArch64_LD4Fourv2s_POST:
2855
30.4k
      case AArch64_LD4Fourv4h_POST:
2856
30.6k
      case AArch64_LD4Fourv4s_POST:
2857
30.8k
      case AArch64_LD4Fourv8b_POST:
2858
30.9k
      case AArch64_LD4Fourv8h_POST:
2859
30.9k
      case AArch64_LD4Rv16b_POST:
2860
30.9k
      case AArch64_LD4Rv1d_POST:
2861
31.1k
      case AArch64_LD4Rv2d_POST:
2862
31.5k
      case AArch64_LD4Rv2s_POST:
2863
31.7k
      case AArch64_LD4Rv4h_POST:
2864
32.0k
      case AArch64_LD4Rv4s_POST:
2865
32.2k
      case AArch64_LD4Rv8b_POST:
2866
32.2k
      case AArch64_LD4Rv8h_POST:
2867
32.9k
      case AArch64_LD4i16_POST:
2868
33.4k
      case AArch64_LD4i32_POST:
2869
33.6k
      case AArch64_LD4i64_POST:
2870
34.6k
      case AArch64_LD4i8_POST:
2871
34.8k
      case AArch64_LDRBBpost:
2872
34.9k
      case AArch64_LDRBpost:
2873
35.1k
      case AArch64_LDRDpost:
2874
35.3k
      case AArch64_LDRHHpost:
2875
35.3k
      case AArch64_LDRHpost:
2876
35.4k
      case AArch64_LDRQpost:
2877
35.5k
      case AArch64_LDPDpost:
2878
35.6k
      case AArch64_LDPQpost:
2879
35.8k
      case AArch64_LDPSWpost:
2880
35.9k
      case AArch64_LDPSpost:
2881
36.2k
      case AArch64_LDPWpost:
2882
36.6k
      case AArch64_LDPXpost:
2883
36.7k
      case AArch64_ST1Fourv16b_POST:
2884
36.9k
      case AArch64_ST1Fourv1d_POST:
2885
37.0k
      case AArch64_ST1Fourv2d_POST:
2886
37.0k
      case AArch64_ST1Fourv2s_POST:
2887
37.5k
      case AArch64_ST1Fourv4h_POST:
2888
37.5k
      case AArch64_ST1Fourv4s_POST:
2889
37.7k
      case AArch64_ST1Fourv8b_POST:
2890
38.5k
      case AArch64_ST1Fourv8h_POST:
2891
38.5k
      case AArch64_ST1Onev16b_POST:
2892
38.7k
      case AArch64_ST1Onev1d_POST:
2893
38.8k
      case AArch64_ST1Onev2d_POST:
2894
38.9k
      case AArch64_ST1Onev2s_POST:
2895
39.0k
      case AArch64_ST1Onev4h_POST:
2896
39.1k
      case AArch64_ST1Onev4s_POST:
2897
39.5k
      case AArch64_ST1Onev8b_POST:
2898
39.6k
      case AArch64_ST1Onev8h_POST:
2899
40.2k
      case AArch64_ST1Threev16b_POST:
2900
40.3k
      case AArch64_ST1Threev1d_POST:
2901
40.3k
      case AArch64_ST1Threev2d_POST:
2902
40.4k
      case AArch64_ST1Threev2s_POST:
2903
40.6k
      case AArch64_ST1Threev4h_POST:
2904
40.6k
      case AArch64_ST1Threev4s_POST:
2905
40.9k
      case AArch64_ST1Threev8b_POST:
2906
41.5k
      case AArch64_ST1Threev8h_POST:
2907
41.6k
      case AArch64_ST1Twov16b_POST:
2908
41.7k
      case AArch64_ST1Twov1d_POST:
2909
42.2k
      case AArch64_ST1Twov2d_POST:
2910
42.2k
      case AArch64_ST1Twov2s_POST:
2911
42.3k
      case AArch64_ST1Twov4h_POST:
2912
42.3k
      case AArch64_ST1Twov4s_POST:
2913
42.5k
      case AArch64_ST1Twov8b_POST:
2914
42.7k
      case AArch64_ST1Twov8h_POST:
2915
42.9k
      case AArch64_ST1i16_POST:
2916
43.0k
      case AArch64_ST1i32_POST:
2917
43.3k
      case AArch64_ST1i64_POST:
2918
43.9k
      case AArch64_ST1i8_POST:
2919
44.2k
      case AArch64_ST2GPostIndex:
2920
44.4k
      case AArch64_ST2Twov16b_POST:
2921
44.5k
      case AArch64_ST2Twov2d_POST:
2922
45.0k
      case AArch64_ST2Twov2s_POST:
2923
45.3k
      case AArch64_ST2Twov4h_POST:
2924
46.5k
      case AArch64_ST2Twov4s_POST:
2925
46.5k
      case AArch64_ST2Twov8b_POST:
2926
46.6k
      case AArch64_ST2Twov8h_POST:
2927
46.8k
      case AArch64_ST2i16_POST:
2928
47.0k
      case AArch64_ST2i32_POST:
2929
47.3k
      case AArch64_ST2i64_POST:
2930
47.8k
      case AArch64_ST2i8_POST:
2931
48.4k
      case AArch64_ST3Threev16b_POST:
2932
48.5k
      case AArch64_ST3Threev2d_POST:
2933
48.8k
      case AArch64_ST3Threev2s_POST:
2934
48.8k
      case AArch64_ST3Threev4h_POST:
2935
49.3k
      case AArch64_ST3Threev4s_POST:
2936
49.4k
      case AArch64_ST3Threev8b_POST:
2937
49.4k
      case AArch64_ST3Threev8h_POST:
2938
50.2k
      case AArch64_ST3i16_POST:
2939
51.7k
      case AArch64_ST3i32_POST:
2940
52.2k
      case AArch64_ST3i64_POST:
2941
52.5k
      case AArch64_ST3i8_POST:
2942
53.0k
      case AArch64_ST4Fourv16b_POST:
2943
53.8k
      case AArch64_ST4Fourv2d_POST:
2944
53.9k
      case AArch64_ST4Fourv2s_POST:
2945
53.9k
      case AArch64_ST4Fourv4h_POST:
2946
54.6k
      case AArch64_ST4Fourv4s_POST:
2947
54.7k
      case AArch64_ST4Fourv8b_POST:
2948
54.8k
      case AArch64_ST4Fourv8h_POST:
2949
55.5k
      case AArch64_ST4i16_POST:
2950
56.3k
      case AArch64_ST4i32_POST:
2951
56.6k
      case AArch64_ST4i64_POST:
2952
56.8k
      case AArch64_ST4i8_POST:
2953
57.3k
      case AArch64_STPDpost:
2954
57.6k
      case AArch64_STPQpost:
2955
57.9k
      case AArch64_STPSpost:
2956
58.5k
      case AArch64_STPWpost:
2957
59.7k
      case AArch64_STPXpost:
2958
59.8k
      case AArch64_STRBBpost:
2959
59.8k
      case AArch64_STRBpost:
2960
59.9k
      case AArch64_STRDpost:
2961
60.1k
      case AArch64_STRHHpost:
2962
60.2k
      case AArch64_STRHpost:
2963
60.5k
      case AArch64_STRQpost:
2964
60.6k
      case AArch64_STRSpost:
2965
60.6k
      case AArch64_STRWpost:
2966
60.7k
      case AArch64_STRXpost:
2967
61.0k
      case AArch64_STZ2GPostIndex:
2968
61.1k
      case AArch64_STZGPostIndex:
2969
61.1k
      case AArch64_STGPostIndex:
2970
61.1k
      case AArch64_STGPpost:
2971
61.2k
      case AArch64_LDRSBWpost:
2972
61.3k
      case AArch64_LDRSBXpost:
2973
61.5k
      case AArch64_LDRSHWpost:
2974
61.7k
      case AArch64_LDRSHXpost:
2975
61.8k
      case AArch64_LDRSWpost:
2976
61.9k
      case AArch64_LDRSpost:
2977
62.0k
      case AArch64_LDRWpost:
2978
62.1k
      case AArch64_LDRXpost:
2979
62.1k
        flat_insn->detail->arm64.writeback = true;
2980
62.1k
          flat_insn->detail->arm64.post_index = true;
2981
62.1k
        break;
2982
382
      case AArch64_LDRAAwriteback:
2983
1.10k
      case AArch64_LDRABwriteback:
2984
1.27k
      case AArch64_ST2GPreIndex:
2985
1.52k
      case AArch64_LDPDpre:
2986
1.60k
      case AArch64_LDPQpre:
2987
1.69k
      case AArch64_LDPSWpre:
2988
1.79k
      case AArch64_LDPSpre:
2989
1.95k
      case AArch64_LDPWpre:
2990
2.26k
      case AArch64_LDPXpre:
2991
2.55k
      case AArch64_LDRBBpre:
2992
2.64k
      case AArch64_LDRBpre:
2993
2.73k
      case AArch64_LDRDpre:
2994
2.87k
      case AArch64_LDRHHpre:
2995
2.93k
      case AArch64_LDRHpre:
2996
2.96k
      case AArch64_LDRQpre:
2997
3.25k
      case AArch64_LDRSBWpre:
2998
3.29k
      case AArch64_LDRSBXpre:
2999
3.89k
      case AArch64_LDRSHWpre:
3000
3.96k
      case AArch64_LDRSHXpre:
3001
4.00k
      case AArch64_LDRSWpre:
3002
4.02k
      case AArch64_LDRSpre:
3003
4.04k
      case AArch64_LDRWpre:
3004
4.29k
      case AArch64_LDRXpre:
3005
4.53k
      case AArch64_STGPreIndex:
3006
4.66k
      case AArch64_STPDpre:
3007
5.37k
      case AArch64_STPQpre:
3008
5.68k
      case AArch64_STPSpre:
3009
6.05k
      case AArch64_STPWpre:
3010
6.55k
      case AArch64_STPXpre:
3011
6.65k
      case AArch64_STRBBpre:
3012
6.89k
      case AArch64_STRBpre:
3013
6.98k
      case AArch64_STRDpre:
3014
7.41k
      case AArch64_STRHHpre:
3015
7.42k
      case AArch64_STRHpre:
3016
7.66k
      case AArch64_STRQpre:
3017
7.80k
      case AArch64_STRSpre:
3018
7.96k
      case AArch64_STRWpre:
3019
8.10k
      case AArch64_STRXpre:
3020
8.48k
      case AArch64_STZ2GPreIndex:
3021
8.93k
      case AArch64_STZGPreIndex:
3022
8.93k
      case AArch64_STGPpre:
3023
8.93k
        flat_insn->detail->arm64.writeback = true;
3024
8.93k
        break;
3025
346k
    }
3026
346k
  }
3027
346k
}
3028
3029
#endif