Coverage Report

Created: 2025-08-26 06:30

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
43.2k
{
20
43.2k
  static const uint32_t OpInfo[] = {
21
43.2k
    0U, // PHI
22
43.2k
    0U, // INLINEASM
23
43.2k
    0U, // CFI_INSTRUCTION
24
43.2k
    0U, // EH_LABEL
25
43.2k
    0U, // GC_LABEL
26
43.2k
    0U, // KILL
27
43.2k
    0U, // EXTRACT_SUBREG
28
43.2k
    0U, // INSERT_SUBREG
29
43.2k
    0U, // IMPLICIT_DEF
30
43.2k
    0U, // SUBREG_TO_REG
31
43.2k
    0U, // COPY_TO_REGCLASS
32
43.2k
    2452U,  // DBG_VALUE
33
43.2k
    0U, // REG_SEQUENCE
34
43.2k
    0U, // COPY
35
43.2k
    2445U,  // BUNDLE
36
43.2k
    2462U,  // LIFETIME_START
37
43.2k
    2432U,  // LIFETIME_END
38
43.2k
    0U, // STACKMAP
39
43.2k
    0U, // PATCHPOINT
40
43.2k
    0U, // LOAD_STACK_GUARD
41
43.2k
    0U, // STATEPOINT
42
43.2k
    0U, // FRAME_ALLOC
43
43.2k
    4688U,  // ADDCCri
44
43.2k
    4688U,  // ADDCCrr
45
43.2k
    5925U,  // ADDCri
46
43.2k
    5925U,  // ADDCrr
47
43.2k
    4772U,  // ADDEri
48
43.2k
    4772U,  // ADDErr
49
43.2k
    4786U,  // ADDXC
50
43.2k
    4678U,  // ADDXCCC
51
43.2k
    4808U,  // ADDXri
52
43.2k
    4808U,  // ADDXrr
53
43.2k
    4808U,  // ADDri
54
43.2k
    4808U,  // ADDrr
55
43.2k
    74166U, // ADJCALLSTACKDOWN
56
43.2k
    74185U, // ADJCALLSTACKUP
57
43.2k
    5497U,  // ALIGNADDR
58
43.2k
    5127U,  // ALIGNADDRL
59
43.2k
    4695U,  // ANDCCri
60
43.2k
    4695U,  // ANDCCrr
61
43.2k
    4718U,  // ANDNCCri
62
43.2k
    4718U,  // ANDNCCrr
63
43.2k
    5182U,  // ANDNri
64
43.2k
    5182U,  // ANDNrr
65
43.2k
    5182U,  // ANDXNrr
66
43.2k
    4876U,  // ANDXri
67
43.2k
    4876U,  // ANDXrr
68
43.2k
    4876U,  // ANDri
69
43.2k
    4876U,  // ANDrr
70
43.2k
    4502U,  // ARRAY16
71
43.2k
    4255U,  // ARRAY32
72
43.2k
    4526U,  // ARRAY8
73
43.2k
    0U, // ATOMIC_LOAD_ADD_32
74
43.2k
    0U, // ATOMIC_LOAD_ADD_64
75
43.2k
    0U, // ATOMIC_LOAD_AND_32
76
43.2k
    0U, // ATOMIC_LOAD_AND_64
77
43.2k
    0U, // ATOMIC_LOAD_MAX_32
78
43.2k
    0U, // ATOMIC_LOAD_MAX_64
79
43.2k
    0U, // ATOMIC_LOAD_MIN_32
80
43.2k
    0U, // ATOMIC_LOAD_MIN_64
81
43.2k
    0U, // ATOMIC_LOAD_NAND_32
82
43.2k
    0U, // ATOMIC_LOAD_NAND_64
83
43.2k
    0U, // ATOMIC_LOAD_OR_32
84
43.2k
    0U, // ATOMIC_LOAD_OR_64
85
43.2k
    0U, // ATOMIC_LOAD_SUB_32
86
43.2k
    0U, // ATOMIC_LOAD_SUB_64
87
43.2k
    0U, // ATOMIC_LOAD_UMAX_32
88
43.2k
    0U, // ATOMIC_LOAD_UMAX_64
89
43.2k
    0U, // ATOMIC_LOAD_UMIN_32
90
43.2k
    0U, // ATOMIC_LOAD_UMIN_64
91
43.2k
    0U, // ATOMIC_LOAD_XOR_32
92
43.2k
    0U, // ATOMIC_LOAD_XOR_64
93
43.2k
    0U, // ATOMIC_SWAP_64
94
43.2k
    74271U, // BA
95
43.2k
    1194492U, // BCOND
96
43.2k
    1260028U, // BCONDA
97
43.2k
    17659U, // BINDri
98
43.2k
    17659U, // BINDrr
99
43.2k
    5065U,  // BMASK
100
43.2k
    145915U,  // BPFCC
101
43.2k
    211451U,  // BPFCCA
102
43.2k
    276987U,  // BPFCCANT
103
43.2k
    342523U,  // BPFCCNT
104
43.2k
    2106465U, // BPGEZapn
105
43.2k
    2105838U, // BPGEZapt
106
43.2k
    2106532U, // BPGEZnapn
107
43.2k
    2107288U, // BPGEZnapt
108
43.2k
    2106489U, // BPGZapn
109
43.2k
    2105856U, // BPGZapt
110
43.2k
    2106552U, // BPGZnapn
111
43.2k
    2107384U, // BPGZnapt
112
43.2k
    1456636U, // BPICC
113
43.2k
    473596U,  // BPICCA
114
43.2k
    539132U,  // BPICCANT
115
43.2k
    604668U,  // BPICCNT
116
43.2k
    2106477U, // BPLEZapn
117
43.2k
    2105847U, // BPLEZapt
118
43.2k
    2106542U, // BPLEZnapn
119
43.2k
    2107337U, // BPLEZnapt
120
43.2k
    2106500U, // BPLZapn
121
43.2k
    2105864U, // BPLZapt
122
43.2k
    2106561U, // BPLZnapn
123
43.2k
    2107428U, // BPLZnapt
124
43.2k
    2106511U, // BPNZapn
125
43.2k
    2105872U, // BPNZapt
126
43.2k
    2106570U, // BPNZnapn
127
43.2k
    2107472U, // BPNZnapt
128
43.2k
    1718780U, // BPXCC
129
43.2k
    735740U,  // BPXCCA
130
43.2k
    801276U,  // BPXCCANT
131
43.2k
    866812U,  // BPXCCNT
132
43.2k
    2106522U, // BPZapn
133
43.2k
    2105880U, // BPZapt
134
43.2k
    2106579U, // BPZnapn
135
43.2k
    2107505U, // BPZnapt
136
43.2k
    4983U,  // BSHUFFLE
137
43.2k
    74742U, // CALL
138
43.2k
    17398U, // CALLri
139
43.2k
    17398U, // CALLrr
140
43.2k
    924148U,  // CASXrr
141
43.2k
    924129U,  // CASrr
142
43.2k
    74001U, // CMASK16
143
43.2k
    73833U, // CMASK32
144
43.2k
    74150U, // CMASK8
145
43.2k
    2106607U, // CMPri
146
43.2k
    2106607U, // CMPrr
147
43.2k
    4332U,  // EDGE16
148
43.2k
    5081U,  // EDGE16L
149
43.2k
    5198U,  // EDGE16LN
150
43.2k
    5165U,  // EDGE16N
151
43.2k
    4164U,  // EDGE32
152
43.2k
    5072U,  // EDGE32L
153
43.2k
    5188U,  // EDGE32LN
154
43.2k
    5156U,  // EDGE32N
155
43.2k
    4511U,  // EDGE8
156
43.2k
    5090U,  // EDGE8L
157
43.2k
    5208U,  // EDGE8LN
158
43.2k
    5174U,  // EDGE8N
159
43.2k
    1053516U, // FABSD
160
43.2k
    1054031U, // FABSQ
161
43.2k
    1054376U, // FABSS
162
43.2k
    4813U,  // FADDD
163
43.2k
    5383U,  // FADDQ
164
43.2k
    5645U,  // FADDS
165
43.2k
    4648U,  // FALIGNADATA
166
43.2k
    4875U,  // FAND
167
43.2k
    4112U,  // FANDNOT1
168
43.2k
    5544U,  // FANDNOT1S
169
43.2k
    4271U,  // FANDNOT2
170
43.2k
    5591U,  // FANDNOT2S
171
43.2k
    5677U,  // FANDS
172
43.2k
    1194491U, // FBCOND
173
43.2k
    1260027U, // FBCONDA
174
43.2k
    4394U,  // FCHKSM16
175
43.2k
    2106173U, // FCMPD
176
43.2k
    4413U,  // FCMPEQ16
177
43.2k
    4226U,  // FCMPEQ32
178
43.2k
    4432U,  // FCMPGT16
179
43.2k
    4245U,  // FCMPGT32
180
43.2k
    4340U,  // FCMPLE16
181
43.2k
    4172U,  // FCMPLE32
182
43.2k
    4350U,  // FCMPNE16
183
43.2k
    4182U,  // FCMPNE32
184
43.2k
    2106696U, // FCMPQ
185
43.2k
    2107005U, // FCMPS
186
43.2k
    4960U,  // FDIVD
187
43.2k
    5475U,  // FDIVQ
188
43.2k
    5815U,  // FDIVS
189
43.2k
    5405U,  // FDMULQ
190
43.2k
    1053620U, // FDTOI
191
43.2k
    1053996U, // FDTOQ
192
43.2k
    1054305U, // FDTOS
193
43.2k
    1054536U, // FDTOX
194
43.2k
    1053464U, // FEXPAND
195
43.2k
    4820U,  // FHADDD
196
43.2k
    5652U,  // FHADDS
197
43.2k
    4800U,  // FHSUBD
198
43.2k
    5637U,  // FHSUBS
199
43.2k
    1053473U, // FITOD
200
43.2k
    1054003U, // FITOQ
201
43.2k
    1054312U, // FITOS
202
43.2k
    6300484U, // FLCMPD
203
43.2k
    6301316U, // FLCMPS
204
43.2k
    2606U,  // FLUSHW
205
43.2k
    4404U,  // FMEAN16
206
43.2k
    1053543U, // FMOVD
207
43.2k
    1006078U, // FMOVD_FCC
208
43.2k
    23484926U,  // FMOVD_ICC
209
43.2k
    23747070U,  // FMOVD_XCC
210
43.2k
    1054058U, // FMOVQ
211
43.2k
    1006102U, // FMOVQ_FCC
212
43.2k
    23484950U,  // FMOVQ_ICC
213
43.2k
    23747094U,  // FMOVQ_XCC
214
43.2k
    6018U,  // FMOVRGEZD
215
43.2k
    6029U,  // FMOVRGEZQ
216
43.2k
    6056U,  // FMOVRGEZS
217
43.2k
    6116U,  // FMOVRGZD
218
43.2k
    6126U,  // FMOVRGZQ
219
43.2k
    6150U,  // FMOVRGZS
220
43.2k
    6067U,  // FMOVRLEZD
221
43.2k
    6078U,  // FMOVRLEZQ
222
43.2k
    6105U,  // FMOVRLEZS
223
43.2k
    6160U,  // FMOVRLZD
224
43.2k
    6170U,  // FMOVRLZQ
225
43.2k
    6194U,  // FMOVRLZS
226
43.2k
    6204U,  // FMOVRNZD
227
43.2k
    6214U,  // FMOVRNZQ
228
43.2k
    6238U,  // FMOVRNZS
229
43.2k
    6009U,  // FMOVRZD
230
43.2k
    6248U,  // FMOVRZQ
231
43.2k
    6269U,  // FMOVRZS
232
43.2k
    1054398U, // FMOVS
233
43.2k
    1006114U, // FMOVS_FCC
234
43.2k
    23484962U,  // FMOVS_ICC
235
43.2k
    23747106U,  // FMOVS_XCC
236
43.2k
    4490U,  // FMUL8SUX16
237
43.2k
    4465U,  // FMUL8ULX16
238
43.2k
    4442U,  // FMUL8X16
239
43.2k
    5098U,  // FMUL8X16AL
240
43.2k
    5849U,  // FMUL8X16AU
241
43.2k
    4860U,  // FMULD
242
43.2k
    4477U,  // FMULD8SUX16
243
43.2k
    4452U,  // FMULD8ULX16
244
43.2k
    5413U,  // FMULQ
245
43.2k
    5714U,  // FMULS
246
43.2k
    4837U,  // FNADDD
247
43.2k
    5669U,  // FNADDS
248
43.2k
    4881U,  // FNAND
249
43.2k
    5684U,  // FNANDS
250
43.2k
    1053429U, // FNEGD
251
43.2k
    1053974U, // FNEGQ
252
43.2k
    1054283U, // FNEGS
253
43.2k
    4828U,  // FNHADDD
254
43.2k
    5660U,  // FNHADDS
255
43.2k
    4828U,  // FNMULD
256
43.2k
    5660U,  // FNMULS
257
43.2k
    5513U,  // FNOR
258
43.2k
    5778U,  // FNORS
259
43.2k
    1052698U, // FNOT1
260
43.2k
    1054131U, // FNOT1S
261
43.2k
    1052857U, // FNOT2
262
43.2k
    1054178U, // FNOT2S
263
43.2k
    5660U,  // FNSMULD
264
43.2k
    74625U, // FONE
265
43.2k
    75324U, // FONES
266
43.2k
    5508U,  // FOR
267
43.2k
    4129U,  // FORNOT1
268
43.2k
    5563U,  // FORNOT1S
269
43.2k
    4288U,  // FORNOT2
270
43.2k
    5610U,  // FORNOT2S
271
43.2k
    5772U,  // FORS
272
43.2k
    1052936U, // FPACK16
273
43.2k
    4192U,  // FPACK32
274
43.2k
    1054507U, // FPACKFIX
275
43.2k
    4323U,  // FPADD16
276
43.2k
    5620U,  // FPADD16S
277
43.2k
    4155U,  // FPADD32
278
43.2k
    5573U,  // FPADD32S
279
43.2k
    4297U,  // FPADD64
280
43.2k
    4974U,  // FPMERGE
281
43.2k
    4314U,  // FPSUB16
282
43.2k
    4580U,  // FPSUB16S
283
43.2k
    4146U,  // FPSUB32
284
43.2k
    4570U,  // FPSUB32S
285
43.2k
    1053480U, // FQTOD
286
43.2k
    1053627U, // FQTOI
287
43.2k
    1054319U, // FQTOS
288
43.2k
    1054552U, // FQTOX
289
43.2k
    4423U,  // FSLAS16
290
43.2k
    4236U,  // FSLAS32
291
43.2k
    4378U,  // FSLL16
292
43.2k
    4210U,  // FSLL32
293
43.2k
    4867U,  // FSMULD
294
43.2k
    1053523U, // FSQRTD
295
43.2k
    1054038U, // FSQRTQ
296
43.2k
    1054383U, // FSQRTS
297
43.2k
    4306U,  // FSRA16
298
43.2k
    4138U,  // FSRA32
299
43.2k
    1052681U, // FSRC1
300
43.2k
    1054112U, // FSRC1S
301
43.2k
    1052840U, // FSRC2
302
43.2k
    1054159U, // FSRC2S
303
43.2k
    4386U,  // FSRL16
304
43.2k
    4218U,  // FSRL32
305
43.2k
    1053487U, // FSTOD
306
43.2k
    1053634U, // FSTOI
307
43.2k
    1054010U, // FSTOQ
308
43.2k
    1054559U, // FSTOX
309
43.2k
    4793U,  // FSUBD
310
43.2k
    5376U,  // FSUBQ
311
43.2k
    5630U,  // FSUBS
312
43.2k
    5519U,  // FXNOR
313
43.2k
    5785U,  // FXNORS
314
43.2k
    5526U,  // FXOR
315
43.2k
    5793U,  // FXORS
316
43.2k
    1053494U, // FXTOD
317
43.2k
    1054017U, // FXTOQ
318
43.2k
    1054326U, // FXTOS
319
43.2k
    74984U, // FZERO
320
43.2k
    75353U, // FZEROS
321
43.2k
    24584U, // GETPCX
322
43.2k
    1078273U, // JMPLri
323
43.2k
    1078273U, // JMPLrr
324
43.2k
    1997243U, // LDDFri
325
43.2k
    1997243U, // LDDFrr
326
43.2k
    1997249U, // LDFri
327
43.2k
    1997249U, // LDFrr
328
43.2k
    1997275U, // LDQFri
329
43.2k
    1997275U, // LDQFrr
330
43.2k
    1997229U, // LDSBri
331
43.2k
    1997229U, // LDSBrr
332
43.2k
    1997254U, // LDSHri
333
43.2k
    1997254U, // LDSHrr
334
43.2k
    1997287U, // LDSWri
335
43.2k
    1997287U, // LDSWrr
336
43.2k
    1997236U, // LDUBri
337
43.2k
    1997236U, // LDUBrr
338
43.2k
    1997261U, // LDUHri
339
43.2k
    1997261U, // LDUHrr
340
43.2k
    1997294U, // LDXri
341
43.2k
    1997294U, // LDXrr
342
43.2k
    1997249U, // LDri
343
43.2k
    1997249U, // LDrr
344
43.2k
    33480U, // LEAX_ADDri
345
43.2k
    33480U, // LEA_ADDri
346
43.2k
    1054405U, // LZCNT
347
43.2k
    75121U, // MEMBARi
348
43.2k
    1054543U, // MOVDTOX
349
43.2k
    1006122U, // MOVFCCri
350
43.2k
    1006122U, // MOVFCCrr
351
43.2k
    23484970U,  // MOVICCri
352
43.2k
    23484970U,  // MOVICCrr
353
43.2k
    6047U,  // MOVRGEZri
354
43.2k
    6047U,  // MOVRGEZrr
355
43.2k
    6142U,  // MOVRGZri
356
43.2k
    6142U,  // MOVRGZrr
357
43.2k
    6096U,  // MOVRLEZri
358
43.2k
    6096U,  // MOVRLEZrr
359
43.2k
    6186U,  // MOVRLZri
360
43.2k
    6186U,  // MOVRLZrr
361
43.2k
    6230U,  // MOVRNZri
362
43.2k
    6230U,  // MOVRNZrr
363
43.2k
    6262U,  // MOVRRZri
364
43.2k
    6262U,  // MOVRRZrr
365
43.2k
    1054469U, // MOVSTOSW
366
43.2k
    1054479U, // MOVSTOUW
367
43.2k
    1054543U, // MOVWTOS
368
43.2k
    23747114U,  // MOVXCCri
369
43.2k
    23747114U,  // MOVXCCrr
370
43.2k
    1054543U, // MOVXTOD
371
43.2k
    5954U,  // MULXri
372
43.2k
    5954U,  // MULXrr
373
43.2k
    2578U,  // NOP
374
43.2k
    4735U,  // ORCCri
375
43.2k
    4735U,  // ORCCrr
376
43.2k
    4726U,  // ORNCCri
377
43.2k
    4726U,  // ORNCCrr
378
43.2k
    5339U,  // ORNri
379
43.2k
    5339U,  // ORNrr
380
43.2k
    5339U,  // ORXNrr
381
43.2k
    5509U,  // ORXri
382
43.2k
    5509U,  // ORXrr
383
43.2k
    5509U,  // ORri
384
43.2k
    5509U,  // ORrr
385
43.2k
    5836U,  // PDIST
386
43.2k
    5344U,  // PDISTN
387
43.2k
    1053356U, // POPCrr
388
43.2k
    73729U, // RDY
389
43.2k
    4999U,  // RESTOREri
390
43.2k
    4999U,  // RESTORErr
391
43.2k
    76132U, // RET
392
43.2k
    76141U, // RETL
393
43.2k
    18131U, // RETTri
394
43.2k
    18131U, // RETTrr
395
43.2k
    5008U,  // SAVEri
396
43.2k
    5008U,  // SAVErr
397
43.2k
    4748U,  // SDIVCCri
398
43.2k
    4748U,  // SDIVCCrr
399
43.2k
    5995U,  // SDIVXri
400
43.2k
    5995U,  // SDIVXrr
401
43.2k
    5861U,  // SDIVri
402
43.2k
    5861U,  // SDIVrr
403
43.2k
    2182U,  // SELECT_CC_DFP_FCC
404
43.2k
    2293U,  // SELECT_CC_DFP_ICC
405
43.2k
    2238U,  // SELECT_CC_FP_FCC
406
43.2k
    2349U,  // SELECT_CC_FP_ICC
407
43.2k
    2265U,  // SELECT_CC_Int_FCC
408
43.2k
    2376U,  // SELECT_CC_Int_ICC
409
43.2k
    2210U,  // SELECT_CC_QFP_FCC
410
43.2k
    2321U,  // SELECT_CC_QFP_ICC
411
43.2k
    1053595U, // SETHIXi
412
43.2k
    1053595U, // SETHIi
413
43.2k
    2569U,  // SHUTDOWN
414
43.2k
    2564U,  // SIAM
415
43.2k
    5941U,  // SLLXri
416
43.2k
    5941U,  // SLLXrr
417
43.2k
    5116U,  // SLLri
418
43.2k
    5116U,  // SLLrr
419
43.2k
    4702U,  // SMULCCri
420
43.2k
    4702U,  // SMULCCrr
421
43.2k
    5144U,  // SMULri
422
43.2k
    5144U,  // SMULrr
423
43.2k
    5913U,  // SRAXri
424
43.2k
    5913U,  // SRAXrr
425
43.2k
    4643U,  // SRAri
426
43.2k
    4643U,  // SRArr
427
43.2k
    5947U,  // SRLXri
428
43.2k
    5947U,  // SRLXrr
429
43.2k
    5139U,  // SRLri
430
43.2k
    5139U,  // SRLrr
431
43.2k
    2588U,  // STBAR
432
43.2k
    37428U, // STBri
433
43.2k
    37428U, // STBrr
434
43.2k
    37723U, // STDFri
435
43.2k
    37723U, // STDFrr
436
43.2k
    38607U, // STFri
437
43.2k
    38607U, // STFrr
438
43.2k
    37782U, // STHri
439
43.2k
    37782U, // STHrr
440
43.2k
    38238U, // STQFri
441
43.2k
    38238U, // STQFrr
442
43.2k
    38758U, // STXri
443
43.2k
    38758U, // STXrr
444
43.2k
    38607U, // STri
445
43.2k
    38607U, // STrr
446
43.2k
    4671U,  // SUBCCri
447
43.2k
    4671U,  // SUBCCrr
448
43.2k
    5919U,  // SUBCri
449
43.2k
    5919U,  // SUBCrr
450
43.2k
    4764U,  // SUBEri
451
43.2k
    4764U,  // SUBErr
452
43.2k
    4665U,  // SUBXri
453
43.2k
    4665U,  // SUBXrr
454
43.2k
    4665U,  // SUBri
455
43.2k
    4665U,  // SUBrr
456
43.2k
    1997268U, // SWAPri
457
43.2k
    1997268U, // SWAPrr
458
43.2k
    2422U,  // TA3
459
43.2k
    2427U,  // TA5
460
43.2k
    5883U,  // TADDCCTVri
461
43.2k
    5883U,  // TADDCCTVrr
462
43.2k
    4687U,  // TADDCCri
463
43.2k
    4687U,  // TADDCCrr
464
43.2k
    9873960U, // TICCri
465
43.2k
    9873960U, // TICCrr
466
43.2k
    37753544U,  // TLS_ADDXrr
467
43.2k
    37753544U,  // TLS_ADDrr
468
43.2k
    2106358U, // TLS_CALL
469
43.2k
    39746030U,  // TLS_LDXrr
470
43.2k
    39745985U,  // TLS_LDrr
471
43.2k
    5873U,  // TSUBCCTVri
472
43.2k
    5873U,  // TSUBCCTVrr
473
43.2k
    4670U,  // TSUBCCri
474
43.2k
    4670U,  // TSUBCCrr
475
43.2k
    10136104U,  // TXCCri
476
43.2k
    10136104U,  // TXCCrr
477
43.2k
    4756U,  // UDIVCCri
478
43.2k
    4756U,  // UDIVCCrr
479
43.2k
    6002U,  // UDIVXri
480
43.2k
    6002U,  // UDIVXrr
481
43.2k
    5867U,  // UDIVri
482
43.2k
    5867U,  // UDIVrr
483
43.2k
    4710U,  // UMULCCri
484
43.2k
    4710U,  // UMULCCrr
485
43.2k
    5026U,  // UMULXHI
486
43.2k
    5150U,  // UMULri
487
43.2k
    5150U,  // UMULrr
488
43.2k
    74996U, // UNIMP
489
43.2k
    6300477U, // V9FCMPD
490
43.2k
    6300397U, // V9FCMPED
491
43.2k
    6300942U, // V9FCMPEQ
492
43.2k
    6301251U, // V9FCMPES
493
43.2k
    6301000U, // V9FCMPQ
494
43.2k
    6301309U, // V9FCMPS
495
43.2k
    47614U, // V9FMOVD_FCC
496
43.2k
    47638U, // V9FMOVQ_FCC
497
43.2k
    47650U, // V9FMOVS_FCC
498
43.2k
    47658U, // V9MOVFCCri
499
43.2k
    47658U, // V9MOVFCCrr
500
43.2k
    14689692U,  // WRYri
501
43.2k
    14689692U,  // WRYrr
502
43.2k
    5953U,  // XMULX
503
43.2k
    5035U,  // XMULXHI
504
43.2k
    4733U,  // XNORCCri
505
43.2k
    4733U,  // XNORCCrr
506
43.2k
    5520U,  // XNORXrr
507
43.2k
    5520U,  // XNORri
508
43.2k
    5520U,  // XNORrr
509
43.2k
    4741U,  // XORCCri
510
43.2k
    4741U,  // XORCCrr
511
43.2k
    5527U,  // XORXri
512
43.2k
    5527U,  // XORXrr
513
43.2k
    5527U,  // XORri
514
43.2k
    5527U,  // XORrr
515
43.2k
    0U
516
43.2k
  };
517
518
43.2k
#ifndef CAPSTONE_DIET
519
43.2k
  static const char AsmStrs[] = {
520
43.2k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
43.2k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
43.2k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
43.2k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
43.2k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
43.2k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
43.2k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
43.2k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
43.2k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
43.2k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
43.2k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
43.2k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
43.2k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
43.2k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
43.2k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
43.2k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
43.2k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
43.2k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
43.2k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
43.2k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
43.2k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
43.2k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
43.2k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
43.2k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
43.2k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
43.2k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
43.2k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
43.2k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
43.2k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
43.2k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
43.2k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
43.2k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
43.2k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
43.2k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
43.2k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
43.2k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
43.2k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
43.2k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
43.2k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
43.2k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
43.2k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
43.2k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
43.2k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
43.2k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
43.2k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
43.2k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
43.2k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
43.2k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
43.2k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
43.2k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
43.2k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
43.2k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
43.2k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
43.2k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
43.2k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
43.2k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
43.2k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
43.2k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
43.2k
  /* 542 */ 'b', 'a', 32, 0,
579
43.2k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
43.2k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
43.2k
  /* 563 */ 's', 't', 'b', 32, 0,
582
43.2k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
43.2k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
43.2k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
43.2k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
43.2k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
43.2k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
43.2k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
43.2k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
43.2k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
43.2k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
43.2k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
43.2k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
43.2k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
43.2k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
43.2k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
43.2k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
43.2k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
43.2k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
43.2k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
43.2k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
43.2k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
43.2k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
43.2k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
43.2k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
43.2k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
43.2k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
43.2k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
43.2k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
43.2k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
43.2k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
43.2k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
43.2k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
43.2k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
43.2k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
43.2k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
43.2k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
43.2k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
43.2k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
43.2k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
43.2k
  /* 858 */ 's', 't', 'd', 32, 0,
622
43.2k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
43.2k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
43.2k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
43.2k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
43.2k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
43.2k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
43.2k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
43.2k
  /* 917 */ 's', 't', 'h', 32, 0,
630
43.2k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
43.2k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
43.2k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
43.2k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
43.2k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
43.2k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
43.2k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
43.2k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
43.2k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
43.2k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
43.2k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
43.2k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
43.2k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
43.2k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
43.2k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
43.2k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
43.2k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
43.2k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
43.2k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
43.2k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
43.2k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
43.2k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
43.2k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
43.2k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
43.2k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
43.2k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
43.2k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
43.2k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
43.2k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
43.2k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
43.2k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
43.2k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
43.2k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
43.2k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
43.2k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
43.2k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
43.2k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
43.2k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
43.2k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
43.2k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
43.2k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
43.2k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
43.2k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
43.2k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
43.2k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
43.2k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
43.2k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
43.2k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
43.2k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
43.2k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
43.2k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
43.2k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
43.2k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
43.2k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
43.2k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
43.2k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
43.2k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
43.2k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
43.2k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
43.2k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
43.2k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
43.2k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
43.2k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
43.2k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
43.2k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
43.2k
  /* 1435 */ 'w', 'r', 32, 0,
696
43.2k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
43.2k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
43.2k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
43.2k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
43.2k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
43.2k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
43.2k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
43.2k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
43.2k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
43.2k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
43.2k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
43.2k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
43.2k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
43.2k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
43.2k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
43.2k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
43.2k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
43.2k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
43.2k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
43.2k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
43.2k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
43.2k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
43.2k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
43.2k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
43.2k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
43.2k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
43.2k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
43.2k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
43.2k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
43.2k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
43.2k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
43.2k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
43.2k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
43.2k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
43.2k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
43.2k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
43.2k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
43.2k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
43.2k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
43.2k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
43.2k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
43.2k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
43.2k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
43.2k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
43.2k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
43.2k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
43.2k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
43.2k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
43.2k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
43.2k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
43.2k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
43.2k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
43.2k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
43.2k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
43.2k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
43.2k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
43.2k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
43.2k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
43.2k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
43.2k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
43.2k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
43.2k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
43.2k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
43.2k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
43.2k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
43.2k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
43.2k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
43.2k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
43.2k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
43.2k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
43.2k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
43.2k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
43.2k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
43.2k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
43.2k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
43.2k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
43.2k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
43.2k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
43.2k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
43.2k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
43.2k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
43.2k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
43.2k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
43.2k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
43.2k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
43.2k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
43.2k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
43.2k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
43.2k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
43.2k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
43.2k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
43.2k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
43.2k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
43.2k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
43.2k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
43.2k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
43.2k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
43.2k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
43.2k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
43.2k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
43.2k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
43.2k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
43.2k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
43.2k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
43.2k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
43.2k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
43.2k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
43.2k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
43.2k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
43.2k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
43.2k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
43.2k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
43.2k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
43.2k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
43.2k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
43.2k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
43.2k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
43.2k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
43.2k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
43.2k
  /* 2554 */ 'f', 'b', 0,
816
43.2k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
43.2k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
43.2k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
43.2k
  /* 2577 */ 'n', 'o', 'p', 0,
820
43.2k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
43.2k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
43.2k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
43.2k
  /* 2599 */ 't', 0,
824
43.2k
  /* 2601 */ 'm', 'o', 'v', 0,
825
43.2k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
43.2k
  };
827
43.2k
#endif
828
829
  // Emit the opcode for the instruction.
830
43.2k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
43.2k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
43.2k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
43.2k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
43.2k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
220
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
220
    return;
844
0
    break;
845
7.12k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
7.12k
    printOperand(MI, 1, O); 
848
7.12k
    break;
849
23.5k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
23.5k
    printOperand(MI, 0, O); 
852
23.5k
    break;
853
3.62k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.62k
    printCCOperand(MI, 1, O); 
856
3.62k
    break;
857
153
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
153
    printMemOperand(MI, 0, O, NULL); 
860
153
    return;
861
0
    break;
862
2.87k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.87k
    printCCOperand(MI, 3, O); 
865
2.87k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.57k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.57k
    printMemOperand(MI, 1, O, NULL); 
874
2.57k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.26k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.26k
    printOperand(MI, 2, O); 
885
1.26k
    SStream_concat0(O, ", ["); 
886
1.26k
    printMemOperand(MI, 0, O, NULL); 
887
1.26k
    SStream_concat0(O, "]"); 
888
1.26k
    return;
889
0
    break;
890
531
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
531
    printCCOperand(MI, 2, O); 
893
531
    break;
894
1.39k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.39k
    printCCOperand(MI, 4, O); 
897
1.39k
    SStream_concat0(O, " "); 
898
1.39k
    printOperand(MI, 1, O); 
899
1.39k
    SStream_concat0(O, ", "); 
900
1.39k
    printOperand(MI, 2, O); 
901
1.39k
    SStream_concat0(O, ", "); 
902
1.39k
    printOperand(MI, 0, O); 
903
1.39k
    return;
904
0
    break;
905
43.2k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
40.2k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
12.7k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
12.7k
    SStream_concat0(O, ", "); 
915
12.7k
    break;
916
18.0k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
18.0k
    return;
919
0
    break;
920
1.23k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.23k
    SStream_concat0(O, " "); 
923
1.23k
    break;
924
982
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
982
    SStream_concat0(O, ",a ");
927
982
  Sparc_add_hint(MI, SPARC_HINT_A);
928
982
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
2.12k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
2.12k
    SStream_concat0(O, " %icc, ");
950
2.12k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
2.12k
    break;
952
329
  case 7:
953
    // BPICCA
954
329
    SStream_concat0(O, ",a %icc, ");
955
329
  Sparc_add_hint(MI, SPARC_HINT_A);
956
329
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
329
    printOperand(MI, 0, O); 
958
329
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.06k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.06k
    SStream_concat0(O, " %xcc, ");
979
1.06k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.06k
    break;
981
378
  case 11:
982
    // BPXCCA
983
378
    SStream_concat0(O, ",a %xcc, ");
984
378
  Sparc_add_hint(MI, SPARC_HINT_A);
985
378
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
378
    printOperand(MI, 0, O); 
987
378
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.45k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.45k
    SStream_concat0(O, "], "); 
1008
2.45k
    break;
1009
920
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
920
    SStream_concat0(O, " %fcc0, ");
1012
920
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
920
    printOperand(MI, 1, O); 
1014
920
    SStream_concat0(O, ", "); 
1015
920
    printOperand(MI, 0, O); 
1016
920
    return;
1017
0
    break;
1018
40.2k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
20.5k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.46k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.46k
    printOperand(MI, 2, O); 
1028
5.46k
    SStream_concat0(O, ", "); 
1029
5.46k
    printOperand(MI, 0, O); 
1030
5.46k
    break;
1031
7.67k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
7.67k
    printOperand(MI, 0, O); 
1034
7.67k
    break;
1035
7.42k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
7.42k
    printOperand(MI, 1, O); 
1038
7.42k
    break;
1039
20.5k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
20.5k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
16.6k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
16.6k
    return;
1049
0
    break;
1050
3.06k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
3.06k
    SStream_concat0(O, ", "); 
1053
3.06k
    break;
1054
531
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
531
    SStream_concat0(O, " + ");  // qq
1057
531
    printOperand(MI, 1, O); 
1058
531
    return;
1059
0
    break;
1060
283
  case 3:
1061
    // WRYri, WRYrr
1062
283
    SStream_concat0(O, ", %y");
1063
283
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
283
    return;
1065
0
    break;
1066
20.5k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
3.06k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.10k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.10k
    printOperand(MI, 2, O); 
1076
1.10k
    return;
1077
0
    break;
1078
1.95k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.95k
    printOperand(MI, 0, O); 
1081
1.95k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
3.06k
  }
1089
3.06k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
63.7k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
63.7k
#ifndef CAPSTONE_DIET
1100
63.7k
  static const char AsmStrs[] = {
1101
63.7k
  /* 0 */ 'f', '1', '0', 0,
1102
63.7k
  /* 4 */ 'f', '2', '0', 0,
1103
63.7k
  /* 8 */ 'f', '3', '0', 0,
1104
63.7k
  /* 12 */ 'f', '4', '0', 0,
1105
63.7k
  /* 16 */ 'f', '5', '0', 0,
1106
63.7k
  /* 20 */ 'f', '6', '0', 0,
1107
63.7k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
63.7k
  /* 29 */ 'f', '0', 0,
1109
63.7k
  /* 32 */ 'g', '0', 0,
1110
63.7k
  /* 35 */ 'i', '0', 0,
1111
63.7k
  /* 38 */ 'l', '0', 0,
1112
63.7k
  /* 41 */ 'o', '0', 0,
1113
63.7k
  /* 44 */ 'f', '1', '1', 0,
1114
63.7k
  /* 48 */ 'f', '2', '1', 0,
1115
63.7k
  /* 52 */ 'f', '3', '1', 0,
1116
63.7k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
63.7k
  /* 61 */ 'f', '1', 0,
1118
63.7k
  /* 64 */ 'g', '1', 0,
1119
63.7k
  /* 67 */ 'i', '1', 0,
1120
63.7k
  /* 70 */ 'l', '1', 0,
1121
63.7k
  /* 73 */ 'o', '1', 0,
1122
63.7k
  /* 76 */ 'f', '1', '2', 0,
1123
63.7k
  /* 80 */ 'f', '2', '2', 0,
1124
63.7k
  /* 84 */ 'f', '3', '2', 0,
1125
63.7k
  /* 88 */ 'f', '4', '2', 0,
1126
63.7k
  /* 92 */ 'f', '5', '2', 0,
1127
63.7k
  /* 96 */ 'f', '6', '2', 0,
1128
63.7k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
63.7k
  /* 105 */ 'f', '2', 0,
1130
63.7k
  /* 108 */ 'g', '2', 0,
1131
63.7k
  /* 111 */ 'i', '2', 0,
1132
63.7k
  /* 114 */ 'l', '2', 0,
1133
63.7k
  /* 117 */ 'o', '2', 0,
1134
63.7k
  /* 120 */ 'f', '1', '3', 0,
1135
63.7k
  /* 124 */ 'f', '2', '3', 0,
1136
63.7k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
63.7k
  /* 133 */ 'f', '3', 0,
1138
63.7k
  /* 136 */ 'g', '3', 0,
1139
63.7k
  /* 139 */ 'i', '3', 0,
1140
63.7k
  /* 142 */ 'l', '3', 0,
1141
63.7k
  /* 145 */ 'o', '3', 0,
1142
63.7k
  /* 148 */ 'f', '1', '4', 0,
1143
63.7k
  /* 152 */ 'f', '2', '4', 0,
1144
63.7k
  /* 156 */ 'f', '3', '4', 0,
1145
63.7k
  /* 160 */ 'f', '4', '4', 0,
1146
63.7k
  /* 164 */ 'f', '5', '4', 0,
1147
63.7k
  /* 168 */ 'f', '4', 0,
1148
63.7k
  /* 171 */ 'g', '4', 0,
1149
63.7k
  /* 174 */ 'i', '4', 0,
1150
63.7k
  /* 177 */ 'l', '4', 0,
1151
63.7k
  /* 180 */ 'o', '4', 0,
1152
63.7k
  /* 183 */ 'f', '1', '5', 0,
1153
63.7k
  /* 187 */ 'f', '2', '5', 0,
1154
63.7k
  /* 191 */ 'f', '5', 0,
1155
63.7k
  /* 194 */ 'g', '5', 0,
1156
63.7k
  /* 197 */ 'i', '5', 0,
1157
63.7k
  /* 200 */ 'l', '5', 0,
1158
63.7k
  /* 203 */ 'o', '5', 0,
1159
63.7k
  /* 206 */ 'f', '1', '6', 0,
1160
63.7k
  /* 210 */ 'f', '2', '6', 0,
1161
63.7k
  /* 214 */ 'f', '3', '6', 0,
1162
63.7k
  /* 218 */ 'f', '4', '6', 0,
1163
63.7k
  /* 222 */ 'f', '5', '6', 0,
1164
63.7k
  /* 226 */ 'f', '6', 0,
1165
63.7k
  /* 229 */ 'g', '6', 0,
1166
63.7k
  /* 232 */ 'l', '6', 0,
1167
63.7k
  /* 235 */ 'f', '1', '7', 0,
1168
63.7k
  /* 239 */ 'f', '2', '7', 0,
1169
63.7k
  /* 243 */ 'f', '7', 0,
1170
63.7k
  /* 246 */ 'g', '7', 0,
1171
63.7k
  /* 249 */ 'i', '7', 0,
1172
63.7k
  /* 252 */ 'l', '7', 0,
1173
63.7k
  /* 255 */ 'o', '7', 0,
1174
63.7k
  /* 258 */ 'f', '1', '8', 0,
1175
63.7k
  /* 262 */ 'f', '2', '8', 0,
1176
63.7k
  /* 266 */ 'f', '3', '8', 0,
1177
63.7k
  /* 270 */ 'f', '4', '8', 0,
1178
63.7k
  /* 274 */ 'f', '5', '8', 0,
1179
63.7k
  /* 278 */ 'f', '8', 0,
1180
63.7k
  /* 281 */ 'f', '1', '9', 0,
1181
63.7k
  /* 285 */ 'f', '2', '9', 0,
1182
63.7k
  /* 289 */ 'f', '9', 0,
1183
63.7k
  /* 292 */ 'i', 'c', 'c', 0,
1184
63.7k
  /* 296 */ 'f', 'p', 0,
1185
63.7k
  /* 299 */ 's', 'p', 0,
1186
63.7k
  /* 302 */ 'y', 0,
1187
63.7k
  };
1188
1189
63.7k
  static const uint16_t RegAsmOffset[] = {
1190
63.7k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
63.7k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
63.7k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
63.7k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
63.7k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
63.7k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
63.7k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
63.7k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
63.7k
    12, 160, 270, 92, 222, 20, 
1199
63.7k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
63.7k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
63.7k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
78.5k
{
1221
396k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
78.5k
  const char *AsmString;
1223
78.5k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
78.5k
  int OpIdx, PrintMethodIdx;
1225
78.5k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
78.5k
  switch (MCInst_getOpcode(MI)) {
1227
38.9k
  default: return NULL;
1228
3.49k
  case SP_BCOND:
1229
3.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
3.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
595
      AsmString = "bn $\x01";
1241
595
      break;
1242
595
    }
1243
2.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
242
      AsmString = "bne $\x01";
1248
242
      break;
1249
242
    }
1250
2.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
221
      AsmString = "be $\x01";
1255
221
      break;
1256
221
    }
1257
2.43k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
148
      AsmString = "bg $\x01";
1262
148
      break;
1263
148
    }
1264
2.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
2.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
2.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
200
      AsmString = "ble $\x01";
1269
200
      break;
1270
200
    }
1271
2.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
66
      AsmString = "bge $\x01";
1276
66
      break;
1277
66
    }
1278
2.02k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
2.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
2.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
232
      AsmString = "bl $\x01";
1283
232
      break;
1284
232
    }
1285
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
226
      AsmString = "bgu $\x01";
1290
226
      break;
1291
226
    }
1292
1.56k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
328
      AsmString = "bleu $\x01";
1297
328
      break;
1298
328
    }
1299
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
41
      AsmString = "bcc $\x01";
1304
41
      break;
1305
41
    }
1306
1.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
72
      AsmString = "bcs $\x01";
1311
72
      break;
1312
72
    }
1313
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1314
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
73
      AsmString = "bpos $\x01";
1318
73
      break;
1319
73
    }
1320
1.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1321
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
213
      AsmString = "bneg $\x01";
1325
213
      break;
1326
213
    }
1327
836
    if (MCInst_getNumOperands(MI) == 2 &&
1328
836
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
836
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
204
      AsmString = "bvc $\x01";
1332
204
      break;
1333
204
    }
1334
632
    if (MCInst_getNumOperands(MI) == 2 &&
1335
632
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
632
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
632
      AsmString = "bvs $\x01";
1339
632
      break;
1340
632
    }
1341
0
    return NULL;
1342
3.05k
  case SP_BCONDA:
1343
3.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
3.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
3.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
670
      AsmString = "ba,a $\x01";
1348
670
      break;
1349
670
    }
1350
2.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
259
      AsmString = "bn,a $\x01";
1355
259
      break;
1356
259
    }
1357
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
86
      AsmString = "bne,a $\x01";
1362
86
      break;
1363
86
    }
1364
2.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
2.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
2.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
75
      AsmString = "be,a $\x01";
1369
75
      break;
1370
75
    }
1371
1.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
278
      AsmString = "bg,a $\x01";
1376
278
      break;
1377
278
    }
1378
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
206
      AsmString = "ble,a $\x01";
1383
206
      break;
1384
206
    }
1385
1.47k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
74
      AsmString = "bge,a $\x01";
1390
74
      break;
1391
74
    }
1392
1.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
92
      AsmString = "bl,a $\x01";
1397
92
      break;
1398
92
    }
1399
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
83
      AsmString = "bgu,a $\x01";
1404
83
      break;
1405
83
    }
1406
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
227
      AsmString = "bleu,a $\x01";
1411
227
      break;
1412
227
    }
1413
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1414
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
217
      AsmString = "bcc,a $\x01";
1418
217
      break;
1419
217
    }
1420
783
    if (MCInst_getNumOperands(MI) == 2 &&
1421
783
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
783
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
293
      AsmString = "bcs,a $\x01";
1425
293
      break;
1426
293
    }
1427
490
    if (MCInst_getNumOperands(MI) == 2 &&
1428
490
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
490
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
225
      AsmString = "bpos,a $\x01";
1432
225
      break;
1433
225
    }
1434
265
    if (MCInst_getNumOperands(MI) == 2 &&
1435
265
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
265
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
79
      AsmString = "bneg,a $\x01";
1439
79
      break;
1440
79
    }
1441
186
    if (MCInst_getNumOperands(MI) == 2 &&
1442
186
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
186
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
79
      AsmString = "bvc,a $\x01";
1446
79
      break;
1447
79
    }
1448
107
    if (MCInst_getNumOperands(MI) == 2 &&
1449
107
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
107
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
107
      AsmString = "bvs,a $\x01";
1453
107
      break;
1454
107
    }
1455
0
    return NULL;
1456
3.97k
  case SP_BPFCCANT:
1457
3.97k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
3.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
3.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
3.97k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
3.97k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
209
      AsmString = "fba,a,pn $\x03, $\x01";
1464
209
      break;
1465
209
    }
1466
3.77k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.77k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.77k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
487
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
487
      break;
1474
487
    }
1475
3.28k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.28k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
501
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
501
      break;
1483
501
    }
1484
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.78k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
209
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
209
      break;
1492
209
    }
1493
2.57k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.57k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.57k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
118
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
118
      break;
1501
118
    }
1502
2.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.45k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
102
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
102
      break;
1510
102
    }
1511
2.35k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
2.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
2.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
2.35k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
2.35k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
93
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
93
      break;
1519
93
    }
1520
2.26k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.26k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.26k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
199
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
199
      break;
1528
199
    }
1529
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
2.06k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
224
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
224
      break;
1537
224
    }
1538
1.83k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.83k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.83k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
255
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
255
      break;
1546
255
    }
1547
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.58k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
121
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
121
      break;
1555
121
    }
1556
1.46k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.46k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.46k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
205
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
205
      break;
1564
205
    }
1565
1.25k
    if (MCInst_getNumOperands(MI) == 3 &&
1566
1.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
1.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
1.25k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
1.25k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
536
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
536
      break;
1573
536
    }
1574
720
    if (MCInst_getNumOperands(MI) == 3 &&
1575
720
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
720
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
720
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
720
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
236
      AsmString = "fble,a,pn $\x03, $\x01";
1581
236
      break;
1582
236
    }
1583
484
    if (MCInst_getNumOperands(MI) == 3 &&
1584
484
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
484
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
484
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
484
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
282
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
282
      break;
1591
282
    }
1592
202
    if (MCInst_getNumOperands(MI) == 3 &&
1593
202
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
202
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
202
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
202
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
202
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
202
      break;
1600
202
    }
1601
0
    return NULL;
1602
3.53k
  case SP_BPFCCNT:
1603
3.53k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
3.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
3.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
3.53k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
3.53k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
236
      AsmString = "fba,pn $\x03, $\x01";
1610
236
      break;
1611
236
    }
1612
3.29k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
3.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
3.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
3.29k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
3.29k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
223
      AsmString = "fbn,pn $\x03, $\x01";
1619
223
      break;
1620
223
    }
1621
3.07k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
3.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
3.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
3.07k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
3.07k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
253
      AsmString = "fbu,pn $\x03, $\x01";
1628
253
      break;
1629
253
    }
1630
2.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.82k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.82k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
224
      AsmString = "fbg,pn $\x03, $\x01";
1637
224
      break;
1638
224
    }
1639
2.59k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.59k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
201
      AsmString = "fbug,pn $\x03, $\x01";
1646
201
      break;
1647
201
    }
1648
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
2.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
212
      AsmString = "fbl,pn $\x03, $\x01";
1655
212
      break;
1656
212
    }
1657
2.18k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
2.18k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
2.18k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
120
      AsmString = "fbul,pn $\x03, $\x01";
1664
120
      break;
1665
120
    }
1666
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
2.06k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
272
      AsmString = "fblg,pn $\x03, $\x01";
1673
272
      break;
1674
272
    }
1675
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.79k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
173
      AsmString = "fbne,pn $\x03, $\x01";
1682
173
      break;
1683
173
    }
1684
1.61k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.61k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.61k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
211
      AsmString = "fbe,pn $\x03, $\x01";
1691
211
      break;
1692
211
    }
1693
1.40k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
1.40k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
1.40k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
477
      AsmString = "fbue,pn $\x03, $\x01";
1700
477
      break;
1701
477
    }
1702
931
    if (MCInst_getNumOperands(MI) == 3 &&
1703
931
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
931
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
931
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
931
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
74
      AsmString = "fbge,pn $\x03, $\x01";
1709
74
      break;
1710
74
    }
1711
857
    if (MCInst_getNumOperands(MI) == 3 &&
1712
857
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
857
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
857
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
857
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
147
      AsmString = "fbuge,pn $\x03, $\x01";
1718
147
      break;
1719
147
    }
1720
710
    if (MCInst_getNumOperands(MI) == 3 &&
1721
710
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
710
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
710
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
710
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
79
      AsmString = "fble,pn $\x03, $\x01";
1727
79
      break;
1728
79
    }
1729
631
    if (MCInst_getNumOperands(MI) == 3 &&
1730
631
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
631
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
631
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
631
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
241
      AsmString = "fbule,pn $\x03, $\x01";
1736
241
      break;
1737
241
    }
1738
390
    if (MCInst_getNumOperands(MI) == 3 &&
1739
390
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
390
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
390
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
390
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
390
      AsmString = "fbo,pn $\x03, $\x01";
1745
390
      break;
1746
390
    }
1747
0
    return NULL;
1748
2.81k
  case SP_BPICCANT:
1749
2.81k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
213
      AsmString = "ba,a,pn %icc, $\x01";
1754
213
      break;
1755
213
    }
1756
2.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
217
      AsmString = "bn,a,pn %icc, $\x01";
1761
217
      break;
1762
217
    }
1763
2.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
2.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
2.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
116
      AsmString = "bne,a,pn %icc, $\x01";
1768
116
      break;
1769
116
    }
1770
2.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
115
      AsmString = "be,a,pn %icc, $\x01";
1775
115
      break;
1776
115
    }
1777
2.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
2.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
2.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
551
      AsmString = "bg,a,pn %icc, $\x01";
1782
551
      break;
1783
551
    }
1784
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
83
      AsmString = "ble,a,pn %icc, $\x01";
1789
83
      break;
1790
83
    }
1791
1.51k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
43
      AsmString = "bge,a,pn %icc, $\x01";
1796
43
      break;
1797
43
    }
1798
1.47k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
70
      AsmString = "bl,a,pn %icc, $\x01";
1803
70
      break;
1804
70
    }
1805
1.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
70
      AsmString = "bgu,a,pn %icc, $\x01";
1810
70
      break;
1811
70
    }
1812
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
395
      AsmString = "bleu,a,pn %icc, $\x01";
1817
395
      break;
1818
395
    }
1819
938
    if (MCInst_getNumOperands(MI) == 2 &&
1820
938
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
938
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
19
      AsmString = "bcc,a,pn %icc, $\x01";
1824
19
      break;
1825
19
    }
1826
919
    if (MCInst_getNumOperands(MI) == 2 &&
1827
919
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
919
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
254
      AsmString = "bcs,a,pn %icc, $\x01";
1831
254
      break;
1832
254
    }
1833
665
    if (MCInst_getNumOperands(MI) == 2 &&
1834
665
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
665
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
340
      AsmString = "bpos,a,pn %icc, $\x01";
1838
340
      break;
1839
340
    }
1840
325
    if (MCInst_getNumOperands(MI) == 2 &&
1841
325
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
325
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
72
      AsmString = "bneg,a,pn %icc, $\x01";
1845
72
      break;
1846
72
    }
1847
253
    if (MCInst_getNumOperands(MI) == 2 &&
1848
253
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
253
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
75
      AsmString = "bvc,a,pn %icc, $\x01";
1852
75
      break;
1853
75
    }
1854
178
    if (MCInst_getNumOperands(MI) == 2 &&
1855
178
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
178
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
178
      AsmString = "bvs,a,pn %icc, $\x01";
1859
178
      break;
1860
178
    }
1861
0
    return NULL;
1862
3.20k
  case SP_BPICCNT:
1863
3.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
3.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
3.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
125
      AsmString = "ba,pn %icc, $\x01";
1868
125
      break;
1869
125
    }
1870
3.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
3.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
3.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
366
      AsmString = "bn,pn %icc, $\x01";
1875
366
      break;
1876
366
    }
1877
2.70k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
351
      AsmString = "bne,pn %icc, $\x01";
1882
351
      break;
1883
351
    }
1884
2.35k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
681
      AsmString = "be,pn %icc, $\x01";
1889
681
      break;
1890
681
    }
1891
1.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
200
      AsmString = "bg,pn %icc, $\x01";
1896
200
      break;
1897
200
    }
1898
1.47k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
78
      AsmString = "ble,pn %icc, $\x01";
1903
78
      break;
1904
78
    }
1905
1.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
66
      AsmString = "bge,pn %icc, $\x01";
1910
66
      break;
1911
66
    }
1912
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
68
      AsmString = "bl,pn %icc, $\x01";
1917
68
      break;
1918
68
    }
1919
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
70
      AsmString = "bgu,pn %icc, $\x01";
1924
70
      break;
1925
70
    }
1926
1.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
236
      AsmString = "bleu,pn %icc, $\x01";
1931
236
      break;
1932
236
    }
1933
959
    if (MCInst_getNumOperands(MI) == 2 &&
1934
959
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
959
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
75
      AsmString = "bcc,pn %icc, $\x01";
1938
75
      break;
1939
75
    }
1940
884
    if (MCInst_getNumOperands(MI) == 2 &&
1941
884
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
884
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
269
      AsmString = "bcs,pn %icc, $\x01";
1945
269
      break;
1946
269
    }
1947
615
    if (MCInst_getNumOperands(MI) == 2 &&
1948
615
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
615
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
75
      AsmString = "bpos,pn %icc, $\x01";
1952
75
      break;
1953
75
    }
1954
540
    if (MCInst_getNumOperands(MI) == 2 &&
1955
540
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
540
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
69
      AsmString = "bneg,pn %icc, $\x01";
1959
69
      break;
1960
69
    }
1961
471
    if (MCInst_getNumOperands(MI) == 2 &&
1962
471
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
471
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
196
      AsmString = "bvc,pn %icc, $\x01";
1966
196
      break;
1967
196
    }
1968
275
    if (MCInst_getNumOperands(MI) == 2 &&
1969
275
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
275
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
275
      AsmString = "bvs,pn %icc, $\x01";
1973
275
      break;
1974
275
    }
1975
0
    return NULL;
1976
1.93k
  case SP_BPXCCANT:
1977
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
113
      AsmString = "ba,a,pn %xcc, $\x01";
1982
113
      break;
1983
113
    }
1984
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
68
      AsmString = "bn,a,pn %xcc, $\x01";
1989
68
      break;
1990
68
    }
1991
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
67
      AsmString = "bne,a,pn %xcc, $\x01";
1996
67
      break;
1997
67
    }
1998
1.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
38
      AsmString = "be,a,pn %xcc, $\x01";
2003
38
      break;
2004
38
    }
2005
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
82
      AsmString = "bg,a,pn %xcc, $\x01";
2010
82
      break;
2011
82
    }
2012
1.56k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
81
      AsmString = "ble,a,pn %xcc, $\x01";
2017
81
      break;
2018
81
    }
2019
1.48k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
70
      AsmString = "bge,a,pn %xcc, $\x01";
2024
70
      break;
2025
70
    }
2026
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
232
      AsmString = "bl,a,pn %xcc, $\x01";
2031
232
      break;
2032
232
    }
2033
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
129
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
129
      break;
2039
129
    }
2040
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
2041
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
109
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
109
      break;
2046
109
    }
2047
947
    if (MCInst_getNumOperands(MI) == 2 &&
2048
947
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
947
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
67
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
67
      break;
2053
67
    }
2054
880
    if (MCInst_getNumOperands(MI) == 2 &&
2055
880
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
880
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
219
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
219
      break;
2060
219
    }
2061
661
    if (MCInst_getNumOperands(MI) == 2 &&
2062
661
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
661
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
111
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
111
      break;
2067
111
    }
2068
550
    if (MCInst_getNumOperands(MI) == 2 &&
2069
550
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
550
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
172
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
172
      break;
2074
172
    }
2075
378
    if (MCInst_getNumOperands(MI) == 2 &&
2076
378
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
378
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
228
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
228
      break;
2081
228
    }
2082
150
    if (MCInst_getNumOperands(MI) == 2 &&
2083
150
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
150
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
150
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
150
      break;
2088
150
    }
2089
0
    return NULL;
2090
2.35k
  case SP_BPXCCNT:
2091
2.35k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
219
      AsmString = "ba,pn %xcc, $\x01";
2096
219
      break;
2097
219
    }
2098
2.13k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
286
      AsmString = "bn,pn %xcc, $\x01";
2103
286
      break;
2104
286
    }
2105
1.84k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
68
      AsmString = "bne,pn %xcc, $\x01";
2110
68
      break;
2111
68
    }
2112
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
72
      AsmString = "be,pn %xcc, $\x01";
2117
72
      break;
2118
72
    }
2119
1.70k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
209
      AsmString = "bg,pn %xcc, $\x01";
2124
209
      break;
2125
209
    }
2126
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
219
      AsmString = "ble,pn %xcc, $\x01";
2131
219
      break;
2132
219
    }
2133
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
202
      AsmString = "bge,pn %xcc, $\x01";
2138
202
      break;
2139
202
    }
2140
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
73
      AsmString = "bl,pn %xcc, $\x01";
2145
73
      break;
2146
73
    }
2147
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
68
      AsmString = "bgu,pn %xcc, $\x01";
2152
68
      break;
2153
68
    }
2154
938
    if (MCInst_getNumOperands(MI) == 2 &&
2155
938
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
938
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
174
      AsmString = "bleu,pn %xcc, $\x01";
2159
174
      break;
2160
174
    }
2161
764
    if (MCInst_getNumOperands(MI) == 2 &&
2162
764
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
764
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
70
      AsmString = "bcc,pn %xcc, $\x01";
2166
70
      break;
2167
70
    }
2168
694
    if (MCInst_getNumOperands(MI) == 2 &&
2169
694
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
694
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
68
      AsmString = "bcs,pn %xcc, $\x01";
2173
68
      break;
2174
68
    }
2175
626
    if (MCInst_getNumOperands(MI) == 2 &&
2176
626
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
626
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
70
      AsmString = "bpos,pn %xcc, $\x01";
2180
70
      break;
2181
70
    }
2182
556
    if (MCInst_getNumOperands(MI) == 2 &&
2183
556
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
556
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
236
      AsmString = "bneg,pn %xcc, $\x01";
2187
236
      break;
2188
236
    }
2189
320
    if (MCInst_getNumOperands(MI) == 2 &&
2190
320
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
320
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
21
      AsmString = "bvc,pn %xcc, $\x01";
2194
21
      break;
2195
21
    }
2196
299
    if (MCInst_getNumOperands(MI) == 2 &&
2197
299
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
299
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
299
      AsmString = "bvs,pn %xcc, $\x01";
2201
299
      break;
2202
299
    }
2203
0
    return NULL;
2204
195
  case SP_FMOVD_ICC:
2205
195
    if (MCInst_getNumOperands(MI) == 3 &&
2206
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
195
    if (MCInst_getNumOperands(MI) == 3 &&
2217
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
195
    if (MCInst_getNumOperands(MI) == 3 &&
2228
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
195
    if (MCInst_getNumOperands(MI) == 3 &&
2239
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
195
    if (MCInst_getNumOperands(MI) == 3 &&
2250
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
195
    if (MCInst_getNumOperands(MI) == 3 &&
2261
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
195
    if (MCInst_getNumOperands(MI) == 3 &&
2272
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
195
    if (MCInst_getNumOperands(MI) == 3 &&
2283
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
195
    if (MCInst_getNumOperands(MI) == 3 &&
2294
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
195
    if (MCInst_getNumOperands(MI) == 3 &&
2305
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
195
    if (MCInst_getNumOperands(MI) == 3 &&
2316
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
195
    if (MCInst_getNumOperands(MI) == 3 &&
2327
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
195
    if (MCInst_getNumOperands(MI) == 3 &&
2338
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
195
    if (MCInst_getNumOperands(MI) == 3 &&
2349
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
195
    if (MCInst_getNumOperands(MI) == 3 &&
2360
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
195
    if (MCInst_getNumOperands(MI) == 3 &&
2371
195
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
195
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
195
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
195
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
195
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
195
    return NULL;
2382
67
  case SP_FMOVD_XCC:
2383
67
    if (MCInst_getNumOperands(MI) == 3 &&
2384
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
67
    if (MCInst_getNumOperands(MI) == 3 &&
2395
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
67
    if (MCInst_getNumOperands(MI) == 3 &&
2406
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
67
    if (MCInst_getNumOperands(MI) == 3 &&
2417
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
67
    if (MCInst_getNumOperands(MI) == 3 &&
2428
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
67
    if (MCInst_getNumOperands(MI) == 3 &&
2439
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
67
    if (MCInst_getNumOperands(MI) == 3 &&
2450
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
67
    if (MCInst_getNumOperands(MI) == 3 &&
2461
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
67
    if (MCInst_getNumOperands(MI) == 3 &&
2472
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
67
    if (MCInst_getNumOperands(MI) == 3 &&
2483
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
67
    if (MCInst_getNumOperands(MI) == 3 &&
2494
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
67
    if (MCInst_getNumOperands(MI) == 3 &&
2505
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
67
    if (MCInst_getNumOperands(MI) == 3 &&
2516
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
67
    if (MCInst_getNumOperands(MI) == 3 &&
2527
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
67
    if (MCInst_getNumOperands(MI) == 3 &&
2538
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
67
    if (MCInst_getNumOperands(MI) == 3 &&
2549
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
67
    return NULL;
2560
468
  case SP_FMOVQ_ICC:
2561
468
    if (MCInst_getNumOperands(MI) == 3 &&
2562
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
468
    if (MCInst_getNumOperands(MI) == 3 &&
2573
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
468
    if (MCInst_getNumOperands(MI) == 3 &&
2584
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
468
    if (MCInst_getNumOperands(MI) == 3 &&
2595
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
468
    if (MCInst_getNumOperands(MI) == 3 &&
2606
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
468
    if (MCInst_getNumOperands(MI) == 3 &&
2617
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
468
    if (MCInst_getNumOperands(MI) == 3 &&
2628
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
468
    if (MCInst_getNumOperands(MI) == 3 &&
2639
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
468
    if (MCInst_getNumOperands(MI) == 3 &&
2650
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
468
    if (MCInst_getNumOperands(MI) == 3 &&
2661
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
468
    if (MCInst_getNumOperands(MI) == 3 &&
2672
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
468
    if (MCInst_getNumOperands(MI) == 3 &&
2683
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
468
    if (MCInst_getNumOperands(MI) == 3 &&
2694
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
468
    if (MCInst_getNumOperands(MI) == 3 &&
2705
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
468
    if (MCInst_getNumOperands(MI) == 3 &&
2716
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
468
    if (MCInst_getNumOperands(MI) == 3 &&
2727
468
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
468
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
468
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
468
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
468
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
468
    return NULL;
2738
34
  case SP_FMOVQ_XCC:
2739
34
    if (MCInst_getNumOperands(MI) == 3 &&
2740
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
34
    if (MCInst_getNumOperands(MI) == 3 &&
2751
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
34
    if (MCInst_getNumOperands(MI) == 3 &&
2762
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
34
    if (MCInst_getNumOperands(MI) == 3 &&
2773
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
34
    if (MCInst_getNumOperands(MI) == 3 &&
2784
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
34
    if (MCInst_getNumOperands(MI) == 3 &&
2795
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
34
    if (MCInst_getNumOperands(MI) == 3 &&
2806
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
34
    if (MCInst_getNumOperands(MI) == 3 &&
2817
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
34
    if (MCInst_getNumOperands(MI) == 3 &&
2828
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
34
    if (MCInst_getNumOperands(MI) == 3 &&
2839
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
34
    if (MCInst_getNumOperands(MI) == 3 &&
2850
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
34
    if (MCInst_getNumOperands(MI) == 3 &&
2861
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
34
    if (MCInst_getNumOperands(MI) == 3 &&
2872
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
34
    if (MCInst_getNumOperands(MI) == 3 &&
2883
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
34
    if (MCInst_getNumOperands(MI) == 3 &&
2894
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
34
    if (MCInst_getNumOperands(MI) == 3 &&
2905
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
34
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
34
    return NULL;
2916
88
  case SP_FMOVS_ICC:
2917
88
    if (MCInst_getNumOperands(MI) == 3 &&
2918
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
88
    if (MCInst_getNumOperands(MI) == 3 &&
2929
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
88
    if (MCInst_getNumOperands(MI) == 3 &&
2940
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
88
    if (MCInst_getNumOperands(MI) == 3 &&
2951
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
88
    if (MCInst_getNumOperands(MI) == 3 &&
2962
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
88
    if (MCInst_getNumOperands(MI) == 3 &&
2973
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
88
    if (MCInst_getNumOperands(MI) == 3 &&
2984
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
88
    if (MCInst_getNumOperands(MI) == 3 &&
2995
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
88
    if (MCInst_getNumOperands(MI) == 3 &&
3006
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
88
    if (MCInst_getNumOperands(MI) == 3 &&
3017
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
88
    if (MCInst_getNumOperands(MI) == 3 &&
3028
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
88
    if (MCInst_getNumOperands(MI) == 3 &&
3039
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
88
    if (MCInst_getNumOperands(MI) == 3 &&
3050
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
88
    if (MCInst_getNumOperands(MI) == 3 &&
3061
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
88
    if (MCInst_getNumOperands(MI) == 3 &&
3072
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
88
    if (MCInst_getNumOperands(MI) == 3 &&
3083
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
88
    return NULL;
3094
34
  case SP_FMOVS_XCC:
3095
34
    if (MCInst_getNumOperands(MI) == 3 &&
3096
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
34
    if (MCInst_getNumOperands(MI) == 3 &&
3107
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
34
    if (MCInst_getNumOperands(MI) == 3 &&
3118
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
34
    if (MCInst_getNumOperands(MI) == 3 &&
3129
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
34
    if (MCInst_getNumOperands(MI) == 3 &&
3140
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
34
    if (MCInst_getNumOperands(MI) == 3 &&
3151
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
34
    if (MCInst_getNumOperands(MI) == 3 &&
3162
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
34
    if (MCInst_getNumOperands(MI) == 3 &&
3173
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
34
    if (MCInst_getNumOperands(MI) == 3 &&
3184
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
34
    if (MCInst_getNumOperands(MI) == 3 &&
3195
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
34
    if (MCInst_getNumOperands(MI) == 3 &&
3206
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
34
    if (MCInst_getNumOperands(MI) == 3 &&
3217
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
34
    if (MCInst_getNumOperands(MI) == 3 &&
3228
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
34
    if (MCInst_getNumOperands(MI) == 3 &&
3239
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
34
    if (MCInst_getNumOperands(MI) == 3 &&
3250
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
34
    if (MCInst_getNumOperands(MI) == 3 &&
3261
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
34
    return NULL;
3272
227
  case SP_MOVICCri:
3273
227
    if (MCInst_getNumOperands(MI) == 3 &&
3274
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
227
    if (MCInst_getNumOperands(MI) == 3 &&
3283
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
227
    if (MCInst_getNumOperands(MI) == 3 &&
3292
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
227
    if (MCInst_getNumOperands(MI) == 3 &&
3301
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
227
    if (MCInst_getNumOperands(MI) == 3 &&
3310
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
227
    if (MCInst_getNumOperands(MI) == 3 &&
3319
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
227
    if (MCInst_getNumOperands(MI) == 3 &&
3328
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
227
    if (MCInst_getNumOperands(MI) == 3 &&
3337
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
227
    if (MCInst_getNumOperands(MI) == 3 &&
3346
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
227
    if (MCInst_getNumOperands(MI) == 3 &&
3355
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
227
    if (MCInst_getNumOperands(MI) == 3 &&
3364
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
227
    if (MCInst_getNumOperands(MI) == 3 &&
3373
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
227
    if (MCInst_getNumOperands(MI) == 3 &&
3382
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
227
    if (MCInst_getNumOperands(MI) == 3 &&
3391
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
227
    if (MCInst_getNumOperands(MI) == 3 &&
3400
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
227
    if (MCInst_getNumOperands(MI) == 3 &&
3409
227
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
227
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
227
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
227
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
227
    return NULL;
3418
240
  case SP_MOVICCrr:
3419
240
    if (MCInst_getNumOperands(MI) == 3 &&
3420
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
240
    if (MCInst_getNumOperands(MI) == 3 &&
3431
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
240
    if (MCInst_getNumOperands(MI) == 3 &&
3442
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
240
    if (MCInst_getNumOperands(MI) == 3 &&
3453
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
240
    if (MCInst_getNumOperands(MI) == 3 &&
3464
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
240
    if (MCInst_getNumOperands(MI) == 3 &&
3475
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
240
    if (MCInst_getNumOperands(MI) == 3 &&
3486
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
240
    if (MCInst_getNumOperands(MI) == 3 &&
3497
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
240
    if (MCInst_getNumOperands(MI) == 3 &&
3508
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
240
    if (MCInst_getNumOperands(MI) == 3 &&
3519
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
240
    if (MCInst_getNumOperands(MI) == 3 &&
3530
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
240
    if (MCInst_getNumOperands(MI) == 3 &&
3541
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
240
    if (MCInst_getNumOperands(MI) == 3 &&
3552
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
240
    if (MCInst_getNumOperands(MI) == 3 &&
3563
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
240
    if (MCInst_getNumOperands(MI) == 3 &&
3574
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
240
    if (MCInst_getNumOperands(MI) == 3 &&
3585
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
240
    return NULL;
3596
207
  case SP_MOVXCCri:
3597
207
    if (MCInst_getNumOperands(MI) == 3 &&
3598
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
207
    if (MCInst_getNumOperands(MI) == 3 &&
3607
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
207
    if (MCInst_getNumOperands(MI) == 3 &&
3616
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
207
    if (MCInst_getNumOperands(MI) == 3 &&
3625
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
207
    if (MCInst_getNumOperands(MI) == 3 &&
3634
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
207
    if (MCInst_getNumOperands(MI) == 3 &&
3643
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
207
    if (MCInst_getNumOperands(MI) == 3 &&
3652
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
207
    if (MCInst_getNumOperands(MI) == 3 &&
3661
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
207
    if (MCInst_getNumOperands(MI) == 3 &&
3670
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
207
    if (MCInst_getNumOperands(MI) == 3 &&
3679
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
207
    if (MCInst_getNumOperands(MI) == 3 &&
3688
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
207
    if (MCInst_getNumOperands(MI) == 3 &&
3697
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
207
    if (MCInst_getNumOperands(MI) == 3 &&
3706
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
207
    if (MCInst_getNumOperands(MI) == 3 &&
3715
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
207
    if (MCInst_getNumOperands(MI) == 3 &&
3724
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
207
    if (MCInst_getNumOperands(MI) == 3 &&
3733
207
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
207
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
207
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
207
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
207
    return NULL;
3742
397
  case SP_MOVXCCrr:
3743
397
    if (MCInst_getNumOperands(MI) == 3 &&
3744
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
397
    if (MCInst_getNumOperands(MI) == 3 &&
3755
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
397
    if (MCInst_getNumOperands(MI) == 3 &&
3766
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
397
    if (MCInst_getNumOperands(MI) == 3 &&
3777
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
397
    if (MCInst_getNumOperands(MI) == 3 &&
3788
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
397
    if (MCInst_getNumOperands(MI) == 3 &&
3799
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
397
    if (MCInst_getNumOperands(MI) == 3 &&
3810
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
397
    if (MCInst_getNumOperands(MI) == 3 &&
3821
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
397
    if (MCInst_getNumOperands(MI) == 3 &&
3832
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
397
    if (MCInst_getNumOperands(MI) == 3 &&
3843
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
397
    if (MCInst_getNumOperands(MI) == 3 &&
3854
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
397
    if (MCInst_getNumOperands(MI) == 3 &&
3865
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
397
    if (MCInst_getNumOperands(MI) == 3 &&
3876
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
397
    if (MCInst_getNumOperands(MI) == 3 &&
3887
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
397
    if (MCInst_getNumOperands(MI) == 3 &&
3898
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
397
    if (MCInst_getNumOperands(MI) == 3 &&
3909
397
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
397
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
397
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
397
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
397
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
397
    return NULL;
3920
405
  case SP_ORri:
3921
405
    if (MCInst_getNumOperands(MI) == 3 &&
3922
405
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
405
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
405
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
38
      AsmString = "mov $\x03, $\x01";
3927
38
      break;
3928
38
    }
3929
367
    return NULL;
3930
392
  case SP_ORrr:
3931
392
    if (MCInst_getNumOperands(MI) == 3 &&
3932
392
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
392
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
392
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
392
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
392
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
355
      AsmString = "mov $\x03, $\x01";
3939
355
      break;
3940
355
    }
3941
37
    return NULL;
3942
190
  case SP_RESTORErr:
3943
190
    if (MCInst_getNumOperands(MI) == 3 &&
3944
190
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
190
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
190
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
48
      AsmString = "restore";
3949
48
      break;
3950
48
    }
3951
142
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
6.11k
  case SP_TXCCri:
3971
6.11k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
6.11k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
6.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
6.11k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
6.11k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
353
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
353
      break;
3979
353
    }
3980
5.76k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
5.76k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
5.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
5.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
5.76k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
5.76k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
5.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
5.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
5.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
268
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
268
      break;
3996
268
    }
3997
5.49k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
5.49k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
5.49k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
5.49k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
5.49k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
5.49k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
5.49k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
5.49k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
5.49k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
261
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
261
      break;
4013
261
    }
4014
5.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
5.23k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
5.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
5.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
5.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
5.23k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
5.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
5.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
5.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
34
      AsmString = "te %xcc, $\x01 + $\x02";
4029
34
      break;
4030
34
    }
4031
5.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
5.19k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
5.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
5.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
5.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
5.19k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
5.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
5.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
5.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
523
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
523
      break;
4047
523
    }
4048
4.67k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
4.67k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
4.67k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
4.67k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
4.67k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
4.67k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
4.67k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
4.67k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
4.67k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
991
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
991
      break;
4064
991
    }
4065
3.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
3.68k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
3.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
3.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
3.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
3.68k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
3.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
3.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
3.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
113
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
113
      break;
4081
113
    }
4082
3.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
3.57k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
3.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
3.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
3.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
3.57k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
3.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
3.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
3.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
99
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
99
      break;
4098
99
    }
4099
3.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
3.47k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
3.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
3.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
3.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
3.47k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
3.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
3.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
3.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
96
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
96
      break;
4115
96
    }
4116
3.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
3.37k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
3.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
3.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
3.37k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
3.37k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
3.37k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
3.37k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
3.37k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
167
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
167
      break;
4132
167
    }
4133
3.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
3.21k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
3.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
3.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
3.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
3.21k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
3.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
3.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
3.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
391
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
391
      break;
4149
391
    }
4150
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
2.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
2.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
66
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
66
      break;
4166
66
    }
4167
2.75k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
2.75k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
2.75k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
2.75k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
2.75k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
2.75k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
2.75k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
2.75k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
2.75k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
108
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
108
      break;
4183
108
    }
4184
2.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4185
2.64k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
2.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
2.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
2.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4193
2.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
2.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
2.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
2.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
239
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
239
      break;
4200
239
    }
4201
2.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4202
2.40k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
2.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4210
2.40k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
2.40k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
176
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
176
      break;
4217
176
    }
4218
2.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4219
2.23k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
2.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4227
2.23k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
2.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
2.23k
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
2.23k
      break;
4234
2.23k
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.54k
  case SP_TXCCrr:
4245
2.54k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.54k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.54k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.54k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.54k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.54k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
225
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
225
      break;
4255
225
    }
4256
2.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.31k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.31k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.31k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.31k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
18
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
18
      break;
4276
18
    }
4277
2.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.29k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.29k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.29k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.29k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.29k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.29k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.29k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.29k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
216
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
216
      break;
4297
216
    }
4298
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
70
      AsmString = "te %xcc, $\x01 + $\x02";
4317
70
      break;
4318
70
    }
4319
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.01k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
134
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
134
      break;
4339
134
    }
4340
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
1.87k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
68
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
68
      break;
4360
68
    }
4361
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
54
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
54
      break;
4381
54
    }
4382
1.75k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.75k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
1.75k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
1.75k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.75k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.75k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.75k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.75k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.75k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
582
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
582
      break;
4402
582
    }
4403
1.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
35
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
35
      break;
4423
35
    }
4424
1.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.14k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.14k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.14k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.14k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
20
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
20
      break;
4444
20
    }
4445
1.12k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.12k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.12k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
66
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
66
      break;
4465
66
    }
4466
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.05k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
34
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
34
      break;
4486
34
    }
4487
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.02k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
40
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
40
      break;
4507
40
    }
4508
980
    if (MCInst_getNumOperands(MI) == 3 &&
4509
980
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
980
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
980
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
980
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
980
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
980
    if (MCInst_getNumOperands(MI) == 3 &&
4519
980
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
980
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
980
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
980
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
980
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
980
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
16
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
16
      break;
4528
16
    }
4529
964
    if (MCInst_getNumOperands(MI) == 3 &&
4530
964
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
964
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
964
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
964
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
964
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
964
    if (MCInst_getNumOperands(MI) == 3 &&
4540
964
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
964
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
964
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
964
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
964
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
964
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
69
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
69
      break;
4549
69
    }
4550
895
    if (MCInst_getNumOperands(MI) == 3 &&
4551
895
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
895
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
895
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
895
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
895
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
895
    if (MCInst_getNumOperands(MI) == 3 &&
4561
895
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
895
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
895
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
895
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
895
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
895
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
895
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
895
      break;
4570
895
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
106
  case SP_V9FCMPD:
4583
106
    if (MCInst_getNumOperands(MI) == 3 &&
4584
106
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
106
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
106
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
106
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
106
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
36
      AsmString = "fcmpd $\x02, $\x03";
4591
36
      break;
4592
36
    }
4593
70
    return NULL;
4594
522
  case SP_V9FCMPED:
4595
522
    if (MCInst_getNumOperands(MI) == 3 &&
4596
522
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
522
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
522
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
522
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
522
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
427
      AsmString = "fcmped $\x02, $\x03";
4603
427
      break;
4604
427
    }
4605
95
    return NULL;
4606
435
  case SP_V9FCMPEQ:
4607
435
    if (MCInst_getNumOperands(MI) == 3 &&
4608
435
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
435
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
435
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
435
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
435
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
34
      AsmString = "fcmpeq $\x02, $\x03";
4615
34
      break;
4616
34
    }
4617
401
    return NULL;
4618
704
  case SP_V9FCMPES:
4619
704
    if (MCInst_getNumOperands(MI) == 3 &&
4620
704
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
704
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
704
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
704
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
704
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
596
      AsmString = "fcmpes $\x02, $\x03";
4627
596
      break;
4628
596
    }
4629
108
    return NULL;
4630
271
  case SP_V9FCMPQ:
4631
271
    if (MCInst_getNumOperands(MI) == 3 &&
4632
271
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
271
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
271
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
271
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
271
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
70
      AsmString = "fcmpq $\x02, $\x03";
4639
70
      break;
4640
70
    }
4641
201
    return NULL;
4642
262
  case SP_V9FCMPS:
4643
262
    if (MCInst_getNumOperands(MI) == 3 &&
4644
262
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
262
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
262
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
262
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
262
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
34
      AsmString = "fcmps $\x02, $\x03";
4651
34
      break;
4652
34
    }
4653
228
    return NULL;
4654
79
  case SP_V9FMOVD_FCC:
4655
79
    if (MCInst_getNumOperands(MI) == 4 &&
4656
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
79
    if (MCInst_getNumOperands(MI) == 4 &&
4669
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
79
    if (MCInst_getNumOperands(MI) == 4 &&
4682
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
79
    if (MCInst_getNumOperands(MI) == 4 &&
4695
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
79
    if (MCInst_getNumOperands(MI) == 4 &&
4708
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
79
    if (MCInst_getNumOperands(MI) == 4 &&
4721
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
79
    if (MCInst_getNumOperands(MI) == 4 &&
4734
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
79
    if (MCInst_getNumOperands(MI) == 4 &&
4747
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
79
    if (MCInst_getNumOperands(MI) == 4 &&
4760
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
79
    if (MCInst_getNumOperands(MI) == 4 &&
4773
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
79
    if (MCInst_getNumOperands(MI) == 4 &&
4786
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
79
    if (MCInst_getNumOperands(MI) == 4 &&
4799
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
79
    if (MCInst_getNumOperands(MI) == 4 &&
4812
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
79
    if (MCInst_getNumOperands(MI) == 4 &&
4825
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
79
    if (MCInst_getNumOperands(MI) == 4 &&
4838
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
79
    if (MCInst_getNumOperands(MI) == 4 &&
4851
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
79
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
79
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
79
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
79
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
79
    return NULL;
4864
329
  case SP_V9FMOVQ_FCC:
4865
329
    if (MCInst_getNumOperands(MI) == 4 &&
4866
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
329
    if (MCInst_getNumOperands(MI) == 4 &&
4879
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
329
    if (MCInst_getNumOperands(MI) == 4 &&
4892
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
329
    if (MCInst_getNumOperands(MI) == 4 &&
4905
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
329
    if (MCInst_getNumOperands(MI) == 4 &&
4918
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
329
    if (MCInst_getNumOperands(MI) == 4 &&
4931
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
329
    if (MCInst_getNumOperands(MI) == 4 &&
4944
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
329
    if (MCInst_getNumOperands(MI) == 4 &&
4957
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
329
    if (MCInst_getNumOperands(MI) == 4 &&
4970
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
329
    if (MCInst_getNumOperands(MI) == 4 &&
4983
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
329
    if (MCInst_getNumOperands(MI) == 4 &&
4996
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
329
    if (MCInst_getNumOperands(MI) == 4 &&
5009
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
329
    if (MCInst_getNumOperands(MI) == 4 &&
5022
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
329
    if (MCInst_getNumOperands(MI) == 4 &&
5035
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
329
    if (MCInst_getNumOperands(MI) == 4 &&
5048
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
329
    if (MCInst_getNumOperands(MI) == 4 &&
5061
329
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
329
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
329
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
329
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
329
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
329
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
329
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
329
    return NULL;
5074
485
  case SP_V9FMOVS_FCC:
5075
485
    if (MCInst_getNumOperands(MI) == 4 &&
5076
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
485
    if (MCInst_getNumOperands(MI) == 4 &&
5089
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
485
    if (MCInst_getNumOperands(MI) == 4 &&
5102
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
485
    if (MCInst_getNumOperands(MI) == 4 &&
5115
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
485
    if (MCInst_getNumOperands(MI) == 4 &&
5128
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
485
    if (MCInst_getNumOperands(MI) == 4 &&
5141
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
485
    if (MCInst_getNumOperands(MI) == 4 &&
5154
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
485
    if (MCInst_getNumOperands(MI) == 4 &&
5167
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
485
    if (MCInst_getNumOperands(MI) == 4 &&
5180
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
485
    if (MCInst_getNumOperands(MI) == 4 &&
5193
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
485
    if (MCInst_getNumOperands(MI) == 4 &&
5206
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
485
    if (MCInst_getNumOperands(MI) == 4 &&
5219
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
485
    if (MCInst_getNumOperands(MI) == 4 &&
5232
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
485
    if (MCInst_getNumOperands(MI) == 4 &&
5245
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
485
    if (MCInst_getNumOperands(MI) == 4 &&
5258
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
485
    if (MCInst_getNumOperands(MI) == 4 &&
5271
485
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
485
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
485
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
485
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
485
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
485
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
485
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
485
    return NULL;
5284
266
  case SP_V9MOVFCCri:
5285
266
    if (MCInst_getNumOperands(MI) == 4 &&
5286
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
266
    if (MCInst_getNumOperands(MI) == 4 &&
5297
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
266
    if (MCInst_getNumOperands(MI) == 4 &&
5308
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
266
    if (MCInst_getNumOperands(MI) == 4 &&
5319
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
266
    if (MCInst_getNumOperands(MI) == 4 &&
5330
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
266
    if (MCInst_getNumOperands(MI) == 4 &&
5341
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
266
    if (MCInst_getNumOperands(MI) == 4 &&
5352
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
266
    if (MCInst_getNumOperands(MI) == 4 &&
5363
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
266
    if (MCInst_getNumOperands(MI) == 4 &&
5374
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
266
    if (MCInst_getNumOperands(MI) == 4 &&
5385
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
266
    if (MCInst_getNumOperands(MI) == 4 &&
5396
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
266
    if (MCInst_getNumOperands(MI) == 4 &&
5407
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
266
    if (MCInst_getNumOperands(MI) == 4 &&
5418
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
266
    if (MCInst_getNumOperands(MI) == 4 &&
5429
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
266
    if (MCInst_getNumOperands(MI) == 4 &&
5440
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
266
    if (MCInst_getNumOperands(MI) == 4 &&
5451
266
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
266
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
266
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
266
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
266
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
266
    return NULL;
5462
231
  case SP_V9MOVFCCrr:
5463
231
    if (MCInst_getNumOperands(MI) == 4 &&
5464
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
231
    if (MCInst_getNumOperands(MI) == 4 &&
5477
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
231
    if (MCInst_getNumOperands(MI) == 4 &&
5490
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
231
    if (MCInst_getNumOperands(MI) == 4 &&
5503
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
231
    if (MCInst_getNumOperands(MI) == 4 &&
5516
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
231
    if (MCInst_getNumOperands(MI) == 4 &&
5529
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
231
    if (MCInst_getNumOperands(MI) == 4 &&
5542
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
231
    if (MCInst_getNumOperands(MI) == 4 &&
5555
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
231
    if (MCInst_getNumOperands(MI) == 4 &&
5568
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
231
    if (MCInst_getNumOperands(MI) == 4 &&
5581
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
231
    if (MCInst_getNumOperands(MI) == 4 &&
5594
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
231
    if (MCInst_getNumOperands(MI) == 4 &&
5607
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
231
    if (MCInst_getNumOperands(MI) == 4 &&
5620
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
231
    if (MCInst_getNumOperands(MI) == 4 &&
5633
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
231
    if (MCInst_getNumOperands(MI) == 4 &&
5646
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
231
    if (MCInst_getNumOperands(MI) == 4 &&
5659
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
231
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
231
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
231
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
231
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
231
    return NULL;
5672
78.5k
  }
5673
5674
34.6k
  tmp = cs_strdup(AsmString);
5675
34.6k
  AsmMnem = tmp;
5676
219k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
219k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
34.6k
      *AsmOps = '\0';
5679
34.6k
      AsmOps++;
5680
34.6k
      break;
5681
34.6k
    }
5682
219k
  }
5683
34.6k
  SStream_concat0(OS, AsmMnem);
5684
34.6k
  if (*AsmOps) {
5685
34.6k
    SStream_concat0(OS, "\t");
5686
34.6k
    if (strstr(AsmOps, "icc"))
5687
6.01k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
34.6k
    if (strstr(AsmOps, "xcc"))
5689
12.9k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
244k
    for (c = AsmOps; *c; c++) {
5691
210k
      if (*c == '$') {
5692
52.3k
        c += 1;
5693
52.3k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
52.3k
          printOperand(MI, *c - 1, OS);
5701
157k
      } else {
5702
157k
        SStream_concat(OS, "%c", *c);
5703
157k
      }
5704
210k
    }
5705
34.6k
  }
5706
34.6k
  return tmp;
5707
78.5k
}
5708
5709
#endif // PRINT_ALIAS_INSTR