/src/capstonenext/arch/HPPA/HPPADisassembler.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_HPPA |
5 | | |
6 | | #include <string.h> |
7 | | #include <stddef.h> // offsetof macro |
8 | | #include <stdio.h> |
9 | | #include "HPPADisassembler.h" |
10 | | #include "HPPAConstants.h" |
11 | | |
12 | | #include "../../Mapping.h" |
13 | | #include "../../MathExtras.h" |
14 | | #include "../../utils.h" |
15 | | |
16 | 0 | #define CMPLT_HAS_MODIFY_BIT(CMPLT) (((CMPLT) & 1) == 1) |
17 | | |
18 | 0 | #define HPPA_EXT_REF(MI) (&MI->hppa_ext) |
19 | | |
20 | | static const char *const compare_cond_names[] = { |
21 | | "", "=", "<", "<=", "<<", "<<=", "sv", "od", |
22 | | "tr", "<>", ">=", ">", ">>=", ">>", "nsv", "ev" |
23 | | }; |
24 | | static const char *const compare_cond_64_names[] = { |
25 | | "*", "*=", "*<", "*<=", "*<<", "*<<=", "*sv", "*od", |
26 | | "*tr", "*<>", "*>=", "*>", "*>>=", "*>>", "*nsv", "*ev" |
27 | | }; |
28 | | static const char *const cmpib_cond_64_names[] = { "*<<", "*=", "*<", "*<=", |
29 | | "*>>=", "*<>", "*>=", "*>" }; |
30 | | static const char *const add_cond_names[] = { |
31 | | "", "=", "<", "<=", "nuv", "znv", "sv", "od", |
32 | | "tr", "<>", ">=", ">", "uv", "vnz", "nsv", "ev" |
33 | | }; |
34 | | static const char *const add_cond_64_names[] = { |
35 | | "*", "*=", "*<", "*<=", "*nuv", "*znv", "*sv", "*od", |
36 | | "*tr", "*<>", "*>=", "*>", "*uv", "*vnz", "*nsv", "*ev" |
37 | | }; |
38 | | static const char *const wide_add_cond_names[] = { |
39 | | "*", "=", "<", "<=", "nuv", "*=", "*<", "*<=", |
40 | | "tr", "<>", ">=", ">", "uv", "*<>", "*>=", "*>" |
41 | | }; |
42 | | static const char *const logical_cond_names[] = { |
43 | | "", "=", "<", "<=", "", "", "", "od", |
44 | | "tr", "<>", ">=", ">", "", "", "", "ev" |
45 | | }; |
46 | | static const char *const logical_cond_64_names[] = { |
47 | | "*", "*=", "*<", "*<=", "", "", "", "*od", |
48 | | "*tr", "*<>", "*>=", "*>", "", "", "", "*ev" |
49 | | }; |
50 | | static const char *const unit_cond_names[] = { "", "swz", "sbz", "shz", |
51 | | "sdc", "swc", "sbc", "shc", |
52 | | "tr", "nwz", "nbz", "nhz", |
53 | | "ndc", "nwc", "nbc", "nhc" }; |
54 | | static const char *const unit_cond_64_names[] = { |
55 | | "*", "*swz", "*sbz", "*shz", "*sdc", "*swc", "*sbc", "*shc", |
56 | | "*tr", "*nwz", "*nbz", "*nhz", "*ndc", "*nwc", "*nbc", "*nhc" |
57 | | }; |
58 | | static const char *const shift_cond_names[] = { "", "=", "<", "od", |
59 | | "tr", "<>", ">=", "ev" }; |
60 | | static const char *const shift_cond_64_names[] = { "*", "*=", "*<", "*od", |
61 | | "*tr", "*<>", "*>=", "*ev" }; |
62 | | static const char *const index_compl_names[] = { "", "m", "s", "sm" }; |
63 | | static const char *const short_ldst_compl_names[] = { "", "ma", "", "mb" }; |
64 | | static const char *const short_bytes_compl_names[] = { "", "b,m", "e", "e,m" }; |
65 | | static const char *const float_format_names[] = { "sgl", "dbl", "", "quad" }; |
66 | | static const char *const float_cond_names[] = { |
67 | | "", "acc", "rej", "", "", "acc8", "rej8", "", "", "acc6", "", |
68 | | "", "", "acc4", "", "", "", "acc2", "", "", "", "", |
69 | | "", "", "", "", "", "", "", "", "", "" |
70 | | }; |
71 | | static const char *const fcnv_fixed_names[] = { "w", "dw", "", "qw" }; |
72 | | static const char *const fcnv_ufixed_names[] = { "uw", "udw", "", "uqw" }; |
73 | | static const char *const float_comp_names[] = { |
74 | | "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", |
75 | | "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", |
76 | | "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", |
77 | | "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" |
78 | | }; |
79 | | static const char *const signed_unsigned_names[] = { "u", "s" }; |
80 | | static const char *const saturation_names[] = { "us", "ss", "", "" }; |
81 | | static const char *const add_compl_names[] = { "", "", "l", "tsv" }; |
82 | | |
83 | 0 | #define CREATE_GR_REG(MI, gr) MCOperand_CreateReg0(MI, gr + HPPA_REG_GR0) |
84 | 0 | #define CREATE_SR_REG(MI, sr) MCOperand_CreateReg0(MI, sr + HPPA_REG_SR0) |
85 | 0 | #define CREATE_CR_REG(MI, cr) MCOperand_CreateReg0(MI, cr + HPPA_REG_CR0) |
86 | 0 | #define CREATE_FPR_REG(MI, fpr) MCOperand_CreateReg0(MI, fpr + HPPA_REG_FPR0) |
87 | 0 | #define CREATE_FPE_REG(MI, fpe) MCOperand_CreateReg0(MI, fpe + HPPA_REG_FPE0) |
88 | | #define CREATE_SP_FPR_REG(MI, fpr) \ |
89 | 0 | MCOperand_CreateReg0(MI, fpr + HPPA_REG_SP_FPR0) |
90 | | |
91 | | static void create_float_reg_spec(MCInst *MI, uint32_t reg, uint32_t fpe_flag) |
92 | 0 | { |
93 | 0 | if (fpe_flag == 1) { |
94 | 0 | CREATE_FPE_REG(MI, reg); |
95 | 0 | } else { |
96 | 0 | CREATE_FPR_REG(MI, reg); |
97 | 0 | } |
98 | 0 | } |
99 | | |
100 | | /* Get at various relevant fields of an instruction word. */ |
101 | | |
102 | 0 | #define MASK_5 0x1f |
103 | | #define MASK_10 0x3ff |
104 | 0 | #define MASK_11 0x7ff |
105 | 0 | #define MASK_14 0x3fff |
106 | | #define MASK_16 0xffff |
107 | 0 | #define MASK_21 0x1fffff |
108 | | |
109 | | /* Routines to extract various sized constants out of hppa |
110 | | instructions. */ |
111 | | |
112 | | /* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ |
113 | | static int extract_3(unsigned word) |
114 | 0 | { |
115 | 0 | return get_insn_field(word, 18, 18) << 2 | get_insn_field(word, 16, 17); |
116 | 0 | } |
117 | | |
118 | | static int extract_5_load(unsigned word) |
119 | 0 | { |
120 | 0 | return LowSignExtend64(word >> 16 & MASK_5, 5); |
121 | 0 | } |
122 | | |
123 | | /* Extract the immediate field from a st{bhw}s instruction. */ |
124 | | |
125 | | static int extract_5_store(unsigned word) |
126 | 0 | { |
127 | 0 | return LowSignExtend64(word & MASK_5, 5); |
128 | 0 | } |
129 | | |
130 | | /* Extract an 11 bit immediate field. */ |
131 | | |
132 | | static int extract_11(unsigned word) |
133 | 0 | { |
134 | 0 | return LowSignExtend64(word & MASK_11, 11); |
135 | 0 | } |
136 | | |
137 | | /* Extract a 14 bit immediate field. */ |
138 | | |
139 | | static int extract_14(unsigned word) |
140 | 0 | { |
141 | 0 | return LowSignExtend64(word & MASK_14, 14); |
142 | 0 | } |
143 | | |
144 | | /* Extract a 16 bit immediate field. */ |
145 | | |
146 | | static int extract_16(unsigned word, bool wide) |
147 | 0 | { |
148 | 0 | int m15, m0, m1; |
149 | |
|
150 | 0 | m0 = get_insn_bit(word, 16); |
151 | 0 | m1 = get_insn_bit(word, 17); |
152 | 0 | m15 = get_insn_bit(word, 31); |
153 | 0 | word = (word >> 1) & 0x1fff; |
154 | 0 | if (wide) { |
155 | 0 | word = word | (m15 << 15) | ((m15 ^ m0) << 14) | |
156 | 0 | ((m15 ^ m1) << 13); |
157 | 0 | } else { |
158 | 0 | word = word | (m15 << 15) | (m15 << 14) | (m15 << 13); |
159 | 0 | } |
160 | 0 | return SignExtend32(word, 16); |
161 | 0 | } |
162 | | |
163 | | /* Extract a 21 bit constant. */ |
164 | | |
165 | | static int32_t extract_21(unsigned word) |
166 | 0 | { |
167 | 0 | int val; |
168 | |
|
169 | 0 | word &= MASK_21; |
170 | 0 | word <<= 11; |
171 | 0 | val = get_insn_field(word, 20, 20); |
172 | 0 | val <<= 11; |
173 | 0 | val |= get_insn_field(word, 9, 19); |
174 | 0 | val <<= 2; |
175 | 0 | val |= get_insn_field(word, 5, 6); |
176 | 0 | val <<= 5; |
177 | 0 | val |= get_insn_field(word, 0, 4); |
178 | 0 | val <<= 2; |
179 | 0 | val |= get_insn_field(word, 7, 8); |
180 | 0 | return (uint32_t)SignExtend32(val, 21) << 11; |
181 | 0 | } |
182 | | |
183 | | /* Extract a 12 bit constant from branch instructions. */ |
184 | | |
185 | | static int32_t extract_12(unsigned word) |
186 | 0 | { |
187 | 0 | return (uint32_t)SignExtend32(get_insn_field(word, 19, 28) | |
188 | 0 | get_insn_field(word, 29, 29) |
189 | 0 | << 10 | |
190 | 0 | (word & 0x1) << 11, |
191 | 0 | 12) |
192 | 0 | << 2; |
193 | 0 | } |
194 | | |
195 | | /* Extract a 17 bit constant from branch instructions, returning the |
196 | | 19 bit signed value. */ |
197 | | |
198 | | static int32_t extract_17(unsigned word) |
199 | 0 | { |
200 | 0 | return (uint32_t)SignExtend32( |
201 | 0 | get_insn_field(word, 19, 28) | |
202 | 0 | get_insn_field(word, 29, 29) << 10 | |
203 | 0 | get_insn_field(word, 11, 15) << 11 | |
204 | 0 | (word & 0x1) << 16, |
205 | 0 | 17) |
206 | 0 | << 2; |
207 | 0 | } |
208 | | |
209 | | static int32_t extract_22(unsigned word) |
210 | 0 | { |
211 | 0 | return (uint32_t)SignExtend32( |
212 | 0 | get_insn_field(word, 19, 28) | |
213 | 0 | get_insn_field(word, 29, 29) << 10 | |
214 | 0 | get_insn_field(word, 11, 15) << 11 | |
215 | 0 | get_insn_field(word, 6, 10) << 16 | |
216 | 0 | (word & 0x1) << 21, |
217 | 0 | 22) |
218 | 0 | << 2; |
219 | 0 | } |
220 | | |
221 | | static void push_str_modifier(hppa_ext *hppa, const char *modifier) |
222 | 0 | { |
223 | 0 | if (strcmp(modifier, "")) { |
224 | 0 | hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; |
225 | 0 | CS_ASSERT_RET(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); |
226 | 0 | mod->type = HPPA_MOD_STR; |
227 | 0 | CS_ASSERT_RET(strlen(modifier) < HPPA_STR_MODIFIER_LEN); |
228 | 0 | strncpy(mod->str_mod, modifier, HPPA_STR_MODIFIER_LEN - 1); |
229 | 0 | } |
230 | 0 | } |
231 | | |
232 | | static void push_int_modifier(hppa_ext *hppa, uint64_t modifier) |
233 | 0 | { |
234 | 0 | hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; |
235 | 0 | CS_ASSERT_RET(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); |
236 | 0 | mod->type = HPPA_MOD_INT; |
237 | 0 | mod->int_mod = modifier; |
238 | 0 | } |
239 | | |
240 | | static void fill_sysop_insn_name(MCInst *MI, uint32_t insn) |
241 | 0 | { |
242 | 0 | uint32_t ext8 = get_insn_field(insn, 19, 26); |
243 | 0 | uint32_t ext5 = get_insn_field(insn, 11, 15); |
244 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
245 | 0 | switch (ext8) { |
246 | 0 | case 0xa5: |
247 | 0 | MCInst_setOpcode(MI, HPPA_INS_MFIA); |
248 | 0 | return; |
249 | 0 | case 0xc6: |
250 | 0 | MCInst_setOpcode(MI, HPPA_INS_MTSARCM); |
251 | 0 | return; |
252 | 0 | case 0x65: |
253 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "r"); |
254 | | // fallthrough |
255 | 0 | case 0x60: |
256 | 0 | MCInst_setOpcode(MI, HPPA_INS_RFI); |
257 | 0 | return; |
258 | 0 | default: |
259 | 0 | break; |
260 | 0 | } |
261 | 0 | } |
262 | | |
263 | 0 | switch (ext8) { |
264 | 0 | case 0x00: |
265 | 0 | MCInst_setOpcode(MI, HPPA_INS_BREAK); |
266 | 0 | break; |
267 | 0 | case 0x20: |
268 | 0 | if (ext5 == 0x00) { |
269 | 0 | MCInst_setOpcode(MI, HPPA_INS_SYNC); |
270 | 0 | } else if (ext5 == 0x10) { |
271 | 0 | MCInst_setOpcode(MI, HPPA_INS_SYNCDMA); |
272 | 0 | } |
273 | 0 | break; |
274 | 0 | case 0x60: |
275 | 0 | MCInst_setOpcode(MI, HPPA_INS_RFI); |
276 | 0 | break; |
277 | 0 | case 0x65: |
278 | 0 | MCInst_setOpcode(MI, HPPA_INS_RFIR); |
279 | 0 | break; |
280 | 0 | case 0x6b: |
281 | 0 | MCInst_setOpcode(MI, HPPA_INS_SSM); |
282 | 0 | break; |
283 | 0 | case 0x73: |
284 | 0 | MCInst_setOpcode(MI, HPPA_INS_RSM); |
285 | 0 | break; |
286 | 0 | case 0xc3: |
287 | 0 | MCInst_setOpcode(MI, HPPA_INS_MTSM); |
288 | 0 | break; |
289 | 0 | case 0x85: |
290 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDSID); |
291 | 0 | break; |
292 | 0 | case 0xc1: |
293 | 0 | MCInst_setOpcode(MI, HPPA_INS_MTSP); |
294 | 0 | break; |
295 | 0 | case 0x25: |
296 | 0 | MCInst_setOpcode(MI, HPPA_INS_MFSP); |
297 | 0 | break; |
298 | 0 | case 0xc2: |
299 | 0 | MCInst_setOpcode(MI, HPPA_INS_MTCTL); |
300 | 0 | break; |
301 | 0 | case 0x45: |
302 | 0 | MCInst_setOpcode(MI, HPPA_INS_MFCTL); |
303 | 0 | if (get_insn_bit(insn, 17) == 1 && |
304 | 0 | MODE_IS_HPPA_20(MI->csh->mode)) { |
305 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "w"); |
306 | 0 | } |
307 | 0 | break; |
308 | 0 | default: |
309 | 0 | break; |
310 | 0 | } |
311 | 0 | } |
312 | | |
313 | | static bool decode_sysop(const cs_struct *ud, MCInst *MI, uint32_t insn) |
314 | 0 | { |
315 | 0 | uint32_t ext8 = get_insn_field(insn, 19, 26); |
316 | 0 | uint32_t ext5 = get_insn_field(insn, 11, 15); |
317 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
318 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
319 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
320 | 0 | uint32_t s = extract_3(insn); |
321 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
322 | 0 | switch (ext8) { |
323 | 0 | case 0xa5: |
324 | 0 | if (ext5 != 0) { |
325 | 0 | return false; |
326 | 0 | } |
327 | 0 | CREATE_GR_REG(MI, t); |
328 | 0 | return true; |
329 | 0 | case 0xc6: |
330 | 0 | CREATE_GR_REG(MI, r2); |
331 | 0 | return true; |
332 | 0 | default: |
333 | 0 | break; |
334 | 0 | } |
335 | 0 | } |
336 | | |
337 | 0 | switch (ext8) { |
338 | 0 | case 0x00: |
339 | 0 | MCOperand_CreateImm0(MI, t); |
340 | 0 | MCOperand_CreateImm0(MI, get_insn_field(insn, 6, 18)); |
341 | 0 | return true; |
342 | 0 | case 0x20: |
343 | 0 | if (ext5 != 0x00 && ext5 != 0x10) { |
344 | 0 | return false; |
345 | 0 | } |
346 | | // fallthrough |
347 | 0 | case 0x60: |
348 | 0 | case 0x65: |
349 | 0 | return true; |
350 | 0 | case 0x6b: |
351 | 0 | case 0x73: |
352 | 0 | MCOperand_CreateImm0(MI, get_insn_field(insn, 9, 15)); |
353 | 0 | CREATE_GR_REG(MI, t); |
354 | 0 | return true; |
355 | 0 | case 0xc3: |
356 | 0 | CREATE_GR_REG(MI, r2); |
357 | 0 | return true; |
358 | 0 | case 0x85: |
359 | 0 | CREATE_SR_REG(MI, s); |
360 | 0 | CREATE_GR_REG(MI, r1); |
361 | 0 | CREATE_GR_REG(MI, t); |
362 | 0 | return true; |
363 | 0 | case 0xc1: |
364 | 0 | CREATE_GR_REG(MI, r2); |
365 | 0 | CREATE_SR_REG(MI, s); |
366 | 0 | return true; |
367 | 0 | case 0x25: |
368 | 0 | if (ext5 != 0) { |
369 | 0 | return false; |
370 | 0 | } |
371 | 0 | CREATE_SR_REG(MI, s); |
372 | 0 | CREATE_GR_REG(MI, t); |
373 | 0 | return true; |
374 | 0 | case 0xc2: |
375 | 0 | CREATE_GR_REG(MI, r2); |
376 | 0 | CREATE_CR_REG(MI, r1); |
377 | 0 | return true; |
378 | 0 | case 0x45: |
379 | 0 | if (ext5 != 0) { |
380 | 0 | return false; |
381 | 0 | } |
382 | 0 | if (get_insn_bit(insn, 17) == 1 && MODE_IS_HPPA_20(ud->mode) && |
383 | 0 | r1 != 11) { |
384 | 0 | return false; |
385 | 0 | } |
386 | 0 | CREATE_CR_REG(MI, r1); |
387 | 0 | CREATE_GR_REG(MI, t); |
388 | 0 | return true; |
389 | 0 | default: |
390 | 0 | return false; |
391 | 0 | } |
392 | 0 | } |
393 | | |
394 | | static void fill_memmgmt_insn_name(MCInst *MI, uint32_t insn) |
395 | 0 | { |
396 | 0 | uint32_t ext = get_insn_field(insn, 19, 25); |
397 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
398 | 0 | switch (ext) { |
399 | 0 | case 0x20: |
400 | 0 | MCInst_setOpcode(MI, HPPA_INS_IITLBT); |
401 | 0 | return; |
402 | 0 | case 0x18: |
403 | 0 | MCInst_setOpcode(MI, HPPA_INS_PITLB); |
404 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "l"); |
405 | 0 | return; |
406 | 0 | case 0x60: |
407 | 0 | MCInst_setOpcode(MI, HPPA_INS_IDTLBT); |
408 | 0 | return; |
409 | 0 | case 0x58: |
410 | 0 | MCInst_setOpcode(MI, HPPA_INS_PDTLB); |
411 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "l"); |
412 | 0 | return; |
413 | 0 | case 0x4f: |
414 | 0 | MCInst_setOpcode(MI, HPPA_INS_FIC); |
415 | 0 | return; |
416 | 0 | case 0x46: |
417 | 0 | if (get_insn_bit(insn, 18) == 0) { |
418 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBE); |
419 | 0 | } else { |
420 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBEI); |
421 | 0 | }; |
422 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "r"); |
423 | 0 | return; |
424 | 0 | case 0x47: |
425 | 0 | if (get_insn_bit(insn, 18) == 0) { |
426 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBE); |
427 | 0 | } else { |
428 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBEI); |
429 | 0 | }; |
430 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "w"); |
431 | 0 | return; |
432 | 0 | default: |
433 | 0 | break; |
434 | 0 | } |
435 | 0 | } |
436 | | |
437 | 0 | switch (ext) { |
438 | 0 | case 0x00: |
439 | 0 | MCInst_setOpcode(MI, HPPA_INS_IITLBP); |
440 | 0 | break; |
441 | 0 | case 0x01: |
442 | 0 | MCInst_setOpcode(MI, HPPA_INS_IITLBA); |
443 | 0 | break; |
444 | 0 | case 0x08: |
445 | 0 | MCInst_setOpcode(MI, HPPA_INS_PITLB); |
446 | 0 | break; |
447 | 0 | case 0x09: |
448 | 0 | MCInst_setOpcode(MI, HPPA_INS_PITLBE); |
449 | 0 | break; |
450 | 0 | case 0x0a: |
451 | 0 | MCInst_setOpcode(MI, HPPA_INS_FIC); |
452 | 0 | break; |
453 | 0 | case 0x0b: |
454 | 0 | MCInst_setOpcode(MI, HPPA_INS_FICE); |
455 | 0 | break; |
456 | 0 | case 0x40: |
457 | 0 | MCInst_setOpcode(MI, HPPA_INS_IDTLBP); |
458 | 0 | break; |
459 | 0 | case 0x41: |
460 | 0 | MCInst_setOpcode(MI, HPPA_INS_IDTLBA); |
461 | 0 | break; |
462 | 0 | case 0x48: |
463 | 0 | MCInst_setOpcode(MI, HPPA_INS_PDTLB); |
464 | 0 | break; |
465 | 0 | case 0x49: |
466 | 0 | MCInst_setOpcode(MI, HPPA_INS_PDTLBE); |
467 | 0 | break; |
468 | 0 | case 0x4a: |
469 | 0 | MCInst_setOpcode(MI, HPPA_INS_FDC); |
470 | 0 | break; |
471 | 0 | case 0x4b: |
472 | 0 | MCInst_setOpcode(MI, HPPA_INS_FDCE); |
473 | 0 | break; |
474 | 0 | case 0x4e: |
475 | 0 | MCInst_setOpcode(MI, HPPA_INS_PDC); |
476 | 0 | break; |
477 | 0 | case 0x46: |
478 | 0 | if (get_insn_bit(insn, 18) == 0) { |
479 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBER); |
480 | 0 | } else { |
481 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBERI); |
482 | 0 | }; |
483 | 0 | break; |
484 | 0 | case 0x47: |
485 | 0 | if (get_insn_bit(insn, 18) == 0) { |
486 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBEW); |
487 | 0 | } else { |
488 | 0 | MCInst_setOpcode(MI, HPPA_INS_PROBEWI); |
489 | 0 | }; |
490 | 0 | break; |
491 | 0 | case 0x4d: |
492 | 0 | MCInst_setOpcode(MI, HPPA_INS_LPA); |
493 | 0 | break; |
494 | 0 | case 0x4c: |
495 | 0 | MCInst_setOpcode(MI, HPPA_INS_LCI); |
496 | 0 | break; |
497 | 0 | default: |
498 | 0 | break; |
499 | 0 | } |
500 | 0 | } |
501 | | |
502 | | static void fill_memmgmt_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) |
503 | 0 | { |
504 | 0 | uint8_t cmplt = get_insn_bit(insn, 26); |
505 | 0 | uint32_t ext = get_insn_field(insn, 19, 25); |
506 | 0 | if (MODE_IS_HPPA_20(mode)) { |
507 | 0 | switch (ext) { |
508 | 0 | case 0x18: |
509 | 0 | case 0x58: |
510 | 0 | case 0x4f: |
511 | 0 | goto success; |
512 | 0 | default: |
513 | 0 | break; |
514 | 0 | } |
515 | 0 | } |
516 | | |
517 | 0 | switch (ext) { |
518 | 0 | case 0x08: |
519 | 0 | case 0x09: |
520 | 0 | case 0x0a: |
521 | 0 | case 0x0b: |
522 | 0 | case 0x48: |
523 | 0 | case 0x49: |
524 | 0 | case 0x4a: |
525 | 0 | case 0x4b: |
526 | 0 | case 0x4e: |
527 | 0 | case 0x4d: |
528 | 0 | break; |
529 | 0 | default: |
530 | 0 | return; |
531 | 0 | } |
532 | 0 | success: |
533 | 0 | if (CMPLT_HAS_MODIFY_BIT(cmplt)) { |
534 | 0 | hppa_ext->b_writeble = true; |
535 | 0 | } |
536 | 0 | push_str_modifier(hppa_ext, index_compl_names[cmplt]); |
537 | 0 | } |
538 | | |
539 | | static bool decode_memmgmt(const cs_struct *ud, MCInst *MI, uint32_t insn) |
540 | 0 | { |
541 | 0 | uint32_t ext = get_insn_field(insn, 19, 25); |
542 | 0 | uint32_t b = get_insn_field(insn, 6, 10); |
543 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
544 | 0 | uint32_t s3 = extract_3(insn); |
545 | 0 | uint32_t s2 = get_insn_field(insn, 16, 17); |
546 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
547 | 0 | if (ext > 0x20 && get_insn_bit(insn, 18) == 1 && |
548 | 0 | (ext != 0x46 && ext != 0x47)) { |
549 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
550 | 0 | if (ext != 0x4a) { |
551 | 0 | return false; |
552 | 0 | } |
553 | 0 | } else { |
554 | 0 | return false; |
555 | 0 | } |
556 | 0 | } |
557 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
558 | 0 | switch (ext) { |
559 | 0 | case 0x20: |
560 | 0 | case 0x60: |
561 | 0 | CREATE_GR_REG(MI, r); |
562 | 0 | CREATE_GR_REG(MI, b); |
563 | 0 | goto success; |
564 | 0 | case 0x58: |
565 | 0 | case 0x4f: |
566 | 0 | CREATE_GR_REG(MI, r); |
567 | 0 | CREATE_SR_REG(MI, s2); |
568 | 0 | CREATE_GR_REG(MI, b); |
569 | 0 | goto success; |
570 | 0 | case 0x18: |
571 | 0 | CREATE_GR_REG(MI, r); |
572 | 0 | CREATE_SR_REG(MI, s3); |
573 | 0 | CREATE_GR_REG(MI, b); |
574 | 0 | goto success; |
575 | 0 | case 0x4a: |
576 | 0 | if (get_insn_bit(insn, 18) == 1) { |
577 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); |
578 | 0 | } else { |
579 | 0 | CREATE_GR_REG(MI, r); |
580 | 0 | } |
581 | 0 | CREATE_SR_REG(MI, s2); |
582 | 0 | CREATE_GR_REG(MI, b); |
583 | 0 | goto success; |
584 | 0 | default: |
585 | 0 | break; |
586 | 0 | } |
587 | 0 | } |
588 | | |
589 | 0 | switch (ext) { |
590 | 0 | case 0x00: |
591 | 0 | case 0x01: |
592 | 0 | case 0x08: |
593 | 0 | case 0x09: |
594 | 0 | case 0x0a: |
595 | 0 | case 0x0b: |
596 | 0 | CREATE_GR_REG(MI, r); |
597 | 0 | CREATE_SR_REG(MI, s3); |
598 | 0 | CREATE_GR_REG(MI, b); |
599 | 0 | break; |
600 | 0 | case 0x40: |
601 | 0 | case 0x41: |
602 | 0 | case 0x48: |
603 | 0 | case 0x49: |
604 | 0 | case 0x4a: |
605 | 0 | case 0x4b: |
606 | 0 | case 0x4e: |
607 | 0 | CREATE_GR_REG(MI, r); |
608 | 0 | CREATE_SR_REG(MI, s2); |
609 | 0 | CREATE_GR_REG(MI, b); |
610 | 0 | break; |
611 | 0 | case 0x46: |
612 | 0 | case 0x47: |
613 | 0 | CREATE_SR_REG(MI, s2); |
614 | 0 | CREATE_GR_REG(MI, b); |
615 | 0 | if (get_insn_bit(insn, 18) == 0) { |
616 | 0 | CREATE_GR_REG(MI, r); |
617 | 0 | } else { |
618 | 0 | MCOperand_CreateImm0(MI, r); |
619 | 0 | } |
620 | 0 | CREATE_GR_REG(MI, t); |
621 | 0 | break; |
622 | 0 | case 0x4d: |
623 | 0 | case 0x4c: |
624 | 0 | CREATE_GR_REG(MI, r); |
625 | 0 | CREATE_SR_REG(MI, s2); |
626 | 0 | CREATE_GR_REG(MI, b); |
627 | 0 | CREATE_GR_REG(MI, t); |
628 | 0 | break; |
629 | 0 | default: |
630 | 0 | return false; |
631 | 0 | } |
632 | 0 | success: |
633 | 0 | fill_memmgmt_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); |
634 | 0 | return true; |
635 | 0 | } |
636 | | |
637 | | static void fill_alu_insn_name(MCInst *MI, uint32_t insn) |
638 | 0 | { |
639 | 0 | uint32_t ext = get_insn_field(insn, 20, 25); |
640 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
641 | 0 | switch (ext) { |
642 | 0 | case 0x28: |
643 | 0 | case 0x38: |
644 | 0 | case 0x1c: |
645 | 0 | case 0x3c: |
646 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADD); |
647 | 0 | return; |
648 | 0 | case 0x19: |
649 | 0 | case 0x29: |
650 | 0 | case 0x39: |
651 | 0 | case 0x1a: |
652 | 0 | case 0x2a: |
653 | 0 | case 0x3a: |
654 | 0 | case 0x1b: |
655 | 0 | case 0x2b: |
656 | 0 | case 0x3b: |
657 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHLADD); |
658 | 0 | return; |
659 | 0 | case 0x30: |
660 | 0 | case 0x13: |
661 | 0 | case 0x33: |
662 | 0 | case 0x14: |
663 | 0 | case 0x34: |
664 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUB); |
665 | 0 | return; |
666 | 0 | case 0x22: |
667 | 0 | MCInst_setOpcode(MI, HPPA_INS_CMPCLR); |
668 | 0 | return; |
669 | 0 | case 0x27: |
670 | 0 | MCInst_setOpcode(MI, HPPA_INS_UADDCM); |
671 | 0 | return; |
672 | 0 | case 0x2f: |
673 | 0 | MCInst_setOpcode(MI, HPPA_INS_DCOR); |
674 | 0 | return; |
675 | 0 | case 0x0f: |
676 | 0 | case 0x0d: |
677 | 0 | case 0x0c: |
678 | 0 | MCInst_setOpcode(MI, HPPA_INS_HADD); |
679 | 0 | return; |
680 | 0 | case 0x07: |
681 | 0 | case 0x05: |
682 | 0 | case 0x04: |
683 | 0 | MCInst_setOpcode(MI, HPPA_INS_HSUB); |
684 | 0 | return; |
685 | 0 | case 0x0b: |
686 | 0 | MCInst_setOpcode(MI, HPPA_INS_HAVG); |
687 | 0 | return; |
688 | 0 | case 0x1d: |
689 | 0 | case 0x1e: |
690 | 0 | case 0x1f: |
691 | 0 | MCInst_setOpcode(MI, HPPA_INS_HSHLADD); |
692 | 0 | return; |
693 | 0 | case 0x15: |
694 | 0 | case 0x16: |
695 | 0 | case 0x17: |
696 | 0 | MCInst_setOpcode(MI, HPPA_INS_HSHRADD); |
697 | 0 | return; |
698 | 0 | default: |
699 | 0 | break; |
700 | 0 | } |
701 | 0 | } |
702 | | |
703 | 0 | switch (ext) { |
704 | 0 | case 0x18: |
705 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADD); |
706 | 0 | break; |
707 | 0 | case 0x38: |
708 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDO); |
709 | 0 | break; |
710 | 0 | case 0x1c: |
711 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDC); |
712 | 0 | break; |
713 | 0 | case 0x3c: |
714 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDCO); |
715 | 0 | break; |
716 | 0 | case 0x19: |
717 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH1ADD); |
718 | 0 | break; |
719 | 0 | case 0x39: |
720 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH1ADDO); |
721 | 0 | break; |
722 | 0 | case 0x1a: |
723 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH2ADD); |
724 | 0 | break; |
725 | 0 | case 0x3a: |
726 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH2ADDO); |
727 | 0 | break; |
728 | 0 | case 0x1b: |
729 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH3ADD); |
730 | 0 | break; |
731 | 0 | case 0x3b: |
732 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH3ADDO); |
733 | 0 | break; |
734 | 0 | case 0x10: |
735 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUB); |
736 | 0 | break; |
737 | 0 | case 0x30: |
738 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBO); |
739 | 0 | break; |
740 | 0 | case 0x13: |
741 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBT); |
742 | 0 | break; |
743 | 0 | case 0x33: |
744 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBTO); |
745 | 0 | break; |
746 | 0 | case 0x14: |
747 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBB); |
748 | 0 | break; |
749 | 0 | case 0x34: |
750 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBBO); |
751 | 0 | break; |
752 | 0 | case 0x11: |
753 | 0 | MCInst_setOpcode(MI, HPPA_INS_DS); |
754 | 0 | break; |
755 | 0 | case 0x00: |
756 | 0 | MCInst_setOpcode(MI, HPPA_INS_ANDCM); |
757 | 0 | break; |
758 | 0 | case 0x08: |
759 | 0 | MCInst_setOpcode(MI, HPPA_INS_AND); |
760 | 0 | break; |
761 | 0 | case 0x09: |
762 | 0 | MCInst_setOpcode(MI, HPPA_INS_OR); |
763 | 0 | break; |
764 | 0 | case 0x0a: |
765 | 0 | MCInst_setOpcode(MI, HPPA_INS_XOR); |
766 | 0 | break; |
767 | 0 | case 0x0e: |
768 | 0 | MCInst_setOpcode(MI, HPPA_INS_UXOR); |
769 | 0 | break; |
770 | 0 | case 0x22: |
771 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMCLR); |
772 | 0 | break; |
773 | 0 | case 0x26: |
774 | 0 | MCInst_setOpcode(MI, HPPA_INS_UADDCM); |
775 | 0 | break; |
776 | 0 | case 0x27: |
777 | 0 | MCInst_setOpcode(MI, HPPA_INS_UADDCMT); |
778 | 0 | break; |
779 | 0 | case 0x28: |
780 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDL); |
781 | 0 | break; |
782 | 0 | case 0x29: |
783 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH1ADDL); |
784 | 0 | break; |
785 | 0 | case 0x2a: |
786 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH2ADDL); |
787 | 0 | break; |
788 | 0 | case 0x2b: |
789 | 0 | MCInst_setOpcode(MI, HPPA_INS_SH3ADDL); |
790 | 0 | break; |
791 | 0 | case 0x2e: |
792 | 0 | MCInst_setOpcode(MI, HPPA_INS_DCOR); |
793 | 0 | break; |
794 | 0 | case 0x2f: |
795 | 0 | MCInst_setOpcode(MI, HPPA_INS_IDCOR); |
796 | 0 | break; |
797 | 0 | default: |
798 | 0 | break; |
799 | 0 | } |
800 | 0 | } |
801 | | |
802 | | static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) |
803 | 0 | { |
804 | 0 | uint32_t cond = (get_insn_field(insn, 19, 19) << 3) | |
805 | 0 | get_insn_field(insn, 16, 18); |
806 | 0 | uint32_t ext = get_insn_field(insn, 20, 25); |
807 | 0 | if (MODE_IS_HPPA_20(mode)) { |
808 | 0 | uint32_t e1 = get_insn_field(insn, 20, 21); |
809 | 0 | uint32_t e2 = get_insn_bit(insn, 23); |
810 | 0 | uint32_t e3 = get_insn_field(insn, 24, 25); |
811 | 0 | uint32_t d = get_insn_bit(insn, 26); |
812 | 0 | switch (ext) { |
813 | 0 | case 0x18: |
814 | 0 | case 0x28: |
815 | 0 | case 0x38: |
816 | 0 | case 0x1c: |
817 | 0 | case 0x3c: |
818 | 0 | if (e2 == 1) { |
819 | 0 | if (d == 1) { |
820 | 0 | push_str_modifier(hppa_ext, "dc"); |
821 | 0 | } else { |
822 | 0 | push_str_modifier(hppa_ext, "c"); |
823 | 0 | } |
824 | 0 | } |
825 | | // fallthrough |
826 | 0 | case 0x19: |
827 | 0 | case 0x29: |
828 | 0 | case 0x39: |
829 | 0 | case 0x1a: |
830 | 0 | case 0x2a: |
831 | 0 | case 0x3a: |
832 | 0 | case 0x1b: |
833 | 0 | case 0x2b: |
834 | 0 | case 0x3b: |
835 | 0 | push_str_modifier(hppa_ext, add_compl_names[e1]); |
836 | 0 | if (d == 1) { |
837 | 0 | push_str_modifier(hppa_ext, |
838 | 0 | add_cond_64_names[cond]); |
839 | 0 | } else { |
840 | 0 | push_str_modifier(hppa_ext, |
841 | 0 | add_cond_names[cond]); |
842 | 0 | } |
843 | 0 | return; |
844 | 0 | case 0x10: |
845 | 0 | case 0x30: |
846 | 0 | case 0x13: |
847 | 0 | case 0x33: |
848 | 0 | case 0x14: |
849 | 0 | case 0x34: |
850 | 0 | if (e2 == 1) { |
851 | 0 | if (d == 1) { |
852 | 0 | push_str_modifier(hppa_ext, "db"); |
853 | 0 | } else { |
854 | 0 | push_str_modifier(hppa_ext, "b"); |
855 | 0 | } |
856 | 0 | } |
857 | 0 | if (e1 == 3) { |
858 | 0 | push_str_modifier(hppa_ext, "tsv"); |
859 | 0 | } |
860 | 0 | if (e3 == 3) { |
861 | 0 | push_str_modifier(hppa_ext, "tc"); |
862 | 0 | } |
863 | | // fallthrough |
864 | 0 | case 0x22: |
865 | 0 | if (d == 1) { |
866 | 0 | push_str_modifier(hppa_ext, |
867 | 0 | compare_cond_64_names[cond]); |
868 | 0 | } else { |
869 | 0 | push_str_modifier(hppa_ext, |
870 | 0 | compare_cond_names[cond]); |
871 | 0 | } |
872 | 0 | return; |
873 | 0 | case 0x00: |
874 | 0 | case 0x08: |
875 | 0 | case 0x09: |
876 | 0 | case 0x0a: |
877 | 0 | if (d == 1) { |
878 | 0 | push_str_modifier(hppa_ext, |
879 | 0 | logical_cond_64_names[cond]); |
880 | 0 | } else { |
881 | 0 | push_str_modifier(hppa_ext, |
882 | 0 | logical_cond_names[cond]); |
883 | 0 | } |
884 | 0 | return; |
885 | 0 | case 0x27: |
886 | 0 | push_str_modifier(hppa_ext, "tc"); |
887 | 0 | goto unit_cond; |
888 | 0 | case 0x2f: |
889 | 0 | push_str_modifier(hppa_ext, "i"); |
890 | | // fallthrough |
891 | 0 | case 0x26: |
892 | 0 | case 0x0e: |
893 | 0 | case 0x2e: |
894 | 0 | unit_cond: |
895 | 0 | if (d == 1) { |
896 | 0 | push_str_modifier(hppa_ext, |
897 | 0 | unit_cond_64_names[cond]); |
898 | 0 | } else { |
899 | 0 | push_str_modifier(hppa_ext, |
900 | 0 | unit_cond_names[cond]); |
901 | 0 | } |
902 | 0 | return; |
903 | 0 | case 0x0d: |
904 | 0 | case 0x0c: |
905 | 0 | case 0x05: |
906 | 0 | case 0x04: |
907 | 0 | push_str_modifier(hppa_ext, saturation_names[e3]); |
908 | 0 | return; |
909 | 0 | default: |
910 | 0 | break; |
911 | 0 | } |
912 | 0 | } |
913 | | |
914 | 0 | switch (ext) { |
915 | 0 | case 0x18: |
916 | 0 | case 0x38: |
917 | 0 | case 0x1c: |
918 | 0 | case 0x3c: |
919 | 0 | case 0x19: |
920 | 0 | case 0x39: |
921 | 0 | case 0x1a: |
922 | 0 | case 0x3a: |
923 | 0 | case 0x3b: |
924 | 0 | case 0x28: |
925 | 0 | case 0x29: |
926 | 0 | case 0x2a: |
927 | 0 | case 0x2b: |
928 | 0 | push_str_modifier(hppa_ext, add_cond_names[cond]); |
929 | 0 | break; |
930 | 0 | case 0x10: |
931 | 0 | case 0x30: |
932 | 0 | case 0x13: |
933 | 0 | case 0x33: |
934 | 0 | case 0x14: |
935 | 0 | case 0x34: |
936 | 0 | case 0x11: |
937 | 0 | case 0x22: |
938 | 0 | push_str_modifier(hppa_ext, compare_cond_names[cond]); |
939 | 0 | break; |
940 | 0 | case 0x00: |
941 | 0 | case 0x08: |
942 | 0 | case 0x09: |
943 | 0 | case 0x0a: |
944 | 0 | push_str_modifier(hppa_ext, logical_cond_names[cond]); |
945 | 0 | break; |
946 | 0 | case 0x0e: |
947 | 0 | case 0x26: |
948 | 0 | case 0x27: |
949 | 0 | case 0x2e: |
950 | 0 | case 0x2f: |
951 | 0 | push_str_modifier(hppa_ext, unit_cond_names[cond]); |
952 | 0 | break; |
953 | 0 | default: |
954 | 0 | break; |
955 | 0 | } |
956 | 0 | } |
957 | | |
958 | | static bool decode_alu(const cs_struct *ud, MCInst *MI, uint32_t insn) |
959 | 0 | { |
960 | 0 | uint32_t ext = get_insn_field(insn, 20, 25); |
961 | 0 | uint32_t r1 = get_insn_field(insn, 11, 15); |
962 | 0 | uint32_t r2 = get_insn_field(insn, 6, 10); |
963 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
964 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
965 | 0 | switch (ext) { |
966 | 0 | case 0x19: |
967 | 0 | case 0x29: |
968 | 0 | case 0x39: |
969 | 0 | case 0x1a: |
970 | 0 | case 0x2a: |
971 | 0 | case 0x3a: |
972 | 0 | case 0x1b: |
973 | 0 | case 0x2b: |
974 | 0 | case 0x3b: |
975 | 0 | case 0x1d: |
976 | 0 | case 0x1e: |
977 | 0 | case 0x1f: |
978 | 0 | case 0x15: |
979 | 0 | case 0x16: |
980 | 0 | case 0x17: |
981 | 0 | case 0x0f: |
982 | 0 | case 0x0d: |
983 | 0 | case 0x0c: |
984 | 0 | case 0x07: |
985 | 0 | case 0x05: |
986 | 0 | case 0x04: |
987 | 0 | case 0x0b: |
988 | 0 | CREATE_GR_REG(MI, r1); |
989 | 0 | if (ext > 0x10) { |
990 | 0 | MCOperand_CreateImm0( |
991 | 0 | MI, get_insn_field(insn, 24, 25)); |
992 | 0 | } |
993 | 0 | CREATE_GR_REG(MI, r2); |
994 | 0 | CREATE_GR_REG(MI, t); |
995 | 0 | goto success; |
996 | 0 | default: |
997 | 0 | break; |
998 | 0 | } |
999 | 0 | } |
1000 | 0 | switch (ext) { |
1001 | 0 | case 0x18: |
1002 | 0 | case 0x38: |
1003 | 0 | case 0x1c: |
1004 | 0 | case 0x3c: |
1005 | 0 | case 0x19: |
1006 | 0 | case 0x39: |
1007 | 0 | case 0x1a: |
1008 | 0 | case 0x3a: |
1009 | 0 | case 0x1b: |
1010 | 0 | case 0x3b: |
1011 | 0 | case 0x10: |
1012 | 0 | case 0x30: |
1013 | 0 | case 0x13: |
1014 | 0 | case 0x33: |
1015 | 0 | case 0x14: |
1016 | 0 | case 0x34: |
1017 | 0 | case 0x11: |
1018 | 0 | case 0x00: |
1019 | 0 | case 0x08: |
1020 | 0 | case 0x09: |
1021 | 0 | case 0x0a: |
1022 | 0 | case 0x0e: |
1023 | 0 | case 0x22: |
1024 | 0 | case 0x26: |
1025 | 0 | case 0x27: |
1026 | 0 | case 0x28: |
1027 | 0 | case 0x29: |
1028 | 0 | case 0x2a: |
1029 | 0 | case 0x2b: |
1030 | 0 | CREATE_GR_REG(MI, r1); |
1031 | | // fallthrough |
1032 | 0 | case 0x2e: |
1033 | 0 | case 0x2f: |
1034 | 0 | CREATE_GR_REG(MI, r2); |
1035 | 0 | CREATE_GR_REG(MI, t); |
1036 | 0 | break; |
1037 | 0 | default: |
1038 | 0 | return false; |
1039 | 0 | } |
1040 | 0 | success: |
1041 | 0 | fill_alu_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); |
1042 | 0 | return true; |
1043 | 0 | } |
1044 | | |
1045 | | static void fill_idxmem_insn_name(MCInst *MI, uint32_t insn) |
1046 | 0 | { |
1047 | 0 | uint32_t ext = get_insn_field(insn, 22, 25); |
1048 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
1049 | 0 | switch (ext) { |
1050 | 0 | case 0x00: |
1051 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDB); |
1052 | 0 | return; |
1053 | 0 | case 0x01: |
1054 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDH); |
1055 | 0 | return; |
1056 | 0 | case 0x02: |
1057 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDW); |
1058 | 0 | return; |
1059 | 0 | case 0x03: |
1060 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDD); |
1061 | 0 | return; |
1062 | 0 | case 0x04: |
1063 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDDA); |
1064 | 0 | return; |
1065 | 0 | case 0x05: |
1066 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDCD); |
1067 | 0 | return; |
1068 | 0 | case 0x06: |
1069 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWA); |
1070 | 0 | return; |
1071 | 0 | case 0x07: |
1072 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDCW); |
1073 | 0 | return; |
1074 | 0 | default: |
1075 | 0 | break; |
1076 | 0 | } |
1077 | 0 | if (get_insn_bit(insn, 19) == 1) { |
1078 | 0 | switch (ext) { |
1079 | 0 | case 0x08: |
1080 | 0 | MCInst_setOpcode(MI, HPPA_INS_STB); |
1081 | 0 | return; |
1082 | 0 | case 0x09: |
1083 | 0 | MCInst_setOpcode(MI, HPPA_INS_STH); |
1084 | 0 | return; |
1085 | 0 | case 0x0a: |
1086 | 0 | MCInst_setOpcode(MI, HPPA_INS_STW); |
1087 | 0 | return; |
1088 | 0 | case 0x0b: |
1089 | 0 | MCInst_setOpcode(MI, HPPA_INS_STD); |
1090 | 0 | return; |
1091 | 0 | case 0x0c: |
1092 | 0 | MCInst_setOpcode(MI, HPPA_INS_STBY); |
1093 | 0 | return; |
1094 | 0 | case 0x0d: |
1095 | 0 | MCInst_setOpcode(MI, HPPA_INS_STDBY); |
1096 | 0 | return; |
1097 | 0 | case 0x0e: |
1098 | 0 | MCInst_setOpcode(MI, HPPA_INS_STWA); |
1099 | 0 | return; |
1100 | 0 | case 0x0f: |
1101 | 0 | MCInst_setOpcode(MI, HPPA_INS_STDA); |
1102 | 0 | return; |
1103 | 0 | default: |
1104 | 0 | break; |
1105 | 0 | } |
1106 | 0 | } |
1107 | 0 | } |
1108 | 0 | if (get_insn_bit(insn, 19) == 0) { |
1109 | 0 | switch (ext) { |
1110 | 0 | case 0x00: |
1111 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDBX); |
1112 | 0 | break; |
1113 | 0 | case 0x01: |
1114 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDHX); |
1115 | 0 | break; |
1116 | 0 | case 0x02: |
1117 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWX); |
1118 | 0 | break; |
1119 | 0 | case 0x07: |
1120 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDCWX); |
1121 | 0 | break; |
1122 | 0 | case 0x06: |
1123 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWAX); |
1124 | 0 | break; |
1125 | 0 | default: |
1126 | 0 | break; |
1127 | 0 | } |
1128 | 0 | } else { |
1129 | 0 | switch (ext) { |
1130 | 0 | case 0x00: |
1131 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDBS); |
1132 | 0 | break; |
1133 | 0 | case 0x01: |
1134 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDHS); |
1135 | 0 | break; |
1136 | 0 | case 0x02: |
1137 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWS); |
1138 | 0 | break; |
1139 | 0 | case 0x07: |
1140 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDCWS); |
1141 | 0 | break; |
1142 | 0 | case 0x06: |
1143 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWAS); |
1144 | 0 | break; |
1145 | 0 | case 0x08: |
1146 | 0 | MCInst_setOpcode(MI, HPPA_INS_STBS); |
1147 | 0 | break; |
1148 | 0 | case 0x09: |
1149 | 0 | MCInst_setOpcode(MI, HPPA_INS_STHS); |
1150 | 0 | break; |
1151 | 0 | case 0x0a: |
1152 | 0 | MCInst_setOpcode(MI, HPPA_INS_STWS); |
1153 | 0 | break; |
1154 | 0 | case 0x0c: |
1155 | 0 | MCInst_setOpcode(MI, HPPA_INS_STBYS); |
1156 | 0 | break; |
1157 | 0 | case 0x0e: |
1158 | 0 | MCInst_setOpcode(MI, HPPA_INS_STWAS); |
1159 | 0 | break; |
1160 | 0 | default: |
1161 | 0 | break; |
1162 | 0 | } |
1163 | 0 | } |
1164 | 0 | } |
1165 | | |
1166 | | static void fill_idxmem_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode, |
1167 | | uint32_t im5) |
1168 | 0 | { |
1169 | 0 | uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); |
1170 | 0 | uint32_t cc = get_insn_field(insn, 20, 21); |
1171 | 0 | uint32_t ext = get_insn_field(insn, 22, 25); |
1172 | 0 | if (CMPLT_HAS_MODIFY_BIT(cmplt)) { |
1173 | 0 | hppa_ext->b_writeble = true; |
1174 | 0 | } |
1175 | 0 | if (get_insn_bit(insn, 19) == 0) { |
1176 | 0 | switch (ext) { |
1177 | 0 | case 0x00: |
1178 | 0 | case 0x01: |
1179 | 0 | case 0x02: |
1180 | 0 | case 0x03: |
1181 | 0 | case 0x04: |
1182 | 0 | case 0x06: |
1183 | 0 | push_str_modifier(hppa_ext, index_compl_names[cmplt]); |
1184 | 0 | if (cc == 2) { |
1185 | 0 | push_str_modifier(hppa_ext, "sl"); |
1186 | 0 | } |
1187 | 0 | break; |
1188 | 0 | case 0x05: |
1189 | 0 | case 0x07: |
1190 | 0 | push_str_modifier(hppa_ext, index_compl_names[cmplt]); |
1191 | 0 | if (cc == 1) { |
1192 | 0 | push_str_modifier(hppa_ext, "co"); |
1193 | 0 | } |
1194 | 0 | break; |
1195 | 0 | default: |
1196 | 0 | break; |
1197 | 0 | } |
1198 | 0 | } else { |
1199 | 0 | switch (ext) { |
1200 | 0 | case 0x00: |
1201 | 0 | case 0x01: |
1202 | 0 | case 0x02: |
1203 | 0 | case 0x03: |
1204 | 0 | case 0x04: |
1205 | 0 | case 0x06: |
1206 | 0 | if (cmplt == 1 && im5 == 0) { |
1207 | 0 | push_str_modifier(hppa_ext, "o"); |
1208 | 0 | } else { |
1209 | 0 | push_str_modifier( |
1210 | 0 | hppa_ext, |
1211 | 0 | short_ldst_compl_names[cmplt]); |
1212 | 0 | } |
1213 | 0 | if (cc == 2) { |
1214 | 0 | push_str_modifier(hppa_ext, "sl"); |
1215 | 0 | } |
1216 | 0 | break; |
1217 | 0 | case 0x05: |
1218 | 0 | case 0x07: |
1219 | 0 | if (cmplt == 1 && im5 == 0) { |
1220 | 0 | push_str_modifier(hppa_ext, "o"); |
1221 | 0 | } else { |
1222 | 0 | push_str_modifier( |
1223 | 0 | hppa_ext, |
1224 | 0 | short_ldst_compl_names[cmplt]); |
1225 | 0 | } |
1226 | 0 | if (cc == 1) { |
1227 | 0 | push_str_modifier(hppa_ext, "co"); |
1228 | 0 | } |
1229 | 0 | break; |
1230 | 0 | case 0x08: |
1231 | 0 | case 0x09: |
1232 | 0 | case 0x0a: |
1233 | 0 | case 0x0b: |
1234 | 0 | case 0x0e: |
1235 | 0 | case 0x0f: |
1236 | 0 | if (cmplt == 1 && im5 == 0) { |
1237 | 0 | push_str_modifier(hppa_ext, "o"); |
1238 | 0 | } else { |
1239 | 0 | push_str_modifier( |
1240 | 0 | hppa_ext, |
1241 | 0 | short_ldst_compl_names[cmplt]); |
1242 | 0 | } |
1243 | 0 | if (cc == 1) { |
1244 | 0 | push_str_modifier(hppa_ext, "bc"); |
1245 | 0 | } else if (cc == 2) { |
1246 | 0 | push_str_modifier(hppa_ext, "sl"); |
1247 | 0 | } |
1248 | 0 | break; |
1249 | 0 | case 0x0c: |
1250 | 0 | case 0x0d: |
1251 | 0 | push_str_modifier(hppa_ext, |
1252 | 0 | short_bytes_compl_names[cmplt]); |
1253 | 0 | if (cc == 1) { |
1254 | 0 | push_str_modifier(hppa_ext, "bc"); |
1255 | 0 | } else if (cc == 2) { |
1256 | 0 | push_str_modifier(hppa_ext, "sl"); |
1257 | 0 | } |
1258 | 0 | break; |
1259 | 0 | default: |
1260 | 0 | break; |
1261 | 0 | } |
1262 | 0 | } |
1263 | 0 | } |
1264 | | |
1265 | | static bool decode_idxmem(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1266 | 0 | { |
1267 | 0 | uint32_t ext = get_insn_field(insn, 22, 25); |
1268 | 0 | uint32_t im5; |
1269 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
1270 | 0 | uint32_t b = get_insn_field(insn, 6, 10); |
1271 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
1272 | 0 | uint32_t s = get_insn_field(insn, 16, 17); |
1273 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
1274 | 0 | if (get_insn_bit(insn, 19) == 0) { |
1275 | 0 | switch (ext) { |
1276 | 0 | case 0x03: |
1277 | 0 | case 0x05: |
1278 | 0 | case 0x04: |
1279 | 0 | CREATE_GR_REG(MI, r); |
1280 | 0 | if (ext != 0x04) { |
1281 | 0 | CREATE_SR_REG(MI, s); |
1282 | 0 | } |
1283 | 0 | CREATE_GR_REG(MI, b); |
1284 | 0 | CREATE_GR_REG(MI, t); |
1285 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), |
1286 | 0 | ud->mode, -1); |
1287 | 0 | return true; |
1288 | 0 | default: |
1289 | 0 | break; |
1290 | 0 | } |
1291 | 0 | } else { |
1292 | 0 | switch (ext) { |
1293 | 0 | case 0x03: |
1294 | 0 | case 0x05: |
1295 | 0 | case 0x04: |
1296 | 0 | im5 = extract_5_load(insn); |
1297 | 0 | MCOperand_CreateImm0(MI, im5); |
1298 | 0 | if (ext != 0x04) { |
1299 | 0 | CREATE_SR_REG(MI, s); |
1300 | 0 | } |
1301 | 0 | CREATE_GR_REG(MI, b); |
1302 | 0 | CREATE_GR_REG(MI, t); |
1303 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), |
1304 | 0 | ud->mode, im5); |
1305 | 0 | return true; |
1306 | 0 | case 0x0b: |
1307 | 0 | case 0x0d: |
1308 | 0 | case 0x0f: |
1309 | 0 | im5 = extract_5_store(insn); |
1310 | 0 | CREATE_GR_REG(MI, r); |
1311 | 0 | MCOperand_CreateImm0(MI, im5); |
1312 | 0 | if (ext != 0x0f) { |
1313 | 0 | CREATE_SR_REG(MI, s); |
1314 | 0 | } |
1315 | 0 | CREATE_GR_REG(MI, b); |
1316 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), |
1317 | 0 | ud->mode, im5); |
1318 | 0 | return true; |
1319 | 0 | default: |
1320 | 0 | break; |
1321 | 0 | } |
1322 | 0 | } |
1323 | 0 | } |
1324 | 0 | if (get_insn_bit(insn, 19) == 0) { |
1325 | 0 | switch (ext) { |
1326 | 0 | case 0x00: |
1327 | 0 | case 0x01: |
1328 | 0 | case 0x02: |
1329 | 0 | case 0x07: |
1330 | 0 | case 0x06: |
1331 | 0 | CREATE_GR_REG(MI, r); |
1332 | 0 | if (ext != 0x06) { |
1333 | 0 | CREATE_SR_REG(MI, s); |
1334 | 0 | } |
1335 | 0 | CREATE_GR_REG(MI, b); |
1336 | 0 | CREATE_GR_REG(MI, t); |
1337 | 0 | break; |
1338 | 0 | default: |
1339 | 0 | return false; |
1340 | 0 | } |
1341 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); |
1342 | 0 | return true; |
1343 | 0 | } else { |
1344 | 0 | switch (ext) { |
1345 | 0 | case 0x00: |
1346 | 0 | case 0x01: |
1347 | 0 | case 0x02: |
1348 | 0 | case 0x07: |
1349 | 0 | case 0x06: |
1350 | 0 | im5 = extract_5_load(insn); |
1351 | 0 | MCOperand_CreateImm0(MI, im5); |
1352 | 0 | if (ext != 0x06) { |
1353 | 0 | CREATE_SR_REG(MI, s); |
1354 | 0 | } |
1355 | 0 | CREATE_GR_REG(MI, b); |
1356 | 0 | CREATE_GR_REG(MI, t); |
1357 | 0 | break; |
1358 | 0 | case 0x08: |
1359 | 0 | case 0x09: |
1360 | 0 | case 0x0a: |
1361 | 0 | case 0x0c: |
1362 | 0 | case 0x0e: |
1363 | 0 | im5 = extract_5_store(insn); |
1364 | 0 | CREATE_GR_REG(MI, r); |
1365 | 0 | MCOperand_CreateImm0(MI, im5); |
1366 | 0 | if (ext != 0x0e) { |
1367 | 0 | CREATE_SR_REG(MI, s); |
1368 | 0 | } |
1369 | 0 | CREATE_GR_REG(MI, b); |
1370 | 0 | break; |
1371 | 0 | default: |
1372 | 0 | return false; |
1373 | 0 | } |
1374 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
1375 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, im5); |
1376 | 0 | } else { |
1377 | 0 | fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); |
1378 | 0 | } |
1379 | 0 | return true; |
1380 | 0 | } |
1381 | 0 | } |
1382 | | |
1383 | | static void fill_ldst_dw_insn_name(MCInst *MI, uint32_t insn) |
1384 | 0 | { |
1385 | 0 | uint32_t opcode = insn >> 26; |
1386 | 0 | uint32_t ext = get_insn_bit(insn, 30); |
1387 | 0 | if (opcode == 0x14) { |
1388 | 0 | if (ext == 0) { |
1389 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDD); |
1390 | 0 | } else { |
1391 | 0 | MCInst_setOpcode(MI, HPPA_INS_FLDD); |
1392 | 0 | } |
1393 | 0 | } else { |
1394 | 0 | if (ext == 0) { |
1395 | 0 | MCInst_setOpcode(MI, HPPA_INS_STD); |
1396 | 0 | } else { |
1397 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSTD); |
1398 | 0 | } |
1399 | 0 | } |
1400 | 0 | } |
1401 | | |
1402 | | static void fill_ldst_dw_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) |
1403 | 0 | { |
1404 | 0 | uint32_t cmplt = (get_insn_bit(insn, 29) << 1) | get_insn_bit(insn, 28); |
1405 | 0 | if (cmplt == 1 && im == 0) { |
1406 | 0 | push_str_modifier(hppa_ext, "o"); |
1407 | 0 | } else { |
1408 | 0 | push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); |
1409 | 0 | } |
1410 | 0 | } |
1411 | | |
1412 | | static bool decode_ldst_dw(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1413 | 0 | { |
1414 | 0 | uint32_t opcode = insn >> 26; |
1415 | 0 | uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); |
1416 | 0 | im &= ~7; |
1417 | 0 | uint32_t ext = get_insn_bit(insn, 30); |
1418 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
1419 | 0 | uint32_t b = get_insn_field(insn, 6, 10); |
1420 | 0 | uint32_t s = get_insn_field(insn, 16, 17); |
1421 | 0 | if (opcode == HPPA_OP_TYPE_LOADDW) { |
1422 | 0 | MCOperand_CreateImm0(MI, im); |
1423 | 0 | CREATE_SR_REG(MI, s); |
1424 | 0 | CREATE_GR_REG(MI, b); |
1425 | 0 | if (ext == 0) { |
1426 | 0 | CREATE_GR_REG(MI, r); |
1427 | 0 | } else { |
1428 | 0 | CREATE_FPR_REG(MI, r); |
1429 | 0 | } |
1430 | 0 | } else { |
1431 | 0 | if (ext == 0) { |
1432 | 0 | CREATE_GR_REG(MI, r); |
1433 | 0 | } else { |
1434 | 0 | CREATE_FPR_REG(MI, r); |
1435 | 0 | } |
1436 | 0 | MCOperand_CreateImm0(MI, im); |
1437 | 0 | CREATE_SR_REG(MI, s); |
1438 | 0 | CREATE_GR_REG(MI, b); |
1439 | 0 | } |
1440 | 0 | fill_ldst_dw_mods(insn, HPPA_EXT_REF(MI), im); |
1441 | 0 | return true; |
1442 | 0 | } |
1443 | | |
1444 | | static void fill_ldst_w_insn_name(MCInst *MI, uint32_t insn) |
1445 | 0 | { |
1446 | 0 | uint32_t opcode = insn >> 26; |
1447 | 0 | uint32_t ext = get_insn_bit(insn, 29); |
1448 | 0 | if (opcode == 0x17) { |
1449 | 0 | if (ext == 0) { |
1450 | 0 | MCInst_setOpcode(MI, HPPA_INS_FLDW); |
1451 | 0 | } else { |
1452 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDW); |
1453 | 0 | } |
1454 | 0 | } else { |
1455 | 0 | if (ext == 0) { |
1456 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSTW); |
1457 | 0 | } else { |
1458 | 0 | MCInst_setOpcode(MI, HPPA_INS_STW); |
1459 | 0 | } |
1460 | 0 | } |
1461 | 0 | } |
1462 | | |
1463 | | static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, int32_t im) |
1464 | 0 | { |
1465 | 0 | if (im >= 0) { |
1466 | 0 | push_str_modifier(hppa_ext, "mb"); |
1467 | 0 | } else { |
1468 | 0 | push_str_modifier(hppa_ext, "ma"); |
1469 | 0 | } |
1470 | 0 | } |
1471 | | |
1472 | | static bool decode_ldst_w(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1473 | 0 | { |
1474 | 0 | uint32_t opcode = insn >> 26; |
1475 | 0 | uint32_t ext = get_insn_bit(insn, 29); |
1476 | 0 | int32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); |
1477 | 0 | im &= ~3; |
1478 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
1479 | 0 | uint32_t b = get_insn_field(insn, 6, 10); |
1480 | 0 | uint32_t s = get_insn_field(insn, 16, 17); |
1481 | 0 | if (opcode == 0x17) { |
1482 | 0 | MCOperand_CreateImm0(MI, im); |
1483 | 0 | CREATE_SR_REG(MI, s); |
1484 | 0 | CREATE_GR_REG(MI, b); |
1485 | 0 | if (ext == 1) { |
1486 | 0 | CREATE_GR_REG(MI, r); |
1487 | 0 | } else { |
1488 | 0 | CREATE_FPR_REG(MI, r); |
1489 | 0 | } |
1490 | 0 | } else { |
1491 | 0 | if (ext == 1) { |
1492 | 0 | CREATE_GR_REG(MI, r); |
1493 | 0 | } else { |
1494 | 0 | CREATE_FPR_REG(MI, r); |
1495 | 0 | } |
1496 | 0 | MCOperand_CreateImm0(MI, im); |
1497 | 0 | CREATE_SR_REG(MI, s); |
1498 | 0 | CREATE_GR_REG(MI, b); |
1499 | 0 | } |
1500 | 0 | if (ext == 1) { |
1501 | 0 | fill_ldst_w_mods(insn, HPPA_EXT_REF(MI), im); |
1502 | 0 | } |
1503 | 0 | return true; |
1504 | 0 | } |
1505 | | |
1506 | | static void fill_arith_imm_insn_name(MCInst *MI, uint32_t insn) |
1507 | 0 | { |
1508 | 0 | uint32_t opcode = insn >> 26; |
1509 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
1510 | 0 | switch (opcode) { |
1511 | 0 | case 0x2d: |
1512 | 0 | case 0x2c: |
1513 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDI); |
1514 | 0 | return; |
1515 | 0 | case 0x25: |
1516 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBI); |
1517 | 0 | return; |
1518 | 0 | default: |
1519 | 0 | break; |
1520 | 0 | } |
1521 | 0 | } |
1522 | 0 | if (get_insn_bit(insn, 20) == 0) { |
1523 | 0 | switch (opcode) { |
1524 | 0 | case 0x2d: |
1525 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDI); |
1526 | 0 | break; |
1527 | 0 | case 0x2c: |
1528 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIT); |
1529 | 0 | break; |
1530 | 0 | case 0x25: |
1531 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBI); |
1532 | 0 | break; |
1533 | 0 | default: |
1534 | 0 | break; |
1535 | 0 | } |
1536 | 0 | } else { |
1537 | 0 | switch (opcode) { |
1538 | 0 | case 0x2d: |
1539 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIO); |
1540 | 0 | break; |
1541 | 0 | case 0x2c: |
1542 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDITO); |
1543 | 0 | break; |
1544 | 0 | case 0x25: |
1545 | 0 | MCInst_setOpcode(MI, HPPA_INS_SUBIO); |
1546 | 0 | break; |
1547 | 0 | default: |
1548 | 0 | break; |
1549 | 0 | } |
1550 | 0 | } |
1551 | 0 | } |
1552 | | |
1553 | | static void fill_arith_imm_insn_mods(uint32_t insn, hppa_ext *hppa_ext, |
1554 | | cs_mode mode) |
1555 | 0 | { |
1556 | 0 | uint32_t opcode = insn >> 26; |
1557 | 0 | uint32_t cond = (get_insn_bit(insn, 19) << 3) | |
1558 | 0 | get_insn_field(insn, 16, 18); |
1559 | 0 | uint32_t cmplt = get_insn_bit(insn, 20); |
1560 | 0 | if (MODE_IS_HPPA_20(mode)) { |
1561 | 0 | if (cmplt == 1) { |
1562 | 0 | push_str_modifier(hppa_ext, "tsv"); |
1563 | 0 | } |
1564 | 0 | if (opcode == 0x2c) { |
1565 | 0 | push_str_modifier(hppa_ext, "tc"); |
1566 | 0 | } |
1567 | 0 | } |
1568 | 0 | switch (opcode) { |
1569 | 0 | case 0x2d: |
1570 | 0 | case 0x2c: |
1571 | 0 | push_str_modifier(hppa_ext, add_cond_names[cond]); |
1572 | 0 | break; |
1573 | 0 | case 0x25: |
1574 | 0 | push_str_modifier(hppa_ext, compare_cond_names[cond]); |
1575 | 0 | break; |
1576 | 0 | default: |
1577 | 0 | break; |
1578 | 0 | } |
1579 | 0 | } |
1580 | | |
1581 | | static bool decode_arith_imm(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1582 | 0 | { |
1583 | 0 | MCOperand_CreateImm0(MI, extract_11(insn)); |
1584 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
1585 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
1586 | 0 | fill_arith_imm_insn_mods(insn, HPPA_EXT_REF(MI), ud->mode); |
1587 | 0 | return true; |
1588 | 0 | } |
1589 | | |
1590 | | static void fill_shexdep0_insn_name(MCInst *MI, uint32_t insn) |
1591 | 0 | { |
1592 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1593 | 0 | uint32_t d = get_insn_bit(insn, 22); |
1594 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
1595 | 0 | switch (ext) { |
1596 | 0 | case 0x01: |
1597 | 0 | case 0x03: |
1598 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHRPD); |
1599 | 0 | return; |
1600 | 0 | case 0x02: |
1601 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHRPW); |
1602 | 0 | return; |
1603 | 0 | case 0x06: |
1604 | 0 | case 0x07: |
1605 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRW); |
1606 | 0 | return; |
1607 | 0 | case 0x00: |
1608 | 0 | if (d == 0) { |
1609 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHRPW); |
1610 | 0 | } else { |
1611 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHRPD); |
1612 | 0 | } |
1613 | 0 | return; |
1614 | 0 | case 0x04: |
1615 | 0 | case 0x05: |
1616 | 0 | if (d == 0) { |
1617 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRW); |
1618 | 0 | } else { |
1619 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRD); |
1620 | 0 | } |
1621 | 0 | return; |
1622 | 0 | default: |
1623 | 0 | break; |
1624 | 0 | } |
1625 | 0 | } |
1626 | 0 | switch (ext) { |
1627 | 0 | case 0x00: |
1628 | 0 | MCInst_setOpcode(MI, HPPA_INS_VSHD); |
1629 | 0 | break; |
1630 | 0 | case 0x02: |
1631 | 0 | MCInst_setOpcode(MI, HPPA_INS_SHD); |
1632 | 0 | break; |
1633 | 0 | case 0x04: |
1634 | 0 | MCInst_setOpcode(MI, HPPA_INS_VEXTRU); |
1635 | 0 | break; |
1636 | 0 | case 0x05: |
1637 | 0 | MCInst_setOpcode(MI, HPPA_INS_VEXTRS); |
1638 | 0 | break; |
1639 | 0 | case 0x06: |
1640 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRU); |
1641 | 0 | break; |
1642 | 0 | case 0x07: |
1643 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRS); |
1644 | 0 | break; |
1645 | 0 | default: |
1646 | 0 | break; |
1647 | 0 | } |
1648 | 0 | } |
1649 | | |
1650 | | static void fill_shexdep0_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) |
1651 | 0 | { |
1652 | 0 | uint32_t cond = get_insn_field(insn, 16, 18); |
1653 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1654 | 0 | uint32_t d = get_insn_bit(insn, 22); |
1655 | |
|
1656 | 0 | if (ext >= 0x04 && MODE_IS_HPPA_20(mode)) { |
1657 | 0 | push_str_modifier(hppa_ext, signed_unsigned_names[ext & 1]); |
1658 | 0 | } |
1659 | |
|
1660 | 0 | if (MODE_IS_HPPA_20(mode)) { |
1661 | 0 | switch (ext) { |
1662 | 0 | case 0x00: |
1663 | 0 | case 0x04: |
1664 | 0 | case 0x05: |
1665 | 0 | if (d == 0) { |
1666 | 0 | break; |
1667 | 0 | } |
1668 | | // fallthrough |
1669 | 0 | case 0x01: |
1670 | 0 | case 0x03: |
1671 | 0 | push_str_modifier(hppa_ext, shift_cond_64_names[cond]); |
1672 | 0 | return; |
1673 | 0 | default: |
1674 | 0 | break; |
1675 | 0 | } |
1676 | 0 | } |
1677 | 0 | push_str_modifier(hppa_ext, shift_cond_names[cond]); |
1678 | 0 | } |
1679 | | |
1680 | | static bool decode_shexdep0(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1681 | 0 | { |
1682 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1683 | 0 | uint32_t cp = get_insn_bit(insn, 20); |
1684 | 0 | uint32_t cpos = get_insn_field(insn, 22, 26); |
1685 | 0 | uint32_t sa = 63 - ((cp << 5) | cpos); |
1686 | 0 | uint32_t r1 = get_insn_field(insn, 11, 15); |
1687 | 0 | uint32_t r2 = get_insn_field(insn, 6, 10); |
1688 | 0 | uint32_t clen_t = get_insn_field(insn, 27, 31); |
1689 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
1690 | 0 | switch (ext) { |
1691 | 0 | case 0x01: |
1692 | 0 | case 0x00: |
1693 | 0 | case 0x03: |
1694 | 0 | case 0x02: |
1695 | 0 | CREATE_GR_REG(MI, r1); |
1696 | 0 | CREATE_GR_REG(MI, r2); |
1697 | 0 | if (ext <= 0x01) { |
1698 | 0 | CREATE_CR_REG(MI, 11); |
1699 | 0 | HPPA_EXT_REF(MI)->is_alternative = true; |
1700 | 0 | } else { |
1701 | 0 | MCOperand_CreateImm0(MI, sa); |
1702 | 0 | } |
1703 | 0 | CREATE_GR_REG(MI, clen_t); |
1704 | 0 | break; |
1705 | 0 | case 0x06: |
1706 | 0 | case 0x07: |
1707 | 0 | case 0x04: |
1708 | 0 | case 0x05: |
1709 | 0 | CREATE_GR_REG(MI, r2); |
1710 | 0 | if (ext >= 0x06) { |
1711 | 0 | MCOperand_CreateImm0(MI, cpos); |
1712 | 0 | } else { |
1713 | 0 | CREATE_CR_REG(MI, 11); |
1714 | 0 | HPPA_EXT_REF(MI)->is_alternative = true; |
1715 | 0 | } |
1716 | 0 | MCOperand_CreateImm0(MI, 32 - clen_t); |
1717 | 0 | CREATE_GR_REG(MI, r1); |
1718 | 0 | break; |
1719 | 0 | default: |
1720 | 0 | return false; |
1721 | 0 | } |
1722 | 0 | } else { |
1723 | 0 | switch (ext) { |
1724 | 0 | case 0x00: |
1725 | 0 | case 0x02: |
1726 | 0 | CREATE_GR_REG(MI, r1); |
1727 | 0 | CREATE_GR_REG(MI, r2); |
1728 | 0 | if (ext == 0x02) { |
1729 | 0 | MCOperand_CreateImm0(MI, 31 - cpos); |
1730 | 0 | } |
1731 | 0 | CREATE_GR_REG(MI, clen_t); |
1732 | 0 | break; |
1733 | 0 | case 0x04: |
1734 | 0 | case 0x05: |
1735 | 0 | case 0x06: |
1736 | 0 | case 0x07: |
1737 | 0 | CREATE_GR_REG(MI, r2); |
1738 | 0 | if (ext >= 0x06) { |
1739 | 0 | MCOperand_CreateImm0(MI, cpos); |
1740 | 0 | } |
1741 | 0 | MCOperand_CreateImm0(MI, 32 - clen_t); |
1742 | 0 | CREATE_GR_REG(MI, r1); |
1743 | 0 | break; |
1744 | 0 | default: |
1745 | 0 | return false; |
1746 | 0 | } |
1747 | 0 | } |
1748 | 0 | fill_shexdep0_mods(insn, HPPA_EXT_REF(MI), ud->mode); |
1749 | 0 | return true; |
1750 | 0 | } |
1751 | | |
1752 | | static void fill_shexdep1_insn_name(MCInst *MI, uint32_t insn) |
1753 | 0 | { |
1754 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1755 | 0 | uint32_t d = get_insn_bit(insn, 22); |
1756 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
1757 | 0 | switch (ext) { |
1758 | 0 | case 0x02: |
1759 | 0 | case 0x03: |
1760 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPW); |
1761 | 0 | break; |
1762 | 0 | case 0x06: |
1763 | 0 | case 0x07: |
1764 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPWI); |
1765 | 0 | break; |
1766 | 0 | case 0x00: |
1767 | 0 | case 0x01: |
1768 | 0 | if (d == 0) { |
1769 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPW); |
1770 | 0 | } else { |
1771 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPD); |
1772 | 0 | } |
1773 | 0 | break; |
1774 | 0 | case 0x04: |
1775 | 0 | case 0x05: |
1776 | 0 | if (d == 0) { |
1777 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPWI); |
1778 | 0 | } else { |
1779 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPDI); |
1780 | 0 | } |
1781 | 0 | break; |
1782 | 0 | default: |
1783 | 0 | break; |
1784 | 0 | } |
1785 | 0 | } else { |
1786 | 0 | switch (ext) { |
1787 | 0 | case 0x00: |
1788 | 0 | MCInst_setOpcode(MI, HPPA_INS_ZVDEP); |
1789 | 0 | break; |
1790 | 0 | case 0x01: |
1791 | 0 | MCInst_setOpcode(MI, HPPA_INS_VDEP); |
1792 | 0 | break; |
1793 | 0 | case 0x02: |
1794 | 0 | MCInst_setOpcode(MI, HPPA_INS_ZDEP); |
1795 | 0 | break; |
1796 | 0 | case 0x03: |
1797 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEP); |
1798 | 0 | break; |
1799 | 0 | case 0x04: |
1800 | 0 | MCInst_setOpcode(MI, HPPA_INS_ZVDEPI); |
1801 | 0 | break; |
1802 | 0 | case 0x05: |
1803 | 0 | MCInst_setOpcode(MI, HPPA_INS_VDEPI); |
1804 | 0 | break; |
1805 | 0 | case 0x06: |
1806 | 0 | MCInst_setOpcode(MI, HPPA_INS_ZDEPI); |
1807 | 0 | break; |
1808 | 0 | case 0x07: |
1809 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPI); |
1810 | 0 | break; |
1811 | 0 | default: |
1812 | 0 | break; |
1813 | 0 | } |
1814 | 0 | } |
1815 | 0 | } |
1816 | | |
1817 | | static void fill_shexdep1_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) |
1818 | 0 | { |
1819 | 0 | uint32_t cond = get_insn_field(insn, 16, 18); |
1820 | 0 | uint32_t cmplt = get_insn_bit(insn, 21); |
1821 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1822 | 0 | if (MODE_IS_HPPA_20(mode)) { |
1823 | 0 | if (cmplt == 0) { |
1824 | 0 | push_str_modifier(hppa_ext, "z"); |
1825 | 0 | } |
1826 | 0 | switch (ext) { |
1827 | 0 | case 0x00: |
1828 | 0 | case 0x01: |
1829 | 0 | case 0x04: |
1830 | 0 | case 0x05: |
1831 | 0 | push_str_modifier(hppa_ext, shift_cond_64_names[cond]); |
1832 | 0 | return; |
1833 | 0 | default: |
1834 | 0 | break; |
1835 | 0 | } |
1836 | 0 | } |
1837 | 0 | push_str_modifier(hppa_ext, shift_cond_names[cond]); |
1838 | 0 | } |
1839 | | |
1840 | | static bool decode_shexdep1(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1841 | 0 | { |
1842 | 0 | uint32_t ext = get_insn_field(insn, 19, 21); |
1843 | 0 | uint32_t cl = get_insn_bit(insn, 23); |
1844 | 0 | uint32_t clen = get_insn_field(insn, 27, 31); |
1845 | 0 | uint32_t len = (cl + 1) * 32 - clen; |
1846 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
1847 | 0 | uint32_t t = get_insn_field(insn, 6, 10); |
1848 | 0 | uint32_t cpos = get_insn_field(insn, 22, 26); |
1849 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
1850 | 0 | switch (ext) { |
1851 | 0 | case 0x02: |
1852 | 0 | case 0x03: |
1853 | 0 | case 0x06: |
1854 | 0 | case 0x07: |
1855 | 0 | if (ext >= 0x06) { |
1856 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); |
1857 | 0 | } else { |
1858 | 0 | CREATE_GR_REG(MI, r); |
1859 | 0 | } |
1860 | 0 | MCOperand_CreateImm0(MI, 31 - cpos); |
1861 | 0 | MCOperand_CreateImm0(MI, 32 - clen); |
1862 | 0 | CREATE_GR_REG(MI, t); |
1863 | 0 | break; |
1864 | 0 | case 0x00: |
1865 | 0 | case 0x01: |
1866 | 0 | case 0x04: |
1867 | 0 | case 0x05: |
1868 | 0 | if (ext >= 0x04) { |
1869 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); |
1870 | 0 | } else { |
1871 | 0 | CREATE_GR_REG(MI, r); |
1872 | 0 | } |
1873 | 0 | CREATE_CR_REG(MI, 11); |
1874 | 0 | HPPA_EXT_REF(MI)->is_alternative = true; |
1875 | 0 | MCOperand_CreateImm0(MI, len); |
1876 | 0 | CREATE_GR_REG(MI, t); |
1877 | 0 | break; |
1878 | 0 | default: |
1879 | 0 | break; |
1880 | 0 | } |
1881 | 0 | } else { |
1882 | 0 | switch (ext) { |
1883 | 0 | case 0x00: |
1884 | 0 | case 0x01: |
1885 | 0 | case 0x02: |
1886 | 0 | case 0x03: |
1887 | 0 | CREATE_GR_REG(MI, r); |
1888 | 0 | if (ext >= 0x02) { |
1889 | 0 | MCOperand_CreateImm0(MI, 31 - cpos); |
1890 | 0 | } |
1891 | 0 | MCOperand_CreateImm0(MI, 32 - clen); |
1892 | 0 | CREATE_GR_REG(MI, t); |
1893 | 0 | break; |
1894 | 0 | case 0x04: |
1895 | 0 | case 0x05: |
1896 | 0 | case 0x06: |
1897 | 0 | case 0x07: |
1898 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); |
1899 | 0 | if (ext >= 0x06) { |
1900 | 0 | MCOperand_CreateImm0(MI, 31 - cpos); |
1901 | 0 | } |
1902 | 0 | MCOperand_CreateImm0(MI, 32 - clen); |
1903 | 0 | CREATE_GR_REG(MI, t); |
1904 | 0 | break; |
1905 | 0 | default: |
1906 | 0 | break; |
1907 | 0 | } |
1908 | 0 | } |
1909 | 0 | fill_shexdep1_mods(insn, HPPA_EXT_REF(MI), ud->mode); |
1910 | 0 | return true; |
1911 | 0 | } |
1912 | | |
1913 | | static void fill_shexdep2_mods(uint32_t insn, hppa_ext *hppa_ext) |
1914 | 0 | { |
1915 | 0 | uint32_t cmplt = get_insn_bit(insn, 21); |
1916 | 0 | uint32_t cond = get_insn_field(insn, 16, 18); |
1917 | 0 | push_str_modifier(hppa_ext, signed_unsigned_names[cmplt]); |
1918 | 0 | push_str_modifier(hppa_ext, shift_cond_64_names[cond]); |
1919 | 0 | } |
1920 | | |
1921 | | static bool decode_shexdep2(MCInst *MI, uint32_t insn) |
1922 | 0 | { |
1923 | 0 | uint32_t pos = (get_insn_bit(insn, 20) << 5) | |
1924 | 0 | get_insn_field(insn, 22, 26); |
1925 | 0 | uint32_t cl = get_insn_bit(insn, 19); |
1926 | 0 | uint32_t clen = get_insn_field(insn, 27, 31); |
1927 | 0 | uint32_t len = (cl + 1) * 32 - clen; |
1928 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
1929 | 0 | MCOperand_CreateImm0(MI, pos); |
1930 | 0 | MCOperand_CreateImm0(MI, len); |
1931 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
1932 | 0 | fill_shexdep2_mods(insn, HPPA_EXT_REF(MI)); |
1933 | 0 | return true; |
1934 | 0 | } |
1935 | | |
1936 | | static void fill_shexdep3_mods(uint32_t insn, hppa_ext *hppa_ext) |
1937 | 0 | { |
1938 | 0 | uint32_t cmplt = get_insn_bit(insn, 21); |
1939 | 0 | uint32_t cond = get_insn_field(insn, 16, 18); |
1940 | 0 | if (cmplt == 0) { |
1941 | 0 | push_str_modifier(hppa_ext, "z"); |
1942 | 0 | } |
1943 | 0 | push_str_modifier(hppa_ext, shift_cond_64_names[cond]); |
1944 | 0 | } |
1945 | | |
1946 | | static bool decode_shexdep3(const cs_struct *ud, MCInst *MI, uint32_t insn) |
1947 | 0 | { |
1948 | 0 | uint32_t opcode = insn >> 26; |
1949 | 0 | if (opcode == HPPA_OP_TYPE_SHEXDEP3) { |
1950 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPD); |
1951 | 0 | } else { |
1952 | 0 | MCInst_setOpcode(MI, HPPA_INS_DEPDI); |
1953 | 0 | } |
1954 | 0 | uint32_t pos = 63 - ((get_insn_bit(insn, 20) << 5) | |
1955 | 0 | get_insn_field(insn, 22, 26)); |
1956 | 0 | uint32_t cl = get_insn_bit(insn, 19); |
1957 | 0 | uint32_t clen = get_insn_field(insn, 27, 31); |
1958 | 0 | uint32_t len = (cl + 1) * 32 - clen; |
1959 | 0 | if (opcode == HPPA_OP_TYPE_SHEXDEP3) { |
1960 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
1961 | 0 | } else { |
1962 | 0 | MCOperand_CreateImm0( |
1963 | 0 | MI, LowSignExtend64(get_insn_field(insn, 11, 15), 5)); |
1964 | 0 | } |
1965 | 0 | MCOperand_CreateImm0(MI, pos); |
1966 | 0 | MCOperand_CreateImm0(MI, len); |
1967 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
1968 | 0 | fill_shexdep3_mods(insn, HPPA_EXT_REF(MI)); |
1969 | 0 | return true; |
1970 | 0 | } |
1971 | | |
1972 | | static void fill_multmed_insn_name(MCInst *MI, uint32_t insn) |
1973 | 0 | { |
1974 | 0 | uint32_t bit_16 = get_insn_bit(insn, 16); |
1975 | 0 | uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | |
1976 | 0 | get_insn_field(insn, 20, 21); |
1977 | 0 | if (bit_16 == 0) { |
1978 | 0 | MCInst_setOpcode(MI, HPPA_INS_PERMH); |
1979 | 0 | return; |
1980 | 0 | } |
1981 | 0 | switch (ext) { |
1982 | 0 | case 0x02: |
1983 | 0 | MCInst_setOpcode(MI, HPPA_INS_HSHL); |
1984 | 0 | break; |
1985 | 0 | case 0x0a: |
1986 | 0 | case 0x0b: |
1987 | 0 | MCInst_setOpcode(MI, HPPA_INS_HSHR); |
1988 | 0 | break; |
1989 | 0 | case 0x00: |
1990 | 0 | case 0x08: |
1991 | 0 | MCInst_setOpcode(MI, HPPA_INS_MIXW); |
1992 | 0 | break; |
1993 | 0 | case 0x01: |
1994 | 0 | case 0x09: |
1995 | 0 | MCInst_setOpcode(MI, HPPA_INS_MIXH); |
1996 | 0 | break; |
1997 | 0 | default: |
1998 | 0 | break; |
1999 | 0 | } |
2000 | 0 | } |
2001 | | |
2002 | | static void fill_multmed_mods(uint32_t insn, hppa_ext *hppa_ext) |
2003 | 0 | { |
2004 | 0 | uint32_t bit_16 = get_insn_bit(insn, 16); |
2005 | 0 | uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | |
2006 | 0 | get_insn_field(insn, 20, 21); |
2007 | 0 | uint32_t eb = get_insn_field(insn, 20, 21); |
2008 | 0 | uint32_t ea = get_insn_field(insn, 17, 18); |
2009 | 0 | if (bit_16 == 0) { |
2010 | 0 | char c[5]; |
2011 | 0 | snprintf(c, sizeof(c), "%d%d%d%d", get_insn_field(insn, 17, 18), |
2012 | 0 | get_insn_field(insn, 20, 21), |
2013 | 0 | get_insn_field(insn, 22, 23), |
2014 | 0 | get_insn_field(insn, 24, 25)); |
2015 | 0 | push_str_modifier(hppa_ext, c); |
2016 | 0 | return; |
2017 | 0 | } |
2018 | 0 | switch (ext) { |
2019 | 0 | case 0x0a: |
2020 | 0 | case 0x0b: |
2021 | 0 | if (eb >= 2) { |
2022 | 0 | push_str_modifier(hppa_ext, |
2023 | 0 | signed_unsigned_names[eb - 2]); |
2024 | 0 | } |
2025 | 0 | break; |
2026 | 0 | case 0x00: |
2027 | 0 | case 0x08: |
2028 | 0 | case 0x01: |
2029 | 0 | case 0x09: |
2030 | 0 | if (ea == 2) { |
2031 | 0 | push_str_modifier(hppa_ext, "l"); |
2032 | 0 | } else if (ea == 0) { |
2033 | 0 | push_str_modifier(hppa_ext, "r"); |
2034 | 0 | } |
2035 | 0 | break; |
2036 | 0 | default: |
2037 | 0 | break; |
2038 | 0 | } |
2039 | 0 | } |
2040 | | |
2041 | | static bool decode_multmed(MCInst *MI, uint32_t insn) |
2042 | 0 | { |
2043 | 0 | uint32_t bit_16 = get_insn_bit(insn, 16); |
2044 | 0 | uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | |
2045 | 0 | get_insn_field(insn, 20, 21); |
2046 | 0 | uint32_t r1 = get_insn_field(insn, 11, 15); |
2047 | 0 | uint32_t r2 = get_insn_field(insn, 6, 10); |
2048 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
2049 | 0 | uint32_t sa = get_insn_field(insn, 22, 25); |
2050 | 0 | if (bit_16 == 0) { |
2051 | 0 | CREATE_GR_REG(MI, r2); |
2052 | 0 | CREATE_GR_REG(MI, t); |
2053 | 0 | goto success; |
2054 | 0 | } |
2055 | 0 | switch (ext) { |
2056 | 0 | case 0x02: |
2057 | 0 | case 0x0a: |
2058 | 0 | case 0x0b: |
2059 | 0 | if (ext >= 0x0a) { |
2060 | 0 | CREATE_GR_REG(MI, r2); |
2061 | 0 | } else { |
2062 | 0 | CREATE_GR_REG(MI, r1); |
2063 | 0 | } |
2064 | 0 | MCOperand_CreateImm0(MI, sa); |
2065 | 0 | CREATE_GR_REG(MI, t); |
2066 | 0 | break; |
2067 | 0 | case 0x00: |
2068 | 0 | case 0x08: |
2069 | 0 | case 0x01: |
2070 | 0 | case 0x09: |
2071 | 0 | CREATE_GR_REG(MI, r1); |
2072 | 0 | CREATE_GR_REG(MI, r2); |
2073 | 0 | CREATE_GR_REG(MI, t); |
2074 | 0 | break; |
2075 | 0 | default: |
2076 | 0 | return false; |
2077 | 0 | } |
2078 | 0 | success: |
2079 | 0 | fill_multmed_mods(insn, HPPA_EXT_REF(MI)); |
2080 | 0 | return true; |
2081 | 0 | } |
2082 | | |
2083 | | static void fill_branch_insn_name(MCInst *MI, uint32_t insn) |
2084 | 0 | { |
2085 | 0 | uint32_t ext = get_insn_field(insn, 16, 18); |
2086 | 0 | uint32_t bit_19 = get_insn_bit(insn, 19); |
2087 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
2088 | 0 | if (insn == 0xe8004005) { |
2089 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLRBTS); |
2090 | 0 | return; |
2091 | 0 | } else if (insn == 0xe8004001) { |
2092 | 0 | MCInst_setOpcode(MI, HPPA_INS_PUSHNOM); |
2093 | 0 | return; |
2094 | 0 | } |
2095 | | |
2096 | 0 | switch (ext) { |
2097 | 0 | case 0x00: |
2098 | 0 | case 0x01: |
2099 | 0 | case 0x04: |
2100 | 0 | case 0x05: |
2101 | 0 | MCInst_setOpcode(MI, HPPA_INS_B); |
2102 | 0 | return; |
2103 | 0 | case 0x06: |
2104 | 0 | if (bit_19 == 0) { |
2105 | 0 | MCInst_setOpcode(MI, HPPA_INS_BV); |
2106 | 0 | } else { |
2107 | 0 | MCInst_setOpcode(MI, HPPA_INS_BVE); |
2108 | 0 | } |
2109 | 0 | return; |
2110 | 0 | case 0x07: |
2111 | 0 | if (bit_19 == 1) { |
2112 | 0 | MCInst_setOpcode(MI, HPPA_INS_BVE); |
2113 | 0 | } |
2114 | 0 | return; |
2115 | 0 | case 0x02: |
2116 | 0 | if (get_insn_field(insn, 19, 29) == 0 && |
2117 | 0 | get_insn_bit(insn, 31) == 0) { |
2118 | 0 | MCInst_setOpcode(MI, HPPA_INS_BLR); |
2119 | 0 | return; |
2120 | 0 | } |
2121 | 0 | if (get_insn_field(insn, 19, 31) == 1) { |
2122 | 0 | MCInst_setOpcode(MI, HPPA_INS_PUSHBTS); |
2123 | 0 | return; |
2124 | 0 | } |
2125 | 0 | if (bit_19 == 0 && |
2126 | 0 | get_insn_field(insn, 29, 31) == 0x5) { |
2127 | 0 | MCInst_setOpcode(MI, HPPA_INS_POPBTS); |
2128 | 0 | return; |
2129 | 0 | } |
2130 | 0 | return; |
2131 | 0 | default: |
2132 | 0 | return; |
2133 | 0 | } |
2134 | 0 | } |
2135 | 0 | switch (ext) { |
2136 | 0 | case 0x00: |
2137 | 0 | MCInst_setOpcode(MI, HPPA_INS_BL); |
2138 | 0 | break; |
2139 | 0 | case 0x01: |
2140 | 0 | MCInst_setOpcode(MI, HPPA_INS_GATE); |
2141 | 0 | break; |
2142 | 0 | case 0x02: |
2143 | 0 | MCInst_setOpcode(MI, HPPA_INS_BLR); |
2144 | 0 | break; |
2145 | 0 | case 0x06: |
2146 | 0 | MCInst_setOpcode(MI, HPPA_INS_BV); |
2147 | 0 | break; |
2148 | 0 | default: |
2149 | 0 | break; |
2150 | 0 | } |
2151 | 0 | } |
2152 | | |
2153 | | static void fill_branch_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) |
2154 | 0 | { |
2155 | 0 | uint32_t ext = get_insn_field(insn, 16, 18); |
2156 | 0 | uint32_t n = get_insn_bit(insn, 30); |
2157 | 0 | uint32_t p = get_insn_bit(insn, 31); |
2158 | 0 | if (MODE_IS_HPPA_20(mode)) { |
2159 | 0 | switch (ext) { |
2160 | 0 | case 0x00: |
2161 | 0 | case 0x05: |
2162 | 0 | push_str_modifier(hppa_ext, "l"); |
2163 | | // fallthrough |
2164 | 0 | case 0x02: |
2165 | 0 | break; |
2166 | 0 | case 0x01: |
2167 | 0 | push_str_modifier(hppa_ext, "gate"); |
2168 | 0 | break; |
2169 | 0 | case 0x04: |
2170 | 0 | push_str_modifier(hppa_ext, "l"); |
2171 | 0 | push_str_modifier(hppa_ext, "push"); |
2172 | 0 | break; |
2173 | 0 | case 0x06: |
2174 | 0 | case 0x07: |
2175 | 0 | if (get_insn_bit(insn, 19) == 0) { |
2176 | 0 | break; |
2177 | 0 | } |
2178 | 0 | if (ext == 7) { |
2179 | 0 | push_str_modifier(hppa_ext, "l"); |
2180 | 0 | hppa_ext->is_alternative = true; |
2181 | 0 | if (p == 1) { |
2182 | 0 | push_str_modifier(hppa_ext, "push"); |
2183 | 0 | } |
2184 | 0 | } else { |
2185 | 0 | if (p == 1) { |
2186 | 0 | push_str_modifier(hppa_ext, "pop"); |
2187 | 0 | } |
2188 | 0 | } |
2189 | 0 | break; |
2190 | 0 | default: |
2191 | 0 | return; |
2192 | 0 | } |
2193 | 0 | } |
2194 | 0 | if (n == 1) { |
2195 | 0 | push_str_modifier(hppa_ext, "n"); |
2196 | 0 | } |
2197 | 0 | } |
2198 | | |
2199 | | static bool decode_branch(const cs_struct *ud, MCInst *MI, uint32_t insn) |
2200 | 0 | { |
2201 | 0 | uint32_t ext = get_insn_field(insn, 16, 18); |
2202 | 0 | uint32_t t = get_insn_field(insn, 6, 10); |
2203 | 0 | uint32_t i = get_insn_field(insn, 20, 28); |
2204 | 0 | uint32_t r = get_insn_field(insn, 11, 15); |
2205 | 0 | uint32_t bit_19 = get_insn_bit(insn, 19); |
2206 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
2207 | 0 | if (insn == 0xe8004005 || insn == 0xe8004001) { |
2208 | 0 | return true; |
2209 | 0 | } |
2210 | | |
2211 | 0 | switch (ext) { |
2212 | 0 | case 0x01: |
2213 | 0 | case 0x00: |
2214 | 0 | MCOperand_CreateImm0(MI, extract_17(insn)); |
2215 | 0 | CREATE_GR_REG(MI, t); |
2216 | 0 | break; |
2217 | 0 | case 0x04: |
2218 | 0 | case 0x05: |
2219 | 0 | MCOperand_CreateImm0(MI, extract_22(insn)); |
2220 | 0 | CREATE_GR_REG(MI, t); |
2221 | 0 | break; |
2222 | 0 | case 0x02: |
2223 | 0 | if (bit_19 == 1) { |
2224 | 0 | return false; |
2225 | 0 | } |
2226 | 0 | if (get_insn_field(insn, 20, 31) == 1 && t == 0) { |
2227 | 0 | CREATE_GR_REG(MI, r); |
2228 | 0 | break; |
2229 | 0 | } |
2230 | 0 | if (r == 0 && t == 0 && |
2231 | 0 | get_insn_field(insn, 29, 31) == 0x5) { |
2232 | 0 | MCOperand_CreateImm0(MI, i); |
2233 | 0 | break; |
2234 | 0 | } |
2235 | 0 | if (get_insn_bit(insn, 31) == 0 && |
2236 | 0 | get_insn_field(insn, 19, 29) == 0) { |
2237 | 0 | CREATE_GR_REG(MI, r); |
2238 | 0 | CREATE_GR_REG(MI, t); |
2239 | 0 | break; |
2240 | 0 | } |
2241 | 0 | return false; |
2242 | 0 | case 0x06: |
2243 | 0 | if (bit_19 == 0) { |
2244 | 0 | CREATE_GR_REG(MI, r); |
2245 | 0 | } |
2246 | 0 | CREATE_GR_REG(MI, t); |
2247 | 0 | break; |
2248 | 0 | case 0x07: |
2249 | 0 | if (bit_19 == 1) { |
2250 | 0 | CREATE_GR_REG(MI, t); |
2251 | 0 | CREATE_GR_REG(MI, 2); |
2252 | 0 | break; |
2253 | 0 | } |
2254 | | // fallthrough |
2255 | 0 | default: |
2256 | 0 | return false; |
2257 | 0 | } |
2258 | 0 | fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); |
2259 | 0 | return true; |
2260 | 0 | } else { |
2261 | 0 | switch (ext) { |
2262 | 0 | case 0x00: |
2263 | 0 | case 0x01: |
2264 | 0 | MCOperand_CreateImm0(MI, extract_17(insn)); |
2265 | 0 | CREATE_GR_REG(MI, t); |
2266 | 0 | break; |
2267 | 0 | case 0x02: |
2268 | 0 | case 0x06: |
2269 | 0 | CREATE_GR_REG(MI, r); |
2270 | 0 | CREATE_GR_REG(MI, t); |
2271 | 0 | break; |
2272 | 0 | default: |
2273 | 0 | return false; |
2274 | 0 | } |
2275 | 0 | fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); |
2276 | 0 | return true; |
2277 | 0 | } |
2278 | 0 | } |
2279 | | |
2280 | | static void fill_corpdw_insn_name(MCInst *MI, uint32_t insn) |
2281 | 0 | { |
2282 | 0 | uint32_t ext = (get_insn_field(insn, 19, 19) << 1) | |
2283 | 0 | get_insn_field(insn, 22, 22); |
2284 | 0 | uint32_t opcode = insn >> 26; |
2285 | 0 | uint32_t uid = get_insn_field(insn, 23, 25); |
2286 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
2287 | 0 | if (opcode == 0x09) { |
2288 | 0 | switch (ext) { |
2289 | 0 | case 0x00: |
2290 | 0 | case 0x02: |
2291 | 0 | if (uid <= 0x01) { |
2292 | 0 | MCInst_setOpcode(MI, HPPA_INS_FLDW); |
2293 | 0 | } else { |
2294 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDW); |
2295 | 0 | } |
2296 | 0 | return; |
2297 | 0 | case 0x01: |
2298 | 0 | case 0x03: |
2299 | 0 | if (uid <= 0x01) { |
2300 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSTW); |
2301 | 0 | } else { |
2302 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTW); |
2303 | 0 | } |
2304 | 0 | return; |
2305 | 0 | default: |
2306 | 0 | break; |
2307 | 0 | } |
2308 | 0 | } else { |
2309 | 0 | switch (ext) { |
2310 | 0 | case 0x00: |
2311 | 0 | case 0x02: |
2312 | 0 | if (uid == 0x00) { |
2313 | 0 | MCInst_setOpcode(MI, HPPA_INS_FLDD); |
2314 | 0 | } else { |
2315 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDD); |
2316 | 0 | } |
2317 | 0 | return; |
2318 | 0 | case 0x01: |
2319 | 0 | case 0x03: |
2320 | 0 | if (uid == 0x00) { |
2321 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSTD); |
2322 | 0 | } else { |
2323 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTD); |
2324 | 0 | } |
2325 | 0 | return; |
2326 | 0 | default: |
2327 | 0 | break; |
2328 | 0 | } |
2329 | 0 | } |
2330 | 0 | } |
2331 | 0 | if (opcode == 0x09) { |
2332 | 0 | switch (ext) { |
2333 | 0 | case 0x00: |
2334 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDWX); |
2335 | 0 | break; |
2336 | 0 | case 0x01: |
2337 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTWX); |
2338 | 0 | break; |
2339 | 0 | case 0x02: |
2340 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDWS); |
2341 | 0 | break; |
2342 | 0 | case 0x03: |
2343 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTWS); |
2344 | 0 | break; |
2345 | 0 | default: |
2346 | 0 | break; |
2347 | 0 | } |
2348 | 0 | } else { |
2349 | 0 | switch (ext) { |
2350 | 0 | case 0x00: |
2351 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDDX); |
2352 | 0 | break; |
2353 | 0 | case 0x01: |
2354 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTDX); |
2355 | 0 | break; |
2356 | 0 | case 0x02: |
2357 | 0 | MCInst_setOpcode(MI, HPPA_INS_CLDDS); |
2358 | 0 | break; |
2359 | 0 | case 0x03: |
2360 | 0 | MCInst_setOpcode(MI, HPPA_INS_CSTDS); |
2361 | 0 | break; |
2362 | 0 | default: |
2363 | 0 | break; |
2364 | 0 | } |
2365 | 0 | } |
2366 | 0 | } |
2367 | | |
2368 | | static inline bool coprdw_has_uid_mod(uint32_t opcode, uint32_t uid) |
2369 | 0 | { |
2370 | 0 | return !((opcode == HPPA_OP_TYPE_COPRW && uid <= 0x01) || |
2371 | 0 | (opcode == HPPA_OP_TYPE_COPRDW && uid == 0x00)); |
2372 | 0 | } |
2373 | | |
2374 | | static void fill_corpdw_mods(uint32_t insn, uint32_t im, hppa_ext *hppa_ext, |
2375 | | cs_mode mode) |
2376 | 0 | { |
2377 | 0 | uint32_t uid = get_insn_field(insn, 23, 25); |
2378 | 0 | uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); |
2379 | 0 | uint32_t cc = get_insn_field(insn, 20, 21); |
2380 | 0 | uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); |
2381 | 0 | uint32_t opcode = insn >> 26; |
2382 | |
|
2383 | 0 | if (coprdw_has_uid_mod(opcode, uid)) { |
2384 | 0 | push_int_modifier(hppa_ext, uid); |
2385 | 0 | } |
2386 | 0 | if (CMPLT_HAS_MODIFY_BIT(cmplt)) { |
2387 | 0 | hppa_ext->b_writeble = true; |
2388 | 0 | } |
2389 | |
|
2390 | 0 | switch (ext) { |
2391 | 0 | case 0x00: |
2392 | 0 | case 0x01: |
2393 | 0 | push_str_modifier(hppa_ext, index_compl_names[cmplt]); |
2394 | 0 | break; |
2395 | 0 | case 0x02: |
2396 | 0 | case 0x03: |
2397 | 0 | if (MODE_IS_HPPA_20(mode)) { |
2398 | 0 | if (cmplt == 1 && im == 0) { |
2399 | 0 | push_str_modifier(hppa_ext, "o"); |
2400 | 0 | break; |
2401 | 0 | } |
2402 | 0 | } |
2403 | 0 | push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); |
2404 | 0 | break; |
2405 | 0 | default: |
2406 | 0 | break; |
2407 | 0 | } |
2408 | 0 | if ((ext & 1) == 1 && cc == 1) { |
2409 | 0 | push_str_modifier(hppa_ext, "bc"); |
2410 | 0 | } |
2411 | 0 | if (cc == 2) { |
2412 | 0 | push_str_modifier(hppa_ext, "sl"); |
2413 | 0 | } |
2414 | 0 | } |
2415 | | |
2416 | | static bool decode_corpdw(const cs_struct *ud, MCInst *MI, uint32_t insn) |
2417 | 0 | { |
2418 | 0 | uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); |
2419 | 0 | uint32_t x = get_insn_field(insn, 11, 15); |
2420 | 0 | uint32_t b = get_insn_field(insn, 6, 10); |
2421 | 0 | uint32_t s = get_insn_field(insn, 16, 17); |
2422 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
2423 | 0 | uint32_t opcode = MCInst_getOpcode(MI); |
2424 | 0 | switch (ext) { |
2425 | 0 | case 0x00: |
2426 | 0 | case 0x02: |
2427 | 0 | if (ext == 0x02) { |
2428 | 0 | x = LowSignExtend64(x, 5); |
2429 | 0 | MCOperand_CreateImm0(MI, x); |
2430 | 0 | } else { |
2431 | 0 | CREATE_GR_REG(MI, x); |
2432 | 0 | } |
2433 | 0 | CREATE_SR_REG(MI, s); |
2434 | 0 | CREATE_GR_REG(MI, b); |
2435 | 0 | if (opcode == HPPA_INS_FLDW || opcode == HPPA_INS_FLDD) { |
2436 | 0 | CREATE_FPR_REG(MI, t); |
2437 | 0 | } else { |
2438 | 0 | CREATE_GR_REG(MI, t); |
2439 | 0 | } |
2440 | 0 | break; |
2441 | 0 | case 0x01: |
2442 | 0 | case 0x03: |
2443 | 0 | if (opcode == HPPA_INS_FSTW || opcode == HPPA_INS_FSTD) { |
2444 | 0 | CREATE_FPR_REG(MI, t); |
2445 | 0 | } else { |
2446 | 0 | CREATE_GR_REG(MI, t); |
2447 | 0 | } |
2448 | 0 | if (ext == 0x03) { |
2449 | 0 | x = LowSignExtend64(x, 5); |
2450 | 0 | MCOperand_CreateImm0(MI, x); |
2451 | 0 | } else { |
2452 | 0 | CREATE_GR_REG(MI, x); |
2453 | 0 | } |
2454 | 0 | CREATE_SR_REG(MI, s); |
2455 | 0 | CREATE_GR_REG(MI, b); |
2456 | 0 | break; |
2457 | 0 | default: |
2458 | 0 | break; |
2459 | 0 | } |
2460 | 0 | fill_corpdw_mods(insn, x, HPPA_EXT_REF(MI), ud->mode); |
2461 | 0 | return true; |
2462 | 0 | } |
2463 | | |
2464 | | static void fill_spop_insn_name(MCInst *MI, uint32_t insn) |
2465 | 0 | { |
2466 | 0 | uint32_t ext = get_insn_field(insn, 21, 22); |
2467 | 0 | switch (ext) { |
2468 | 0 | case 0x00: |
2469 | 0 | MCInst_setOpcode(MI, HPPA_INS_SPOP0); |
2470 | 0 | break; |
2471 | 0 | case 0x01: |
2472 | 0 | MCInst_setOpcode(MI, HPPA_INS_SPOP1); |
2473 | 0 | break; |
2474 | 0 | case 0x02: |
2475 | 0 | MCInst_setOpcode(MI, HPPA_INS_SPOP2); |
2476 | 0 | break; |
2477 | 0 | case 0x03: |
2478 | 0 | MCInst_setOpcode(MI, HPPA_INS_SPOP3); |
2479 | 0 | break; |
2480 | 0 | default: |
2481 | 0 | break; |
2482 | 0 | } |
2483 | 0 | } |
2484 | | |
2485 | | static void fill_spop_mods(uint32_t insn, uint32_t ext, hppa_ext *hppa_ext) |
2486 | 0 | { |
2487 | 0 | uint32_t sfu = get_insn_field(insn, 23, 25); |
2488 | 0 | uint32_t n = get_insn_field(insn, 26, 26); |
2489 | 0 | uint32_t sop; |
2490 | |
|
2491 | 0 | push_int_modifier(hppa_ext, sfu); |
2492 | 0 | switch (ext) { |
2493 | 0 | case 0x00: |
2494 | 0 | sop = (get_insn_field(insn, 6, 20) << 5) | |
2495 | 0 | get_insn_field(insn, 27, 31); |
2496 | 0 | break; |
2497 | 0 | case 0x01: |
2498 | 0 | sop = get_insn_field(insn, 6, 20); |
2499 | 0 | break; |
2500 | 0 | case 0x02: |
2501 | 0 | sop = (get_insn_field(insn, 11, 20) << 5) | |
2502 | 0 | get_insn_field(insn, 27, 31); |
2503 | 0 | break; |
2504 | 0 | case 0x03: |
2505 | 0 | sop = (get_insn_field(insn, 16, 20) << 5) | |
2506 | 0 | get_insn_field(insn, 27, 31); |
2507 | 0 | break; |
2508 | 0 | default: |
2509 | 0 | return; |
2510 | 0 | } |
2511 | 0 | push_int_modifier(hppa_ext, sop); |
2512 | 0 | if (n == 1) { |
2513 | 0 | push_str_modifier(hppa_ext, "n"); |
2514 | 0 | } |
2515 | 0 | } |
2516 | | |
2517 | | static bool decode_spop(const cs_struct *ud, MCInst *MI, uint32_t insn) |
2518 | 0 | { |
2519 | 0 | uint32_t ext = get_insn_field(insn, 21, 22); |
2520 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
2521 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
2522 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
2523 | 0 | switch (ext) { |
2524 | 0 | case 0x00: |
2525 | 0 | break; |
2526 | 0 | case 0x01: |
2527 | 0 | CREATE_GR_REG(MI, t); |
2528 | 0 | break; |
2529 | 0 | case 0x02: |
2530 | 0 | CREATE_GR_REG(MI, r1); |
2531 | 0 | break; |
2532 | 0 | case 0x03: |
2533 | 0 | CREATE_GR_REG(MI, r2); |
2534 | 0 | CREATE_GR_REG(MI, r1); |
2535 | 0 | break; |
2536 | 0 | default: |
2537 | 0 | return false; |
2538 | 0 | } |
2539 | 0 | fill_spop_mods(insn, ext, HPPA_EXT_REF(MI)); |
2540 | 0 | return true; |
2541 | 0 | } |
2542 | | |
2543 | | static void fill_copr_insn_name(MCInst *MI, uint32_t insn) |
2544 | 0 | { |
2545 | 0 | uint32_t class = get_insn_field(insn, 21, 22); |
2546 | 0 | uint32_t uid = get_insn_field(insn, 23, 25); |
2547 | 0 | uint32_t subop; |
2548 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
2549 | 0 | if (uid == 0) { |
2550 | 0 | if (class == 0) { |
2551 | 0 | subop = get_insn_field(insn, 16, 18); |
2552 | 0 | switch (subop) { |
2553 | 0 | case 0x00: |
2554 | 0 | MCInst_setOpcode(MI, HPPA_INS_FID); |
2555 | 0 | return; |
2556 | 0 | case 0x06: |
2557 | 0 | MCInst_setOpcode(MI, HPPA_INS_FNEG); |
2558 | 0 | return; |
2559 | 0 | case 0x07: |
2560 | 0 | MCInst_setOpcode(MI, HPPA_INS_FNEGABS); |
2561 | 0 | return; |
2562 | 0 | default: |
2563 | 0 | break; |
2564 | 0 | } |
2565 | 0 | } else if (class == 1) { |
2566 | 0 | subop = get_insn_field(insn, 14, 16); |
2567 | 0 | if (subop != 4) { |
2568 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNV); |
2569 | 0 | return; |
2570 | 0 | } |
2571 | 0 | } else if (class == 2) { |
2572 | 0 | if (get_insn_bit(insn, 26) == 0) { |
2573 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCMP); |
2574 | 0 | } else { |
2575 | 0 | MCInst_setOpcode(MI, HPPA_INS_FTEST); |
2576 | 0 | } |
2577 | 0 | return; |
2578 | 0 | } |
2579 | 0 | } |
2580 | 0 | } |
2581 | | |
2582 | 0 | if (uid == 0) { |
2583 | 0 | if (class == 0) { |
2584 | 0 | subop = get_insn_field(insn, 16, 18); |
2585 | 0 | switch (subop) { |
2586 | 0 | case 0x00: |
2587 | 0 | MCInst_setOpcode(MI, HPPA_INS_COPR); |
2588 | 0 | return; |
2589 | 0 | case 0x02: |
2590 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCPY); |
2591 | 0 | return; |
2592 | 0 | case 0x03: |
2593 | 0 | MCInst_setOpcode(MI, HPPA_INS_FABS); |
2594 | 0 | return; |
2595 | 0 | case 0x04: |
2596 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSQRT); |
2597 | 0 | return; |
2598 | 0 | case 0x05: |
2599 | 0 | MCInst_setOpcode(MI, HPPA_INS_FRND); |
2600 | 0 | return; |
2601 | 0 | default: |
2602 | 0 | break; |
2603 | 0 | } |
2604 | 0 | } else if (class == 1) { |
2605 | 0 | subop = get_insn_field(insn, 15, 16); |
2606 | 0 | switch (subop) { |
2607 | 0 | case 0x00: |
2608 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFF); |
2609 | 0 | return; |
2610 | 0 | case 0x01: |
2611 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVXF); |
2612 | 0 | return; |
2613 | 0 | case 0x02: |
2614 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFX); |
2615 | 0 | return; |
2616 | 0 | case 0x03: |
2617 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); |
2618 | 0 | return; |
2619 | 0 | default: |
2620 | 0 | break; |
2621 | 0 | } |
2622 | 0 | } else if (class == 2) { |
2623 | 0 | subop = get_insn_field(insn, 16, 18); |
2624 | 0 | switch (subop) { |
2625 | 0 | case 0x00: |
2626 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCMP); |
2627 | 0 | return; |
2628 | 0 | case 0x01: |
2629 | 0 | MCInst_setOpcode(MI, HPPA_INS_FTEST); |
2630 | 0 | return; |
2631 | 0 | default: |
2632 | 0 | break; |
2633 | 0 | } |
2634 | 0 | } else if (class == 3) { |
2635 | 0 | subop = get_insn_field(insn, 16, 18); |
2636 | 0 | switch (subop) { |
2637 | 0 | case 0x00: |
2638 | 0 | MCInst_setOpcode(MI, HPPA_INS_FADD); |
2639 | 0 | return; |
2640 | 0 | case 0x01: |
2641 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSUB); |
2642 | 0 | return; |
2643 | 0 | case 0x02: |
2644 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPY); |
2645 | 0 | return; |
2646 | 0 | case 0x03: |
2647 | 0 | MCInst_setOpcode(MI, HPPA_INS_FDIV); |
2648 | 0 | return; |
2649 | 0 | default: |
2650 | 0 | break; |
2651 | 0 | } |
2652 | 0 | } |
2653 | 0 | } else if (uid == 2) { |
2654 | 0 | subop = get_insn_field(insn, 18, 22); |
2655 | 0 | switch (subop) { |
2656 | 0 | case 0x01: |
2657 | 0 | MCInst_setOpcode(MI, HPPA_INS_PMDIS); |
2658 | 0 | return; |
2659 | 0 | case 0x03: |
2660 | 0 | MCInst_setOpcode(MI, HPPA_INS_PMENB); |
2661 | 0 | return; |
2662 | 0 | default: |
2663 | 0 | break; |
2664 | 0 | } |
2665 | 0 | } |
2666 | 0 | MCInst_setOpcode(MI, HPPA_INS_COPR); |
2667 | 0 | } |
2668 | | |
2669 | | static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class, |
2670 | | hppa_ext *hppa_ext, uint32_t subop, cs_mode mode) |
2671 | 0 | { |
2672 | 0 | uint32_t n = get_insn_field(insn, 26, 26); |
2673 | 0 | uint32_t sf = get_insn_field(insn, 19, 20); |
2674 | 0 | uint32_t df = get_insn_field(insn, 17, 18); |
2675 | 0 | if (MODE_IS_HPPA_20(mode)) { |
2676 | 0 | if (uid == 0) { |
2677 | 0 | if (class == 0) { |
2678 | 0 | switch (subop) { |
2679 | 0 | case 0x00: |
2680 | 0 | return; |
2681 | 0 | default: |
2682 | 0 | break; |
2683 | 0 | } |
2684 | 0 | } else if (class == 1) { |
2685 | 0 | switch (subop) { |
2686 | 0 | case 0x00: |
2687 | 0 | push_str_modifier( |
2688 | 0 | hppa_ext, |
2689 | 0 | float_format_names[sf]); |
2690 | 0 | push_str_modifier( |
2691 | 0 | hppa_ext, |
2692 | 0 | float_format_names[df]); |
2693 | 0 | return; |
2694 | 0 | case 0x01: |
2695 | 0 | push_str_modifier(hppa_ext, |
2696 | 0 | fcnv_fixed_names[sf]); |
2697 | 0 | push_str_modifier( |
2698 | 0 | hppa_ext, |
2699 | 0 | float_format_names[df]); |
2700 | 0 | return; |
2701 | 0 | case 0x03: |
2702 | 0 | push_str_modifier(hppa_ext, "t"); |
2703 | | // fallthrough |
2704 | 0 | case 0x02: |
2705 | 0 | push_str_modifier( |
2706 | 0 | hppa_ext, |
2707 | 0 | float_format_names[sf]); |
2708 | 0 | push_str_modifier(hppa_ext, |
2709 | 0 | fcnv_fixed_names[df]); |
2710 | 0 | return; |
2711 | 0 | case 0x05: |
2712 | 0 | push_str_modifier( |
2713 | 0 | hppa_ext, |
2714 | 0 | fcnv_ufixed_names[sf]); |
2715 | 0 | push_str_modifier( |
2716 | 0 | hppa_ext, |
2717 | 0 | float_format_names[df]); |
2718 | 0 | return; |
2719 | 0 | case 0x07: |
2720 | 0 | push_str_modifier(hppa_ext, "t"); |
2721 | | // fallthrough |
2722 | 0 | case 0x06: |
2723 | 0 | push_str_modifier( |
2724 | 0 | hppa_ext, |
2725 | 0 | float_format_names[sf]); |
2726 | 0 | push_str_modifier( |
2727 | 0 | hppa_ext, |
2728 | 0 | fcnv_ufixed_names[df]); |
2729 | 0 | return; |
2730 | 0 | default: |
2731 | 0 | break; |
2732 | 0 | } |
2733 | 0 | } |
2734 | 0 | } |
2735 | 0 | } |
2736 | | |
2737 | 0 | if (uid == 0) { |
2738 | 0 | if (class == 0) { |
2739 | 0 | switch (subop) { |
2740 | 0 | case 0x00: |
2741 | 0 | push_int_modifier(hppa_ext, 0); |
2742 | 0 | push_int_modifier(hppa_ext, 0); |
2743 | 0 | if (n == 1) { |
2744 | 0 | push_str_modifier(hppa_ext, "n"); |
2745 | 0 | } |
2746 | 0 | break; |
2747 | 0 | case 0x02: |
2748 | 0 | case 0x03: |
2749 | 0 | case 0x04: |
2750 | 0 | case 0x05: |
2751 | 0 | case 0x06: |
2752 | 0 | case 0x07: |
2753 | 0 | push_str_modifier(hppa_ext, |
2754 | 0 | float_format_names[sf]); |
2755 | 0 | break; |
2756 | 0 | default: |
2757 | 0 | break; |
2758 | 0 | } |
2759 | 0 | } else if (class == 1) { |
2760 | 0 | push_str_modifier(hppa_ext, float_format_names[sf]); |
2761 | 0 | push_str_modifier(hppa_ext, float_format_names[df]); |
2762 | 0 | } else if (class == 2) { |
2763 | 0 | uint32_t cond = get_insn_field(insn, 27, 31); |
2764 | 0 | if (n == 1 && subop == 1) { |
2765 | 0 | push_str_modifier(hppa_ext, |
2766 | 0 | float_cond_names[cond]); |
2767 | 0 | } |
2768 | 0 | if (n == 0) { |
2769 | 0 | push_str_modifier(hppa_ext, |
2770 | 0 | float_format_names[sf]); |
2771 | 0 | push_str_modifier(hppa_ext, |
2772 | 0 | float_comp_names[cond]); |
2773 | 0 | } |
2774 | 0 | } else if (class == 3) { |
2775 | 0 | push_str_modifier(hppa_ext, float_format_names[sf]); |
2776 | 0 | } |
2777 | 0 | } else if (uid == 2) { |
2778 | 0 | if (n == 1) { |
2779 | 0 | push_str_modifier(hppa_ext, "n"); |
2780 | 0 | } |
2781 | 0 | } else { |
2782 | 0 | uid = get_insn_field(insn, 23, 25); |
2783 | 0 | uint32_t sop = (get_insn_field(insn, 6, 22) << 5) | |
2784 | 0 | get_insn_field(insn, 27, 31); |
2785 | 0 | push_int_modifier(hppa_ext, uid); |
2786 | 0 | push_int_modifier(hppa_ext, sop); |
2787 | 0 | if (n == 1) { |
2788 | 0 | push_str_modifier(hppa_ext, "n"); |
2789 | 0 | } |
2790 | 0 | } |
2791 | 0 | } |
2792 | | |
2793 | | static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) |
2794 | 0 | { |
2795 | 0 | uint32_t class = get_insn_field(insn, 21, 22); |
2796 | 0 | uint32_t uid = get_insn_field(insn, 23, 25); |
2797 | 0 | uint32_t subop; |
2798 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
2799 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
2800 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
2801 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
2802 | 0 | if (uid == 0) { |
2803 | 0 | if (class == 0) { |
2804 | 0 | subop = get_insn_field(insn, 16, 18); |
2805 | 0 | if (subop == 0x01) { |
2806 | 0 | return false; |
2807 | 0 | } |
2808 | 0 | if (subop >= 0x02) { |
2809 | 0 | CREATE_FPR_REG(MI, r1); |
2810 | 0 | CREATE_FPR_REG(MI, t); |
2811 | 0 | } |
2812 | 0 | } else if (class == 1) { |
2813 | 0 | subop = get_insn_field(insn, 14, 16); |
2814 | 0 | if (subop == 0x04) { |
2815 | 0 | return false; |
2816 | 0 | } |
2817 | 0 | CREATE_FPR_REG(MI, r1); |
2818 | 0 | CREATE_FPR_REG(MI, t); |
2819 | 0 | } else if (class == 2) { |
2820 | 0 | uint32_t n = get_insn_bit(insn, 26); |
2821 | 0 | subop = get_insn_field(insn, 16, 18); |
2822 | 0 | if (n == 0) { |
2823 | 0 | CREATE_FPR_REG(MI, r1); |
2824 | 0 | CREATE_FPR_REG(MI, r2); |
2825 | 0 | if (subop != 0) { |
2826 | 0 | MCOperand_CreateImm0(MI, |
2827 | 0 | subop - 1); |
2828 | 0 | HPPA_EXT_REF(MI) |
2829 | 0 | ->is_alternative = true; |
2830 | 0 | } |
2831 | 0 | } else { |
2832 | 0 | if (subop != 1) { |
2833 | 0 | MCOperand_CreateImm0( |
2834 | 0 | MI, (subop ^ 1) - 1); |
2835 | 0 | HPPA_EXT_REF(MI) |
2836 | 0 | ->is_alternative = true; |
2837 | 0 | } |
2838 | 0 | } |
2839 | 0 | } else { |
2840 | 0 | subop = get_insn_field(insn, 16, 18); |
2841 | 0 | if (subop >= 4) { |
2842 | 0 | return false; |
2843 | 0 | } |
2844 | 0 | CREATE_FPR_REG(MI, r1); |
2845 | 0 | CREATE_FPR_REG(MI, r2); |
2846 | 0 | CREATE_FPR_REG(MI, t); |
2847 | 0 | } |
2848 | 0 | fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), |
2849 | 0 | subop, ud->mode); |
2850 | 0 | return true; |
2851 | 0 | } |
2852 | 0 | } |
2853 | 0 | if (uid == 0) { |
2854 | 0 | if (class == 0) { |
2855 | 0 | subop = get_insn_field(insn, 16, 18); |
2856 | 0 | switch (subop) { |
2857 | 0 | case 0x02: |
2858 | 0 | case 0x03: |
2859 | 0 | case 0x04: |
2860 | 0 | case 0x05: |
2861 | 0 | CREATE_FPR_REG(MI, r1); |
2862 | 0 | CREATE_FPR_REG(MI, t); |
2863 | | // fallthrough |
2864 | 0 | case 0x00: |
2865 | 0 | break; |
2866 | 0 | default: |
2867 | 0 | return false; |
2868 | 0 | } |
2869 | 0 | } else if (class == 1) { |
2870 | 0 | subop = get_insn_field(insn, 15, 16); |
2871 | 0 | switch (subop) { |
2872 | 0 | case 0x00: |
2873 | 0 | case 0x01: |
2874 | 0 | case 0x02: |
2875 | 0 | case 0x03: |
2876 | 0 | CREATE_FPR_REG(MI, r1); |
2877 | 0 | CREATE_FPR_REG(MI, t); |
2878 | 0 | break; |
2879 | 0 | default: |
2880 | 0 | return false; |
2881 | 0 | } |
2882 | 0 | } else if (class == 2) { |
2883 | 0 | subop = get_insn_field(insn, 16, 18); |
2884 | 0 | switch (subop) { |
2885 | 0 | case 0x00: |
2886 | 0 | CREATE_FPR_REG(MI, r1); |
2887 | 0 | CREATE_FPR_REG(MI, r2); |
2888 | | // fallthrough |
2889 | 0 | case 0x01: |
2890 | 0 | break; |
2891 | 0 | default: |
2892 | 0 | return false; |
2893 | 0 | } |
2894 | 0 | } else { |
2895 | 0 | subop = get_insn_field(insn, 16, 18); |
2896 | 0 | switch (subop) { |
2897 | 0 | case 0x00: |
2898 | 0 | case 0x01: |
2899 | 0 | case 0x02: |
2900 | 0 | case 0x03: |
2901 | 0 | CREATE_FPR_REG(MI, r1); |
2902 | 0 | CREATE_FPR_REG(MI, r2); |
2903 | 0 | CREATE_FPR_REG(MI, t); |
2904 | 0 | break; |
2905 | 0 | default: |
2906 | 0 | return false; |
2907 | 0 | } |
2908 | 0 | } |
2909 | 0 | fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), subop, |
2910 | 0 | ud->mode); |
2911 | 0 | return true; |
2912 | 0 | } else if (uid == 2) { |
2913 | 0 | subop = get_insn_field(insn, 18, 22); |
2914 | 0 | switch (subop) { |
2915 | 0 | case 0x01: |
2916 | 0 | case 0x03: |
2917 | 0 | break; |
2918 | 0 | default: |
2919 | 0 | return false; |
2920 | 0 | } |
2921 | 0 | } |
2922 | 0 | fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), -1, ud->mode); |
2923 | 0 | return true; |
2924 | 0 | } |
2925 | | |
2926 | | static void fill_float_insn_name(MCInst *MI, uint32_t insn) |
2927 | 0 | { |
2928 | 0 | uint32_t class = get_insn_field(insn, 21, 22); |
2929 | 0 | uint32_t subop; |
2930 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
2931 | 0 | if (class == 0) { |
2932 | 0 | subop = get_insn_field(insn, 16, 18); |
2933 | 0 | switch (subop) { |
2934 | 0 | case 0x06: |
2935 | 0 | MCInst_setOpcode(MI, HPPA_INS_FNEG); |
2936 | 0 | return; |
2937 | 0 | case 0x07: |
2938 | 0 | MCInst_setOpcode(MI, HPPA_INS_FNEGABS); |
2939 | 0 | return; |
2940 | 0 | default: |
2941 | 0 | break; |
2942 | 0 | } |
2943 | 0 | } else if (class == 1) { |
2944 | 0 | subop = get_insn_field(insn, 14, 16); |
2945 | 0 | if (subop == 0x04) { |
2946 | 0 | return; |
2947 | 0 | } |
2948 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNV); |
2949 | 0 | return; |
2950 | 0 | } else if (class == 2) { |
2951 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCMP); |
2952 | 0 | return; |
2953 | 0 | } |
2954 | 0 | } |
2955 | 0 | if (class == 0) { |
2956 | 0 | subop = get_insn_field(insn, 16, 18); |
2957 | 0 | switch (subop) { |
2958 | 0 | case 0x02: |
2959 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCPY); |
2960 | 0 | break; |
2961 | 0 | case 0x03: |
2962 | 0 | MCInst_setOpcode(MI, HPPA_INS_FABS); |
2963 | 0 | break; |
2964 | 0 | case 0x04: |
2965 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSQRT); |
2966 | 0 | break; |
2967 | 0 | case 0x05: |
2968 | 0 | MCInst_setOpcode(MI, HPPA_INS_FRND); |
2969 | 0 | break; |
2970 | 0 | default: |
2971 | 0 | break; |
2972 | 0 | } |
2973 | 0 | } else if (class == 1) { |
2974 | 0 | subop = get_insn_field(insn, 15, 16); |
2975 | 0 | switch (subop) { |
2976 | 0 | case 0x00: |
2977 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFF); |
2978 | 0 | break; |
2979 | 0 | case 0x01: |
2980 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVXF); |
2981 | 0 | break; |
2982 | 0 | case 0x02: |
2983 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFX); |
2984 | 0 | break; |
2985 | 0 | case 0x03: |
2986 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); |
2987 | 0 | break; |
2988 | 0 | default: |
2989 | 0 | break; |
2990 | 0 | } |
2991 | 0 | } else if (class == 2) { |
2992 | 0 | subop = get_insn_field(insn, 16, 18); |
2993 | 0 | if (subop == 0x00) { |
2994 | 0 | MCInst_setOpcode(MI, HPPA_INS_FCMP); |
2995 | 0 | } |
2996 | 0 | } else if (class == 3) { |
2997 | 0 | subop = get_insn_field(insn, 16, 18); |
2998 | 0 | uint32_t fixed = get_insn_field(insn, 23, 23); |
2999 | 0 | if (fixed == 0) { |
3000 | 0 | switch (subop) { |
3001 | 0 | case 0x00: |
3002 | 0 | MCInst_setOpcode(MI, HPPA_INS_FADD); |
3003 | 0 | break; |
3004 | 0 | case 0x01: |
3005 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSUB); |
3006 | 0 | break; |
3007 | 0 | case 0x02: |
3008 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPY); |
3009 | 0 | break; |
3010 | 0 | case 0x03: |
3011 | 0 | MCInst_setOpcode(MI, HPPA_INS_FDIV); |
3012 | 0 | break; |
3013 | 0 | default: |
3014 | 0 | break; |
3015 | 0 | } |
3016 | 0 | } else { |
3017 | 0 | if (subop == 0x02) { |
3018 | 0 | MCInst_setOpcode(MI, HPPA_INS_XMPYU); |
3019 | 0 | } |
3020 | 0 | } |
3021 | 0 | } |
3022 | 0 | } |
3023 | | |
3024 | | static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext, |
3025 | | uint32_t subop, cs_mode mode) |
3026 | 0 | { |
3027 | 0 | uint32_t sf = get_insn_field(insn, 19, 20); |
3028 | 0 | uint32_t df = get_insn_field(insn, 17, 18); |
3029 | |
|
3030 | 0 | if (MODE_IS_HPPA_20(mode)) { |
3031 | 0 | if (class == 1) { |
3032 | 0 | switch (subop) { |
3033 | 0 | case 0x00: |
3034 | 0 | push_str_modifier(hppa_ext, |
3035 | 0 | float_format_names[sf]); |
3036 | 0 | push_str_modifier(hppa_ext, |
3037 | 0 | float_format_names[df]); |
3038 | 0 | return; |
3039 | 0 | case 0x01: |
3040 | 0 | push_str_modifier(hppa_ext, |
3041 | 0 | fcnv_fixed_names[sf]); |
3042 | 0 | push_str_modifier(hppa_ext, |
3043 | 0 | float_format_names[df]); |
3044 | 0 | return; |
3045 | 0 | case 0x03: |
3046 | 0 | push_str_modifier(hppa_ext, "t"); |
3047 | | // fallthrough |
3048 | 0 | case 0x02: |
3049 | 0 | push_str_modifier(hppa_ext, |
3050 | 0 | float_format_names[sf]); |
3051 | 0 | push_str_modifier(hppa_ext, |
3052 | 0 | fcnv_fixed_names[df]); |
3053 | 0 | return; |
3054 | 0 | case 0x05: |
3055 | 0 | push_str_modifier(hppa_ext, |
3056 | 0 | fcnv_ufixed_names[sf]); |
3057 | 0 | push_str_modifier(hppa_ext, |
3058 | 0 | float_format_names[df]); |
3059 | 0 | return; |
3060 | 0 | case 0x07: |
3061 | 0 | push_str_modifier(hppa_ext, "t"); |
3062 | | // fallthrough |
3063 | 0 | case 0x06: |
3064 | 0 | push_str_modifier(hppa_ext, |
3065 | 0 | float_format_names[sf]); |
3066 | 0 | push_str_modifier(hppa_ext, |
3067 | 0 | fcnv_ufixed_names[df]); |
3068 | 0 | return; |
3069 | 0 | default: |
3070 | 0 | return; |
3071 | 0 | } |
3072 | 0 | } |
3073 | 0 | } |
3074 | | |
3075 | 0 | if (class == 0) { |
3076 | 0 | uint32_t fmt = get_insn_field(insn, 19, 20); |
3077 | 0 | push_str_modifier(hppa_ext, float_format_names[fmt]); |
3078 | 0 | } else if (class == 1) { |
3079 | 0 | push_str_modifier(hppa_ext, float_format_names[sf]); |
3080 | 0 | push_str_modifier(hppa_ext, float_format_names[df]); |
3081 | 0 | } else if (class == 2) { |
3082 | 0 | uint32_t fmt = get_insn_field(insn, 20, 20); |
3083 | 0 | uint32_t cond = get_insn_field(insn, 27, 31); |
3084 | 0 | push_str_modifier(hppa_ext, float_format_names[fmt]); |
3085 | 0 | push_str_modifier(hppa_ext, float_cond_names[cond]); |
3086 | 0 | } else if (class == 3) { |
3087 | 0 | if (get_insn_field(insn, 23, 23) == 0) { |
3088 | 0 | uint32_t fmt = get_insn_field(insn, 20, 20); |
3089 | 0 | push_str_modifier(hppa_ext, float_format_names[fmt]); |
3090 | 0 | } |
3091 | 0 | } |
3092 | 0 | } |
3093 | | |
3094 | | static bool decode_float(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3095 | 0 | { |
3096 | 0 | uint32_t class = get_insn_field(insn, 21, 22); |
3097 | 0 | uint32_t subop; |
3098 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
3099 | 0 | uint32_t r1_fpe = get_insn_bit(insn, 24); |
3100 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
3101 | 0 | uint32_t r2_fpe = get_insn_bit(insn, 19); |
3102 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
3103 | 0 | uint32_t t_fpe = get_insn_bit(insn, 25); |
3104 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3105 | 0 | if (class == 0) { |
3106 | 0 | subop = get_insn_field(insn, 16, 18); |
3107 | 0 | if (subop >= 0x02) { |
3108 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3109 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3110 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), |
3111 | 0 | subop, ud->mode); |
3112 | 0 | return true; |
3113 | 0 | } |
3114 | 0 | } else if (class == 1) { |
3115 | 0 | subop = get_insn_field(insn, 14, 16); |
3116 | 0 | if (subop == 0x04) { |
3117 | 0 | return false; |
3118 | 0 | } |
3119 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3120 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3121 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3122 | 0 | ud->mode); |
3123 | 0 | return true; |
3124 | 0 | } else if (class == 2) { |
3125 | 0 | subop = get_insn_field(insn, 16, 18); |
3126 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3127 | 0 | create_float_reg_spec(MI, r2, r2_fpe); |
3128 | 0 | if (subop != 0) { |
3129 | 0 | MCOperand_CreateImm0(MI, subop - 1); |
3130 | 0 | } |
3131 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3132 | 0 | ud->mode); |
3133 | 0 | return true; |
3134 | 0 | } |
3135 | 0 | } |
3136 | 0 | if (class == 0) { |
3137 | 0 | subop = get_insn_field(insn, 16, 18); |
3138 | 0 | switch (subop) { |
3139 | 0 | case 0x02: |
3140 | 0 | case 0x03: |
3141 | 0 | case 0x04: |
3142 | 0 | case 0x05: |
3143 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3144 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3145 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3146 | 0 | ud->mode); |
3147 | 0 | return true; |
3148 | 0 | default: |
3149 | 0 | return false; |
3150 | 0 | } |
3151 | 0 | } else if (class == 1) { |
3152 | 0 | subop = get_insn_field(insn, 15, 16); |
3153 | 0 | if (subop <= 0x03) { |
3154 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3155 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3156 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3157 | 0 | ud->mode); |
3158 | 0 | return true; |
3159 | 0 | } |
3160 | 0 | } else if (class == 2) { |
3161 | 0 | subop = get_insn_field(insn, 16, 18); |
3162 | 0 | switch (subop) { |
3163 | 0 | case 0x00: |
3164 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3165 | 0 | create_float_reg_spec(MI, r2, r2_fpe); |
3166 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3167 | 0 | ud->mode); |
3168 | 0 | return true; |
3169 | 0 | default: |
3170 | 0 | return false; |
3171 | 0 | } |
3172 | 0 | } else if (class == 3) { |
3173 | 0 | subop = get_insn_field(insn, 16, 18); |
3174 | 0 | uint32_t fixed = get_insn_field(insn, 23, 23); |
3175 | 0 | if ((fixed == 0 && subop <= 0x03) || |
3176 | 0 | (fixed == 1 && subop == 0x02)) { |
3177 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3178 | 0 | create_float_reg_spec(MI, r2, r2_fpe); |
3179 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3180 | 0 | fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, |
3181 | 0 | ud->mode); |
3182 | 0 | return true; |
3183 | 0 | } |
3184 | 0 | return false; |
3185 | 0 | } |
3186 | 0 | return false; |
3187 | 0 | } |
3188 | | |
3189 | | static void fill_fpfused_insn_name(MCInst *MI, uint32_t insn) |
3190 | 0 | { |
3191 | 0 | uint32_t subop = get_insn_bit(insn, 26); |
3192 | 0 | if (subop == 0x00) { |
3193 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPYFADD); |
3194 | 0 | } else { |
3195 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPYNFADD); |
3196 | 0 | } |
3197 | 0 | } |
3198 | | |
3199 | | static void fill_fpfused_mods(uint32_t insn, hppa_ext *hppa_ext) |
3200 | 0 | { |
3201 | 0 | uint32_t fmt = get_insn_bit(insn, 20); |
3202 | 0 | push_str_modifier(hppa_ext, float_format_names[fmt]); |
3203 | 0 | } |
3204 | | |
3205 | | static bool decode_fpfused(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3206 | 0 | { |
3207 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
3208 | 0 | uint32_t r1_fpe = get_insn_bit(insn, 24); |
3209 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
3210 | 0 | uint32_t r2_fpe = get_insn_bit(insn, 19); |
3211 | 0 | uint32_t ra = (get_insn_field(insn, 16, 18) << 2) | |
3212 | 0 | get_insn_field(insn, 21, 22); |
3213 | 0 | uint32_t ra_fpe = get_insn_bit(insn, 23); |
3214 | 0 | uint32_t t = get_insn_field(insn, 27, 31); |
3215 | 0 | uint32_t t_fpe = get_insn_bit(insn, 25); |
3216 | 0 | create_float_reg_spec(MI, r1, r1_fpe); |
3217 | 0 | create_float_reg_spec(MI, r2, r2_fpe); |
3218 | 0 | create_float_reg_spec(MI, ra, ra_fpe); |
3219 | 0 | create_float_reg_spec(MI, t, t_fpe); |
3220 | 0 | fill_fpfused_mods(insn, HPPA_EXT_REF(MI)); |
3221 | 0 | return true; |
3222 | 0 | } |
3223 | | |
3224 | | static void fill_action_and_branch_insn_name(MCInst *MI, uint32_t opcode) |
3225 | 0 | { |
3226 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
3227 | 0 | switch (opcode) { |
3228 | 0 | case HPPA_OP_TYPE_CMPBT: |
3229 | 0 | case HPPA_OP_TYPE_CMPBF: |
3230 | 0 | case HPPA_OP_TYPE_CMPBDWT: |
3231 | 0 | case HPPA_OP_TYPE_CMPBDWF: |
3232 | 0 | MCInst_setOpcode(MI, HPPA_INS_CMPB); |
3233 | 0 | return; |
3234 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3235 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3236 | 0 | case HPPA_OP_TYPE_CMPIBDW: |
3237 | 0 | MCInst_setOpcode(MI, HPPA_INS_CMPIB); |
3238 | 0 | return; |
3239 | 0 | case HPPA_OP_TYPE_ADDBT: |
3240 | 0 | case HPPA_OP_TYPE_ADDBF: |
3241 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDB); |
3242 | 0 | return; |
3243 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3244 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3245 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIB); |
3246 | 0 | return; |
3247 | 0 | case HPPA_OP_TYPE_BBS: |
3248 | 0 | MCInst_setOpcode(MI, HPPA_INS_BB); |
3249 | 0 | return; |
3250 | 0 | default: |
3251 | 0 | break; |
3252 | 0 | } |
3253 | 0 | } |
3254 | 0 | switch (opcode) { |
3255 | 0 | case HPPA_OP_TYPE_CMPBT: |
3256 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMBT); |
3257 | 0 | break; |
3258 | 0 | case HPPA_OP_TYPE_CMPBF: |
3259 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMBF); |
3260 | 0 | break; |
3261 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3262 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMIBT); |
3263 | 0 | break; |
3264 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3265 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMIBF); |
3266 | 0 | break; |
3267 | 0 | case HPPA_OP_TYPE_ADDBT: |
3268 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDBT); |
3269 | 0 | break; |
3270 | 0 | case HPPA_OP_TYPE_ADDBF: |
3271 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDBF); |
3272 | 0 | break; |
3273 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3274 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIBT); |
3275 | 0 | break; |
3276 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3277 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIBF); |
3278 | 0 | break; |
3279 | 0 | case HPPA_OP_TYPE_MOVB: |
3280 | 0 | MCInst_setOpcode(MI, HPPA_INS_MOVB); |
3281 | 0 | break; |
3282 | 0 | case HPPA_OP_TYPE_MOVIB: |
3283 | 0 | MCInst_setOpcode(MI, HPPA_INS_MOVIB); |
3284 | 0 | break; |
3285 | 0 | case HPPA_OP_TYPE_BBS: |
3286 | 0 | MCInst_setOpcode(MI, HPPA_INS_BVB); |
3287 | 0 | break; |
3288 | 0 | case HPPA_OP_TYPE_BB: |
3289 | 0 | MCInst_setOpcode(MI, HPPA_INS_BB); |
3290 | 0 | break; |
3291 | 0 | default: |
3292 | 0 | break; |
3293 | 0 | } |
3294 | 0 | } |
3295 | | |
3296 | | static void fill_action_and_branch_mods(uint32_t insn, uint32_t opcode, |
3297 | | hppa_ext *hppa_ext, cs_mode mode) |
3298 | 0 | { |
3299 | 0 | uint32_t cond = get_insn_field(insn, 16, 18); |
3300 | 0 | uint32_t n = get_insn_bit(insn, 30); |
3301 | 0 | uint32_t d = get_insn_bit(insn, 18); |
3302 | |
|
3303 | 0 | if (MODE_IS_HPPA_20(mode)) { |
3304 | 0 | switch (opcode) { |
3305 | 0 | case HPPA_OP_TYPE_CMPBT: |
3306 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3307 | 0 | push_str_modifier(hppa_ext, compare_cond_names[cond]); |
3308 | 0 | break; |
3309 | 0 | case HPPA_OP_TYPE_CMPBF: |
3310 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3311 | 0 | push_str_modifier(hppa_ext, |
3312 | 0 | compare_cond_names[cond + 8]); |
3313 | 0 | break; |
3314 | 0 | case HPPA_OP_TYPE_CMPBDWT: |
3315 | 0 | push_str_modifier(hppa_ext, |
3316 | 0 | compare_cond_64_names[cond]); |
3317 | 0 | break; |
3318 | 0 | case HPPA_OP_TYPE_CMPBDWF: |
3319 | 0 | push_str_modifier(hppa_ext, |
3320 | 0 | compare_cond_64_names[cond + 8]); |
3321 | 0 | break; |
3322 | 0 | case HPPA_OP_TYPE_CMPIBDW: |
3323 | 0 | push_str_modifier(hppa_ext, cmpib_cond_64_names[cond]); |
3324 | 0 | break; |
3325 | 0 | case HPPA_OP_TYPE_ADDBT: |
3326 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3327 | 0 | if (MODE_IS_HPPA_20W(mode)) { |
3328 | 0 | push_str_modifier(hppa_ext, |
3329 | 0 | wide_add_cond_names[cond]); |
3330 | 0 | } else { |
3331 | 0 | push_str_modifier(hppa_ext, |
3332 | 0 | add_cond_names[cond]); |
3333 | 0 | } |
3334 | 0 | break; |
3335 | 0 | case HPPA_OP_TYPE_ADDBF: |
3336 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3337 | 0 | if (MODE_IS_HPPA_20W(mode)) { |
3338 | 0 | push_str_modifier( |
3339 | 0 | hppa_ext, |
3340 | 0 | wide_add_cond_names[cond + 8]); |
3341 | 0 | } else { |
3342 | 0 | push_str_modifier(hppa_ext, |
3343 | 0 | add_cond_names[cond + 8]); |
3344 | 0 | } |
3345 | 0 | break; |
3346 | 0 | case HPPA_OP_TYPE_BBS: |
3347 | 0 | case HPPA_OP_TYPE_BB: |
3348 | 0 | if (d == 0) { |
3349 | 0 | push_str_modifier(hppa_ext, |
3350 | 0 | shift_cond_names[cond]); |
3351 | 0 | } else { |
3352 | 0 | push_str_modifier(hppa_ext, |
3353 | 0 | shift_cond_64_names[cond]); |
3354 | 0 | } |
3355 | 0 | break; |
3356 | 0 | case HPPA_OP_TYPE_MOVB: |
3357 | 0 | case HPPA_OP_TYPE_MOVIB: |
3358 | 0 | push_str_modifier(hppa_ext, shift_cond_names[cond]); |
3359 | 0 | break; |
3360 | 0 | default: |
3361 | 0 | break; |
3362 | 0 | } |
3363 | 0 | if (n == 1) { |
3364 | 0 | push_str_modifier(hppa_ext, "n"); |
3365 | 0 | } |
3366 | 0 | return; |
3367 | 0 | } |
3368 | 0 | switch (opcode) { |
3369 | 0 | case HPPA_OP_TYPE_CMPBT: |
3370 | 0 | case HPPA_OP_TYPE_CMPBF: |
3371 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3372 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3373 | 0 | push_str_modifier(hppa_ext, compare_cond_names[cond]); |
3374 | 0 | break; |
3375 | 0 | case HPPA_OP_TYPE_ADDBT: |
3376 | 0 | case HPPA_OP_TYPE_ADDBF: |
3377 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3378 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3379 | 0 | push_str_modifier(hppa_ext, add_cond_names[cond]); |
3380 | 0 | break; |
3381 | 0 | case HPPA_OP_TYPE_MOVB: |
3382 | 0 | case HPPA_OP_TYPE_MOVIB: |
3383 | 0 | case HPPA_OP_TYPE_BBS: |
3384 | 0 | case HPPA_OP_TYPE_BB: |
3385 | 0 | push_str_modifier(hppa_ext, shift_cond_names[cond]); |
3386 | 0 | break; |
3387 | 0 | default: |
3388 | 0 | break; |
3389 | 0 | } |
3390 | 0 | if (n == 1) { |
3391 | 0 | push_str_modifier(hppa_ext, "n"); |
3392 | 0 | } |
3393 | 0 | } |
3394 | | |
3395 | | static bool fill_action_and_branch(const cs_struct *ud, MCInst *MI, |
3396 | | uint32_t insn) |
3397 | 0 | { |
3398 | 0 | uint32_t opcode = insn >> 26; |
3399 | 0 | uint32_t r1 = get_insn_field(insn, 6, 10); |
3400 | 0 | uint32_t r2 = get_insn_field(insn, 11, 15); |
3401 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3402 | 0 | switch (opcode) { |
3403 | 0 | case HPPA_OP_TYPE_CMPBT: |
3404 | 0 | case HPPA_OP_TYPE_CMPBF: |
3405 | 0 | case HPPA_OP_TYPE_CMPBDWT: |
3406 | 0 | case HPPA_OP_TYPE_CMPBDWF: |
3407 | 0 | case HPPA_OP_TYPE_ADDBT: |
3408 | 0 | case HPPA_OP_TYPE_ADDBF: |
3409 | 0 | case HPPA_OP_TYPE_MOVB: |
3410 | 0 | CREATE_GR_REG(MI, r2); |
3411 | 0 | CREATE_GR_REG(MI, r1); |
3412 | 0 | MCOperand_CreateImm0(MI, extract_12(insn)); |
3413 | 0 | break; |
3414 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3415 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3416 | 0 | case HPPA_OP_TYPE_CMPIBDW: |
3417 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3418 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3419 | 0 | case HPPA_OP_TYPE_MOVIB: |
3420 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); |
3421 | 0 | CREATE_GR_REG(MI, r1); |
3422 | 0 | MCOperand_CreateImm0(MI, extract_12(insn)); |
3423 | 0 | break; |
3424 | 0 | case HPPA_OP_TYPE_BBS: |
3425 | 0 | case HPPA_OP_TYPE_BB: |
3426 | 0 | CREATE_GR_REG(MI, r2); |
3427 | 0 | if ((opcode & 1) == 1) { |
3428 | 0 | MCOperand_CreateImm0(MI, r1); |
3429 | 0 | } else { |
3430 | 0 | CREATE_CR_REG(MI, 11); |
3431 | 0 | } |
3432 | 0 | MCOperand_CreateImm0(MI, extract_12(insn)); |
3433 | 0 | break; |
3434 | 0 | default: |
3435 | 0 | return false; |
3436 | 0 | } |
3437 | 0 | fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), |
3438 | 0 | ud->mode); |
3439 | 0 | return true; |
3440 | 0 | } |
3441 | 0 | if ((opcode & 1) == 0 || opcode == HPPA_OP_TYPE_BB) { |
3442 | 0 | CREATE_GR_REG(MI, r2); |
3443 | 0 | } else { |
3444 | 0 | MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); |
3445 | 0 | } |
3446 | 0 | if (opcode == HPPA_OP_TYPE_BB) { |
3447 | 0 | MCOperand_CreateImm0(MI, r1); |
3448 | 0 | } else if (opcode != HPPA_OP_TYPE_BBS) { |
3449 | 0 | CREATE_GR_REG(MI, r1); |
3450 | 0 | } |
3451 | 0 | MCOperand_CreateImm0(MI, extract_12(insn)); |
3452 | 0 | fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), ud->mode); |
3453 | 0 | return true; |
3454 | 0 | } |
3455 | | |
3456 | | static void fill_load_insn_name(MCInst *MI, uint32_t opcode) |
3457 | 0 | { |
3458 | 0 | switch (opcode) { |
3459 | 0 | case HPPA_OP_TYPE_LDB: |
3460 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDB); |
3461 | 0 | break; |
3462 | 0 | case HPPA_OP_TYPE_LDH: |
3463 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDH); |
3464 | 0 | break; |
3465 | 0 | case HPPA_OP_TYPE_LDW: |
3466 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDW); |
3467 | 0 | break; |
3468 | 0 | case HPPA_OP_TYPE_LDWM: |
3469 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
3470 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDW); |
3471 | 0 | } else { |
3472 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDWM); |
3473 | 0 | } |
3474 | 0 | break; |
3475 | 0 | default: |
3476 | 0 | break; |
3477 | 0 | } |
3478 | 0 | } |
3479 | | |
3480 | | static void fill_store_insn_name(MCInst *MI, uint32_t opcode) |
3481 | 0 | { |
3482 | 0 | switch (opcode) { |
3483 | 0 | case HPPA_OP_TYPE_STB: |
3484 | 0 | MCInst_setOpcode(MI, HPPA_INS_STB); |
3485 | 0 | break; |
3486 | 0 | case HPPA_OP_TYPE_STH: |
3487 | 0 | MCInst_setOpcode(MI, HPPA_INS_STH); |
3488 | 0 | break; |
3489 | 0 | case HPPA_OP_TYPE_STW: |
3490 | 0 | MCInst_setOpcode(MI, HPPA_INS_STW); |
3491 | 0 | break; |
3492 | 0 | case HPPA_OP_TYPE_STWM: |
3493 | 0 | if (MODE_IS_HPPA_20(MI->csh->mode)) { |
3494 | 0 | MCInst_setOpcode(MI, HPPA_INS_STW); |
3495 | 0 | } else { |
3496 | 0 | MCInst_setOpcode(MI, HPPA_INS_STWM); |
3497 | 0 | } |
3498 | 0 | break; |
3499 | 0 | default: |
3500 | 0 | break; |
3501 | 0 | } |
3502 | 0 | } |
3503 | | |
3504 | | static bool decode_cmpclr(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3505 | 0 | { |
3506 | 0 | uint32_t cond = (get_insn_bit(insn, 19) << 3) | |
3507 | 0 | get_insn_field(insn, 16, 18); |
3508 | 0 | uint32_t d = get_insn_bit(insn, 20); |
3509 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3510 | 0 | MCInst_setOpcode(MI, HPPA_INS_CMPICLR); |
3511 | 0 | } else { |
3512 | 0 | MCInst_setOpcode(MI, HPPA_INS_COMICLR); |
3513 | 0 | } |
3514 | |
|
3515 | 0 | MCOperand_CreateImm0(MI, |
3516 | 0 | LowSignExtend64(get_insn_field(insn, 21, 31), 11)); |
3517 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3518 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
3519 | |
|
3520 | 0 | if (d == 0) { |
3521 | 0 | push_str_modifier(HPPA_EXT_REF(MI), compare_cond_names[cond]); |
3522 | 0 | } else { |
3523 | 0 | push_str_modifier(HPPA_EXT_REF(MI), |
3524 | 0 | compare_cond_64_names[cond]); |
3525 | 0 | } |
3526 | 0 | return true; |
3527 | 0 | } |
3528 | | |
3529 | | static bool decode_be(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3530 | 0 | { |
3531 | 0 | uint32_t opcode = insn >> 26; |
3532 | 0 | uint32_t n = get_insn_bit(insn, 30); |
3533 | 0 | bool mode = MODE_IS_HPPA_20(ud->mode); |
3534 | 0 | if (opcode == HPPA_OP_TYPE_BLE) { |
3535 | 0 | if (!mode) { |
3536 | 0 | MCInst_setOpcode(MI, HPPA_INS_BLE); |
3537 | 0 | } else { |
3538 | 0 | MCInst_setOpcode(MI, HPPA_INS_BE); |
3539 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "l"); |
3540 | 0 | HPPA_EXT_REF(MI)->is_alternative = true; |
3541 | 0 | } |
3542 | 0 | } else { |
3543 | 0 | MCInst_setOpcode(MI, HPPA_INS_BE); |
3544 | 0 | } |
3545 | |
|
3546 | 0 | MCOperand_CreateImm0(MI, extract_17(insn)); |
3547 | 0 | CREATE_SR_REG(MI, extract_3(insn)); |
3548 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3549 | 0 | if (opcode == HPPA_OP_TYPE_BLE && mode) { |
3550 | 0 | CREATE_SR_REG(MI, 0); |
3551 | 0 | CREATE_GR_REG(MI, 31); |
3552 | 0 | } |
3553 | 0 | if (n == 1) { |
3554 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "n"); |
3555 | 0 | } |
3556 | 0 | return true; |
3557 | 0 | } |
3558 | | |
3559 | | static bool decode_float_ldst(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3560 | 0 | { |
3561 | 0 | uint32_t opcode = insn >> 26; |
3562 | 0 | uint32_t a = get_insn_bit(insn, 29); |
3563 | 0 | uint32_t disp = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); |
3564 | 0 | disp &= ~3; |
3565 | |
|
3566 | 0 | if (opcode == HPPA_OP_TYPE_FLDW) { |
3567 | 0 | MCInst_setOpcode(MI, HPPA_INS_FLDW); |
3568 | 0 | MCOperand_CreateImm0(MI, disp); |
3569 | 0 | CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); |
3570 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3571 | 0 | CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); |
3572 | 0 | } else { |
3573 | 0 | MCInst_setOpcode(MI, HPPA_INS_FSTW); |
3574 | 0 | CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); |
3575 | 0 | MCOperand_CreateImm0(MI, disp); |
3576 | 0 | CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); |
3577 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3578 | 0 | } |
3579 | |
|
3580 | 0 | if (a == 0) { |
3581 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "ma"); |
3582 | 0 | } else { |
3583 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "mb"); |
3584 | 0 | } |
3585 | 0 | return true; |
3586 | 0 | } |
3587 | | |
3588 | | static bool decode_fmpy(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3589 | 0 | { |
3590 | 0 | uint32_t opcode = insn >> 26; |
3591 | 0 | uint32_t rm1 = get_insn_field(insn, 6, 10); |
3592 | 0 | uint32_t rm2 = get_insn_field(insn, 11, 15); |
3593 | 0 | uint32_t ta = get_insn_field(insn, 16, 20); |
3594 | 0 | uint32_t ra = get_insn_field(insn, 21, 25); |
3595 | 0 | uint32_t tm = get_insn_field(insn, 27, 31); |
3596 | 0 | uint32_t fmt = get_insn_field(insn, 26, 26); |
3597 | |
|
3598 | 0 | if (opcode == HPPA_OP_TYPE_FMPYADD) { |
3599 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPYADD); |
3600 | 0 | } else { |
3601 | 0 | MCInst_setOpcode(MI, HPPA_INS_FMPYSUB); |
3602 | 0 | } |
3603 | |
|
3604 | 0 | if (fmt == 0) { |
3605 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "dbl"); |
3606 | 0 | CREATE_FPR_REG(MI, rm1); |
3607 | 0 | CREATE_FPR_REG(MI, rm2); |
3608 | 0 | CREATE_FPR_REG(MI, tm); |
3609 | 0 | CREATE_FPR_REG(MI, ra); |
3610 | 0 | CREATE_FPR_REG(MI, ta); |
3611 | 0 | } else { |
3612 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "sgl"); |
3613 | 0 | CREATE_SP_FPR_REG(MI, rm1); |
3614 | 0 | CREATE_SP_FPR_REG(MI, rm2); |
3615 | 0 | CREATE_SP_FPR_REG(MI, tm); |
3616 | 0 | CREATE_SP_FPR_REG(MI, ra); |
3617 | 0 | CREATE_SP_FPR_REG(MI, ta); |
3618 | 0 | } |
3619 | |
|
3620 | 0 | return true; |
3621 | 0 | } |
3622 | | |
3623 | | static bool decode_load(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3624 | 0 | { |
3625 | 0 | uint32_t opcode = insn >> 26; |
3626 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3627 | 0 | int32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); |
3628 | 0 | if (opcode == HPPA_OP_TYPE_LDWM) { |
3629 | 0 | if (d < 0) { |
3630 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "mb"); |
3631 | 0 | } else { |
3632 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "ma"); |
3633 | 0 | } |
3634 | 0 | } |
3635 | 0 | MCOperand_CreateImm0(MI, d); |
3636 | 0 | } else { |
3637 | 0 | MCOperand_CreateImm0(MI, extract_14(insn)); |
3638 | 0 | } |
3639 | 0 | CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); |
3640 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3641 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
3642 | 0 | return true; |
3643 | 0 | } |
3644 | | |
3645 | | static bool decode_store(const cs_struct *ud, MCInst *MI, uint32_t insn) |
3646 | 0 | { |
3647 | 0 | uint32_t opcode = insn >> 26; |
3648 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); |
3649 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3650 | 0 | int d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); |
3651 | 0 | if (opcode == HPPA_OP_TYPE_STWM) { |
3652 | 0 | if (d < 0) { |
3653 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "mb"); |
3654 | 0 | } else { |
3655 | 0 | push_str_modifier(HPPA_EXT_REF(MI), "ma"); |
3656 | 0 | } |
3657 | 0 | } |
3658 | 0 | MCOperand_CreateImm0(MI, d); |
3659 | 0 | } else { |
3660 | 0 | MCOperand_CreateImm0(MI, extract_14(insn)); |
3661 | 0 | } |
3662 | 0 | CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); |
3663 | 0 | CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); |
3664 | 0 | return true; |
3665 | 0 | } |
3666 | | |
3667 | | static bool getInstruction(const cs_struct *ud, const uint8_t *code, |
3668 | | size_t code_len, MCInst *MI) |
3669 | 0 | { |
3670 | 0 | if (code_len < 4) |
3671 | 0 | return false; |
3672 | | |
3673 | 0 | MCInst_clear(MI); |
3674 | |
|
3675 | 0 | uint32_t full_insn = readBytes32(MI, code); |
3676 | 0 | uint8_t opcode = full_insn >> 26; |
3677 | |
|
3678 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3679 | 0 | switch (opcode) { |
3680 | 0 | case HPPA_OP_TYPE_LOADDW: |
3681 | 0 | case HPPA_OP_TYPE_STOREDW: |
3682 | 0 | fill_ldst_dw_insn_name(MI, full_insn); |
3683 | 0 | return decode_ldst_dw(ud, MI, full_insn); |
3684 | 0 | case HPPA_OP_TYPE_LOADW: |
3685 | 0 | case HPPA_OP_TYPE_STOREW: |
3686 | 0 | fill_ldst_w_insn_name(MI, full_insn); |
3687 | 0 | return decode_ldst_w(ud, MI, full_insn); |
3688 | 0 | case HPPA_OP_TYPE_SHEXDEP2: |
3689 | 0 | MCInst_setOpcode(MI, HPPA_INS_EXTRD); |
3690 | 0 | return decode_shexdep2(MI, full_insn); |
3691 | 0 | case HPPA_OP_TYPE_SHEXDEP3: |
3692 | 0 | case HPPA_OP_TYPE_SHEXDEP4: |
3693 | 0 | return decode_shexdep3(ud, MI, full_insn); |
3694 | 0 | case HPPA_OP_TYPE_MULTMED: |
3695 | 0 | fill_multmed_insn_name(MI, full_insn); |
3696 | 0 | return decode_multmed(MI, full_insn); |
3697 | 0 | case HPPA_OP_TYPE_FPFUSED: |
3698 | 0 | fill_fpfused_insn_name(MI, full_insn); |
3699 | 0 | return decode_fpfused(ud, MI, full_insn); |
3700 | 0 | case HPPA_OP_TYPE_FLDW: |
3701 | 0 | case HPPA_OP_TYPE_FSTW: |
3702 | 0 | return decode_float_ldst(ud, MI, full_insn); |
3703 | 0 | case HPPA_OP_TYPE_CMPBDWT: |
3704 | 0 | case HPPA_OP_TYPE_CMPBDWF: |
3705 | 0 | case HPPA_OP_TYPE_CMPIBDW: |
3706 | 0 | fill_action_and_branch_insn_name(MI, opcode); |
3707 | 0 | return fill_action_and_branch(ud, MI, full_insn); |
3708 | 0 | default: |
3709 | 0 | break; |
3710 | 0 | } |
3711 | 0 | } |
3712 | | |
3713 | 0 | switch (opcode) { |
3714 | 0 | case HPPA_OP_TYPE_SYSOP: |
3715 | 0 | fill_sysop_insn_name(MI, full_insn); |
3716 | 0 | return decode_sysop(ud, MI, full_insn); |
3717 | 0 | case HPPA_OP_TYPE_MEMMGMT: |
3718 | 0 | fill_memmgmt_insn_name(MI, full_insn); |
3719 | 0 | return decode_memmgmt(ud, MI, full_insn); |
3720 | 0 | case HPPA_OP_TYPE_ALU: |
3721 | 0 | fill_alu_insn_name(MI, full_insn); |
3722 | 0 | return decode_alu(ud, MI, full_insn); |
3723 | 0 | case HPPA_OP_TYPE_IDXMEM: |
3724 | 0 | fill_idxmem_insn_name(MI, full_insn); |
3725 | 0 | return decode_idxmem(ud, MI, full_insn); |
3726 | 0 | case HPPA_OP_TYPE_ADDIT: |
3727 | 0 | case HPPA_OP_TYPE_ADDI: |
3728 | 0 | case HPPA_OP_TYPE_SUBI: |
3729 | 0 | fill_arith_imm_insn_name(MI, full_insn); |
3730 | 0 | return decode_arith_imm(ud, MI, full_insn); |
3731 | 0 | case HPPA_OP_TYPE_SHEXDEP0: |
3732 | 0 | fill_shexdep0_insn_name(MI, full_insn); |
3733 | 0 | return decode_shexdep0(ud, MI, full_insn); |
3734 | 0 | case HPPA_OP_TYPE_SHEXDEP1: |
3735 | 0 | fill_shexdep1_insn_name(MI, full_insn); |
3736 | 0 | return decode_shexdep1(ud, MI, full_insn); |
3737 | 0 | case HPPA_OP_TYPE_BRANCH: |
3738 | 0 | fill_branch_insn_name(MI, full_insn); |
3739 | 0 | return decode_branch(ud, MI, full_insn); |
3740 | 0 | case HPPA_OP_TYPE_COPRW: |
3741 | 0 | case HPPA_OP_TYPE_COPRDW: |
3742 | 0 | fill_corpdw_insn_name(MI, full_insn); |
3743 | 0 | return decode_corpdw(ud, MI, full_insn); |
3744 | 0 | case HPPA_OP_TYPE_SPOP: |
3745 | 0 | fill_spop_insn_name(MI, full_insn); |
3746 | 0 | return decode_spop(ud, MI, full_insn); |
3747 | 0 | case HPPA_OP_TYPE_COPR: |
3748 | 0 | fill_copr_insn_name(MI, full_insn); |
3749 | 0 | return decode_copr(ud, MI, full_insn); |
3750 | 0 | case HPPA_OP_TYPE_FLOAT: |
3751 | 0 | fill_float_insn_name(MI, full_insn); |
3752 | 0 | return decode_float(ud, MI, full_insn); |
3753 | 0 | case HPPA_OP_TYPE_DIAG: |
3754 | 0 | MCInst_setOpcode(MI, HPPA_INS_DIAG); |
3755 | 0 | MCOperand_CreateImm0(MI, get_insn_field(full_insn, 6, 31)); |
3756 | 0 | return true; |
3757 | 0 | case HPPA_OP_TYPE_FMPYADD: |
3758 | 0 | case HPPA_OP_TYPE_FMPYSUB: |
3759 | 0 | return decode_fmpy(ud, MI, full_insn); |
3760 | 0 | case HPPA_OP_TYPE_LDIL: |
3761 | 0 | case HPPA_OP_TYPE_ADDIL: |
3762 | 0 | if (opcode == HPPA_OP_TYPE_LDIL) { |
3763 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDIL); |
3764 | 0 | } else { |
3765 | 0 | MCInst_setOpcode(MI, HPPA_INS_ADDIL); |
3766 | 0 | } |
3767 | 0 | MCOperand_CreateImm0(MI, extract_21(full_insn)); |
3768 | 0 | CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); |
3769 | 0 | return true; |
3770 | 0 | case HPPA_OP_TYPE_LDO: |
3771 | 0 | MCInst_setOpcode(MI, HPPA_INS_LDO); |
3772 | 0 | if (MODE_IS_HPPA_20(ud->mode)) { |
3773 | 0 | MCOperand_CreateImm0( |
3774 | 0 | MI, extract_16(full_insn, |
3775 | 0 | MODE_IS_HPPA_20W(ud->mode))); |
3776 | 0 | } else { |
3777 | 0 | MCOperand_CreateImm0(MI, extract_14(full_insn)); |
3778 | 0 | } |
3779 | 0 | CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); |
3780 | 0 | CREATE_GR_REG(MI, get_insn_field(full_insn, 11, 15)); |
3781 | 0 | return true; |
3782 | 0 | case HPPA_OP_TYPE_LDB: |
3783 | 0 | case HPPA_OP_TYPE_LDH: |
3784 | 0 | case HPPA_OP_TYPE_LDW: |
3785 | 0 | case HPPA_OP_TYPE_LDWM: |
3786 | 0 | fill_load_insn_name(MI, opcode); |
3787 | 0 | return decode_load(ud, MI, full_insn); |
3788 | 0 | case HPPA_OP_TYPE_STB: |
3789 | 0 | case HPPA_OP_TYPE_STH: |
3790 | 0 | case HPPA_OP_TYPE_STW: |
3791 | 0 | case HPPA_OP_TYPE_STWM: |
3792 | 0 | fill_store_insn_name(MI, opcode); |
3793 | 0 | return decode_store(ud, MI, full_insn); |
3794 | 0 | case HPPA_OP_TYPE_CMPBT: |
3795 | 0 | case HPPA_OP_TYPE_CMPBF: |
3796 | 0 | case HPPA_OP_TYPE_ADDBT: |
3797 | 0 | case HPPA_OP_TYPE_ADDBF: |
3798 | 0 | case HPPA_OP_TYPE_MOVB: |
3799 | 0 | case HPPA_OP_TYPE_CMPIBT: |
3800 | 0 | case HPPA_OP_TYPE_CMPIBF: |
3801 | 0 | case HPPA_OP_TYPE_ADDIBT: |
3802 | 0 | case HPPA_OP_TYPE_ADDIBF: |
3803 | 0 | case HPPA_OP_TYPE_MOVIB: |
3804 | 0 | case HPPA_OP_TYPE_BBS: |
3805 | 0 | case HPPA_OP_TYPE_BB: |
3806 | 0 | fill_action_and_branch_insn_name(MI, opcode); |
3807 | 0 | return fill_action_and_branch(ud, MI, full_insn); |
3808 | 0 | case HPPA_OP_TYPE_CMPICLR: |
3809 | 0 | return decode_cmpclr(ud, MI, full_insn); |
3810 | 0 | case HPPA_OP_TYPE_BE: |
3811 | 0 | case HPPA_OP_TYPE_BLE: |
3812 | 0 | return decode_be(ud, MI, full_insn); |
3813 | 0 | default: |
3814 | 0 | return false; |
3815 | 0 | } |
3816 | 0 | } |
3817 | | |
3818 | | void init_details(MCInst *MI) |
3819 | 0 | { |
3820 | 0 | cs_detail *detail = get_detail(MI); |
3821 | 0 | if (detail) { |
3822 | 0 | memset(detail, 0, offsetof(cs_detail, hppa) + sizeof(cs_hppa)); |
3823 | 0 | } |
3824 | 0 | } |
3825 | | |
3826 | | bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, |
3827 | | MCInst *instr, uint16_t *size, uint64_t address, |
3828 | | void *info) |
3829 | 0 | { |
3830 | 0 | cs_struct *cs = (cs_struct *)ud; |
3831 | 0 | init_details(instr); |
3832 | 0 | if (!getInstruction(cs, code, code_len, instr)) { |
3833 | 0 | *size = 0; |
3834 | 0 | return false; |
3835 | 0 | } |
3836 | 0 | *size = 4; |
3837 | 0 | return true; |
3838 | 0 | } |
3839 | | |
3840 | | #endif |