/src/capstonenext/arch/TMS320C64x/TMS320C64xMapping.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_TMS320C64X |
5 | | |
6 | | #include <stdio.h> // debug |
7 | | #include <string.h> |
8 | | |
9 | | #include "../../Mapping.h" |
10 | | #include "../../utils.h" |
11 | | |
12 | | #include "TMS320C64xMapping.h" |
13 | | |
14 | | #define GET_INSTRINFO_ENUM |
15 | | #include "TMS320C64xGenInstrInfo.inc" |
16 | | |
17 | | static const name_map reg_name_maps[] = { |
18 | | { TMS320C64X_REG_INVALID, NULL }, |
19 | | |
20 | | { TMS320C64X_REG_AMR, "amr" }, { TMS320C64X_REG_CSR, "csr" }, |
21 | | { TMS320C64X_REG_DIER, "dier" }, { TMS320C64X_REG_DNUM, "dnum" }, |
22 | | { TMS320C64X_REG_ECR, "ecr" }, { TMS320C64X_REG_GFPGFR, "gfpgfr" }, |
23 | | { TMS320C64X_REG_GPLYA, "gplya" }, { TMS320C64X_REG_GPLYB, "gplyb" }, |
24 | | { TMS320C64X_REG_ICR, "icr" }, { TMS320C64X_REG_IER, "ier" }, |
25 | | { TMS320C64X_REG_IERR, "ierr" }, { TMS320C64X_REG_ILC, "ilc" }, |
26 | | { TMS320C64X_REG_IRP, "irp" }, { TMS320C64X_REG_ISR, "isr" }, |
27 | | { TMS320C64X_REG_ISTP, "istp" }, { TMS320C64X_REG_ITSR, "itsr" }, |
28 | | { TMS320C64X_REG_NRP, "nrp" }, { TMS320C64X_REG_NTSR, "ntsr" }, |
29 | | { TMS320C64X_REG_REP, "rep" }, { TMS320C64X_REG_RILC, "rilc" }, |
30 | | { TMS320C64X_REG_SSR, "ssr" }, { TMS320C64X_REG_TSCH, "tsch" }, |
31 | | { TMS320C64X_REG_TSCL, "tscl" }, { TMS320C64X_REG_TSR, "tsr" }, |
32 | | { TMS320C64X_REG_A0, "a0" }, { TMS320C64X_REG_A1, "a1" }, |
33 | | { TMS320C64X_REG_A2, "a2" }, { TMS320C64X_REG_A3, "a3" }, |
34 | | { TMS320C64X_REG_A4, "a4" }, { TMS320C64X_REG_A5, "a5" }, |
35 | | { TMS320C64X_REG_A6, "a6" }, { TMS320C64X_REG_A7, "a7" }, |
36 | | { TMS320C64X_REG_A8, "a8" }, { TMS320C64X_REG_A9, "a9" }, |
37 | | { TMS320C64X_REG_A10, "a10" }, { TMS320C64X_REG_A11, "a11" }, |
38 | | { TMS320C64X_REG_A12, "a12" }, { TMS320C64X_REG_A13, "a13" }, |
39 | | { TMS320C64X_REG_A14, "a14" }, { TMS320C64X_REG_A15, "a15" }, |
40 | | { TMS320C64X_REG_A16, "a16" }, { TMS320C64X_REG_A17, "a17" }, |
41 | | { TMS320C64X_REG_A18, "a18" }, { TMS320C64X_REG_A19, "a19" }, |
42 | | { TMS320C64X_REG_A20, "a20" }, { TMS320C64X_REG_A21, "a21" }, |
43 | | { TMS320C64X_REG_A22, "a22" }, { TMS320C64X_REG_A23, "a23" }, |
44 | | { TMS320C64X_REG_A24, "a24" }, { TMS320C64X_REG_A25, "a25" }, |
45 | | { TMS320C64X_REG_A26, "a26" }, { TMS320C64X_REG_A27, "a27" }, |
46 | | { TMS320C64X_REG_A28, "a28" }, { TMS320C64X_REG_A29, "a29" }, |
47 | | { TMS320C64X_REG_A30, "a30" }, { TMS320C64X_REG_A31, "a31" }, |
48 | | { TMS320C64X_REG_B0, "b0" }, { TMS320C64X_REG_B1, "b1" }, |
49 | | { TMS320C64X_REG_B2, "b2" }, { TMS320C64X_REG_B3, "b3" }, |
50 | | { TMS320C64X_REG_B4, "b4" }, { TMS320C64X_REG_B5, "b5" }, |
51 | | { TMS320C64X_REG_B6, "b6" }, { TMS320C64X_REG_B7, "b7" }, |
52 | | { TMS320C64X_REG_B8, "b8" }, { TMS320C64X_REG_B9, "b9" }, |
53 | | { TMS320C64X_REG_B10, "b10" }, { TMS320C64X_REG_B11, "b11" }, |
54 | | { TMS320C64X_REG_B12, "b12" }, { TMS320C64X_REG_B13, "b13" }, |
55 | | { TMS320C64X_REG_B14, "b14" }, { TMS320C64X_REG_B15, "b15" }, |
56 | | { TMS320C64X_REG_B16, "b16" }, { TMS320C64X_REG_B17, "b17" }, |
57 | | { TMS320C64X_REG_B18, "b18" }, { TMS320C64X_REG_B19, "b19" }, |
58 | | { TMS320C64X_REG_B20, "b20" }, { TMS320C64X_REG_B21, "b21" }, |
59 | | { TMS320C64X_REG_B22, "b22" }, { TMS320C64X_REG_B23, "b23" }, |
60 | | { TMS320C64X_REG_B24, "b24" }, { TMS320C64X_REG_B25, "b25" }, |
61 | | { TMS320C64X_REG_B26, "b26" }, { TMS320C64X_REG_B27, "b27" }, |
62 | | { TMS320C64X_REG_B28, "b28" }, { TMS320C64X_REG_B29, "b29" }, |
63 | | { TMS320C64X_REG_B30, "b30" }, { TMS320C64X_REG_B31, "b31" }, |
64 | | { TMS320C64X_REG_PCE1, "pce1" }, |
65 | | }; |
66 | | |
67 | | const char *TMS320C64x_reg_name(csh handle, unsigned int reg) |
68 | 44.4k | { |
69 | 44.4k | #ifndef CAPSTONE_DIET |
70 | 44.4k | if (reg >= ARR_SIZE(reg_name_maps)) |
71 | 0 | return NULL; |
72 | | |
73 | 44.4k | return reg_name_maps[reg].name; |
74 | | #else |
75 | | return NULL; |
76 | | #endif |
77 | 44.4k | } |
78 | | |
79 | | tms320c64x_reg TMS320C64x_reg_id(char *name) |
80 | 0 | { |
81 | 0 | int i; |
82 | |
|
83 | 0 | for (i = 1; i < ARR_SIZE(reg_name_maps); i++) { |
84 | 0 | if (!strcmp(name, reg_name_maps[i].name)) |
85 | 0 | return reg_name_maps[i].id; |
86 | 0 | } |
87 | | |
88 | 0 | return 0; |
89 | 0 | } |
90 | | |
91 | | static const insn_map insns[] = { |
92 | | { 0, |
93 | | 0, |
94 | | #ifndef CAPSTONE_DIET |
95 | | { 0 }, |
96 | | { 0 }, |
97 | | { 0 }, |
98 | | 0, |
99 | | 0 |
100 | | #endif |
101 | | }, |
102 | | |
103 | | { TMS320C64x_ABS2_l2_rr, |
104 | | TMS320C64X_INS_ABS2, |
105 | | #ifndef CAPSTONE_DIET |
106 | | { 0 }, |
107 | | { 0 }, |
108 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
109 | | 0, |
110 | | 0 |
111 | | #endif |
112 | | }, |
113 | | { TMS320C64x_ABS_l1_pp, |
114 | | TMS320C64X_INS_ABS, |
115 | | #ifndef CAPSTONE_DIET |
116 | | { 0 }, |
117 | | { 0 }, |
118 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
119 | | 0, |
120 | | 0 |
121 | | #endif |
122 | | }, |
123 | | { TMS320C64x_ABS_l1_rr, |
124 | | TMS320C64X_INS_ABS, |
125 | | #ifndef CAPSTONE_DIET |
126 | | { 0 }, |
127 | | { 0 }, |
128 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
129 | | 0, |
130 | | 0 |
131 | | #endif |
132 | | }, |
133 | | { TMS320C64x_ADD2_d2_rrr, |
134 | | TMS320C64X_INS_ADD2, |
135 | | #ifndef CAPSTONE_DIET |
136 | | { 0 }, |
137 | | { 0 }, |
138 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
139 | | 0, |
140 | | 0 |
141 | | #endif |
142 | | }, |
143 | | { TMS320C64x_ADD2_l1_rrr_x2, |
144 | | TMS320C64X_INS_ADD2, |
145 | | #ifndef CAPSTONE_DIET |
146 | | { 0 }, |
147 | | { 0 }, |
148 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
149 | | 0, |
150 | | 0 |
151 | | #endif |
152 | | }, |
153 | | { TMS320C64x_ADD2_s1_rrr, |
154 | | TMS320C64X_INS_ADD2, |
155 | | #ifndef CAPSTONE_DIET |
156 | | { 0 }, |
157 | | { 0 }, |
158 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
159 | | 0, |
160 | | 0 |
161 | | #endif |
162 | | }, |
163 | | { TMS320C64x_ADD4_l1_rrr_x2, |
164 | | TMS320C64X_INS_ADD4, |
165 | | #ifndef CAPSTONE_DIET |
166 | | { 0 }, |
167 | | { 0 }, |
168 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
169 | | 0, |
170 | | 0 |
171 | | #endif |
172 | | }, |
173 | | { TMS320C64x_ADDAB_d1_rir, |
174 | | TMS320C64X_INS_ADDAB, |
175 | | #ifndef CAPSTONE_DIET |
176 | | { 0 }, |
177 | | { 0 }, |
178 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
179 | | 0, |
180 | | 0 |
181 | | #endif |
182 | | }, |
183 | | { TMS320C64x_ADDAB_d1_rrr, |
184 | | TMS320C64X_INS_ADDAB, |
185 | | #ifndef CAPSTONE_DIET |
186 | | { 0 }, |
187 | | { 0 }, |
188 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
189 | | 0, |
190 | | 0 |
191 | | #endif |
192 | | }, |
193 | | { TMS320C64x_ADDAD_d1_rir, |
194 | | TMS320C64X_INS_ADDAD, |
195 | | #ifndef CAPSTONE_DIET |
196 | | { 0 }, |
197 | | { 0 }, |
198 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
199 | | 0, |
200 | | 0 |
201 | | #endif |
202 | | }, |
203 | | { TMS320C64x_ADDAD_d1_rrr, |
204 | | TMS320C64X_INS_ADDAD, |
205 | | #ifndef CAPSTONE_DIET |
206 | | { 0 }, |
207 | | { 0 }, |
208 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
209 | | 0, |
210 | | 0 |
211 | | #endif |
212 | | }, |
213 | | { TMS320C64x_ADDAH_d1_rir, |
214 | | TMS320C64X_INS_ADDAH, |
215 | | #ifndef CAPSTONE_DIET |
216 | | { 0 }, |
217 | | { 0 }, |
218 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
219 | | 0, |
220 | | 0 |
221 | | #endif |
222 | | }, |
223 | | { TMS320C64x_ADDAH_d1_rrr, |
224 | | TMS320C64X_INS_ADDAH, |
225 | | #ifndef CAPSTONE_DIET |
226 | | { 0 }, |
227 | | { 0 }, |
228 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
229 | | 0, |
230 | | 0 |
231 | | #endif |
232 | | }, |
233 | | { TMS320C64x_ADDAW_d1_rir, |
234 | | TMS320C64X_INS_ADDAW, |
235 | | #ifndef CAPSTONE_DIET |
236 | | { 0 }, |
237 | | { 0 }, |
238 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
239 | | 0, |
240 | | 0 |
241 | | #endif |
242 | | }, |
243 | | { TMS320C64x_ADDAW_d1_rrr, |
244 | | TMS320C64X_INS_ADDAW, |
245 | | #ifndef CAPSTONE_DIET |
246 | | { 0 }, |
247 | | { 0 }, |
248 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
249 | | 0, |
250 | | 0 |
251 | | #endif |
252 | | }, |
253 | | { TMS320C64x_ADDKPC_s3_iir, |
254 | | TMS320C64X_INS_ADDKPC, |
255 | | #ifndef CAPSTONE_DIET |
256 | | { 0 }, |
257 | | { 0 }, |
258 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
259 | | 0, |
260 | | 0 |
261 | | #endif |
262 | | }, |
263 | | { TMS320C64x_ADDK_s2_ir, |
264 | | TMS320C64X_INS_ADDK, |
265 | | #ifndef CAPSTONE_DIET |
266 | | { 0 }, |
267 | | { 0 }, |
268 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
269 | | 0, |
270 | | 0 |
271 | | #endif |
272 | | }, |
273 | | { TMS320C64x_ADDU_l1_rpp, |
274 | | TMS320C64X_INS_ADDU, |
275 | | #ifndef CAPSTONE_DIET |
276 | | { 0 }, |
277 | | { 0 }, |
278 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
279 | | 0, |
280 | | 0 |
281 | | #endif |
282 | | }, |
283 | | { TMS320C64x_ADDU_l1_rrp_x2, |
284 | | TMS320C64X_INS_ADDU, |
285 | | #ifndef CAPSTONE_DIET |
286 | | { 0 }, |
287 | | { 0 }, |
288 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
289 | | 0, |
290 | | 0 |
291 | | #endif |
292 | | }, |
293 | | { TMS320C64x_ADD_d1_rir, |
294 | | TMS320C64X_INS_ADD, |
295 | | #ifndef CAPSTONE_DIET |
296 | | { 0 }, |
297 | | { 0 }, |
298 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
299 | | 0, |
300 | | 0 |
301 | | #endif |
302 | | }, |
303 | | { TMS320C64x_ADD_d1_rrr, |
304 | | TMS320C64X_INS_ADD, |
305 | | #ifndef CAPSTONE_DIET |
306 | | { 0 }, |
307 | | { 0 }, |
308 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
309 | | 0, |
310 | | 0 |
311 | | #endif |
312 | | }, |
313 | | { TMS320C64x_ADD_d2_rir, |
314 | | TMS320C64X_INS_ADD, |
315 | | #ifndef CAPSTONE_DIET |
316 | | { 0 }, |
317 | | { 0 }, |
318 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
319 | | 0, |
320 | | 0 |
321 | | #endif |
322 | | }, |
323 | | { TMS320C64x_ADD_d2_rrr, |
324 | | TMS320C64X_INS_ADD, |
325 | | #ifndef CAPSTONE_DIET |
326 | | { 0 }, |
327 | | { 0 }, |
328 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
329 | | 0, |
330 | | 0 |
331 | | #endif |
332 | | }, |
333 | | { TMS320C64x_ADD_l1_ipp, |
334 | | TMS320C64X_INS_ADD, |
335 | | #ifndef CAPSTONE_DIET |
336 | | { 0 }, |
337 | | { 0 }, |
338 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
339 | | 0, |
340 | | 0 |
341 | | #endif |
342 | | }, |
343 | | { TMS320C64x_ADD_l1_irr, |
344 | | TMS320C64X_INS_ADD, |
345 | | #ifndef CAPSTONE_DIET |
346 | | { 0 }, |
347 | | { 0 }, |
348 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
349 | | 0, |
350 | | 0 |
351 | | #endif |
352 | | }, |
353 | | { TMS320C64x_ADD_l1_rpp, |
354 | | TMS320C64X_INS_ADD, |
355 | | #ifndef CAPSTONE_DIET |
356 | | { 0 }, |
357 | | { 0 }, |
358 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
359 | | 0, |
360 | | 0 |
361 | | #endif |
362 | | }, |
363 | | { TMS320C64x_ADD_l1_rrp_x2, |
364 | | TMS320C64X_INS_ADD, |
365 | | #ifndef CAPSTONE_DIET |
366 | | { 0 }, |
367 | | { 0 }, |
368 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
369 | | 0, |
370 | | 0 |
371 | | #endif |
372 | | }, |
373 | | { TMS320C64x_ADD_l1_rrr_x2, |
374 | | TMS320C64X_INS_ADD, |
375 | | #ifndef CAPSTONE_DIET |
376 | | { 0 }, |
377 | | { 0 }, |
378 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
379 | | 0, |
380 | | 0 |
381 | | #endif |
382 | | }, |
383 | | { TMS320C64x_ADD_s1_irr, |
384 | | TMS320C64X_INS_ADD, |
385 | | #ifndef CAPSTONE_DIET |
386 | | { 0 }, |
387 | | { 0 }, |
388 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
389 | | 0, |
390 | | 0 |
391 | | #endif |
392 | | }, |
393 | | { TMS320C64x_ADD_s1_rrr, |
394 | | TMS320C64X_INS_ADD, |
395 | | #ifndef CAPSTONE_DIET |
396 | | { 0 }, |
397 | | { 0 }, |
398 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
399 | | 0, |
400 | | 0 |
401 | | #endif |
402 | | }, |
403 | | { TMS320C64x_ANDN_d2_rrr, |
404 | | TMS320C64X_INS_ANDN, |
405 | | #ifndef CAPSTONE_DIET |
406 | | { 0 }, |
407 | | { 0 }, |
408 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
409 | | 0, |
410 | | 0 |
411 | | #endif |
412 | | }, |
413 | | { TMS320C64x_ANDN_l1_rrr_x2, |
414 | | TMS320C64X_INS_ANDN, |
415 | | #ifndef CAPSTONE_DIET |
416 | | { 0 }, |
417 | | { 0 }, |
418 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
419 | | 0, |
420 | | 0 |
421 | | #endif |
422 | | }, |
423 | | { TMS320C64x_ANDN_s4_rrr, |
424 | | TMS320C64X_INS_ANDN, |
425 | | #ifndef CAPSTONE_DIET |
426 | | { 0 }, |
427 | | { 0 }, |
428 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
429 | | 0, |
430 | | 0 |
431 | | #endif |
432 | | }, |
433 | | { TMS320C64x_AND_d2_rir, |
434 | | TMS320C64X_INS_AND, |
435 | | #ifndef CAPSTONE_DIET |
436 | | { 0 }, |
437 | | { 0 }, |
438 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
439 | | 0, |
440 | | 0 |
441 | | #endif |
442 | | }, |
443 | | { TMS320C64x_AND_d2_rrr, |
444 | | TMS320C64X_INS_AND, |
445 | | #ifndef CAPSTONE_DIET |
446 | | { 0 }, |
447 | | { 0 }, |
448 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
449 | | 0, |
450 | | 0 |
451 | | #endif |
452 | | }, |
453 | | { TMS320C64x_AND_l1_irr, |
454 | | TMS320C64X_INS_AND, |
455 | | #ifndef CAPSTONE_DIET |
456 | | { 0 }, |
457 | | { 0 }, |
458 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
459 | | 0, |
460 | | 0 |
461 | | #endif |
462 | | }, |
463 | | { TMS320C64x_AND_l1_rrr_x2, |
464 | | TMS320C64X_INS_AND, |
465 | | #ifndef CAPSTONE_DIET |
466 | | { 0 }, |
467 | | { 0 }, |
468 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
469 | | 0, |
470 | | 0 |
471 | | #endif |
472 | | }, |
473 | | { TMS320C64x_AND_s1_irr, |
474 | | TMS320C64X_INS_AND, |
475 | | #ifndef CAPSTONE_DIET |
476 | | { 0 }, |
477 | | { 0 }, |
478 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
479 | | 0, |
480 | | 0 |
481 | | #endif |
482 | | }, |
483 | | { TMS320C64x_AND_s1_rrr, |
484 | | TMS320C64X_INS_AND, |
485 | | #ifndef CAPSTONE_DIET |
486 | | { 0 }, |
487 | | { 0 }, |
488 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
489 | | 0, |
490 | | 0 |
491 | | #endif |
492 | | }, |
493 | | { TMS320C64x_AVG2_m1_rrr, |
494 | | TMS320C64X_INS_AVG2, |
495 | | #ifndef CAPSTONE_DIET |
496 | | { 0 }, |
497 | | { 0 }, |
498 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
499 | | 0, |
500 | | 0 |
501 | | #endif |
502 | | }, |
503 | | { TMS320C64x_AVGU4_m1_rrr, |
504 | | TMS320C64X_INS_AVGU4, |
505 | | #ifndef CAPSTONE_DIET |
506 | | { 0 }, |
507 | | { 0 }, |
508 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
509 | | 0, |
510 | | 0 |
511 | | #endif |
512 | | }, |
513 | | { TMS320C64x_BDEC_s8_ir, |
514 | | TMS320C64X_INS_BDEC, |
515 | | #ifndef CAPSTONE_DIET |
516 | | { 0 }, |
517 | | { 0 }, |
518 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
519 | | 1, |
520 | | 0 |
521 | | #endif |
522 | | }, |
523 | | { TMS320C64x_BITC4_m2_rr, |
524 | | TMS320C64X_INS_BITC4, |
525 | | #ifndef CAPSTONE_DIET |
526 | | { 0 }, |
527 | | { 0 }, |
528 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
529 | | 0, |
530 | | 0 |
531 | | #endif |
532 | | }, |
533 | | { TMS320C64x_BNOP_s10_ri, |
534 | | TMS320C64X_INS_BNOP, |
535 | | #ifndef CAPSTONE_DIET |
536 | | { 0 }, |
537 | | { 0 }, |
538 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
539 | | 1, |
540 | | 0 |
541 | | #endif |
542 | | }, |
543 | | { TMS320C64x_BNOP_s9_ii, |
544 | | TMS320C64X_INS_BNOP, |
545 | | #ifndef CAPSTONE_DIET |
546 | | { 0 }, |
547 | | { 0 }, |
548 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
549 | | 1, |
550 | | 0 |
551 | | #endif |
552 | | }, |
553 | | { TMS320C64x_BPOS_s8_ir, |
554 | | TMS320C64X_INS_BPOS, |
555 | | #ifndef CAPSTONE_DIET |
556 | | { 0 }, |
557 | | { 0 }, |
558 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
559 | | 1, |
560 | | 0 |
561 | | #endif |
562 | | }, |
563 | | { TMS320C64x_B_s5_i, |
564 | | TMS320C64X_INS_B, |
565 | | #ifndef CAPSTONE_DIET |
566 | | { 0 }, |
567 | | { 0 }, |
568 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
569 | | 1, |
570 | | 0 |
571 | | #endif |
572 | | }, |
573 | | { TMS320C64x_B_s6_r, |
574 | | TMS320C64X_INS_B, |
575 | | #ifndef CAPSTONE_DIET |
576 | | { 0 }, |
577 | | { 0 }, |
578 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
579 | | 1, |
580 | | 0 |
581 | | #endif |
582 | | }, |
583 | | { TMS320C64x_B_s7_irp, |
584 | | TMS320C64X_INS_B, |
585 | | #ifndef CAPSTONE_DIET |
586 | | { 0 }, |
587 | | { 0 }, |
588 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
589 | | 1, |
590 | | 0 |
591 | | #endif |
592 | | }, |
593 | | { TMS320C64x_B_s7_nrp, |
594 | | TMS320C64X_INS_B, |
595 | | #ifndef CAPSTONE_DIET |
596 | | { 0 }, |
597 | | { 0 }, |
598 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
599 | | 1, |
600 | | 0 |
601 | | #endif |
602 | | }, |
603 | | { TMS320C64x_CLR_s15_riir, |
604 | | TMS320C64X_INS_CLR, |
605 | | #ifndef CAPSTONE_DIET |
606 | | { 0 }, |
607 | | { 0 }, |
608 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
609 | | 0, |
610 | | 0 |
611 | | #endif |
612 | | }, |
613 | | { TMS320C64x_CLR_s1_rrr, |
614 | | TMS320C64X_INS_CLR, |
615 | | #ifndef CAPSTONE_DIET |
616 | | { 0 }, |
617 | | { 0 }, |
618 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
619 | | 0, |
620 | | 0 |
621 | | #endif |
622 | | }, |
623 | | { TMS320C64x_CMPEQ2_s1_rrr, |
624 | | TMS320C64X_INS_CMPEQ2, |
625 | | #ifndef CAPSTONE_DIET |
626 | | { 0 }, |
627 | | { 0 }, |
628 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
629 | | 0, |
630 | | 0 |
631 | | #endif |
632 | | }, |
633 | | { TMS320C64x_CMPEQ4_s1_rrr, |
634 | | TMS320C64X_INS_CMPEQ4, |
635 | | #ifndef CAPSTONE_DIET |
636 | | { 0 }, |
637 | | { 0 }, |
638 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
639 | | 0, |
640 | | 0 |
641 | | #endif |
642 | | }, |
643 | | { TMS320C64x_CMPEQ_l1_ipr, |
644 | | TMS320C64X_INS_CMPEQ, |
645 | | #ifndef CAPSTONE_DIET |
646 | | { 0 }, |
647 | | { 0 }, |
648 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
649 | | 0, |
650 | | 0 |
651 | | #endif |
652 | | }, |
653 | | { TMS320C64x_CMPEQ_l1_irr, |
654 | | TMS320C64X_INS_CMPEQ, |
655 | | #ifndef CAPSTONE_DIET |
656 | | { 0 }, |
657 | | { 0 }, |
658 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
659 | | 0, |
660 | | 0 |
661 | | #endif |
662 | | }, |
663 | | { TMS320C64x_CMPEQ_l1_rpr, |
664 | | TMS320C64X_INS_CMPEQ, |
665 | | #ifndef CAPSTONE_DIET |
666 | | { 0 }, |
667 | | { 0 }, |
668 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
669 | | 0, |
670 | | 0 |
671 | | #endif |
672 | | }, |
673 | | { TMS320C64x_CMPEQ_l1_rrr_x2, |
674 | | TMS320C64X_INS_CMPEQ, |
675 | | #ifndef CAPSTONE_DIET |
676 | | { 0 }, |
677 | | { 0 }, |
678 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
679 | | 0, |
680 | | 0 |
681 | | #endif |
682 | | }, |
683 | | { TMS320C64x_CMPGT2_s1_rrr, |
684 | | TMS320C64X_INS_CMPGT2, |
685 | | #ifndef CAPSTONE_DIET |
686 | | { 0 }, |
687 | | { 0 }, |
688 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
689 | | 0, |
690 | | 0 |
691 | | #endif |
692 | | }, |
693 | | { TMS320C64x_CMPGTU4_s1_rrr, |
694 | | TMS320C64X_INS_CMPGTU4, |
695 | | #ifndef CAPSTONE_DIET |
696 | | { 0 }, |
697 | | { 0 }, |
698 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
699 | | 0, |
700 | | 0 |
701 | | #endif |
702 | | }, |
703 | | { TMS320C64x_CMPGT_l1_ipr, |
704 | | TMS320C64X_INS_CMPGT, |
705 | | #ifndef CAPSTONE_DIET |
706 | | { 0 }, |
707 | | { 0 }, |
708 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
709 | | 0, |
710 | | 0 |
711 | | #endif |
712 | | }, |
713 | | { TMS320C64x_CMPGT_l1_irr, |
714 | | TMS320C64X_INS_CMPGT, |
715 | | #ifndef CAPSTONE_DIET |
716 | | { 0 }, |
717 | | { 0 }, |
718 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
719 | | 0, |
720 | | 0 |
721 | | #endif |
722 | | }, |
723 | | { TMS320C64x_CMPGT_l1_rpr, |
724 | | TMS320C64X_INS_CMPGT, |
725 | | #ifndef CAPSTONE_DIET |
726 | | { 0 }, |
727 | | { 0 }, |
728 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
729 | | 0, |
730 | | 0 |
731 | | #endif |
732 | | }, |
733 | | { TMS320C64x_CMPGT_l1_rrr_x2, |
734 | | TMS320C64X_INS_CMPGT, |
735 | | #ifndef CAPSTONE_DIET |
736 | | { 0 }, |
737 | | { 0 }, |
738 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
739 | | 0, |
740 | | 0 |
741 | | #endif |
742 | | }, |
743 | | { TMS320C64x_CMPLTU_l1_ipr, |
744 | | TMS320C64X_INS_CMPLTU, |
745 | | #ifndef CAPSTONE_DIET |
746 | | { 0 }, |
747 | | { 0 }, |
748 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
749 | | 0, |
750 | | 0 |
751 | | #endif |
752 | | }, |
753 | | { TMS320C64x_CMPLTU_l1_irr, |
754 | | TMS320C64X_INS_CMPLTU, |
755 | | #ifndef CAPSTONE_DIET |
756 | | { 0 }, |
757 | | { 0 }, |
758 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
759 | | 0, |
760 | | 0 |
761 | | #endif |
762 | | }, |
763 | | { TMS320C64x_CMPLTU_l1_rpr, |
764 | | TMS320C64X_INS_CMPLTU, |
765 | | #ifndef CAPSTONE_DIET |
766 | | { 0 }, |
767 | | { 0 }, |
768 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
769 | | 0, |
770 | | 0 |
771 | | #endif |
772 | | }, |
773 | | { TMS320C64x_CMPLTU_l1_rrr_x2, |
774 | | TMS320C64X_INS_CMPLTU, |
775 | | #ifndef CAPSTONE_DIET |
776 | | { 0 }, |
777 | | { 0 }, |
778 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
779 | | 0, |
780 | | 0 |
781 | | #endif |
782 | | }, |
783 | | { TMS320C64x_CMPLT_l1_ipr, |
784 | | TMS320C64X_INS_CMPLT, |
785 | | #ifndef CAPSTONE_DIET |
786 | | { 0 }, |
787 | | { 0 }, |
788 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
789 | | 0, |
790 | | 0 |
791 | | #endif |
792 | | }, |
793 | | { TMS320C64x_CMPLT_l1_irr, |
794 | | TMS320C64X_INS_CMPLT, |
795 | | #ifndef CAPSTONE_DIET |
796 | | { 0 }, |
797 | | { 0 }, |
798 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
799 | | 0, |
800 | | 0 |
801 | | #endif |
802 | | }, |
803 | | { TMS320C64x_CMPLT_l1_rpr, |
804 | | TMS320C64X_INS_CMPLT, |
805 | | #ifndef CAPSTONE_DIET |
806 | | { 0 }, |
807 | | { 0 }, |
808 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
809 | | 0, |
810 | | 0 |
811 | | #endif |
812 | | }, |
813 | | { TMS320C64x_CMPLT_l1_rrr_x2, |
814 | | TMS320C64X_INS_CMPLT, |
815 | | #ifndef CAPSTONE_DIET |
816 | | { 0 }, |
817 | | { 0 }, |
818 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
819 | | 0, |
820 | | 0 |
821 | | #endif |
822 | | }, |
823 | | { TMS320C64x_DEAL_m2_rr, |
824 | | TMS320C64X_INS_DEAL, |
825 | | #ifndef CAPSTONE_DIET |
826 | | { 0 }, |
827 | | { 0 }, |
828 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
829 | | 0, |
830 | | 0 |
831 | | #endif |
832 | | }, |
833 | | { TMS320C64x_DOTP2_m1_rrp, |
834 | | TMS320C64X_INS_DOTP2, |
835 | | #ifndef CAPSTONE_DIET |
836 | | { 0 }, |
837 | | { 0 }, |
838 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
839 | | 0, |
840 | | 0 |
841 | | #endif |
842 | | }, |
843 | | { TMS320C64x_DOTP2_m1_rrr, |
844 | | TMS320C64X_INS_DOTP2, |
845 | | #ifndef CAPSTONE_DIET |
846 | | { 0 }, |
847 | | { 0 }, |
848 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
849 | | 0, |
850 | | 0 |
851 | | #endif |
852 | | }, |
853 | | { TMS320C64x_DOTPN2_m1_rrr, |
854 | | TMS320C64X_INS_DOTPN2, |
855 | | #ifndef CAPSTONE_DIET |
856 | | { 0 }, |
857 | | { 0 }, |
858 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
859 | | 0, |
860 | | 0 |
861 | | #endif |
862 | | }, |
863 | | { TMS320C64x_DOTPNRSU2_m1_rrr, |
864 | | TMS320C64X_INS_DOTPNRSU2, |
865 | | #ifndef CAPSTONE_DIET |
866 | | { 0 }, |
867 | | { 0 }, |
868 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
869 | | 0, |
870 | | 0 |
871 | | #endif |
872 | | }, |
873 | | { TMS320C64x_DOTPRSU2_m1_rrr, |
874 | | TMS320C64X_INS_DOTPRSU2, |
875 | | #ifndef CAPSTONE_DIET |
876 | | { 0 }, |
877 | | { 0 }, |
878 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
879 | | 0, |
880 | | 0 |
881 | | #endif |
882 | | }, |
883 | | { TMS320C64x_DOTPSU4_m1_rrr, |
884 | | TMS320C64X_INS_DOTPSU4, |
885 | | #ifndef CAPSTONE_DIET |
886 | | { 0 }, |
887 | | { 0 }, |
888 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
889 | | 0, |
890 | | 0 |
891 | | #endif |
892 | | }, |
893 | | { TMS320C64x_DOTPU4_m1_rrr, |
894 | | TMS320C64X_INS_DOTPU4, |
895 | | #ifndef CAPSTONE_DIET |
896 | | { 0 }, |
897 | | { 0 }, |
898 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
899 | | 0, |
900 | | 0 |
901 | | #endif |
902 | | }, |
903 | | { TMS320C64x_EXTU_s15_riir, |
904 | | TMS320C64X_INS_EXTU, |
905 | | #ifndef CAPSTONE_DIET |
906 | | { 0 }, |
907 | | { 0 }, |
908 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
909 | | 0, |
910 | | 0 |
911 | | #endif |
912 | | }, |
913 | | { TMS320C64x_EXTU_s1_rrr, |
914 | | TMS320C64X_INS_EXTU, |
915 | | #ifndef CAPSTONE_DIET |
916 | | { 0 }, |
917 | | { 0 }, |
918 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
919 | | 0, |
920 | | 0 |
921 | | #endif |
922 | | }, |
923 | | { TMS320C64x_EXT_s15_riir, |
924 | | TMS320C64X_INS_EXT, |
925 | | #ifndef CAPSTONE_DIET |
926 | | { 0 }, |
927 | | { 0 }, |
928 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
929 | | 0, |
930 | | 0 |
931 | | #endif |
932 | | }, |
933 | | { TMS320C64x_EXT_s1_rrr, |
934 | | TMS320C64X_INS_EXT, |
935 | | #ifndef CAPSTONE_DIET |
936 | | { 0 }, |
937 | | { 0 }, |
938 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
939 | | 0, |
940 | | 0 |
941 | | #endif |
942 | | }, |
943 | | { TMS320C64x_GMPGTU_l1_ipr, |
944 | | TMS320C64X_INS_GMPGTU, |
945 | | #ifndef CAPSTONE_DIET |
946 | | { 0 }, |
947 | | { 0 }, |
948 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
949 | | 0, |
950 | | 0 |
951 | | #endif |
952 | | }, |
953 | | { TMS320C64x_GMPGTU_l1_irr, |
954 | | TMS320C64X_INS_GMPGTU, |
955 | | #ifndef CAPSTONE_DIET |
956 | | { 0 }, |
957 | | { 0 }, |
958 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
959 | | 0, |
960 | | 0 |
961 | | #endif |
962 | | }, |
963 | | { TMS320C64x_GMPGTU_l1_rpr, |
964 | | TMS320C64X_INS_GMPGTU, |
965 | | #ifndef CAPSTONE_DIET |
966 | | { 0 }, |
967 | | { 0 }, |
968 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
969 | | 0, |
970 | | 0 |
971 | | #endif |
972 | | }, |
973 | | { TMS320C64x_GMPGTU_l1_rrr_x2, |
974 | | TMS320C64X_INS_GMPGTU, |
975 | | #ifndef CAPSTONE_DIET |
976 | | { 0 }, |
977 | | { 0 }, |
978 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
979 | | 0, |
980 | | 0 |
981 | | #endif |
982 | | }, |
983 | | { TMS320C64x_GMPY4_m1_rrr, |
984 | | TMS320C64X_INS_GMPY4, |
985 | | #ifndef CAPSTONE_DIET |
986 | | { 0 }, |
987 | | { 0 }, |
988 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
989 | | 0, |
990 | | 0 |
991 | | #endif |
992 | | }, |
993 | | { TMS320C64x_LDBU_d5_mr, |
994 | | TMS320C64X_INS_LDBU, |
995 | | #ifndef CAPSTONE_DIET |
996 | | { 0 }, |
997 | | { 0 }, |
998 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
999 | | 0, |
1000 | | 0 |
1001 | | #endif |
1002 | | }, |
1003 | | { TMS320C64x_LDBU_d6_mr, |
1004 | | TMS320C64X_INS_LDBU, |
1005 | | #ifndef CAPSTONE_DIET |
1006 | | { 0 }, |
1007 | | { 0 }, |
1008 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1009 | | 0, |
1010 | | 0 |
1011 | | #endif |
1012 | | }, |
1013 | | { TMS320C64x_LDB_d5_mr, |
1014 | | TMS320C64X_INS_LDB, |
1015 | | #ifndef CAPSTONE_DIET |
1016 | | { 0 }, |
1017 | | { 0 }, |
1018 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1019 | | 0, |
1020 | | 0 |
1021 | | #endif |
1022 | | }, |
1023 | | { TMS320C64x_LDB_d6_mr, |
1024 | | TMS320C64X_INS_LDB, |
1025 | | #ifndef CAPSTONE_DIET |
1026 | | { 0 }, |
1027 | | { 0 }, |
1028 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1029 | | 0, |
1030 | | 0 |
1031 | | #endif |
1032 | | }, |
1033 | | { TMS320C64x_LDDW_d7_mp, |
1034 | | TMS320C64X_INS_LDDW, |
1035 | | #ifndef CAPSTONE_DIET |
1036 | | { 0 }, |
1037 | | { 0 }, |
1038 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1039 | | 0, |
1040 | | 0 |
1041 | | #endif |
1042 | | }, |
1043 | | { TMS320C64x_LDHU_d5_mr, |
1044 | | TMS320C64X_INS_LDHU, |
1045 | | #ifndef CAPSTONE_DIET |
1046 | | { 0 }, |
1047 | | { 0 }, |
1048 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1049 | | 0, |
1050 | | 0 |
1051 | | #endif |
1052 | | }, |
1053 | | { TMS320C64x_LDHU_d6_mr, |
1054 | | TMS320C64X_INS_LDHU, |
1055 | | #ifndef CAPSTONE_DIET |
1056 | | { 0 }, |
1057 | | { 0 }, |
1058 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1059 | | 0, |
1060 | | 0 |
1061 | | #endif |
1062 | | }, |
1063 | | { TMS320C64x_LDH_d5_mr, |
1064 | | TMS320C64X_INS_LDH, |
1065 | | #ifndef CAPSTONE_DIET |
1066 | | { 0 }, |
1067 | | { 0 }, |
1068 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1069 | | 0, |
1070 | | 0 |
1071 | | #endif |
1072 | | }, |
1073 | | { TMS320C64x_LDH_d6_mr, |
1074 | | TMS320C64X_INS_LDH, |
1075 | | #ifndef CAPSTONE_DIET |
1076 | | { 0 }, |
1077 | | { 0 }, |
1078 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1079 | | 0, |
1080 | | 0 |
1081 | | #endif |
1082 | | }, |
1083 | | { TMS320C64x_LDNDW_d8_mp, |
1084 | | TMS320C64X_INS_LDNDW, |
1085 | | #ifndef CAPSTONE_DIET |
1086 | | { 0 }, |
1087 | | { 0 }, |
1088 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1089 | | 0, |
1090 | | 0 |
1091 | | #endif |
1092 | | }, |
1093 | | { TMS320C64x_LDNW_d5_mr, |
1094 | | TMS320C64X_INS_LDNW, |
1095 | | #ifndef CAPSTONE_DIET |
1096 | | { 0 }, |
1097 | | { 0 }, |
1098 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1099 | | 0, |
1100 | | 0 |
1101 | | #endif |
1102 | | }, |
1103 | | { TMS320C64x_LDW_d5_mr, |
1104 | | TMS320C64X_INS_LDW, |
1105 | | #ifndef CAPSTONE_DIET |
1106 | | { 0 }, |
1107 | | { 0 }, |
1108 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1109 | | 0, |
1110 | | 0 |
1111 | | #endif |
1112 | | }, |
1113 | | { TMS320C64x_LDW_d6_mr, |
1114 | | TMS320C64X_INS_LDW, |
1115 | | #ifndef CAPSTONE_DIET |
1116 | | { 0 }, |
1117 | | { 0 }, |
1118 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1119 | | 0, |
1120 | | 0 |
1121 | | #endif |
1122 | | }, |
1123 | | { TMS320C64x_LMBD_l1_irr, |
1124 | | TMS320C64X_INS_LMBD, |
1125 | | #ifndef CAPSTONE_DIET |
1126 | | { 0 }, |
1127 | | { 0 }, |
1128 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1129 | | 0, |
1130 | | 0 |
1131 | | #endif |
1132 | | }, |
1133 | | { TMS320C64x_LMBD_l1_rrr_x2, |
1134 | | TMS320C64X_INS_LMBD, |
1135 | | #ifndef CAPSTONE_DIET |
1136 | | { 0 }, |
1137 | | { 0 }, |
1138 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1139 | | 0, |
1140 | | 0 |
1141 | | #endif |
1142 | | }, |
1143 | | { TMS320C64x_MAX2_l1_rrr_x2, |
1144 | | TMS320C64X_INS_MAX2, |
1145 | | #ifndef CAPSTONE_DIET |
1146 | | { 0 }, |
1147 | | { 0 }, |
1148 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1149 | | 0, |
1150 | | 0 |
1151 | | #endif |
1152 | | }, |
1153 | | { TMS320C64x_MAXU4_l1_rrr_x2, |
1154 | | TMS320C64X_INS_MAXU4, |
1155 | | #ifndef CAPSTONE_DIET |
1156 | | { 0 }, |
1157 | | { 0 }, |
1158 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1159 | | 0, |
1160 | | 0 |
1161 | | #endif |
1162 | | }, |
1163 | | { TMS320C64x_MIN2_l1_rrr_x2, |
1164 | | TMS320C64X_INS_MIN2, |
1165 | | #ifndef CAPSTONE_DIET |
1166 | | { 0 }, |
1167 | | { 0 }, |
1168 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1169 | | 0, |
1170 | | 0 |
1171 | | #endif |
1172 | | }, |
1173 | | { TMS320C64x_MINU4_l1_rrr_x2, |
1174 | | TMS320C64X_INS_MINU4, |
1175 | | #ifndef CAPSTONE_DIET |
1176 | | { 0 }, |
1177 | | { 0 }, |
1178 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1179 | | 0, |
1180 | | 0 |
1181 | | #endif |
1182 | | }, |
1183 | | { TMS320C64x_MPY2_m1_rrp, |
1184 | | TMS320C64X_INS_MPY2, |
1185 | | #ifndef CAPSTONE_DIET |
1186 | | { 0 }, |
1187 | | { 0 }, |
1188 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1189 | | 0, |
1190 | | 0 |
1191 | | #endif |
1192 | | }, |
1193 | | { TMS320C64x_MPYHIR_m1_rrr, |
1194 | | TMS320C64X_INS_MPYHIR, |
1195 | | #ifndef CAPSTONE_DIET |
1196 | | { 0 }, |
1197 | | { 0 }, |
1198 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1199 | | 0, |
1200 | | 0 |
1201 | | #endif |
1202 | | }, |
1203 | | { TMS320C64x_MPYHI_m1_rrp, |
1204 | | TMS320C64X_INS_MPYHI, |
1205 | | #ifndef CAPSTONE_DIET |
1206 | | { 0 }, |
1207 | | { 0 }, |
1208 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1209 | | 0, |
1210 | | 0 |
1211 | | #endif |
1212 | | }, |
1213 | | { TMS320C64x_MPYHLU_m4_rrr, |
1214 | | TMS320C64X_INS_MPYHLU, |
1215 | | #ifndef CAPSTONE_DIET |
1216 | | { 0 }, |
1217 | | { 0 }, |
1218 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1219 | | 0, |
1220 | | 0 |
1221 | | #endif |
1222 | | }, |
1223 | | { TMS320C64x_MPYHL_m4_rrr, |
1224 | | TMS320C64X_INS_MPYHL, |
1225 | | #ifndef CAPSTONE_DIET |
1226 | | { 0 }, |
1227 | | { 0 }, |
1228 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1229 | | 0, |
1230 | | 0 |
1231 | | #endif |
1232 | | }, |
1233 | | { TMS320C64x_MPYHSLU_m4_rrr, |
1234 | | TMS320C64X_INS_MPYHSLU, |
1235 | | #ifndef CAPSTONE_DIET |
1236 | | { 0 }, |
1237 | | { 0 }, |
1238 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1239 | | 0, |
1240 | | 0 |
1241 | | #endif |
1242 | | }, |
1243 | | { TMS320C64x_MPYHSU_m4_rrr, |
1244 | | TMS320C64X_INS_MPYHSU, |
1245 | | #ifndef CAPSTONE_DIET |
1246 | | { 0 }, |
1247 | | { 0 }, |
1248 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1249 | | 0, |
1250 | | 0 |
1251 | | #endif |
1252 | | }, |
1253 | | { TMS320C64x_MPYHULS_m4_rrr, |
1254 | | TMS320C64X_INS_MPYHULS, |
1255 | | #ifndef CAPSTONE_DIET |
1256 | | { 0 }, |
1257 | | { 0 }, |
1258 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1259 | | 0, |
1260 | | 0 |
1261 | | #endif |
1262 | | }, |
1263 | | { TMS320C64x_MPYHUS_m4_rrr, |
1264 | | TMS320C64X_INS_MPYHUS, |
1265 | | #ifndef CAPSTONE_DIET |
1266 | | { 0 }, |
1267 | | { 0 }, |
1268 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1269 | | 0, |
1270 | | 0 |
1271 | | #endif |
1272 | | }, |
1273 | | { TMS320C64x_MPYHU_m4_rrr, |
1274 | | TMS320C64X_INS_MPYHU, |
1275 | | #ifndef CAPSTONE_DIET |
1276 | | { 0 }, |
1277 | | { 0 }, |
1278 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1279 | | 0, |
1280 | | 0 |
1281 | | #endif |
1282 | | }, |
1283 | | { TMS320C64x_MPYH_m4_rrr, |
1284 | | TMS320C64X_INS_MPYH, |
1285 | | #ifndef CAPSTONE_DIET |
1286 | | { 0 }, |
1287 | | { 0 }, |
1288 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1289 | | 0, |
1290 | | 0 |
1291 | | #endif |
1292 | | }, |
1293 | | { TMS320C64x_MPYLHU_m4_rrr, |
1294 | | TMS320C64X_INS_MPYLHU, |
1295 | | #ifndef CAPSTONE_DIET |
1296 | | { 0 }, |
1297 | | { 0 }, |
1298 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1299 | | 0, |
1300 | | 0 |
1301 | | #endif |
1302 | | }, |
1303 | | { TMS320C64x_MPYLH_m4_rrr, |
1304 | | TMS320C64X_INS_MPYLH, |
1305 | | #ifndef CAPSTONE_DIET |
1306 | | { 0 }, |
1307 | | { 0 }, |
1308 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1309 | | 0, |
1310 | | 0 |
1311 | | #endif |
1312 | | }, |
1313 | | { TMS320C64x_MPYLIR_m1_rrr, |
1314 | | TMS320C64X_INS_MPYLIR, |
1315 | | #ifndef CAPSTONE_DIET |
1316 | | { 0 }, |
1317 | | { 0 }, |
1318 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1319 | | 0, |
1320 | | 0 |
1321 | | #endif |
1322 | | }, |
1323 | | { TMS320C64x_MPYLI_m1_rrp, |
1324 | | TMS320C64X_INS_MPYLI, |
1325 | | #ifndef CAPSTONE_DIET |
1326 | | { 0 }, |
1327 | | { 0 }, |
1328 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1329 | | 0, |
1330 | | 0 |
1331 | | #endif |
1332 | | }, |
1333 | | { TMS320C64x_MPYLSHU_m4_rrr, |
1334 | | TMS320C64X_INS_MPYLSHU, |
1335 | | #ifndef CAPSTONE_DIET |
1336 | | { 0 }, |
1337 | | { 0 }, |
1338 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1339 | | 0, |
1340 | | 0 |
1341 | | #endif |
1342 | | }, |
1343 | | { TMS320C64x_MPYLUHS_m4_rrr, |
1344 | | TMS320C64X_INS_MPYLUHS, |
1345 | | #ifndef CAPSTONE_DIET |
1346 | | { 0 }, |
1347 | | { 0 }, |
1348 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1349 | | 0, |
1350 | | 0 |
1351 | | #endif |
1352 | | }, |
1353 | | { TMS320C64x_MPYSU4_m1_rrp, |
1354 | | TMS320C64X_INS_MPYSU4, |
1355 | | #ifndef CAPSTONE_DIET |
1356 | | { 0 }, |
1357 | | { 0 }, |
1358 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1359 | | 0, |
1360 | | 0 |
1361 | | #endif |
1362 | | }, |
1363 | | { TMS320C64x_MPYSU_m4_irr, |
1364 | | TMS320C64X_INS_MPYSU, |
1365 | | #ifndef CAPSTONE_DIET |
1366 | | { 0 }, |
1367 | | { 0 }, |
1368 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1369 | | 0, |
1370 | | 0 |
1371 | | #endif |
1372 | | }, |
1373 | | { TMS320C64x_MPYSU_m4_rrr, |
1374 | | TMS320C64X_INS_MPYSU, |
1375 | | #ifndef CAPSTONE_DIET |
1376 | | { 0 }, |
1377 | | { 0 }, |
1378 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1379 | | 0, |
1380 | | 0 |
1381 | | #endif |
1382 | | }, |
1383 | | { TMS320C64x_MPYU4_m1_rrp, |
1384 | | TMS320C64X_INS_MPYU4, |
1385 | | #ifndef CAPSTONE_DIET |
1386 | | { 0 }, |
1387 | | { 0 }, |
1388 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1389 | | 0, |
1390 | | 0 |
1391 | | #endif |
1392 | | }, |
1393 | | { TMS320C64x_MPYUS_m4_rrr, |
1394 | | TMS320C64X_INS_MPYUS, |
1395 | | #ifndef CAPSTONE_DIET |
1396 | | { 0 }, |
1397 | | { 0 }, |
1398 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1399 | | 0, |
1400 | | 0 |
1401 | | #endif |
1402 | | }, |
1403 | | { TMS320C64x_MPYU_m4_rrr, |
1404 | | TMS320C64X_INS_MPYU, |
1405 | | #ifndef CAPSTONE_DIET |
1406 | | { 0 }, |
1407 | | { 0 }, |
1408 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1409 | | 0, |
1410 | | 0 |
1411 | | #endif |
1412 | | }, |
1413 | | { TMS320C64x_MPY_m4_irr, |
1414 | | TMS320C64X_INS_MPY, |
1415 | | #ifndef CAPSTONE_DIET |
1416 | | { 0 }, |
1417 | | { 0 }, |
1418 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1419 | | 0, |
1420 | | 0 |
1421 | | #endif |
1422 | | }, |
1423 | | { TMS320C64x_MPY_m4_rrr, |
1424 | | TMS320C64X_INS_MPY, |
1425 | | #ifndef CAPSTONE_DIET |
1426 | | { 0 }, |
1427 | | { 0 }, |
1428 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1429 | | 0, |
1430 | | 0 |
1431 | | #endif |
1432 | | }, |
1433 | | { TMS320C64x_MVC_s1_rr, |
1434 | | TMS320C64X_INS_MVC, |
1435 | | #ifndef CAPSTONE_DIET |
1436 | | { 0 }, |
1437 | | { 0 }, |
1438 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1439 | | 0, |
1440 | | 0 |
1441 | | #endif |
1442 | | }, |
1443 | | { TMS320C64x_MVC_s1_rr2, |
1444 | | TMS320C64X_INS_MVC, |
1445 | | #ifndef CAPSTONE_DIET |
1446 | | { 0 }, |
1447 | | { 0 }, |
1448 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1449 | | 0, |
1450 | | 0 |
1451 | | #endif |
1452 | | }, |
1453 | | { TMS320C64x_MVD_m2_rr, |
1454 | | TMS320C64X_INS_MVD, |
1455 | | #ifndef CAPSTONE_DIET |
1456 | | { 0 }, |
1457 | | { 0 }, |
1458 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1459 | | 0, |
1460 | | 0 |
1461 | | #endif |
1462 | | }, |
1463 | | { TMS320C64x_MVKLH_s12_ir, |
1464 | | TMS320C64X_INS_MVKLH, |
1465 | | #ifndef CAPSTONE_DIET |
1466 | | { 0 }, |
1467 | | { 0 }, |
1468 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1469 | | 0, |
1470 | | 0 |
1471 | | #endif |
1472 | | }, |
1473 | | { TMS320C64x_MVKL_s12_ir, |
1474 | | TMS320C64X_INS_MVKL, |
1475 | | #ifndef CAPSTONE_DIET |
1476 | | { 0 }, |
1477 | | { 0 }, |
1478 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1479 | | 0, |
1480 | | 0 |
1481 | | #endif |
1482 | | }, |
1483 | | { TMS320C64x_MVK_d1_rr, |
1484 | | TMS320C64X_INS_MVK, |
1485 | | #ifndef CAPSTONE_DIET |
1486 | | { 0 }, |
1487 | | { 0 }, |
1488 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1489 | | 0, |
1490 | | 0 |
1491 | | #endif |
1492 | | }, |
1493 | | { TMS320C64x_MVK_l2_ir, |
1494 | | TMS320C64X_INS_MVK, |
1495 | | #ifndef CAPSTONE_DIET |
1496 | | { 0 }, |
1497 | | { 0 }, |
1498 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1499 | | 0, |
1500 | | 0 |
1501 | | #endif |
1502 | | }, |
1503 | | { TMS320C64x_NOP_n, |
1504 | | TMS320C64X_INS_NOP, |
1505 | | #ifndef CAPSTONE_DIET |
1506 | | { 0 }, |
1507 | | { 0 }, |
1508 | | { TMS320C64X_GRP_FUNIT_NO, 0 }, |
1509 | | 0, |
1510 | | 0 |
1511 | | #endif |
1512 | | }, |
1513 | | { TMS320C64x_NORM_l1_pr, |
1514 | | TMS320C64X_INS_NORM, |
1515 | | #ifndef CAPSTONE_DIET |
1516 | | { 0 }, |
1517 | | { 0 }, |
1518 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1519 | | 0, |
1520 | | 0 |
1521 | | #endif |
1522 | | }, |
1523 | | { TMS320C64x_NORM_l1_rr, |
1524 | | TMS320C64X_INS_NORM, |
1525 | | #ifndef CAPSTONE_DIET |
1526 | | { 0 }, |
1527 | | { 0 }, |
1528 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1529 | | 0, |
1530 | | 0 |
1531 | | #endif |
1532 | | }, |
1533 | | { TMS320C64x_OR_d2_rir, |
1534 | | TMS320C64X_INS_OR, |
1535 | | #ifndef CAPSTONE_DIET |
1536 | | { 0 }, |
1537 | | { 0 }, |
1538 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1539 | | 0, |
1540 | | 0 |
1541 | | #endif |
1542 | | }, |
1543 | | { TMS320C64x_OR_d2_rrr, |
1544 | | TMS320C64X_INS_OR, |
1545 | | #ifndef CAPSTONE_DIET |
1546 | | { 0 }, |
1547 | | { 0 }, |
1548 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
1549 | | 0, |
1550 | | 0 |
1551 | | #endif |
1552 | | }, |
1553 | | { TMS320C64x_OR_l1_irr, |
1554 | | TMS320C64X_INS_OR, |
1555 | | #ifndef CAPSTONE_DIET |
1556 | | { 0 }, |
1557 | | { 0 }, |
1558 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1559 | | 0, |
1560 | | 0 |
1561 | | #endif |
1562 | | }, |
1563 | | { TMS320C64x_OR_l1_rrr_x2, |
1564 | | TMS320C64X_INS_OR, |
1565 | | #ifndef CAPSTONE_DIET |
1566 | | { 0 }, |
1567 | | { 0 }, |
1568 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1569 | | 0, |
1570 | | 0 |
1571 | | #endif |
1572 | | }, |
1573 | | { TMS320C64x_OR_s1_irr, |
1574 | | TMS320C64X_INS_OR, |
1575 | | #ifndef CAPSTONE_DIET |
1576 | | { 0 }, |
1577 | | { 0 }, |
1578 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1579 | | 0, |
1580 | | 0 |
1581 | | #endif |
1582 | | }, |
1583 | | { TMS320C64x_OR_s1_rrr, |
1584 | | TMS320C64X_INS_OR, |
1585 | | #ifndef CAPSTONE_DIET |
1586 | | { 0 }, |
1587 | | { 0 }, |
1588 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1589 | | 0, |
1590 | | 0 |
1591 | | #endif |
1592 | | }, |
1593 | | { TMS320C64x_PACK2_l1_rrr_x2, |
1594 | | TMS320C64X_INS_PACK2, |
1595 | | #ifndef CAPSTONE_DIET |
1596 | | { 0 }, |
1597 | | { 0 }, |
1598 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1599 | | 0, |
1600 | | 0 |
1601 | | #endif |
1602 | | }, |
1603 | | { TMS320C64x_PACK2_s4_rrr, |
1604 | | TMS320C64X_INS_PACK2, |
1605 | | #ifndef CAPSTONE_DIET |
1606 | | { 0 }, |
1607 | | { 0 }, |
1608 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1609 | | 0, |
1610 | | 0 |
1611 | | #endif |
1612 | | }, |
1613 | | { TMS320C64x_PACKH2_l1_rrr_x2, |
1614 | | TMS320C64X_INS_PACKH2, |
1615 | | #ifndef CAPSTONE_DIET |
1616 | | { 0 }, |
1617 | | { 0 }, |
1618 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1619 | | 0, |
1620 | | 0 |
1621 | | #endif |
1622 | | }, |
1623 | | { TMS320C64x_PACKH2_s1_rrr, |
1624 | | TMS320C64X_INS_PACKH2, |
1625 | | #ifndef CAPSTONE_DIET |
1626 | | { 0 }, |
1627 | | { 0 }, |
1628 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1629 | | 0, |
1630 | | 0 |
1631 | | #endif |
1632 | | }, |
1633 | | { TMS320C64x_PACKH4_l1_rrr_x2, |
1634 | | TMS320C64X_INS_PACKH4, |
1635 | | #ifndef CAPSTONE_DIET |
1636 | | { 0 }, |
1637 | | { 0 }, |
1638 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1639 | | 0, |
1640 | | 0 |
1641 | | #endif |
1642 | | }, |
1643 | | { TMS320C64x_PACKHL2_l1_rrr_x2, |
1644 | | TMS320C64X_INS_PACKHL2, |
1645 | | #ifndef CAPSTONE_DIET |
1646 | | { 0 }, |
1647 | | { 0 }, |
1648 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1649 | | 0, |
1650 | | 0 |
1651 | | #endif |
1652 | | }, |
1653 | | { TMS320C64x_PACKHL2_s1_rrr, |
1654 | | TMS320C64X_INS_PACKHL2, |
1655 | | #ifndef CAPSTONE_DIET |
1656 | | { 0 }, |
1657 | | { 0 }, |
1658 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1659 | | 0, |
1660 | | 0 |
1661 | | #endif |
1662 | | }, |
1663 | | { TMS320C64x_PACKL4_l1_rrr_x2, |
1664 | | TMS320C64X_INS_PACKL4, |
1665 | | #ifndef CAPSTONE_DIET |
1666 | | { 0 }, |
1667 | | { 0 }, |
1668 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1669 | | 0, |
1670 | | 0 |
1671 | | #endif |
1672 | | }, |
1673 | | { TMS320C64x_PACKLH2_l1_rrr_x2, |
1674 | | TMS320C64X_INS_PACKLH2, |
1675 | | #ifndef CAPSTONE_DIET |
1676 | | { 0 }, |
1677 | | { 0 }, |
1678 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1679 | | 0, |
1680 | | 0 |
1681 | | #endif |
1682 | | }, |
1683 | | { TMS320C64x_PACKLH2_s1_rrr, |
1684 | | TMS320C64X_INS_PACKLH2, |
1685 | | #ifndef CAPSTONE_DIET |
1686 | | { 0 }, |
1687 | | { 0 }, |
1688 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1689 | | 0, |
1690 | | 0 |
1691 | | #endif |
1692 | | }, |
1693 | | { TMS320C64x_ROTL_m1_rir, |
1694 | | TMS320C64X_INS_ROTL, |
1695 | | #ifndef CAPSTONE_DIET |
1696 | | { 0 }, |
1697 | | { 0 }, |
1698 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1699 | | 0, |
1700 | | 0 |
1701 | | #endif |
1702 | | }, |
1703 | | { TMS320C64x_ROTL_m1_rrr, |
1704 | | TMS320C64X_INS_ROTL, |
1705 | | #ifndef CAPSTONE_DIET |
1706 | | { 0 }, |
1707 | | { 0 }, |
1708 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1709 | | 0, |
1710 | | 0 |
1711 | | #endif |
1712 | | }, |
1713 | | { TMS320C64x_SADD2_s4_rrr, |
1714 | | TMS320C64X_INS_SADD2, |
1715 | | #ifndef CAPSTONE_DIET |
1716 | | { 0 }, |
1717 | | { 0 }, |
1718 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1719 | | 0, |
1720 | | 0 |
1721 | | #endif |
1722 | | }, |
1723 | | { TMS320C64x_SADDU4_s4_rrr, |
1724 | | TMS320C64X_INS_SADDU4, |
1725 | | #ifndef CAPSTONE_DIET |
1726 | | { 0 }, |
1727 | | { 0 }, |
1728 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1729 | | 0, |
1730 | | 0 |
1731 | | #endif |
1732 | | }, |
1733 | | { TMS320C64x_SADDUS2_s4_rrr, |
1734 | | TMS320C64X_INS_SADDUS2, |
1735 | | #ifndef CAPSTONE_DIET |
1736 | | { 0 }, |
1737 | | { 0 }, |
1738 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1739 | | 0, |
1740 | | 0 |
1741 | | #endif |
1742 | | }, |
1743 | | { TMS320C64x_SADD_l1_ipp, |
1744 | | TMS320C64X_INS_SADD, |
1745 | | #ifndef CAPSTONE_DIET |
1746 | | { 0 }, |
1747 | | { 0 }, |
1748 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1749 | | 0, |
1750 | | 0 |
1751 | | #endif |
1752 | | }, |
1753 | | { TMS320C64x_SADD_l1_irr, |
1754 | | TMS320C64X_INS_SADD, |
1755 | | #ifndef CAPSTONE_DIET |
1756 | | { 0 }, |
1757 | | { 0 }, |
1758 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1759 | | 0, |
1760 | | 0 |
1761 | | #endif |
1762 | | }, |
1763 | | { TMS320C64x_SADD_l1_rpp, |
1764 | | TMS320C64X_INS_SADD, |
1765 | | #ifndef CAPSTONE_DIET |
1766 | | { 0 }, |
1767 | | { 0 }, |
1768 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1769 | | 0, |
1770 | | 0 |
1771 | | #endif |
1772 | | }, |
1773 | | { TMS320C64x_SADD_l1_rrr_x2, |
1774 | | TMS320C64X_INS_SADD, |
1775 | | #ifndef CAPSTONE_DIET |
1776 | | { 0 }, |
1777 | | { 0 }, |
1778 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1779 | | 0, |
1780 | | 0 |
1781 | | #endif |
1782 | | }, |
1783 | | { TMS320C64x_SADD_s1_rrr, |
1784 | | TMS320C64X_INS_SADD, |
1785 | | #ifndef CAPSTONE_DIET |
1786 | | { 0 }, |
1787 | | { 0 }, |
1788 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1789 | | 0, |
1790 | | 0 |
1791 | | #endif |
1792 | | }, |
1793 | | { TMS320C64x_SAT_l1_pr, |
1794 | | TMS320C64X_INS_SAT, |
1795 | | #ifndef CAPSTONE_DIET |
1796 | | { 0 }, |
1797 | | { 0 }, |
1798 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1799 | | 0, |
1800 | | 0 |
1801 | | #endif |
1802 | | }, |
1803 | | { TMS320C64x_SET_s15_riir, |
1804 | | TMS320C64X_INS_SET, |
1805 | | #ifndef CAPSTONE_DIET |
1806 | | { 0 }, |
1807 | | { 0 }, |
1808 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1809 | | 0, |
1810 | | 0 |
1811 | | #endif |
1812 | | }, |
1813 | | { TMS320C64x_SET_s1_rrr, |
1814 | | TMS320C64X_INS_SET, |
1815 | | #ifndef CAPSTONE_DIET |
1816 | | { 0 }, |
1817 | | { 0 }, |
1818 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1819 | | 0, |
1820 | | 0 |
1821 | | #endif |
1822 | | }, |
1823 | | { TMS320C64x_SHFL_m2_rr, |
1824 | | TMS320C64X_INS_SHFL, |
1825 | | #ifndef CAPSTONE_DIET |
1826 | | { 0 }, |
1827 | | { 0 }, |
1828 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
1829 | | 0, |
1830 | | 0 |
1831 | | #endif |
1832 | | }, |
1833 | | { TMS320C64x_SHLMB_l1_rrr_x2, |
1834 | | TMS320C64X_INS_SHLMB, |
1835 | | #ifndef CAPSTONE_DIET |
1836 | | { 0 }, |
1837 | | { 0 }, |
1838 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1839 | | 0, |
1840 | | 0 |
1841 | | #endif |
1842 | | }, |
1843 | | { TMS320C64x_SHLMB_s4_rrr, |
1844 | | TMS320C64X_INS_SHLMB, |
1845 | | #ifndef CAPSTONE_DIET |
1846 | | { 0 }, |
1847 | | { 0 }, |
1848 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1849 | | 0, |
1850 | | 0 |
1851 | | #endif |
1852 | | }, |
1853 | | { TMS320C64x_SHL_s1_pip, |
1854 | | TMS320C64X_INS_SHL, |
1855 | | #ifndef CAPSTONE_DIET |
1856 | | { 0 }, |
1857 | | { 0 }, |
1858 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1859 | | 0, |
1860 | | 0 |
1861 | | #endif |
1862 | | }, |
1863 | | { TMS320C64x_SHL_s1_prp, |
1864 | | TMS320C64X_INS_SHL, |
1865 | | #ifndef CAPSTONE_DIET |
1866 | | { 0 }, |
1867 | | { 0 }, |
1868 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1869 | | 0, |
1870 | | 0 |
1871 | | #endif |
1872 | | }, |
1873 | | { TMS320C64x_SHL_s1_rip, |
1874 | | TMS320C64X_INS_SHL, |
1875 | | #ifndef CAPSTONE_DIET |
1876 | | { 0 }, |
1877 | | { 0 }, |
1878 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1879 | | 0, |
1880 | | 0 |
1881 | | #endif |
1882 | | }, |
1883 | | { TMS320C64x_SHL_s1_rir, |
1884 | | TMS320C64X_INS_SHL, |
1885 | | #ifndef CAPSTONE_DIET |
1886 | | { 0 }, |
1887 | | { 0 }, |
1888 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1889 | | 0, |
1890 | | 0 |
1891 | | #endif |
1892 | | }, |
1893 | | { TMS320C64x_SHL_s1_rrp, |
1894 | | TMS320C64X_INS_SHL, |
1895 | | #ifndef CAPSTONE_DIET |
1896 | | { 0 }, |
1897 | | { 0 }, |
1898 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1899 | | 0, |
1900 | | 0 |
1901 | | #endif |
1902 | | }, |
1903 | | { TMS320C64x_SHL_s1_rrr, |
1904 | | TMS320C64X_INS_SHL, |
1905 | | #ifndef CAPSTONE_DIET |
1906 | | { 0 }, |
1907 | | { 0 }, |
1908 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1909 | | 0, |
1910 | | 0 |
1911 | | #endif |
1912 | | }, |
1913 | | { TMS320C64x_SHR2_s1_rir, |
1914 | | TMS320C64X_INS_SHR2, |
1915 | | #ifndef CAPSTONE_DIET |
1916 | | { 0 }, |
1917 | | { 0 }, |
1918 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1919 | | 0, |
1920 | | 0 |
1921 | | #endif |
1922 | | }, |
1923 | | { TMS320C64x_SHR2_s4_rrr, |
1924 | | TMS320C64X_INS_SHR2, |
1925 | | #ifndef CAPSTONE_DIET |
1926 | | { 0 }, |
1927 | | { 0 }, |
1928 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1929 | | 0, |
1930 | | 0 |
1931 | | #endif |
1932 | | }, |
1933 | | { TMS320C64x_SHRMB_l1_rrr_x2, |
1934 | | TMS320C64X_INS_SHRMB, |
1935 | | #ifndef CAPSTONE_DIET |
1936 | | { 0 }, |
1937 | | { 0 }, |
1938 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
1939 | | 0, |
1940 | | 0 |
1941 | | #endif |
1942 | | }, |
1943 | | { TMS320C64x_SHRMB_s4_rrr, |
1944 | | TMS320C64X_INS_SHRMB, |
1945 | | #ifndef CAPSTONE_DIET |
1946 | | { 0 }, |
1947 | | { 0 }, |
1948 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1949 | | 0, |
1950 | | 0 |
1951 | | #endif |
1952 | | }, |
1953 | | { TMS320C64x_SHRU2_s1_rir, |
1954 | | TMS320C64X_INS_SHRU2, |
1955 | | #ifndef CAPSTONE_DIET |
1956 | | { 0 }, |
1957 | | { 0 }, |
1958 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1959 | | 0, |
1960 | | 0 |
1961 | | #endif |
1962 | | }, |
1963 | | { TMS320C64x_SHRU2_s4_rrr, |
1964 | | TMS320C64X_INS_SHRU2, |
1965 | | #ifndef CAPSTONE_DIET |
1966 | | { 0 }, |
1967 | | { 0 }, |
1968 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1969 | | 0, |
1970 | | 0 |
1971 | | #endif |
1972 | | }, |
1973 | | { TMS320C64x_SHRU_s1_pip, |
1974 | | TMS320C64X_INS_SHRU, |
1975 | | #ifndef CAPSTONE_DIET |
1976 | | { 0 }, |
1977 | | { 0 }, |
1978 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1979 | | 0, |
1980 | | 0 |
1981 | | #endif |
1982 | | }, |
1983 | | { TMS320C64x_SHRU_s1_prp, |
1984 | | TMS320C64X_INS_SHRU, |
1985 | | #ifndef CAPSTONE_DIET |
1986 | | { 0 }, |
1987 | | { 0 }, |
1988 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1989 | | 0, |
1990 | | 0 |
1991 | | #endif |
1992 | | }, |
1993 | | { TMS320C64x_SHRU_s1_rir, |
1994 | | TMS320C64X_INS_SHRU, |
1995 | | #ifndef CAPSTONE_DIET |
1996 | | { 0 }, |
1997 | | { 0 }, |
1998 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
1999 | | 0, |
2000 | | 0 |
2001 | | #endif |
2002 | | }, |
2003 | | { TMS320C64x_SHRU_s1_rrr, |
2004 | | TMS320C64X_INS_SHRU, |
2005 | | #ifndef CAPSTONE_DIET |
2006 | | { 0 }, |
2007 | | { 0 }, |
2008 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2009 | | 0, |
2010 | | 0 |
2011 | | #endif |
2012 | | }, |
2013 | | { TMS320C64x_SHR_s1_pip, |
2014 | | TMS320C64X_INS_SHR, |
2015 | | #ifndef CAPSTONE_DIET |
2016 | | { 0 }, |
2017 | | { 0 }, |
2018 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2019 | | 0, |
2020 | | 0 |
2021 | | #endif |
2022 | | }, |
2023 | | { TMS320C64x_SHR_s1_prp, |
2024 | | TMS320C64X_INS_SHR, |
2025 | | #ifndef CAPSTONE_DIET |
2026 | | { 0 }, |
2027 | | { 0 }, |
2028 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2029 | | 0, |
2030 | | 0 |
2031 | | #endif |
2032 | | }, |
2033 | | { TMS320C64x_SHR_s1_rir, |
2034 | | TMS320C64X_INS_SHR, |
2035 | | #ifndef CAPSTONE_DIET |
2036 | | { 0 }, |
2037 | | { 0 }, |
2038 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2039 | | 0, |
2040 | | 0 |
2041 | | #endif |
2042 | | }, |
2043 | | { TMS320C64x_SHR_s1_rrr, |
2044 | | TMS320C64X_INS_SHR, |
2045 | | #ifndef CAPSTONE_DIET |
2046 | | { 0 }, |
2047 | | { 0 }, |
2048 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2049 | | 0, |
2050 | | 0 |
2051 | | #endif |
2052 | | }, |
2053 | | { TMS320C64x_SMPY2_m1_rrp, |
2054 | | TMS320C64X_INS_SMPY2, |
2055 | | #ifndef CAPSTONE_DIET |
2056 | | { 0 }, |
2057 | | { 0 }, |
2058 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2059 | | 0, |
2060 | | 0 |
2061 | | #endif |
2062 | | }, |
2063 | | { TMS320C64x_SMPYHL_m4_rrr, |
2064 | | TMS320C64X_INS_SMPYHL, |
2065 | | #ifndef CAPSTONE_DIET |
2066 | | { 0 }, |
2067 | | { 0 }, |
2068 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2069 | | 0, |
2070 | | 0 |
2071 | | #endif |
2072 | | }, |
2073 | | { TMS320C64x_SMPYH_m4_rrr, |
2074 | | TMS320C64X_INS_SMPYH, |
2075 | | #ifndef CAPSTONE_DIET |
2076 | | { 0 }, |
2077 | | { 0 }, |
2078 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2079 | | 0, |
2080 | | 0 |
2081 | | #endif |
2082 | | }, |
2083 | | { TMS320C64x_SMPYLH_m4_rrr, |
2084 | | TMS320C64X_INS_SMPYLH, |
2085 | | #ifndef CAPSTONE_DIET |
2086 | | { 0 }, |
2087 | | { 0 }, |
2088 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2089 | | 0, |
2090 | | 0 |
2091 | | #endif |
2092 | | }, |
2093 | | { TMS320C64x_SMPY_m4_rrr, |
2094 | | TMS320C64X_INS_SMPY, |
2095 | | #ifndef CAPSTONE_DIET |
2096 | | { 0 }, |
2097 | | { 0 }, |
2098 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2099 | | 0, |
2100 | | 0 |
2101 | | #endif |
2102 | | }, |
2103 | | { TMS320C64x_SPACK2_s4_rrr, |
2104 | | TMS320C64X_INS_SPACK2, |
2105 | | #ifndef CAPSTONE_DIET |
2106 | | { 0 }, |
2107 | | { 0 }, |
2108 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2109 | | 0, |
2110 | | 0 |
2111 | | #endif |
2112 | | }, |
2113 | | { TMS320C64x_SPACKU4_s4_rrr, |
2114 | | TMS320C64X_INS_SPACKU4, |
2115 | | #ifndef CAPSTONE_DIET |
2116 | | { 0 }, |
2117 | | { 0 }, |
2118 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2119 | | 0, |
2120 | | 0 |
2121 | | #endif |
2122 | | }, |
2123 | | { TMS320C64x_SSHL_s1_rir, |
2124 | | TMS320C64X_INS_SSHL, |
2125 | | #ifndef CAPSTONE_DIET |
2126 | | { 0 }, |
2127 | | { 0 }, |
2128 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2129 | | 0, |
2130 | | 0 |
2131 | | #endif |
2132 | | }, |
2133 | | { TMS320C64x_SSHL_s1_rrr, |
2134 | | TMS320C64X_INS_SSHL, |
2135 | | #ifndef CAPSTONE_DIET |
2136 | | { 0 }, |
2137 | | { 0 }, |
2138 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2139 | | 0, |
2140 | | 0 |
2141 | | #endif |
2142 | | }, |
2143 | | { TMS320C64x_SSHVL_m1_rrr, |
2144 | | TMS320C64X_INS_SSHVL, |
2145 | | #ifndef CAPSTONE_DIET |
2146 | | { 0 }, |
2147 | | { 0 }, |
2148 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2149 | | 0, |
2150 | | 0 |
2151 | | #endif |
2152 | | }, |
2153 | | { TMS320C64x_SSHVR_m1_rrr, |
2154 | | TMS320C64X_INS_SSHVR, |
2155 | | #ifndef CAPSTONE_DIET |
2156 | | { 0 }, |
2157 | | { 0 }, |
2158 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2159 | | 0, |
2160 | | 0 |
2161 | | #endif |
2162 | | }, |
2163 | | { TMS320C64x_SSUB_l1_ipp, |
2164 | | TMS320C64X_INS_SSUB, |
2165 | | #ifndef CAPSTONE_DIET |
2166 | | { 0 }, |
2167 | | { 0 }, |
2168 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2169 | | 0, |
2170 | | 0 |
2171 | | #endif |
2172 | | }, |
2173 | | { TMS320C64x_SSUB_l1_irr, |
2174 | | TMS320C64X_INS_SSUB, |
2175 | | #ifndef CAPSTONE_DIET |
2176 | | { 0 }, |
2177 | | { 0 }, |
2178 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2179 | | 0, |
2180 | | 0 |
2181 | | #endif |
2182 | | }, |
2183 | | { TMS320C64x_SSUB_l1_rrr_x1, |
2184 | | TMS320C64X_INS_SSUB, |
2185 | | #ifndef CAPSTONE_DIET |
2186 | | { 0 }, |
2187 | | { 0 }, |
2188 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2189 | | 0, |
2190 | | 0 |
2191 | | #endif |
2192 | | }, |
2193 | | { TMS320C64x_SSUB_l1_rrr_x2, |
2194 | | TMS320C64X_INS_SSUB, |
2195 | | #ifndef CAPSTONE_DIET |
2196 | | { 0 }, |
2197 | | { 0 }, |
2198 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2199 | | 0, |
2200 | | 0 |
2201 | | #endif |
2202 | | }, |
2203 | | { TMS320C64x_STB_d5_rm, |
2204 | | TMS320C64X_INS_STB, |
2205 | | #ifndef CAPSTONE_DIET |
2206 | | { 0 }, |
2207 | | { 0 }, |
2208 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2209 | | 0, |
2210 | | 0 |
2211 | | #endif |
2212 | | }, |
2213 | | { TMS320C64x_STB_d6_rm, |
2214 | | TMS320C64X_INS_STB, |
2215 | | #ifndef CAPSTONE_DIET |
2216 | | { 0 }, |
2217 | | { 0 }, |
2218 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2219 | | 0, |
2220 | | 0 |
2221 | | #endif |
2222 | | }, |
2223 | | { TMS320C64x_STDW_d7_pm, |
2224 | | TMS320C64X_INS_STDW, |
2225 | | #ifndef CAPSTONE_DIET |
2226 | | { 0 }, |
2227 | | { 0 }, |
2228 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2229 | | 0, |
2230 | | 0 |
2231 | | #endif |
2232 | | }, |
2233 | | { TMS320C64x_STH_d5_rm, |
2234 | | TMS320C64X_INS_STH, |
2235 | | #ifndef CAPSTONE_DIET |
2236 | | { 0 }, |
2237 | | { 0 }, |
2238 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2239 | | 0, |
2240 | | 0 |
2241 | | #endif |
2242 | | }, |
2243 | | { TMS320C64x_STH_d6_rm, |
2244 | | TMS320C64X_INS_STH, |
2245 | | #ifndef CAPSTONE_DIET |
2246 | | { 0 }, |
2247 | | { 0 }, |
2248 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2249 | | 0, |
2250 | | 0 |
2251 | | #endif |
2252 | | }, |
2253 | | { TMS320C64x_STNDW_d8_pm, |
2254 | | TMS320C64X_INS_STNDW, |
2255 | | #ifndef CAPSTONE_DIET |
2256 | | { 0 }, |
2257 | | { 0 }, |
2258 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2259 | | 0, |
2260 | | 0 |
2261 | | #endif |
2262 | | }, |
2263 | | { TMS320C64x_STNW_d5_rm, |
2264 | | TMS320C64X_INS_STNW, |
2265 | | #ifndef CAPSTONE_DIET |
2266 | | { 0 }, |
2267 | | { 0 }, |
2268 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2269 | | 0, |
2270 | | 0 |
2271 | | #endif |
2272 | | }, |
2273 | | { TMS320C64x_STW_d5_rm, |
2274 | | TMS320C64X_INS_STW, |
2275 | | #ifndef CAPSTONE_DIET |
2276 | | { 0 }, |
2277 | | { 0 }, |
2278 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2279 | | 0, |
2280 | | 0 |
2281 | | #endif |
2282 | | }, |
2283 | | { TMS320C64x_STW_d6_rm, |
2284 | | TMS320C64X_INS_STW, |
2285 | | #ifndef CAPSTONE_DIET |
2286 | | { 0 }, |
2287 | | { 0 }, |
2288 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2289 | | 0, |
2290 | | 0 |
2291 | | #endif |
2292 | | }, |
2293 | | { TMS320C64x_SUB2_d2_rrr, |
2294 | | TMS320C64X_INS_SUB2, |
2295 | | #ifndef CAPSTONE_DIET |
2296 | | { 0 }, |
2297 | | { 0 }, |
2298 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2299 | | 0, |
2300 | | 0 |
2301 | | #endif |
2302 | | }, |
2303 | | { TMS320C64x_SUB2_l1_rrr_x2, |
2304 | | TMS320C64X_INS_SUB2, |
2305 | | #ifndef CAPSTONE_DIET |
2306 | | { 0 }, |
2307 | | { 0 }, |
2308 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2309 | | 0, |
2310 | | 0 |
2311 | | #endif |
2312 | | }, |
2313 | | { TMS320C64x_SUB2_s1_rrr, |
2314 | | TMS320C64X_INS_SUB2, |
2315 | | #ifndef CAPSTONE_DIET |
2316 | | { 0 }, |
2317 | | { 0 }, |
2318 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2319 | | 0, |
2320 | | 0 |
2321 | | #endif |
2322 | | }, |
2323 | | { TMS320C64x_SUB4_l1_rrr_x2, |
2324 | | TMS320C64X_INS_SUB4, |
2325 | | #ifndef CAPSTONE_DIET |
2326 | | { 0 }, |
2327 | | { 0 }, |
2328 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2329 | | 0, |
2330 | | 0 |
2331 | | #endif |
2332 | | }, |
2333 | | { TMS320C64x_SUBABS4_l1_rrr_x2, |
2334 | | TMS320C64X_INS_SUBABS4, |
2335 | | #ifndef CAPSTONE_DIET |
2336 | | { 0 }, |
2337 | | { 0 }, |
2338 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2339 | | 0, |
2340 | | 0 |
2341 | | #endif |
2342 | | }, |
2343 | | { TMS320C64x_SUBAB_d1_rir, |
2344 | | TMS320C64X_INS_SUBAB, |
2345 | | #ifndef CAPSTONE_DIET |
2346 | | { 0 }, |
2347 | | { 0 }, |
2348 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2349 | | 0, |
2350 | | 0 |
2351 | | #endif |
2352 | | }, |
2353 | | { TMS320C64x_SUBAB_d1_rrr, |
2354 | | TMS320C64X_INS_SUBAB, |
2355 | | #ifndef CAPSTONE_DIET |
2356 | | { 0 }, |
2357 | | { 0 }, |
2358 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2359 | | 0, |
2360 | | 0 |
2361 | | #endif |
2362 | | }, |
2363 | | { TMS320C64x_SUBAH_d1_rir, |
2364 | | TMS320C64X_INS_SUBAH, |
2365 | | #ifndef CAPSTONE_DIET |
2366 | | { 0 }, |
2367 | | { 0 }, |
2368 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2369 | | 0, |
2370 | | 0 |
2371 | | #endif |
2372 | | }, |
2373 | | { TMS320C64x_SUBAH_d1_rrr, |
2374 | | TMS320C64X_INS_SUBAH, |
2375 | | #ifndef CAPSTONE_DIET |
2376 | | { 0 }, |
2377 | | { 0 }, |
2378 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2379 | | 0, |
2380 | | 0 |
2381 | | #endif |
2382 | | }, |
2383 | | { TMS320C64x_SUBAW_d1_rir, |
2384 | | TMS320C64X_INS_SUBAW, |
2385 | | #ifndef CAPSTONE_DIET |
2386 | | { 0 }, |
2387 | | { 0 }, |
2388 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2389 | | 0, |
2390 | | 0 |
2391 | | #endif |
2392 | | }, |
2393 | | { TMS320C64x_SUBAW_d1_rrr, |
2394 | | TMS320C64X_INS_SUBAW, |
2395 | | #ifndef CAPSTONE_DIET |
2396 | | { 0 }, |
2397 | | { 0 }, |
2398 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2399 | | 0, |
2400 | | 0 |
2401 | | #endif |
2402 | | }, |
2403 | | { TMS320C64x_SUBC_l1_rrr_x2, |
2404 | | TMS320C64X_INS_SUBC, |
2405 | | #ifndef CAPSTONE_DIET |
2406 | | { 0 }, |
2407 | | { 0 }, |
2408 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2409 | | 0, |
2410 | | 0 |
2411 | | #endif |
2412 | | }, |
2413 | | { TMS320C64x_SUBU_l1_rrp_x1, |
2414 | | TMS320C64X_INS_SUBU, |
2415 | | #ifndef CAPSTONE_DIET |
2416 | | { 0 }, |
2417 | | { 0 }, |
2418 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2419 | | 0, |
2420 | | 0 |
2421 | | #endif |
2422 | | }, |
2423 | | { TMS320C64x_SUBU_l1_rrp_x2, |
2424 | | TMS320C64X_INS_SUBU, |
2425 | | #ifndef CAPSTONE_DIET |
2426 | | { 0 }, |
2427 | | { 0 }, |
2428 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2429 | | 0, |
2430 | | 0 |
2431 | | #endif |
2432 | | }, |
2433 | | { TMS320C64x_SUB_d1_rir, |
2434 | | TMS320C64X_INS_SUB, |
2435 | | #ifndef CAPSTONE_DIET |
2436 | | { 0 }, |
2437 | | { 0 }, |
2438 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2439 | | 0, |
2440 | | 0 |
2441 | | #endif |
2442 | | }, |
2443 | | { TMS320C64x_SUB_d1_rrr, |
2444 | | TMS320C64X_INS_SUB, |
2445 | | #ifndef CAPSTONE_DIET |
2446 | | { 0 }, |
2447 | | { 0 }, |
2448 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2449 | | 0, |
2450 | | 0 |
2451 | | #endif |
2452 | | }, |
2453 | | { TMS320C64x_SUB_d2_rrr, |
2454 | | TMS320C64X_INS_SUB, |
2455 | | #ifndef CAPSTONE_DIET |
2456 | | { 0 }, |
2457 | | { 0 }, |
2458 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2459 | | 0, |
2460 | | 0 |
2461 | | #endif |
2462 | | }, |
2463 | | { TMS320C64x_SUB_l1_ipp, |
2464 | | TMS320C64X_INS_SUB, |
2465 | | #ifndef CAPSTONE_DIET |
2466 | | { 0 }, |
2467 | | { 0 }, |
2468 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2469 | | 0, |
2470 | | 0 |
2471 | | #endif |
2472 | | }, |
2473 | | { TMS320C64x_SUB_l1_irr, |
2474 | | TMS320C64X_INS_SUB, |
2475 | | #ifndef CAPSTONE_DIET |
2476 | | { 0 }, |
2477 | | { 0 }, |
2478 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2479 | | 0, |
2480 | | 0 |
2481 | | #endif |
2482 | | }, |
2483 | | { TMS320C64x_SUB_l1_rrp_x1, |
2484 | | TMS320C64X_INS_SUB, |
2485 | | #ifndef CAPSTONE_DIET |
2486 | | { 0 }, |
2487 | | { 0 }, |
2488 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2489 | | 0, |
2490 | | 0 |
2491 | | #endif |
2492 | | }, |
2493 | | { TMS320C64x_SUB_l1_rrp_x2, |
2494 | | TMS320C64X_INS_SUB, |
2495 | | #ifndef CAPSTONE_DIET |
2496 | | { 0 }, |
2497 | | { 0 }, |
2498 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2499 | | 0, |
2500 | | 0 |
2501 | | #endif |
2502 | | }, |
2503 | | { TMS320C64x_SUB_l1_rrr_x1, |
2504 | | TMS320C64X_INS_SUB, |
2505 | | #ifndef CAPSTONE_DIET |
2506 | | { 0 }, |
2507 | | { 0 }, |
2508 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2509 | | 0, |
2510 | | 0 |
2511 | | #endif |
2512 | | }, |
2513 | | { TMS320C64x_SUB_l1_rrr_x2, |
2514 | | TMS320C64X_INS_SUB, |
2515 | | #ifndef CAPSTONE_DIET |
2516 | | { 0 }, |
2517 | | { 0 }, |
2518 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2519 | | 0, |
2520 | | 0 |
2521 | | #endif |
2522 | | }, |
2523 | | { TMS320C64x_SUB_s1_irr, |
2524 | | TMS320C64X_INS_SUB, |
2525 | | #ifndef CAPSTONE_DIET |
2526 | | { 0 }, |
2527 | | { 0 }, |
2528 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2529 | | 0, |
2530 | | 0 |
2531 | | #endif |
2532 | | }, |
2533 | | { TMS320C64x_SUB_s1_rrr, |
2534 | | TMS320C64X_INS_SUB, |
2535 | | #ifndef CAPSTONE_DIET |
2536 | | { 0 }, |
2537 | | { 0 }, |
2538 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2539 | | 0, |
2540 | | 0 |
2541 | | #endif |
2542 | | }, |
2543 | | { TMS320C64x_SUB_s4_rrr, |
2544 | | TMS320C64X_INS_SUB, |
2545 | | #ifndef CAPSTONE_DIET |
2546 | | { 0 }, |
2547 | | { 0 }, |
2548 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2549 | | 0, |
2550 | | 0 |
2551 | | #endif |
2552 | | }, |
2553 | | { TMS320C64x_SWAP4_l2_rr, |
2554 | | TMS320C64X_INS_SWAP4, |
2555 | | #ifndef CAPSTONE_DIET |
2556 | | { 0 }, |
2557 | | { 0 }, |
2558 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2559 | | 0, |
2560 | | 0 |
2561 | | #endif |
2562 | | }, |
2563 | | { TMS320C64x_UNPKHU4_l2_rr, |
2564 | | TMS320C64X_INS_UNPKHU4, |
2565 | | #ifndef CAPSTONE_DIET |
2566 | | { 0 }, |
2567 | | { 0 }, |
2568 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2569 | | 0, |
2570 | | 0 |
2571 | | #endif |
2572 | | }, |
2573 | | { TMS320C64x_UNPKHU4_s14_rr, |
2574 | | TMS320C64X_INS_UNPKHU4, |
2575 | | #ifndef CAPSTONE_DIET |
2576 | | { 0 }, |
2577 | | { 0 }, |
2578 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2579 | | 0, |
2580 | | 0 |
2581 | | #endif |
2582 | | }, |
2583 | | { TMS320C64x_UNPKLU4_l2_rr, |
2584 | | TMS320C64X_INS_UNPKLU4, |
2585 | | #ifndef CAPSTONE_DIET |
2586 | | { 0 }, |
2587 | | { 0 }, |
2588 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2589 | | 0, |
2590 | | 0 |
2591 | | #endif |
2592 | | }, |
2593 | | { TMS320C64x_UNPKLU4_s14_rr, |
2594 | | TMS320C64X_INS_UNPKLU4, |
2595 | | #ifndef CAPSTONE_DIET |
2596 | | { 0 }, |
2597 | | { 0 }, |
2598 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2599 | | 0, |
2600 | | 0 |
2601 | | #endif |
2602 | | }, |
2603 | | { TMS320C64x_XOR_d2_rir, |
2604 | | TMS320C64X_INS_XOR, |
2605 | | #ifndef CAPSTONE_DIET |
2606 | | { 0 }, |
2607 | | { 0 }, |
2608 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2609 | | 0, |
2610 | | 0 |
2611 | | #endif |
2612 | | }, |
2613 | | { TMS320C64x_XOR_d2_rrr, |
2614 | | TMS320C64X_INS_XOR, |
2615 | | #ifndef CAPSTONE_DIET |
2616 | | { 0 }, |
2617 | | { 0 }, |
2618 | | { TMS320C64X_GRP_FUNIT_D, 0 }, |
2619 | | 0, |
2620 | | 0 |
2621 | | #endif |
2622 | | }, |
2623 | | { TMS320C64x_XOR_l1_irr, |
2624 | | TMS320C64X_INS_XOR, |
2625 | | #ifndef CAPSTONE_DIET |
2626 | | { 0 }, |
2627 | | { 0 }, |
2628 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2629 | | 0, |
2630 | | 0 |
2631 | | #endif |
2632 | | }, |
2633 | | { TMS320C64x_XOR_l1_rrr_x2, |
2634 | | TMS320C64X_INS_XOR, |
2635 | | #ifndef CAPSTONE_DIET |
2636 | | { 0 }, |
2637 | | { 0 }, |
2638 | | { TMS320C64X_GRP_FUNIT_L, 0 }, |
2639 | | 0, |
2640 | | 0 |
2641 | | #endif |
2642 | | }, |
2643 | | { TMS320C64x_XOR_s1_irr, |
2644 | | TMS320C64X_INS_XOR, |
2645 | | #ifndef CAPSTONE_DIET |
2646 | | { 0 }, |
2647 | | { 0 }, |
2648 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2649 | | 0, |
2650 | | 0 |
2651 | | #endif |
2652 | | }, |
2653 | | { TMS320C64x_XOR_s1_rrr, |
2654 | | TMS320C64X_INS_XOR, |
2655 | | #ifndef CAPSTONE_DIET |
2656 | | { 0 }, |
2657 | | { 0 }, |
2658 | | { TMS320C64X_GRP_FUNIT_S, 0 }, |
2659 | | 0, |
2660 | | 0 |
2661 | | #endif |
2662 | | }, |
2663 | | { TMS320C64x_XPND2_m2_rr, |
2664 | | TMS320C64X_INS_XPND2, |
2665 | | #ifndef CAPSTONE_DIET |
2666 | | { 0 }, |
2667 | | { 0 }, |
2668 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2669 | | 0, |
2670 | | 0 |
2671 | | #endif |
2672 | | }, |
2673 | | { TMS320C64x_XPND4_m2_rr, |
2674 | | TMS320C64X_INS_XPND4, |
2675 | | #ifndef CAPSTONE_DIET |
2676 | | { 0 }, |
2677 | | { 0 }, |
2678 | | { TMS320C64X_GRP_FUNIT_M, 0 }, |
2679 | | 0, |
2680 | | 0 |
2681 | | #endif |
2682 | | }, |
2683 | | }; |
2684 | | |
2685 | | void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
2686 | 68.3k | { |
2687 | 68.3k | unsigned short i; |
2688 | | |
2689 | 68.3k | i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); |
2690 | 68.3k | if (i != 0) { |
2691 | 68.3k | insn->id = insns[i].mapid; |
2692 | | |
2693 | 68.3k | if (h->detail_opt) { |
2694 | 68.3k | #ifndef CAPSTONE_DIET |
2695 | 68.3k | memcpy(insn->detail->regs_read, insns[i].regs_use, |
2696 | 68.3k | sizeof(insns[i].regs_use)); |
2697 | 68.3k | insn->detail->regs_read_count = |
2698 | 68.3k | (uint8_t)count_positive(insns[i].regs_use); |
2699 | | |
2700 | 68.3k | memcpy(insn->detail->regs_write, insns[i].regs_mod, |
2701 | 68.3k | sizeof(insns[i].regs_mod)); |
2702 | 68.3k | insn->detail->regs_write_count = |
2703 | 68.3k | (uint8_t)count_positive(insns[i].regs_mod); |
2704 | | |
2705 | 68.3k | memcpy(insn->detail->groups, insns[i].groups, |
2706 | 68.3k | sizeof(insns[i].groups)); |
2707 | 68.3k | insn->detail->groups_count = |
2708 | 68.3k | (uint8_t)count_positive8(insns[i].groups); |
2709 | | |
2710 | 68.3k | if (insns[i].branch || insns[i].indirect_branch) { |
2711 | 6.91k | insn->detail |
2712 | 6.91k | ->groups[insn->detail->groups_count] = |
2713 | 6.91k | TMS320C64X_GRP_JUMP; |
2714 | 6.91k | insn->detail->groups_count++; |
2715 | 6.91k | } |
2716 | 68.3k | #endif |
2717 | 68.3k | } |
2718 | 68.3k | } |
2719 | 68.3k | } |
2720 | | |
2721 | | #ifndef CAPSTONE_DIET |
2722 | | //grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}' |
2723 | | static const name_map insn_name_maps[] = { |
2724 | | { TMS320C64X_INS_INVALID, NULL }, |
2725 | | { TMS320C64X_INS_ABS, "abs" }, |
2726 | | { TMS320C64X_INS_ABS2, "abs2" }, |
2727 | | { TMS320C64X_INS_ADD, "add" }, |
2728 | | { TMS320C64X_INS_ADD2, "add2" }, |
2729 | | { TMS320C64X_INS_ADD4, "add4" }, |
2730 | | { TMS320C64X_INS_ADDAB, "addab" }, |
2731 | | { TMS320C64X_INS_ADDAD, "addad" }, |
2732 | | { TMS320C64X_INS_ADDAH, "addah" }, |
2733 | | { TMS320C64X_INS_ADDAW, "addaw" }, |
2734 | | { TMS320C64X_INS_ADDK, "addk" }, |
2735 | | { TMS320C64X_INS_ADDKPC, "addkpc" }, |
2736 | | { TMS320C64X_INS_ADDU, "addu" }, |
2737 | | { TMS320C64X_INS_AND, "and" }, |
2738 | | { TMS320C64X_INS_ANDN, "andn" }, |
2739 | | { TMS320C64X_INS_AVG2, "avg2" }, |
2740 | | { TMS320C64X_INS_AVGU4, "avgu4" }, |
2741 | | { TMS320C64X_INS_B, "b" }, |
2742 | | { TMS320C64X_INS_BDEC, "bdec" }, |
2743 | | { TMS320C64X_INS_BITC4, "bitc4" }, |
2744 | | { TMS320C64X_INS_BNOP, "bnop" }, |
2745 | | { TMS320C64X_INS_BPOS, "bpos" }, |
2746 | | { TMS320C64X_INS_CLR, "clr" }, |
2747 | | { TMS320C64X_INS_CMPEQ, "cmpeq" }, |
2748 | | { TMS320C64X_INS_CMPEQ2, "cmpeq2" }, |
2749 | | { TMS320C64X_INS_CMPEQ4, "cmpeq4" }, |
2750 | | { TMS320C64X_INS_CMPGT, "cmpgt" }, |
2751 | | { TMS320C64X_INS_CMPGT2, "cmpgt2" }, |
2752 | | { TMS320C64X_INS_CMPGTU4, "cmpgtu4" }, |
2753 | | { TMS320C64X_INS_CMPLT, "cmplt" }, |
2754 | | { TMS320C64X_INS_CMPLTU, "cmpltu" }, |
2755 | | { TMS320C64X_INS_DEAL, "deal" }, |
2756 | | { TMS320C64X_INS_DOTP2, "dotp2" }, |
2757 | | { TMS320C64X_INS_DOTPN2, "dotpn2" }, |
2758 | | { TMS320C64X_INS_DOTPNRSU2, "dotpnrsu2" }, |
2759 | | { TMS320C64X_INS_DOTPRSU2, "dotprsu2" }, |
2760 | | { TMS320C64X_INS_DOTPSU4, "dotpsu4" }, |
2761 | | { TMS320C64X_INS_DOTPU4, "dotpu4" }, |
2762 | | { TMS320C64X_INS_EXT, "ext" }, |
2763 | | { TMS320C64X_INS_EXTU, "extu" }, |
2764 | | { TMS320C64X_INS_GMPGTU, "gmpgtu" }, |
2765 | | { TMS320C64X_INS_GMPY4, "gmpy4" }, |
2766 | | { TMS320C64X_INS_LDB, "ldb" }, |
2767 | | { TMS320C64X_INS_LDBU, "ldbu" }, |
2768 | | { TMS320C64X_INS_LDDW, "lddw" }, |
2769 | | { TMS320C64X_INS_LDH, "ldh" }, |
2770 | | { TMS320C64X_INS_LDHU, "ldhu" }, |
2771 | | { TMS320C64X_INS_LDNDW, "ldndw" }, |
2772 | | { TMS320C64X_INS_LDNW, "ldnw" }, |
2773 | | { TMS320C64X_INS_LDW, "ldw" }, |
2774 | | { TMS320C64X_INS_LMBD, "lmbd" }, |
2775 | | { TMS320C64X_INS_MAX2, "max2" }, |
2776 | | { TMS320C64X_INS_MAXU4, "maxu4" }, |
2777 | | { TMS320C64X_INS_MIN2, "min2" }, |
2778 | | { TMS320C64X_INS_MINU4, "minu4" }, |
2779 | | { TMS320C64X_INS_MPY, "mpy" }, |
2780 | | { TMS320C64X_INS_MPY2, "mpy2" }, |
2781 | | { TMS320C64X_INS_MPYH, "mpyh" }, |
2782 | | { TMS320C64X_INS_MPYHI, "mpyhi" }, |
2783 | | { TMS320C64X_INS_MPYHIR, "mpyhir" }, |
2784 | | { TMS320C64X_INS_MPYHL, "mpyhl" }, |
2785 | | { TMS320C64X_INS_MPYHLU, "mpyhlu" }, |
2786 | | { TMS320C64X_INS_MPYHSLU, "mpyhslu" }, |
2787 | | { TMS320C64X_INS_MPYHSU, "mpyhsu" }, |
2788 | | { TMS320C64X_INS_MPYHU, "mpyhu" }, |
2789 | | { TMS320C64X_INS_MPYHULS, "mpyhuls" }, |
2790 | | { TMS320C64X_INS_MPYHUS, "mpyhus" }, |
2791 | | { TMS320C64X_INS_MPYLH, "mpylh" }, |
2792 | | { TMS320C64X_INS_MPYLHU, "mpylhu" }, |
2793 | | { TMS320C64X_INS_MPYLI, "mpyli" }, |
2794 | | { TMS320C64X_INS_MPYLIR, "mpylir" }, |
2795 | | { TMS320C64X_INS_MPYLSHU, "mpylshu" }, |
2796 | | { TMS320C64X_INS_MPYLUHS, "mpyluhs" }, |
2797 | | { TMS320C64X_INS_MPYSU, "mpysu" }, |
2798 | | { TMS320C64X_INS_MPYSU4, "mpysu4" }, |
2799 | | { TMS320C64X_INS_MPYU, "mpyu" }, |
2800 | | { TMS320C64X_INS_MPYU4, "mpyu4" }, |
2801 | | { TMS320C64X_INS_MPYUS, "mpyus" }, |
2802 | | { TMS320C64X_INS_MVC, "mvc" }, |
2803 | | { TMS320C64X_INS_MVD, "mvd" }, |
2804 | | { TMS320C64X_INS_MVK, "mvk" }, |
2805 | | { TMS320C64X_INS_MVKL, "mvkl" }, |
2806 | | { TMS320C64X_INS_MVKLH, "mvklh" }, |
2807 | | { TMS320C64X_INS_NOP, "nop" }, |
2808 | | { TMS320C64X_INS_NORM, "norm" }, |
2809 | | { TMS320C64X_INS_OR, "or" }, |
2810 | | { TMS320C64X_INS_PACK2, "pack2" }, |
2811 | | { TMS320C64X_INS_PACKH2, "packh2" }, |
2812 | | { TMS320C64X_INS_PACKH4, "packh4" }, |
2813 | | { TMS320C64X_INS_PACKHL2, "packhl2" }, |
2814 | | { TMS320C64X_INS_PACKL4, "packl4" }, |
2815 | | { TMS320C64X_INS_PACKLH2, "packlh2" }, |
2816 | | { TMS320C64X_INS_ROTL, "rotl" }, |
2817 | | { TMS320C64X_INS_SADD, "sadd" }, |
2818 | | { TMS320C64X_INS_SADD2, "sadd2" }, |
2819 | | { TMS320C64X_INS_SADDU4, "saddu4" }, |
2820 | | { TMS320C64X_INS_SADDUS2, "saddus2" }, |
2821 | | { TMS320C64X_INS_SAT, "sat" }, |
2822 | | { TMS320C64X_INS_SET, "set" }, |
2823 | | { TMS320C64X_INS_SHFL, "shfl" }, |
2824 | | { TMS320C64X_INS_SHL, "shl" }, |
2825 | | { TMS320C64X_INS_SHLMB, "shlmb" }, |
2826 | | { TMS320C64X_INS_SHR, "shr" }, |
2827 | | { TMS320C64X_INS_SHR2, "shr2" }, |
2828 | | { TMS320C64X_INS_SHRMB, "shrmb" }, |
2829 | | { TMS320C64X_INS_SHRU, "shru" }, |
2830 | | { TMS320C64X_INS_SHRU2, "shru2" }, |
2831 | | { TMS320C64X_INS_SMPY, "smpy" }, |
2832 | | { TMS320C64X_INS_SMPY2, "smpy2" }, |
2833 | | { TMS320C64X_INS_SMPYH, "smpyh" }, |
2834 | | { TMS320C64X_INS_SMPYHL, "smpyhl" }, |
2835 | | { TMS320C64X_INS_SMPYLH, "smpylh" }, |
2836 | | { TMS320C64X_INS_SPACK2, "spack2" }, |
2837 | | { TMS320C64X_INS_SPACKU4, "spacku4" }, |
2838 | | { TMS320C64X_INS_SSHL, "sshl" }, |
2839 | | { TMS320C64X_INS_SSHVL, "sshvl" }, |
2840 | | { TMS320C64X_INS_SSHVR, "sshvr" }, |
2841 | | { TMS320C64X_INS_SSUB, "ssub" }, |
2842 | | { TMS320C64X_INS_STB, "stb" }, |
2843 | | { TMS320C64X_INS_STDW, "stdw" }, |
2844 | | { TMS320C64X_INS_STH, "sth" }, |
2845 | | { TMS320C64X_INS_STNDW, "stndw" }, |
2846 | | { TMS320C64X_INS_STNW, "stnw" }, |
2847 | | { TMS320C64X_INS_STW, "stw" }, |
2848 | | { TMS320C64X_INS_SUB, "sub" }, |
2849 | | { TMS320C64X_INS_SUB2, "sub2" }, |
2850 | | { TMS320C64X_INS_SUB4, "sub4" }, |
2851 | | { TMS320C64X_INS_SUBAB, "subab" }, |
2852 | | { TMS320C64X_INS_SUBABS4, "subabs4" }, |
2853 | | { TMS320C64X_INS_SUBAH, "subah" }, |
2854 | | { TMS320C64X_INS_SUBAW, "subaw" }, |
2855 | | { TMS320C64X_INS_SUBC, "subc" }, |
2856 | | { TMS320C64X_INS_SUBU, "subu" }, |
2857 | | { TMS320C64X_INS_SWAP4, "swap4" }, |
2858 | | { TMS320C64X_INS_UNPKHU4, "unpkhu4" }, |
2859 | | { TMS320C64X_INS_UNPKLU4, "unpklu4" }, |
2860 | | { TMS320C64X_INS_XOR, "xor" }, |
2861 | | { TMS320C64X_INS_XPND2, "xpnd2" }, |
2862 | | { TMS320C64X_INS_XPND4, "xpnd4" }, |
2863 | | { TMS320C64X_INS_IDLE, "idle" }, |
2864 | | { TMS320C64X_INS_MV, "mv" }, |
2865 | | { TMS320C64X_INS_NEG, "neg" }, |
2866 | | { TMS320C64X_INS_NOT, "not" }, |
2867 | | { TMS320C64X_INS_SWAP2, "swap2" }, |
2868 | | { TMS320C64X_INS_ZERO, "zero" }, |
2869 | | }; |
2870 | | |
2871 | | #endif |
2872 | | |
2873 | | const char *TMS320C64x_insn_name(csh handle, unsigned int id) |
2874 | 68.3k | { |
2875 | 68.3k | #ifndef CAPSTONE_DIET |
2876 | 68.3k | if (id >= TMS320C64X_INS_ENDING) |
2877 | 0 | return NULL; |
2878 | | |
2879 | 68.3k | return insn_name_maps[id].name; |
2880 | | #else |
2881 | | return NULL; |
2882 | | #endif |
2883 | 68.3k | } |
2884 | | |
2885 | | #ifndef CAPSTONE_DIET |
2886 | | static const name_map group_name_maps[] = { |
2887 | | { TMS320C64X_GRP_INVALID, NULL }, |
2888 | | { TMS320C64X_GRP_FUNIT_D, "funit_d" }, |
2889 | | { TMS320C64X_GRP_FUNIT_L, "funit_l" }, |
2890 | | { TMS320C64X_GRP_FUNIT_M, "funit_m" }, |
2891 | | { TMS320C64X_GRP_FUNIT_S, "funit_s" }, |
2892 | | { TMS320C64X_GRP_FUNIT_NO, "funit_no" }, |
2893 | | { TMS320C64X_GRP_JUMP, "jump" }, |
2894 | | }; |
2895 | | #endif |
2896 | | |
2897 | | const char *TMS320C64x_group_name(csh handle, unsigned int id) |
2898 | 75.2k | { |
2899 | 75.2k | #ifndef CAPSTONE_DIET |
2900 | 75.2k | unsigned int i; |
2901 | | |
2902 | 75.2k | if (id >= ARR_SIZE(group_name_maps)) |
2903 | 68.3k | return NULL; |
2904 | | |
2905 | 48.4k | for (i = 0; i < ARR_SIZE(group_name_maps); i++) { |
2906 | 48.4k | if (group_name_maps[i].id == id) |
2907 | 6.91k | return group_name_maps[i].name; |
2908 | 48.4k | } |
2909 | | |
2910 | 0 | return group_name_maps[id].name; |
2911 | | #else |
2912 | | return NULL; |
2913 | | #endif |
2914 | 6.91k | } |
2915 | | |
2916 | | tms320c64x_reg TMS320C64x_map_register(unsigned int r) |
2917 | 0 | { |
2918 | 0 | static unsigned int map[] = { |
2919 | 0 | 0, |
2920 | 0 | }; |
2921 | |
|
2922 | 0 | if (r < ARR_SIZE(map)) |
2923 | 0 | return map[r]; |
2924 | | |
2925 | 0 | return 0; |
2926 | 0 | } |
2927 | | |
2928 | | #endif |