Coverage Report

Created: 2025-08-28 06:43

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
44.5k
{
20
44.5k
  static const uint32_t OpInfo[] = {
21
44.5k
    0U, // PHI
22
44.5k
    0U, // INLINEASM
23
44.5k
    0U, // CFI_INSTRUCTION
24
44.5k
    0U, // EH_LABEL
25
44.5k
    0U, // GC_LABEL
26
44.5k
    0U, // KILL
27
44.5k
    0U, // EXTRACT_SUBREG
28
44.5k
    0U, // INSERT_SUBREG
29
44.5k
    0U, // IMPLICIT_DEF
30
44.5k
    0U, // SUBREG_TO_REG
31
44.5k
    0U, // COPY_TO_REGCLASS
32
44.5k
    2452U,  // DBG_VALUE
33
44.5k
    0U, // REG_SEQUENCE
34
44.5k
    0U, // COPY
35
44.5k
    2445U,  // BUNDLE
36
44.5k
    2462U,  // LIFETIME_START
37
44.5k
    2432U,  // LIFETIME_END
38
44.5k
    0U, // STACKMAP
39
44.5k
    0U, // PATCHPOINT
40
44.5k
    0U, // LOAD_STACK_GUARD
41
44.5k
    0U, // STATEPOINT
42
44.5k
    0U, // FRAME_ALLOC
43
44.5k
    4688U,  // ADDCCri
44
44.5k
    4688U,  // ADDCCrr
45
44.5k
    5925U,  // ADDCri
46
44.5k
    5925U,  // ADDCrr
47
44.5k
    4772U,  // ADDEri
48
44.5k
    4772U,  // ADDErr
49
44.5k
    4786U,  // ADDXC
50
44.5k
    4678U,  // ADDXCCC
51
44.5k
    4808U,  // ADDXri
52
44.5k
    4808U,  // ADDXrr
53
44.5k
    4808U,  // ADDri
54
44.5k
    4808U,  // ADDrr
55
44.5k
    74166U, // ADJCALLSTACKDOWN
56
44.5k
    74185U, // ADJCALLSTACKUP
57
44.5k
    5497U,  // ALIGNADDR
58
44.5k
    5127U,  // ALIGNADDRL
59
44.5k
    4695U,  // ANDCCri
60
44.5k
    4695U,  // ANDCCrr
61
44.5k
    4718U,  // ANDNCCri
62
44.5k
    4718U,  // ANDNCCrr
63
44.5k
    5182U,  // ANDNri
64
44.5k
    5182U,  // ANDNrr
65
44.5k
    5182U,  // ANDXNrr
66
44.5k
    4876U,  // ANDXri
67
44.5k
    4876U,  // ANDXrr
68
44.5k
    4876U,  // ANDri
69
44.5k
    4876U,  // ANDrr
70
44.5k
    4502U,  // ARRAY16
71
44.5k
    4255U,  // ARRAY32
72
44.5k
    4526U,  // ARRAY8
73
44.5k
    0U, // ATOMIC_LOAD_ADD_32
74
44.5k
    0U, // ATOMIC_LOAD_ADD_64
75
44.5k
    0U, // ATOMIC_LOAD_AND_32
76
44.5k
    0U, // ATOMIC_LOAD_AND_64
77
44.5k
    0U, // ATOMIC_LOAD_MAX_32
78
44.5k
    0U, // ATOMIC_LOAD_MAX_64
79
44.5k
    0U, // ATOMIC_LOAD_MIN_32
80
44.5k
    0U, // ATOMIC_LOAD_MIN_64
81
44.5k
    0U, // ATOMIC_LOAD_NAND_32
82
44.5k
    0U, // ATOMIC_LOAD_NAND_64
83
44.5k
    0U, // ATOMIC_LOAD_OR_32
84
44.5k
    0U, // ATOMIC_LOAD_OR_64
85
44.5k
    0U, // ATOMIC_LOAD_SUB_32
86
44.5k
    0U, // ATOMIC_LOAD_SUB_64
87
44.5k
    0U, // ATOMIC_LOAD_UMAX_32
88
44.5k
    0U, // ATOMIC_LOAD_UMAX_64
89
44.5k
    0U, // ATOMIC_LOAD_UMIN_32
90
44.5k
    0U, // ATOMIC_LOAD_UMIN_64
91
44.5k
    0U, // ATOMIC_LOAD_XOR_32
92
44.5k
    0U, // ATOMIC_LOAD_XOR_64
93
44.5k
    0U, // ATOMIC_SWAP_64
94
44.5k
    74271U, // BA
95
44.5k
    1194492U, // BCOND
96
44.5k
    1260028U, // BCONDA
97
44.5k
    17659U, // BINDri
98
44.5k
    17659U, // BINDrr
99
44.5k
    5065U,  // BMASK
100
44.5k
    145915U,  // BPFCC
101
44.5k
    211451U,  // BPFCCA
102
44.5k
    276987U,  // BPFCCANT
103
44.5k
    342523U,  // BPFCCNT
104
44.5k
    2106465U, // BPGEZapn
105
44.5k
    2105838U, // BPGEZapt
106
44.5k
    2106532U, // BPGEZnapn
107
44.5k
    2107288U, // BPGEZnapt
108
44.5k
    2106489U, // BPGZapn
109
44.5k
    2105856U, // BPGZapt
110
44.5k
    2106552U, // BPGZnapn
111
44.5k
    2107384U, // BPGZnapt
112
44.5k
    1456636U, // BPICC
113
44.5k
    473596U,  // BPICCA
114
44.5k
    539132U,  // BPICCANT
115
44.5k
    604668U,  // BPICCNT
116
44.5k
    2106477U, // BPLEZapn
117
44.5k
    2105847U, // BPLEZapt
118
44.5k
    2106542U, // BPLEZnapn
119
44.5k
    2107337U, // BPLEZnapt
120
44.5k
    2106500U, // BPLZapn
121
44.5k
    2105864U, // BPLZapt
122
44.5k
    2106561U, // BPLZnapn
123
44.5k
    2107428U, // BPLZnapt
124
44.5k
    2106511U, // BPNZapn
125
44.5k
    2105872U, // BPNZapt
126
44.5k
    2106570U, // BPNZnapn
127
44.5k
    2107472U, // BPNZnapt
128
44.5k
    1718780U, // BPXCC
129
44.5k
    735740U,  // BPXCCA
130
44.5k
    801276U,  // BPXCCANT
131
44.5k
    866812U,  // BPXCCNT
132
44.5k
    2106522U, // BPZapn
133
44.5k
    2105880U, // BPZapt
134
44.5k
    2106579U, // BPZnapn
135
44.5k
    2107505U, // BPZnapt
136
44.5k
    4983U,  // BSHUFFLE
137
44.5k
    74742U, // CALL
138
44.5k
    17398U, // CALLri
139
44.5k
    17398U, // CALLrr
140
44.5k
    924148U,  // CASXrr
141
44.5k
    924129U,  // CASrr
142
44.5k
    74001U, // CMASK16
143
44.5k
    73833U, // CMASK32
144
44.5k
    74150U, // CMASK8
145
44.5k
    2106607U, // CMPri
146
44.5k
    2106607U, // CMPrr
147
44.5k
    4332U,  // EDGE16
148
44.5k
    5081U,  // EDGE16L
149
44.5k
    5198U,  // EDGE16LN
150
44.5k
    5165U,  // EDGE16N
151
44.5k
    4164U,  // EDGE32
152
44.5k
    5072U,  // EDGE32L
153
44.5k
    5188U,  // EDGE32LN
154
44.5k
    5156U,  // EDGE32N
155
44.5k
    4511U,  // EDGE8
156
44.5k
    5090U,  // EDGE8L
157
44.5k
    5208U,  // EDGE8LN
158
44.5k
    5174U,  // EDGE8N
159
44.5k
    1053516U, // FABSD
160
44.5k
    1054031U, // FABSQ
161
44.5k
    1054376U, // FABSS
162
44.5k
    4813U,  // FADDD
163
44.5k
    5383U,  // FADDQ
164
44.5k
    5645U,  // FADDS
165
44.5k
    4648U,  // FALIGNADATA
166
44.5k
    4875U,  // FAND
167
44.5k
    4112U,  // FANDNOT1
168
44.5k
    5544U,  // FANDNOT1S
169
44.5k
    4271U,  // FANDNOT2
170
44.5k
    5591U,  // FANDNOT2S
171
44.5k
    5677U,  // FANDS
172
44.5k
    1194491U, // FBCOND
173
44.5k
    1260027U, // FBCONDA
174
44.5k
    4394U,  // FCHKSM16
175
44.5k
    2106173U, // FCMPD
176
44.5k
    4413U,  // FCMPEQ16
177
44.5k
    4226U,  // FCMPEQ32
178
44.5k
    4432U,  // FCMPGT16
179
44.5k
    4245U,  // FCMPGT32
180
44.5k
    4340U,  // FCMPLE16
181
44.5k
    4172U,  // FCMPLE32
182
44.5k
    4350U,  // FCMPNE16
183
44.5k
    4182U,  // FCMPNE32
184
44.5k
    2106696U, // FCMPQ
185
44.5k
    2107005U, // FCMPS
186
44.5k
    4960U,  // FDIVD
187
44.5k
    5475U,  // FDIVQ
188
44.5k
    5815U,  // FDIVS
189
44.5k
    5405U,  // FDMULQ
190
44.5k
    1053620U, // FDTOI
191
44.5k
    1053996U, // FDTOQ
192
44.5k
    1054305U, // FDTOS
193
44.5k
    1054536U, // FDTOX
194
44.5k
    1053464U, // FEXPAND
195
44.5k
    4820U,  // FHADDD
196
44.5k
    5652U,  // FHADDS
197
44.5k
    4800U,  // FHSUBD
198
44.5k
    5637U,  // FHSUBS
199
44.5k
    1053473U, // FITOD
200
44.5k
    1054003U, // FITOQ
201
44.5k
    1054312U, // FITOS
202
44.5k
    6300484U, // FLCMPD
203
44.5k
    6301316U, // FLCMPS
204
44.5k
    2606U,  // FLUSHW
205
44.5k
    4404U,  // FMEAN16
206
44.5k
    1053543U, // FMOVD
207
44.5k
    1006078U, // FMOVD_FCC
208
44.5k
    23484926U,  // FMOVD_ICC
209
44.5k
    23747070U,  // FMOVD_XCC
210
44.5k
    1054058U, // FMOVQ
211
44.5k
    1006102U, // FMOVQ_FCC
212
44.5k
    23484950U,  // FMOVQ_ICC
213
44.5k
    23747094U,  // FMOVQ_XCC
214
44.5k
    6018U,  // FMOVRGEZD
215
44.5k
    6029U,  // FMOVRGEZQ
216
44.5k
    6056U,  // FMOVRGEZS
217
44.5k
    6116U,  // FMOVRGZD
218
44.5k
    6126U,  // FMOVRGZQ
219
44.5k
    6150U,  // FMOVRGZS
220
44.5k
    6067U,  // FMOVRLEZD
221
44.5k
    6078U,  // FMOVRLEZQ
222
44.5k
    6105U,  // FMOVRLEZS
223
44.5k
    6160U,  // FMOVRLZD
224
44.5k
    6170U,  // FMOVRLZQ
225
44.5k
    6194U,  // FMOVRLZS
226
44.5k
    6204U,  // FMOVRNZD
227
44.5k
    6214U,  // FMOVRNZQ
228
44.5k
    6238U,  // FMOVRNZS
229
44.5k
    6009U,  // FMOVRZD
230
44.5k
    6248U,  // FMOVRZQ
231
44.5k
    6269U,  // FMOVRZS
232
44.5k
    1054398U, // FMOVS
233
44.5k
    1006114U, // FMOVS_FCC
234
44.5k
    23484962U,  // FMOVS_ICC
235
44.5k
    23747106U,  // FMOVS_XCC
236
44.5k
    4490U,  // FMUL8SUX16
237
44.5k
    4465U,  // FMUL8ULX16
238
44.5k
    4442U,  // FMUL8X16
239
44.5k
    5098U,  // FMUL8X16AL
240
44.5k
    5849U,  // FMUL8X16AU
241
44.5k
    4860U,  // FMULD
242
44.5k
    4477U,  // FMULD8SUX16
243
44.5k
    4452U,  // FMULD8ULX16
244
44.5k
    5413U,  // FMULQ
245
44.5k
    5714U,  // FMULS
246
44.5k
    4837U,  // FNADDD
247
44.5k
    5669U,  // FNADDS
248
44.5k
    4881U,  // FNAND
249
44.5k
    5684U,  // FNANDS
250
44.5k
    1053429U, // FNEGD
251
44.5k
    1053974U, // FNEGQ
252
44.5k
    1054283U, // FNEGS
253
44.5k
    4828U,  // FNHADDD
254
44.5k
    5660U,  // FNHADDS
255
44.5k
    4828U,  // FNMULD
256
44.5k
    5660U,  // FNMULS
257
44.5k
    5513U,  // FNOR
258
44.5k
    5778U,  // FNORS
259
44.5k
    1052698U, // FNOT1
260
44.5k
    1054131U, // FNOT1S
261
44.5k
    1052857U, // FNOT2
262
44.5k
    1054178U, // FNOT2S
263
44.5k
    5660U,  // FNSMULD
264
44.5k
    74625U, // FONE
265
44.5k
    75324U, // FONES
266
44.5k
    5508U,  // FOR
267
44.5k
    4129U,  // FORNOT1
268
44.5k
    5563U,  // FORNOT1S
269
44.5k
    4288U,  // FORNOT2
270
44.5k
    5610U,  // FORNOT2S
271
44.5k
    5772U,  // FORS
272
44.5k
    1052936U, // FPACK16
273
44.5k
    4192U,  // FPACK32
274
44.5k
    1054507U, // FPACKFIX
275
44.5k
    4323U,  // FPADD16
276
44.5k
    5620U,  // FPADD16S
277
44.5k
    4155U,  // FPADD32
278
44.5k
    5573U,  // FPADD32S
279
44.5k
    4297U,  // FPADD64
280
44.5k
    4974U,  // FPMERGE
281
44.5k
    4314U,  // FPSUB16
282
44.5k
    4580U,  // FPSUB16S
283
44.5k
    4146U,  // FPSUB32
284
44.5k
    4570U,  // FPSUB32S
285
44.5k
    1053480U, // FQTOD
286
44.5k
    1053627U, // FQTOI
287
44.5k
    1054319U, // FQTOS
288
44.5k
    1054552U, // FQTOX
289
44.5k
    4423U,  // FSLAS16
290
44.5k
    4236U,  // FSLAS32
291
44.5k
    4378U,  // FSLL16
292
44.5k
    4210U,  // FSLL32
293
44.5k
    4867U,  // FSMULD
294
44.5k
    1053523U, // FSQRTD
295
44.5k
    1054038U, // FSQRTQ
296
44.5k
    1054383U, // FSQRTS
297
44.5k
    4306U,  // FSRA16
298
44.5k
    4138U,  // FSRA32
299
44.5k
    1052681U, // FSRC1
300
44.5k
    1054112U, // FSRC1S
301
44.5k
    1052840U, // FSRC2
302
44.5k
    1054159U, // FSRC2S
303
44.5k
    4386U,  // FSRL16
304
44.5k
    4218U,  // FSRL32
305
44.5k
    1053487U, // FSTOD
306
44.5k
    1053634U, // FSTOI
307
44.5k
    1054010U, // FSTOQ
308
44.5k
    1054559U, // FSTOX
309
44.5k
    4793U,  // FSUBD
310
44.5k
    5376U,  // FSUBQ
311
44.5k
    5630U,  // FSUBS
312
44.5k
    5519U,  // FXNOR
313
44.5k
    5785U,  // FXNORS
314
44.5k
    5526U,  // FXOR
315
44.5k
    5793U,  // FXORS
316
44.5k
    1053494U, // FXTOD
317
44.5k
    1054017U, // FXTOQ
318
44.5k
    1054326U, // FXTOS
319
44.5k
    74984U, // FZERO
320
44.5k
    75353U, // FZEROS
321
44.5k
    24584U, // GETPCX
322
44.5k
    1078273U, // JMPLri
323
44.5k
    1078273U, // JMPLrr
324
44.5k
    1997243U, // LDDFri
325
44.5k
    1997243U, // LDDFrr
326
44.5k
    1997249U, // LDFri
327
44.5k
    1997249U, // LDFrr
328
44.5k
    1997275U, // LDQFri
329
44.5k
    1997275U, // LDQFrr
330
44.5k
    1997229U, // LDSBri
331
44.5k
    1997229U, // LDSBrr
332
44.5k
    1997254U, // LDSHri
333
44.5k
    1997254U, // LDSHrr
334
44.5k
    1997287U, // LDSWri
335
44.5k
    1997287U, // LDSWrr
336
44.5k
    1997236U, // LDUBri
337
44.5k
    1997236U, // LDUBrr
338
44.5k
    1997261U, // LDUHri
339
44.5k
    1997261U, // LDUHrr
340
44.5k
    1997294U, // LDXri
341
44.5k
    1997294U, // LDXrr
342
44.5k
    1997249U, // LDri
343
44.5k
    1997249U, // LDrr
344
44.5k
    33480U, // LEAX_ADDri
345
44.5k
    33480U, // LEA_ADDri
346
44.5k
    1054405U, // LZCNT
347
44.5k
    75121U, // MEMBARi
348
44.5k
    1054543U, // MOVDTOX
349
44.5k
    1006122U, // MOVFCCri
350
44.5k
    1006122U, // MOVFCCrr
351
44.5k
    23484970U,  // MOVICCri
352
44.5k
    23484970U,  // MOVICCrr
353
44.5k
    6047U,  // MOVRGEZri
354
44.5k
    6047U,  // MOVRGEZrr
355
44.5k
    6142U,  // MOVRGZri
356
44.5k
    6142U,  // MOVRGZrr
357
44.5k
    6096U,  // MOVRLEZri
358
44.5k
    6096U,  // MOVRLEZrr
359
44.5k
    6186U,  // MOVRLZri
360
44.5k
    6186U,  // MOVRLZrr
361
44.5k
    6230U,  // MOVRNZri
362
44.5k
    6230U,  // MOVRNZrr
363
44.5k
    6262U,  // MOVRRZri
364
44.5k
    6262U,  // MOVRRZrr
365
44.5k
    1054469U, // MOVSTOSW
366
44.5k
    1054479U, // MOVSTOUW
367
44.5k
    1054543U, // MOVWTOS
368
44.5k
    23747114U,  // MOVXCCri
369
44.5k
    23747114U,  // MOVXCCrr
370
44.5k
    1054543U, // MOVXTOD
371
44.5k
    5954U,  // MULXri
372
44.5k
    5954U,  // MULXrr
373
44.5k
    2578U,  // NOP
374
44.5k
    4735U,  // ORCCri
375
44.5k
    4735U,  // ORCCrr
376
44.5k
    4726U,  // ORNCCri
377
44.5k
    4726U,  // ORNCCrr
378
44.5k
    5339U,  // ORNri
379
44.5k
    5339U,  // ORNrr
380
44.5k
    5339U,  // ORXNrr
381
44.5k
    5509U,  // ORXri
382
44.5k
    5509U,  // ORXrr
383
44.5k
    5509U,  // ORri
384
44.5k
    5509U,  // ORrr
385
44.5k
    5836U,  // PDIST
386
44.5k
    5344U,  // PDISTN
387
44.5k
    1053356U, // POPCrr
388
44.5k
    73729U, // RDY
389
44.5k
    4999U,  // RESTOREri
390
44.5k
    4999U,  // RESTORErr
391
44.5k
    76132U, // RET
392
44.5k
    76141U, // RETL
393
44.5k
    18131U, // RETTri
394
44.5k
    18131U, // RETTrr
395
44.5k
    5008U,  // SAVEri
396
44.5k
    5008U,  // SAVErr
397
44.5k
    4748U,  // SDIVCCri
398
44.5k
    4748U,  // SDIVCCrr
399
44.5k
    5995U,  // SDIVXri
400
44.5k
    5995U,  // SDIVXrr
401
44.5k
    5861U,  // SDIVri
402
44.5k
    5861U,  // SDIVrr
403
44.5k
    2182U,  // SELECT_CC_DFP_FCC
404
44.5k
    2293U,  // SELECT_CC_DFP_ICC
405
44.5k
    2238U,  // SELECT_CC_FP_FCC
406
44.5k
    2349U,  // SELECT_CC_FP_ICC
407
44.5k
    2265U,  // SELECT_CC_Int_FCC
408
44.5k
    2376U,  // SELECT_CC_Int_ICC
409
44.5k
    2210U,  // SELECT_CC_QFP_FCC
410
44.5k
    2321U,  // SELECT_CC_QFP_ICC
411
44.5k
    1053595U, // SETHIXi
412
44.5k
    1053595U, // SETHIi
413
44.5k
    2569U,  // SHUTDOWN
414
44.5k
    2564U,  // SIAM
415
44.5k
    5941U,  // SLLXri
416
44.5k
    5941U,  // SLLXrr
417
44.5k
    5116U,  // SLLri
418
44.5k
    5116U,  // SLLrr
419
44.5k
    4702U,  // SMULCCri
420
44.5k
    4702U,  // SMULCCrr
421
44.5k
    5144U,  // SMULri
422
44.5k
    5144U,  // SMULrr
423
44.5k
    5913U,  // SRAXri
424
44.5k
    5913U,  // SRAXrr
425
44.5k
    4643U,  // SRAri
426
44.5k
    4643U,  // SRArr
427
44.5k
    5947U,  // SRLXri
428
44.5k
    5947U,  // SRLXrr
429
44.5k
    5139U,  // SRLri
430
44.5k
    5139U,  // SRLrr
431
44.5k
    2588U,  // STBAR
432
44.5k
    37428U, // STBri
433
44.5k
    37428U, // STBrr
434
44.5k
    37723U, // STDFri
435
44.5k
    37723U, // STDFrr
436
44.5k
    38607U, // STFri
437
44.5k
    38607U, // STFrr
438
44.5k
    37782U, // STHri
439
44.5k
    37782U, // STHrr
440
44.5k
    38238U, // STQFri
441
44.5k
    38238U, // STQFrr
442
44.5k
    38758U, // STXri
443
44.5k
    38758U, // STXrr
444
44.5k
    38607U, // STri
445
44.5k
    38607U, // STrr
446
44.5k
    4671U,  // SUBCCri
447
44.5k
    4671U,  // SUBCCrr
448
44.5k
    5919U,  // SUBCri
449
44.5k
    5919U,  // SUBCrr
450
44.5k
    4764U,  // SUBEri
451
44.5k
    4764U,  // SUBErr
452
44.5k
    4665U,  // SUBXri
453
44.5k
    4665U,  // SUBXrr
454
44.5k
    4665U,  // SUBri
455
44.5k
    4665U,  // SUBrr
456
44.5k
    1997268U, // SWAPri
457
44.5k
    1997268U, // SWAPrr
458
44.5k
    2422U,  // TA3
459
44.5k
    2427U,  // TA5
460
44.5k
    5883U,  // TADDCCTVri
461
44.5k
    5883U,  // TADDCCTVrr
462
44.5k
    4687U,  // TADDCCri
463
44.5k
    4687U,  // TADDCCrr
464
44.5k
    9873960U, // TICCri
465
44.5k
    9873960U, // TICCrr
466
44.5k
    37753544U,  // TLS_ADDXrr
467
44.5k
    37753544U,  // TLS_ADDrr
468
44.5k
    2106358U, // TLS_CALL
469
44.5k
    39746030U,  // TLS_LDXrr
470
44.5k
    39745985U,  // TLS_LDrr
471
44.5k
    5873U,  // TSUBCCTVri
472
44.5k
    5873U,  // TSUBCCTVrr
473
44.5k
    4670U,  // TSUBCCri
474
44.5k
    4670U,  // TSUBCCrr
475
44.5k
    10136104U,  // TXCCri
476
44.5k
    10136104U,  // TXCCrr
477
44.5k
    4756U,  // UDIVCCri
478
44.5k
    4756U,  // UDIVCCrr
479
44.5k
    6002U,  // UDIVXri
480
44.5k
    6002U,  // UDIVXrr
481
44.5k
    5867U,  // UDIVri
482
44.5k
    5867U,  // UDIVrr
483
44.5k
    4710U,  // UMULCCri
484
44.5k
    4710U,  // UMULCCrr
485
44.5k
    5026U,  // UMULXHI
486
44.5k
    5150U,  // UMULri
487
44.5k
    5150U,  // UMULrr
488
44.5k
    74996U, // UNIMP
489
44.5k
    6300477U, // V9FCMPD
490
44.5k
    6300397U, // V9FCMPED
491
44.5k
    6300942U, // V9FCMPEQ
492
44.5k
    6301251U, // V9FCMPES
493
44.5k
    6301000U, // V9FCMPQ
494
44.5k
    6301309U, // V9FCMPS
495
44.5k
    47614U, // V9FMOVD_FCC
496
44.5k
    47638U, // V9FMOVQ_FCC
497
44.5k
    47650U, // V9FMOVS_FCC
498
44.5k
    47658U, // V9MOVFCCri
499
44.5k
    47658U, // V9MOVFCCrr
500
44.5k
    14689692U,  // WRYri
501
44.5k
    14689692U,  // WRYrr
502
44.5k
    5953U,  // XMULX
503
44.5k
    5035U,  // XMULXHI
504
44.5k
    4733U,  // XNORCCri
505
44.5k
    4733U,  // XNORCCrr
506
44.5k
    5520U,  // XNORXrr
507
44.5k
    5520U,  // XNORri
508
44.5k
    5520U,  // XNORrr
509
44.5k
    4741U,  // XORCCri
510
44.5k
    4741U,  // XORCCrr
511
44.5k
    5527U,  // XORXri
512
44.5k
    5527U,  // XORXrr
513
44.5k
    5527U,  // XORri
514
44.5k
    5527U,  // XORrr
515
44.5k
    0U
516
44.5k
  };
517
518
44.5k
#ifndef CAPSTONE_DIET
519
44.5k
  static const char AsmStrs[] = {
520
44.5k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
44.5k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
44.5k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
44.5k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
44.5k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
44.5k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
44.5k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
44.5k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
44.5k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
44.5k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
44.5k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
44.5k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
44.5k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
44.5k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
44.5k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
44.5k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
44.5k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
44.5k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
44.5k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
44.5k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
44.5k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
44.5k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
44.5k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
44.5k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
44.5k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
44.5k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
44.5k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
44.5k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
44.5k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
44.5k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
44.5k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
44.5k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
44.5k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
44.5k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
44.5k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
44.5k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
44.5k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
44.5k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
44.5k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
44.5k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
44.5k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
44.5k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
44.5k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
44.5k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
44.5k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
44.5k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
44.5k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
44.5k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
44.5k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
44.5k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
44.5k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
44.5k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
44.5k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
44.5k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
44.5k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
44.5k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
44.5k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
44.5k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
44.5k
  /* 542 */ 'b', 'a', 32, 0,
579
44.5k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
44.5k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
44.5k
  /* 563 */ 's', 't', 'b', 32, 0,
582
44.5k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
44.5k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
44.5k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
44.5k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
44.5k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
44.5k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
44.5k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
44.5k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
44.5k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
44.5k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
44.5k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
44.5k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
44.5k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
44.5k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
44.5k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
44.5k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
44.5k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
44.5k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
44.5k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
44.5k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
44.5k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
44.5k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
44.5k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
44.5k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
44.5k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
44.5k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
44.5k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
44.5k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
44.5k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
44.5k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
44.5k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
44.5k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
44.5k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
44.5k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
44.5k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
44.5k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
44.5k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
44.5k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
44.5k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
44.5k
  /* 858 */ 's', 't', 'd', 32, 0,
622
44.5k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
44.5k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
44.5k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
44.5k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
44.5k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
44.5k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
44.5k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
44.5k
  /* 917 */ 's', 't', 'h', 32, 0,
630
44.5k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
44.5k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
44.5k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
44.5k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
44.5k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
44.5k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
44.5k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
44.5k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
44.5k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
44.5k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
44.5k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
44.5k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
44.5k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
44.5k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
44.5k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
44.5k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
44.5k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
44.5k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
44.5k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
44.5k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
44.5k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
44.5k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
44.5k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
44.5k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
44.5k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
44.5k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
44.5k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
44.5k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
44.5k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
44.5k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
44.5k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
44.5k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
44.5k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
44.5k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
44.5k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
44.5k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
44.5k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
44.5k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
44.5k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
44.5k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
44.5k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
44.5k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
44.5k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
44.5k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
44.5k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
44.5k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
44.5k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
44.5k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
44.5k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
44.5k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
44.5k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
44.5k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
44.5k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
44.5k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
44.5k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
44.5k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
44.5k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
44.5k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
44.5k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
44.5k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
44.5k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
44.5k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
44.5k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
44.5k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
44.5k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
44.5k
  /* 1435 */ 'w', 'r', 32, 0,
696
44.5k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
44.5k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
44.5k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
44.5k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
44.5k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
44.5k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
44.5k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
44.5k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
44.5k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
44.5k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
44.5k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
44.5k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
44.5k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
44.5k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
44.5k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
44.5k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
44.5k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
44.5k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
44.5k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
44.5k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
44.5k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
44.5k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
44.5k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
44.5k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
44.5k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
44.5k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
44.5k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
44.5k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
44.5k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
44.5k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
44.5k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
44.5k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
44.5k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
44.5k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
44.5k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
44.5k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
44.5k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
44.5k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
44.5k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
44.5k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
44.5k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
44.5k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
44.5k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
44.5k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
44.5k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
44.5k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
44.5k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
44.5k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
44.5k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
44.5k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
44.5k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
44.5k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
44.5k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
44.5k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
44.5k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
44.5k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
44.5k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
44.5k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
44.5k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
44.5k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
44.5k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
44.5k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
44.5k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
44.5k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
44.5k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
44.5k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
44.5k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
44.5k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
44.5k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
44.5k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
44.5k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
44.5k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
44.5k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
44.5k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
44.5k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
44.5k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
44.5k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
44.5k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
44.5k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
44.5k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
44.5k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
44.5k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
44.5k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
44.5k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
44.5k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
44.5k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
44.5k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
44.5k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
44.5k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
44.5k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
44.5k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
44.5k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
44.5k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
44.5k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
44.5k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
44.5k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
44.5k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
44.5k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
44.5k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
44.5k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
44.5k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
44.5k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
44.5k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
44.5k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
44.5k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
44.5k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
44.5k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
44.5k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
44.5k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
44.5k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
44.5k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
44.5k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
44.5k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
44.5k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
44.5k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
44.5k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
44.5k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
44.5k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
44.5k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
44.5k
  /* 2554 */ 'f', 'b', 0,
816
44.5k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
44.5k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
44.5k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
44.5k
  /* 2577 */ 'n', 'o', 'p', 0,
820
44.5k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
44.5k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
44.5k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
44.5k
  /* 2599 */ 't', 0,
824
44.5k
  /* 2601 */ 'm', 'o', 'v', 0,
825
44.5k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
44.5k
  };
827
44.5k
#endif
828
829
  // Emit the opcode for the instruction.
830
44.5k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
44.5k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
44.5k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
44.5k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
44.5k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
220
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
220
    return;
844
0
    break;
845
7.74k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
7.74k
    printOperand(MI, 1, O); 
848
7.74k
    break;
849
24.2k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
24.2k
    printOperand(MI, 0, O); 
852
24.2k
    break;
853
3.64k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.64k
    printCCOperand(MI, 1, O); 
856
3.64k
    break;
857
137
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
137
    printMemOperand(MI, 0, O, NULL); 
860
137
    return;
861
0
    break;
862
2.93k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.93k
    printCCOperand(MI, 3, O); 
865
2.93k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.42k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.42k
    printMemOperand(MI, 1, O, NULL); 
874
2.42k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.24k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.24k
    printOperand(MI, 2, O); 
885
1.24k
    SStream_concat0(O, ", ["); 
886
1.24k
    printMemOperand(MI, 0, O, NULL); 
887
1.24k
    SStream_concat0(O, "]"); 
888
1.24k
    return;
889
0
    break;
890
617
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
617
    printCCOperand(MI, 2, O); 
893
617
    break;
894
1.39k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.39k
    printCCOperand(MI, 4, O); 
897
1.39k
    SStream_concat0(O, " "); 
898
1.39k
    printOperand(MI, 1, O); 
899
1.39k
    SStream_concat0(O, ", "); 
900
1.39k
    printOperand(MI, 2, O); 
901
1.39k
    SStream_concat0(O, ", "); 
902
1.39k
    printOperand(MI, 0, O); 
903
1.39k
    return;
904
0
    break;
905
44.5k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
41.5k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
13.2k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
13.2k
    SStream_concat0(O, ", "); 
915
13.2k
    break;
916
18.8k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
18.8k
    return;
919
0
    break;
920
1.33k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.33k
    SStream_concat0(O, " "); 
923
1.33k
    break;
924
926
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
926
    SStream_concat0(O, ",a ");
927
926
  Sparc_add_hint(MI, SPARC_HINT_A);
928
926
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
2.30k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
2.30k
    SStream_concat0(O, " %icc, ");
950
2.30k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
2.30k
    break;
952
351
  case 7:
953
    // BPICCA
954
351
    SStream_concat0(O, ",a %icc, ");
955
351
  Sparc_add_hint(MI, SPARC_HINT_A);
956
351
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
351
    printOperand(MI, 0, O); 
958
351
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.00k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.00k
    SStream_concat0(O, " %xcc, ");
979
1.00k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.00k
    break;
981
350
  case 11:
982
    // BPXCCA
983
350
    SStream_concat0(O, ",a %xcc, ");
984
350
  Sparc_add_hint(MI, SPARC_HINT_A);
985
350
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
350
    printOperand(MI, 0, O); 
987
350
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.31k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.31k
    SStream_concat0(O, "], "); 
1008
2.31k
    break;
1009
927
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
927
    SStream_concat0(O, " %fcc0, ");
1012
927
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
927
    printOperand(MI, 1, O); 
1014
927
    SStream_concat0(O, ", "); 
1015
927
    printOperand(MI, 0, O); 
1016
927
    return;
1017
0
    break;
1018
41.5k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
21.1k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.78k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.78k
    printOperand(MI, 2, O); 
1028
5.78k
    SStream_concat0(O, ", "); 
1029
5.78k
    printOperand(MI, 0, O); 
1030
5.78k
    break;
1031
7.95k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
7.95k
    printOperand(MI, 0, O); 
1034
7.95k
    break;
1035
7.40k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
7.40k
    printOperand(MI, 1, O); 
1038
7.40k
    break;
1039
21.1k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
21.1k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
17.1k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
17.1k
    return;
1049
0
    break;
1050
3.11k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
3.11k
    SStream_concat0(O, ", "); 
1053
3.11k
    break;
1054
617
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
617
    SStream_concat0(O, " + ");  // qq
1057
617
    printOperand(MI, 1, O); 
1058
617
    return;
1059
0
    break;
1060
284
  case 3:
1061
    // WRYri, WRYrr
1062
284
    SStream_concat0(O, ", %y");
1063
284
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
284
    return;
1065
0
    break;
1066
21.1k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
3.11k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.10k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.10k
    printOperand(MI, 2, O); 
1076
1.10k
    return;
1077
0
    break;
1078
2.01k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
2.01k
    printOperand(MI, 0, O); 
1081
2.01k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
3.11k
  }
1089
3.11k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
64.8k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
64.8k
#ifndef CAPSTONE_DIET
1100
64.8k
  static const char AsmStrs[] = {
1101
64.8k
  /* 0 */ 'f', '1', '0', 0,
1102
64.8k
  /* 4 */ 'f', '2', '0', 0,
1103
64.8k
  /* 8 */ 'f', '3', '0', 0,
1104
64.8k
  /* 12 */ 'f', '4', '0', 0,
1105
64.8k
  /* 16 */ 'f', '5', '0', 0,
1106
64.8k
  /* 20 */ 'f', '6', '0', 0,
1107
64.8k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
64.8k
  /* 29 */ 'f', '0', 0,
1109
64.8k
  /* 32 */ 'g', '0', 0,
1110
64.8k
  /* 35 */ 'i', '0', 0,
1111
64.8k
  /* 38 */ 'l', '0', 0,
1112
64.8k
  /* 41 */ 'o', '0', 0,
1113
64.8k
  /* 44 */ 'f', '1', '1', 0,
1114
64.8k
  /* 48 */ 'f', '2', '1', 0,
1115
64.8k
  /* 52 */ 'f', '3', '1', 0,
1116
64.8k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
64.8k
  /* 61 */ 'f', '1', 0,
1118
64.8k
  /* 64 */ 'g', '1', 0,
1119
64.8k
  /* 67 */ 'i', '1', 0,
1120
64.8k
  /* 70 */ 'l', '1', 0,
1121
64.8k
  /* 73 */ 'o', '1', 0,
1122
64.8k
  /* 76 */ 'f', '1', '2', 0,
1123
64.8k
  /* 80 */ 'f', '2', '2', 0,
1124
64.8k
  /* 84 */ 'f', '3', '2', 0,
1125
64.8k
  /* 88 */ 'f', '4', '2', 0,
1126
64.8k
  /* 92 */ 'f', '5', '2', 0,
1127
64.8k
  /* 96 */ 'f', '6', '2', 0,
1128
64.8k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
64.8k
  /* 105 */ 'f', '2', 0,
1130
64.8k
  /* 108 */ 'g', '2', 0,
1131
64.8k
  /* 111 */ 'i', '2', 0,
1132
64.8k
  /* 114 */ 'l', '2', 0,
1133
64.8k
  /* 117 */ 'o', '2', 0,
1134
64.8k
  /* 120 */ 'f', '1', '3', 0,
1135
64.8k
  /* 124 */ 'f', '2', '3', 0,
1136
64.8k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
64.8k
  /* 133 */ 'f', '3', 0,
1138
64.8k
  /* 136 */ 'g', '3', 0,
1139
64.8k
  /* 139 */ 'i', '3', 0,
1140
64.8k
  /* 142 */ 'l', '3', 0,
1141
64.8k
  /* 145 */ 'o', '3', 0,
1142
64.8k
  /* 148 */ 'f', '1', '4', 0,
1143
64.8k
  /* 152 */ 'f', '2', '4', 0,
1144
64.8k
  /* 156 */ 'f', '3', '4', 0,
1145
64.8k
  /* 160 */ 'f', '4', '4', 0,
1146
64.8k
  /* 164 */ 'f', '5', '4', 0,
1147
64.8k
  /* 168 */ 'f', '4', 0,
1148
64.8k
  /* 171 */ 'g', '4', 0,
1149
64.8k
  /* 174 */ 'i', '4', 0,
1150
64.8k
  /* 177 */ 'l', '4', 0,
1151
64.8k
  /* 180 */ 'o', '4', 0,
1152
64.8k
  /* 183 */ 'f', '1', '5', 0,
1153
64.8k
  /* 187 */ 'f', '2', '5', 0,
1154
64.8k
  /* 191 */ 'f', '5', 0,
1155
64.8k
  /* 194 */ 'g', '5', 0,
1156
64.8k
  /* 197 */ 'i', '5', 0,
1157
64.8k
  /* 200 */ 'l', '5', 0,
1158
64.8k
  /* 203 */ 'o', '5', 0,
1159
64.8k
  /* 206 */ 'f', '1', '6', 0,
1160
64.8k
  /* 210 */ 'f', '2', '6', 0,
1161
64.8k
  /* 214 */ 'f', '3', '6', 0,
1162
64.8k
  /* 218 */ 'f', '4', '6', 0,
1163
64.8k
  /* 222 */ 'f', '5', '6', 0,
1164
64.8k
  /* 226 */ 'f', '6', 0,
1165
64.8k
  /* 229 */ 'g', '6', 0,
1166
64.8k
  /* 232 */ 'l', '6', 0,
1167
64.8k
  /* 235 */ 'f', '1', '7', 0,
1168
64.8k
  /* 239 */ 'f', '2', '7', 0,
1169
64.8k
  /* 243 */ 'f', '7', 0,
1170
64.8k
  /* 246 */ 'g', '7', 0,
1171
64.8k
  /* 249 */ 'i', '7', 0,
1172
64.8k
  /* 252 */ 'l', '7', 0,
1173
64.8k
  /* 255 */ 'o', '7', 0,
1174
64.8k
  /* 258 */ 'f', '1', '8', 0,
1175
64.8k
  /* 262 */ 'f', '2', '8', 0,
1176
64.8k
  /* 266 */ 'f', '3', '8', 0,
1177
64.8k
  /* 270 */ 'f', '4', '8', 0,
1178
64.8k
  /* 274 */ 'f', '5', '8', 0,
1179
64.8k
  /* 278 */ 'f', '8', 0,
1180
64.8k
  /* 281 */ 'f', '1', '9', 0,
1181
64.8k
  /* 285 */ 'f', '2', '9', 0,
1182
64.8k
  /* 289 */ 'f', '9', 0,
1183
64.8k
  /* 292 */ 'i', 'c', 'c', 0,
1184
64.8k
  /* 296 */ 'f', 'p', 0,
1185
64.8k
  /* 299 */ 's', 'p', 0,
1186
64.8k
  /* 302 */ 'y', 0,
1187
64.8k
  };
1188
1189
64.8k
  static const uint16_t RegAsmOffset[] = {
1190
64.8k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
64.8k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
64.8k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
64.8k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
64.8k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
64.8k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
64.8k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
64.8k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
64.8k
    12, 160, 270, 92, 222, 20, 
1199
64.8k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
64.8k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
64.8k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
80.6k
{
1221
402k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
80.6k
  const char *AsmString;
1223
80.6k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
80.6k
  int OpIdx, PrintMethodIdx;
1225
80.6k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
80.6k
  switch (MCInst_getOpcode(MI)) {
1227
40.2k
  default: return NULL;
1228
3.49k
  case SP_BCOND:
1229
3.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
3.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
3.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
3.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
603
      AsmString = "bn $\x01";
1241
603
      break;
1242
603
    }
1243
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
205
      AsmString = "bne $\x01";
1248
205
      break;
1249
205
    }
1250
2.68k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
213
      AsmString = "be $\x01";
1255
213
      break;
1256
213
    }
1257
2.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
147
      AsmString = "bg $\x01";
1262
147
      break;
1263
147
    }
1264
2.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
2.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
2.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
200
      AsmString = "ble $\x01";
1269
200
      break;
1270
200
    }
1271
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
66
      AsmString = "bge $\x01";
1276
66
      break;
1277
66
    }
1278
2.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
232
      AsmString = "bl $\x01";
1283
232
      break;
1284
232
    }
1285
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
228
      AsmString = "bgu $\x01";
1290
228
      break;
1291
228
    }
1292
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
223
      AsmString = "bleu $\x01";
1297
223
      break;
1298
223
    }
1299
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1300
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
39
      AsmString = "bcc $\x01";
1304
39
      break;
1305
39
    }
1306
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1307
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
78
      AsmString = "bcs $\x01";
1311
78
      break;
1312
78
    }
1313
1.25k
    if (MCInst_getNumOperands(MI) == 2 &&
1314
1.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
1.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
70
      AsmString = "bpos $\x01";
1318
70
      break;
1319
70
    }
1320
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1321
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
211
      AsmString = "bneg $\x01";
1325
211
      break;
1326
211
    }
1327
975
    if (MCInst_getNumOperands(MI) == 2 &&
1328
975
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
975
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
346
      AsmString = "bvc $\x01";
1332
346
      break;
1333
346
    }
1334
629
    if (MCInst_getNumOperands(MI) == 2 &&
1335
629
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
629
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
629
      AsmString = "bvs $\x01";
1339
629
      break;
1340
629
    }
1341
0
    return NULL;
1342
3.02k
  case SP_BCONDA:
1343
3.02k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
3.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
3.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
646
      AsmString = "ba,a $\x01";
1348
646
      break;
1349
646
    }
1350
2.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
255
      AsmString = "bn,a $\x01";
1355
255
      break;
1356
255
    }
1357
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
92
      AsmString = "bne,a $\x01";
1362
92
      break;
1363
92
    }
1364
2.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
2.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
2.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
207
      AsmString = "be,a $\x01";
1369
207
      break;
1370
207
    }
1371
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
225
      AsmString = "bg,a $\x01";
1376
225
      break;
1377
225
    }
1378
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
205
      AsmString = "ble,a $\x01";
1383
205
      break;
1384
205
    }
1385
1.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
74
      AsmString = "bge,a $\x01";
1390
74
      break;
1391
74
    }
1392
1.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
82
      AsmString = "bl,a $\x01";
1397
82
      break;
1398
82
    }
1399
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
72
      AsmString = "bgu,a $\x01";
1404
72
      break;
1405
72
    }
1406
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
208
      AsmString = "bleu,a $\x01";
1411
208
      break;
1412
208
    }
1413
960
    if (MCInst_getNumOperands(MI) == 2 &&
1414
960
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
960
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
209
      AsmString = "bcc,a $\x01";
1418
209
      break;
1419
209
    }
1420
751
    if (MCInst_getNumOperands(MI) == 2 &&
1421
751
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
751
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
273
      AsmString = "bcs,a $\x01";
1425
273
      break;
1426
273
    }
1427
478
    if (MCInst_getNumOperands(MI) == 2 &&
1428
478
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
478
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
213
      AsmString = "bpos,a $\x01";
1432
213
      break;
1433
213
    }
1434
265
    if (MCInst_getNumOperands(MI) == 2 &&
1435
265
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
265
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
79
      AsmString = "bneg,a $\x01";
1439
79
      break;
1440
79
    }
1441
186
    if (MCInst_getNumOperands(MI) == 2 &&
1442
186
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
186
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
78
      AsmString = "bvc,a $\x01";
1446
78
      break;
1447
78
    }
1448
108
    if (MCInst_getNumOperands(MI) == 2 &&
1449
108
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
108
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
108
      AsmString = "bvs,a $\x01";
1453
108
      break;
1454
108
    }
1455
0
    return NULL;
1456
3.88k
  case SP_BPFCCANT:
1457
3.88k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
3.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
3.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
3.88k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
3.88k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
209
      AsmString = "fba,a,pn $\x03, $\x01";
1464
209
      break;
1465
209
    }
1466
3.67k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.67k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.67k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
503
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
503
      break;
1474
503
    }
1475
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
538
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
538
      break;
1483
538
    }
1484
2.63k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.63k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.63k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
207
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
207
      break;
1492
207
    }
1493
2.42k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.42k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.42k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
116
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
116
      break;
1501
116
    }
1502
2.31k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.31k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.31k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
97
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
97
      break;
1510
97
    }
1511
2.21k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
2.21k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
2.21k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
85
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
85
      break;
1519
85
    }
1520
2.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
200
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
200
      break;
1528
200
    }
1529
1.93k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.93k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.93k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
221
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
221
      break;
1537
221
    }
1538
1.70k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.70k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.70k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
256
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
256
      break;
1546
256
    }
1547
1.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.45k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
254
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
254
      break;
1555
254
    }
1556
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.19k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
214
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
214
      break;
1564
214
    }
1565
985
    if (MCInst_getNumOperands(MI) == 3 &&
1566
985
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
985
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
985
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
985
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
270
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
270
      break;
1573
270
    }
1574
715
    if (MCInst_getNumOperands(MI) == 3 &&
1575
715
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
715
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
715
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
715
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
252
      AsmString = "fble,a,pn $\x03, $\x01";
1581
252
      break;
1582
252
    }
1583
463
    if (MCInst_getNumOperands(MI) == 3 &&
1584
463
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
463
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
463
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
463
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
263
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
263
      break;
1591
263
    }
1592
200
    if (MCInst_getNumOperands(MI) == 3 &&
1593
200
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
200
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
200
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
200
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
200
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
200
      break;
1600
200
    }
1601
0
    return NULL;
1602
3.57k
  case SP_BPFCCNT:
1603
3.57k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
3.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
3.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
3.57k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
3.57k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
242
      AsmString = "fba,pn $\x03, $\x01";
1610
242
      break;
1611
242
    }
1612
3.33k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
3.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
3.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
3.33k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
3.33k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
223
      AsmString = "fbn,pn $\x03, $\x01";
1619
223
      break;
1620
223
    }
1621
3.11k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
3.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
3.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
3.11k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
3.11k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
217
      AsmString = "fbu,pn $\x03, $\x01";
1628
217
      break;
1629
217
    }
1630
2.89k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.89k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.89k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
225
      AsmString = "fbg,pn $\x03, $\x01";
1637
225
      break;
1638
225
    }
1639
2.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
201
      AsmString = "fbug,pn $\x03, $\x01";
1646
201
      break;
1647
201
    }
1648
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
2.46k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
213
      AsmString = "fbl,pn $\x03, $\x01";
1655
213
      break;
1656
213
    }
1657
2.25k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
2.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
2.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
2.25k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
2.25k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
92
      AsmString = "fbul,pn $\x03, $\x01";
1664
92
      break;
1665
92
    }
1666
2.16k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
2.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
2.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
2.16k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
2.16k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
271
      AsmString = "fblg,pn $\x03, $\x01";
1673
271
      break;
1674
271
    }
1675
1.89k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.89k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.89k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
176
      AsmString = "fbne,pn $\x03, $\x01";
1682
176
      break;
1683
176
    }
1684
1.71k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.71k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.71k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
208
      AsmString = "fbe,pn $\x03, $\x01";
1691
208
      break;
1692
208
    }
1693
1.50k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
1.50k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
1.50k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
390
      AsmString = "fbue,pn $\x03, $\x01";
1700
390
      break;
1701
390
    }
1702
1.11k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
1.11k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
1.11k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
200
      AsmString = "fbge,pn $\x03, $\x01";
1709
200
      break;
1710
200
    }
1711
917
    if (MCInst_getNumOperands(MI) == 3 &&
1712
917
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
917
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
917
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
917
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
286
      AsmString = "fbuge,pn $\x03, $\x01";
1718
286
      break;
1719
286
    }
1720
631
    if (MCInst_getNumOperands(MI) == 3 &&
1721
631
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
631
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
631
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
631
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
79
      AsmString = "fble,pn $\x03, $\x01";
1727
79
      break;
1728
79
    }
1729
552
    if (MCInst_getNumOperands(MI) == 3 &&
1730
552
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
552
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
552
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
552
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
211
      AsmString = "fbule,pn $\x03, $\x01";
1736
211
      break;
1737
211
    }
1738
341
    if (MCInst_getNumOperands(MI) == 3 &&
1739
341
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
341
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
341
      AsmString = "fbo,pn $\x03, $\x01";
1745
341
      break;
1746
341
    }
1747
0
    return NULL;
1748
3.06k
  case SP_BPICCANT:
1749
3.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
348
      AsmString = "ba,a,pn %icc, $\x01";
1754
348
      break;
1755
348
    }
1756
2.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
213
      AsmString = "bn,a,pn %icc, $\x01";
1761
213
      break;
1762
213
    }
1763
2.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
2.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
2.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
178
      AsmString = "bne,a,pn %icc, $\x01";
1768
178
      break;
1769
178
    }
1770
2.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
2.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
2.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
104
      AsmString = "be,a,pn %icc, $\x01";
1775
104
      break;
1776
104
    }
1777
2.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
461
      AsmString = "bg,a,pn %icc, $\x01";
1782
461
      break;
1783
461
    }
1784
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
82
      AsmString = "ble,a,pn %icc, $\x01";
1789
82
      break;
1790
82
    }
1791
1.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
76
      AsmString = "bge,a,pn %icc, $\x01";
1796
76
      break;
1797
76
    }
1798
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
72
      AsmString = "bl,a,pn %icc, $\x01";
1803
72
      break;
1804
72
    }
1805
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
71
      AsmString = "bgu,a,pn %icc, $\x01";
1810
71
      break;
1811
71
    }
1812
1.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
394
      AsmString = "bleu,a,pn %icc, $\x01";
1817
394
      break;
1818
394
    }
1819
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1820
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
19
      AsmString = "bcc,a,pn %icc, $\x01";
1824
19
      break;
1825
19
    }
1826
1.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1827
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
264
      AsmString = "bcs,a,pn %icc, $\x01";
1831
264
      break;
1832
264
    }
1833
782
    if (MCInst_getNumOperands(MI) == 2 &&
1834
782
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
782
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
327
      AsmString = "bpos,a,pn %icc, $\x01";
1838
327
      break;
1839
327
    }
1840
455
    if (MCInst_getNumOperands(MI) == 2 &&
1841
455
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
455
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
209
      AsmString = "bneg,a,pn %icc, $\x01";
1845
209
      break;
1846
209
    }
1847
246
    if (MCInst_getNumOperands(MI) == 2 &&
1848
246
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
246
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
74
      AsmString = "bvc,a,pn %icc, $\x01";
1852
74
      break;
1853
74
    }
1854
172
    if (MCInst_getNumOperands(MI) == 2 &&
1855
172
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
172
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
172
      AsmString = "bvs,a,pn %icc, $\x01";
1859
172
      break;
1860
172
    }
1861
0
    return NULL;
1862
3.18k
  case SP_BPICCNT:
1863
3.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
3.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
3.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
126
      AsmString = "ba,pn %icc, $\x01";
1868
126
      break;
1869
126
    }
1870
3.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
3.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
3.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
389
      AsmString = "bn,pn %icc, $\x01";
1875
389
      break;
1876
389
    }
1877
2.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
335
      AsmString = "bne,pn %icc, $\x01";
1882
335
      break;
1883
335
    }
1884
2.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
700
      AsmString = "be,pn %icc, $\x01";
1889
700
      break;
1890
700
    }
1891
1.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
195
      AsmString = "bg,pn %icc, $\x01";
1896
195
      break;
1897
195
    }
1898
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
77
      AsmString = "ble,pn %icc, $\x01";
1903
77
      break;
1904
77
    }
1905
1.36k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
66
      AsmString = "bge,pn %icc, $\x01";
1910
66
      break;
1911
66
    }
1912
1.29k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
69
      AsmString = "bl,pn %icc, $\x01";
1917
69
      break;
1918
69
    }
1919
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
70
      AsmString = "bgu,pn %icc, $\x01";
1924
70
      break;
1925
70
    }
1926
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
237
      AsmString = "bleu,pn %icc, $\x01";
1931
237
      break;
1932
237
    }
1933
923
    if (MCInst_getNumOperands(MI) == 2 &&
1934
923
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
923
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
78
      AsmString = "bcc,pn %icc, $\x01";
1938
78
      break;
1939
78
    }
1940
845
    if (MCInst_getNumOperands(MI) == 2 &&
1941
845
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
845
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
236
      AsmString = "bcs,pn %icc, $\x01";
1945
236
      break;
1946
236
    }
1947
609
    if (MCInst_getNumOperands(MI) == 2 &&
1948
609
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
609
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
72
      AsmString = "bpos,pn %icc, $\x01";
1952
72
      break;
1953
72
    }
1954
537
    if (MCInst_getNumOperands(MI) == 2 &&
1955
537
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
537
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
68
      AsmString = "bneg,pn %icc, $\x01";
1959
68
      break;
1960
68
    }
1961
469
    if (MCInst_getNumOperands(MI) == 2 &&
1962
469
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
469
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
195
      AsmString = "bvc,pn %icc, $\x01";
1966
195
      break;
1967
195
    }
1968
274
    if (MCInst_getNumOperands(MI) == 2 &&
1969
274
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
274
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
274
      AsmString = "bvs,pn %icc, $\x01";
1973
274
      break;
1974
274
    }
1975
0
    return NULL;
1976
2.01k
  case SP_BPXCCANT:
1977
2.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
221
      AsmString = "ba,a,pn %xcc, $\x01";
1982
221
      break;
1983
221
    }
1984
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
68
      AsmString = "bn,a,pn %xcc, $\x01";
1989
68
      break;
1990
68
    }
1991
1.72k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
67
      AsmString = "bne,a,pn %xcc, $\x01";
1996
67
      break;
1997
67
    }
1998
1.66k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
77
      AsmString = "be,a,pn %xcc, $\x01";
2003
77
      break;
2004
77
    }
2005
1.58k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
82
      AsmString = "bg,a,pn %xcc, $\x01";
2010
82
      break;
2011
82
    }
2012
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
81
      AsmString = "ble,a,pn %xcc, $\x01";
2017
81
      break;
2018
81
    }
2019
1.42k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
71
      AsmString = "bge,a,pn %xcc, $\x01";
2024
71
      break;
2025
71
    }
2026
1.35k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
230
      AsmString = "bl,a,pn %xcc, $\x01";
2031
230
      break;
2032
230
    }
2033
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
125
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
125
      break;
2039
125
    }
2040
995
    if (MCInst_getNumOperands(MI) == 2 &&
2041
995
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
995
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
101
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
101
      break;
2046
101
    }
2047
894
    if (MCInst_getNumOperands(MI) == 2 &&
2048
894
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
894
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
67
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
67
      break;
2053
67
    }
2054
827
    if (MCInst_getNumOperands(MI) == 2 &&
2055
827
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
827
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
203
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
203
      break;
2060
203
    }
2061
624
    if (MCInst_getNumOperands(MI) == 2 &&
2062
624
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
624
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
109
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
109
      break;
2067
109
    }
2068
515
    if (MCInst_getNumOperands(MI) == 2 &&
2069
515
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
515
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
168
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
168
      break;
2074
168
    }
2075
347
    if (MCInst_getNumOperands(MI) == 2 &&
2076
347
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
347
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
196
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
196
      break;
2081
196
    }
2082
151
    if (MCInst_getNumOperands(MI) == 2 &&
2083
151
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
151
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
151
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
151
      break;
2088
151
    }
2089
0
    return NULL;
2090
2.87k
  case SP_BPXCCNT:
2091
2.87k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
219
      AsmString = "ba,pn %xcc, $\x01";
2096
219
      break;
2097
219
    }
2098
2.65k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
286
      AsmString = "bn,pn %xcc, $\x01";
2103
286
      break;
2104
286
    }
2105
2.36k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
2.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
2.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
69
      AsmString = "bne,pn %xcc, $\x01";
2110
69
      break;
2111
69
    }
2112
2.29k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
2.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
2.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
69
      AsmString = "be,pn %xcc, $\x01";
2117
69
      break;
2118
69
    }
2119
2.22k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
204
      AsmString = "bg,pn %xcc, $\x01";
2124
204
      break;
2125
204
    }
2126
2.02k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
2.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
2.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
220
      AsmString = "ble,pn %xcc, $\x01";
2131
220
      break;
2132
220
    }
2133
1.80k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.80k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.80k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
204
      AsmString = "bge,pn %xcc, $\x01";
2138
204
      break;
2139
204
    }
2140
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
73
      AsmString = "bl,pn %xcc, $\x01";
2145
73
      break;
2146
73
    }
2147
1.52k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
272
      AsmString = "bgu,pn %xcc, $\x01";
2152
272
      break;
2153
272
    }
2154
1.25k
    if (MCInst_getNumOperands(MI) == 2 &&
2155
1.25k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
1.25k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
167
      AsmString = "bleu,pn %xcc, $\x01";
2159
167
      break;
2160
167
    }
2161
1.08k
    if (MCInst_getNumOperands(MI) == 2 &&
2162
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
71
      AsmString = "bcc,pn %xcc, $\x01";
2166
71
      break;
2167
71
    }
2168
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
2169
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
67
      AsmString = "bcs,pn %xcc, $\x01";
2173
67
      break;
2174
67
    }
2175
951
    if (MCInst_getNumOperands(MI) == 2 &&
2176
951
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
951
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
69
      AsmString = "bpos,pn %xcc, $\x01";
2180
69
      break;
2181
69
    }
2182
882
    if (MCInst_getNumOperands(MI) == 2 &&
2183
882
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
882
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
218
      AsmString = "bneg,pn %xcc, $\x01";
2187
218
      break;
2188
218
    }
2189
664
    if (MCInst_getNumOperands(MI) == 2 &&
2190
664
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
664
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
358
      AsmString = "bvc,pn %xcc, $\x01";
2194
358
      break;
2195
358
    }
2196
306
    if (MCInst_getNumOperands(MI) == 2 &&
2197
306
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
306
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
306
      AsmString = "bvs,pn %xcc, $\x01";
2201
306
      break;
2202
306
    }
2203
0
    return NULL;
2204
213
  case SP_FMOVD_ICC:
2205
213
    if (MCInst_getNumOperands(MI) == 3 &&
2206
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
213
    if (MCInst_getNumOperands(MI) == 3 &&
2217
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
213
    if (MCInst_getNumOperands(MI) == 3 &&
2228
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
213
    if (MCInst_getNumOperands(MI) == 3 &&
2239
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
213
    if (MCInst_getNumOperands(MI) == 3 &&
2250
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
213
    if (MCInst_getNumOperands(MI) == 3 &&
2261
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
213
    if (MCInst_getNumOperands(MI) == 3 &&
2272
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
213
    if (MCInst_getNumOperands(MI) == 3 &&
2283
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
213
    if (MCInst_getNumOperands(MI) == 3 &&
2294
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
213
    if (MCInst_getNumOperands(MI) == 3 &&
2305
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
213
    if (MCInst_getNumOperands(MI) == 3 &&
2316
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
213
    if (MCInst_getNumOperands(MI) == 3 &&
2327
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
213
    if (MCInst_getNumOperands(MI) == 3 &&
2338
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
213
    if (MCInst_getNumOperands(MI) == 3 &&
2349
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
213
    if (MCInst_getNumOperands(MI) == 3 &&
2360
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
213
    if (MCInst_getNumOperands(MI) == 3 &&
2371
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
213
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
213
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
213
    return NULL;
2382
67
  case SP_FMOVD_XCC:
2383
67
    if (MCInst_getNumOperands(MI) == 3 &&
2384
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
67
    if (MCInst_getNumOperands(MI) == 3 &&
2395
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
67
    if (MCInst_getNumOperands(MI) == 3 &&
2406
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
67
    if (MCInst_getNumOperands(MI) == 3 &&
2417
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
67
    if (MCInst_getNumOperands(MI) == 3 &&
2428
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
67
    if (MCInst_getNumOperands(MI) == 3 &&
2439
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
67
    if (MCInst_getNumOperands(MI) == 3 &&
2450
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
67
    if (MCInst_getNumOperands(MI) == 3 &&
2461
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
67
    if (MCInst_getNumOperands(MI) == 3 &&
2472
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
67
    if (MCInst_getNumOperands(MI) == 3 &&
2483
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
67
    if (MCInst_getNumOperands(MI) == 3 &&
2494
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
67
    if (MCInst_getNumOperands(MI) == 3 &&
2505
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
67
    if (MCInst_getNumOperands(MI) == 3 &&
2516
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
67
    if (MCInst_getNumOperands(MI) == 3 &&
2527
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
67
    if (MCInst_getNumOperands(MI) == 3 &&
2538
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
67
    if (MCInst_getNumOperands(MI) == 3 &&
2549
67
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
67
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
67
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
67
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
67
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
67
    return NULL;
2560
555
  case SP_FMOVQ_ICC:
2561
555
    if (MCInst_getNumOperands(MI) == 3 &&
2562
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
555
    if (MCInst_getNumOperands(MI) == 3 &&
2573
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
555
    if (MCInst_getNumOperands(MI) == 3 &&
2584
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
555
    if (MCInst_getNumOperands(MI) == 3 &&
2595
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
555
    if (MCInst_getNumOperands(MI) == 3 &&
2606
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
555
    if (MCInst_getNumOperands(MI) == 3 &&
2617
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
555
    if (MCInst_getNumOperands(MI) == 3 &&
2628
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
555
    if (MCInst_getNumOperands(MI) == 3 &&
2639
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
555
    if (MCInst_getNumOperands(MI) == 3 &&
2650
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
555
    if (MCInst_getNumOperands(MI) == 3 &&
2661
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
555
    if (MCInst_getNumOperands(MI) == 3 &&
2672
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
555
    if (MCInst_getNumOperands(MI) == 3 &&
2683
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
555
    if (MCInst_getNumOperands(MI) == 3 &&
2694
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
555
    if (MCInst_getNumOperands(MI) == 3 &&
2705
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
555
    if (MCInst_getNumOperands(MI) == 3 &&
2716
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
555
    if (MCInst_getNumOperands(MI) == 3 &&
2727
555
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
555
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
555
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
555
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
555
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
555
    return NULL;
2738
38
  case SP_FMOVQ_XCC:
2739
38
    if (MCInst_getNumOperands(MI) == 3 &&
2740
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
38
    if (MCInst_getNumOperands(MI) == 3 &&
2751
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
38
    if (MCInst_getNumOperands(MI) == 3 &&
2762
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
38
    if (MCInst_getNumOperands(MI) == 3 &&
2773
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
38
    if (MCInst_getNumOperands(MI) == 3 &&
2784
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
38
    if (MCInst_getNumOperands(MI) == 3 &&
2795
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
38
    if (MCInst_getNumOperands(MI) == 3 &&
2806
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
38
    if (MCInst_getNumOperands(MI) == 3 &&
2817
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
38
    if (MCInst_getNumOperands(MI) == 3 &&
2828
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
38
    if (MCInst_getNumOperands(MI) == 3 &&
2839
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
38
    if (MCInst_getNumOperands(MI) == 3 &&
2850
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
38
    if (MCInst_getNumOperands(MI) == 3 &&
2861
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
38
    if (MCInst_getNumOperands(MI) == 3 &&
2872
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
38
    if (MCInst_getNumOperands(MI) == 3 &&
2883
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
38
    if (MCInst_getNumOperands(MI) == 3 &&
2894
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
38
    if (MCInst_getNumOperands(MI) == 3 &&
2905
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
38
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
38
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
38
    return NULL;
2916
88
  case SP_FMOVS_ICC:
2917
88
    if (MCInst_getNumOperands(MI) == 3 &&
2918
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
88
    if (MCInst_getNumOperands(MI) == 3 &&
2929
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
88
    if (MCInst_getNumOperands(MI) == 3 &&
2940
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
88
    if (MCInst_getNumOperands(MI) == 3 &&
2951
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
88
    if (MCInst_getNumOperands(MI) == 3 &&
2962
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
88
    if (MCInst_getNumOperands(MI) == 3 &&
2973
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
88
    if (MCInst_getNumOperands(MI) == 3 &&
2984
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
88
    if (MCInst_getNumOperands(MI) == 3 &&
2995
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
88
    if (MCInst_getNumOperands(MI) == 3 &&
3006
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
88
    if (MCInst_getNumOperands(MI) == 3 &&
3017
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
88
    if (MCInst_getNumOperands(MI) == 3 &&
3028
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
88
    if (MCInst_getNumOperands(MI) == 3 &&
3039
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
88
    if (MCInst_getNumOperands(MI) == 3 &&
3050
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
88
    if (MCInst_getNumOperands(MI) == 3 &&
3061
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
88
    if (MCInst_getNumOperands(MI) == 3 &&
3072
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
88
    if (MCInst_getNumOperands(MI) == 3 &&
3083
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
88
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
88
    return NULL;
3094
34
  case SP_FMOVS_XCC:
3095
34
    if (MCInst_getNumOperands(MI) == 3 &&
3096
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
34
    if (MCInst_getNumOperands(MI) == 3 &&
3107
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
34
    if (MCInst_getNumOperands(MI) == 3 &&
3118
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
34
    if (MCInst_getNumOperands(MI) == 3 &&
3129
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
34
    if (MCInst_getNumOperands(MI) == 3 &&
3140
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
34
    if (MCInst_getNumOperands(MI) == 3 &&
3151
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
34
    if (MCInst_getNumOperands(MI) == 3 &&
3162
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
34
    if (MCInst_getNumOperands(MI) == 3 &&
3173
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
34
    if (MCInst_getNumOperands(MI) == 3 &&
3184
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
34
    if (MCInst_getNumOperands(MI) == 3 &&
3195
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
34
    if (MCInst_getNumOperands(MI) == 3 &&
3206
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
34
    if (MCInst_getNumOperands(MI) == 3 &&
3217
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
34
    if (MCInst_getNumOperands(MI) == 3 &&
3228
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
34
    if (MCInst_getNumOperands(MI) == 3 &&
3239
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
34
    if (MCInst_getNumOperands(MI) == 3 &&
3250
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
34
    if (MCInst_getNumOperands(MI) == 3 &&
3261
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
34
    return NULL;
3272
224
  case SP_MOVICCri:
3273
224
    if (MCInst_getNumOperands(MI) == 3 &&
3274
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
224
    if (MCInst_getNumOperands(MI) == 3 &&
3283
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
224
    if (MCInst_getNumOperands(MI) == 3 &&
3292
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
224
    if (MCInst_getNumOperands(MI) == 3 &&
3301
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
224
    if (MCInst_getNumOperands(MI) == 3 &&
3310
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
224
    if (MCInst_getNumOperands(MI) == 3 &&
3319
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
224
    if (MCInst_getNumOperands(MI) == 3 &&
3328
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
224
    if (MCInst_getNumOperands(MI) == 3 &&
3337
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
224
    if (MCInst_getNumOperands(MI) == 3 &&
3346
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
224
    if (MCInst_getNumOperands(MI) == 3 &&
3355
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
224
    if (MCInst_getNumOperands(MI) == 3 &&
3364
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
224
    if (MCInst_getNumOperands(MI) == 3 &&
3373
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
224
    if (MCInst_getNumOperands(MI) == 3 &&
3382
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
224
    if (MCInst_getNumOperands(MI) == 3 &&
3391
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
224
    if (MCInst_getNumOperands(MI) == 3 &&
3400
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
224
    if (MCInst_getNumOperands(MI) == 3 &&
3409
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
224
    return NULL;
3418
240
  case SP_MOVICCrr:
3419
240
    if (MCInst_getNumOperands(MI) == 3 &&
3420
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
240
    if (MCInst_getNumOperands(MI) == 3 &&
3431
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
240
    if (MCInst_getNumOperands(MI) == 3 &&
3442
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
240
    if (MCInst_getNumOperands(MI) == 3 &&
3453
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
240
    if (MCInst_getNumOperands(MI) == 3 &&
3464
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
240
    if (MCInst_getNumOperands(MI) == 3 &&
3475
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
240
    if (MCInst_getNumOperands(MI) == 3 &&
3486
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
240
    if (MCInst_getNumOperands(MI) == 3 &&
3497
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
240
    if (MCInst_getNumOperands(MI) == 3 &&
3508
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
240
    if (MCInst_getNumOperands(MI) == 3 &&
3519
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
240
    if (MCInst_getNumOperands(MI) == 3 &&
3530
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
240
    if (MCInst_getNumOperands(MI) == 3 &&
3541
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
240
    if (MCInst_getNumOperands(MI) == 3 &&
3552
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
240
    if (MCInst_getNumOperands(MI) == 3 &&
3563
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
240
    if (MCInst_getNumOperands(MI) == 3 &&
3574
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
240
    if (MCInst_getNumOperands(MI) == 3 &&
3585
240
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
240
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
240
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
240
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
240
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
240
    return NULL;
3596
208
  case SP_MOVXCCri:
3597
208
    if (MCInst_getNumOperands(MI) == 3 &&
3598
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
208
    if (MCInst_getNumOperands(MI) == 3 &&
3607
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
208
    if (MCInst_getNumOperands(MI) == 3 &&
3616
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
208
    if (MCInst_getNumOperands(MI) == 3 &&
3625
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
208
    if (MCInst_getNumOperands(MI) == 3 &&
3634
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
208
    if (MCInst_getNumOperands(MI) == 3 &&
3643
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
208
    if (MCInst_getNumOperands(MI) == 3 &&
3652
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
208
    if (MCInst_getNumOperands(MI) == 3 &&
3661
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
208
    if (MCInst_getNumOperands(MI) == 3 &&
3670
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
208
    if (MCInst_getNumOperands(MI) == 3 &&
3679
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
208
    if (MCInst_getNumOperands(MI) == 3 &&
3688
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
208
    if (MCInst_getNumOperands(MI) == 3 &&
3697
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
208
    if (MCInst_getNumOperands(MI) == 3 &&
3706
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
208
    if (MCInst_getNumOperands(MI) == 3 &&
3715
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
208
    if (MCInst_getNumOperands(MI) == 3 &&
3724
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
208
    if (MCInst_getNumOperands(MI) == 3 &&
3733
208
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
208
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
208
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
208
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
208
    return NULL;
3742
344
  case SP_MOVXCCrr:
3743
344
    if (MCInst_getNumOperands(MI) == 3 &&
3744
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
344
    if (MCInst_getNumOperands(MI) == 3 &&
3755
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
344
    if (MCInst_getNumOperands(MI) == 3 &&
3766
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
344
    if (MCInst_getNumOperands(MI) == 3 &&
3777
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
344
    if (MCInst_getNumOperands(MI) == 3 &&
3788
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
344
    if (MCInst_getNumOperands(MI) == 3 &&
3799
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
344
    if (MCInst_getNumOperands(MI) == 3 &&
3810
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
344
    if (MCInst_getNumOperands(MI) == 3 &&
3821
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
344
    if (MCInst_getNumOperands(MI) == 3 &&
3832
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
344
    if (MCInst_getNumOperands(MI) == 3 &&
3843
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
344
    if (MCInst_getNumOperands(MI) == 3 &&
3854
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
344
    if (MCInst_getNumOperands(MI) == 3 &&
3865
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
344
    if (MCInst_getNumOperands(MI) == 3 &&
3876
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
344
    if (MCInst_getNumOperands(MI) == 3 &&
3887
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
344
    if (MCInst_getNumOperands(MI) == 3 &&
3898
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
344
    if (MCInst_getNumOperands(MI) == 3 &&
3909
344
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
344
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
344
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
344
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
344
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
344
    return NULL;
3920
357
  case SP_ORri:
3921
357
    if (MCInst_getNumOperands(MI) == 3 &&
3922
357
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
357
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
357
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
43
      AsmString = "mov $\x03, $\x01";
3927
43
      break;
3928
43
    }
3929
314
    return NULL;
3930
271
  case SP_ORrr:
3931
271
    if (MCInst_getNumOperands(MI) == 3 &&
3932
271
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
271
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
271
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
271
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
271
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
234
      AsmString = "mov $\x03, $\x01";
3939
234
      break;
3940
234
    }
3941
37
    return NULL;
3942
194
  case SP_RESTORErr:
3943
194
    if (MCInst_getNumOperands(MI) == 3 &&
3944
194
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
194
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
194
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
45
      AsmString = "restore";
3949
45
      break;
3950
45
    }
3951
149
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
6.11k
  case SP_TXCCri:
3971
6.11k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
6.11k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
6.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
6.11k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
6.11k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
344
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
344
      break;
3979
344
    }
3980
5.77k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
5.77k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
5.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
5.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
5.77k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
5.77k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
5.77k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
5.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
5.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
267
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
267
      break;
3996
267
    }
3997
5.50k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
5.50k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
5.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
5.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
5.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
5.50k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
5.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
5.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
5.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
255
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
255
      break;
4013
255
    }
4014
5.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
5.24k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
5.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
5.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
5.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
5.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
5.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
5.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
5.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
34
      AsmString = "te %xcc, $\x01 + $\x02";
4029
34
      break;
4030
34
    }
4031
5.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
5.21k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
5.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
5.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
5.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
5.21k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
5.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
5.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
5.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
628
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
628
      break;
4047
628
    }
4048
4.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
4.58k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
4.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
4.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
4.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
4.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
4.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
4.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
4.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
1.18k
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
1.18k
      break;
4064
1.18k
    }
4065
3.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
3.40k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
3.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
3.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
3.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
3.40k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
3.40k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
3.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
3.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
132
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
132
      break;
4081
132
    }
4082
3.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
3.27k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
3.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
3.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
3.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
3.27k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
3.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
3.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
3.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
101
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
101
      break;
4098
101
    }
4099
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
3.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
3.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
94
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
94
      break;
4115
94
    }
4116
3.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
3.07k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
3.07k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
3.07k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
3.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
3.07k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
3.07k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
3.07k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
3.07k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
160
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
160
      break;
4132
160
    }
4133
2.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
2.91k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
2.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
2.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
2.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
2.91k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
2.91k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
2.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
2.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
386
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
386
      break;
4149
386
    }
4150
2.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
2.53k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
2.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
2.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
2.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
2.53k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
2.53k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
2.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
2.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
67
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
67
      break;
4166
67
    }
4167
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
2.46k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
2.46k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
67
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
67
      break;
4183
67
    }
4184
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4185
2.39k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
2.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4193
2.39k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
2.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
2.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
2.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
253
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
253
      break;
4200
253
    }
4201
2.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4202
2.14k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
2.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4210
2.14k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
2.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
169
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
169
      break;
4217
169
    }
4218
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4219
1.97k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4227
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
1.97k
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
1.97k
      break;
4234
1.97k
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.70k
  case SP_TXCCrr:
4245
2.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
225
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
225
      break;
4255
225
    }
4256
2.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.47k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.47k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.47k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.47k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
18
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
18
      break;
4276
18
    }
4277
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.46k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.46k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.46k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.46k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
216
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
216
      break;
4297
216
    }
4298
2.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.24k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.24k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.24k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.24k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.24k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.24k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
71
      AsmString = "te %xcc, $\x01 + $\x02";
4317
71
      break;
4318
71
    }
4319
2.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.17k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.17k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.17k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.17k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.17k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
129
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
129
      break;
4339
129
    }
4340
2.04k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.04k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.04k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.04k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
68
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
68
      break;
4360
68
    }
4361
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.97k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.97k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.97k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.97k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.97k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.97k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
54
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
54
      break;
4381
54
    }
4382
1.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.92k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
1.92k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
1.92k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.92k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.92k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.92k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.92k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
582
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
582
      break;
4402
582
    }
4403
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.34k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.34k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.34k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.34k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.34k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.34k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.34k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.34k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
75
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
75
      break;
4423
75
    }
4424
1.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.26k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
35
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
35
      break;
4444
35
    }
4445
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.23k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
66
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
66
      break;
4465
66
    }
4466
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.16k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
34
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
34
      break;
4486
34
    }
4487
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.13k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
84
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
84
      break;
4507
84
    }
4508
1.04k
    if (MCInst_getNumOperands(MI) == 3 &&
4509
1.04k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
1.04k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
1.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
1.04k
    if (MCInst_getNumOperands(MI) == 3 &&
4519
1.04k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
1.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
1.04k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
1.04k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
41
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
41
      break;
4528
41
    }
4529
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4530
1.00k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4540
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
103
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
103
      break;
4549
103
    }
4550
902
    if (MCInst_getNumOperands(MI) == 3 &&
4551
902
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
902
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
902
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
902
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
902
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
902
    if (MCInst_getNumOperands(MI) == 3 &&
4561
902
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
902
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
902
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
902
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
902
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
902
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
902
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
902
      break;
4570
902
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
106
  case SP_V9FCMPD:
4583
106
    if (MCInst_getNumOperands(MI) == 3 &&
4584
106
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
106
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
106
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
106
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
106
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
37
      AsmString = "fcmpd $\x02, $\x03";
4591
37
      break;
4592
37
    }
4593
69
    return NULL;
4594
536
  case SP_V9FCMPED:
4595
536
    if (MCInst_getNumOperands(MI) == 3 &&
4596
536
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
536
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
536
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
536
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
536
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
423
      AsmString = "fcmped $\x02, $\x03";
4603
423
      break;
4604
423
    }
4605
113
    return NULL;
4606
425
  case SP_V9FCMPEQ:
4607
425
    if (MCInst_getNumOperands(MI) == 3 &&
4608
425
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
425
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
425
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
425
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
425
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
34
      AsmString = "fcmpeq $\x02, $\x03";
4615
34
      break;
4616
34
    }
4617
391
    return NULL;
4618
695
  case SP_V9FCMPES:
4619
695
    if (MCInst_getNumOperands(MI) == 3 &&
4620
695
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
695
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
695
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
695
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
695
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
593
      AsmString = "fcmpes $\x02, $\x03";
4627
593
      break;
4628
593
    }
4629
102
    return NULL;
4630
270
  case SP_V9FCMPQ:
4631
270
    if (MCInst_getNumOperands(MI) == 3 &&
4632
270
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
270
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
270
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
270
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
270
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
69
      AsmString = "fcmpq $\x02, $\x03";
4639
69
      break;
4640
69
    }
4641
201
    return NULL;
4642
259
  case SP_V9FCMPS:
4643
259
    if (MCInst_getNumOperands(MI) == 3 &&
4644
259
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
259
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
259
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
259
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
259
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
34
      AsmString = "fcmps $\x02, $\x03";
4651
34
      break;
4652
34
    }
4653
225
    return NULL;
4654
78
  case SP_V9FMOVD_FCC:
4655
78
    if (MCInst_getNumOperands(MI) == 4 &&
4656
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
78
    if (MCInst_getNumOperands(MI) == 4 &&
4669
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
78
    if (MCInst_getNumOperands(MI) == 4 &&
4682
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
78
    if (MCInst_getNumOperands(MI) == 4 &&
4695
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
78
    if (MCInst_getNumOperands(MI) == 4 &&
4708
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
78
    if (MCInst_getNumOperands(MI) == 4 &&
4721
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
78
    if (MCInst_getNumOperands(MI) == 4 &&
4734
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
78
    if (MCInst_getNumOperands(MI) == 4 &&
4747
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
78
    if (MCInst_getNumOperands(MI) == 4 &&
4760
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
78
    if (MCInst_getNumOperands(MI) == 4 &&
4773
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
78
    if (MCInst_getNumOperands(MI) == 4 &&
4786
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
78
    if (MCInst_getNumOperands(MI) == 4 &&
4799
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
78
    if (MCInst_getNumOperands(MI) == 4 &&
4812
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
78
    if (MCInst_getNumOperands(MI) == 4 &&
4825
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
78
    if (MCInst_getNumOperands(MI) == 4 &&
4838
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
78
    if (MCInst_getNumOperands(MI) == 4 &&
4851
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
78
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
78
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
78
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
78
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
78
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
78
    return NULL;
4864
324
  case SP_V9FMOVQ_FCC:
4865
324
    if (MCInst_getNumOperands(MI) == 4 &&
4866
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
324
    if (MCInst_getNumOperands(MI) == 4 &&
4879
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
324
    if (MCInst_getNumOperands(MI) == 4 &&
4892
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
324
    if (MCInst_getNumOperands(MI) == 4 &&
4905
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
324
    if (MCInst_getNumOperands(MI) == 4 &&
4918
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
324
    if (MCInst_getNumOperands(MI) == 4 &&
4931
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
324
    if (MCInst_getNumOperands(MI) == 4 &&
4944
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
324
    if (MCInst_getNumOperands(MI) == 4 &&
4957
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
324
    if (MCInst_getNumOperands(MI) == 4 &&
4970
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
324
    if (MCInst_getNumOperands(MI) == 4 &&
4983
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
324
    if (MCInst_getNumOperands(MI) == 4 &&
4996
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
324
    if (MCInst_getNumOperands(MI) == 4 &&
5009
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
324
    if (MCInst_getNumOperands(MI) == 4 &&
5022
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
324
    if (MCInst_getNumOperands(MI) == 4 &&
5035
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
324
    if (MCInst_getNumOperands(MI) == 4 &&
5048
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
324
    if (MCInst_getNumOperands(MI) == 4 &&
5061
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
324
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
324
    return NULL;
5074
477
  case SP_V9FMOVS_FCC:
5075
477
    if (MCInst_getNumOperands(MI) == 4 &&
5076
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
477
    if (MCInst_getNumOperands(MI) == 4 &&
5089
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
477
    if (MCInst_getNumOperands(MI) == 4 &&
5102
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
477
    if (MCInst_getNumOperands(MI) == 4 &&
5115
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
477
    if (MCInst_getNumOperands(MI) == 4 &&
5128
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
477
    if (MCInst_getNumOperands(MI) == 4 &&
5141
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
477
    if (MCInst_getNumOperands(MI) == 4 &&
5154
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
477
    if (MCInst_getNumOperands(MI) == 4 &&
5167
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
477
    if (MCInst_getNumOperands(MI) == 4 &&
5180
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
477
    if (MCInst_getNumOperands(MI) == 4 &&
5193
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
477
    if (MCInst_getNumOperands(MI) == 4 &&
5206
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
477
    if (MCInst_getNumOperands(MI) == 4 &&
5219
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
477
    if (MCInst_getNumOperands(MI) == 4 &&
5232
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
477
    if (MCInst_getNumOperands(MI) == 4 &&
5245
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
477
    if (MCInst_getNumOperands(MI) == 4 &&
5258
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
477
    if (MCInst_getNumOperands(MI) == 4 &&
5271
477
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
477
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
477
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
477
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
477
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
477
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
477
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
477
    return NULL;
5284
296
  case SP_V9MOVFCCri:
5285
296
    if (MCInst_getNumOperands(MI) == 4 &&
5286
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
296
    if (MCInst_getNumOperands(MI) == 4 &&
5297
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
296
    if (MCInst_getNumOperands(MI) == 4 &&
5308
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
296
    if (MCInst_getNumOperands(MI) == 4 &&
5319
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
296
    if (MCInst_getNumOperands(MI) == 4 &&
5330
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
296
    if (MCInst_getNumOperands(MI) == 4 &&
5341
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
296
    if (MCInst_getNumOperands(MI) == 4 &&
5352
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
296
    if (MCInst_getNumOperands(MI) == 4 &&
5363
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
296
    if (MCInst_getNumOperands(MI) == 4 &&
5374
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
296
    if (MCInst_getNumOperands(MI) == 4 &&
5385
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
296
    if (MCInst_getNumOperands(MI) == 4 &&
5396
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
296
    if (MCInst_getNumOperands(MI) == 4 &&
5407
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
296
    if (MCInst_getNumOperands(MI) == 4 &&
5418
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
296
    if (MCInst_getNumOperands(MI) == 4 &&
5429
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
296
    if (MCInst_getNumOperands(MI) == 4 &&
5440
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
296
    if (MCInst_getNumOperands(MI) == 4 &&
5451
296
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
296
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
296
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
296
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
296
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
296
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
296
    return NULL;
5462
215
  case SP_V9MOVFCCrr:
5463
215
    if (MCInst_getNumOperands(MI) == 4 &&
5464
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
215
    if (MCInst_getNumOperands(MI) == 4 &&
5477
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
215
    if (MCInst_getNumOperands(MI) == 4 &&
5490
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
215
    if (MCInst_getNumOperands(MI) == 4 &&
5503
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
215
    if (MCInst_getNumOperands(MI) == 4 &&
5516
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
215
    if (MCInst_getNumOperands(MI) == 4 &&
5529
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
215
    if (MCInst_getNumOperands(MI) == 4 &&
5542
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
215
    if (MCInst_getNumOperands(MI) == 4 &&
5555
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
215
    if (MCInst_getNumOperands(MI) == 4 &&
5568
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
215
    if (MCInst_getNumOperands(MI) == 4 &&
5581
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
215
    if (MCInst_getNumOperands(MI) == 4 &&
5594
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
215
    if (MCInst_getNumOperands(MI) == 4 &&
5607
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
215
    if (MCInst_getNumOperands(MI) == 4 &&
5620
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
215
    if (MCInst_getNumOperands(MI) == 4 &&
5633
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
215
    if (MCInst_getNumOperands(MI) == 4 &&
5646
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
215
    if (MCInst_getNumOperands(MI) == 4 &&
5659
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
215
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
215
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
215
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
215
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
215
    return NULL;
5672
80.6k
  }
5673
5674
35.4k
  tmp = cs_strdup(AsmString);
5675
35.4k
  AsmMnem = tmp;
5676
224k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
224k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
35.4k
      *AsmOps = '\0';
5679
35.4k
      AsmOps++;
5680
35.4k
      break;
5681
35.4k
    }
5682
224k
  }
5683
35.4k
  SStream_concat0(OS, AsmMnem);
5684
35.4k
  if (*AsmOps) {
5685
35.4k
    SStream_concat0(OS, "\t");
5686
35.4k
    if (strstr(AsmOps, "icc"))
5687
6.25k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
35.4k
    if (strstr(AsmOps, "xcc"))
5689
13.7k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
252k
    for (c = AsmOps; *c; c++) {
5691
217k
      if (*c == '$') {
5692
53.1k
        c += 1;
5693
53.1k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
53.1k
          printOperand(MI, *c - 1, OS);
5701
164k
      } else {
5702
164k
        SStream_concat(OS, "%c", *c);
5703
164k
      }
5704
217k
    }
5705
35.4k
  }
5706
35.4k
  return tmp;
5707
80.6k
}
5708
5709
#endif // PRINT_ALIAS_INSTR