/src/capstonenext/arch/MOS65XX/MOS65XXDisassembler.c

Source (jump to first uncovered line)
/* Capstone Disassembly Engine */
/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */

#include "capstone/mos65xx.h"
#include "MOS65XXDisassembler.h"
#include "MOS65XXDisassemblerInternals.h"

typedef struct OpInfo {
  mos65xx_insn ins;
  mos65xx_address_mode am;
  int operand_bytes;
} OpInfo;

static const struct OpInfo OpInfoTable[] = {

#include "m6502.inc"
#include "m65c02.inc"
#include "mw65c02.inc"
#include "m65816.inc"

};

#ifndef CAPSTONE_DIET
static const char *const RegNames[] = { "invalid", "A",  "X", "Y", "P",
          "SP",    "DP", "B", "K" };

static const char *const GroupNames[] = {
  NULL, "jump", "call", "ret", "int", "iret", "branch_relative"
};

typedef struct InstructionInfo {
  const char *name;
  mos65xx_group_type group_type;
  mos65xx_reg write, read;
  bool modifies_status;
} InstructionInfo;

static const struct InstructionInfo InstructionInfoTable[] = {

#include "instruction_info.inc"

};
#endif

#ifndef CAPSTONE_DIET
static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
{
  int i;
  cs_detail *detail = MI->flat_insn->detail;

  InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];

  detail->mos65xx.am = opinfo.am;
  detail->mos65xx.modifies_flags = insinfo.modifies_status;
  detail->groups_count = 0;
  detail->regs_read_count = 0;
  detail->regs_write_count = 0;
  detail->mos65xx.op_count = 0;

  if (insinfo.group_type != MOS65XX_GRP_INVALID) {
    detail->groups[detail->groups_count] = insinfo.group_type;
    detail->groups_count++;
  }

  if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) {
    detail->groups[detail->groups_count] =
      MOS65XX_GRP_BRANCH_RELATIVE;
    detail->groups_count++;
  }

  if (insinfo.read != MOS65XX_REG_INVALID) {
    detail->regs_read[detail->regs_read_count++] = insinfo.read;
  } else
    switch (opinfo.am) {
    case MOS65XX_AM_ACC:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_ACC;
      break;
    case MOS65XX_AM_ZP_Y:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ABS_Y:
    case MOS65XX_AM_ZP_IND_LONG_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      break;

    case MOS65XX_AM_ZP_X:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ABS_X:
    case MOS65XX_AM_ABS_X_IND:
    case MOS65XX_AM_ABS_LONG_X:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_X;
      break;

    case MOS65XX_AM_SR:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_SP;
      break;
    case MOS65XX_AM_SR_IND_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_SP;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      break;

    default:
      break;
    }

  if (insinfo.write != MOS65XX_REG_INVALID) {
    detail->regs_write[detail->regs_write_count++] = insinfo.write;
  } else if (opinfo.am == MOS65XX_AM_ACC) {
    detail->regs_write[detail->regs_write_count++] =
      MOS65XX_REG_ACC;
  }

  switch (opinfo.ins) {
  case MOS65XX_INS_ADC:
  case MOS65XX_INS_SBC:
  case MOS65XX_INS_ROL:
  case MOS65XX_INS_ROR:
    /* these read carry flag (and decimal for ADC/SBC) */
    detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
    break;
  /* stack operations */
  case MOS65XX_INS_JSL:
  case MOS65XX_INS_JSR:
  case MOS65XX_INS_PEA:
  case MOS65XX_INS_PEI:
  case MOS65XX_INS_PER:
  case MOS65XX_INS_PHA:
  case MOS65XX_INS_PHB:
  case MOS65XX_INS_PHD:
  case MOS65XX_INS_PHK:
  case MOS65XX_INS_PHP:
  case MOS65XX_INS_PHX:
  case MOS65XX_INS_PHY:
  case MOS65XX_INS_PLA:
  case MOS65XX_INS_PLB:
  case MOS65XX_INS_PLD:
  case MOS65XX_INS_PLP:
  case MOS65XX_INS_PLX:
  case MOS65XX_INS_PLY:
  case MOS65XX_INS_RTI:
  case MOS65XX_INS_RTL:
  case MOS65XX_INS_RTS:
    detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
    detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
    break;
  default:
    break;
  }

  if (cpu_type == MOS65XX_CPU_TYPE_65816) {
    switch (opinfo.am) {
    case MOS65XX_AM_ZP:
    case MOS65XX_AM_ZP_X:
    case MOS65XX_AM_ZP_Y:
    case MOS65XX_AM_ZP_IND:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ZP_IND_LONG:
    case MOS65XX_AM_ZP_IND_LONG_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_DP;
      break;
    case MOS65XX_AM_BLOCK:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_ACC;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_X;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_ACC;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_X;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_Y;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_B;
      break;
    default:
      break;
    }

    switch (opinfo.am) {
    case MOS65XX_AM_ZP_IND:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ABS:
    case MOS65XX_AM_ABS_X:
    case MOS65XX_AM_ABS_Y:
    case MOS65XX_AM_ABS_X_IND:
      /* these depend on the databank to generate a 24-bit address */
      /* exceptions: PEA, PEI, and JMP (abs) */
      if (opinfo.ins == MOS65XX_INS_PEI ||
          opinfo.ins == MOS65XX_INS_PEA)
        break;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_B;
      break;
    default:
      break;
    }
  }

  if (insinfo.modifies_status) {
    detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
  }

  switch (opinfo.am) {
  case MOS65XX_AM_IMP:
    break;
  case MOS65XX_AM_IMM:
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_IMM;
    detail->mos65xx.operands[detail->mos65xx.op_count].imm =
      MI->Operands[0].ImmVal;
    detail->mos65xx.op_count++;
    break;
  case MOS65XX_AM_ACC:
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_REG;
    detail->mos65xx.operands[detail->mos65xx.op_count].reg =
      MOS65XX_REG_ACC;
    detail->mos65xx.op_count++;
    break;
  case MOS65XX_AM_REL: {
    int value = MI->Operands[0].ImmVal;
    if (MI->op1_size == 1)
      value = 2 + (signed char)value;
    else
      value = 3 + (signed short)value;
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count].mem =
      (MI->address + value) & 0xffff;
    detail->mos65xx.op_count++;
    break;
  }
  case MOS65XX_AM_ZP_REL: {
    int value = 3 + (signed char)MI->Operands[1].ImmVal;
    /* BBR0, zp, rel  and BBS0, zp, rel */
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count].mem =
      MI->Operands[0].ImmVal;
    detail->mos65xx.operands[detail->mos65xx.op_count + 1].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count + 1].mem =
      (MI->address + value) & 0xffff;
    detail->mos65xx.op_count += 2;
    break;
  }
  default:
    for (i = 0; i < MI->size; ++i) {
      detail->mos65xx.operands[detail->mos65xx.op_count].type =
        MOS65XX_OP_MEM;
      detail->mos65xx.operands[detail->mos65xx.op_count].mem =
        MI->Operands[i].ImmVal;
      detail->mos65xx.op_count++;
    }
    break;
  }
}
#endif

void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
{
#ifndef CAPSTONE_DIET
  unsigned int value;
  unsigned opcode = MCInst_getOpcode(MI);
  mos65xx_info *info = (mos65xx_info *)PrinterInfo;

  OpInfo opinfo = OpInfoTable[opcode];

  const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";

  SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
  switch (opinfo.ins) {
  /* special case - bit included as part of the instruction name */
  case MOS65XX_INS_BBR:
  case MOS65XX_INS_BBS:
  case MOS65XX_INS_RMB:
  case MOS65XX_INS_SMB:
    SStream_concat(O, "%d", (opcode >> 4) & 0x07);
    break;
  default:
    break;
  }

  value = MI->Operands[0].ImmVal;

  switch (opinfo.am) {
  default:
    break;

  case MOS65XX_AM_IMP:
    break;

  case MOS65XX_AM_ACC:
    SStream_concat0(O, " a");
    break;

  case MOS65XX_AM_IMM:
    if (MI->imm_size == 1)
      SStream_concat(O, " #%s%02x", prefix, value);
    else
      SStream_concat(O, " #%s%04x", prefix, value);
    break;

  case MOS65XX_AM_ZP:
    SStream_concat(O, " %s%02x", prefix, value);
    break;

  case MOS65XX_AM_ABS:
    SStream_concat(O, " %s%04x", prefix, value);
    break;

  case MOS65XX_AM_ABS_LONG_X:
    SStream_concat(O, " %s%06x, x", prefix, value);
    break;

  case MOS65XX_AM_INT:
    SStream_concat(O, " %s%02x", prefix, value);
    break;

  case MOS65XX_AM_ABS_X:
    SStream_concat(O, " %s%04x, x", prefix, value);
    break;

  case MOS65XX_AM_ABS_Y:
    SStream_concat(O, " %s%04x, y", prefix, value);
    break;

  case MOS65XX_AM_ABS_LONG:
    SStream_concat(O, " %s%06x", prefix, value);
    break;

  case MOS65XX_AM_ZP_X:
    SStream_concat(O, " %s%02x, x", prefix, value);
    break;

  case MOS65XX_AM_ZP_Y:
    SStream_concat(O, " %s%02x, y", prefix, value);
    break;

  case MOS65XX_AM_REL:
    if (MI->op1_size == 1)
      value = 2 + (signed char)value;
    else
      value = 3 + (signed short)value;

    SStream_concat(O, " %s%04x", prefix,
             (MI->address + value) & 0xffff);
    break;

  case MOS65XX_AM_ABS_IND:
    SStream_concat(O, " (%s%04x)", prefix, value);
    break;

  case MOS65XX_AM_ABS_X_IND:
    SStream_concat(O, " (%s%04x, x)", prefix, value);
    break;

  case MOS65XX_AM_ABS_IND_LONG:
    SStream_concat(O, " [%s%04x]", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND:
    SStream_concat(O, " (%s%02x)", prefix, value);
    break;

  case MOS65XX_AM_ZP_X_IND:
    SStream_concat(O, " (%s%02x, x)", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_Y:
    SStream_concat(O, " (%s%02x), y", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_LONG:
    SStream_concat(O, " [%s%02x]", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_LONG_Y:
    SStream_concat(O, " [%s%02x], y", prefix, value);
    break;

  case MOS65XX_AM_SR:
    SStream_concat(O, " %s%02x, s", prefix, value);
    break;

  case MOS65XX_AM_SR_IND_Y:
    SStream_concat(O, " (%s%02x, s), y", prefix, value);
    break;

  case MOS65XX_AM_BLOCK:
    SStream_concat(O, " %s%02x, %s%02x", prefix,
             MI->Operands[0].ImmVal, prefix,
             MI->Operands[1].ImmVal);
    break;

  case MOS65XX_AM_ZP_REL:
    value = 3 + (signed char)MI->Operands[1].ImmVal;
    /* BBR0, zp, rel  and BBS0, zp, rel */
    SStream_concat(O, " %s%02x, %s%04x", prefix,
             MI->Operands[0].ImmVal, prefix,
             (MI->address + value) & 0xffff);
    break;
  }
#endif
}

bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
          MCInst *MI, uint16_t *size, uint64_t address,
          void *inst_info)
{
  int i;
  unsigned char opcode;
  unsigned char len;
  unsigned cpu_offset = 0;
  int cpu_type = MOS65XX_CPU_TYPE_6502;
  cs_struct *handle = MI->csh;
  mos65xx_info *info = (mos65xx_info *)handle->printer_info;
  OpInfo opinfo;

  if (code_len == 0) {
    *size = 1;
    return false;
  }

  cpu_type = info->cpu_type;
  cpu_offset = cpu_type * 256;

  opcode = code[0];
  opinfo = OpInfoTable[cpu_offset + opcode];
  if (opinfo.ins == MOS65XX_INS_INVALID) {
    *size = 1;
    return false;
  }

  len = opinfo.operand_bytes + 1;

  if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
    switch (opinfo.ins) {
    case MOS65XX_INS_CPX:
    case MOS65XX_INS_CPY:
    case MOS65XX_INS_LDX:
    case MOS65XX_INS_LDY:
      if (info->long_x)
        ++len;
      break;
    case MOS65XX_INS_ADC:
    case MOS65XX_INS_AND:
    case MOS65XX_INS_BIT:
    case MOS65XX_INS_CMP:
    case MOS65XX_INS_EOR:
    case MOS65XX_INS_LDA:
    case MOS65XX_INS_ORA:
    case MOS65XX_INS_SBC:
      if (info->long_m)
        ++len;
      break;
    default:
      break;
    }
  }

  if (code_len < len) {
    *size = 1;
    return false;
  }

  MI->address = address;

  MCInst_setOpcode(MI, cpu_offset + opcode);
  MCInst_setOpcodePub(MI, opinfo.ins);

  *size = len;

  /* needed to differentiate relative vs relative long */
  MI->op1_size = len - 1;
  if (opinfo.ins == MOS65XX_INS_NOP) {
    for (i = 1; i < len; ++i)
      MCOperand_CreateImm0(MI, code[i]);
  }

  switch (opinfo.am) {
  case MOS65XX_AM_ZP_REL:
    MCOperand_CreateImm0(MI, code[1]);
    MCOperand_CreateImm0(MI, code[2]);
    break;
  case MOS65XX_AM_BLOCK:
    MCOperand_CreateImm0(MI, code[2]);
    MCOperand_CreateImm0(MI, code[1]);
    break;
  case MOS65XX_AM_IMP:
  case MOS65XX_AM_ACC:
    break;

  case MOS65XX_AM_IMM:
    MI->has_imm = 1;
    MI->imm_size = len - 1;
    /* 65816 immediate is either 1 or 2 bytes */
    /* drop through */
  default:
    if (len == 2)
      MCOperand_CreateImm0(MI, code[1]);
    else if (len == 3)
      MCOperand_CreateImm0(MI, (code[2] << 8) | code[1]);
    else if (len == 4)
      MCOperand_CreateImm0(
        MI, (code[3] << 16) | (code[2] << 8) | code[1]);
    break;
  }

#ifndef CAPSTONE_DIET
  if (MI->flat_insn->detail) {
    fillDetails(MI, opinfo, cpu_type);
  }
#endif

  return true;
}

const char *MOS65XX_insn_name(csh handle, unsigned int id)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (id >= ARR_SIZE(InstructionInfoTable)) {
    return NULL;
  }
  return InstructionInfoTable[id].name;
#endif
}

const char *MOS65XX_reg_name(csh handle, unsigned int reg)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (reg >= ARR_SIZE(RegNames)) {
    return NULL;
  }
  return RegNames[(int)reg];
#endif
}

void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
  /* id is cpu_offset + opcode */
  if (id < ARR_SIZE(OpInfoTable)) {
    insn->id = OpInfoTable[id].ins;
  }
}

const char *MOS65XX_group_name(csh handle, unsigned int id)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (id >= ARR_SIZE(GroupNames)) {
    return NULL;
  }
  return GroupNames[(int)id];
#endif
}

Coverage Report

Created: 2025-08-29 06:29

Line	Count	Source (jump to first uncovered line)
1		/* Capstone Disassembly Engine */
2		/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
3
4		#include "capstone/mos65xx.h"
5		#include "MOS65XXDisassembler.h"
6		#include "MOS65XXDisassemblerInternals.h"
7
8		typedef struct OpInfo {
9		mos65xx_insn ins;
10		mos65xx_address_mode am;
11		int operand_bytes;
12		} OpInfo;
13
14		static const struct OpInfo OpInfoTable[] = {
15
16		#include "m6502.inc"
17		#include "m65c02.inc"
18		#include "mw65c02.inc"
19		#include "m65816.inc"
20
21		};
22
23		#ifndef CAPSTONE_DIET
24		static const char *const RegNames[] = { "invalid", "A", "X", "Y", "P",
25		"SP", "DP", "B", "K" };
26
27		static const char *const GroupNames[] = {
28		NULL, "jump", "call", "ret", "int", "iret", "branch_relative"
29		};
30
31		typedef struct InstructionInfo {
32		const char *name;
33		mos65xx_group_type group_type;
34		mos65xx_reg write, read;
35		bool modifies_status;
36		} InstructionInfo;
37
38		static const struct InstructionInfo InstructionInfoTable[] = {
39
40		#include "instruction_info.inc"
41
42		};
43		#endif
44
45		#ifndef CAPSTONE_DIET
46		static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
47	9.73k	{
48	9.73k	int i;
49	9.73k	cs_detail *detail = MI->flat_insn->detail;
50
51	9.73k	InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];
52
53	9.73k	detail->mos65xx.am = opinfo.am;
54	9.73k	detail->mos65xx.modifies_flags = insinfo.modifies_status;
55	9.73k	detail->groups_count = 0;
56	9.73k	detail->regs_read_count = 0;
57	9.73k	detail->regs_write_count = 0;
58	9.73k	detail->mos65xx.op_count = 0;
59
60	9.73k	if (insinfo.group_type != MOS65XX_GRP_INVALID) {
61	2.82k	detail->groups[detail->groups_count] = insinfo.group_type;
62	2.82k	detail->groups_count++;
63	2.82k	}
64
65	9.73k	if (opinfo.am == MOS65XX_AM_REL \|\| opinfo.am == MOS65XX_AM_ZP_REL) {
66	556	detail->groups[detail->groups_count] =
67	556	MOS65XX_GRP_BRANCH_RELATIVE;
68	556	detail->groups_count++;
69	556	}
70
71	9.73k	if (insinfo.read != MOS65XX_REG_INVALID) {
72	3.47k	detail->regs_read[detail->regs_read_count++] = insinfo.read;
73	3.47k	} else
74	6.25k	switch (opinfo.am) {
75	782	case MOS65XX_AM_ACC:
76	782	detail->regs_read[detail->regs_read_count++] =
77	782	MOS65XX_REG_ACC;
78	782	break;
79	241	case MOS65XX_AM_ZP_Y:
80	475	case MOS65XX_AM_ZP_IND_Y:
81	575	case MOS65XX_AM_ABS_Y:
82	575	case MOS65XX_AM_ZP_IND_LONG_Y:
83	575	detail->regs_read[detail->regs_read_count++] =
84	575	MOS65XX_REG_Y;
85	575	break;
86
87	558	case MOS65XX_AM_ZP_X:
88	833	case MOS65XX_AM_ZP_X_IND:
89	1.11k	case MOS65XX_AM_ABS_X:
90	1.11k	case MOS65XX_AM_ABS_X_IND:
91	1.11k	case MOS65XX_AM_ABS_LONG_X:
92	1.11k	detail->regs_read[detail->regs_read_count++] =
93	1.11k	MOS65XX_REG_X;
94	1.11k	break;
95
96	0	case MOS65XX_AM_SR:
97	0	detail->regs_read[detail->regs_read_count++] =
98	0	MOS65XX_REG_SP;
99	0	break;
100	0	case MOS65XX_AM_SR_IND_Y:
101	0	detail->regs_read[detail->regs_read_count++] =
102	0	MOS65XX_REG_SP;
103	0	detail->regs_read[detail->regs_read_count++] =
104	0	MOS65XX_REG_Y;
105	0	break;
106
107	3.78k	default:
108	3.78k	break;
109	6.25k	}
110
111	9.73k	if (insinfo.write != MOS65XX_REG_INVALID) {
112	2.73k	detail->regs_write[detail->regs_write_count++] = insinfo.write;
113	7.00k	} else if (opinfo.am == MOS65XX_AM_ACC) {
114	782	detail->regs_write[detail->regs_write_count++] =
115	782	MOS65XX_REG_ACC;
116	782	}
117
118	9.73k	switch (opinfo.ins) {
119	256	case MOS65XX_INS_ADC:
120	556	case MOS65XX_INS_SBC:
121	1.04k	case MOS65XX_INS_ROL:
122	1.41k	case MOS65XX_INS_ROR:
123		/* these read carry flag (and decimal for ADC/SBC) */
124	1.41k	detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
125	1.41k	break;
126		/* stack operations */
127	0	case MOS65XX_INS_JSL:
128	407	case MOS65XX_INS_JSR:
129	407	case MOS65XX_INS_PEA:
130	407	case MOS65XX_INS_PEI:
131	407	case MOS65XX_INS_PER:
132	686	case MOS65XX_INS_PHA:
133	686	case MOS65XX_INS_PHB:
134	686	case MOS65XX_INS_PHD:
135	686	case MOS65XX_INS_PHK:
136	1.06k	case MOS65XX_INS_PHP:
137	1.06k	case MOS65XX_INS_PHX:
138	1.06k	case MOS65XX_INS_PHY:
139	1.33k	case MOS65XX_INS_PLA:
140	1.33k	case MOS65XX_INS_PLB:
141	1.33k	case MOS65XX_INS_PLD:
142	1.76k	case MOS65XX_INS_PLP:
143	1.76k	case MOS65XX_INS_PLX:
144	1.76k	case MOS65XX_INS_PLY:
145	2.04k	case MOS65XX_INS_RTI:
146	2.04k	case MOS65XX_INS_RTL:
147	2.28k	case MOS65XX_INS_RTS:
148	2.28k	detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
149	2.28k	detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
150	2.28k	break;
151	6.02k	default:
152	6.02k	break;
153	9.73k	}
154
155	9.73k	if (cpu_type == MOS65XX_CPU_TYPE_65816) {
156	0	switch (opinfo.am) {
157	0	case MOS65XX_AM_ZP:
158	0	case MOS65XX_AM_ZP_X:
159	0	case MOS65XX_AM_ZP_Y:
160	0	case MOS65XX_AM_ZP_IND:
161	0	case MOS65XX_AM_ZP_X_IND:
162	0	case MOS65XX_AM_ZP_IND_Y:
163	0	case MOS65XX_AM_ZP_IND_LONG:
164	0	case MOS65XX_AM_ZP_IND_LONG_Y:
165	0	detail->regs_read[detail->regs_read_count++] =
166	0	MOS65XX_REG_DP;
167	0	break;
168	0	case MOS65XX_AM_BLOCK:
169	0	detail->regs_read[detail->regs_read_count++] =
170	0	MOS65XX_REG_ACC;
171	0	detail->regs_read[detail->regs_read_count++] =
172	0	MOS65XX_REG_X;
173	0	detail->regs_read[detail->regs_read_count++] =
174	0	MOS65XX_REG_Y;
175	0	detail->regs_write[detail->regs_write_count++] =
176	0	MOS65XX_REG_ACC;
177	0	detail->regs_write[detail->regs_write_count++] =
178	0	MOS65XX_REG_X;
179	0	detail->regs_write[detail->regs_write_count++] =
180	0	MOS65XX_REG_Y;
181	0	detail->regs_write[detail->regs_write_count++] =
182	0	MOS65XX_REG_B;
183	0	break;
184	0	default:
185	0	break;
186	0	}
187
188	0	switch (opinfo.am) {
189	0	case MOS65XX_AM_ZP_IND:
190	0	case MOS65XX_AM_ZP_X_IND:
191	0	case MOS65XX_AM_ZP_IND_Y:
192	0	case MOS65XX_AM_ABS:
193	0	case MOS65XX_AM_ABS_X:
194	0	case MOS65XX_AM_ABS_Y:
195	0	case MOS65XX_AM_ABS_X_IND:
196		/* these depend on the databank to generate a 24-bit address */
197		/* exceptions: PEA, PEI, and JMP (abs) */
198	0	if (opinfo.ins == MOS65XX_INS_PEI \|\|
199	0	opinfo.ins == MOS65XX_INS_PEA)
200	0	break;
201	0	detail->regs_read[detail->regs_read_count++] =
202	0	MOS65XX_REG_B;
203	0	break;
204	0	default:
205	0	break;
206	0	}
207	0	}
208
209	9.73k	if (insinfo.modifies_status) {
210	5.50k	detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
211	5.50k	}
212
213	9.73k	switch (opinfo.am) {
214	2.71k	case MOS65XX_AM_IMP:
215	2.71k	break;
216	685	case MOS65XX_AM_IMM:
217	685	detail->mos65xx.operands[detail->mos65xx.op_count].type =
218	685	MOS65XX_OP_IMM;
219	685	detail->mos65xx.operands[detail->mos65xx.op_count].imm =
220	685	MI->Operands[0].ImmVal;
221	685	detail->mos65xx.op_count++;
222	685	break;
223	782	case MOS65XX_AM_ACC:
224	782	detail->mos65xx.operands[detail->mos65xx.op_count].type =
225	782	MOS65XX_OP_REG;
226	782	detail->mos65xx.operands[detail->mos65xx.op_count].reg =
227	782	MOS65XX_REG_ACC;
228	782	detail->mos65xx.op_count++;
229	782	break;
230	556	case MOS65XX_AM_REL: {
231	556	int value = MI->Operands[0].ImmVal;
232	556	if (MI->op1_size == 1)
233	556	value = 2 + (signed char)value;
234	0	else
235	0	value = 3 + (signed short)value;
236	556	detail->mos65xx.operands[detail->mos65xx.op_count].type =
237	556	MOS65XX_OP_MEM;
238	556	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
239	556	(MI->address + value) & 0xffff;
240	556	detail->mos65xx.op_count++;
241	556	break;
242	0	}
243	0	case MOS65XX_AM_ZP_REL: {
244	0	int value = 3 + (signed char)MI->Operands[1].ImmVal;
245		/* BBR0, zp, rel and BBS0, zp, rel */
246	0	detail->mos65xx.operands[detail->mos65xx.op_count].type =
247	0	MOS65XX_OP_MEM;
248	0	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
249	0	MI->Operands[0].ImmVal;
250	0	detail->mos65xx.operands[detail->mos65xx.op_count + 1].type =
251	0	MOS65XX_OP_MEM;
252	0	detail->mos65xx.operands[detail->mos65xx.op_count + 1].mem =
253	0	(MI->address + value) & 0xffff;
254	0	detail->mos65xx.op_count += 2;
255	0	break;
256	0	}
257	4.99k	default:
258	9.99k	for (i = 0; i < MI->size; ++i) {
259	4.99k	detail->mos65xx.operands[detail->mos65xx.op_count].type =
260	4.99k	MOS65XX_OP_MEM;
261	4.99k	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
262	4.99k	MI->Operands[i].ImmVal;
263	4.99k	detail->mos65xx.op_count++;
264	4.99k	}
265	4.99k	break;
266	9.73k	}
267	9.73k	}
268		#endif
269
270		void MOS65XX_printInst(MCInst MI, struct SStream O, void *PrinterInfo)
271	9.73k	{
272	9.73k	#ifndef CAPSTONE_DIET
273	9.73k	unsigned int value;
274	9.73k	unsigned opcode = MCInst_getOpcode(MI);
275	9.73k	mos65xx_info info = (mos65xx_info )PrinterInfo;
276
277	9.73k	OpInfo opinfo = OpInfoTable[opcode];
278
279	9.73k	const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";
280
281	9.73k	SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
282	9.73k	switch (opinfo.ins) {
283		/* special case - bit included as part of the instruction name */
284	0	case MOS65XX_INS_BBR:
285	0	case MOS65XX_INS_BBS:
286	0	case MOS65XX_INS_RMB:
287	0	case MOS65XX_INS_SMB:
288	0	SStream_concat(O, "%d", (opcode >> 4) & 0x07);
289	0	break;
290	9.73k	default:
291	9.73k	break;
292	9.73k	}
293
294	9.73k	value = MI->Operands[0].ImmVal;
295
296	9.73k	switch (opinfo.am) {
297	0	default:
298	0	break;
299
300	2.71k	case MOS65XX_AM_IMP:
301	2.71k	break;
302
303	782	case MOS65XX_AM_ACC:
304	782	SStream_concat0(O, " a");
305	782	break;
306
307	685	case MOS65XX_AM_IMM:
308	685	if (MI->imm_size == 1)
309	685	SStream_concat(O, " #%s%02x", prefix, value);
310	0	else
311	0	SStream_concat(O, " #%s%04x", prefix, value);
312	685	break;
313
314	511	case MOS65XX_AM_ZP:
315	511	SStream_concat(O, " %s%02x", prefix, value);
316	511	break;
317
318	535	case MOS65XX_AM_ABS:
319	535	SStream_concat(O, " %s%04x", prefix, value);
320	535	break;
321
322	0	case MOS65XX_AM_ABS_LONG_X:
323	0	SStream_concat(O, " %s%06x, x", prefix, value);
324	0	break;
325
326	1.03k	case MOS65XX_AM_INT:
327	1.03k	SStream_concat(O, " %s%02x", prefix, value);
328	1.03k	break;
329
330	347	case MOS65XX_AM_ABS_X:
331	347	SStream_concat(O, " %s%04x, x", prefix, value);
332	347	break;
333
334	308	case MOS65XX_AM_ABS_Y:
335	308	SStream_concat(O, " %s%04x, y", prefix, value);
336	308	break;
337
338	0	case MOS65XX_AM_ABS_LONG:
339	0	SStream_concat(O, " %s%06x", prefix, value);
340	0	break;
341
342	893	case MOS65XX_AM_ZP_X:
343	893	SStream_concat(O, " %s%02x, x", prefix, value);
344	893	break;
345
346	295	case MOS65XX_AM_ZP_Y:
347	295	SStream_concat(O, " %s%02x, y", prefix, value);
348	295	break;
349
350	556	case MOS65XX_AM_REL:
351	556	if (MI->op1_size == 1)
352	556	value = 2 + (signed char)value;
353	0	else
354	0	value = 3 + (signed short)value;
355
356	556	SStream_concat(O, " %s%04x", prefix,
357	556	(MI->address + value) & 0xffff);
358	556	break;
359
360	301	case MOS65XX_AM_ABS_IND:
361	301	SStream_concat(O, " (%s%04x)", prefix, value);
362	301	break;
363
364	0	case MOS65XX_AM_ABS_X_IND:
365	0	SStream_concat(O, " (%s%04x, x)", prefix, value);
366	0	break;
367
368	0	case MOS65XX_AM_ABS_IND_LONG:
369	0	SStream_concat(O, " [%s%04x]", prefix, value);
370	0	break;
371
372	0	case MOS65XX_AM_ZP_IND:
373	0	SStream_concat(O, " (%s%02x)", prefix, value);
374	0	break;
375
376	425	case MOS65XX_AM_ZP_X_IND:
377	425	SStream_concat(O, " (%s%02x, x)", prefix, value);
378	425	break;
379
380	343	case MOS65XX_AM_ZP_IND_Y:
381	343	SStream_concat(O, " (%s%02x), y", prefix, value);
382	343	break;
383
384	0	case MOS65XX_AM_ZP_IND_LONG:
385	0	SStream_concat(O, " [%s%02x]", prefix, value);
386	0	break;
387
388	0	case MOS65XX_AM_ZP_IND_LONG_Y:
389	0	SStream_concat(O, " [%s%02x], y", prefix, value);
390	0	break;
391
392	0	case MOS65XX_AM_SR:
393	0	SStream_concat(O, " %s%02x, s", prefix, value);
394	0	break;
395
396	0	case MOS65XX_AM_SR_IND_Y:
397	0	SStream_concat(O, " (%s%02x, s), y", prefix, value);
398	0	break;
399
400	0	case MOS65XX_AM_BLOCK:
401	0	SStream_concat(O, " %s%02x, %s%02x", prefix,
402	0	MI->Operands[0].ImmVal, prefix,
403	0	MI->Operands[1].ImmVal);
404	0	break;
405
406	0	case MOS65XX_AM_ZP_REL:
407	0	value = 3 + (signed char)MI->Operands[1].ImmVal;
408		/* BBR0, zp, rel and BBS0, zp, rel */
409	0	SStream_concat(O, " %s%02x, %s%04x", prefix,
410	0	MI->Operands[0].ImmVal, prefix,
411	0	(MI->address + value) & 0xffff);
412	0	break;
413	9.73k	}
414	9.73k	#endif
415	9.73k	}
416
417		bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
418		MCInst MI, uint16_t size, uint64_t address,
419		void *inst_info)
420	9.85k	{
421	9.85k	int i;
422	9.85k	unsigned char opcode;
423	9.85k	unsigned char len;
424	9.85k	unsigned cpu_offset = 0;
425	9.85k	int cpu_type = MOS65XX_CPU_TYPE_6502;
426	9.85k	cs_struct *handle = MI->csh;
427	9.85k	mos65xx_info info = (mos65xx_info )handle->printer_info;
428	9.85k	OpInfo opinfo;
429
430	9.85k	if (code_len == 0) {
431	0	*size = 1;
432	0	return false;
433	0	}
434
435	9.85k	cpu_type = info->cpu_type;
436	9.85k	cpu_offset = cpu_type * 256;
437
438	9.85k	opcode = code[0];
439	9.85k	opinfo = OpInfoTable[cpu_offset + opcode];
440	9.85k	if (opinfo.ins == MOS65XX_INS_INVALID) {
441	87	*size = 1;
442	87	return false;
443	87	}
444
445	9.77k	len = opinfo.operand_bytes + 1;
446
447	9.77k	if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
448	0	switch (opinfo.ins) {
449	0	case MOS65XX_INS_CPX:
450	0	case MOS65XX_INS_CPY:
451	0	case MOS65XX_INS_LDX:
452	0	case MOS65XX_INS_LDY:
453	0	if (info->long_x)
454	0	++len;
455	0	break;
456	0	case MOS65XX_INS_ADC:
457	0	case MOS65XX_INS_AND:
458	0	case MOS65XX_INS_BIT:
459	0	case MOS65XX_INS_CMP:
460	0	case MOS65XX_INS_EOR:
461	0	case MOS65XX_INS_LDA:
462	0	case MOS65XX_INS_ORA:
463	0	case MOS65XX_INS_SBC:
464	0	if (info->long_m)
465	0	++len;
466	0	break;
467	0	default:
468	0	break;
469	0	}
470	0	}
471
472	9.77k	if (code_len < len) {
473	38	*size = 1;
474	38	return false;
475	38	}
476
477	9.73k	MI->address = address;
478
479	9.73k	MCInst_setOpcode(MI, cpu_offset + opcode);
480	9.73k	MCInst_setOpcodePub(MI, opinfo.ins);
481
482	9.73k	*size = len;
483
484		/* needed to differentiate relative vs relative long */
485	9.73k	MI->op1_size = len - 1;
486	9.73k	if (opinfo.ins == MOS65XX_INS_NOP) {
487	498	for (i = 1; i < len; ++i)
488	0	MCOperand_CreateImm0(MI, code[i]);
489	498	}
490
491	9.73k	switch (opinfo.am) {
492	0	case MOS65XX_AM_ZP_REL:
493	0	MCOperand_CreateImm0(MI, code[1]);
494	0	MCOperand_CreateImm0(MI, code[2]);
495	0	break;
496	0	case MOS65XX_AM_BLOCK:
497	0	MCOperand_CreateImm0(MI, code[2]);
498	0	MCOperand_CreateImm0(MI, code[1]);
499	0	break;
500	2.71k	case MOS65XX_AM_IMP:
501	3.49k	case MOS65XX_AM_ACC:
502	3.49k	break;
503
504	685	case MOS65XX_AM_IMM:
505	685	MI->has_imm = 1;
506	685	MI->imm_size = len - 1;
507		/* 65816 immediate is either 1 or 2 bytes */
508		/* drop through */
509	6.23k	default:
510	6.23k	if (len == 2)
511	4.74k	MCOperand_CreateImm0(MI, code[1]);
512	1.49k	else if (len == 3)
513	1.49k	MCOperand_CreateImm0(MI, (code[2] << 8) \| code[1]);
514	0	else if (len == 4)
515	0	MCOperand_CreateImm0(
516	0	MI, (code[3] << 16) \| (code[2] << 8) \| code[1]);
517	6.23k	break;
518	9.73k	}
519
520	9.73k	#ifndef CAPSTONE_DIET
521	9.73k	if (MI->flat_insn->detail) {
522	9.73k	fillDetails(MI, opinfo, cpu_type);
523	9.73k	}
524	9.73k	#endif
525
526	9.73k	return true;
527	9.73k	}
528
529		const char *MOS65XX_insn_name(csh handle, unsigned int id)
530	9.73k	{
531		#ifdef CAPSTONE_DIET
532		return NULL;
533		#else
534	9.73k	if (id >= ARR_SIZE(InstructionInfoTable)) {
535	0	return NULL;
536	0	}
537	9.73k	return InstructionInfoTable[id].name;
538	9.73k	#endif
539	9.73k	}
540
541		const char *MOS65XX_reg_name(csh handle, unsigned int reg)
542	20.9k	{
543		#ifdef CAPSTONE_DIET
544		return NULL;
545		#else
546	20.9k	if (reg >= ARR_SIZE(RegNames)) {
547	0	return NULL;
548	0	}
549	20.9k	return RegNames[(int)reg];
550	20.9k	#endif
551	20.9k	}
552
553		void MOS65XX_get_insn_id(cs_struct h, cs_insn insn, unsigned int id)
554	9.73k	{
555		/* id is cpu_offset + opcode */
556	9.73k	if (id < ARR_SIZE(OpInfoTable)) {
557	9.73k	insn->id = OpInfoTable[id].ins;
558	9.73k	}
559	9.73k	}
560
561		const char *MOS65XX_group_name(csh handle, unsigned int id)
562	3.38k	{
563		#ifdef CAPSTONE_DIET
564		return NULL;
565		#else
566	3.38k	if (id >= ARR_SIZE(GroupNames)) {
567	0	return NULL;
568	0	}
569	3.38k	return GroupNames[(int)id];
570	3.38k	#endif
571	3.38k	}