Coverage Report

Created: 2025-10-10 06:20

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/Mips/MipsInstPrinter.c
Line
Count
Source
1
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
4
/* Automatically translated source file from LLVM. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Only small edits allowed. */
10
/* For multiple similar edits, please create a Patch for the translator. */
11
12
/* Capstone's C++ file translator: */
13
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
14
15
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
16
//
17
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18
// See https://llvm.org/LICENSE.txt for license information.
19
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
20
//
21
//===----------------------------------------------------------------------===//
22
//
23
// This class prints an Mips MCInst to a .s file.
24
//
25
//===----------------------------------------------------------------------===//
26
27
#include <stdio.h>
28
#include <string.h>
29
#include <stdlib.h>
30
#include <capstone/platform.h>
31
32
#include "MipsMapping.h"
33
#include "MipsInstPrinter.h"
34
35
#define GET_SUBTARGETINFO_ENUM
36
#include "MipsGenSubtargetInfo.inc"
37
38
#define GET_INSTRINFO_ENUM
39
#include "MipsGenInstrInfo.inc"
40
41
#define GET_REGINFO_ENUM
42
#include "MipsGenRegisterInfo.inc"
43
44
7.50k
#define CONCAT(a, b) CONCAT_(a, b)
45
7.50k
#define CONCAT_(a, b) a##_##b
46
47
#define DEBUG_TYPE "asm-printer"
48
49
#define PRINT_ALIAS_INSTR
50
#include "MipsGenAsmWriter.inc"
51
52
static bool isReg(const MCInst *MI, unsigned OpNo, unsigned R)
53
2.02k
{
54
2.02k
  return MCOperand_getReg(MCInst_getOperand((MCInst *)MI, (OpNo))) == R;
55
2.02k
}
56
57
static const char *MipsFCCToString(Mips_CondCode CC)
58
0
{
59
0
  switch (CC) {
60
0
  case Mips_FCOND_F:
61
0
  case Mips_FCOND_T:
62
0
    return "f";
63
0
  case Mips_FCOND_UN:
64
0
  case Mips_FCOND_OR:
65
0
    return "un";
66
0
  case Mips_FCOND_OEQ:
67
0
  case Mips_FCOND_UNE:
68
0
    return "eq";
69
0
  case Mips_FCOND_UEQ:
70
0
  case Mips_FCOND_ONE:
71
0
    return "ueq";
72
0
  case Mips_FCOND_OLT:
73
0
  case Mips_FCOND_UGE:
74
0
    return "olt";
75
0
  case Mips_FCOND_ULT:
76
0
  case Mips_FCOND_OGE:
77
0
    return "ult";
78
0
  case Mips_FCOND_OLE:
79
0
  case Mips_FCOND_UGT:
80
0
    return "ole";
81
0
  case Mips_FCOND_ULE:
82
0
  case Mips_FCOND_OGT:
83
0
    return "ule";
84
0
  case Mips_FCOND_SF:
85
0
  case Mips_FCOND_ST:
86
0
    return "sf";
87
0
  case Mips_FCOND_NGLE:
88
0
  case Mips_FCOND_GLE:
89
0
    return "ngle";
90
0
  case Mips_FCOND_SEQ:
91
0
  case Mips_FCOND_SNE:
92
0
    return "seq";
93
0
  case Mips_FCOND_NGL:
94
0
  case Mips_FCOND_GL:
95
0
    return "ngl";
96
0
  case Mips_FCOND_LT:
97
0
  case Mips_FCOND_NLT:
98
0
    return "lt";
99
0
  case Mips_FCOND_NGE:
100
0
  case Mips_FCOND_GE:
101
0
    return "nge";
102
0
  case Mips_FCOND_LE:
103
0
  case Mips_FCOND_NLE:
104
0
    return "le";
105
0
  case Mips_FCOND_NGT:
106
0
  case Mips_FCOND_GT:
107
0
    return "ngt";
108
0
  }
109
0
  CS_ASSERT_RET_VAL(0 && "Impossible condition code!", NULL);
110
0
  return "";
111
0
}
112
113
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
114
115
static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
116
66.3k
{
117
66.3k
  int syntax_opt = MI->csh->syntax;
118
66.3k
  if (!(syntax_opt & CS_OPT_SYNTAX_NO_DOLLAR)) {
119
66.3k
    SStream_concat1(OS, '$');
120
66.3k
  }
121
66.3k
  SStream_concat0(OS, Mips_LLVM_getRegisterName(
122
66.3k
            Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME));
123
66.3k
}
124
125
static void patch_cs_printer(MCInst *MI, SStream *O)
126
36.8k
{
127
  // replace '# 16 bit inst' to empty.
128
36.8k
  SStream_replc(O, '#', 0);
129
36.8k
  SStream_trimls(O);
130
131
36.8k
  if (MI->csh->syntax & CS_OPT_SYNTAX_NO_DOLLAR) {
132
0
    char *dollar = strchr(O->buffer, '$');
133
0
    if (!dollar) {
134
0
      return;
135
0
    }
136
0
    size_t dollar_len = strlen(dollar + 1);
137
    // to include `\0`
138
0
    memmove(dollar, dollar + 1, dollar_len + 1);
139
0
  }
140
36.8k
}
141
142
static void patch_cs_detail_operand_reg(cs_mips_op *op, unsigned reg,
143
          unsigned access)
144
318
{
145
318
  op->type = MIPS_OP_REG;
146
318
  op->reg = reg;
147
318
  op->is_reglist = false;
148
318
  op->access = access;
149
318
}
150
151
static void patch_cs_details(MCInst *MI)
152
36.8k
{
153
36.8k
  if (!detail_is_set(MI))
154
0
    return;
155
156
36.8k
  cs_mips_op *op0 = NULL, *op1 = NULL, *op2 = NULL;
157
36.8k
  unsigned opcode = MCInst_getOpcode(MI);
158
36.8k
  unsigned n_ops = MCInst_getNumOperands(MI);
159
160
36.8k
  switch (opcode) {
161
  /* mips r2 to r5 only 64bit */
162
5
  case Mips_DSDIV: /// ddiv $$zero, $rs, $rt
163
    /* fall-thru */
164
70
  case Mips_DUDIV: /// ddivu $$zero, $rs, $rt
165
70
    if (n_ops != 2) {
166
0
      return;
167
0
    }
168
70
    Mips_inc_op_count(MI);
169
70
    op0 = Mips_get_detail_op(MI, -3);
170
70
    op1 = Mips_get_detail_op(MI, -2);
171
70
    op2 = Mips_get_detail_op(MI, -1);
172
    // move all details by one and add $zero reg
173
70
    *op2 = *op1;
174
70
    *op1 = *op0;
175
70
    patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO_64, CS_AC_WRITE);
176
70
    return;
177
178
  /* mips r2 to r5 only */
179
53
  case Mips_SDIV: /// div $$zero, $rs, $rt
180
    /* fall-thru */
181
214
  case Mips_UDIV: /// divu $$zero, $rs, $rt
182
    /* fall-thru */
183
  /* microMIPS only */
184
222
  case Mips_SDIV_MM: /// div $$zero, $rs, $rt
185
    /* fall-thru */
186
248
  case Mips_UDIV_MM: /// divu $$zero, $rs, $rt
187
    /* fall-thru */
188
189
  /* MIPS16 only */
190
248
  case Mips_DivRxRy16: /// div $$zero, $rx, $ry
191
    /* fall-thru */
192
248
  case Mips_DivuRxRy16: /// divu $$zero, $rx, $ry
193
248
    if (n_ops != 2) {
194
0
      return;
195
0
    }
196
248
    Mips_inc_op_count(MI);
197
248
    op0 = Mips_get_detail_op(MI, -3);
198
248
    op1 = Mips_get_detail_op(MI, -2);
199
248
    op2 = Mips_get_detail_op(MI, -1);
200
    // move all details by one and add $zero reg
201
248
    *op2 = *op1;
202
248
    *op1 = *op0;
203
248
    patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO, CS_AC_WRITE);
204
248
    return;
205
0
  case Mips_AddiuSpImm16: /// addiu $$sp, imm8
206
    /* fall-thru */
207
0
  case Mips_AddiuSpImmX16: /// addiu $$sp, imm8
208
0
    if (n_ops != 1) {
209
0
      return;
210
0
    }
211
0
    Mips_inc_op_count(MI);
212
0
    op0 = Mips_get_detail_op(MI, -2);
213
0
    op1 = Mips_get_detail_op(MI, -1);
214
    // move all details by one and add $sp reg
215
0
    *op1 = *op0;
216
0
    patch_cs_detail_operand_reg(op0, MIPS_REG_SP, CS_AC_READ_WRITE);
217
0
    return;
218
0
  case Mips_JrcRa16: /// jrc $ra
219
    /* fall-thru */
220
0
  case Mips_JrRa16: /// jr $ra
221
0
    if (n_ops > 0) {
222
0
      return;
223
0
    }
224
0
    Mips_inc_op_count(MI);
225
0
    op0 = Mips_get_detail_op(MI, -1);
226
0
    patch_cs_detail_operand_reg(op0, MIPS_REG_RA, CS_AC_READ);
227
0
    return;
228
36.5k
  default:
229
36.5k
    return;
230
36.8k
  }
231
36.8k
}
232
233
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O)
234
36.8k
{
235
36.8k
  bool useAliasDetails = map_use_alias_details(MI);
236
36.8k
  if (!useAliasDetails) {
237
0
    SStream_Close(O);
238
0
    printInstruction(MI, Address, O);
239
0
    SStream_Open(O);
240
0
    map_set_fill_detail_ops(MI, false);
241
0
  }
242
243
36.8k
  if (printAliasInstr(MI, Address, O) || printAlias4(MI, Address, O)) {
244
2.06k
    MCInst_setIsAlias(MI, true);
245
34.7k
  } else {
246
34.7k
    printInstruction(MI, Address, O);
247
34.7k
  }
248
249
36.8k
  patch_cs_printer(MI, O);
250
36.8k
  patch_cs_details(MI);
251
252
36.8k
  if (!useAliasDetails) {
253
0
    map_set_fill_detail_ops(MI, true);
254
0
  }
255
36.8k
}
256
257
void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
258
77.5k
{
259
77.5k
  switch (MCInst_getOpcode(MI)) {
260
77.5k
  default:
261
77.5k
    break;
262
77.5k
  case Mips_AND16_NM:
263
0
  case Mips_XOR16_NM:
264
0
  case Mips_OR16_NM:
265
0
    if (MCInst_getNumOperands(MI) == 2 && OpNo == 2)
266
0
      OpNo = 0; // rt, rs -> rt, rs, rt
267
0
    break;
268
0
  case Mips_ADDu4x4_NM:
269
0
  case Mips_MUL4x4_NM:
270
0
    if (MCInst_getNumOperands(MI) == 2 && OpNo > 0)
271
0
      OpNo = OpNo - 1; // rt, rs -> rt, rt, rs
272
0
    break;
273
77.5k
  }
274
275
77.5k
  MCOperand *Op = MCInst_getOperand(MI, (OpNo));
276
77.5k
  if (MCOperand_isReg(Op)) {
277
64.3k
    add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
278
64.3k
    printRegName(MI, O, MCOperand_getReg(Op));
279
64.3k
    return;
280
64.3k
  }
281
282
13.1k
  if (MCOperand_isImm(Op)) {
283
13.1k
    switch (MCInst_getOpcode(MI)) {
284
0
    case Mips_LI48_NM:
285
0
    case Mips_ANDI16_NM:
286
0
    case Mips_ANDI_NM:
287
0
    case Mips_ORI_NM:
288
0
    case Mips_XORI_NM:
289
0
    case Mips_TEQ_NM:
290
0
    case Mips_TNE_NM:
291
0
    case Mips_SIGRIE_NM:
292
0
    case Mips_SDBBP_NM:
293
0
    case Mips_SDBBP16_NM:
294
0
    case Mips_BREAK_NM:
295
0
    case Mips_BREAK16_NM:
296
0
    case Mips_SYSCALL_NM:
297
0
    case Mips_SYSCALL16_NM:
298
0
    case Mips_WAIT_NM:
299
0
      CONCAT(printUImm, CONCAT(32, 0))
300
0
      (MI, OpNo, O);
301
0
      break;
302
13.1k
    default:
303
13.1k
      add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
304
13.1k
      printInt64(O, MCOperand_getImm(Op));
305
13.1k
      break;
306
13.1k
    }
307
13.1k
    return;
308
13.1k
  }
309
13.1k
}
310
311
static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O)
312
668
{
313
668
  add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo);
314
668
  MCOperand *Op = MCInst_getOperand(MI, (OpNo));
315
668
  if (MCOperand_isReg(Op))
316
0
    return printRegName(MI, O, MCOperand_getReg(Op));
317
318
  // only the upper bits are needed.
319
668
  uint64_t Base = MI->address & ~0x0fffffffull;
320
668
  uint64_t Target = MCOperand_getImm(Op);
321
668
  printInt64(O, Base | Target);
322
668
}
323
324
static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
325
             SStream *O)
326
6.37k
{
327
6.37k
  add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo);
328
6.37k
  MCOperand *Op = MCInst_getOperand(MI, (OpNo));
329
6.37k
  if (MCOperand_isReg(Op))
330
342
    return printRegName(MI, O, MCOperand_getReg(Op));
331
332
6.03k
  uint64_t Target = Address + MCOperand_getImm(Op);
333
6.03k
  printInt64(O, Target);
334
6.03k
}
335
336
#define DEFINE_printUImm(Bits) \
337
  static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \
338
                   SStream *O) \
339
7.43k
  { \
340
7.43k
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
7.43k
            opNum); \
342
7.43k
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
7.43k
    if (MCOperand_isImm(MO)) { \
344
7.43k
      uint64_t Imm = MCOperand_getImm(MO); \
345
7.43k
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
7.43k
      printUInt64(O, Imm); \
347
7.43k
      return; \
348
7.43k
    } \
349
7.43k
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_10_0
Line
Count
Source
339
769
  { \
340
769
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
769
            opNum); \
342
769
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
769
    if (MCOperand_isImm(MO)) { \
344
769
      uint64_t Imm = MCOperand_getImm(MO); \
345
769
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
769
      printUInt64(O, Imm); \
347
769
      return; \
348
769
    } \
349
769
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_4_0
Line
Count
Source
339
989
  { \
340
989
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
989
            opNum); \
342
989
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
989
    if (MCOperand_isImm(MO)) { \
344
989
      uint64_t Imm = MCOperand_getImm(MO); \
345
989
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
989
      printUInt64(O, Imm); \
347
989
      return; \
348
989
    } \
349
989
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_5_0
Line
Count
Source
339
1.19k
  { \
340
1.19k
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
1.19k
            opNum); \
342
1.19k
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
1.19k
    if (MCOperand_isImm(MO)) { \
344
1.19k
      uint64_t Imm = MCOperand_getImm(MO); \
345
1.19k
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
1.19k
      printUInt64(O, Imm); \
347
1.19k
      return; \
348
1.19k
    } \
349
1.19k
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
Unexecuted instantiation: MipsInstPrinter.c:printUImm_26_0
MipsInstPrinter.c:printUImm_8_0
Line
Count
Source
339
613
  { \
340
613
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
613
            opNum); \
342
613
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
613
    if (MCOperand_isImm(MO)) { \
344
613
      uint64_t Imm = MCOperand_getImm(MO); \
345
613
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
613
      printUInt64(O, Imm); \
347
613
      return; \
348
613
    } \
349
613
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
Unexecuted instantiation: MipsInstPrinter.c:printUImm_12_0
MipsInstPrinter.c:printUImm_20_0
Line
Count
Source
339
65
  { \
340
65
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
65
            opNum); \
342
65
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
65
    if (MCOperand_isImm(MO)) { \
344
65
      uint64_t Imm = MCOperand_getImm(MO); \
345
65
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
65
      printUInt64(O, Imm); \
347
65
      return; \
348
65
    } \
349
65
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_16_0
Line
Count
Source
339
1.25k
  { \
340
1.25k
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
1.25k
            opNum); \
342
1.25k
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
1.25k
    if (MCOperand_isImm(MO)) { \
344
1.25k
      uint64_t Imm = MCOperand_getImm(MO); \
345
1.25k
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
1.25k
      printUInt64(O, Imm); \
347
1.25k
      return; \
348
1.25k
    } \
349
1.25k
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
Unexecuted instantiation: MipsInstPrinter.c:printUImm_32_0
MipsInstPrinter.c:printUImm_7_0
Line
Count
Source
339
21
  { \
340
21
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
21
            opNum); \
342
21
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
21
    if (MCOperand_isImm(MO)) { \
344
21
      uint64_t Imm = MCOperand_getImm(MO); \
345
21
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
21
      printUInt64(O, Imm); \
347
21
      return; \
348
21
    } \
349
21
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_2_0
Line
Count
Source
339
624
  { \
340
624
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
624
            opNum); \
342
624
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
624
    if (MCOperand_isImm(MO)) { \
344
624
      uint64_t Imm = MCOperand_getImm(MO); \
345
624
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
624
      printUInt64(O, Imm); \
347
624
      return; \
348
624
    } \
349
624
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_1_0
Line
Count
Source
339
450
  { \
340
450
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
450
            opNum); \
342
450
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
450
    if (MCOperand_isImm(MO)) { \
344
450
      uint64_t Imm = MCOperand_getImm(MO); \
345
450
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
450
      printUInt64(O, Imm); \
347
450
      return; \
348
450
    } \
349
450
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_3_0
Line
Count
Source
339
1.08k
  { \
340
1.08k
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
1.08k
            opNum); \
342
1.08k
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
1.08k
    if (MCOperand_isImm(MO)) { \
344
1.08k
      uint64_t Imm = MCOperand_getImm(MO); \
345
1.08k
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
1.08k
      printUInt64(O, Imm); \
347
1.08k
      return; \
348
1.08k
    } \
349
1.08k
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_0_0
Line
Count
Source
339
129
  { \
340
129
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
129
            opNum); \
342
129
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
129
    if (MCOperand_isImm(MO)) { \
344
129
      uint64_t Imm = MCOperand_getImm(MO); \
345
129
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
129
      printUInt64(O, Imm); \
347
129
      return; \
348
129
    } \
349
129
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
MipsInstPrinter.c:printUImm_6_0
Line
Count
Source
339
235
  { \
340
235
    add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \
341
235
            opNum); \
342
235
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
343
235
    if (MCOperand_isImm(MO)) { \
344
235
      uint64_t Imm = MCOperand_getImm(MO); \
345
235
      Imm &= (((uint64_t)1) << Bits) - 1; \
346
235
      printUInt64(O, Imm); \
347
235
      return; \
348
235
    } \
349
235
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
350
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
351
0
  }
352
353
#define DEFINE_printUImm_2(Bits, Offset) \
354
  static void CONCAT(printUImm, CONCAT(Bits, Offset))( \
355
    MCInst * MI, int opNum, SStream *O) \
356
69
  { \
357
69
    add_cs_detail( \
358
69
      MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \
359
69
      opNum); \
360
69
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
361
69
    if (MCOperand_isImm(MO)) { \
362
69
      uint64_t Imm = MCOperand_getImm(MO); \
363
69
      Imm -= Offset; \
364
69
      Imm &= (1 << Bits) - 1; \
365
69
      Imm += Offset; \
366
69
      printUInt64(O, Imm); \
367
69
      return; \
368
69
    } \
369
69
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
370
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
371
0
  }
MipsInstPrinter.c:printUImm_2_1
Line
Count
Source
356
55
  { \
357
55
    add_cs_detail( \
358
55
      MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \
359
55
      opNum); \
360
55
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
361
55
    if (MCOperand_isImm(MO)) { \
362
55
      uint64_t Imm = MCOperand_getImm(MO); \
363
55
      Imm -= Offset; \
364
55
      Imm &= (1 << Bits) - 1; \
365
55
      Imm += Offset; \
366
55
      printUInt64(O, Imm); \
367
55
      return; \
368
55
    } \
369
55
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
370
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
371
0
  }
Unexecuted instantiation: MipsInstPrinter.c:printUImm_5_32
MipsInstPrinter.c:printUImm_5_1
Line
Count
Source
356
14
  { \
357
14
    add_cs_detail( \
358
14
      MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \
359
14
      opNum); \
360
14
    MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
361
14
    if (MCOperand_isImm(MO)) { \
362
14
      uint64_t Imm = MCOperand_getImm(MO); \
363
14
      Imm -= Offset; \
364
14
      Imm &= (1 << Bits) - 1; \
365
14
      Imm += Offset; \
366
14
      printUInt64(O, Imm); \
367
14
      return; \
368
14
    } \
369
14
    MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
370
0
    printRegName(MI, O, MCOperand_getReg(Op)); \
371
0
  }
Unexecuted instantiation: MipsInstPrinter.c:printUImm_6_1
Unexecuted instantiation: MipsInstPrinter.c:printUImm_5_33
Unexecuted instantiation: MipsInstPrinter.c:printUImm_6_2
372
373
DEFINE_printUImm(0);
374
DEFINE_printUImm(1);
375
DEFINE_printUImm(10);
376
DEFINE_printUImm(12);
377
DEFINE_printUImm(16);
378
DEFINE_printUImm(2);
379
DEFINE_printUImm(20);
380
DEFINE_printUImm(26);
381
DEFINE_printUImm(3);
382
DEFINE_printUImm(32);
383
DEFINE_printUImm(4);
384
DEFINE_printUImm(5);
385
DEFINE_printUImm(6);
386
DEFINE_printUImm(7);
387
DEFINE_printUImm(8);
388
DEFINE_printUImm_2(2, 1);
389
DEFINE_printUImm_2(5, 1);
390
DEFINE_printUImm_2(5, 32);
391
DEFINE_printUImm_2(5, 33);
392
DEFINE_printUImm_2(6, 1);
393
DEFINE_printUImm_2(6, 2);
394
395
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
396
8.68k
{
397
  // Load/Store memory operands -- imm($reg)
398
  // If PIC target the target is loaded as the
399
  // pattern lw $25,%call16($28)
400
401
  // opNum can be invalid if instruction had reglist as operand.
402
  // MemOperand is always last operand of instruction (base + offset).
403
8.68k
  switch (MCInst_getOpcode(MI)) {
404
8.33k
  default:
405
8.33k
    break;
406
8.33k
  case Mips_SWM32_MM:
407
130
  case Mips_LWM32_MM:
408
278
  case Mips_SWM16_MM:
409
290
  case Mips_SWM16_MMR6:
410
291
  case Mips_LWM16_MM:
411
356
  case Mips_LWM16_MMR6:
412
356
    opNum = MCInst_getNumOperands(MI) - 2;
413
356
    break;
414
8.68k
  }
415
416
8.68k
  set_mem_access(MI, true);
417
  // Index register is encoded as immediate value
418
  // in case of nanoMIPS indexed instructions
419
8.68k
  switch (MCInst_getOpcode(MI)) {
420
  // No offset needed for paired LL/SC
421
0
  case Mips_LLWP_NM:
422
0
  case Mips_SCWP_NM:
423
0
    break;
424
0
  case Mips_LWX_NM:
425
0
  case Mips_LWXS_NM:
426
0
  case Mips_LWXS16_NM:
427
0
  case Mips_LBX_NM:
428
0
  case Mips_LBUX_NM:
429
0
  case Mips_LHX_NM:
430
0
  case Mips_LHUX_NM:
431
0
  case Mips_LHXS_NM:
432
0
  case Mips_LHUXS_NM:
433
0
  case Mips_SWX_NM:
434
0
  case Mips_SWXS_NM:
435
0
  case Mips_SBX_NM:
436
0
  case Mips_SHX_NM:
437
0
  case Mips_SHXS_NM:
438
0
    if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) {
439
0
      add_cs_detail(MI, Mips_OP_GROUP_MemOperand,
440
0
              (opNum + 1));
441
0
      printRegName(MI, O,
442
0
             MCOperand_getImm(MCInst_getOperand(
443
0
               MI, (opNum + 1))));
444
0
      break;
445
0
    }
446
    // Fall through
447
8.68k
  default:
448
8.68k
    printOperand((MCInst *)MI, opNum + 1, O);
449
8.68k
    break;
450
8.68k
  }
451
8.68k
  SStream_concat0(O, "(");
452
8.68k
  printOperand((MCInst *)MI, opNum, O);
453
8.68k
  SStream_concat0(O, ")");
454
8.68k
  set_mem_access(MI, false);
455
8.68k
}
456
457
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
458
0
{
459
  // when using stack locations for not load/store instructions
460
  // print the same way as all normal 3 operand instructions.
461
0
  printOperand((MCInst *)MI, opNum, O);
462
0
  SStream_concat0(O, ", ");
463
0
  printOperand((MCInst *)MI, opNum + 1, O);
464
0
}
465
466
static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
467
0
{
468
0
  MCOperand *MO = MCInst_getOperand(MI, (opNum));
469
0
  SStream_concat0(O,
470
0
      MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
471
0
}
472
473
static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
474
           unsigned OpNo, SStream *OS, bool IsBranch)
475
558
{
476
558
  SStream_concat(OS, "%s%s", "\t", Str);
477
558
  SStream_concat0(OS, "\t");
478
558
  if (IsBranch)
479
438
    printBranchOperand((MCInst *)MI, Address, OpNo, OS);
480
120
  else
481
120
    printOperand((MCInst *)MI, OpNo, OS);
482
558
  return true;
483
558
}
484
485
static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
486
      unsigned OpNo0, unsigned OpNo1, SStream *OS,
487
      bool IsBranch)
488
422
{
489
422
  printAlias(Str, MI, Address, OpNo0, OS, IsBranch);
490
422
  SStream_concat0(OS, ", ");
491
422
  if (IsBranch)
492
342
    printBranchOperand((MCInst *)MI, Address, OpNo1, OS);
493
80
  else
494
80
    printOperand((MCInst *)MI, OpNo1, OS);
495
422
  return true;
496
422
}
497
498
static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
499
      unsigned OpNo0, unsigned OpNo1, unsigned OpNo2,
500
      SStream *OS)
501
0
{
502
0
  printAlias(Str, MI, Address, OpNo0, OS, false);
503
0
  SStream_concat0(OS, ", ");
504
0
  printOperand((MCInst *)MI, OpNo1, OS);
505
0
  SStream_concat0(OS, ", ");
506
0
  printOperand((MCInst *)MI, OpNo2, OS);
507
0
  return true;
508
0
}
509
510
static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS)
511
35.3k
{
512
35.3k
  switch (MCInst_getOpcode(MI)) {
513
515
  case Mips_BEQ:
514
541
  case Mips_BEQ_MM:
515
    // beq $zero, $zero, $L2 => b $L2
516
    // beq $r0, $zero, $L2 => beqz $r0, $L2
517
541
    return (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO) &&
518
96
      printAlias("b", MI, Address, 2, OS, true)) ||
519
445
           (isReg(MI, 1, Mips_ZERO) &&
520
223
      printAlias2("beqz", MI, Address, 0, 2, OS, true));
521
0
  case Mips_BEQ64:
522
    // beq $r0, $zero, $L2 => beqz $r0, $L2
523
0
    return isReg(MI, 1, Mips_ZERO_64) &&
524
0
           printAlias2("beqz", MI, Address, 0, 2, OS, true);
525
366
  case Mips_BNE:
526
419
  case Mips_BNE_MM:
527
    // bne $r0, $zero, $L2 => bnez $r0, $L2
528
419
    return isReg(MI, 1, Mips_ZERO) &&
529
119
           printAlias2("bnez", MI, Address, 0, 2, OS, true);
530
0
  case Mips_BNE64:
531
    // bne $r0, $zero, $L2 => bnez $r0, $L2
532
0
    return isReg(MI, 1, Mips_ZERO_64) &&
533
0
           printAlias2("bnez", MI, Address, 0, 2, OS, true);
534
20
  case Mips_BGEZAL:
535
    // bgezal $zero, $L1 => bal $L1
536
20
    return isReg(MI, 0, Mips_ZERO) &&
537
0
           printAlias("bal", MI, Address, 1, OS, true);
538
28
  case Mips_BC1T:
539
    // bc1t $fcc0, $L1 => bc1t $L1
540
28
    return isReg(MI, 0, Mips_FCC0) &&
541
0
           printAlias("bc1t", MI, Address, 1, OS, true);
542
29
  case Mips_BC1F:
543
    // bc1f $fcc0, $L1 => bc1f $L1
544
29
    return isReg(MI, 0, Mips_FCC0) &&
545
0
           printAlias("bc1f", MI, Address, 1, OS, true);
546
52
  case Mips_JALR:
547
    // jalr $zero, $r1 => jr $r1
548
    // jalr $ra, $r1 => jalr $r1
549
52
    return (isReg(MI, 0, Mips_ZERO) &&
550
4
      printAlias("jr", MI, Address, 1, OS, false)) ||
551
48
           (isReg(MI, 0, Mips_RA) &&
552
36
      printAlias("jalr", MI, Address, 1, OS, false));
553
0
  case Mips_JALR64:
554
    // jalr $zero, $r1 => jr $r1
555
    // jalr $ra, $r1 => jalr $r1
556
0
    return (isReg(MI, 0, Mips_ZERO_64) &&
557
0
      printAlias("jr", MI, Address, 1, OS, false)) ||
558
0
           (isReg(MI, 0, Mips_RA_64) &&
559
0
      printAlias("jalr", MI, Address, 1, OS, false));
560
57
  case Mips_NOR:
561
108
  case Mips_NOR_MM:
562
112
  case Mips_NOR_MMR6:
563
    // nor $r0, $r1, $zero => not $r0, $r1
564
112
    return isReg(MI, 2, Mips_ZERO) &&
565
62
           printAlias2("not", MI, Address, 0, 1, OS, false);
566
0
  case Mips_NOR64:
567
    // nor $r0, $r1, $zero => not $r0, $r1
568
0
    return isReg(MI, 2, Mips_ZERO_64) &&
569
0
           printAlias2("not", MI, Address, 0, 1, OS, false);
570
64
  case Mips_OR:
571
83
  case Mips_ADDu:
572
    // or $r0, $r1, $zero => move $r0, $r1
573
    // addu $r0, $r1, $zero => move $r0, $r1
574
83
    return isReg(MI, 2, Mips_ZERO) &&
575
18
           printAlias2("move", MI, Address, 0, 1, OS, false);
576
0
  case Mips_LI48_NM:
577
0
  case Mips_LI16_NM:
578
    // li[16/48] $r0, imm => li $r0, imm
579
0
    return printAlias2("li", MI, Address, 0, 1, OS, false);
580
0
  case Mips_ADDIU_NM:
581
0
  case Mips_ADDIUNEG_NM:
582
0
    if (isReg(MI, 1, Mips_ZERO_NM))
583
0
      return printAlias2("li", MI, Address, 0, 2, OS, false);
584
0
    else
585
0
      return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
586
0
  case Mips_ADDIU48_NM:
587
0
  case Mips_ADDIURS5_NM:
588
0
  case Mips_ADDIUR1SP_NM:
589
0
  case Mips_ADDIUR2_NM:
590
0
  case Mips_ADDIUGPB_NM:
591
0
  case Mips_ADDIUGPW_NM:
592
0
    return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
593
0
  case Mips_ANDI16_NM:
594
0
  case Mips_ANDI_NM:
595
    // andi[16/32] $r0, $r1, imm => andi $r0, $r1, imm
596
0
    return printAlias3("andi", MI, Address, 0, 1, 2, OS);
597
34.0k
  default:
598
34.0k
    return false;
599
35.3k
  }
600
35.3k
}
601
602
static void printRegisterList(MCInst *MI, int opNum, SStream *O)
603
356
{
604
  // - 2 because register List is always first operand of instruction and it is
605
  // always followed by memory operand (base + offset).
606
356
  add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum);
607
2.00k
  for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
608
1.64k
    if (i != opNum)
609
1.28k
      SStream_concat0(O, ", ");
610
1.64k
    printRegName(MI, O,
611
1.64k
           MCOperand_getReg(MCInst_getOperand(MI, (i))));
612
1.64k
  }
613
356
}
614
615
static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O)
616
0
{
617
0
  add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum);
618
0
  for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) {
619
0
    SStream_concat0(O, ", ");
620
0
    printRegName(MI, O,
621
0
           MCOperand_getReg(MCInst_getOperand(MI, (I))));
622
0
  }
623
0
}
624
625
static void printHi20(MCInst *MI, int OpNum, SStream *O)
626
0
{
627
0
  MCOperand *MO = MCInst_getOperand(MI, (OpNum));
628
0
  if (MCOperand_isImm(MO)) {
629
0
    add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum);
630
0
    SStream_concat0(O, "%hi(");
631
0
    printUInt64(O, MCOperand_getImm(MO));
632
0
    SStream_concat0(O, ")");
633
0
  } else
634
0
    printOperand(MI, OpNum, O);
635
0
}
636
637
static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
638
0
{
639
0
  MCOperand *MO = MCInst_getOperand(MI, (OpNum));
640
0
  if (MCOperand_isImm(MO)) {
641
0
    add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum);
642
0
    SStream_concat0(O, "%pcrel_hi(");
643
0
    printUInt64(O, MCOperand_getImm(MO) + Address);
644
0
    SStream_concat0(O, ")");
645
0
  } else
646
0
    printOperand(MI, OpNum, O);
647
0
}
648
649
static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
650
0
{
651
0
  MCOperand *MO = MCInst_getOperand(MI, (OpNum));
652
0
  if (MCOperand_isImm(MO)) {
653
0
    add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum);
654
0
    printUInt64(O, MCOperand_getImm(MO) + Address);
655
0
  } else
656
0
    printOperand(MI, OpNum, O);
657
0
}
658
659
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName)
660
74.3k
{
661
74.3k
  if (!RegNo || RegNo >= MIPS_REG_ENDING) {
662
0
    return NULL;
663
0
  }
664
74.3k
  if (noRegName) {
665
0
    return getRegisterName(RegNo);
666
0
  }
667
74.3k
  switch (RegNo) {
668
7.01k
  case MIPS_REG_AT:
669
7.49k
  case MIPS_REG_AT_64:
670
7.49k
    return "at";
671
1.81k
  case MIPS_REG_A0:
672
1.86k
  case MIPS_REG_A0_64:
673
1.86k
    return "a0";
674
1.71k
  case MIPS_REG_A1:
675
1.77k
  case MIPS_REG_A1_64:
676
1.77k
    return "a1";
677
1.42k
  case MIPS_REG_A2:
678
1.59k
  case MIPS_REG_A2_64:
679
1.59k
    return "a2";
680
2.33k
  case MIPS_REG_A3:
681
2.55k
  case MIPS_REG_A3_64:
682
2.55k
    return "a3";
683
327
  case MIPS_REG_K0:
684
370
  case MIPS_REG_K0_64:
685
370
    return "k0";
686
1.13k
  case MIPS_REG_K1:
687
1.59k
  case MIPS_REG_K1_64:
688
1.59k
    return "k1";
689
3.25k
  case MIPS_REG_S0:
690
3.31k
  case MIPS_REG_S0_64:
691
3.31k
    return "s0";
692
1.51k
  case MIPS_REG_S1:
693
1.75k
  case MIPS_REG_S1_64:
694
1.75k
    return "s1";
695
705
  case MIPS_REG_S2:
696
898
  case MIPS_REG_S2_64:
697
898
    return "s2";
698
1.21k
  case MIPS_REG_S3:
699
1.51k
  case MIPS_REG_S3_64:
700
1.51k
    return "s3";
701
1.07k
  case MIPS_REG_S4:
702
1.24k
  case MIPS_REG_S4_64:
703
1.24k
    return "s4";
704
532
  case MIPS_REG_S5:
705
577
  case MIPS_REG_S5_64:
706
577
    return "s5";
707
972
  case MIPS_REG_S6:
708
994
  case MIPS_REG_S6_64:
709
994
    return "s6";
710
726
  case MIPS_REG_S7:
711
777
  case MIPS_REG_S7_64:
712
777
    return "s7";
713
800
  case MIPS_REG_T0:
714
939
  case MIPS_REG_T0_64:
715
939
    return "t0";
716
625
  case MIPS_REG_T1:
717
647
  case MIPS_REG_T1_64:
718
647
    return "t1";
719
776
  case MIPS_REG_T2:
720
811
  case MIPS_REG_T2_64:
721
811
    return "t2";
722
700
  case MIPS_REG_T3:
723
799
  case MIPS_REG_T3_64:
724
799
    return "t3";
725
444
  case MIPS_REG_T4:
726
469
  case MIPS_REG_T4_64:
727
469
    return "t4";
728
974
  case MIPS_REG_T5:
729
1.15k
  case MIPS_REG_T5_64:
730
1.15k
    return "t5";
731
622
  case MIPS_REG_T6:
732
799
  case MIPS_REG_T6_64:
733
799
    return "t6";
734
621
  case MIPS_REG_T7:
735
785
  case MIPS_REG_T7_64:
736
785
    return "t7";
737
1.18k
  case MIPS_REG_T8:
738
1.75k
  case MIPS_REG_T8_64:
739
1.75k
    return "t8";
740
791
  case MIPS_REG_T9:
741
910
  case MIPS_REG_T9_64:
742
910
    return "t9";
743
2.67k
  case MIPS_REG_V0:
744
2.78k
  case MIPS_REG_V0_64:
745
2.78k
    return "v0";
746
1.60k
  case MIPS_REG_V1:
747
1.72k
  case MIPS_REG_V1_64:
748
1.72k
    return "v1";
749
32.4k
  default:
750
32.4k
    return getRegisterName(RegNo);
751
74.3k
  }
752
74.3k
}