Coverage Report

Created: 2025-10-10 06:20

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source
1
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
4
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Do not edit. */
10
11
/* Capstone's LLVM TableGen Backends: */
12
/* https://github.com/capstone-engine/llvm-capstone */
13
14
#include <capstone/platform.h>
15
#include "../../cs_priv.h"
16
17
/// getMnemonic - This method is automatically generated by tablegen
18
/// from the instruction set description.
19
15.5k
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
20
15.5k
#ifndef CAPSTONE_DIET
21
15.5k
  static const char AsmStrs[] = {
22
15.5k
  /* 0 */ "fcmpd %fcc0, \0"
23
15.5k
  /* 14 */ "fcmpq %fcc0, \0"
24
15.5k
  /* 28 */ "fcmps %fcc0, \0"
25
15.5k
  /* 42 */ "rd %wim, \0"
26
15.5k
  /* 52 */ "rdpr %fq, \0"
27
15.5k
  /* 63 */ "rd %tbr, \0"
28
15.5k
  /* 73 */ "rd %psr, \0"
29
15.5k
  /* 83 */ "fsrc1 \0"
30
15.5k
  /* 90 */ "fandnot1 \0"
31
15.5k
  /* 100 */ "fnot1 \0"
32
15.5k
  /* 107 */ "fornot1 \0"
33
15.5k
  /* 116 */ "fsra32 \0"
34
15.5k
  /* 124 */ "fpsub32 \0"
35
15.5k
  /* 133 */ "fpadd32 \0"
36
15.5k
  /* 142 */ "edge32 \0"
37
15.5k
  /* 150 */ "fcmple32 \0"
38
15.5k
  /* 160 */ "fcmpne32 \0"
39
15.5k
  /* 170 */ "fpack32 \0"
40
15.5k
  /* 179 */ "cmask32 \0"
41
15.5k
  /* 188 */ "fsll32 \0"
42
15.5k
  /* 196 */ "fsrl32 \0"
43
15.5k
  /* 204 */ "fcmpeq32 \0"
44
15.5k
  /* 214 */ "fslas32 \0"
45
15.5k
  /* 223 */ "fcmpgt32 \0"
46
15.5k
  /* 233 */ "array32 \0"
47
15.5k
  /* 242 */ "fsrc2 \0"
48
15.5k
  /* 249 */ "fandnot2 \0"
49
15.5k
  /* 259 */ "fnot2 \0"
50
15.5k
  /* 266 */ "fornot2 \0"
51
15.5k
  /* 275 */ "fpadd64 \0"
52
15.5k
  /* 284 */ "fsra16 \0"
53
15.5k
  /* 292 */ "fpsub16 \0"
54
15.5k
  /* 301 */ "fpadd16 \0"
55
15.5k
  /* 310 */ "edge16 \0"
56
15.5k
  /* 318 */ "fcmple16 \0"
57
15.5k
  /* 328 */ "fcmpne16 \0"
58
15.5k
  /* 338 */ "fpack16 \0"
59
15.5k
  /* 347 */ "cmask16 \0"
60
15.5k
  /* 356 */ "fsll16 \0"
61
15.5k
  /* 364 */ "fsrl16 \0"
62
15.5k
  /* 372 */ "fchksm16 \0"
63
15.5k
  /* 382 */ "fmean16 \0"
64
15.5k
  /* 391 */ "fcmpeq16 \0"
65
15.5k
  /* 401 */ "fslas16 \0"
66
15.5k
  /* 410 */ "fcmpgt16 \0"
67
15.5k
  /* 420 */ "fmul8x16 \0"
68
15.5k
  /* 430 */ "fmuld8ulx16 \0"
69
15.5k
  /* 443 */ "fmul8ulx16 \0"
70
15.5k
  /* 455 */ "fmuld8sux16 \0"
71
15.5k
  /* 468 */ "fmul8sux16 \0"
72
15.5k
  /* 480 */ "array16 \0"
73
15.5k
  /* 489 */ "edge8 \0"
74
15.5k
  /* 496 */ "cmask8 \0"
75
15.5k
  /* 504 */ "array8 \0"
76
15.5k
  /* 512 */ "!ADJCALLSTACKDOWN \0"
77
15.5k
  /* 531 */ "!ADJCALLSTACKUP \0"
78
15.5k
  /* 548 */ "stba \0"
79
15.5k
  /* 554 */ "stda \0"
80
15.5k
  /* 560 */ "stha \0"
81
15.5k
  /* 566 */ "stqa \0"
82
15.5k
  /* 572 */ "sra \0"
83
15.5k
  /* 577 */ "faligndata \0"
84
15.5k
  /* 589 */ "sta \0"
85
15.5k
  /* 594 */ "stxa \0"
86
15.5k
  /* 600 */ "stb \0"
87
15.5k
  /* 605 */ "sub \0"
88
15.5k
  /* 610 */ "smac \0"
89
15.5k
  /* 616 */ "umac \0"
90
15.5k
  /* 622 */ "tsubcc \0"
91
15.5k
  /* 630 */ "addxccc \0"
92
15.5k
  /* 639 */ "taddcc \0"
93
15.5k
  /* 647 */ "andcc \0"
94
15.5k
  /* 654 */ "smulcc \0"
95
15.5k
  /* 662 */ "umulcc \0"
96
15.5k
  /* 670 */ "andncc \0"
97
15.5k
  /* 678 */ "orncc \0"
98
15.5k
  /* 685 */ "xnorcc \0"
99
15.5k
  /* 693 */ "xorcc \0"
100
15.5k
  /* 700 */ "mulscc \0"
101
15.5k
  /* 708 */ "sdivcc \0"
102
15.5k
  /* 716 */ "udivcc \0"
103
15.5k
  /* 724 */ "subxcc \0"
104
15.5k
  /* 732 */ "addxcc \0"
105
15.5k
  /* 740 */ "popc \0"
106
15.5k
  /* 746 */ "addxc \0"
107
15.5k
  /* 753 */ "fsubd \0"
108
15.5k
  /* 760 */ "fhsubd \0"
109
15.5k
  /* 768 */ "add \0"
110
15.5k
  /* 773 */ "faddd \0"
111
15.5k
  /* 780 */ "fhaddd \0"
112
15.5k
  /* 788 */ "fnhaddd \0"
113
15.5k
  /* 797 */ "fnaddd \0"
114
15.5k
  /* 805 */ "fcmped \0"
115
15.5k
  /* 813 */ "fnegd \0"
116
15.5k
  /* 820 */ "fmuld \0"
117
15.5k
  /* 827 */ "fnmuld \0"
118
15.5k
  /* 835 */ "fsmuld \0"
119
15.5k
  /* 843 */ "fnsmuld \0"
120
15.5k
  /* 852 */ "fand \0"
121
15.5k
  /* 858 */ "fnand \0"
122
15.5k
  /* 865 */ "fexpand \0"
123
15.5k
  /* 874 */ "fitod \0"
124
15.5k
  /* 881 */ "fqtod \0"
125
15.5k
  /* 888 */ "fstod \0"
126
15.5k
  /* 895 */ "fxtod \0"
127
15.5k
  /* 902 */ "movxtod \0"
128
15.5k
  /* 911 */ "fcmpd \0"
129
15.5k
  /* 918 */ "flcmpd \0"
130
15.5k
  /* 926 */ "rd \0"
131
15.5k
  /* 930 */ "fabsd \0"
132
15.5k
  /* 937 */ "fsqrtd \0"
133
15.5k
  /* 945 */ "std \0"
134
15.5k
  /* 950 */ "fdivd \0"
135
15.5k
  /* 957 */ "fmovd \0"
136
15.5k
  /* 964 */ "fpmerge \0"
137
15.5k
  /* 973 */ "bshuffle \0"
138
15.5k
  /* 983 */ "fone \0"
139
15.5k
  /* 989 */ "restore \0"
140
15.5k
  /* 998 */ "save \0"
141
15.5k
  /* 1004 */ "flush \0"
142
15.5k
  /* 1011 */ "sth \0"
143
15.5k
  /* 1016 */ "sethi \0"
144
15.5k
  /* 1023 */ "umulxhi \0"
145
15.5k
  /* 1032 */ "xmulxhi \0"
146
15.5k
  /* 1041 */ "fdtoi \0"
147
15.5k
  /* 1048 */ "fqtoi \0"
148
15.5k
  /* 1055 */ "fstoi \0"
149
15.5k
  /* 1062 */ "bmask \0"
150
15.5k
  /* 1069 */ "edge32l \0"
151
15.5k
  /* 1078 */ "edge16l \0"
152
15.5k
  /* 1087 */ "edge8l \0"
153
15.5k
  /* 1095 */ "fmul8x16al \0"
154
15.5k
  /* 1107 */ "call \0"
155
15.5k
  /* 1113 */ "sll \0"
156
15.5k
  /* 1118 */ "jmpl \0"
157
15.5k
  /* 1124 */ "alignaddrl \0"
158
15.5k
  /* 1136 */ "srl \0"
159
15.5k
  /* 1141 */ "smul \0"
160
15.5k
  /* 1147 */ "umul \0"
161
15.5k
  /* 1153 */ "edge32n \0"
162
15.5k
  /* 1162 */ "edge16n \0"
163
15.5k
  /* 1171 */ "edge8n \0"
164
15.5k
  /* 1179 */ "andn \0"
165
15.5k
  /* 1185 */ "edge32ln \0"
166
15.5k
  /* 1195 */ "edge16ln \0"
167
15.5k
  /* 1205 */ "edge8ln \0"
168
15.5k
  /* 1214 */ "orn \0"
169
15.5k
  /* 1219 */ "pdistn \0"
170
15.5k
  /* 1227 */ "fzero \0"
171
15.5k
  /* 1234 */ "unimp \0"
172
15.5k
  /* 1241 */ "jmp \0"
173
15.5k
  /* 1246 */ "fsubq \0"
174
15.5k
  /* 1253 */ "faddq \0"
175
15.5k
  /* 1260 */ "fcmpeq \0"
176
15.5k
  /* 1268 */ "fnegq \0"
177
15.5k
  /* 1275 */ "fdmulq \0"
178
15.5k
  /* 1283 */ "fmulq \0"
179
15.5k
  /* 1290 */ "fdtoq \0"
180
15.5k
  /* 1297 */ "fitoq \0"
181
15.5k
  /* 1304 */ "fstoq \0"
182
15.5k
  /* 1311 */ "fxtoq \0"
183
15.5k
  /* 1318 */ "fcmpq \0"
184
15.5k
  /* 1325 */ "fabsq \0"
185
15.5k
  /* 1332 */ "fsqrtq \0"
186
15.5k
  /* 1340 */ "stq \0"
187
15.5k
  /* 1345 */ "fdivq \0"
188
15.5k
  /* 1352 */ "fmovq \0"
189
15.5k
  /* 1359 */ "membar \0"
190
15.5k
  /* 1367 */ "alignaddr \0"
191
15.5k
  /* 1378 */ "sir \0"
192
15.5k
  /* 1383 */ "for \0"
193
15.5k
  /* 1388 */ "fnor \0"
194
15.5k
  /* 1394 */ "fxnor \0"
195
15.5k
  /* 1401 */ "fxor \0"
196
15.5k
  /* 1407 */ "rdpr \0"
197
15.5k
  /* 1413 */ "wrpr \0"
198
15.5k
  /* 1419 */ "pwr \0"
199
15.5k
  /* 1424 */ "fsrc1s \0"
200
15.5k
  /* 1432 */ "fandnot1s \0"
201
15.5k
  /* 1443 */ "fnot1s \0"
202
15.5k
  /* 1451 */ "fornot1s \0"
203
15.5k
  /* 1461 */ "fpsub32s \0"
204
15.5k
  /* 1471 */ "fpadd32s \0"
205
15.5k
  /* 1481 */ "fsrc2s \0"
206
15.5k
  /* 1489 */ "fandnot2s \0"
207
15.5k
  /* 1500 */ "fnot2s \0"
208
15.5k
  /* 1508 */ "fornot2s \0"
209
15.5k
  /* 1518 */ "fpsub16s \0"
210
15.5k
  /* 1528 */ "fpadd16s \0"
211
15.5k
  /* 1538 */ "fsubs \0"
212
15.5k
  /* 1545 */ "fhsubs \0"
213
15.5k
  /* 1553 */ "fadds \0"
214
15.5k
  /* 1560 */ "fhadds \0"
215
15.5k
  /* 1568 */ "fnhadds \0"
216
15.5k
  /* 1577 */ "fnadds \0"
217
15.5k
  /* 1585 */ "fands \0"
218
15.5k
  /* 1592 */ "fnands \0"
219
15.5k
  /* 1600 */ "fones \0"
220
15.5k
  /* 1607 */ "fcmpes \0"
221
15.5k
  /* 1615 */ "fnegs \0"
222
15.5k
  /* 1622 */ "fmuls \0"
223
15.5k
  /* 1629 */ "fnmuls \0"
224
15.5k
  /* 1637 */ "fzeros \0"
225
15.5k
  /* 1645 */ "fdtos \0"
226
15.5k
  /* 1652 */ "fitos \0"
227
15.5k
  /* 1659 */ "fqtos \0"
228
15.5k
  /* 1666 */ "movwtos \0"
229
15.5k
  /* 1675 */ "fxtos \0"
230
15.5k
  /* 1682 */ "fcmps \0"
231
15.5k
  /* 1689 */ "flcmps \0"
232
15.5k
  /* 1697 */ "fors \0"
233
15.5k
  /* 1703 */ "fnors \0"
234
15.5k
  /* 1710 */ "fxnors \0"
235
15.5k
  /* 1718 */ "fxors \0"
236
15.5k
  /* 1725 */ "fabss \0"
237
15.5k
  /* 1732 */ "fsqrts \0"
238
15.5k
  /* 1740 */ "fdivs \0"
239
15.5k
  /* 1747 */ "fmovs \0"
240
15.5k
  /* 1754 */ "set \0"
241
15.5k
  /* 1759 */ "lzcnt \0"
242
15.5k
  /* 1766 */ "pdist \0"
243
15.5k
  /* 1773 */ "rett \0"
244
15.5k
  /* 1779 */ "fmul8x16au \0"
245
15.5k
  /* 1791 */ "sdiv \0"
246
15.5k
  /* 1797 */ "udiv \0"
247
15.5k
  /* 1803 */ "tsubcctv \0"
248
15.5k
  /* 1813 */ "taddcctv \0"
249
15.5k
  /* 1823 */ "movstosw \0"
250
15.5k
  /* 1833 */ "movstouw \0"
251
15.5k
  /* 1843 */ "srax \0"
252
15.5k
  /* 1849 */ "subx \0"
253
15.5k
  /* 1855 */ "addx \0"
254
15.5k
  /* 1861 */ "fpackfix \0"
255
15.5k
  /* 1871 */ "sllx \0"
256
15.5k
  /* 1877 */ "srlx \0"
257
15.5k
  /* 1883 */ "xmulx \0"
258
15.5k
  /* 1890 */ "fdtox \0"
259
15.5k
  /* 1897 */ "movdtox \0"
260
15.5k
  /* 1906 */ "fqtox \0"
261
15.5k
  /* 1913 */ "fstox \0"
262
15.5k
  /* 1920 */ "setx \0"
263
15.5k
  /* 1926 */ "stx \0"
264
15.5k
  /* 1931 */ "sdivx \0"
265
15.5k
  /* 1938 */ "udivx \0"
266
15.5k
  /* 1945 */ "; SELECT_CC_DFP_FCC PSEUDO!\0"
267
15.5k
  /* 1973 */ "; SELECT_CC_QFP_FCC PSEUDO!\0"
268
15.5k
  /* 2001 */ "; SELECT_CC_FP_FCC PSEUDO!\0"
269
15.5k
  /* 2028 */ "; SELECT_CC_Int_FCC PSEUDO!\0"
270
15.5k
  /* 2056 */ "; SELECT_CC_DFP_ICC PSEUDO!\0"
271
15.5k
  /* 2084 */ "; SELECT_CC_QFP_ICC PSEUDO!\0"
272
15.5k
  /* 2112 */ "; SELECT_CC_FP_ICC PSEUDO!\0"
273
15.5k
  /* 2139 */ "; SELECT_CC_Int_ICC PSEUDO!\0"
274
15.5k
  /* 2167 */ "; SELECT_CC_DFP_XCC PSEUDO!\0"
275
15.5k
  /* 2195 */ "; SELECT_CC_QFP_XCC PSEUDO!\0"
276
15.5k
  /* 2223 */ "; SELECT_CC_FP_XCC PSEUDO!\0"
277
15.5k
  /* 2250 */ "; SELECT_CC_Int_XCC PSEUDO!\0"
278
15.5k
  /* 2278 */ "jmp %i7+\0"
279
15.5k
  /* 2287 */ "jmp %o7+\0"
280
15.5k
  /* 2296 */ "# XRay Function Patchable RET.\0"
281
15.5k
  /* 2327 */ "# XRay Typed Event Log.\0"
282
15.5k
  /* 2351 */ "# XRay Custom Event Log.\0"
283
15.5k
  /* 2376 */ "# XRay Function Enter.\0"
284
15.5k
  /* 2399 */ "# XRay Tail Call Exit.\0"
285
15.5k
  /* 2422 */ "# XRay Function Exit.\0"
286
15.5k
  /* 2444 */ "flush %g0\0"
287
15.5k
  /* 2454 */ "ta 1\0"
288
15.5k
  /* 2459 */ "ta 3\0"
289
15.5k
  /* 2464 */ "ta 5\0"
290
15.5k
  /* 2469 */ "LIFETIME_END\0"
291
15.5k
  /* 2482 */ "PSEUDO_PROBE\0"
292
15.5k
  /* 2495 */ "BUNDLE\0"
293
15.5k
  /* 2502 */ "DBG_VALUE\0"
294
15.5k
  /* 2512 */ "DBG_INSTR_REF\0"
295
15.5k
  /* 2526 */ "DBG_PHI\0"
296
15.5k
  /* 2534 */ "DBG_LABEL\0"
297
15.5k
  /* 2544 */ "LIFETIME_START\0"
298
15.5k
  /* 2559 */ "DBG_VALUE_LIST\0"
299
15.5k
  /* 2574 */ "std %cq, [\0"
300
15.5k
  /* 2585 */ "std %fq, [\0"
301
15.5k
  /* 2596 */ "st %csr, [\0"
302
15.5k
  /* 2607 */ "st %fsr, [\0"
303
15.5k
  /* 2618 */ "stx %fsr, [\0"
304
15.5k
  /* 2630 */ "ldsba [\0"
305
15.5k
  /* 2638 */ "lduba [\0"
306
15.5k
  /* 2646 */ "ldstuba [\0"
307
15.5k
  /* 2656 */ "ldda [\0"
308
15.5k
  /* 2663 */ "lda [\0"
309
15.5k
  /* 2669 */ "ldsha [\0"
310
15.5k
  /* 2677 */ "lduha [\0"
311
15.5k
  /* 2685 */ "swapa [\0"
312
15.5k
  /* 2693 */ "ldqa [\0"
313
15.5k
  /* 2700 */ "casa [\0"
314
15.5k
  /* 2707 */ "ldswa [\0"
315
15.5k
  /* 2715 */ "ldxa [\0"
316
15.5k
  /* 2722 */ "casxa [\0"
317
15.5k
  /* 2730 */ "ldsb [\0"
318
15.5k
  /* 2737 */ "ldub [\0"
319
15.5k
  /* 2744 */ "ldstub [\0"
320
15.5k
  /* 2753 */ "ldd [\0"
321
15.5k
  /* 2759 */ "ld [\0"
322
15.5k
  /* 2764 */ "prefetch [\0"
323
15.5k
  /* 2775 */ "ldsh [\0"
324
15.5k
  /* 2782 */ "lduh [\0"
325
15.5k
  /* 2789 */ "swap [\0"
326
15.5k
  /* 2796 */ "ldq [\0"
327
15.5k
  /* 2802 */ "ldsw [\0"
328
15.5k
  /* 2809 */ "ldx [\0"
329
15.5k
  /* 2815 */ "cb\0"
330
15.5k
  /* 2818 */ "fb\0"
331
15.5k
  /* 2821 */ "restored\0"
332
15.5k
  /* 2830 */ "saved\0"
333
15.5k
  /* 2836 */ "fmovrd\0"
334
15.5k
  /* 2843 */ "fmovd\0"
335
15.5k
  /* 2849 */ "done\0"
336
15.5k
  /* 2854 */ "# FEntry call\0"
337
15.5k
  /* 2868 */ "siam\0"
338
15.5k
  /* 2873 */ "shutdown\0"
339
15.5k
  /* 2882 */ "nop\0"
340
15.5k
  /* 2886 */ "fmovrq\0"
341
15.5k
  /* 2893 */ "fmovq\0"
342
15.5k
  /* 2899 */ "stbar\0"
343
15.5k
  /* 2905 */ "br\0"
344
15.5k
  /* 2908 */ "movr\0"
345
15.5k
  /* 2913 */ "fmovrs\0"
346
15.5k
  /* 2920 */ "fmovs\0"
347
15.5k
  /* 2926 */ "t\0"
348
15.5k
  /* 2928 */ "mov\0"
349
15.5k
  /* 2932 */ "flushw\0"
350
15.5k
  /* 2939 */ "retry\0"
351
15.5k
};
352
15.5k
#endif // CAPSTONE_DIET
353
354
15.5k
  static const uint32_t OpInfo0[] = {
355
15.5k
    0U, // PHI
356
15.5k
    0U, // INLINEASM
357
15.5k
    0U, // INLINEASM_BR
358
15.5k
    0U, // CFI_INSTRUCTION
359
15.5k
    0U, // EH_LABEL
360
15.5k
    0U, // GC_LABEL
361
15.5k
    0U, // ANNOTATION_LABEL
362
15.5k
    0U, // KILL
363
15.5k
    0U, // EXTRACT_SUBREG
364
15.5k
    0U, // INSERT_SUBREG
365
15.5k
    0U, // IMPLICIT_DEF
366
15.5k
    0U, // SUBREG_TO_REG
367
15.5k
    0U, // COPY_TO_REGCLASS
368
15.5k
    2503U,  // DBG_VALUE
369
15.5k
    2560U,  // DBG_VALUE_LIST
370
15.5k
    2513U,  // DBG_INSTR_REF
371
15.5k
    2527U,  // DBG_PHI
372
15.5k
    2535U,  // DBG_LABEL
373
15.5k
    0U, // REG_SEQUENCE
374
15.5k
    0U, // COPY
375
15.5k
    2496U,  // BUNDLE
376
15.5k
    2545U,  // LIFETIME_START
377
15.5k
    2470U,  // LIFETIME_END
378
15.5k
    2483U,  // PSEUDO_PROBE
379
15.5k
    0U, // ARITH_FENCE
380
15.5k
    0U, // STACKMAP
381
15.5k
    2855U,  // FENTRY_CALL
382
15.5k
    0U, // PATCHPOINT
383
15.5k
    0U, // LOAD_STACK_GUARD
384
15.5k
    0U, // PREALLOCATED_SETUP
385
15.5k
    0U, // PREALLOCATED_ARG
386
15.5k
    0U, // STATEPOINT
387
15.5k
    0U, // LOCAL_ESCAPE
388
15.5k
    0U, // FAULTING_OP
389
15.5k
    0U, // PATCHABLE_OP
390
15.5k
    2377U,  // PATCHABLE_FUNCTION_ENTER
391
15.5k
    2297U,  // PATCHABLE_RET
392
15.5k
    2423U,  // PATCHABLE_FUNCTION_EXIT
393
15.5k
    2400U,  // PATCHABLE_TAIL_CALL
394
15.5k
    2352U,  // PATCHABLE_EVENT_CALL
395
15.5k
    2328U,  // PATCHABLE_TYPED_EVENT_CALL
396
15.5k
    0U, // ICALL_BRANCH_FUNNEL
397
15.5k
    0U, // MEMBARRIER
398
15.5k
    0U, // JUMP_TABLE_DEBUG_INFO
399
15.5k
    0U, // G_ASSERT_SEXT
400
15.5k
    0U, // G_ASSERT_ZEXT
401
15.5k
    0U, // G_ASSERT_ALIGN
402
15.5k
    0U, // G_ADD
403
15.5k
    0U, // G_SUB
404
15.5k
    0U, // G_MUL
405
15.5k
    0U, // G_SDIV
406
15.5k
    0U, // G_UDIV
407
15.5k
    0U, // G_SREM
408
15.5k
    0U, // G_UREM
409
15.5k
    0U, // G_SDIVREM
410
15.5k
    0U, // G_UDIVREM
411
15.5k
    0U, // G_AND
412
15.5k
    0U, // G_OR
413
15.5k
    0U, // G_XOR
414
15.5k
    0U, // G_IMPLICIT_DEF
415
15.5k
    0U, // G_PHI
416
15.5k
    0U, // G_FRAME_INDEX
417
15.5k
    0U, // G_GLOBAL_VALUE
418
15.5k
    0U, // G_CONSTANT_POOL
419
15.5k
    0U, // G_EXTRACT
420
15.5k
    0U, // G_UNMERGE_VALUES
421
15.5k
    0U, // G_INSERT
422
15.5k
    0U, // G_MERGE_VALUES
423
15.5k
    0U, // G_BUILD_VECTOR
424
15.5k
    0U, // G_BUILD_VECTOR_TRUNC
425
15.5k
    0U, // G_CONCAT_VECTORS
426
15.5k
    0U, // G_PTRTOINT
427
15.5k
    0U, // G_INTTOPTR
428
15.5k
    0U, // G_BITCAST
429
15.5k
    0U, // G_FREEZE
430
15.5k
    0U, // G_CONSTANT_FOLD_BARRIER
431
15.5k
    0U, // G_INTRINSIC_FPTRUNC_ROUND
432
15.5k
    0U, // G_INTRINSIC_TRUNC
433
15.5k
    0U, // G_INTRINSIC_ROUND
434
15.5k
    0U, // G_INTRINSIC_LRINT
435
15.5k
    0U, // G_INTRINSIC_ROUNDEVEN
436
15.5k
    0U, // G_READCYCLECOUNTER
437
15.5k
    0U, // G_LOAD
438
15.5k
    0U, // G_SEXTLOAD
439
15.5k
    0U, // G_ZEXTLOAD
440
15.5k
    0U, // G_INDEXED_LOAD
441
15.5k
    0U, // G_INDEXED_SEXTLOAD
442
15.5k
    0U, // G_INDEXED_ZEXTLOAD
443
15.5k
    0U, // G_STORE
444
15.5k
    0U, // G_INDEXED_STORE
445
15.5k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
446
15.5k
    0U, // G_ATOMIC_CMPXCHG
447
15.5k
    0U, // G_ATOMICRMW_XCHG
448
15.5k
    0U, // G_ATOMICRMW_ADD
449
15.5k
    0U, // G_ATOMICRMW_SUB
450
15.5k
    0U, // G_ATOMICRMW_AND
451
15.5k
    0U, // G_ATOMICRMW_NAND
452
15.5k
    0U, // G_ATOMICRMW_OR
453
15.5k
    0U, // G_ATOMICRMW_XOR
454
15.5k
    0U, // G_ATOMICRMW_MAX
455
15.5k
    0U, // G_ATOMICRMW_MIN
456
15.5k
    0U, // G_ATOMICRMW_UMAX
457
15.5k
    0U, // G_ATOMICRMW_UMIN
458
15.5k
    0U, // G_ATOMICRMW_FADD
459
15.5k
    0U, // G_ATOMICRMW_FSUB
460
15.5k
    0U, // G_ATOMICRMW_FMAX
461
15.5k
    0U, // G_ATOMICRMW_FMIN
462
15.5k
    0U, // G_ATOMICRMW_UINC_WRAP
463
15.5k
    0U, // G_ATOMICRMW_UDEC_WRAP
464
15.5k
    0U, // G_FENCE
465
15.5k
    0U, // G_PREFETCH
466
15.5k
    0U, // G_BRCOND
467
15.5k
    0U, // G_BRINDIRECT
468
15.5k
    0U, // G_INVOKE_REGION_START
469
15.5k
    0U, // G_INTRINSIC
470
15.5k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
471
15.5k
    0U, // G_INTRINSIC_CONVERGENT
472
15.5k
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
473
15.5k
    0U, // G_ANYEXT
474
15.5k
    0U, // G_TRUNC
475
15.5k
    0U, // G_CONSTANT
476
15.5k
    0U, // G_FCONSTANT
477
15.5k
    0U, // G_VASTART
478
15.5k
    0U, // G_VAARG
479
15.5k
    0U, // G_SEXT
480
15.5k
    0U, // G_SEXT_INREG
481
15.5k
    0U, // G_ZEXT
482
15.5k
    0U, // G_SHL
483
15.5k
    0U, // G_LSHR
484
15.5k
    0U, // G_ASHR
485
15.5k
    0U, // G_FSHL
486
15.5k
    0U, // G_FSHR
487
15.5k
    0U, // G_ROTR
488
15.5k
    0U, // G_ROTL
489
15.5k
    0U, // G_ICMP
490
15.5k
    0U, // G_FCMP
491
15.5k
    0U, // G_SELECT
492
15.5k
    0U, // G_UADDO
493
15.5k
    0U, // G_UADDE
494
15.5k
    0U, // G_USUBO
495
15.5k
    0U, // G_USUBE
496
15.5k
    0U, // G_SADDO
497
15.5k
    0U, // G_SADDE
498
15.5k
    0U, // G_SSUBO
499
15.5k
    0U, // G_SSUBE
500
15.5k
    0U, // G_UMULO
501
15.5k
    0U, // G_SMULO
502
15.5k
    0U, // G_UMULH
503
15.5k
    0U, // G_SMULH
504
15.5k
    0U, // G_UADDSAT
505
15.5k
    0U, // G_SADDSAT
506
15.5k
    0U, // G_USUBSAT
507
15.5k
    0U, // G_SSUBSAT
508
15.5k
    0U, // G_USHLSAT
509
15.5k
    0U, // G_SSHLSAT
510
15.5k
    0U, // G_SMULFIX
511
15.5k
    0U, // G_UMULFIX
512
15.5k
    0U, // G_SMULFIXSAT
513
15.5k
    0U, // G_UMULFIXSAT
514
15.5k
    0U, // G_SDIVFIX
515
15.5k
    0U, // G_UDIVFIX
516
15.5k
    0U, // G_SDIVFIXSAT
517
15.5k
    0U, // G_UDIVFIXSAT
518
15.5k
    0U, // G_FADD
519
15.5k
    0U, // G_FSUB
520
15.5k
    0U, // G_FMUL
521
15.5k
    0U, // G_FMA
522
15.5k
    0U, // G_FMAD
523
15.5k
    0U, // G_FDIV
524
15.5k
    0U, // G_FREM
525
15.5k
    0U, // G_FPOW
526
15.5k
    0U, // G_FPOWI
527
15.5k
    0U, // G_FEXP
528
15.5k
    0U, // G_FEXP2
529
15.5k
    0U, // G_FEXP10
530
15.5k
    0U, // G_FLOG
531
15.5k
    0U, // G_FLOG2
532
15.5k
    0U, // G_FLOG10
533
15.5k
    0U, // G_FLDEXP
534
15.5k
    0U, // G_FFREXP
535
15.5k
    0U, // G_FNEG
536
15.5k
    0U, // G_FPEXT
537
15.5k
    0U, // G_FPTRUNC
538
15.5k
    0U, // G_FPTOSI
539
15.5k
    0U, // G_FPTOUI
540
15.5k
    0U, // G_SITOFP
541
15.5k
    0U, // G_UITOFP
542
15.5k
    0U, // G_FABS
543
15.5k
    0U, // G_FCOPYSIGN
544
15.5k
    0U, // G_IS_FPCLASS
545
15.5k
    0U, // G_FCANONICALIZE
546
15.5k
    0U, // G_FMINNUM
547
15.5k
    0U, // G_FMAXNUM
548
15.5k
    0U, // G_FMINNUM_IEEE
549
15.5k
    0U, // G_FMAXNUM_IEEE
550
15.5k
    0U, // G_FMINIMUM
551
15.5k
    0U, // G_FMAXIMUM
552
15.5k
    0U, // G_GET_FPENV
553
15.5k
    0U, // G_SET_FPENV
554
15.5k
    0U, // G_RESET_FPENV
555
15.5k
    0U, // G_GET_FPMODE
556
15.5k
    0U, // G_SET_FPMODE
557
15.5k
    0U, // G_RESET_FPMODE
558
15.5k
    0U, // G_PTR_ADD
559
15.5k
    0U, // G_PTRMASK
560
15.5k
    0U, // G_SMIN
561
15.5k
    0U, // G_SMAX
562
15.5k
    0U, // G_UMIN
563
15.5k
    0U, // G_UMAX
564
15.5k
    0U, // G_ABS
565
15.5k
    0U, // G_LROUND
566
15.5k
    0U, // G_LLROUND
567
15.5k
    0U, // G_BR
568
15.5k
    0U, // G_BRJT
569
15.5k
    0U, // G_INSERT_VECTOR_ELT
570
15.5k
    0U, // G_EXTRACT_VECTOR_ELT
571
15.5k
    0U, // G_SHUFFLE_VECTOR
572
15.5k
    0U, // G_CTTZ
573
15.5k
    0U, // G_CTTZ_ZERO_UNDEF
574
15.5k
    0U, // G_CTLZ
575
15.5k
    0U, // G_CTLZ_ZERO_UNDEF
576
15.5k
    0U, // G_CTPOP
577
15.5k
    0U, // G_BSWAP
578
15.5k
    0U, // G_BITREVERSE
579
15.5k
    0U, // G_FCEIL
580
15.5k
    0U, // G_FCOS
581
15.5k
    0U, // G_FSIN
582
15.5k
    0U, // G_FSQRT
583
15.5k
    0U, // G_FFLOOR
584
15.5k
    0U, // G_FRINT
585
15.5k
    0U, // G_FNEARBYINT
586
15.5k
    0U, // G_ADDRSPACE_CAST
587
15.5k
    0U, // G_BLOCK_ADDR
588
15.5k
    0U, // G_JUMP_TABLE
589
15.5k
    0U, // G_DYN_STACKALLOC
590
15.5k
    0U, // G_STACKSAVE
591
15.5k
    0U, // G_STACKRESTORE
592
15.5k
    0U, // G_STRICT_FADD
593
15.5k
    0U, // G_STRICT_FSUB
594
15.5k
    0U, // G_STRICT_FMUL
595
15.5k
    0U, // G_STRICT_FDIV
596
15.5k
    0U, // G_STRICT_FREM
597
15.5k
    0U, // G_STRICT_FMA
598
15.5k
    0U, // G_STRICT_FSQRT
599
15.5k
    0U, // G_STRICT_FLDEXP
600
15.5k
    0U, // G_READ_REGISTER
601
15.5k
    0U, // G_WRITE_REGISTER
602
15.5k
    0U, // G_MEMCPY
603
15.5k
    0U, // G_MEMCPY_INLINE
604
15.5k
    0U, // G_MEMMOVE
605
15.5k
    0U, // G_MEMSET
606
15.5k
    0U, // G_BZERO
607
15.5k
    0U, // G_VECREDUCE_SEQ_FADD
608
15.5k
    0U, // G_VECREDUCE_SEQ_FMUL
609
15.5k
    0U, // G_VECREDUCE_FADD
610
15.5k
    0U, // G_VECREDUCE_FMUL
611
15.5k
    0U, // G_VECREDUCE_FMAX
612
15.5k
    0U, // G_VECREDUCE_FMIN
613
15.5k
    0U, // G_VECREDUCE_FMAXIMUM
614
15.5k
    0U, // G_VECREDUCE_FMINIMUM
615
15.5k
    0U, // G_VECREDUCE_ADD
616
15.5k
    0U, // G_VECREDUCE_MUL
617
15.5k
    0U, // G_VECREDUCE_AND
618
15.5k
    0U, // G_VECREDUCE_OR
619
15.5k
    0U, // G_VECREDUCE_XOR
620
15.5k
    0U, // G_VECREDUCE_SMAX
621
15.5k
    0U, // G_VECREDUCE_SMIN
622
15.5k
    0U, // G_VECREDUCE_UMAX
623
15.5k
    0U, // G_VECREDUCE_UMIN
624
15.5k
    0U, // G_SBFX
625
15.5k
    0U, // G_UBFX
626
15.5k
    4609U,  // ADJCALLSTACKDOWN
627
15.5k
    70164U, // ADJCALLSTACKUP
628
15.5k
    8206U,  // GETPCX
629
15.5k
    1946U,  // SELECT_CC_DFP_FCC
630
15.5k
    2057U,  // SELECT_CC_DFP_ICC
631
15.5k
    2168U,  // SELECT_CC_DFP_XCC
632
15.5k
    2002U,  // SELECT_CC_FP_FCC
633
15.5k
    2113U,  // SELECT_CC_FP_ICC
634
15.5k
    2224U,  // SELECT_CC_FP_XCC
635
15.5k
    2029U,  // SELECT_CC_Int_FCC
636
15.5k
    2140U,  // SELECT_CC_Int_ICC
637
15.5k
    2251U,  // SELECT_CC_Int_XCC
638
15.5k
    1974U,  // SELECT_CC_QFP_FCC
639
15.5k
    2085U,  // SELECT_CC_QFP_ICC
640
15.5k
    2196U,  // SELECT_CC_QFP_XCC
641
15.5k
    2111195U, // SET
642
15.5k
    20985729U,  // SETX
643
15.5k
    20984449U,  // ADDCCri
644
15.5k
    20984449U,  // ADDCCrr
645
15.5k
    20985664U,  // ADDCri
646
15.5k
    20985664U,  // ADDCrr
647
15.5k
    20984541U,  // ADDEri
648
15.5k
    20984541U,  // ADDErr
649
15.5k
    20984555U,  // ADDXC
650
15.5k
    20984439U,  // ADDXCCC
651
15.5k
    20984577U,  // ADDri
652
15.5k
    20984577U,  // ADDrr
653
15.5k
    20985176U,  // ALIGNADDR
654
15.5k
    20984933U,  // ALIGNADDRL
655
15.5k
    20984456U,  // ANDCCri
656
15.5k
    20984456U,  // ANDCCrr
657
15.5k
    20984479U,  // ANDNCCri
658
15.5k
    20984479U,  // ANDNCCrr
659
15.5k
    20984988U,  // ANDNri
660
15.5k
    20984988U,  // ANDNrr
661
15.5k
    20984662U,  // ANDri
662
15.5k
    20984662U,  // ANDrr
663
15.5k
    20984289U,  // ARRAY16
664
15.5k
    20984042U,  // ARRAY32
665
15.5k
    20984313U,  // ARRAY8
666
15.5k
    2247425U, // BCOND
667
15.5k
    2312961U, // BCONDA
668
15.5k
    87258U, // BINDri
669
15.5k
    87258U, // BINDrr
670
15.5k
    20984871U,  // BMASK
671
15.5k
    21121795U,  // BPFCC
672
15.5k
    21187331U,  // BPFCCA
673
15.5k
    281347U,  // BPFCCANT
674
15.5k
    346883U,  // BPFCCNT
675
15.5k
    2509569U, // BPICC
676
15.5k
    477953U,  // BPICCA
677
15.5k
    543489U,  // BPICCANT
678
15.5k
    609025U,  // BPICCNT
679
15.5k
    21121882U,  // BPR
680
15.5k
    21187418U,  // BPRA
681
15.5k
    281434U,  // BPRANT
682
15.5k
    346970U,  // BPRNT
683
15.5k
    2771713U, // BPXCC
684
15.5k
    740097U,  // BPXCCA
685
15.5k
    805633U,  // BPXCCANT
686
15.5k
    871169U,  // BPXCCNT
687
15.5k
    20984782U,  // BSHUFFLE
688
15.5k
    70740U, // CALL
689
15.5k
    87124U, // CALLri
690
15.5k
    87124U, // CALLrr
691
15.5k
    21904013U,  // CASAri
692
15.5k
    7289485U, // CASArr
693
15.5k
    21904035U,  // CASXAri
694
15.5k
    7289507U, // CASXArr
695
15.5k
    2247424U, // CBCOND
696
15.5k
    2312960U, // CBCONDA
697
15.5k
    69980U, // CMASK16
698
15.5k
    69812U, // CMASK32
699
15.5k
    70129U, // CMASK8
700
15.5k
    2850U,  // DONE
701
15.5k
    20984119U,  // EDGE16
702
15.5k
    20984887U,  // EDGE16L
703
15.5k
    20985004U,  // EDGE16LN
704
15.5k
    20984971U,  // EDGE16N
705
15.5k
    20983951U,  // EDGE32
706
15.5k
    20984878U,  // EDGE32L
707
15.5k
    20984994U,  // EDGE32LN
708
15.5k
    20984962U,  // EDGE32N
709
15.5k
    20984298U,  // EDGE8
710
15.5k
    20984896U,  // EDGE8L
711
15.5k
    20985014U,  // EDGE8LN
712
15.5k
    20984980U,  // EDGE8N
713
15.5k
    2110371U, // FABSD
714
15.5k
    2110766U, // FABSQ
715
15.5k
    2111166U, // FABSS
716
15.5k
    20984582U,  // FADDD
717
15.5k
    20985062U,  // FADDQ
718
15.5k
    20985362U,  // FADDS
719
15.5k
    20984386U,  // FALIGNADATA
720
15.5k
    20984661U,  // FAND
721
15.5k
    20983899U,  // FANDNOT1
722
15.5k
    20985241U,  // FANDNOT1S
723
15.5k
    20984058U,  // FANDNOT2
724
15.5k
    20985298U,  // FANDNOT2S
725
15.5k
    20985394U,  // FANDS
726
15.5k
    2247427U, // FBCOND
727
15.5k
    2312963U, // FBCONDA
728
15.5k
    1067779U, // FBCONDA_V9
729
15.5k
    3230467U, // FBCOND_V9
730
15.5k
    20984181U,  // FCHKSM16
731
15.5k
    5008U,  // FCMPD
732
15.5k
    4097U,  // FCMPD_V9
733
15.5k
    20984200U,  // FCMPEQ16
734
15.5k
    20984013U,  // FCMPEQ32
735
15.5k
    20984219U,  // FCMPGT16
736
15.5k
    20984032U,  // FCMPGT32
737
15.5k
    20984127U,  // FCMPLE16
738
15.5k
    20983959U,  // FCMPLE32
739
15.5k
    20984137U,  // FCMPNE16
740
15.5k
    20983969U,  // FCMPNE32
741
15.5k
    5415U,  // FCMPQ
742
15.5k
    4111U,  // FCMPQ_V9
743
15.5k
    5779U,  // FCMPS
744
15.5k
    4125U,  // FCMPS_V9
745
15.5k
    20984759U,  // FDIVD
746
15.5k
    20985154U,  // FDIVQ
747
15.5k
    20985549U,  // FDIVS
748
15.5k
    20985084U,  // FDMULQ
749
15.5k
    2110482U, // FDTOI
750
15.5k
    2110731U, // FDTOQ
751
15.5k
    2111086U, // FDTOS
752
15.5k
    2111331U, // FDTOX
753
15.5k
    2110306U, // FEXPAND
754
15.5k
    20984589U,  // FHADDD
755
15.5k
    20985369U,  // FHADDS
756
15.5k
    20984569U,  // FHSUBD
757
15.5k
    20985354U,  // FHSUBS
758
15.5k
    2110315U, // FITOD
759
15.5k
    2110738U, // FITOQ
760
15.5k
    2111093U, // FITOS
761
15.5k
    150999959U, // FLCMPD
762
15.5k
    151000730U, // FLCMPS
763
15.5k
    2445U,  // FLUSH
764
15.5k
    2933U,  // FLUSHW
765
15.5k
    87021U, // FLUSHri
766
15.5k
    87021U, // FLUSHrr
767
15.5k
    20984191U,  // FMEAN16
768
15.5k
    2110398U, // FMOVD
769
15.5k
    17918748U,  // FMOVD_FCC
770
15.5k
    17197852U,  // FMOVD_ICC
771
15.5k
    17459996U,  // FMOVD_XCC
772
15.5k
    2110793U, // FMOVQ
773
15.5k
    17918798U,  // FMOVQ_FCC
774
15.5k
    17197902U,  // FMOVQ_ICC
775
15.5k
    17460046U,  // FMOVQ_XCC
776
15.5k
    31509U, // FMOVRD
777
15.5k
    31559U, // FMOVRQ
778
15.5k
    31586U, // FMOVRS
779
15.5k
    2111188U, // FMOVS
780
15.5k
    17918825U,  // FMOVS_FCC
781
15.5k
    17197929U,  // FMOVS_ICC
782
15.5k
    17460073U,  // FMOVS_XCC
783
15.5k
    20984277U,  // FMUL8SUX16
784
15.5k
    20984252U,  // FMUL8ULX16
785
15.5k
    20984229U,  // FMUL8X16
786
15.5k
    20984904U,  // FMUL8X16AL
787
15.5k
    20985588U,  // FMUL8X16AU
788
15.5k
    20984629U,  // FMULD
789
15.5k
    20984264U,  // FMULD8SUX16
790
15.5k
    20984239U,  // FMULD8ULX16
791
15.5k
    20985092U,  // FMULQ
792
15.5k
    20985431U,  // FMULS
793
15.5k
    20984606U,  // FNADDD
794
15.5k
    20985386U,  // FNADDS
795
15.5k
    20984667U,  // FNAND
796
15.5k
    20985401U,  // FNANDS
797
15.5k
    2110254U, // FNEGD
798
15.5k
    2110709U, // FNEGQ
799
15.5k
    2111056U, // FNEGS
800
15.5k
    20984597U,  // FNHADDD
801
15.5k
    20985377U,  // FNHADDS
802
15.5k
    20984636U,  // FNMULD
803
15.5k
    20985438U,  // FNMULS
804
15.5k
    20985197U,  // FNOR
805
15.5k
    20985512U,  // FNORS
806
15.5k
    2109541U, // FNOT1
807
15.5k
    2110884U, // FNOT1S
808
15.5k
    2109700U, // FNOT2
809
15.5k
    2110941U, // FNOT2S
810
15.5k
    20984652U,  // FNSMULD
811
15.5k
    70616U, // FONE
812
15.5k
    71233U, // FONES
813
15.5k
    20985192U,  // FOR
814
15.5k
    20983916U,  // FORNOT1
815
15.5k
    20985260U,  // FORNOT1S
816
15.5k
    20984075U,  // FORNOT2
817
15.5k
    20985317U,  // FORNOT2S
818
15.5k
    20985506U,  // FORS
819
15.5k
    2109779U, // FPACK16
820
15.5k
    20983979U,  // FPACK32
821
15.5k
    2111302U, // FPACKFIX
822
15.5k
    20984110U,  // FPADD16
823
15.5k
    20985337U,  // FPADD16S
824
15.5k
    20983942U,  // FPADD32
825
15.5k
    20985280U,  // FPADD32S
826
15.5k
    20984084U,  // FPADD64
827
15.5k
    20984773U,  // FPMERGE
828
15.5k
    20984101U,  // FPSUB16
829
15.5k
    20985327U,  // FPSUB16S
830
15.5k
    20983933U,  // FPSUB32
831
15.5k
    20985270U,  // FPSUB32S
832
15.5k
    2110322U, // FQTOD
833
15.5k
    2110489U, // FQTOI
834
15.5k
    2111100U, // FQTOS
835
15.5k
    2111347U, // FQTOX
836
15.5k
    20984210U,  // FSLAS16
837
15.5k
    20984023U,  // FSLAS32
838
15.5k
    20984165U,  // FSLL16
839
15.5k
    20983997U,  // FSLL32
840
15.5k
    20984644U,  // FSMULD
841
15.5k
    2110378U, // FSQRTD
842
15.5k
    2110773U, // FSQRTQ
843
15.5k
    2111173U, // FSQRTS
844
15.5k
    20984093U,  // FSRA16
845
15.5k
    20983925U,  // FSRA32
846
15.5k
    2109524U, // FSRC1
847
15.5k
    2110865U, // FSRC1S
848
15.5k
    2109683U, // FSRC2
849
15.5k
    2110922U, // FSRC2S
850
15.5k
    20984173U,  // FSRL16
851
15.5k
    20984005U,  // FSRL32
852
15.5k
    2110329U, // FSTOD
853
15.5k
    2110496U, // FSTOI
854
15.5k
    2110745U, // FSTOQ
855
15.5k
    2111354U, // FSTOX
856
15.5k
    20984562U,  // FSUBD
857
15.5k
    20985055U,  // FSUBQ
858
15.5k
    20985347U,  // FSUBS
859
15.5k
    20985203U,  // FXNOR
860
15.5k
    20985519U,  // FXNORS
861
15.5k
    20985210U,  // FXOR
862
15.5k
    20985527U,  // FXORS
863
15.5k
    2110336U, // FXTOD
864
15.5k
    2110752U, // FXTOQ
865
15.5k
    2111116U, // FXTOS
866
15.5k
    70860U, // FZERO
867
15.5k
    71270U, // FZEROS
868
15.5k
    288525050U, // GDOP_LDXrr
869
15.5k
    288525000U, // GDOP_LDrr
870
15.5k
    2131039U, // JMPLri
871
15.5k
    2131039U, // JMPLrr
872
15.5k
    3050088U, // LDAri
873
15.5k
    26184296U,  // LDArr
874
15.5k
    1268424U, // LDCSRri
875
15.5k
    1268424U, // LDCSRrr
876
15.5k
    3312328U, // LDCri
877
15.5k
    3312328U, // LDCrr
878
15.5k
    3050081U, // LDDAri
879
15.5k
    26184289U,  // LDDArr
880
15.5k
    3312322U, // LDDCri
881
15.5k
    3312322U, // LDDCrr
882
15.5k
    3050081U, // LDDFAri
883
15.5k
    26184289U,  // LDDFArr
884
15.5k
    3312322U, // LDDFri
885
15.5k
    3312322U, // LDDFrr
886
15.5k
    3312322U, // LDDri
887
15.5k
    3312322U, // LDDrr
888
15.5k
    3050088U, // LDFAri
889
15.5k
    26184296U,  // LDFArr
890
15.5k
    1333960U, // LDFSRri
891
15.5k
    1333960U, // LDFSRrr
892
15.5k
    3312328U, // LDFri
893
15.5k
    3312328U, // LDFrr
894
15.5k
    3050118U, // LDQFAri
895
15.5k
    26184326U,  // LDQFArr
896
15.5k
    3312365U, // LDQFri
897
15.5k
    3312365U, // LDQFrr
898
15.5k
    3050055U, // LDSBAri
899
15.5k
    26184263U,  // LDSBArr
900
15.5k
    3312299U, // LDSBri
901
15.5k
    3312299U, // LDSBrr
902
15.5k
    3050094U, // LDSHAri
903
15.5k
    26184302U,  // LDSHArr
904
15.5k
    3312344U, // LDSHri
905
15.5k
    3312344U, // LDSHrr
906
15.5k
    3050071U, // LDSTUBAri
907
15.5k
    26184279U,  // LDSTUBArr
908
15.5k
    3312313U, // LDSTUBri
909
15.5k
    3312313U, // LDSTUBrr
910
15.5k
    3050132U, // LDSWAri
911
15.5k
    26184340U,  // LDSWArr
912
15.5k
    3312371U, // LDSWri
913
15.5k
    3312371U, // LDSWrr
914
15.5k
    3050063U, // LDUBAri
915
15.5k
    26184271U,  // LDUBArr
916
15.5k
    3312306U, // LDUBri
917
15.5k
    3312306U, // LDUBrr
918
15.5k
    3050102U, // LDUHAri
919
15.5k
    26184310U,  // LDUHArr
920
15.5k
    3312351U, // LDUHri
921
15.5k
    3312351U, // LDUHrr
922
15.5k
    3050140U, // LDXAri
923
15.5k
    26184348U,  // LDXArr
924
15.5k
    1334010U, // LDXFSRri
925
15.5k
    1334010U, // LDXFSRrr
926
15.5k
    3312378U, // LDXri
927
15.5k
    3312378U, // LDXrr
928
15.5k
    3312328U, // LDri
929
15.5k
    3312328U, // LDrr
930
15.5k
    2111200U, // LZCNT
931
15.5k
    38224U, // MEMBARi
932
15.5k
    2111338U, // MOVDTOX
933
15.5k
    17918833U,  // MOVFCCri
934
15.5k
    17918833U,  // MOVFCCrr
935
15.5k
    17197937U,  // MOVICCri
936
15.5k
    17197937U,  // MOVICCrr
937
15.5k
    31581U, // MOVRri
938
15.5k
    31581U, // MOVRrr
939
15.5k
    2111264U, // MOVSTOSW
940
15.5k
    2111274U, // MOVSTOUW
941
15.5k
    2111107U, // MOVWTOS
942
15.5k
    17460081U,  // MOVXCCri
943
15.5k
    17460081U,  // MOVXCCrr
944
15.5k
    2110343U, // MOVXTOD
945
15.5k
    20984509U,  // MULSCCri
946
15.5k
    20984509U,  // MULSCCrr
947
15.5k
    20985693U,  // MULXri
948
15.5k
    20985693U,  // MULXrr
949
15.5k
    2883U,  // NOP
950
15.5k
    20984496U,  // ORCCri
951
15.5k
    20984496U,  // ORCCrr
952
15.5k
    20984487U,  // ORNCCri
953
15.5k
    20984487U,  // ORNCCrr
954
15.5k
    20985023U,  // ORNri
955
15.5k
    20985023U,  // ORNrr
956
15.5k
    20985193U,  // ORri
957
15.5k
    20985193U,  // ORrr
958
15.5k
    20985575U,  // PDIST
959
15.5k
    20985028U,  // PDISTN
960
15.5k
    2110181U, // POPCrr
961
15.5k
    5397197U, // PREFETCHi
962
15.5k
    5397197U, // PREFETCHr
963
15.5k
    33559948U,  // PWRPSRri
964
15.5k
    33559948U,  // PWRPSRrr
965
15.5k
    2110367U, // RDASR
966
15.5k
    69685U, // RDFQ
967
15.5k
    2110848U, // RDPR
968
15.5k
    69706U, // RDPSR
969
15.5k
    69696U, // RDTBR
970
15.5k
    69675U, // RDWIM
971
15.5k
    2822U,  // RESTORED
972
15.5k
    20984798U,  // RESTOREri
973
15.5k
    20984798U,  // RESTORErr
974
15.5k
    71911U, // RET
975
15.5k
    71920U, // RETL
976
15.5k
    2940U,  // RETRY
977
15.5k
    87790U, // RETTri
978
15.5k
    87790U, // RETTrr
979
15.5k
    2831U,  // SAVED
980
15.5k
    20984807U,  // SAVEri
981
15.5k
    20984807U,  // SAVErr
982
15.5k
    20984517U,  // SDIVCCri
983
15.5k
    20984517U,  // SDIVCCrr
984
15.5k
    20985740U,  // SDIVXri
985
15.5k
    20985740U,  // SDIVXrr
986
15.5k
    20985600U,  // SDIVri
987
15.5k
    20985600U,  // SDIVrr
988
15.5k
    2110457U, // SETHIi
989
15.5k
    2874U,  // SHUTDOWN
990
15.5k
    2869U,  // SIAM
991
15.5k
    71011U, // SIR
992
15.5k
    20985680U,  // SLLXri
993
15.5k
    20985680U,  // SLLXrr
994
15.5k
    20984922U,  // SLLri
995
15.5k
    20984922U,  // SLLrr
996
15.5k
    20984419U,  // SMACri
997
15.5k
    20984419U,  // SMACrr
998
15.5k
    20984463U,  // SMULCCri
999
15.5k
    20984463U,  // SMULCCrr
1000
15.5k
    20984950U,  // SMULri
1001
15.5k
    20984950U,  // SMULrr
1002
15.5k
    20985652U,  // SRAXri
1003
15.5k
    20985652U,  // SRAXrr
1004
15.5k
    20984381U,  // SRAri
1005
15.5k
    20984381U,  // SRArr
1006
15.5k
    20985686U,  // SRLXri
1007
15.5k
    20985686U,  // SRLXrr
1008
15.5k
    20984945U,  // SRLri
1009
15.5k
    20984945U,  // SRLrr
1010
15.5k
    1417806U, // STAri
1011
15.5k
    9413198U, // STArr
1012
15.5k
    2900U,  // STBAR
1013
15.5k
    1417765U, // STBAri
1014
15.5k
    9413157U, // STBArr
1015
15.5k
    1483353U, // STBri
1016
15.5k
    1483353U, // STBrr
1017
15.5k
    1464869U, // STCSRri
1018
15.5k
    1464869U, // STCSRrr
1019
15.5k
    1484522U, // STCri
1020
15.5k
    1484522U, // STCrr
1021
15.5k
    1417771U, // STDAri
1022
15.5k
    9413163U, // STDArr
1023
15.5k
    1464847U, // STDCQri
1024
15.5k
    1464847U, // STDCQrr
1025
15.5k
    1483698U, // STDCri
1026
15.5k
    1483698U, // STDCrr
1027
15.5k
    1417771U, // STDFAri
1028
15.5k
    9413163U, // STDFArr
1029
15.5k
    1464858U, // STDFQri
1030
15.5k
    1464858U, // STDFQrr
1031
15.5k
    1483698U, // STDFri
1032
15.5k
    1483698U, // STDFrr
1033
15.5k
    1483698U, // STDri
1034
15.5k
    1483698U, // STDrr
1035
15.5k
    1417806U, // STFAri
1036
15.5k
    9413198U, // STFArr
1037
15.5k
    1464880U, // STFSRri
1038
15.5k
    1464880U, // STFSRrr
1039
15.5k
    1484522U, // STFri
1040
15.5k
    1484522U, // STFrr
1041
15.5k
    1417777U, // STHAri
1042
15.5k
    9413169U, // STHArr
1043
15.5k
    1483764U, // STHri
1044
15.5k
    1483764U, // STHrr
1045
15.5k
    1417783U, // STQFAri
1046
15.5k
    9413175U, // STQFArr
1047
15.5k
    1484093U, // STQFri
1048
15.5k
    1484093U, // STQFrr
1049
15.5k
    1417811U, // STXAri
1050
15.5k
    9413203U, // STXArr
1051
15.5k
    1464891U, // STXFSRri
1052
15.5k
    1464891U, // STXFSRrr
1053
15.5k
    1484679U, // STXri
1054
15.5k
    1484679U, // STXrr
1055
15.5k
    1484522U, // STri
1056
15.5k
    1484522U, // STrr
1057
15.5k
    20984432U,  // SUBCCri
1058
15.5k
    20984432U,  // SUBCCrr
1059
15.5k
    20985658U,  // SUBCri
1060
15.5k
    20985658U,  // SUBCrr
1061
15.5k
    20984533U,  // SUBEri
1062
15.5k
    20984533U,  // SUBErr
1063
15.5k
    20984414U,  // SUBri
1064
15.5k
    20984414U,  // SUBrr
1065
15.5k
    3050110U, // SWAPAri
1066
15.5k
    26184318U,  // SWAPArr
1067
15.5k
    3312358U, // SWAPri
1068
15.5k
    3312358U, // SWAPrr
1069
15.5k
    2455U,  // TA1
1070
15.5k
    2460U,  // TA3
1071
15.5k
    2465U,  // TA5
1072
15.5k
    20985622U,  // TADDCCTVri
1073
15.5k
    20985622U,  // TADDCCTVrr
1074
15.5k
    20984448U,  // TADDCCri
1075
15.5k
    20984448U,  // TADDCCrr
1076
15.5k
    70740U, // TAIL_CALL
1077
15.5k
    87258U, // TAIL_CALLri
1078
15.5k
    52869999U,  // TICCri
1079
15.5k
    52869999U,  // TICCrr
1080
15.5k
    557855489U, // TLS_ADDrr
1081
15.5k
    5204U,  // TLS_CALL
1082
15.5k
    288525050U, // TLS_LDXrr
1083
15.5k
    288525000U, // TLS_LDrr
1084
15.5k
    52607855U,  // TRAPri
1085
15.5k
    52607855U,  // TRAPrr
1086
15.5k
    20985612U,  // TSUBCCTVri
1087
15.5k
    20985612U,  // TSUBCCTVrr
1088
15.5k
    20984431U,  // TSUBCCri
1089
15.5k
    20984431U,  // TSUBCCrr
1090
15.5k
    53132143U,  // TXCCri
1091
15.5k
    53132143U,  // TXCCrr
1092
15.5k
    20984525U,  // UDIVCCri
1093
15.5k
    20984525U,  // UDIVCCrr
1094
15.5k
    20985747U,  // UDIVXri
1095
15.5k
    20985747U,  // UDIVXrr
1096
15.5k
    20985606U,  // UDIVri
1097
15.5k
    20985606U,  // UDIVrr
1098
15.5k
    20984425U,  // UMACri
1099
15.5k
    20984425U,  // UMACrr
1100
15.5k
    20984471U,  // UMULCCri
1101
15.5k
    20984471U,  // UMULCCrr
1102
15.5k
    20984832U,  // UMULXHI
1103
15.5k
    20984956U,  // UMULri
1104
15.5k
    20984956U,  // UMULrr
1105
15.5k
    70867U, // UNIMP
1106
15.5k
    150999952U, // V9FCMPD
1107
15.5k
    150999846U, // V9FCMPED
1108
15.5k
    151000301U, // V9FCMPEQ
1109
15.5k
    151000648U, // V9FCMPES
1110
15.5k
    151000359U, // V9FCMPQ
1111
15.5k
    151000723U, // V9FCMPS
1112
15.5k
    31516U, // V9FMOVD_FCC
1113
15.5k
    31566U, // V9FMOVQ_FCC
1114
15.5k
    31593U, // V9FMOVS_FCC
1115
15.5k
    31601U, // V9MOVFCCri
1116
15.5k
    31601U, // V9MOVFCCrr
1117
15.5k
    20985229U,  // WRASRri
1118
15.5k
    20985229U,  // WRASRrr
1119
15.5k
    20985222U,  // WRPRri
1120
15.5k
    20985222U,  // WRPRrr
1121
15.5k
    33559949U,  // WRPSRri
1122
15.5k
    33559949U,  // WRPSRrr
1123
15.5k
    67114381U,  // WRTBRri
1124
15.5k
    67114381U,  // WRTBRrr
1125
15.5k
    83891597U,  // WRWIMri
1126
15.5k
    83891597U,  // WRWIMrr
1127
15.5k
    20985692U,  // XMULX
1128
15.5k
    20984841U,  // XMULXHI
1129
15.5k
    20984494U,  // XNORCCri
1130
15.5k
    20984494U,  // XNORCCrr
1131
15.5k
    20985204U,  // XNORri
1132
15.5k
    20985204U,  // XNORrr
1133
15.5k
    20984502U,  // XORCCri
1134
15.5k
    20984502U,  // XORCCrr
1135
15.5k
    20985211U,  // XORri
1136
15.5k
    20985211U,  // XORrr
1137
15.5k
  };
1138
1139
  // Emit the opcode for the instruction.
1140
15.5k
  uint32_t Bits = 0;
1141
15.5k
  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
1142
15.5k
  MnemonicBitsInfo MBI = {
1143
15.5k
#ifndef CAPSTONE_DIET
1144
15.5k
    AsmStrs+(Bits & 4095)-1,
1145
#else
1146
    NULL,
1147
#endif // CAPSTONE_DIET
1148
15.5k
    Bits
1149
15.5k
  };
1150
15.5k
  return MBI;
1151
15.5k
}
1152
1153
/// printInstruction - This method is automatically generated by tablegen
1154
/// from the instruction set description.
1155
15.5k
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
1156
15.5k
  SStream_concat0(O, "");
1157
15.5k
  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
1158
1159
15.5k
  SStream_concat0(O, MnemonicInfo.first);
1160
1161
15.5k
  uint32_t Bits = MnemonicInfo.second;
1162
15.5k
  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
1163
1164
  // Fragment 0 encoded into 4 bits for 12 unique commands.
1165
15.5k
  switch ((Bits >> 12) & 15) {
1166
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1167
13
  case 0:
1168
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1169
13
    return;
1170
0
    break;
1171
3.52k
  case 1:
1172
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CALL, CMASK16, CMASK32, CMASK8, FCMP...
1173
3.52k
    printOperand(MI, 0, O);
1174
3.52k
    break;
1175
0
  case 2:
1176
    // GETPCX
1177
0
    printGetPCX(MI, 0, O);
1178
0
    return;
1179
0
    break;
1180
4.27k
  case 3:
1181
    // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD...
1182
4.27k
    printOperand(MI, 1, O);
1183
4.27k
    break;
1184
2.17k
  case 4:
1185
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1186
2.17k
    printCCOperand(MI, 1, O);
1187
2.17k
    break;
1188
298
  case 5:
1189
    // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD...
1190
298
    printMemOperand(MI, 0, O);
1191
298
    break;
1192
423
  case 6:
1193
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1194
423
    printCCOperand(MI, 3, O);
1195
423
    break;
1196
129
  case 7:
1197
    // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1198
129
    printCCOperand(MI, 4, O);
1199
129
    SStream_concat1(O, ' ');
1200
129
    printOperand(MI, 1, O);
1201
129
    SStream_concat0(O, ", ");
1202
129
    printOperand(MI, 2, O);
1203
129
    SStream_concat0(O, ", ");
1204
129
    printOperand(MI, 0, O);
1205
129
    return;
1206
0
    break;
1207
2.98k
  case 8:
1208
    // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1209
2.98k
    printMemOperand(MI, 1, O);
1210
2.98k
    break;
1211
222
  case 9:
1212
    // MEMBARi
1213
222
    printMembarTag(MI, 0, O);
1214
222
    return;
1215
0
    break;
1216
1.48k
  case 10:
1217
    // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1218
1.48k
    printOperand(MI, 2, O);
1219
1.48k
    SStream_concat0(O, ", [");
1220
1.48k
    printMemOperand(MI, 0, O);
1221
1.48k
    break;
1222
0
  case 11:
1223
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1224
0
    printCCOperand(MI, 2, O);
1225
0
    break;
1226
15.5k
  }
1227
1228
1229
  // Fragment 1 encoded into 5 bits for 23 unique commands.
1230
15.1k
  switch ((Bits >> 16) & 31) {
1231
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1232
5.06k
  case 0:
1233
    // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
1234
5.06k
    SStream_concat0(O, ", ");
1235
5.06k
    break;
1236
2.61k
  case 1:
1237
    // ADJCALLSTACKUP, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMASK32...
1238
2.61k
    return;
1239
0
    break;
1240
931
  case 2:
1241
    // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr
1242
931
    SStream_concat1(O, ' ');
1243
931
    break;
1244
522
  case 3:
1245
    // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA
1246
522
    SStream_concat0(O, ",a ");
1247
522
    break;
1248
1
  case 4:
1249
    // BPFCCANT, BPRANT
1250
1
    SStream_concat0(O, ",a,pn ");
1251
1
    printOperand(MI, 2, O);
1252
1
    SStream_concat0(O, ", ");
1253
1
    printOperand(MI, 0, O);
1254
1
    return;
1255
0
    break;
1256
191
  case 5:
1257
    // BPFCCNT, BPRNT
1258
191
    SStream_concat0(O, ",pn ");
1259
191
    printOperand(MI, 2, O);
1260
191
    SStream_concat0(O, ", ");
1261
191
    printOperand(MI, 0, O);
1262
191
    return;
1263
0
    break;
1264
108
  case 6:
1265
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1266
108
    SStream_concat0(O, " %icc, ");
1267
108
    break;
1268
11
  case 7:
1269
    // BPICCA
1270
11
    SStream_concat0(O, ",a %icc, ");
1271
11
    printOperand(MI, 0, O);
1272
11
    return;
1273
0
    break;
1274
0
  case 8:
1275
    // BPICCANT
1276
0
    SStream_concat0(O, ",a,pn %icc, ");
1277
0
    printOperand(MI, 0, O);
1278
0
    return;
1279
0
    break;
1280
0
  case 9:
1281
    // BPICCNT
1282
0
    SStream_concat0(O, ",pn %icc, ");
1283
0
    printOperand(MI, 0, O);
1284
0
    return;
1285
0
    break;
1286
149
  case 10:
1287
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1288
149
    SStream_concat0(O, " %xcc, ");
1289
149
    break;
1290
220
  case 11:
1291
    // BPXCCA
1292
220
    SStream_concat0(O, ",a %xcc, ");
1293
220
    printOperand(MI, 0, O);
1294
220
    return;
1295
0
    break;
1296
0
  case 12:
1297
    // BPXCCANT
1298
0
    SStream_concat0(O, ",a,pn %xcc, ");
1299
0
    printOperand(MI, 0, O);
1300
0
    return;
1301
0
    break;
1302
0
  case 13:
1303
    // BPXCCNT
1304
0
    SStream_concat0(O, ",pn %xcc, ");
1305
0
    printOperand(MI, 0, O);
1306
0
    return;
1307
0
    break;
1308
908
  case 14:
1309
    // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1310
908
    SStream_concat0(O, "] %asi, ");
1311
908
    break;
1312
1.88k
  case 15:
1313
    // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1314
1.88k
    SStream_concat0(O, "] ");
1315
1.88k
    break;
1316
37
  case 16:
1317
    // FBCONDA_V9
1318
37
    SStream_concat0(O, ",a %fcc0, ");
1319
37
    printOperand(MI, 0, O);
1320
37
    return;
1321
0
    break;
1322
427
  case 17:
1323
    // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1324
427
    SStream_concat0(O, " %fcc0, ");
1325
427
    break;
1326
1.03k
  case 18:
1327
    // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1328
1.03k
    SStream_concat0(O, "], ");
1329
1.03k
    break;
1330
11
  case 19:
1331
    // LDCSRri, LDCSRrr
1332
11
    SStream_concat0(O, "], %csr");
1333
11
    return;
1334
0
    break;
1335
58
  case 20:
1336
    // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1337
58
    SStream_concat0(O, "], %fsr");
1338
58
    return;
1339
0
    break;
1340
90
  case 21:
1341
    // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1342
90
    SStream_concat0(O, "] %asi");
1343
90
    return;
1344
0
    break;
1345
922
  case 22:
1346
    // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1347
922
    SStream_concat1(O, ']');
1348
922
    return;
1349
0
    break;
1350
15.1k
  }
1351
1352
1353
  // Fragment 2 encoded into 3 bits for 5 unique commands.
1354
11.0k
  switch ((Bits >> 21) & 7) {
1355
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1356
1.37k
  case 0:
1357
    // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F...
1358
1.37k
    printOperand(MI, 1, O);
1359
1.37k
    break;
1360
5.53k
  case 1:
1361
    // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS...
1362
5.53k
    printOperand(MI, 0, O);
1363
5.53k
    break;
1364
2.23k
  case 2:
1365
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1366
2.23k
    printOperand(MI, 2, O);
1367
2.23k
    break;
1368
164
  case 3:
1369
    // CASArr, CASXArr
1370
164
    printASITag(MI, 4, O);
1371
164
    SStream_concat0(O, ", ");
1372
164
    printOperand(MI, 2, O);
1373
164
    SStream_concat0(O, ", ");
1374
164
    printOperand(MI, 0, O);
1375
164
    return;
1376
0
    break;
1377
1.72k
  case 4:
1378
    // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1379
1.72k
    printASITag(MI, 3, O);
1380
1.72k
    break;
1381
11.0k
  }
1382
1383
1384
  // Fragment 3 encoded into 3 bits for 6 unique commands.
1385
10.8k
  switch ((Bits >> 24) & 7) {
1386
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1387
6.20k
  case 0:
1388
    // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, F...
1389
6.20k
    return;
1390
0
    break;
1391
4.18k
  case 1:
1392
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1393
4.18k
    SStream_concat0(O, ", ");
1394
4.18k
    break;
1395
200
  case 2:
1396
    // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1397
200
    SStream_concat0(O, ", %psr");
1398
200
    return;
1399
0
    break;
1400
0
  case 3:
1401
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1402
0
    SStream_concat0(O, " + ");
1403
0
    printOperand(MI, 1, O);
1404
0
    return;
1405
0
    break;
1406
209
  case 4:
1407
    // WRTBRri, WRTBRrr
1408
209
    SStream_concat0(O, ", %tbr");
1409
209
    return;
1410
0
    break;
1411
62
  case 5:
1412
    // WRWIMri, WRWIMrr
1413
62
    SStream_concat0(O, ", %wim");
1414
62
    return;
1415
0
    break;
1416
10.8k
  }
1417
1418
1419
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1420
4.18k
  switch ((Bits >> 27) & 3) {
1421
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1422
3.70k
  case 0:
1423
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1424
3.70k
    printOperand(MI, 0, O);
1425
3.70k
    break;
1426
478
  case 1:
1427
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1428
478
    printOperand(MI, 2, O);
1429
478
    return;
1430
0
    break;
1431
0
  case 2:
1432
    // GDOP_LDXrr, GDOP_LDrr, TLS_LDXrr, TLS_LDrr
1433
0
    printOperand(MI, 3, O);
1434
0
    return;
1435
0
    break;
1436
4.18k
  }
1437
1438
1439
  // Fragment 5 encoded into 1 bits for 2 unique commands.
1440
3.70k
  if ((Bits >> 29) & 1) {
1441
    // TLS_ADDrr
1442
0
    SStream_concat0(O, ", ");
1443
0
    printOperand(MI, 3, O);
1444
0
    return;
1445
3.70k
  } else {
1446
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1447
3.70k
    return;
1448
3.70k
  }
1449
1450
3.70k
}
1451
1452
1453
/// getRegisterName - This method is automatically generated by tblgen
1454
/// from the register set description.  This returns the assembler name
1455
/// for the specified register.
1456
static const char *
1457
58.1k
getRegisterName(unsigned RegNo, unsigned AltIdx) {
1458
58.1k
#ifndef CAPSTONE_DIET
1459
58.1k
  CS_ASSERT_RET_VAL(RegNo && RegNo < 238 && "Invalid register number!", NULL);
1460
1461
58.1k
  static const char AsmStrsNoRegAltName[] = {
1462
58.1k
  /* 0 */ "c10\0"
1463
58.1k
  /* 4 */ "f10\0"
1464
58.1k
  /* 8 */ "asr10\0"
1465
58.1k
  /* 14 */ "c20\0"
1466
58.1k
  /* 18 */ "f20\0"
1467
58.1k
  /* 22 */ "asr20\0"
1468
58.1k
  /* 28 */ "c30\0"
1469
58.1k
  /* 32 */ "f30\0"
1470
58.1k
  /* 36 */ "asr30\0"
1471
58.1k
  /* 42 */ "f40\0"
1472
58.1k
  /* 46 */ "f50\0"
1473
58.1k
  /* 50 */ "f60\0"
1474
58.1k
  /* 54 */ "fcc0\0"
1475
58.1k
  /* 59 */ "f0\0"
1476
58.1k
  /* 62 */ "g0\0"
1477
58.1k
  /* 65 */ "i0\0"
1478
58.1k
  /* 68 */ "l0\0"
1479
58.1k
  /* 71 */ "o0\0"
1480
58.1k
  /* 74 */ "c11\0"
1481
58.1k
  /* 78 */ "f11\0"
1482
58.1k
  /* 82 */ "asr11\0"
1483
58.1k
  /* 88 */ "c21\0"
1484
58.1k
  /* 92 */ "f21\0"
1485
58.1k
  /* 96 */ "asr21\0"
1486
58.1k
  /* 102 */ "c31\0"
1487
58.1k
  /* 106 */ "f31\0"
1488
58.1k
  /* 110 */ "asr31\0"
1489
58.1k
  /* 116 */ "fcc1\0"
1490
58.1k
  /* 121 */ "f1\0"
1491
58.1k
  /* 124 */ "g1\0"
1492
58.1k
  /* 127 */ "i1\0"
1493
58.1k
  /* 130 */ "l1\0"
1494
58.1k
  /* 133 */ "o1\0"
1495
58.1k
  /* 136 */ "asr1\0"
1496
58.1k
  /* 141 */ "c12\0"
1497
58.1k
  /* 145 */ "f12\0"
1498
58.1k
  /* 149 */ "asr12\0"
1499
58.1k
  /* 155 */ "c22\0"
1500
58.1k
  /* 159 */ "f22\0"
1501
58.1k
  /* 163 */ "asr22\0"
1502
58.1k
  /* 169 */ "f32\0"
1503
58.1k
  /* 173 */ "f42\0"
1504
58.1k
  /* 177 */ "f52\0"
1505
58.1k
  /* 181 */ "f62\0"
1506
58.1k
  /* 185 */ "fcc2\0"
1507
58.1k
  /* 190 */ "f2\0"
1508
58.1k
  /* 193 */ "g2\0"
1509
58.1k
  /* 196 */ "i2\0"
1510
58.1k
  /* 199 */ "l2\0"
1511
58.1k
  /* 202 */ "o2\0"
1512
58.1k
  /* 205 */ "asr2\0"
1513
58.1k
  /* 210 */ "c13\0"
1514
58.1k
  /* 214 */ "f13\0"
1515
58.1k
  /* 218 */ "asr13\0"
1516
58.1k
  /* 224 */ "c23\0"
1517
58.1k
  /* 228 */ "f23\0"
1518
58.1k
  /* 232 */ "asr23\0"
1519
58.1k
  /* 238 */ "fcc3\0"
1520
58.1k
  /* 243 */ "f3\0"
1521
58.1k
  /* 246 */ "g3\0"
1522
58.1k
  /* 249 */ "i3\0"
1523
58.1k
  /* 252 */ "l3\0"
1524
58.1k
  /* 255 */ "o3\0"
1525
58.1k
  /* 258 */ "asr3\0"
1526
58.1k
  /* 263 */ "c14\0"
1527
58.1k
  /* 267 */ "f14\0"
1528
58.1k
  /* 271 */ "asr14\0"
1529
58.1k
  /* 277 */ "c24\0"
1530
58.1k
  /* 281 */ "f24\0"
1531
58.1k
  /* 285 */ "asr24\0"
1532
58.1k
  /* 291 */ "f34\0"
1533
58.1k
  /* 295 */ "f44\0"
1534
58.1k
  /* 299 */ "f54\0"
1535
58.1k
  /* 303 */ "c4\0"
1536
58.1k
  /* 306 */ "f4\0"
1537
58.1k
  /* 309 */ "g4\0"
1538
58.1k
  /* 312 */ "i4\0"
1539
58.1k
  /* 315 */ "l4\0"
1540
58.1k
  /* 318 */ "o4\0"
1541
58.1k
  /* 321 */ "asr4\0"
1542
58.1k
  /* 326 */ "c15\0"
1543
58.1k
  /* 330 */ "f15\0"
1544
58.1k
  /* 334 */ "asr15\0"
1545
58.1k
  /* 340 */ "c25\0"
1546
58.1k
  /* 344 */ "f25\0"
1547
58.1k
  /* 348 */ "asr25\0"
1548
58.1k
  /* 354 */ "c5\0"
1549
58.1k
  /* 357 */ "f5\0"
1550
58.1k
  /* 360 */ "g5\0"
1551
58.1k
  /* 363 */ "i5\0"
1552
58.1k
  /* 366 */ "l5\0"
1553
58.1k
  /* 369 */ "o5\0"
1554
58.1k
  /* 372 */ "asr5\0"
1555
58.1k
  /* 377 */ "c16\0"
1556
58.1k
  /* 381 */ "f16\0"
1557
58.1k
  /* 385 */ "asr16\0"
1558
58.1k
  /* 391 */ "c26\0"
1559
58.1k
  /* 395 */ "f26\0"
1560
58.1k
  /* 399 */ "asr26\0"
1561
58.1k
  /* 405 */ "f36\0"
1562
58.1k
  /* 409 */ "f46\0"
1563
58.1k
  /* 413 */ "f56\0"
1564
58.1k
  /* 417 */ "c6\0"
1565
58.1k
  /* 420 */ "f6\0"
1566
58.1k
  /* 423 */ "g6\0"
1567
58.1k
  /* 426 */ "i6\0"
1568
58.1k
  /* 429 */ "l6\0"
1569
58.1k
  /* 432 */ "o6\0"
1570
58.1k
  /* 435 */ "asr6\0"
1571
58.1k
  /* 440 */ "c17\0"
1572
58.1k
  /* 444 */ "f17\0"
1573
58.1k
  /* 448 */ "asr17\0"
1574
58.1k
  /* 454 */ "c27\0"
1575
58.1k
  /* 458 */ "f27\0"
1576
58.1k
  /* 462 */ "asr27\0"
1577
58.1k
  /* 468 */ "c7\0"
1578
58.1k
  /* 471 */ "f7\0"
1579
58.1k
  /* 474 */ "g7\0"
1580
58.1k
  /* 477 */ "i7\0"
1581
58.1k
  /* 480 */ "l7\0"
1582
58.1k
  /* 483 */ "o7\0"
1583
58.1k
  /* 486 */ "asr7\0"
1584
58.1k
  /* 491 */ "c18\0"
1585
58.1k
  /* 495 */ "f18\0"
1586
58.1k
  /* 499 */ "asr18\0"
1587
58.1k
  /* 505 */ "c28\0"
1588
58.1k
  /* 509 */ "f28\0"
1589
58.1k
  /* 513 */ "asr28\0"
1590
58.1k
  /* 519 */ "f38\0"
1591
58.1k
  /* 523 */ "f48\0"
1592
58.1k
  /* 527 */ "f58\0"
1593
58.1k
  /* 531 */ "c8\0"
1594
58.1k
  /* 534 */ "f8\0"
1595
58.1k
  /* 537 */ "asr8\0"
1596
58.1k
  /* 542 */ "c19\0"
1597
58.1k
  /* 546 */ "f19\0"
1598
58.1k
  /* 550 */ "asr19\0"
1599
58.1k
  /* 556 */ "c29\0"
1600
58.1k
  /* 560 */ "f29\0"
1601
58.1k
  /* 564 */ "asr29\0"
1602
58.1k
  /* 570 */ "c9\0"
1603
58.1k
  /* 573 */ "f9\0"
1604
58.1k
  /* 576 */ "asr9\0"
1605
58.1k
  /* 581 */ "tba\0"
1606
58.1k
  /* 585 */ "icc\0"
1607
58.1k
  /* 589 */ "tnpc\0"
1608
58.1k
  /* 594 */ "tpc\0"
1609
58.1k
  /* 598 */ "canrestore\0"
1610
58.1k
  /* 609 */ "pstate\0"
1611
58.1k
  /* 616 */ "tstate\0"
1612
58.1k
  /* 623 */ "wstate\0"
1613
58.1k
  /* 630 */ "cansave\0"
1614
58.1k
  /* 638 */ "tick\0"
1615
58.1k
  /* 643 */ "gl\0"
1616
58.1k
  /* 646 */ "pil\0"
1617
58.1k
  /* 650 */ "tl\0"
1618
58.1k
  /* 653 */ "wim\0"
1619
58.1k
  /* 657 */ "cleanwin\0"
1620
58.1k
  /* 666 */ "otherwin\0"
1621
58.1k
  /* 675 */ "fp\0"
1622
58.1k
  /* 678 */ "sp\0"
1623
58.1k
  /* 681 */ "cwp\0"
1624
58.1k
  /* 685 */ "cq\0"
1625
58.1k
  /* 688 */ "fq\0"
1626
58.1k
  /* 691 */ "tbr\0"
1627
58.1k
  /* 695 */ "ver\0"
1628
58.1k
  /* 699 */ "csr\0"
1629
58.1k
  /* 703 */ "fsr\0"
1630
58.1k
  /* 707 */ "psr\0"
1631
58.1k
  /* 711 */ "tt\0"
1632
58.1k
  /* 714 */ "y\0"
1633
58.1k
};
1634
58.1k
  static const uint16_t RegAsmOffsetNoRegAltName[] = {
1635
58.1k
    598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, 
1636
58.1k
    581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, 
1637
58.1k
    258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, 
1638
58.1k
    448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, 
1639
58.1k
    110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, 
1640
58.1k
    210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, 
1641
58.1k
    454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, 
1642
58.1k
    495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, 
1643
58.1k
    409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, 
1644
58.1k
    357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, 
1645
58.1k
    546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, 
1646
58.1k
    116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, 
1647
58.1k
    249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, 
1648
58.1k
    133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, 
1649
58.1k
    509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, 
1650
58.1k
    0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, 
1651
58.1k
    423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, 
1652
58.1k
  };
1653
1654
58.1k
  static const char AsmStrsRegNamesStateReg[] = {
1655
58.1k
  /* 0 */ "pc\0"
1656
58.1k
  /* 3 */ "asi\0"
1657
58.1k
  /* 7 */ "tick\0"
1658
58.1k
  /* 12 */ "ccr\0"
1659
58.1k
  /* 16 */ "fprs\0"
1660
58.1k
};
1661
58.1k
  static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1662
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1663
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, 
1664
58.1k
    3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1665
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1666
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1667
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1668
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1669
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1670
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1671
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1672
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1673
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1674
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1675
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1676
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1677
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1678
58.1k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1679
58.1k
  };
1680
1681
58.1k
  switch(AltIdx) {
1682
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
1683
30.2k
  case Sparc_NoRegAltName:
1684
30.2k
    CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1685
30.2k
           "Invalid alt name index for register!", NULL);
1686
30.2k
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1687
27.9k
  case Sparc_RegNamesStateReg:
1688
27.9k
    if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1689
26.7k
      return getRegisterName(RegNo, Sparc_NoRegAltName);
1690
1.19k
    return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1691
58.1k
  }
1692
#else
1693
  return NULL;
1694
#endif // CAPSTONE_DIET
1695
58.1k
}
1696
#ifdef PRINT_ALIAS_INSTR
1697
#undef PRINT_ALIAS_INSTR
1698
1699
17.6k
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
1700
17.6k
#ifndef CAPSTONE_DIET
1701
17.6k
  static const PatternsForOpcode OpToPatterns[] = {
1702
17.6k
    {Sparc_BCOND, 0, 16 },
1703
17.6k
    {Sparc_BCONDA, 16, 16 },
1704
17.6k
    {Sparc_BPFCCANT, 32, 16 },
1705
17.6k
    {Sparc_BPFCCNT, 48, 16 },
1706
17.6k
    {Sparc_BPICCANT, 64, 16 },
1707
17.6k
    {Sparc_BPICCNT, 80, 16 },
1708
17.6k
    {Sparc_BPRANT, 96, 6 },
1709
17.6k
    {Sparc_BPRNT, 102, 6 },
1710
17.6k
    {Sparc_BPXCCANT, 108, 16 },
1711
17.6k
    {Sparc_BPXCCNT, 124, 16 },
1712
17.6k
    {Sparc_CASArr, 140, 2 },
1713
17.6k
    {Sparc_CASXArr, 142, 2 },
1714
17.6k
    {Sparc_FMOVD_ICC, 144, 16 },
1715
17.6k
    {Sparc_FMOVD_XCC, 160, 16 },
1716
17.6k
    {Sparc_FMOVQ_ICC, 176, 16 },
1717
17.6k
    {Sparc_FMOVQ_XCC, 192, 16 },
1718
17.6k
    {Sparc_FMOVRD, 208, 6 },
1719
17.6k
    {Sparc_FMOVRQ, 214, 6 },
1720
17.6k
    {Sparc_FMOVRS, 220, 6 },
1721
17.6k
    {Sparc_FMOVS_ICC, 226, 16 },
1722
17.6k
    {Sparc_FMOVS_XCC, 242, 16 },
1723
17.6k
    {Sparc_MOVICCri, 258, 16 },
1724
17.6k
    {Sparc_MOVICCrr, 274, 16 },
1725
17.6k
    {Sparc_MOVRri, 290, 6 },
1726
17.6k
    {Sparc_MOVRrr, 296, 6 },
1727
17.6k
    {Sparc_MOVXCCri, 302, 16 },
1728
17.6k
    {Sparc_MOVXCCrr, 318, 16 },
1729
17.6k
    {Sparc_ORCCrr, 334, 1 },
1730
17.6k
    {Sparc_ORri, 335, 1 },
1731
17.6k
    {Sparc_ORrr, 336, 1 },
1732
17.6k
    {Sparc_RESTORErr, 337, 1 },
1733
17.6k
    {Sparc_RET, 338, 1 },
1734
17.6k
    {Sparc_RETL, 339, 1 },
1735
17.6k
    {Sparc_SAVErr, 340, 1 },
1736
17.6k
    {Sparc_SUBCCri, 341, 1 },
1737
17.6k
    {Sparc_SUBCCrr, 342, 1 },
1738
17.6k
    {Sparc_TICCri, 343, 32 },
1739
17.6k
    {Sparc_TICCrr, 375, 32 },
1740
17.6k
    {Sparc_TRAPri, 407, 32 },
1741
17.6k
    {Sparc_TRAPrr, 439, 32 },
1742
17.6k
    {Sparc_TXCCri, 471, 32 },
1743
17.6k
    {Sparc_TXCCrr, 503, 32 },
1744
17.6k
    {Sparc_V9FCMPD, 535, 1 },
1745
17.6k
    {Sparc_V9FCMPED, 536, 1 },
1746
17.6k
    {Sparc_V9FCMPEQ, 537, 1 },
1747
17.6k
    {Sparc_V9FCMPES, 538, 1 },
1748
17.6k
    {Sparc_V9FCMPQ, 539, 1 },
1749
17.6k
    {Sparc_V9FCMPS, 540, 1 },
1750
17.6k
    {Sparc_V9FMOVD_FCC, 541, 16 },
1751
17.6k
    {Sparc_V9FMOVQ_FCC, 557, 16 },
1752
17.6k
    {Sparc_V9FMOVS_FCC, 573, 16 },
1753
17.6k
    {Sparc_V9MOVFCCri, 589, 16 },
1754
17.6k
    {Sparc_V9MOVFCCrr, 605, 16 },
1755
17.6k
  {0},  };
1756
1757
17.6k
  static const AliasPattern Patterns[] = {
1758
    // Sparc_BCOND - 0
1759
17.6k
    {0, 0, 2, 2 },
1760
17.6k
    {6, 2, 2, 2 },
1761
17.6k
    {12, 4, 2, 2 },
1762
17.6k
    {19, 6, 2, 2 },
1763
17.6k
    {25, 8, 2, 2 },
1764
17.6k
    {31, 10, 2, 2 },
1765
17.6k
    {38, 12, 2, 2 },
1766
17.6k
    {45, 14, 2, 2 },
1767
17.6k
    {51, 16, 2, 2 },
1768
17.6k
    {58, 18, 2, 2 },
1769
17.6k
    {66, 20, 2, 2 },
1770
17.6k
    {73, 22, 2, 2 },
1771
17.6k
    {80, 24, 2, 2 },
1772
17.6k
    {88, 26, 2, 2 },
1773
17.6k
    {96, 28, 2, 2 },
1774
17.6k
    {103, 30, 2, 2 },
1775
    // Sparc_BCONDA - 16
1776
17.6k
    {110, 32, 2, 2 },
1777
17.6k
    {118, 34, 2, 2 },
1778
17.6k
    {126, 36, 2, 2 },
1779
17.6k
    {135, 38, 2, 2 },
1780
17.6k
    {143, 40, 2, 2 },
1781
17.6k
    {151, 42, 2, 2 },
1782
17.6k
    {160, 44, 2, 2 },
1783
17.6k
    {169, 46, 2, 2 },
1784
17.6k
    {177, 48, 2, 2 },
1785
17.6k
    {186, 50, 2, 2 },
1786
17.6k
    {196, 52, 2, 2 },
1787
17.6k
    {205, 54, 2, 2 },
1788
17.6k
    {214, 56, 2, 2 },
1789
17.6k
    {224, 58, 2, 2 },
1790
17.6k
    {234, 60, 2, 2 },
1791
17.6k
    {243, 62, 2, 2 },
1792
    // Sparc_BPFCCANT - 32
1793
17.6k
    {252, 64, 3, 4 },
1794
17.6k
    {268, 68, 3, 4 },
1795
17.6k
    {284, 72, 3, 4 },
1796
17.6k
    {300, 76, 3, 4 },
1797
17.6k
    {316, 80, 3, 4 },
1798
17.6k
    {333, 84, 3, 4 },
1799
17.6k
    {349, 88, 3, 4 },
1800
17.6k
    {366, 92, 3, 4 },
1801
17.6k
    {383, 96, 3, 4 },
1802
17.6k
    {400, 100, 3, 4 },
1803
17.6k
    {416, 104, 3, 4 },
1804
17.6k
    {433, 108, 3, 4 },
1805
17.6k
    {450, 112, 3, 4 },
1806
17.6k
    {468, 116, 3, 4 },
1807
17.6k
    {485, 120, 3, 4 },
1808
17.6k
    {503, 124, 3, 4 },
1809
    // Sparc_BPFCCNT - 48
1810
17.6k
    {519, 128, 3, 4 },
1811
17.6k
    {533, 132, 3, 4 },
1812
17.6k
    {547, 136, 3, 4 },
1813
17.6k
    {561, 140, 3, 4 },
1814
17.6k
    {575, 144, 3, 4 },
1815
17.6k
    {590, 148, 3, 4 },
1816
17.6k
    {604, 152, 3, 4 },
1817
17.6k
    {619, 156, 3, 4 },
1818
17.6k
    {634, 160, 3, 4 },
1819
17.6k
    {649, 164, 3, 4 },
1820
17.6k
    {663, 168, 3, 4 },
1821
17.6k
    {678, 172, 3, 4 },
1822
17.6k
    {693, 176, 3, 4 },
1823
17.6k
    {709, 180, 3, 4 },
1824
17.6k
    {724, 184, 3, 4 },
1825
17.6k
    {740, 188, 3, 4 },
1826
    // Sparc_BPICCANT - 64
1827
17.6k
    {754, 192, 2, 3 },
1828
17.6k
    {771, 195, 2, 3 },
1829
17.6k
    {788, 198, 2, 3 },
1830
17.6k
    {806, 201, 2, 3 },
1831
17.6k
    {823, 204, 2, 3 },
1832
17.6k
    {840, 207, 2, 3 },
1833
17.6k
    {858, 210, 2, 3 },
1834
17.6k
    {876, 213, 2, 3 },
1835
17.6k
    {893, 216, 2, 3 },
1836
17.6k
    {911, 219, 2, 3 },
1837
17.6k
    {930, 222, 2, 3 },
1838
17.6k
    {948, 225, 2, 3 },
1839
17.6k
    {966, 228, 2, 3 },
1840
17.6k
    {985, 231, 2, 3 },
1841
17.6k
    {1004, 234, 2, 3 },
1842
17.6k
    {1022, 237, 2, 3 },
1843
    // Sparc_BPICCNT - 80
1844
17.6k
    {1040, 240, 2, 3 },
1845
17.6k
    {1055, 243, 2, 3 },
1846
17.6k
    {1070, 246, 2, 3 },
1847
17.6k
    {1086, 249, 2, 3 },
1848
17.6k
    {1101, 252, 2, 3 },
1849
17.6k
    {1116, 255, 2, 3 },
1850
17.6k
    {1132, 258, 2, 3 },
1851
17.6k
    {1148, 261, 2, 3 },
1852
17.6k
    {1163, 264, 2, 3 },
1853
17.6k
    {1179, 267, 2, 3 },
1854
17.6k
    {1196, 270, 2, 3 },
1855
17.6k
    {1212, 273, 2, 3 },
1856
17.6k
    {1228, 276, 2, 3 },
1857
17.6k
    {1245, 279, 2, 3 },
1858
17.6k
    {1262, 282, 2, 3 },
1859
17.6k
    {1278, 285, 2, 3 },
1860
    // Sparc_BPRANT - 96
1861
17.6k
    {1294, 288, 3, 4 },
1862
17.6k
    {1310, 292, 3, 4 },
1863
17.6k
    {1328, 296, 3, 4 },
1864
17.6k
    {1345, 300, 3, 4 },
1865
17.6k
    {1362, 304, 3, 4 },
1866
17.6k
    {1379, 308, 3, 4 },
1867
    // Sparc_BPRNT - 102
1868
17.6k
    {1397, 312, 3, 4 },
1869
17.6k
    {1411, 316, 3, 4 },
1870
17.6k
    {1427, 320, 3, 4 },
1871
17.6k
    {1442, 324, 3, 4 },
1872
17.6k
    {1457, 328, 3, 4 },
1873
17.6k
    {1472, 332, 3, 4 },
1874
    // Sparc_BPXCCANT - 108
1875
17.6k
    {1488, 336, 2, 3 },
1876
17.6k
    {1505, 339, 2, 3 },
1877
17.6k
    {1522, 342, 2, 3 },
1878
17.6k
    {1540, 345, 2, 3 },
1879
17.6k
    {1557, 348, 2, 3 },
1880
17.6k
    {1574, 351, 2, 3 },
1881
17.6k
    {1592, 354, 2, 3 },
1882
17.6k
    {1610, 357, 2, 3 },
1883
17.6k
    {1627, 360, 2, 3 },
1884
17.6k
    {1645, 363, 2, 3 },
1885
17.6k
    {1664, 366, 2, 3 },
1886
17.6k
    {1682, 369, 2, 3 },
1887
17.6k
    {1700, 372, 2, 3 },
1888
17.6k
    {1719, 375, 2, 3 },
1889
17.6k
    {1738, 378, 2, 3 },
1890
17.6k
    {1756, 381, 2, 3 },
1891
    // Sparc_BPXCCNT - 124
1892
17.6k
    {1774, 384, 2, 3 },
1893
17.6k
    {1789, 387, 2, 3 },
1894
17.6k
    {1804, 390, 2, 3 },
1895
17.6k
    {1820, 393, 2, 3 },
1896
17.6k
    {1835, 396, 2, 3 },
1897
17.6k
    {1850, 399, 2, 3 },
1898
17.6k
    {1866, 402, 2, 3 },
1899
17.6k
    {1882, 405, 2, 3 },
1900
17.6k
    {1897, 408, 2, 3 },
1901
17.6k
    {1913, 411, 2, 3 },
1902
17.6k
    {1930, 414, 2, 3 },
1903
17.6k
    {1946, 417, 2, 3 },
1904
17.6k
    {1962, 420, 2, 3 },
1905
17.6k
    {1979, 423, 2, 3 },
1906
17.6k
    {1996, 426, 2, 3 },
1907
17.6k
    {2012, 429, 2, 3 },
1908
    // Sparc_CASArr - 140
1909
17.6k
    {2028, 432, 5, 6 },
1910
17.6k
    {2045, 438, 5, 6 },
1911
    // Sparc_CASXArr - 142
1912
17.6k
    {2063, 444, 5, 6 },
1913
17.6k
    {2081, 450, 5, 6 },
1914
    // Sparc_FMOVD_ICC - 144
1915
17.6k
    {2100, 456, 4, 5 },
1916
17.6k
    {2120, 461, 4, 5 },
1917
17.6k
    {2140, 466, 4, 5 },
1918
17.6k
    {2161, 471, 4, 5 },
1919
17.6k
    {2181, 476, 4, 5 },
1920
17.6k
    {2201, 481, 4, 5 },
1921
17.6k
    {2222, 486, 4, 5 },
1922
17.6k
    {2243, 491, 4, 5 },
1923
17.6k
    {2263, 496, 4, 5 },
1924
17.6k
    {2284, 501, 4, 5 },
1925
17.6k
    {2306, 506, 4, 5 },
1926
17.6k
    {2327, 511, 4, 5 },
1927
17.6k
    {2348, 516, 4, 5 },
1928
17.6k
    {2370, 521, 4, 5 },
1929
17.6k
    {2392, 526, 4, 5 },
1930
17.6k
    {2413, 531, 4, 5 },
1931
    // Sparc_FMOVD_XCC - 160
1932
17.6k
    {2434, 536, 4, 5 },
1933
17.6k
    {2454, 541, 4, 5 },
1934
17.6k
    {2474, 546, 4, 5 },
1935
17.6k
    {2495, 551, 4, 5 },
1936
17.6k
    {2515, 556, 4, 5 },
1937
17.6k
    {2535, 561, 4, 5 },
1938
17.6k
    {2556, 566, 4, 5 },
1939
17.6k
    {2577, 571, 4, 5 },
1940
17.6k
    {2597, 576, 4, 5 },
1941
17.6k
    {2618, 581, 4, 5 },
1942
17.6k
    {2640, 586, 4, 5 },
1943
17.6k
    {2661, 591, 4, 5 },
1944
17.6k
    {2682, 596, 4, 5 },
1945
17.6k
    {2704, 601, 4, 5 },
1946
17.6k
    {2726, 606, 4, 5 },
1947
17.6k
    {2747, 611, 4, 5 },
1948
    // Sparc_FMOVQ_ICC - 176
1949
17.6k
    {2768, 616, 4, 5 },
1950
17.6k
    {2788, 621, 4, 5 },
1951
17.6k
    {2808, 626, 4, 5 },
1952
17.6k
    {2829, 631, 4, 5 },
1953
17.6k
    {2849, 636, 4, 5 },
1954
17.6k
    {2869, 641, 4, 5 },
1955
17.6k
    {2890, 646, 4, 5 },
1956
17.6k
    {2911, 651, 4, 5 },
1957
17.6k
    {2931, 656, 4, 5 },
1958
17.6k
    {2952, 661, 4, 5 },
1959
17.6k
    {2974, 666, 4, 5 },
1960
17.6k
    {2995, 671, 4, 5 },
1961
17.6k
    {3016, 676, 4, 5 },
1962
17.6k
    {3038, 681, 4, 5 },
1963
17.6k
    {3060, 686, 4, 5 },
1964
17.6k
    {3081, 691, 4, 5 },
1965
    // Sparc_FMOVQ_XCC - 192
1966
17.6k
    {3102, 696, 4, 5 },
1967
17.6k
    {3122, 701, 4, 5 },
1968
17.6k
    {3142, 706, 4, 5 },
1969
17.6k
    {3163, 711, 4, 5 },
1970
17.6k
    {3183, 716, 4, 5 },
1971
17.6k
    {3203, 721, 4, 5 },
1972
17.6k
    {3224, 726, 4, 5 },
1973
17.6k
    {3245, 731, 4, 5 },
1974
17.6k
    {3265, 736, 4, 5 },
1975
17.6k
    {3286, 741, 4, 5 },
1976
17.6k
    {3308, 746, 4, 5 },
1977
17.6k
    {3329, 751, 4, 5 },
1978
17.6k
    {3350, 756, 4, 5 },
1979
17.6k
    {3372, 761, 4, 5 },
1980
17.6k
    {3394, 766, 4, 5 },
1981
17.6k
    {3415, 771, 4, 5 },
1982
    // Sparc_FMOVRD - 208
1983
17.6k
    {3436, 776, 5, 6 },
1984
17.6k
    {3455, 782, 5, 6 },
1985
17.6k
    {3476, 788, 5, 6 },
1986
17.6k
    {3496, 794, 5, 6 },
1987
17.6k
    {3516, 800, 5, 6 },
1988
17.6k
    {3536, 806, 5, 6 },
1989
    // Sparc_FMOVRQ - 214
1990
17.6k
    {3557, 812, 5, 6 },
1991
17.6k
    {3576, 818, 5, 6 },
1992
17.6k
    {3597, 824, 5, 6 },
1993
17.6k
    {3617, 830, 5, 6 },
1994
17.6k
    {3637, 836, 5, 6 },
1995
17.6k
    {3657, 842, 5, 6 },
1996
    // Sparc_FMOVRS - 220
1997
17.6k
    {3678, 848, 5, 6 },
1998
17.6k
    {3697, 854, 5, 6 },
1999
17.6k
    {3718, 860, 5, 6 },
2000
17.6k
    {3738, 866, 5, 6 },
2001
17.6k
    {3758, 872, 5, 6 },
2002
17.6k
    {3778, 878, 5, 6 },
2003
    // Sparc_FMOVS_ICC - 226
2004
17.6k
    {3799, 884, 4, 5 },
2005
17.6k
    {3819, 889, 4, 5 },
2006
17.6k
    {3839, 894, 4, 5 },
2007
17.6k
    {3860, 899, 4, 5 },
2008
17.6k
    {3880, 904, 4, 5 },
2009
17.6k
    {3900, 909, 4, 5 },
2010
17.6k
    {3921, 914, 4, 5 },
2011
17.6k
    {3942, 919, 4, 5 },
2012
17.6k
    {3962, 924, 4, 5 },
2013
17.6k
    {3983, 929, 4, 5 },
2014
17.6k
    {4005, 934, 4, 5 },
2015
17.6k
    {4026, 939, 4, 5 },
2016
17.6k
    {4047, 944, 4, 5 },
2017
17.6k
    {4069, 949, 4, 5 },
2018
17.6k
    {4091, 954, 4, 5 },
2019
17.6k
    {4112, 959, 4, 5 },
2020
    // Sparc_FMOVS_XCC - 242
2021
17.6k
    {4133, 964, 4, 5 },
2022
17.6k
    {4153, 969, 4, 5 },
2023
17.6k
    {4173, 974, 4, 5 },
2024
17.6k
    {4194, 979, 4, 5 },
2025
17.6k
    {4214, 984, 4, 5 },
2026
17.6k
    {4234, 989, 4, 5 },
2027
17.6k
    {4255, 994, 4, 5 },
2028
17.6k
    {4276, 999, 4, 5 },
2029
17.6k
    {4296, 1004, 4, 5 },
2030
17.6k
    {4317, 1009, 4, 5 },
2031
17.6k
    {4339, 1014, 4, 5 },
2032
17.6k
    {4360, 1019, 4, 5 },
2033
17.6k
    {4381, 1024, 4, 5 },
2034
17.6k
    {4403, 1029, 4, 5 },
2035
17.6k
    {4425, 1034, 4, 5 },
2036
17.6k
    {4446, 1039, 4, 5 },
2037
    // Sparc_MOVICCri - 258
2038
17.6k
    {4467, 1044, 4, 5 },
2039
17.6k
    {4485, 1049, 4, 5 },
2040
17.6k
    {4503, 1054, 4, 5 },
2041
17.6k
    {4522, 1059, 4, 5 },
2042
17.6k
    {4540, 1064, 4, 5 },
2043
17.6k
    {4558, 1069, 4, 5 },
2044
17.6k
    {4577, 1074, 4, 5 },
2045
17.6k
    {4596, 1079, 4, 5 },
2046
17.6k
    {4614, 1084, 4, 5 },
2047
17.6k
    {4633, 1089, 4, 5 },
2048
17.6k
    {4653, 1094, 4, 5 },
2049
17.6k
    {4672, 1099, 4, 5 },
2050
17.6k
    {4691, 1104, 4, 5 },
2051
17.6k
    {4711, 1109, 4, 5 },
2052
17.6k
    {4731, 1114, 4, 5 },
2053
17.6k
    {4750, 1119, 4, 5 },
2054
    // Sparc_MOVICCrr - 274
2055
17.6k
    {4467, 1124, 4, 5 },
2056
17.6k
    {4485, 1129, 4, 5 },
2057
17.6k
    {4503, 1134, 4, 5 },
2058
17.6k
    {4522, 1139, 4, 5 },
2059
17.6k
    {4540, 1144, 4, 5 },
2060
17.6k
    {4558, 1149, 4, 5 },
2061
17.6k
    {4577, 1154, 4, 5 },
2062
17.6k
    {4596, 1159, 4, 5 },
2063
17.6k
    {4614, 1164, 4, 5 },
2064
17.6k
    {4633, 1169, 4, 5 },
2065
17.6k
    {4653, 1174, 4, 5 },
2066
17.6k
    {4672, 1179, 4, 5 },
2067
17.6k
    {4691, 1184, 4, 5 },
2068
17.6k
    {4711, 1189, 4, 5 },
2069
17.6k
    {4731, 1194, 4, 5 },
2070
17.6k
    {4750, 1199, 4, 5 },
2071
    // Sparc_MOVRri - 290
2072
17.6k
    {4769, 1204, 5, 6 },
2073
17.6k
    {4786, 1210, 5, 6 },
2074
17.6k
    {4805, 1216, 5, 6 },
2075
17.6k
    {4823, 1222, 5, 6 },
2076
17.6k
    {4841, 1228, 5, 6 },
2077
17.6k
    {4859, 1234, 5, 6 },
2078
    // Sparc_MOVRrr - 296
2079
17.6k
    {4769, 1240, 5, 6 },
2080
17.6k
    {4786, 1246, 5, 6 },
2081
17.6k
    {4805, 1252, 5, 6 },
2082
17.6k
    {4823, 1258, 5, 6 },
2083
17.6k
    {4841, 1264, 5, 6 },
2084
17.6k
    {4859, 1270, 5, 6 },
2085
    // Sparc_MOVXCCri - 302
2086
17.6k
    {4878, 1276, 4, 5 },
2087
17.6k
    {4896, 1281, 4, 5 },
2088
17.6k
    {4914, 1286, 4, 5 },
2089
17.6k
    {4933, 1291, 4, 5 },
2090
17.6k
    {4951, 1296, 4, 5 },
2091
17.6k
    {4969, 1301, 4, 5 },
2092
17.6k
    {4988, 1306, 4, 5 },
2093
17.6k
    {5007, 1311, 4, 5 },
2094
17.6k
    {5025, 1316, 4, 5 },
2095
17.6k
    {5044, 1321, 4, 5 },
2096
17.6k
    {5064, 1326, 4, 5 },
2097
17.6k
    {5083, 1331, 4, 5 },
2098
17.6k
    {5102, 1336, 4, 5 },
2099
17.6k
    {5122, 1341, 4, 5 },
2100
17.6k
    {5142, 1346, 4, 5 },
2101
17.6k
    {5161, 1351, 4, 5 },
2102
    // Sparc_MOVXCCrr - 318
2103
17.6k
    {4878, 1356, 4, 5 },
2104
17.6k
    {4896, 1361, 4, 5 },
2105
17.6k
    {4914, 1366, 4, 5 },
2106
17.6k
    {4933, 1371, 4, 5 },
2107
17.6k
    {4951, 1376, 4, 5 },
2108
17.6k
    {4969, 1381, 4, 5 },
2109
17.6k
    {4988, 1386, 4, 5 },
2110
17.6k
    {5007, 1391, 4, 5 },
2111
17.6k
    {5025, 1396, 4, 5 },
2112
17.6k
    {5044, 1401, 4, 5 },
2113
17.6k
    {5064, 1406, 4, 5 },
2114
17.6k
    {5083, 1411, 4, 5 },
2115
17.6k
    {5102, 1416, 4, 5 },
2116
17.6k
    {5122, 1421, 4, 5 },
2117
17.6k
    {5142, 1426, 4, 5 },
2118
17.6k
    {5161, 1431, 4, 5 },
2119
    // Sparc_ORCCrr - 334
2120
17.6k
    {5180, 1436, 3, 3 },
2121
    // Sparc_ORri - 335
2122
17.6k
    {5187, 1439, 3, 2 },
2123
    // Sparc_ORrr - 336
2124
17.6k
    {5187, 1441, 3, 3 },
2125
    // Sparc_RESTORErr - 337
2126
17.6k
    {5198, 1444, 3, 3 },
2127
    // Sparc_RET - 338
2128
17.6k
    {5206, 1447, 1, 1 },
2129
    // Sparc_RETL - 339
2130
17.6k
    {5210, 1448, 1, 1 },
2131
    // Sparc_SAVErr - 340
2132
17.6k
    {5215, 1449, 3, 3 },
2133
    // Sparc_SUBCCri - 341
2134
17.6k
    {5220, 1452, 3, 2 },
2135
    // Sparc_SUBCCrr - 342
2136
17.6k
    {5220, 1454, 3, 3 },
2137
    // Sparc_TICCri - 343
2138
17.6k
    {5231, 1457, 3, 4 },
2139
17.6k
    {5243, 1461, 3, 4 },
2140
17.6k
    {5260, 1465, 3, 4 },
2141
17.6k
    {5272, 1469, 3, 4 },
2142
17.6k
    {5289, 1473, 3, 4 },
2143
17.6k
    {5302, 1477, 3, 4 },
2144
17.6k
    {5320, 1481, 3, 4 },
2145
17.6k
    {5332, 1485, 3, 4 },
2146
17.6k
    {5349, 1489, 3, 4 },
2147
17.6k
    {5361, 1493, 3, 4 },
2148
17.6k
    {5378, 1497, 3, 4 },
2149
17.6k
    {5391, 1501, 3, 4 },
2150
17.6k
    {5409, 1505, 3, 4 },
2151
17.6k
    {5422, 1509, 3, 4 },
2152
17.6k
    {5440, 1513, 3, 4 },
2153
17.6k
    {5452, 1517, 3, 4 },
2154
17.6k
    {5469, 1521, 3, 4 },
2155
17.6k
    {5482, 1525, 3, 4 },
2156
17.6k
    {5500, 1529, 3, 4 },
2157
17.6k
    {5514, 1533, 3, 4 },
2158
17.6k
    {5533, 1537, 3, 4 },
2159
17.6k
    {5546, 1541, 3, 4 },
2160
17.6k
    {5564, 1545, 3, 4 },
2161
17.6k
    {5577, 1549, 3, 4 },
2162
17.6k
    {5595, 1553, 3, 4 },
2163
17.6k
    {5609, 1557, 3, 4 },
2164
17.6k
    {5628, 1561, 3, 4 },
2165
17.6k
    {5642, 1565, 3, 4 },
2166
17.6k
    {5661, 1569, 3, 4 },
2167
17.6k
    {5674, 1573, 3, 4 },
2168
17.6k
    {5692, 1577, 3, 4 },
2169
17.6k
    {5705, 1581, 3, 4 },
2170
    // Sparc_TICCrr - 375
2171
17.6k
    {5231, 1585, 3, 4 },
2172
17.6k
    {5243, 1589, 3, 4 },
2173
17.6k
    {5260, 1593, 3, 4 },
2174
17.6k
    {5272, 1597, 3, 4 },
2175
17.6k
    {5289, 1601, 3, 4 },
2176
17.6k
    {5302, 1605, 3, 4 },
2177
17.6k
    {5320, 1609, 3, 4 },
2178
17.6k
    {5332, 1613, 3, 4 },
2179
17.6k
    {5349, 1617, 3, 4 },
2180
17.6k
    {5361, 1621, 3, 4 },
2181
17.6k
    {5378, 1625, 3, 4 },
2182
17.6k
    {5391, 1629, 3, 4 },
2183
17.6k
    {5409, 1633, 3, 4 },
2184
17.6k
    {5422, 1637, 3, 4 },
2185
17.6k
    {5440, 1641, 3, 4 },
2186
17.6k
    {5452, 1645, 3, 4 },
2187
17.6k
    {5469, 1649, 3, 4 },
2188
17.6k
    {5482, 1653, 3, 4 },
2189
17.6k
    {5500, 1657, 3, 4 },
2190
17.6k
    {5514, 1661, 3, 4 },
2191
17.6k
    {5533, 1665, 3, 4 },
2192
17.6k
    {5546, 1669, 3, 4 },
2193
17.6k
    {5564, 1673, 3, 4 },
2194
17.6k
    {5577, 1677, 3, 4 },
2195
17.6k
    {5595, 1681, 3, 4 },
2196
17.6k
    {5609, 1685, 3, 4 },
2197
17.6k
    {5628, 1689, 3, 4 },
2198
17.6k
    {5642, 1693, 3, 4 },
2199
17.6k
    {5661, 1697, 3, 4 },
2200
17.6k
    {5674, 1701, 3, 4 },
2201
17.6k
    {5692, 1705, 3, 4 },
2202
17.6k
    {5705, 1709, 3, 4 },
2203
    // Sparc_TRAPri - 407
2204
17.6k
    {5723, 1713, 3, 3 },
2205
17.6k
    {5729, 1716, 3, 3 },
2206
17.6k
    {5740, 1719, 3, 3 },
2207
17.6k
    {5746, 1722, 3, 3 },
2208
17.6k
    {5757, 1725, 3, 3 },
2209
17.6k
    {5764, 1728, 3, 3 },
2210
17.6k
    {5776, 1731, 3, 3 },
2211
17.6k
    {5782, 1734, 3, 3 },
2212
17.6k
    {5793, 1737, 3, 3 },
2213
17.6k
    {5799, 1740, 3, 3 },
2214
17.6k
    {5810, 1743, 3, 3 },
2215
17.6k
    {5817, 1746, 3, 3 },
2216
17.6k
    {5829, 1749, 3, 3 },
2217
17.6k
    {5836, 1752, 3, 3 },
2218
17.6k
    {5848, 1755, 3, 3 },
2219
17.6k
    {5854, 1758, 3, 3 },
2220
17.6k
    {5865, 1761, 3, 3 },
2221
17.6k
    {5872, 1764, 3, 3 },
2222
17.6k
    {5884, 1767, 3, 3 },
2223
17.6k
    {5892, 1770, 3, 3 },
2224
17.6k
    {5905, 1773, 3, 3 },
2225
17.6k
    {5912, 1776, 3, 3 },
2226
17.6k
    {5924, 1779, 3, 3 },
2227
17.6k
    {5931, 1782, 3, 3 },
2228
17.6k
    {5943, 1785, 3, 3 },
2229
17.6k
    {5951, 1788, 3, 3 },
2230
17.6k
    {5964, 1791, 3, 3 },
2231
17.6k
    {5972, 1794, 3, 3 },
2232
17.6k
    {5985, 1797, 3, 3 },
2233
17.6k
    {5992, 1800, 3, 3 },
2234
17.6k
    {6004, 1803, 3, 3 },
2235
17.6k
    {6011, 1806, 3, 3 },
2236
    // Sparc_TRAPrr - 439
2237
17.6k
    {5723, 1809, 3, 3 },
2238
17.6k
    {5729, 1812, 3, 3 },
2239
17.6k
    {5740, 1815, 3, 3 },
2240
17.6k
    {5746, 1818, 3, 3 },
2241
17.6k
    {5757, 1821, 3, 3 },
2242
17.6k
    {5764, 1824, 3, 3 },
2243
17.6k
    {5776, 1827, 3, 3 },
2244
17.6k
    {5782, 1830, 3, 3 },
2245
17.6k
    {5793, 1833, 3, 3 },
2246
17.6k
    {5799, 1836, 3, 3 },
2247
17.6k
    {5810, 1839, 3, 3 },
2248
17.6k
    {5817, 1842, 3, 3 },
2249
17.6k
    {5829, 1845, 3, 3 },
2250
17.6k
    {5836, 1848, 3, 3 },
2251
17.6k
    {5848, 1851, 3, 3 },
2252
17.6k
    {5854, 1854, 3, 3 },
2253
17.6k
    {5865, 1857, 3, 3 },
2254
17.6k
    {5872, 1860, 3, 3 },
2255
17.6k
    {5884, 1863, 3, 3 },
2256
17.6k
    {5892, 1866, 3, 3 },
2257
17.6k
    {5905, 1869, 3, 3 },
2258
17.6k
    {5912, 1872, 3, 3 },
2259
17.6k
    {5924, 1875, 3, 3 },
2260
17.6k
    {5931, 1878, 3, 3 },
2261
17.6k
    {5943, 1881, 3, 3 },
2262
17.6k
    {5951, 1884, 3, 3 },
2263
17.6k
    {5964, 1887, 3, 3 },
2264
17.6k
    {5972, 1890, 3, 3 },
2265
17.6k
    {5985, 1893, 3, 3 },
2266
17.6k
    {5992, 1896, 3, 3 },
2267
17.6k
    {6004, 1899, 3, 3 },
2268
17.6k
    {6011, 1902, 3, 3 },
2269
    // Sparc_TXCCri - 471
2270
17.6k
    {6023, 1905, 3, 4 },
2271
17.6k
    {6035, 1909, 3, 4 },
2272
17.6k
    {6052, 1913, 3, 4 },
2273
17.6k
    {6064, 1917, 3, 4 },
2274
17.6k
    {6081, 1921, 3, 4 },
2275
17.6k
    {6094, 1925, 3, 4 },
2276
17.6k
    {6112, 1929, 3, 4 },
2277
17.6k
    {6124, 1933, 3, 4 },
2278
17.6k
    {6141, 1937, 3, 4 },
2279
17.6k
    {6153, 1941, 3, 4 },
2280
17.6k
    {6170, 1945, 3, 4 },
2281
17.6k
    {6183, 1949, 3, 4 },
2282
17.6k
    {6201, 1953, 3, 4 },
2283
17.6k
    {6214, 1957, 3, 4 },
2284
17.6k
    {6232, 1961, 3, 4 },
2285
17.6k
    {6244, 1965, 3, 4 },
2286
17.6k
    {6261, 1969, 3, 4 },
2287
17.6k
    {6274, 1973, 3, 4 },
2288
17.6k
    {6292, 1977, 3, 4 },
2289
17.6k
    {6306, 1981, 3, 4 },
2290
17.6k
    {6325, 1985, 3, 4 },
2291
17.6k
    {6338, 1989, 3, 4 },
2292
17.6k
    {6356, 1993, 3, 4 },
2293
17.6k
    {6369, 1997, 3, 4 },
2294
17.6k
    {6387, 2001, 3, 4 },
2295
17.6k
    {6401, 2005, 3, 4 },
2296
17.6k
    {6420, 2009, 3, 4 },
2297
17.6k
    {6434, 2013, 3, 4 },
2298
17.6k
    {6453, 2017, 3, 4 },
2299
17.6k
    {6466, 2021, 3, 4 },
2300
17.6k
    {6484, 2025, 3, 4 },
2301
17.6k
    {6497, 2029, 3, 4 },
2302
    // Sparc_TXCCrr - 503
2303
17.6k
    {6023, 2033, 3, 4 },
2304
17.6k
    {6035, 2037, 3, 4 },
2305
17.6k
    {6052, 2041, 3, 4 },
2306
17.6k
    {6064, 2045, 3, 4 },
2307
17.6k
    {6081, 2049, 3, 4 },
2308
17.6k
    {6094, 2053, 3, 4 },
2309
17.6k
    {6112, 2057, 3, 4 },
2310
17.6k
    {6124, 2061, 3, 4 },
2311
17.6k
    {6141, 2065, 3, 4 },
2312
17.6k
    {6153, 2069, 3, 4 },
2313
17.6k
    {6170, 2073, 3, 4 },
2314
17.6k
    {6183, 2077, 3, 4 },
2315
17.6k
    {6201, 2081, 3, 4 },
2316
17.6k
    {6214, 2085, 3, 4 },
2317
17.6k
    {6232, 2089, 3, 4 },
2318
17.6k
    {6244, 2093, 3, 4 },
2319
17.6k
    {6261, 2097, 3, 4 },
2320
17.6k
    {6274, 2101, 3, 4 },
2321
17.6k
    {6292, 2105, 3, 4 },
2322
17.6k
    {6306, 2109, 3, 4 },
2323
17.6k
    {6325, 2113, 3, 4 },
2324
17.6k
    {6338, 2117, 3, 4 },
2325
17.6k
    {6356, 2121, 3, 4 },
2326
17.6k
    {6369, 2125, 3, 4 },
2327
17.6k
    {6387, 2129, 3, 4 },
2328
17.6k
    {6401, 2133, 3, 4 },
2329
17.6k
    {6420, 2137, 3, 4 },
2330
17.6k
    {6434, 2141, 3, 4 },
2331
17.6k
    {6453, 2145, 3, 4 },
2332
17.6k
    {6466, 2149, 3, 4 },
2333
17.6k
    {6484, 2153, 3, 4 },
2334
17.6k
    {6497, 2157, 3, 4 },
2335
    // Sparc_V9FCMPD - 535
2336
17.6k
    {6515, 2161, 3, 3 },
2337
    // Sparc_V9FCMPED - 536
2338
17.6k
    {6528, 2164, 3, 3 },
2339
    // Sparc_V9FCMPEQ - 537
2340
17.6k
    {6542, 2167, 3, 3 },
2341
    // Sparc_V9FCMPES - 538
2342
17.6k
    {6556, 2170, 3, 3 },
2343
    // Sparc_V9FCMPQ - 539
2344
17.6k
    {6570, 2173, 3, 3 },
2345
    // Sparc_V9FCMPS - 540
2346
17.6k
    {6583, 2176, 3, 3 },
2347
    // Sparc_V9FMOVD_FCC - 541
2348
17.6k
    {6596, 2179, 5, 6 },
2349
17.6k
    {6614, 2185, 5, 6 },
2350
17.6k
    {6632, 2191, 5, 6 },
2351
17.6k
    {6650, 2197, 5, 6 },
2352
17.6k
    {6668, 2203, 5, 6 },
2353
17.6k
    {6687, 2209, 5, 6 },
2354
17.6k
    {6705, 2215, 5, 6 },
2355
17.6k
    {6724, 2221, 5, 6 },
2356
17.6k
    {6743, 2227, 5, 6 },
2357
17.6k
    {6762, 2233, 5, 6 },
2358
17.6k
    {6780, 2239, 5, 6 },
2359
17.6k
    {6799, 2245, 5, 6 },
2360
17.6k
    {6818, 2251, 5, 6 },
2361
17.6k
    {6838, 2257, 5, 6 },
2362
17.6k
    {6857, 2263, 5, 6 },
2363
17.6k
    {6877, 2269, 5, 6 },
2364
    // Sparc_V9FMOVQ_FCC - 557
2365
17.6k
    {6895, 2275, 5, 6 },
2366
17.6k
    {6913, 2281, 5, 6 },
2367
17.6k
    {6931, 2287, 5, 6 },
2368
17.6k
    {6949, 2293, 5, 6 },
2369
17.6k
    {6967, 2299, 5, 6 },
2370
17.6k
    {6986, 2305, 5, 6 },
2371
17.6k
    {7004, 2311, 5, 6 },
2372
17.6k
    {7023, 2317, 5, 6 },
2373
17.6k
    {7042, 2323, 5, 6 },
2374
17.6k
    {7061, 2329, 5, 6 },
2375
17.6k
    {7079, 2335, 5, 6 },
2376
17.6k
    {7098, 2341, 5, 6 },
2377
17.6k
    {7117, 2347, 5, 6 },
2378
17.6k
    {7137, 2353, 5, 6 },
2379
17.6k
    {7156, 2359, 5, 6 },
2380
17.6k
    {7176, 2365, 5, 6 },
2381
    // Sparc_V9FMOVS_FCC - 573
2382
17.6k
    {7194, 2371, 5, 6 },
2383
17.6k
    {7212, 2377, 5, 6 },
2384
17.6k
    {7230, 2383, 5, 6 },
2385
17.6k
    {7248, 2389, 5, 6 },
2386
17.6k
    {7266, 2395, 5, 6 },
2387
17.6k
    {7285, 2401, 5, 6 },
2388
17.6k
    {7303, 2407, 5, 6 },
2389
17.6k
    {7322, 2413, 5, 6 },
2390
17.6k
    {7341, 2419, 5, 6 },
2391
17.6k
    {7360, 2425, 5, 6 },
2392
17.6k
    {7378, 2431, 5, 6 },
2393
17.6k
    {7397, 2437, 5, 6 },
2394
17.6k
    {7416, 2443, 5, 6 },
2395
17.6k
    {7436, 2449, 5, 6 },
2396
17.6k
    {7455, 2455, 5, 6 },
2397
17.6k
    {7475, 2461, 5, 6 },
2398
    // Sparc_V9MOVFCCri - 589
2399
17.6k
    {7493, 2467, 5, 6 },
2400
17.6k
    {7509, 2473, 5, 6 },
2401
17.6k
    {7525, 2479, 5, 6 },
2402
17.6k
    {7541, 2485, 5, 6 },
2403
17.6k
    {7557, 2491, 5, 6 },
2404
17.6k
    {7574, 2497, 5, 6 },
2405
17.6k
    {7590, 2503, 5, 6 },
2406
17.6k
    {7607, 2509, 5, 6 },
2407
17.6k
    {7624, 2515, 5, 6 },
2408
17.6k
    {7641, 2521, 5, 6 },
2409
17.6k
    {7657, 2527, 5, 6 },
2410
17.6k
    {7674, 2533, 5, 6 },
2411
17.6k
    {7691, 2539, 5, 6 },
2412
17.6k
    {7709, 2545, 5, 6 },
2413
17.6k
    {7726, 2551, 5, 6 },
2414
17.6k
    {7744, 2557, 5, 6 },
2415
    // Sparc_V9MOVFCCrr - 605
2416
17.6k
    {7493, 2563, 5, 6 },
2417
17.6k
    {7509, 2569, 5, 6 },
2418
17.6k
    {7525, 2575, 5, 6 },
2419
17.6k
    {7541, 2581, 5, 6 },
2420
17.6k
    {7557, 2587, 5, 6 },
2421
17.6k
    {7574, 2593, 5, 6 },
2422
17.6k
    {7590, 2599, 5, 6 },
2423
17.6k
    {7607, 2605, 5, 6 },
2424
17.6k
    {7624, 2611, 5, 6 },
2425
17.6k
    {7641, 2617, 5, 6 },
2426
17.6k
    {7657, 2623, 5, 6 },
2427
17.6k
    {7674, 2629, 5, 6 },
2428
17.6k
    {7691, 2635, 5, 6 },
2429
17.6k
    {7709, 2641, 5, 6 },
2430
17.6k
    {7726, 2647, 5, 6 },
2431
17.6k
    {7744, 2653, 5, 6 },
2432
17.6k
  {0},  };
2433
2434
17.6k
  static const AliasPatternCond Conds[] = {
2435
    // (BCOND brtarget:$imm, 8) - 0
2436
17.6k
    {AliasPatternCond_K_Ignore, 0},
2437
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2438
    // (BCOND brtarget:$imm, 0) - 2
2439
17.6k
    {AliasPatternCond_K_Ignore, 0},
2440
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2441
    // (BCOND brtarget:$imm, 9) - 4
2442
17.6k
    {AliasPatternCond_K_Ignore, 0},
2443
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2444
    // (BCOND brtarget:$imm, 1) - 6
2445
17.6k
    {AliasPatternCond_K_Ignore, 0},
2446
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2447
    // (BCOND brtarget:$imm, 10) - 8
2448
17.6k
    {AliasPatternCond_K_Ignore, 0},
2449
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2450
    // (BCOND brtarget:$imm, 2) - 10
2451
17.6k
    {AliasPatternCond_K_Ignore, 0},
2452
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2453
    // (BCOND brtarget:$imm, 11) - 12
2454
17.6k
    {AliasPatternCond_K_Ignore, 0},
2455
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2456
    // (BCOND brtarget:$imm, 3) - 14
2457
17.6k
    {AliasPatternCond_K_Ignore, 0},
2458
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2459
    // (BCOND brtarget:$imm, 12) - 16
2460
17.6k
    {AliasPatternCond_K_Ignore, 0},
2461
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2462
    // (BCOND brtarget:$imm, 4) - 18
2463
17.6k
    {AliasPatternCond_K_Ignore, 0},
2464
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2465
    // (BCOND brtarget:$imm, 13) - 20
2466
17.6k
    {AliasPatternCond_K_Ignore, 0},
2467
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2468
    // (BCOND brtarget:$imm, 5) - 22
2469
17.6k
    {AliasPatternCond_K_Ignore, 0},
2470
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2471
    // (BCOND brtarget:$imm, 14) - 24
2472
17.6k
    {AliasPatternCond_K_Ignore, 0},
2473
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2474
    // (BCOND brtarget:$imm, 6) - 26
2475
17.6k
    {AliasPatternCond_K_Ignore, 0},
2476
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2477
    // (BCOND brtarget:$imm, 15) - 28
2478
17.6k
    {AliasPatternCond_K_Ignore, 0},
2479
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2480
    // (BCOND brtarget:$imm, 7) - 30
2481
17.6k
    {AliasPatternCond_K_Ignore, 0},
2482
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2483
    // (BCONDA brtarget:$imm, 8) - 32
2484
17.6k
    {AliasPatternCond_K_Ignore, 0},
2485
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2486
    // (BCONDA brtarget:$imm, 0) - 34
2487
17.6k
    {AliasPatternCond_K_Ignore, 0},
2488
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2489
    // (BCONDA brtarget:$imm, 9) - 36
2490
17.6k
    {AliasPatternCond_K_Ignore, 0},
2491
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2492
    // (BCONDA brtarget:$imm, 1) - 38
2493
17.6k
    {AliasPatternCond_K_Ignore, 0},
2494
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2495
    // (BCONDA brtarget:$imm, 10) - 40
2496
17.6k
    {AliasPatternCond_K_Ignore, 0},
2497
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2498
    // (BCONDA brtarget:$imm, 2) - 42
2499
17.6k
    {AliasPatternCond_K_Ignore, 0},
2500
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2501
    // (BCONDA brtarget:$imm, 11) - 44
2502
17.6k
    {AliasPatternCond_K_Ignore, 0},
2503
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2504
    // (BCONDA brtarget:$imm, 3) - 46
2505
17.6k
    {AliasPatternCond_K_Ignore, 0},
2506
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2507
    // (BCONDA brtarget:$imm, 12) - 48
2508
17.6k
    {AliasPatternCond_K_Ignore, 0},
2509
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2510
    // (BCONDA brtarget:$imm, 4) - 50
2511
17.6k
    {AliasPatternCond_K_Ignore, 0},
2512
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2513
    // (BCONDA brtarget:$imm, 13) - 52
2514
17.6k
    {AliasPatternCond_K_Ignore, 0},
2515
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2516
    // (BCONDA brtarget:$imm, 5) - 54
2517
17.6k
    {AliasPatternCond_K_Ignore, 0},
2518
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2519
    // (BCONDA brtarget:$imm, 14) - 56
2520
17.6k
    {AliasPatternCond_K_Ignore, 0},
2521
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2522
    // (BCONDA brtarget:$imm, 6) - 58
2523
17.6k
    {AliasPatternCond_K_Ignore, 0},
2524
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2525
    // (BCONDA brtarget:$imm, 15) - 60
2526
17.6k
    {AliasPatternCond_K_Ignore, 0},
2527
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2528
    // (BCONDA brtarget:$imm, 7) - 62
2529
17.6k
    {AliasPatternCond_K_Ignore, 0},
2530
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2531
    // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2532
17.6k
    {AliasPatternCond_K_Ignore, 0},
2533
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2534
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2535
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2536
    // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2537
17.6k
    {AliasPatternCond_K_Ignore, 0},
2538
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2539
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2540
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2541
    // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2542
17.6k
    {AliasPatternCond_K_Ignore, 0},
2543
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2544
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2545
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2546
    // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2547
17.6k
    {AliasPatternCond_K_Ignore, 0},
2548
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2549
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2550
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2551
    // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2552
17.6k
    {AliasPatternCond_K_Ignore, 0},
2553
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2554
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2555
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2556
    // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2557
17.6k
    {AliasPatternCond_K_Ignore, 0},
2558
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2559
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2560
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2561
    // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2562
17.6k
    {AliasPatternCond_K_Ignore, 0},
2563
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2564
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2565
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2566
    // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2567
17.6k
    {AliasPatternCond_K_Ignore, 0},
2568
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2569
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2570
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2571
    // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2572
17.6k
    {AliasPatternCond_K_Ignore, 0},
2573
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2574
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2575
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2576
    // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2577
17.6k
    {AliasPatternCond_K_Ignore, 0},
2578
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2579
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2580
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2581
    // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2582
17.6k
    {AliasPatternCond_K_Ignore, 0},
2583
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2584
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2585
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2586
    // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2587
17.6k
    {AliasPatternCond_K_Ignore, 0},
2588
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2589
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2590
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2591
    // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2592
17.6k
    {AliasPatternCond_K_Ignore, 0},
2593
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2594
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2595
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2596
    // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2597
17.6k
    {AliasPatternCond_K_Ignore, 0},
2598
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2599
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2600
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2601
    // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2602
17.6k
    {AliasPatternCond_K_Ignore, 0},
2603
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2604
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2605
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2606
    // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2607
17.6k
    {AliasPatternCond_K_Ignore, 0},
2608
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2609
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2610
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2611
    // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2612
17.6k
    {AliasPatternCond_K_Ignore, 0},
2613
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2614
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2615
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2616
    // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
2617
17.6k
    {AliasPatternCond_K_Ignore, 0},
2618
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2619
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2620
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2621
    // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
2622
17.6k
    {AliasPatternCond_K_Ignore, 0},
2623
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2624
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2625
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2626
    // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
2627
17.6k
    {AliasPatternCond_K_Ignore, 0},
2628
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2629
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2630
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2631
    // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
2632
17.6k
    {AliasPatternCond_K_Ignore, 0},
2633
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2634
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2635
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2636
    // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
2637
17.6k
    {AliasPatternCond_K_Ignore, 0},
2638
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2639
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2640
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2641
    // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
2642
17.6k
    {AliasPatternCond_K_Ignore, 0},
2643
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2644
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2645
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2646
    // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
2647
17.6k
    {AliasPatternCond_K_Ignore, 0},
2648
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2649
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2650
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2651
    // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
2652
17.6k
    {AliasPatternCond_K_Ignore, 0},
2653
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2654
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2655
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2656
    // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
2657
17.6k
    {AliasPatternCond_K_Ignore, 0},
2658
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2659
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2660
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2661
    // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
2662
17.6k
    {AliasPatternCond_K_Ignore, 0},
2663
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2664
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2665
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2666
    // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
2667
17.6k
    {AliasPatternCond_K_Ignore, 0},
2668
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2669
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2670
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2671
    // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
2672
17.6k
    {AliasPatternCond_K_Ignore, 0},
2673
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2674
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2675
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2676
    // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
2677
17.6k
    {AliasPatternCond_K_Ignore, 0},
2678
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2679
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2680
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2681
    // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
2682
17.6k
    {AliasPatternCond_K_Ignore, 0},
2683
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2684
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2685
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2686
    // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
2687
17.6k
    {AliasPatternCond_K_Ignore, 0},
2688
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2689
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2690
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2691
    // (BPICCANT brtarget:$imm, 8) - 192
2692
17.6k
    {AliasPatternCond_K_Ignore, 0},
2693
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2694
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2695
    // (BPICCANT brtarget:$imm, 0) - 195
2696
17.6k
    {AliasPatternCond_K_Ignore, 0},
2697
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2698
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2699
    // (BPICCANT brtarget:$imm, 9) - 198
2700
17.6k
    {AliasPatternCond_K_Ignore, 0},
2701
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2702
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2703
    // (BPICCANT brtarget:$imm, 1) - 201
2704
17.6k
    {AliasPatternCond_K_Ignore, 0},
2705
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2706
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2707
    // (BPICCANT brtarget:$imm, 10) - 204
2708
17.6k
    {AliasPatternCond_K_Ignore, 0},
2709
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2710
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2711
    // (BPICCANT brtarget:$imm, 2) - 207
2712
17.6k
    {AliasPatternCond_K_Ignore, 0},
2713
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2714
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2715
    // (BPICCANT brtarget:$imm, 11) - 210
2716
17.6k
    {AliasPatternCond_K_Ignore, 0},
2717
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2718
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2719
    // (BPICCANT brtarget:$imm, 3) - 213
2720
17.6k
    {AliasPatternCond_K_Ignore, 0},
2721
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2722
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2723
    // (BPICCANT brtarget:$imm, 12) - 216
2724
17.6k
    {AliasPatternCond_K_Ignore, 0},
2725
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2726
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2727
    // (BPICCANT brtarget:$imm, 4) - 219
2728
17.6k
    {AliasPatternCond_K_Ignore, 0},
2729
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2730
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2731
    // (BPICCANT brtarget:$imm, 13) - 222
2732
17.6k
    {AliasPatternCond_K_Ignore, 0},
2733
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2734
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2735
    // (BPICCANT brtarget:$imm, 5) - 225
2736
17.6k
    {AliasPatternCond_K_Ignore, 0},
2737
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2738
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2739
    // (BPICCANT brtarget:$imm, 14) - 228
2740
17.6k
    {AliasPatternCond_K_Ignore, 0},
2741
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2742
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2743
    // (BPICCANT brtarget:$imm, 6) - 231
2744
17.6k
    {AliasPatternCond_K_Ignore, 0},
2745
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2746
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2747
    // (BPICCANT brtarget:$imm, 15) - 234
2748
17.6k
    {AliasPatternCond_K_Ignore, 0},
2749
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2750
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2751
    // (BPICCANT brtarget:$imm, 7) - 237
2752
17.6k
    {AliasPatternCond_K_Ignore, 0},
2753
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2754
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2755
    // (BPICCNT brtarget:$imm, 8) - 240
2756
17.6k
    {AliasPatternCond_K_Ignore, 0},
2757
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2758
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2759
    // (BPICCNT brtarget:$imm, 0) - 243
2760
17.6k
    {AliasPatternCond_K_Ignore, 0},
2761
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2762
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2763
    // (BPICCNT brtarget:$imm, 9) - 246
2764
17.6k
    {AliasPatternCond_K_Ignore, 0},
2765
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2766
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2767
    // (BPICCNT brtarget:$imm, 1) - 249
2768
17.6k
    {AliasPatternCond_K_Ignore, 0},
2769
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2770
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2771
    // (BPICCNT brtarget:$imm, 10) - 252
2772
17.6k
    {AliasPatternCond_K_Ignore, 0},
2773
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2774
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2775
    // (BPICCNT brtarget:$imm, 2) - 255
2776
17.6k
    {AliasPatternCond_K_Ignore, 0},
2777
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2778
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2779
    // (BPICCNT brtarget:$imm, 11) - 258
2780
17.6k
    {AliasPatternCond_K_Ignore, 0},
2781
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2782
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2783
    // (BPICCNT brtarget:$imm, 3) - 261
2784
17.6k
    {AliasPatternCond_K_Ignore, 0},
2785
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2786
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2787
    // (BPICCNT brtarget:$imm, 12) - 264
2788
17.6k
    {AliasPatternCond_K_Ignore, 0},
2789
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2790
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2791
    // (BPICCNT brtarget:$imm, 4) - 267
2792
17.6k
    {AliasPatternCond_K_Ignore, 0},
2793
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2794
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2795
    // (BPICCNT brtarget:$imm, 13) - 270
2796
17.6k
    {AliasPatternCond_K_Ignore, 0},
2797
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2798
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2799
    // (BPICCNT brtarget:$imm, 5) - 273
2800
17.6k
    {AliasPatternCond_K_Ignore, 0},
2801
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2802
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2803
    // (BPICCNT brtarget:$imm, 14) - 276
2804
17.6k
    {AliasPatternCond_K_Ignore, 0},
2805
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2806
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2807
    // (BPICCNT brtarget:$imm, 6) - 279
2808
17.6k
    {AliasPatternCond_K_Ignore, 0},
2809
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2810
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2811
    // (BPICCNT brtarget:$imm, 15) - 282
2812
17.6k
    {AliasPatternCond_K_Ignore, 0},
2813
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2814
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2815
    // (BPICCNT brtarget:$imm, 7) - 285
2816
17.6k
    {AliasPatternCond_K_Ignore, 0},
2817
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2818
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2819
    // (BPRANT bprtarget16:$imm, 1, I64Regs:$rs1) - 288
2820
17.6k
    {AliasPatternCond_K_Ignore, 0},
2821
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2822
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2823
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2824
    // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 292
2825
17.6k
    {AliasPatternCond_K_Ignore, 0},
2826
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2827
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2828
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2829
    // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 296
2830
17.6k
    {AliasPatternCond_K_Ignore, 0},
2831
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2832
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2833
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2834
    // (BPRANT bprtarget16:$imm, 5, I64Regs:$rs1) - 300
2835
17.6k
    {AliasPatternCond_K_Ignore, 0},
2836
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2837
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2838
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2839
    // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 304
2840
17.6k
    {AliasPatternCond_K_Ignore, 0},
2841
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2842
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2843
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2844
    // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 308
2845
17.6k
    {AliasPatternCond_K_Ignore, 0},
2846
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2847
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2848
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2849
    // (BPRNT bprtarget16:$imm, 1, I64Regs:$rs1) - 312
2850
17.6k
    {AliasPatternCond_K_Ignore, 0},
2851
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2852
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2853
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2854
    // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 316
2855
17.6k
    {AliasPatternCond_K_Ignore, 0},
2856
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2857
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2858
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2859
    // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 320
2860
17.6k
    {AliasPatternCond_K_Ignore, 0},
2861
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2862
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2863
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2864
    // (BPRNT bprtarget16:$imm, 5, I64Regs:$rs1) - 324
2865
17.6k
    {AliasPatternCond_K_Ignore, 0},
2866
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2867
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2868
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2869
    // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 328
2870
17.6k
    {AliasPatternCond_K_Ignore, 0},
2871
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2872
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2873
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2874
    // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 332
2875
17.6k
    {AliasPatternCond_K_Ignore, 0},
2876
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2877
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2878
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2879
    // (BPXCCANT brtarget:$imm, 8) - 336
2880
17.6k
    {AliasPatternCond_K_Ignore, 0},
2881
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2882
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2883
    // (BPXCCANT brtarget:$imm, 0) - 339
2884
17.6k
    {AliasPatternCond_K_Ignore, 0},
2885
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2886
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2887
    // (BPXCCANT brtarget:$imm, 9) - 342
2888
17.6k
    {AliasPatternCond_K_Ignore, 0},
2889
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2890
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2891
    // (BPXCCANT brtarget:$imm, 1) - 345
2892
17.6k
    {AliasPatternCond_K_Ignore, 0},
2893
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2894
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2895
    // (BPXCCANT brtarget:$imm, 10) - 348
2896
17.6k
    {AliasPatternCond_K_Ignore, 0},
2897
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2898
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2899
    // (BPXCCANT brtarget:$imm, 2) - 351
2900
17.6k
    {AliasPatternCond_K_Ignore, 0},
2901
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2902
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2903
    // (BPXCCANT brtarget:$imm, 11) - 354
2904
17.6k
    {AliasPatternCond_K_Ignore, 0},
2905
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2906
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2907
    // (BPXCCANT brtarget:$imm, 3) - 357
2908
17.6k
    {AliasPatternCond_K_Ignore, 0},
2909
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2910
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2911
    // (BPXCCANT brtarget:$imm, 12) - 360
2912
17.6k
    {AliasPatternCond_K_Ignore, 0},
2913
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2914
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2915
    // (BPXCCANT brtarget:$imm, 4) - 363
2916
17.6k
    {AliasPatternCond_K_Ignore, 0},
2917
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2918
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2919
    // (BPXCCANT brtarget:$imm, 13) - 366
2920
17.6k
    {AliasPatternCond_K_Ignore, 0},
2921
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2922
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2923
    // (BPXCCANT brtarget:$imm, 5) - 369
2924
17.6k
    {AliasPatternCond_K_Ignore, 0},
2925
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2926
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2927
    // (BPXCCANT brtarget:$imm, 14) - 372
2928
17.6k
    {AliasPatternCond_K_Ignore, 0},
2929
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2930
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2931
    // (BPXCCANT brtarget:$imm, 6) - 375
2932
17.6k
    {AliasPatternCond_K_Ignore, 0},
2933
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2934
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2935
    // (BPXCCANT brtarget:$imm, 15) - 378
2936
17.6k
    {AliasPatternCond_K_Ignore, 0},
2937
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2938
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2939
    // (BPXCCANT brtarget:$imm, 7) - 381
2940
17.6k
    {AliasPatternCond_K_Ignore, 0},
2941
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2942
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2943
    // (BPXCCNT brtarget:$imm, 8) - 384
2944
17.6k
    {AliasPatternCond_K_Ignore, 0},
2945
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2946
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2947
    // (BPXCCNT brtarget:$imm, 0) - 387
2948
17.6k
    {AliasPatternCond_K_Ignore, 0},
2949
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2950
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2951
    // (BPXCCNT brtarget:$imm, 9) - 390
2952
17.6k
    {AliasPatternCond_K_Ignore, 0},
2953
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2954
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2955
    // (BPXCCNT brtarget:$imm, 1) - 393
2956
17.6k
    {AliasPatternCond_K_Ignore, 0},
2957
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2958
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2959
    // (BPXCCNT brtarget:$imm, 10) - 396
2960
17.6k
    {AliasPatternCond_K_Ignore, 0},
2961
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2962
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2963
    // (BPXCCNT brtarget:$imm, 2) - 399
2964
17.6k
    {AliasPatternCond_K_Ignore, 0},
2965
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2966
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2967
    // (BPXCCNT brtarget:$imm, 11) - 402
2968
17.6k
    {AliasPatternCond_K_Ignore, 0},
2969
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2970
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2971
    // (BPXCCNT brtarget:$imm, 3) - 405
2972
17.6k
    {AliasPatternCond_K_Ignore, 0},
2973
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2974
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2975
    // (BPXCCNT brtarget:$imm, 12) - 408
2976
17.6k
    {AliasPatternCond_K_Ignore, 0},
2977
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2978
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2979
    // (BPXCCNT brtarget:$imm, 4) - 411
2980
17.6k
    {AliasPatternCond_K_Ignore, 0},
2981
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2982
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2983
    // (BPXCCNT brtarget:$imm, 13) - 414
2984
17.6k
    {AliasPatternCond_K_Ignore, 0},
2985
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2986
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2987
    // (BPXCCNT brtarget:$imm, 5) - 417
2988
17.6k
    {AliasPatternCond_K_Ignore, 0},
2989
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2990
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2991
    // (BPXCCNT brtarget:$imm, 14) - 420
2992
17.6k
    {AliasPatternCond_K_Ignore, 0},
2993
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2994
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2995
    // (BPXCCNT brtarget:$imm, 6) - 423
2996
17.6k
    {AliasPatternCond_K_Ignore, 0},
2997
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2998
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2999
    // (BPXCCNT brtarget:$imm, 15) - 426
3000
17.6k
    {AliasPatternCond_K_Ignore, 0},
3001
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3002
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3003
    // (BPXCCNT brtarget:$imm, 7) - 429
3004
17.6k
    {AliasPatternCond_K_Ignore, 0},
3005
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3006
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3007
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 432
3008
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3009
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3010
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3011
17.6k
    {AliasPatternCond_K_Ignore, 0},
3012
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)128},
3013
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3014
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 438
3015
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3016
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3017
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3018
17.6k
    {AliasPatternCond_K_Ignore, 0},
3019
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)136},
3020
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3021
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 444
3022
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3023
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3024
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3025
17.6k
    {AliasPatternCond_K_Ignore, 0},
3026
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)128},
3027
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3028
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 450
3029
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3030
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3031
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3032
17.6k
    {AliasPatternCond_K_Ignore, 0},
3033
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)136},
3034
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3035
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 456
3036
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3037
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3038
17.6k
    {AliasPatternCond_K_Ignore, 0},
3039
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3040
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3041
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 461
3042
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3043
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3044
17.6k
    {AliasPatternCond_K_Ignore, 0},
3045
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3046
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3047
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 466
3048
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3049
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3050
17.6k
    {AliasPatternCond_K_Ignore, 0},
3051
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3052
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3053
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 471
3054
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3055
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3056
17.6k
    {AliasPatternCond_K_Ignore, 0},
3057
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3058
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3059
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 476
3060
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3061
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3062
17.6k
    {AliasPatternCond_K_Ignore, 0},
3063
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3064
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3065
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 481
3066
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3067
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3068
17.6k
    {AliasPatternCond_K_Ignore, 0},
3069
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3070
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3071
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 486
3072
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3073
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3074
17.6k
    {AliasPatternCond_K_Ignore, 0},
3075
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3076
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3077
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 491
3078
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3079
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3080
17.6k
    {AliasPatternCond_K_Ignore, 0},
3081
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3082
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3083
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 496
3084
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3085
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3086
17.6k
    {AliasPatternCond_K_Ignore, 0},
3087
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3088
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3089
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 501
3090
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3091
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3092
17.6k
    {AliasPatternCond_K_Ignore, 0},
3093
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3094
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3095
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 506
3096
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3097
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3098
17.6k
    {AliasPatternCond_K_Ignore, 0},
3099
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3100
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3101
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 511
3102
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3103
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3104
17.6k
    {AliasPatternCond_K_Ignore, 0},
3105
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3106
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3107
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 516
3108
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3109
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3110
17.6k
    {AliasPatternCond_K_Ignore, 0},
3111
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3112
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3113
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 521
3114
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3115
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3116
17.6k
    {AliasPatternCond_K_Ignore, 0},
3117
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3118
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3119
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 526
3120
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3121
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3122
17.6k
    {AliasPatternCond_K_Ignore, 0},
3123
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3124
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3125
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 531
3126
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3127
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3128
17.6k
    {AliasPatternCond_K_Ignore, 0},
3129
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3130
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3131
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 536
3132
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3133
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3134
17.6k
    {AliasPatternCond_K_Ignore, 0},
3135
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3136
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3137
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 541
3138
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3139
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3140
17.6k
    {AliasPatternCond_K_Ignore, 0},
3141
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3142
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3143
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 546
3144
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3145
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3146
17.6k
    {AliasPatternCond_K_Ignore, 0},
3147
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3148
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3149
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 551
3150
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3151
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3152
17.6k
    {AliasPatternCond_K_Ignore, 0},
3153
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3154
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3155
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 556
3156
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3157
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3158
17.6k
    {AliasPatternCond_K_Ignore, 0},
3159
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3160
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3161
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 561
3162
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3163
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3164
17.6k
    {AliasPatternCond_K_Ignore, 0},
3165
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3166
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3167
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 566
3168
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3169
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3170
17.6k
    {AliasPatternCond_K_Ignore, 0},
3171
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3172
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3173
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 571
3174
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3175
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3176
17.6k
    {AliasPatternCond_K_Ignore, 0},
3177
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3178
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3179
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 576
3180
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3181
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3182
17.6k
    {AliasPatternCond_K_Ignore, 0},
3183
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3184
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3185
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 581
3186
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3187
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3188
17.6k
    {AliasPatternCond_K_Ignore, 0},
3189
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3190
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3191
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 586
3192
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3193
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3194
17.6k
    {AliasPatternCond_K_Ignore, 0},
3195
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3196
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3197
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 591
3198
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3199
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3200
17.6k
    {AliasPatternCond_K_Ignore, 0},
3201
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3202
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3203
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 596
3204
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3205
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3206
17.6k
    {AliasPatternCond_K_Ignore, 0},
3207
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3208
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3209
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 601
3210
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3211
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3212
17.6k
    {AliasPatternCond_K_Ignore, 0},
3213
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3214
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3215
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 606
3216
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3217
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3218
17.6k
    {AliasPatternCond_K_Ignore, 0},
3219
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3220
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3221
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 611
3222
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3223
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3224
17.6k
    {AliasPatternCond_K_Ignore, 0},
3225
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3226
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3227
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 616
3228
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3229
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3230
17.6k
    {AliasPatternCond_K_Ignore, 0},
3231
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3232
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3233
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 621
3234
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3235
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3236
17.6k
    {AliasPatternCond_K_Ignore, 0},
3237
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3238
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3239
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 626
3240
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3241
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3242
17.6k
    {AliasPatternCond_K_Ignore, 0},
3243
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3244
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3245
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 631
3246
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3247
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3248
17.6k
    {AliasPatternCond_K_Ignore, 0},
3249
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3250
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3251
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 636
3252
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3253
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3254
17.6k
    {AliasPatternCond_K_Ignore, 0},
3255
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3256
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3257
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 641
3258
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3259
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3260
17.6k
    {AliasPatternCond_K_Ignore, 0},
3261
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3262
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3263
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 646
3264
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3265
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3266
17.6k
    {AliasPatternCond_K_Ignore, 0},
3267
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3268
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3269
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 651
3270
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3271
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3272
17.6k
    {AliasPatternCond_K_Ignore, 0},
3273
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3274
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3275
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 656
3276
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3277
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3278
17.6k
    {AliasPatternCond_K_Ignore, 0},
3279
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3280
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3281
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 661
3282
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3283
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3284
17.6k
    {AliasPatternCond_K_Ignore, 0},
3285
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3286
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3287
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 666
3288
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3289
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3290
17.6k
    {AliasPatternCond_K_Ignore, 0},
3291
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3292
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3293
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 671
3294
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3295
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3296
17.6k
    {AliasPatternCond_K_Ignore, 0},
3297
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3298
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3299
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 676
3300
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3301
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3302
17.6k
    {AliasPatternCond_K_Ignore, 0},
3303
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3304
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3305
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 681
3306
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3307
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3308
17.6k
    {AliasPatternCond_K_Ignore, 0},
3309
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3310
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3311
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 686
3312
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3313
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3314
17.6k
    {AliasPatternCond_K_Ignore, 0},
3315
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3316
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3317
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 691
3318
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3319
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3320
17.6k
    {AliasPatternCond_K_Ignore, 0},
3321
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3322
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3323
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 696
3324
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3325
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3326
17.6k
    {AliasPatternCond_K_Ignore, 0},
3327
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3328
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3329
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 701
3330
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3331
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3332
17.6k
    {AliasPatternCond_K_Ignore, 0},
3333
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3334
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3335
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 706
3336
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3337
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3338
17.6k
    {AliasPatternCond_K_Ignore, 0},
3339
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3340
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3341
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 711
3342
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3343
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3344
17.6k
    {AliasPatternCond_K_Ignore, 0},
3345
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3346
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3347
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 716
3348
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3349
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3350
17.6k
    {AliasPatternCond_K_Ignore, 0},
3351
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3352
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3353
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 721
3354
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3355
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3356
17.6k
    {AliasPatternCond_K_Ignore, 0},
3357
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3358
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3359
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 726
3360
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3361
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3362
17.6k
    {AliasPatternCond_K_Ignore, 0},
3363
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3364
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3365
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 731
3366
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3367
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3368
17.6k
    {AliasPatternCond_K_Ignore, 0},
3369
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3370
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3371
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 736
3372
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3373
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3374
17.6k
    {AliasPatternCond_K_Ignore, 0},
3375
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3376
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3377
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 741
3378
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3379
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3380
17.6k
    {AliasPatternCond_K_Ignore, 0},
3381
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3382
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3383
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 746
3384
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3385
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3386
17.6k
    {AliasPatternCond_K_Ignore, 0},
3387
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3388
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3389
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 751
3390
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3391
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3392
17.6k
    {AliasPatternCond_K_Ignore, 0},
3393
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3394
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3395
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 756
3396
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3397
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3398
17.6k
    {AliasPatternCond_K_Ignore, 0},
3399
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3400
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3401
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 761
3402
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3403
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3404
17.6k
    {AliasPatternCond_K_Ignore, 0},
3405
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3406
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3407
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 766
3408
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3409
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3410
17.6k
    {AliasPatternCond_K_Ignore, 0},
3411
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3412
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3413
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 771
3414
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3415
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3416
17.6k
    {AliasPatternCond_K_Ignore, 0},
3417
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3418
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3419
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 1) - 776
3420
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3421
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3422
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3423
17.6k
    {AliasPatternCond_K_Ignore, 0},
3424
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3425
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3426
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 782
3427
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3428
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3429
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3430
17.6k
    {AliasPatternCond_K_Ignore, 0},
3431
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3432
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3433
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 788
3434
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3435
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3436
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3437
17.6k
    {AliasPatternCond_K_Ignore, 0},
3438
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3439
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3440
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 5) - 794
3441
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3442
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3443
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3444
17.6k
    {AliasPatternCond_K_Ignore, 0},
3445
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3446
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3447
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 800
3448
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3449
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3450
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3451
17.6k
    {AliasPatternCond_K_Ignore, 0},
3452
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3453
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3454
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 806
3455
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3456
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3457
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3458
17.6k
    {AliasPatternCond_K_Ignore, 0},
3459
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3460
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3461
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 1) - 812
3462
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3463
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3464
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3465
17.6k
    {AliasPatternCond_K_Ignore, 0},
3466
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3467
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3468
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 818
3469
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3470
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3471
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3472
17.6k
    {AliasPatternCond_K_Ignore, 0},
3473
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3474
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3475
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 824
3476
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3477
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3478
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3479
17.6k
    {AliasPatternCond_K_Ignore, 0},
3480
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3481
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3482
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 5) - 830
3483
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3484
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3485
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3486
17.6k
    {AliasPatternCond_K_Ignore, 0},
3487
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3488
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3489
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 836
3490
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3491
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3492
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3493
17.6k
    {AliasPatternCond_K_Ignore, 0},
3494
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3495
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3496
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 842
3497
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3498
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3499
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3500
17.6k
    {AliasPatternCond_K_Ignore, 0},
3501
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3502
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3503
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 1) - 848
3504
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3505
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3506
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3507
17.6k
    {AliasPatternCond_K_Ignore, 0},
3508
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3509
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3510
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 854
3511
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3512
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3513
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3514
17.6k
    {AliasPatternCond_K_Ignore, 0},
3515
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3516
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3517
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 860
3518
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3519
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3520
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3521
17.6k
    {AliasPatternCond_K_Ignore, 0},
3522
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3523
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3524
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 5) - 866
3525
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3526
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3527
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3528
17.6k
    {AliasPatternCond_K_Ignore, 0},
3529
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3530
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3531
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 872
3532
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3533
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3534
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3535
17.6k
    {AliasPatternCond_K_Ignore, 0},
3536
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3537
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3538
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 878
3539
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3540
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3541
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3542
17.6k
    {AliasPatternCond_K_Ignore, 0},
3543
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3544
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3545
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 884
3546
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3547
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3548
17.6k
    {AliasPatternCond_K_Ignore, 0},
3549
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3550
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3551
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 889
3552
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3553
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3554
17.6k
    {AliasPatternCond_K_Ignore, 0},
3555
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3556
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3557
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 894
3558
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3559
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3560
17.6k
    {AliasPatternCond_K_Ignore, 0},
3561
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3562
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3563
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 899
3564
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3565
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3566
17.6k
    {AliasPatternCond_K_Ignore, 0},
3567
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3568
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3569
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 904
3570
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3571
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3572
17.6k
    {AliasPatternCond_K_Ignore, 0},
3573
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3574
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3575
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 909
3576
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3577
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3578
17.6k
    {AliasPatternCond_K_Ignore, 0},
3579
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3580
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3581
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 914
3582
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3583
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3584
17.6k
    {AliasPatternCond_K_Ignore, 0},
3585
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3586
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3587
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 919
3588
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3589
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3590
17.6k
    {AliasPatternCond_K_Ignore, 0},
3591
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3592
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3593
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 924
3594
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3595
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3596
17.6k
    {AliasPatternCond_K_Ignore, 0},
3597
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3598
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3599
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 929
3600
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3601
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3602
17.6k
    {AliasPatternCond_K_Ignore, 0},
3603
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3604
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3605
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 934
3606
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3607
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3608
17.6k
    {AliasPatternCond_K_Ignore, 0},
3609
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3610
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3611
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 939
3612
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3613
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3614
17.6k
    {AliasPatternCond_K_Ignore, 0},
3615
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3616
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3617
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 944
3618
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3619
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3620
17.6k
    {AliasPatternCond_K_Ignore, 0},
3621
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3622
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3623
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 949
3624
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3625
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3626
17.6k
    {AliasPatternCond_K_Ignore, 0},
3627
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3628
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3629
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 954
3630
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3631
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3632
17.6k
    {AliasPatternCond_K_Ignore, 0},
3633
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3634
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3635
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 959
3636
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3637
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3638
17.6k
    {AliasPatternCond_K_Ignore, 0},
3639
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3640
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3641
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 964
3642
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3643
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3644
17.6k
    {AliasPatternCond_K_Ignore, 0},
3645
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3646
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3647
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 969
3648
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3649
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3650
17.6k
    {AliasPatternCond_K_Ignore, 0},
3651
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3652
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3653
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 974
3654
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3655
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3656
17.6k
    {AliasPatternCond_K_Ignore, 0},
3657
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3658
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3659
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 979
3660
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3661
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3662
17.6k
    {AliasPatternCond_K_Ignore, 0},
3663
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3664
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3665
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 984
3666
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3667
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3668
17.6k
    {AliasPatternCond_K_Ignore, 0},
3669
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3670
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3671
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 989
3672
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3673
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3674
17.6k
    {AliasPatternCond_K_Ignore, 0},
3675
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3676
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3677
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 994
3678
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3679
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3680
17.6k
    {AliasPatternCond_K_Ignore, 0},
3681
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3682
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3683
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 999
3684
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3685
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3686
17.6k
    {AliasPatternCond_K_Ignore, 0},
3687
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3688
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3689
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 1004
3690
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3691
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3692
17.6k
    {AliasPatternCond_K_Ignore, 0},
3693
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3694
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3695
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 1009
3696
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3697
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3698
17.6k
    {AliasPatternCond_K_Ignore, 0},
3699
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3700
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3701
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 1014
3702
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3703
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3704
17.6k
    {AliasPatternCond_K_Ignore, 0},
3705
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3706
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3707
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 1019
3708
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3709
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3710
17.6k
    {AliasPatternCond_K_Ignore, 0},
3711
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3712
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3713
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 1024
3714
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3715
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3716
17.6k
    {AliasPatternCond_K_Ignore, 0},
3717
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3718
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3719
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 1029
3720
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3721
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3722
17.6k
    {AliasPatternCond_K_Ignore, 0},
3723
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3724
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3725
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 1034
3726
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3727
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3728
17.6k
    {AliasPatternCond_K_Ignore, 0},
3729
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3730
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3731
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 1039
3732
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3733
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3734
17.6k
    {AliasPatternCond_K_Ignore, 0},
3735
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3736
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3737
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1044
3738
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3739
17.6k
    {AliasPatternCond_K_Ignore, 0},
3740
17.6k
    {AliasPatternCond_K_Ignore, 0},
3741
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3742
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3743
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1049
3744
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3745
17.6k
    {AliasPatternCond_K_Ignore, 0},
3746
17.6k
    {AliasPatternCond_K_Ignore, 0},
3747
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3748
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3749
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1054
3750
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3751
17.6k
    {AliasPatternCond_K_Ignore, 0},
3752
17.6k
    {AliasPatternCond_K_Ignore, 0},
3753
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3754
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3755
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1059
3756
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3757
17.6k
    {AliasPatternCond_K_Ignore, 0},
3758
17.6k
    {AliasPatternCond_K_Ignore, 0},
3759
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3760
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3761
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1064
3762
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3763
17.6k
    {AliasPatternCond_K_Ignore, 0},
3764
17.6k
    {AliasPatternCond_K_Ignore, 0},
3765
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3766
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3767
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1069
3768
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3769
17.6k
    {AliasPatternCond_K_Ignore, 0},
3770
17.6k
    {AliasPatternCond_K_Ignore, 0},
3771
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3772
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3773
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1074
3774
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3775
17.6k
    {AliasPatternCond_K_Ignore, 0},
3776
17.6k
    {AliasPatternCond_K_Ignore, 0},
3777
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3778
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3779
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1079
3780
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3781
17.6k
    {AliasPatternCond_K_Ignore, 0},
3782
17.6k
    {AliasPatternCond_K_Ignore, 0},
3783
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3784
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3785
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1084
3786
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3787
17.6k
    {AliasPatternCond_K_Ignore, 0},
3788
17.6k
    {AliasPatternCond_K_Ignore, 0},
3789
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3790
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3791
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1089
3792
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3793
17.6k
    {AliasPatternCond_K_Ignore, 0},
3794
17.6k
    {AliasPatternCond_K_Ignore, 0},
3795
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3796
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3797
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1094
3798
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3799
17.6k
    {AliasPatternCond_K_Ignore, 0},
3800
17.6k
    {AliasPatternCond_K_Ignore, 0},
3801
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3802
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3803
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1099
3804
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3805
17.6k
    {AliasPatternCond_K_Ignore, 0},
3806
17.6k
    {AliasPatternCond_K_Ignore, 0},
3807
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3808
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3809
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1104
3810
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3811
17.6k
    {AliasPatternCond_K_Ignore, 0},
3812
17.6k
    {AliasPatternCond_K_Ignore, 0},
3813
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3814
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3815
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1109
3816
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3817
17.6k
    {AliasPatternCond_K_Ignore, 0},
3818
17.6k
    {AliasPatternCond_K_Ignore, 0},
3819
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3820
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3821
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1114
3822
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3823
17.6k
    {AliasPatternCond_K_Ignore, 0},
3824
17.6k
    {AliasPatternCond_K_Ignore, 0},
3825
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3826
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3827
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1119
3828
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3829
17.6k
    {AliasPatternCond_K_Ignore, 0},
3830
17.6k
    {AliasPatternCond_K_Ignore, 0},
3831
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3832
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3833
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1124
3834
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3835
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3836
17.6k
    {AliasPatternCond_K_Ignore, 0},
3837
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3838
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3839
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1129
3840
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3841
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3842
17.6k
    {AliasPatternCond_K_Ignore, 0},
3843
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3844
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3845
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1134
3846
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3847
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3848
17.6k
    {AliasPatternCond_K_Ignore, 0},
3849
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3850
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3851
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1139
3852
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3853
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3854
17.6k
    {AliasPatternCond_K_Ignore, 0},
3855
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3856
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3857
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1144
3858
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3859
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3860
17.6k
    {AliasPatternCond_K_Ignore, 0},
3861
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3862
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3863
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1149
3864
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3865
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3866
17.6k
    {AliasPatternCond_K_Ignore, 0},
3867
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3868
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3869
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1154
3870
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3871
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3872
17.6k
    {AliasPatternCond_K_Ignore, 0},
3873
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3874
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3875
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1159
3876
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3877
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3878
17.6k
    {AliasPatternCond_K_Ignore, 0},
3879
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3880
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3881
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1164
3882
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3883
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3884
17.6k
    {AliasPatternCond_K_Ignore, 0},
3885
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3886
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3887
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1169
3888
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3889
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3890
17.6k
    {AliasPatternCond_K_Ignore, 0},
3891
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3892
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3893
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1174
3894
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3895
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3896
17.6k
    {AliasPatternCond_K_Ignore, 0},
3897
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3898
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3899
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1179
3900
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3901
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3902
17.6k
    {AliasPatternCond_K_Ignore, 0},
3903
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3904
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3905
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1184
3906
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3907
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3908
17.6k
    {AliasPatternCond_K_Ignore, 0},
3909
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3910
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3911
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1189
3912
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3913
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3914
17.6k
    {AliasPatternCond_K_Ignore, 0},
3915
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3916
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3917
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1194
3918
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3919
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3920
17.6k
    {AliasPatternCond_K_Ignore, 0},
3921
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3922
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3923
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1199
3924
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3925
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3926
17.6k
    {AliasPatternCond_K_Ignore, 0},
3927
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3928
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3929
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 1) - 1204
3930
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3931
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3932
17.6k
    {AliasPatternCond_K_Ignore, 0},
3933
17.6k
    {AliasPatternCond_K_Ignore, 0},
3934
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3935
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3936
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1210
3937
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3938
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3939
17.6k
    {AliasPatternCond_K_Ignore, 0},
3940
17.6k
    {AliasPatternCond_K_Ignore, 0},
3941
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3942
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3943
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1216
3944
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3945
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3946
17.6k
    {AliasPatternCond_K_Ignore, 0},
3947
17.6k
    {AliasPatternCond_K_Ignore, 0},
3948
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3949
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3950
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 5) - 1222
3951
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3952
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3953
17.6k
    {AliasPatternCond_K_Ignore, 0},
3954
17.6k
    {AliasPatternCond_K_Ignore, 0},
3955
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3956
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3957
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1228
3958
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3959
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3960
17.6k
    {AliasPatternCond_K_Ignore, 0},
3961
17.6k
    {AliasPatternCond_K_Ignore, 0},
3962
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3963
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3964
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1234
3965
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3966
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3967
17.6k
    {AliasPatternCond_K_Ignore, 0},
3968
17.6k
    {AliasPatternCond_K_Ignore, 0},
3969
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3970
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3971
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 1) - 1240
3972
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3973
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3974
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3975
17.6k
    {AliasPatternCond_K_Ignore, 0},
3976
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3977
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3978
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1246
3979
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3980
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3981
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3982
17.6k
    {AliasPatternCond_K_Ignore, 0},
3983
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3984
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3985
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1252
3986
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3987
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3988
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3989
17.6k
    {AliasPatternCond_K_Ignore, 0},
3990
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3991
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3992
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 5) - 1258
3993
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3994
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3995
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3996
17.6k
    {AliasPatternCond_K_Ignore, 0},
3997
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3998
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3999
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1264
4000
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4001
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
4002
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4003
17.6k
    {AliasPatternCond_K_Ignore, 0},
4004
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4005
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4006
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1270
4007
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4008
17.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
4009
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4010
17.6k
    {AliasPatternCond_K_Ignore, 0},
4011
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4012
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4013
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1276
4014
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4015
17.6k
    {AliasPatternCond_K_Ignore, 0},
4016
17.6k
    {AliasPatternCond_K_Ignore, 0},
4017
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4018
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4019
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1281
4020
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4021
17.6k
    {AliasPatternCond_K_Ignore, 0},
4022
17.6k
    {AliasPatternCond_K_Ignore, 0},
4023
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4024
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4025
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1286
4026
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4027
17.6k
    {AliasPatternCond_K_Ignore, 0},
4028
17.6k
    {AliasPatternCond_K_Ignore, 0},
4029
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4030
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4031
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1291
4032
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4033
17.6k
    {AliasPatternCond_K_Ignore, 0},
4034
17.6k
    {AliasPatternCond_K_Ignore, 0},
4035
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4036
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4037
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1296
4038
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4039
17.6k
    {AliasPatternCond_K_Ignore, 0},
4040
17.6k
    {AliasPatternCond_K_Ignore, 0},
4041
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4042
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4043
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1301
4044
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4045
17.6k
    {AliasPatternCond_K_Ignore, 0},
4046
17.6k
    {AliasPatternCond_K_Ignore, 0},
4047
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4048
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4049
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1306
4050
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4051
17.6k
    {AliasPatternCond_K_Ignore, 0},
4052
17.6k
    {AliasPatternCond_K_Ignore, 0},
4053
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4054
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4055
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1311
4056
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4057
17.6k
    {AliasPatternCond_K_Ignore, 0},
4058
17.6k
    {AliasPatternCond_K_Ignore, 0},
4059
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4060
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4061
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1316
4062
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4063
17.6k
    {AliasPatternCond_K_Ignore, 0},
4064
17.6k
    {AliasPatternCond_K_Ignore, 0},
4065
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4066
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4067
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1321
4068
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4069
17.6k
    {AliasPatternCond_K_Ignore, 0},
4070
17.6k
    {AliasPatternCond_K_Ignore, 0},
4071
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4072
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4073
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1326
4074
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4075
17.6k
    {AliasPatternCond_K_Ignore, 0},
4076
17.6k
    {AliasPatternCond_K_Ignore, 0},
4077
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4078
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4079
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1331
4080
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4081
17.6k
    {AliasPatternCond_K_Ignore, 0},
4082
17.6k
    {AliasPatternCond_K_Ignore, 0},
4083
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4084
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4085
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1336
4086
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4087
17.6k
    {AliasPatternCond_K_Ignore, 0},
4088
17.6k
    {AliasPatternCond_K_Ignore, 0},
4089
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4090
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4091
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1341
4092
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4093
17.6k
    {AliasPatternCond_K_Ignore, 0},
4094
17.6k
    {AliasPatternCond_K_Ignore, 0},
4095
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4096
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4097
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1346
4098
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4099
17.6k
    {AliasPatternCond_K_Ignore, 0},
4100
17.6k
    {AliasPatternCond_K_Ignore, 0},
4101
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4102
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4103
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1351
4104
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4105
17.6k
    {AliasPatternCond_K_Ignore, 0},
4106
17.6k
    {AliasPatternCond_K_Ignore, 0},
4107
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4108
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4109
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1356
4110
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4111
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4112
17.6k
    {AliasPatternCond_K_Ignore, 0},
4113
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4114
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4115
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1361
4116
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4117
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4118
17.6k
    {AliasPatternCond_K_Ignore, 0},
4119
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4120
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4121
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1366
4122
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4123
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4124
17.6k
    {AliasPatternCond_K_Ignore, 0},
4125
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4126
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4127
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1371
4128
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4129
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4130
17.6k
    {AliasPatternCond_K_Ignore, 0},
4131
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4132
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4133
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1376
4134
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4135
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4136
17.6k
    {AliasPatternCond_K_Ignore, 0},
4137
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4138
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4139
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1381
4140
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4141
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4142
17.6k
    {AliasPatternCond_K_Ignore, 0},
4143
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4144
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4145
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1386
4146
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4147
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4148
17.6k
    {AliasPatternCond_K_Ignore, 0},
4149
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4150
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4151
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1391
4152
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4153
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4154
17.6k
    {AliasPatternCond_K_Ignore, 0},
4155
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4156
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4157
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1396
4158
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4159
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4160
17.6k
    {AliasPatternCond_K_Ignore, 0},
4161
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4162
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4163
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1401
4164
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4165
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4166
17.6k
    {AliasPatternCond_K_Ignore, 0},
4167
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4168
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4169
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1406
4170
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4171
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4172
17.6k
    {AliasPatternCond_K_Ignore, 0},
4173
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4174
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4175
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1411
4176
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4177
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4178
17.6k
    {AliasPatternCond_K_Ignore, 0},
4179
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4180
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4181
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1416
4182
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4183
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4184
17.6k
    {AliasPatternCond_K_Ignore, 0},
4185
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4186
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4187
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1421
4188
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4189
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4190
17.6k
    {AliasPatternCond_K_Ignore, 0},
4191
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4192
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4193
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1426
4194
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4195
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4196
17.6k
    {AliasPatternCond_K_Ignore, 0},
4197
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4198
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4199
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1431
4200
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4201
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4202
17.6k
    {AliasPatternCond_K_Ignore, 0},
4203
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4204
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4205
    // (ORCCrr G0, IntRegs:$rs2, G0) - 1436
4206
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4207
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4208
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4209
    // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1439
4210
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4211
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4212
    // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1441
4213
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4214
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4215
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4216
    // (RESTORErr G0, G0, G0) - 1444
4217
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4218
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4219
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4220
    // (RET 8) - 1447
4221
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4222
    // (RETL 8) - 1448
4223
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4224
    // (SAVErr G0, G0, G0) - 1449
4225
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4226
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4227
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4228
    // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1452
4229
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4230
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4231
    // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1454
4232
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4233
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4234
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4235
    // (TICCri G0, i32imm:$imm, 8) - 1457
4236
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4237
17.6k
    {AliasPatternCond_K_Ignore, 0},
4238
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4239
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4240
    // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1461
4241
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4242
17.6k
    {AliasPatternCond_K_Ignore, 0},
4243
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4244
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4245
    // (TICCri G0, i32imm:$imm, 0) - 1465
4246
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4247
17.6k
    {AliasPatternCond_K_Ignore, 0},
4248
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4249
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4250
    // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1469
4251
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4252
17.6k
    {AliasPatternCond_K_Ignore, 0},
4253
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4254
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4255
    // (TICCri G0, i32imm:$imm, 9) - 1473
4256
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4257
17.6k
    {AliasPatternCond_K_Ignore, 0},
4258
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4259
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4260
    // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1477
4261
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4262
17.6k
    {AliasPatternCond_K_Ignore, 0},
4263
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4264
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4265
    // (TICCri G0, i32imm:$imm, 1) - 1481
4266
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4267
17.6k
    {AliasPatternCond_K_Ignore, 0},
4268
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4269
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4270
    // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1485
4271
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4272
17.6k
    {AliasPatternCond_K_Ignore, 0},
4273
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4274
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4275
    // (TICCri G0, i32imm:$imm, 10) - 1489
4276
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4277
17.6k
    {AliasPatternCond_K_Ignore, 0},
4278
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4279
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4280
    // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1493
4281
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4282
17.6k
    {AliasPatternCond_K_Ignore, 0},
4283
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4284
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4285
    // (TICCri G0, i32imm:$imm, 2) - 1497
4286
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4287
17.6k
    {AliasPatternCond_K_Ignore, 0},
4288
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4289
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4290
    // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1501
4291
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4292
17.6k
    {AliasPatternCond_K_Ignore, 0},
4293
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4294
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4295
    // (TICCri G0, i32imm:$imm, 11) - 1505
4296
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4297
17.6k
    {AliasPatternCond_K_Ignore, 0},
4298
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4299
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4300
    // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1509
4301
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4302
17.6k
    {AliasPatternCond_K_Ignore, 0},
4303
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4304
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4305
    // (TICCri G0, i32imm:$imm, 3) - 1513
4306
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4307
17.6k
    {AliasPatternCond_K_Ignore, 0},
4308
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4309
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4310
    // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1517
4311
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4312
17.6k
    {AliasPatternCond_K_Ignore, 0},
4313
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4314
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4315
    // (TICCri G0, i32imm:$imm, 12) - 1521
4316
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4317
17.6k
    {AliasPatternCond_K_Ignore, 0},
4318
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4319
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4320
    // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1525
4321
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4322
17.6k
    {AliasPatternCond_K_Ignore, 0},
4323
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4324
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4325
    // (TICCri G0, i32imm:$imm, 4) - 1529
4326
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4327
17.6k
    {AliasPatternCond_K_Ignore, 0},
4328
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4329
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4330
    // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1533
4331
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4332
17.6k
    {AliasPatternCond_K_Ignore, 0},
4333
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4334
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4335
    // (TICCri G0, i32imm:$imm, 13) - 1537
4336
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4337
17.6k
    {AliasPatternCond_K_Ignore, 0},
4338
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4339
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4340
    // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1541
4341
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4342
17.6k
    {AliasPatternCond_K_Ignore, 0},
4343
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4344
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4345
    // (TICCri G0, i32imm:$imm, 5) - 1545
4346
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4347
17.6k
    {AliasPatternCond_K_Ignore, 0},
4348
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4349
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4350
    // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1549
4351
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4352
17.6k
    {AliasPatternCond_K_Ignore, 0},
4353
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4354
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4355
    // (TICCri G0, i32imm:$imm, 14) - 1553
4356
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4357
17.6k
    {AliasPatternCond_K_Ignore, 0},
4358
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4359
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4360
    // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1557
4361
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4362
17.6k
    {AliasPatternCond_K_Ignore, 0},
4363
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4364
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4365
    // (TICCri G0, i32imm:$imm, 6) - 1561
4366
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4367
17.6k
    {AliasPatternCond_K_Ignore, 0},
4368
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4369
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4370
    // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1565
4371
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4372
17.6k
    {AliasPatternCond_K_Ignore, 0},
4373
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4374
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4375
    // (TICCri G0, i32imm:$imm, 15) - 1569
4376
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4377
17.6k
    {AliasPatternCond_K_Ignore, 0},
4378
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4379
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4380
    // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1573
4381
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4382
17.6k
    {AliasPatternCond_K_Ignore, 0},
4383
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4384
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4385
    // (TICCri G0, i32imm:$imm, 7) - 1577
4386
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4387
17.6k
    {AliasPatternCond_K_Ignore, 0},
4388
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4389
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4390
    // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1581
4391
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4392
17.6k
    {AliasPatternCond_K_Ignore, 0},
4393
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4394
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4395
    // (TICCrr G0, IntRegs:$rs2, 8) - 1585
4396
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4397
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4398
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4399
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4400
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1589
4401
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4402
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4403
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4404
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4405
    // (TICCrr G0, IntRegs:$rs2, 0) - 1593
4406
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4407
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4408
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4409
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4410
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1597
4411
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4412
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4413
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4414
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4415
    // (TICCrr G0, IntRegs:$rs2, 9) - 1601
4416
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4417
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4418
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4419
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4420
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1605
4421
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4422
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4423
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4424
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4425
    // (TICCrr G0, IntRegs:$rs2, 1) - 1609
4426
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4427
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4428
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4429
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4430
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1613
4431
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4432
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4433
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4434
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4435
    // (TICCrr G0, IntRegs:$rs2, 10) - 1617
4436
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4437
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4438
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4439
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4440
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1621
4441
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4442
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4443
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4444
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4445
    // (TICCrr G0, IntRegs:$rs2, 2) - 1625
4446
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4447
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4448
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4449
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4450
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1629
4451
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4452
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4453
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4454
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4455
    // (TICCrr G0, IntRegs:$rs2, 11) - 1633
4456
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4457
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4458
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4459
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4460
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1637
4461
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4462
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4463
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4464
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4465
    // (TICCrr G0, IntRegs:$rs2, 3) - 1641
4466
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4467
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4468
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4469
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4470
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1645
4471
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4472
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4473
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4474
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4475
    // (TICCrr G0, IntRegs:$rs2, 12) - 1649
4476
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4477
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4478
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4479
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4480
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1653
4481
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4482
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4483
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4484
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4485
    // (TICCrr G0, IntRegs:$rs2, 4) - 1657
4486
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4487
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4488
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4489
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4490
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1661
4491
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4492
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4493
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4494
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4495
    // (TICCrr G0, IntRegs:$rs2, 13) - 1665
4496
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4497
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4498
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4499
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4500
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1669
4501
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4502
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4503
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4504
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4505
    // (TICCrr G0, IntRegs:$rs2, 5) - 1673
4506
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4507
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4508
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4509
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4510
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1677
4511
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4512
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4513
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4514
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4515
    // (TICCrr G0, IntRegs:$rs2, 14) - 1681
4516
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4517
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4518
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4519
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4520
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1685
4521
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4522
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4523
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4524
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4525
    // (TICCrr G0, IntRegs:$rs2, 6) - 1689
4526
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4527
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4528
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4529
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4530
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1693
4531
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4532
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4533
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4534
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4535
    // (TICCrr G0, IntRegs:$rs2, 15) - 1697
4536
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4537
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4538
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4539
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4540
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1701
4541
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4542
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4543
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4544
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4545
    // (TICCrr G0, IntRegs:$rs2, 7) - 1705
4546
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4547
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4548
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4549
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4550
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1709
4551
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4552
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4553
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4554
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4555
    // (TRAPri G0, i32imm:$imm, 8) - 1713
4556
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4557
17.6k
    {AliasPatternCond_K_Ignore, 0},
4558
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4559
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1716
4560
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4561
17.6k
    {AliasPatternCond_K_Ignore, 0},
4562
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4563
    // (TRAPri G0, i32imm:$imm, 0) - 1719
4564
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4565
17.6k
    {AliasPatternCond_K_Ignore, 0},
4566
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4567
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1722
4568
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4569
17.6k
    {AliasPatternCond_K_Ignore, 0},
4570
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4571
    // (TRAPri G0, i32imm:$imm, 9) - 1725
4572
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4573
17.6k
    {AliasPatternCond_K_Ignore, 0},
4574
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4575
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1728
4576
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4577
17.6k
    {AliasPatternCond_K_Ignore, 0},
4578
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4579
    // (TRAPri G0, i32imm:$imm, 1) - 1731
4580
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4581
17.6k
    {AliasPatternCond_K_Ignore, 0},
4582
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4583
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1734
4584
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4585
17.6k
    {AliasPatternCond_K_Ignore, 0},
4586
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4587
    // (TRAPri G0, i32imm:$imm, 10) - 1737
4588
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4589
17.6k
    {AliasPatternCond_K_Ignore, 0},
4590
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4591
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1740
4592
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4593
17.6k
    {AliasPatternCond_K_Ignore, 0},
4594
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4595
    // (TRAPri G0, i32imm:$imm, 2) - 1743
4596
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4597
17.6k
    {AliasPatternCond_K_Ignore, 0},
4598
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4599
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1746
4600
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4601
17.6k
    {AliasPatternCond_K_Ignore, 0},
4602
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4603
    // (TRAPri G0, i32imm:$imm, 11) - 1749
4604
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4605
17.6k
    {AliasPatternCond_K_Ignore, 0},
4606
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4607
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1752
4608
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4609
17.6k
    {AliasPatternCond_K_Ignore, 0},
4610
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4611
    // (TRAPri G0, i32imm:$imm, 3) - 1755
4612
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4613
17.6k
    {AliasPatternCond_K_Ignore, 0},
4614
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4615
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1758
4616
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4617
17.6k
    {AliasPatternCond_K_Ignore, 0},
4618
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4619
    // (TRAPri G0, i32imm:$imm, 12) - 1761
4620
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4621
17.6k
    {AliasPatternCond_K_Ignore, 0},
4622
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4623
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1764
4624
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4625
17.6k
    {AliasPatternCond_K_Ignore, 0},
4626
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4627
    // (TRAPri G0, i32imm:$imm, 4) - 1767
4628
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4629
17.6k
    {AliasPatternCond_K_Ignore, 0},
4630
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4631
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1770
4632
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4633
17.6k
    {AliasPatternCond_K_Ignore, 0},
4634
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4635
    // (TRAPri G0, i32imm:$imm, 13) - 1773
4636
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4637
17.6k
    {AliasPatternCond_K_Ignore, 0},
4638
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4639
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1776
4640
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4641
17.6k
    {AliasPatternCond_K_Ignore, 0},
4642
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4643
    // (TRAPri G0, i32imm:$imm, 5) - 1779
4644
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4645
17.6k
    {AliasPatternCond_K_Ignore, 0},
4646
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4647
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1782
4648
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4649
17.6k
    {AliasPatternCond_K_Ignore, 0},
4650
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4651
    // (TRAPri G0, i32imm:$imm, 14) - 1785
4652
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4653
17.6k
    {AliasPatternCond_K_Ignore, 0},
4654
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4655
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1788
4656
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4657
17.6k
    {AliasPatternCond_K_Ignore, 0},
4658
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4659
    // (TRAPri G0, i32imm:$imm, 6) - 1791
4660
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4661
17.6k
    {AliasPatternCond_K_Ignore, 0},
4662
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4663
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1794
4664
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4665
17.6k
    {AliasPatternCond_K_Ignore, 0},
4666
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4667
    // (TRAPri G0, i32imm:$imm, 15) - 1797
4668
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4669
17.6k
    {AliasPatternCond_K_Ignore, 0},
4670
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4671
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1800
4672
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4673
17.6k
    {AliasPatternCond_K_Ignore, 0},
4674
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4675
    // (TRAPri G0, i32imm:$imm, 7) - 1803
4676
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4677
17.6k
    {AliasPatternCond_K_Ignore, 0},
4678
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4679
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1806
4680
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4681
17.6k
    {AliasPatternCond_K_Ignore, 0},
4682
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4683
    // (TRAPrr G0, IntRegs:$rs1, 8) - 1809
4684
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4685
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4686
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4687
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1812
4688
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4689
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4690
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4691
    // (TRAPrr G0, IntRegs:$rs1, 0) - 1815
4692
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4693
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4694
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4695
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1818
4696
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4697
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4698
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4699
    // (TRAPrr G0, IntRegs:$rs1, 9) - 1821
4700
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4701
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4702
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4703
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1824
4704
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4705
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4706
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4707
    // (TRAPrr G0, IntRegs:$rs1, 1) - 1827
4708
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4709
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4710
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4711
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1830
4712
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4713
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4714
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4715
    // (TRAPrr G0, IntRegs:$rs1, 10) - 1833
4716
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4717
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4718
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4719
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1836
4720
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4721
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4722
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4723
    // (TRAPrr G0, IntRegs:$rs1, 2) - 1839
4724
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4725
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4726
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4727
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1842
4728
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4729
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4730
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4731
    // (TRAPrr G0, IntRegs:$rs1, 11) - 1845
4732
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4733
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4734
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4735
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1848
4736
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4737
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4738
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4739
    // (TRAPrr G0, IntRegs:$rs1, 3) - 1851
4740
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4741
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4742
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4743
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1854
4744
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4745
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4746
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4747
    // (TRAPrr G0, IntRegs:$rs1, 12) - 1857
4748
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4749
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4750
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4751
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1860
4752
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4753
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4754
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4755
    // (TRAPrr G0, IntRegs:$rs1, 4) - 1863
4756
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4757
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4758
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4759
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1866
4760
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4761
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4762
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4763
    // (TRAPrr G0, IntRegs:$rs1, 13) - 1869
4764
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4765
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4766
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4767
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1872
4768
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4769
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4770
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4771
    // (TRAPrr G0, IntRegs:$rs1, 5) - 1875
4772
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4773
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4774
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4775
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1878
4776
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4777
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4778
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4779
    // (TRAPrr G0, IntRegs:$rs1, 14) - 1881
4780
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4781
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4782
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4783
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1884
4784
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4785
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4786
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4787
    // (TRAPrr G0, IntRegs:$rs1, 6) - 1887
4788
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4789
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4790
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4791
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1890
4792
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4793
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4794
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4795
    // (TRAPrr G0, IntRegs:$rs1, 15) - 1893
4796
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4797
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4798
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4799
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1896
4800
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4801
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4802
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4803
    // (TRAPrr G0, IntRegs:$rs1, 7) - 1899
4804
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4805
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4806
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4807
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1902
4808
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4809
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4810
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4811
    // (TXCCri G0, i32imm:$imm, 8) - 1905
4812
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4813
17.6k
    {AliasPatternCond_K_Ignore, 0},
4814
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4815
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4816
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1909
4817
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4818
17.6k
    {AliasPatternCond_K_Ignore, 0},
4819
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4820
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4821
    // (TXCCri G0, i32imm:$imm, 0) - 1913
4822
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4823
17.6k
    {AliasPatternCond_K_Ignore, 0},
4824
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4825
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4826
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1917
4827
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4828
17.6k
    {AliasPatternCond_K_Ignore, 0},
4829
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4830
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4831
    // (TXCCri G0, i32imm:$imm, 9) - 1921
4832
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4833
17.6k
    {AliasPatternCond_K_Ignore, 0},
4834
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4835
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4836
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1925
4837
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4838
17.6k
    {AliasPatternCond_K_Ignore, 0},
4839
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4840
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4841
    // (TXCCri G0, i32imm:$imm, 1) - 1929
4842
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4843
17.6k
    {AliasPatternCond_K_Ignore, 0},
4844
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4845
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4846
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1933
4847
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4848
17.6k
    {AliasPatternCond_K_Ignore, 0},
4849
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4850
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4851
    // (TXCCri G0, i32imm:$imm, 10) - 1937
4852
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4853
17.6k
    {AliasPatternCond_K_Ignore, 0},
4854
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4855
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4856
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1941
4857
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4858
17.6k
    {AliasPatternCond_K_Ignore, 0},
4859
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4860
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4861
    // (TXCCri G0, i32imm:$imm, 2) - 1945
4862
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4863
17.6k
    {AliasPatternCond_K_Ignore, 0},
4864
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4865
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4866
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1949
4867
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4868
17.6k
    {AliasPatternCond_K_Ignore, 0},
4869
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4870
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4871
    // (TXCCri G0, i32imm:$imm, 11) - 1953
4872
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4873
17.6k
    {AliasPatternCond_K_Ignore, 0},
4874
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4875
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4876
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1957
4877
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4878
17.6k
    {AliasPatternCond_K_Ignore, 0},
4879
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4880
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4881
    // (TXCCri G0, i32imm:$imm, 3) - 1961
4882
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4883
17.6k
    {AliasPatternCond_K_Ignore, 0},
4884
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4885
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4886
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1965
4887
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4888
17.6k
    {AliasPatternCond_K_Ignore, 0},
4889
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4890
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4891
    // (TXCCri G0, i32imm:$imm, 12) - 1969
4892
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4893
17.6k
    {AliasPatternCond_K_Ignore, 0},
4894
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4895
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4896
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1973
4897
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4898
17.6k
    {AliasPatternCond_K_Ignore, 0},
4899
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4900
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4901
    // (TXCCri G0, i32imm:$imm, 4) - 1977
4902
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4903
17.6k
    {AliasPatternCond_K_Ignore, 0},
4904
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4905
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4906
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1981
4907
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4908
17.6k
    {AliasPatternCond_K_Ignore, 0},
4909
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4910
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4911
    // (TXCCri G0, i32imm:$imm, 13) - 1985
4912
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4913
17.6k
    {AliasPatternCond_K_Ignore, 0},
4914
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4915
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4916
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1989
4917
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4918
17.6k
    {AliasPatternCond_K_Ignore, 0},
4919
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4920
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4921
    // (TXCCri G0, i32imm:$imm, 5) - 1993
4922
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4923
17.6k
    {AliasPatternCond_K_Ignore, 0},
4924
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4925
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4926
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1997
4927
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4928
17.6k
    {AliasPatternCond_K_Ignore, 0},
4929
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4930
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4931
    // (TXCCri G0, i32imm:$imm, 14) - 2001
4932
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4933
17.6k
    {AliasPatternCond_K_Ignore, 0},
4934
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4935
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4936
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2005
4937
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4938
17.6k
    {AliasPatternCond_K_Ignore, 0},
4939
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4940
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4941
    // (TXCCri G0, i32imm:$imm, 6) - 2009
4942
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4943
17.6k
    {AliasPatternCond_K_Ignore, 0},
4944
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4945
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4946
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2013
4947
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4948
17.6k
    {AliasPatternCond_K_Ignore, 0},
4949
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4950
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4951
    // (TXCCri G0, i32imm:$imm, 15) - 2017
4952
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4953
17.6k
    {AliasPatternCond_K_Ignore, 0},
4954
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4955
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4956
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2021
4957
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4958
17.6k
    {AliasPatternCond_K_Ignore, 0},
4959
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4960
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4961
    // (TXCCri G0, i32imm:$imm, 7) - 2025
4962
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4963
17.6k
    {AliasPatternCond_K_Ignore, 0},
4964
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4965
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4966
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2029
4967
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4968
17.6k
    {AliasPatternCond_K_Ignore, 0},
4969
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4970
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4971
    // (TXCCrr G0, IntRegs:$rs2, 8) - 2033
4972
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4973
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4974
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4975
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4976
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2037
4977
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4978
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4979
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4980
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4981
    // (TXCCrr G0, IntRegs:$rs2, 0) - 2041
4982
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4983
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4984
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4985
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4986
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2045
4987
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4988
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4989
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4990
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4991
    // (TXCCrr G0, IntRegs:$rs2, 9) - 2049
4992
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4993
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4994
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4995
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4996
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2053
4997
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4998
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4999
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5000
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5001
    // (TXCCrr G0, IntRegs:$rs2, 1) - 2057
5002
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5003
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5004
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5005
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5006
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2061
5007
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5008
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5009
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5010
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5011
    // (TXCCrr G0, IntRegs:$rs2, 10) - 2065
5012
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5013
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5014
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5015
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5016
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2069
5017
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5018
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5019
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5020
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5021
    // (TXCCrr G0, IntRegs:$rs2, 2) - 2073
5022
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5023
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5024
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5025
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5026
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2077
5027
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5028
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5029
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5030
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5031
    // (TXCCrr G0, IntRegs:$rs2, 11) - 2081
5032
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5033
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5034
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5035
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5036
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2085
5037
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5038
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5039
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5040
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5041
    // (TXCCrr G0, IntRegs:$rs2, 3) - 2089
5042
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5043
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5044
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5045
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5046
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2093
5047
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5048
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5049
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5050
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5051
    // (TXCCrr G0, IntRegs:$rs2, 12) - 2097
5052
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5053
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5054
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5055
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5056
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2101
5057
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5058
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5059
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5060
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5061
    // (TXCCrr G0, IntRegs:$rs2, 4) - 2105
5062
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5063
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5064
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5065
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5066
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2109
5067
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5068
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5069
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5070
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5071
    // (TXCCrr G0, IntRegs:$rs2, 13) - 2113
5072
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5073
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5074
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5075
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5076
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2117
5077
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5078
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5079
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5080
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5081
    // (TXCCrr G0, IntRegs:$rs2, 5) - 2121
5082
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5083
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5084
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5085
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5086
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2125
5087
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5088
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5089
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5090
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5091
    // (TXCCrr G0, IntRegs:$rs2, 14) - 2129
5092
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5093
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5094
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5095
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5096
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2133
5097
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5098
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5099
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5100
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5101
    // (TXCCrr G0, IntRegs:$rs2, 6) - 2137
5102
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5103
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5104
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5105
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5106
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2141
5107
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5108
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5109
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5110
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5111
    // (TXCCrr G0, IntRegs:$rs2, 15) - 2145
5112
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5113
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5114
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5115
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5116
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2149
5117
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5118
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5119
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5120
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5121
    // (TXCCrr G0, IntRegs:$rs2, 7) - 2153
5122
17.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5123
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5124
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5125
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5126
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2157
5127
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5128
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5129
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5130
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5131
    // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2161
5132
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5133
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5134
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5135
    // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2164
5136
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5137
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5138
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5139
    // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2167
5140
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5141
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5142
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5143
    // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2170
5144
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5145
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5146
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5147
    // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2173
5148
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5149
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5150
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5151
    // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2176
5152
17.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5153
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5154
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5155
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2179
5156
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5157
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5158
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5159
17.6k
    {AliasPatternCond_K_Ignore, 0},
5160
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5161
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5162
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2185
5163
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5164
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5165
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5166
17.6k
    {AliasPatternCond_K_Ignore, 0},
5167
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5168
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5169
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2191
5170
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5171
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5172
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5173
17.6k
    {AliasPatternCond_K_Ignore, 0},
5174
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5175
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5176
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2197
5177
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5178
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5179
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5180
17.6k
    {AliasPatternCond_K_Ignore, 0},
5181
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5182
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5183
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2203
5184
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5185
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5186
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5187
17.6k
    {AliasPatternCond_K_Ignore, 0},
5188
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5189
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5190
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2209
5191
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5192
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5193
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5194
17.6k
    {AliasPatternCond_K_Ignore, 0},
5195
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5196
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5197
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2215
5198
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5199
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5200
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5201
17.6k
    {AliasPatternCond_K_Ignore, 0},
5202
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5203
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5204
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2221
5205
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5206
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5207
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5208
17.6k
    {AliasPatternCond_K_Ignore, 0},
5209
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5210
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5211
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2227
5212
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5213
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5214
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5215
17.6k
    {AliasPatternCond_K_Ignore, 0},
5216
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5217
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5218
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2233
5219
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5220
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5221
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5222
17.6k
    {AliasPatternCond_K_Ignore, 0},
5223
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5224
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5225
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2239
5226
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5227
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5228
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5229
17.6k
    {AliasPatternCond_K_Ignore, 0},
5230
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5231
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5232
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2245
5233
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5234
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5235
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5236
17.6k
    {AliasPatternCond_K_Ignore, 0},
5237
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5238
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5239
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2251
5240
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5241
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5242
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5243
17.6k
    {AliasPatternCond_K_Ignore, 0},
5244
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5245
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5246
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2257
5247
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5248
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5249
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5250
17.6k
    {AliasPatternCond_K_Ignore, 0},
5251
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5252
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5253
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2263
5254
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5255
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5256
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5257
17.6k
    {AliasPatternCond_K_Ignore, 0},
5258
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5259
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5260
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2269
5261
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5262
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5263
17.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5264
17.6k
    {AliasPatternCond_K_Ignore, 0},
5265
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5266
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5267
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2275
5268
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5269
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5270
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5271
17.6k
    {AliasPatternCond_K_Ignore, 0},
5272
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5273
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5274
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2281
5275
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5276
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5277
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5278
17.6k
    {AliasPatternCond_K_Ignore, 0},
5279
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5280
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5281
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2287
5282
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5283
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5284
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5285
17.6k
    {AliasPatternCond_K_Ignore, 0},
5286
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5287
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5288
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2293
5289
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5290
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5291
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5292
17.6k
    {AliasPatternCond_K_Ignore, 0},
5293
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5294
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5295
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2299
5296
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5297
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5298
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5299
17.6k
    {AliasPatternCond_K_Ignore, 0},
5300
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5301
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5302
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2305
5303
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5304
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5305
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5306
17.6k
    {AliasPatternCond_K_Ignore, 0},
5307
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5308
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5309
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2311
5310
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5311
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5312
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5313
17.6k
    {AliasPatternCond_K_Ignore, 0},
5314
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5315
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5316
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2317
5317
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5318
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5319
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5320
17.6k
    {AliasPatternCond_K_Ignore, 0},
5321
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5322
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5323
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2323
5324
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5325
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5326
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5327
17.6k
    {AliasPatternCond_K_Ignore, 0},
5328
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5329
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5330
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2329
5331
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5332
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5333
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5334
17.6k
    {AliasPatternCond_K_Ignore, 0},
5335
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5336
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5337
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2335
5338
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5339
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5340
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5341
17.6k
    {AliasPatternCond_K_Ignore, 0},
5342
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5343
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5344
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2341
5345
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5346
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5347
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5348
17.6k
    {AliasPatternCond_K_Ignore, 0},
5349
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5350
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5351
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2347
5352
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5353
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5354
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5355
17.6k
    {AliasPatternCond_K_Ignore, 0},
5356
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5357
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5358
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2353
5359
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5360
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5361
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5362
17.6k
    {AliasPatternCond_K_Ignore, 0},
5363
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5364
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5365
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2359
5366
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5367
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5368
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5369
17.6k
    {AliasPatternCond_K_Ignore, 0},
5370
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5371
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5372
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2365
5373
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5374
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5375
17.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5376
17.6k
    {AliasPatternCond_K_Ignore, 0},
5377
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5378
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5379
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2371
5380
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5381
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5382
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5383
17.6k
    {AliasPatternCond_K_Ignore, 0},
5384
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5385
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5386
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2377
5387
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5388
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5389
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5390
17.6k
    {AliasPatternCond_K_Ignore, 0},
5391
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5392
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5393
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2383
5394
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5395
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5396
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5397
17.6k
    {AliasPatternCond_K_Ignore, 0},
5398
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5399
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5400
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2389
5401
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5402
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5403
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5404
17.6k
    {AliasPatternCond_K_Ignore, 0},
5405
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5406
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5407
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2395
5408
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5409
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5410
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5411
17.6k
    {AliasPatternCond_K_Ignore, 0},
5412
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5413
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5414
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2401
5415
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5416
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5417
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5418
17.6k
    {AliasPatternCond_K_Ignore, 0},
5419
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5420
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5421
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2407
5422
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5423
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5424
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5425
17.6k
    {AliasPatternCond_K_Ignore, 0},
5426
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5427
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5428
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2413
5429
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5430
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5431
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5432
17.6k
    {AliasPatternCond_K_Ignore, 0},
5433
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5434
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5435
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2419
5436
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5437
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5438
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5439
17.6k
    {AliasPatternCond_K_Ignore, 0},
5440
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5441
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5442
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2425
5443
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5444
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5445
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5446
17.6k
    {AliasPatternCond_K_Ignore, 0},
5447
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5448
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5449
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2431
5450
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5451
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5452
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5453
17.6k
    {AliasPatternCond_K_Ignore, 0},
5454
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5455
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5456
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2437
5457
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5458
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5459
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5460
17.6k
    {AliasPatternCond_K_Ignore, 0},
5461
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5462
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5463
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2443
5464
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5465
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5466
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5467
17.6k
    {AliasPatternCond_K_Ignore, 0},
5468
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5469
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5470
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2449
5471
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5472
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5473
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5474
17.6k
    {AliasPatternCond_K_Ignore, 0},
5475
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5476
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5477
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2455
5478
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5479
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5480
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5481
17.6k
    {AliasPatternCond_K_Ignore, 0},
5482
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5483
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5484
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2461
5485
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5486
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5487
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5488
17.6k
    {AliasPatternCond_K_Ignore, 0},
5489
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5490
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5491
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2467
5492
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5493
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5494
17.6k
    {AliasPatternCond_K_Ignore, 0},
5495
17.6k
    {AliasPatternCond_K_Ignore, 0},
5496
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5497
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5498
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2473
5499
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5500
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5501
17.6k
    {AliasPatternCond_K_Ignore, 0},
5502
17.6k
    {AliasPatternCond_K_Ignore, 0},
5503
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5504
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5505
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2479
5506
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5507
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5508
17.6k
    {AliasPatternCond_K_Ignore, 0},
5509
17.6k
    {AliasPatternCond_K_Ignore, 0},
5510
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5511
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5512
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2485
5513
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5514
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5515
17.6k
    {AliasPatternCond_K_Ignore, 0},
5516
17.6k
    {AliasPatternCond_K_Ignore, 0},
5517
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5518
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5519
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2491
5520
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5521
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5522
17.6k
    {AliasPatternCond_K_Ignore, 0},
5523
17.6k
    {AliasPatternCond_K_Ignore, 0},
5524
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5525
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5526
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2497
5527
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5528
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5529
17.6k
    {AliasPatternCond_K_Ignore, 0},
5530
17.6k
    {AliasPatternCond_K_Ignore, 0},
5531
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5532
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5533
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2503
5534
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5535
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5536
17.6k
    {AliasPatternCond_K_Ignore, 0},
5537
17.6k
    {AliasPatternCond_K_Ignore, 0},
5538
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5539
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5540
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2509
5541
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5542
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5543
17.6k
    {AliasPatternCond_K_Ignore, 0},
5544
17.6k
    {AliasPatternCond_K_Ignore, 0},
5545
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5546
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5547
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2515
5548
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5549
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5550
17.6k
    {AliasPatternCond_K_Ignore, 0},
5551
17.6k
    {AliasPatternCond_K_Ignore, 0},
5552
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5553
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5554
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2521
5555
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5556
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5557
17.6k
    {AliasPatternCond_K_Ignore, 0},
5558
17.6k
    {AliasPatternCond_K_Ignore, 0},
5559
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5560
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5561
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2527
5562
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5563
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5564
17.6k
    {AliasPatternCond_K_Ignore, 0},
5565
17.6k
    {AliasPatternCond_K_Ignore, 0},
5566
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5567
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5568
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2533
5569
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5570
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5571
17.6k
    {AliasPatternCond_K_Ignore, 0},
5572
17.6k
    {AliasPatternCond_K_Ignore, 0},
5573
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5574
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5575
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2539
5576
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5577
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5578
17.6k
    {AliasPatternCond_K_Ignore, 0},
5579
17.6k
    {AliasPatternCond_K_Ignore, 0},
5580
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5581
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5582
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2545
5583
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5584
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5585
17.6k
    {AliasPatternCond_K_Ignore, 0},
5586
17.6k
    {AliasPatternCond_K_Ignore, 0},
5587
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5588
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5589
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2551
5590
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5591
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5592
17.6k
    {AliasPatternCond_K_Ignore, 0},
5593
17.6k
    {AliasPatternCond_K_Ignore, 0},
5594
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5595
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5596
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2557
5597
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5598
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5599
17.6k
    {AliasPatternCond_K_Ignore, 0},
5600
17.6k
    {AliasPatternCond_K_Ignore, 0},
5601
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5602
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5603
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2563
5604
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5605
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5606
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5607
17.6k
    {AliasPatternCond_K_Ignore, 0},
5608
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5609
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5610
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2569
5611
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5612
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5613
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5614
17.6k
    {AliasPatternCond_K_Ignore, 0},
5615
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5616
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5617
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2575
5618
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5619
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5620
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5621
17.6k
    {AliasPatternCond_K_Ignore, 0},
5622
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5623
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5624
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2581
5625
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5626
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5627
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5628
17.6k
    {AliasPatternCond_K_Ignore, 0},
5629
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5630
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5631
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2587
5632
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5633
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5634
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5635
17.6k
    {AliasPatternCond_K_Ignore, 0},
5636
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5637
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5638
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2593
5639
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5640
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5641
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5642
17.6k
    {AliasPatternCond_K_Ignore, 0},
5643
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5644
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5645
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2599
5646
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5647
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5648
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5649
17.6k
    {AliasPatternCond_K_Ignore, 0},
5650
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5651
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5652
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2605
5653
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5654
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5655
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5656
17.6k
    {AliasPatternCond_K_Ignore, 0},
5657
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5658
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5659
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2611
5660
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5661
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5662
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5663
17.6k
    {AliasPatternCond_K_Ignore, 0},
5664
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5665
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5666
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2617
5667
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5668
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5669
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5670
17.6k
    {AliasPatternCond_K_Ignore, 0},
5671
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5672
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5673
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2623
5674
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5675
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5676
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5677
17.6k
    {AliasPatternCond_K_Ignore, 0},
5678
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5679
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5680
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2629
5681
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5682
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5683
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5684
17.6k
    {AliasPatternCond_K_Ignore, 0},
5685
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5686
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5687
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2635
5688
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5689
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5690
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5691
17.6k
    {AliasPatternCond_K_Ignore, 0},
5692
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5693
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5694
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2641
5695
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5696
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5697
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5698
17.6k
    {AliasPatternCond_K_Ignore, 0},
5699
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5700
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5701
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2647
5702
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5703
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5704
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5705
17.6k
    {AliasPatternCond_K_Ignore, 0},
5706
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5707
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5708
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2653
5709
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5710
17.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5711
17.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5712
17.6k
    {AliasPatternCond_K_Ignore, 0},
5713
17.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5714
17.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5715
17.6k
  {0},  };
5716
5717
17.6k
  static const char AsmStrings[] =
5718
17.6k
    /* 0 */ "ba $\x01\0"
5719
17.6k
    /* 6 */ "bn $\x01\0"
5720
17.6k
    /* 12 */ "bne $\x01\0"
5721
17.6k
    /* 19 */ "be $\x01\0"
5722
17.6k
    /* 25 */ "bg $\x01\0"
5723
17.6k
    /* 31 */ "ble $\x01\0"
5724
17.6k
    /* 38 */ "bge $\x01\0"
5725
17.6k
    /* 45 */ "bl $\x01\0"
5726
17.6k
    /* 51 */ "bgu $\x01\0"
5727
17.6k
    /* 58 */ "bleu $\x01\0"
5728
17.6k
    /* 66 */ "bcc $\x01\0"
5729
17.6k
    /* 73 */ "bcs $\x01\0"
5730
17.6k
    /* 80 */ "bpos $\x01\0"
5731
17.6k
    /* 88 */ "bneg $\x01\0"
5732
17.6k
    /* 96 */ "bvc $\x01\0"
5733
17.6k
    /* 103 */ "bvs $\x01\0"
5734
17.6k
    /* 110 */ "ba,a $\x01\0"
5735
17.6k
    /* 118 */ "bn,a $\x01\0"
5736
17.6k
    /* 126 */ "bne,a $\x01\0"
5737
17.6k
    /* 135 */ "be,a $\x01\0"
5738
17.6k
    /* 143 */ "bg,a $\x01\0"
5739
17.6k
    /* 151 */ "ble,a $\x01\0"
5740
17.6k
    /* 160 */ "bge,a $\x01\0"
5741
17.6k
    /* 169 */ "bl,a $\x01\0"
5742
17.6k
    /* 177 */ "bgu,a $\x01\0"
5743
17.6k
    /* 186 */ "bleu,a $\x01\0"
5744
17.6k
    /* 196 */ "bcc,a $\x01\0"
5745
17.6k
    /* 205 */ "bcs,a $\x01\0"
5746
17.6k
    /* 214 */ "bpos,a $\x01\0"
5747
17.6k
    /* 224 */ "bneg,a $\x01\0"
5748
17.6k
    /* 234 */ "bvc,a $\x01\0"
5749
17.6k
    /* 243 */ "bvs,a $\x01\0"
5750
17.6k
    /* 252 */ "fba,a,pn $\x03, $\x01\0"
5751
17.6k
    /* 268 */ "fbn,a,pn $\x03, $\x01\0"
5752
17.6k
    /* 284 */ "fbu,a,pn $\x03, $\x01\0"
5753
17.6k
    /* 300 */ "fbg,a,pn $\x03, $\x01\0"
5754
17.6k
    /* 316 */ "fbug,a,pn $\x03, $\x01\0"
5755
17.6k
    /* 333 */ "fbl,a,pn $\x03, $\x01\0"
5756
17.6k
    /* 349 */ "fbul,a,pn $\x03, $\x01\0"
5757
17.6k
    /* 366 */ "fblg,a,pn $\x03, $\x01\0"
5758
17.6k
    /* 383 */ "fbne,a,pn $\x03, $\x01\0"
5759
17.6k
    /* 400 */ "fbe,a,pn $\x03, $\x01\0"
5760
17.6k
    /* 416 */ "fbue,a,pn $\x03, $\x01\0"
5761
17.6k
    /* 433 */ "fbge,a,pn $\x03, $\x01\0"
5762
17.6k
    /* 450 */ "fbuge,a,pn $\x03, $\x01\0"
5763
17.6k
    /* 468 */ "fble,a,pn $\x03, $\x01\0"
5764
17.6k
    /* 485 */ "fbule,a,pn $\x03, $\x01\0"
5765
17.6k
    /* 503 */ "fbo,a,pn $\x03, $\x01\0"
5766
17.6k
    /* 519 */ "fba,pn $\x03, $\x01\0"
5767
17.6k
    /* 533 */ "fbn,pn $\x03, $\x01\0"
5768
17.6k
    /* 547 */ "fbu,pn $\x03, $\x01\0"
5769
17.6k
    /* 561 */ "fbg,pn $\x03, $\x01\0"
5770
17.6k
    /* 575 */ "fbug,pn $\x03, $\x01\0"
5771
17.6k
    /* 590 */ "fbl,pn $\x03, $\x01\0"
5772
17.6k
    /* 604 */ "fbul,pn $\x03, $\x01\0"
5773
17.6k
    /* 619 */ "fblg,pn $\x03, $\x01\0"
5774
17.6k
    /* 634 */ "fbne,pn $\x03, $\x01\0"
5775
17.6k
    /* 649 */ "fbe,pn $\x03, $\x01\0"
5776
17.6k
    /* 663 */ "fbue,pn $\x03, $\x01\0"
5777
17.6k
    /* 678 */ "fbge,pn $\x03, $\x01\0"
5778
17.6k
    /* 693 */ "fbuge,pn $\x03, $\x01\0"
5779
17.6k
    /* 709 */ "fble,pn $\x03, $\x01\0"
5780
17.6k
    /* 724 */ "fbule,pn $\x03, $\x01\0"
5781
17.6k
    /* 740 */ "fbo,pn $\x03, $\x01\0"
5782
17.6k
    /* 754 */ "ba,a,pn %icc, $\x01\0"
5783
17.6k
    /* 771 */ "bn,a,pn %icc, $\x01\0"
5784
17.6k
    /* 788 */ "bne,a,pn %icc, $\x01\0"
5785
17.6k
    /* 806 */ "be,a,pn %icc, $\x01\0"
5786
17.6k
    /* 823 */ "bg,a,pn %icc, $\x01\0"
5787
17.6k
    /* 840 */ "ble,a,pn %icc, $\x01\0"
5788
17.6k
    /* 858 */ "bge,a,pn %icc, $\x01\0"
5789
17.6k
    /* 876 */ "bl,a,pn %icc, $\x01\0"
5790
17.6k
    /* 893 */ "bgu,a,pn %icc, $\x01\0"
5791
17.6k
    /* 911 */ "bleu,a,pn %icc, $\x01\0"
5792
17.6k
    /* 930 */ "bcc,a,pn %icc, $\x01\0"
5793
17.6k
    /* 948 */ "bcs,a,pn %icc, $\x01\0"
5794
17.6k
    /* 966 */ "bpos,a,pn %icc, $\x01\0"
5795
17.6k
    /* 985 */ "bneg,a,pn %icc, $\x01\0"
5796
17.6k
    /* 1004 */ "bvc,a,pn %icc, $\x01\0"
5797
17.6k
    /* 1022 */ "bvs,a,pn %icc, $\x01\0"
5798
17.6k
    /* 1040 */ "ba,pn %icc, $\x01\0"
5799
17.6k
    /* 1055 */ "bn,pn %icc, $\x01\0"
5800
17.6k
    /* 1070 */ "bne,pn %icc, $\x01\0"
5801
17.6k
    /* 1086 */ "be,pn %icc, $\x01\0"
5802
17.6k
    /* 1101 */ "bg,pn %icc, $\x01\0"
5803
17.6k
    /* 1116 */ "ble,pn %icc, $\x01\0"
5804
17.6k
    /* 1132 */ "bge,pn %icc, $\x01\0"
5805
17.6k
    /* 1148 */ "bl,pn %icc, $\x01\0"
5806
17.6k
    /* 1163 */ "bgu,pn %icc, $\x01\0"
5807
17.6k
    /* 1179 */ "bleu,pn %icc, $\x01\0"
5808
17.6k
    /* 1196 */ "bcc,pn %icc, $\x01\0"
5809
17.6k
    /* 1212 */ "bcs,pn %icc, $\x01\0"
5810
17.6k
    /* 1228 */ "bpos,pn %icc, $\x01\0"
5811
17.6k
    /* 1245 */ "bneg,pn %icc, $\x01\0"
5812
17.6k
    /* 1262 */ "bvc,pn %icc, $\x01\0"
5813
17.6k
    /* 1278 */ "bvs,pn %icc, $\x01\0"
5814
17.6k
    /* 1294 */ "brz,a,pn $\x03, $\x01\0"
5815
17.6k
    /* 1310 */ "brlez,a,pn $\x03, $\x01\0"
5816
17.6k
    /* 1328 */ "brlz,a,pn $\x03, $\x01\0"
5817
17.6k
    /* 1345 */ "brnz,a,pn $\x03, $\x01\0"
5818
17.6k
    /* 1362 */ "brgz,a,pn $\x03, $\x01\0"
5819
17.6k
    /* 1379 */ "brgez,a,pn $\x03, $\x01\0"
5820
17.6k
    /* 1397 */ "brz,pn $\x03, $\x01\0"
5821
17.6k
    /* 1411 */ "brlez,pn $\x03, $\x01\0"
5822
17.6k
    /* 1427 */ "brlz,pn $\x03, $\x01\0"
5823
17.6k
    /* 1442 */ "brnz,pn $\x03, $\x01\0"
5824
17.6k
    /* 1457 */ "brgz,pn $\x03, $\x01\0"
5825
17.6k
    /* 1472 */ "brgez,pn $\x03, $\x01\0"
5826
17.6k
    /* 1488 */ "ba,a,pn %xcc, $\x01\0"
5827
17.6k
    /* 1505 */ "bn,a,pn %xcc, $\x01\0"
5828
17.6k
    /* 1522 */ "bne,a,pn %xcc, $\x01\0"
5829
17.6k
    /* 1540 */ "be,a,pn %xcc, $\x01\0"
5830
17.6k
    /* 1557 */ "bg,a,pn %xcc, $\x01\0"
5831
17.6k
    /* 1574 */ "ble,a,pn %xcc, $\x01\0"
5832
17.6k
    /* 1592 */ "bge,a,pn %xcc, $\x01\0"
5833
17.6k
    /* 1610 */ "bl,a,pn %xcc, $\x01\0"
5834
17.6k
    /* 1627 */ "bgu,a,pn %xcc, $\x01\0"
5835
17.6k
    /* 1645 */ "bleu,a,pn %xcc, $\x01\0"
5836
17.6k
    /* 1664 */ "bcc,a,pn %xcc, $\x01\0"
5837
17.6k
    /* 1682 */ "bcs,a,pn %xcc, $\x01\0"
5838
17.6k
    /* 1700 */ "bpos,a,pn %xcc, $\x01\0"
5839
17.6k
    /* 1719 */ "bneg,a,pn %xcc, $\x01\0"
5840
17.6k
    /* 1738 */ "bvc,a,pn %xcc, $\x01\0"
5841
17.6k
    /* 1756 */ "bvs,a,pn %xcc, $\x01\0"
5842
17.6k
    /* 1774 */ "ba,pn %xcc, $\x01\0"
5843
17.6k
    /* 1789 */ "bn,pn %xcc, $\x01\0"
5844
17.6k
    /* 1804 */ "bne,pn %xcc, $\x01\0"
5845
17.6k
    /* 1820 */ "be,pn %xcc, $\x01\0"
5846
17.6k
    /* 1835 */ "bg,pn %xcc, $\x01\0"
5847
17.6k
    /* 1850 */ "ble,pn %xcc, $\x01\0"
5848
17.6k
    /* 1866 */ "bge,pn %xcc, $\x01\0"
5849
17.6k
    /* 1882 */ "bl,pn %xcc, $\x01\0"
5850
17.6k
    /* 1897 */ "bgu,pn %xcc, $\x01\0"
5851
17.6k
    /* 1913 */ "bleu,pn %xcc, $\x01\0"
5852
17.6k
    /* 1930 */ "bcc,pn %xcc, $\x01\0"
5853
17.6k
    /* 1946 */ "bcs,pn %xcc, $\x01\0"
5854
17.6k
    /* 1962 */ "bpos,pn %xcc, $\x01\0"
5855
17.6k
    /* 1979 */ "bneg,pn %xcc, $\x01\0"
5856
17.6k
    /* 1996 */ "bvc,pn %xcc, $\x01\0"
5857
17.6k
    /* 2012 */ "bvs,pn %xcc, $\x01\0"
5858
17.6k
    /* 2028 */ "cas [$\x02], $\x03, $\x01\0"
5859
17.6k
    /* 2045 */ "casl [$\x02], $\x03, $\x01\0"
5860
17.6k
    /* 2063 */ "casx [$\x02], $\x03, $\x01\0"
5861
17.6k
    /* 2081 */ "casxl [$\x02], $\x03, $\x01\0"
5862
17.6k
    /* 2100 */ "fmovda %icc, $\x02, $\x01\0"
5863
17.6k
    /* 2120 */ "fmovdn %icc, $\x02, $\x01\0"
5864
17.6k
    /* 2140 */ "fmovdne %icc, $\x02, $\x01\0"
5865
17.6k
    /* 2161 */ "fmovde %icc, $\x02, $\x01\0"
5866
17.6k
    /* 2181 */ "fmovdg %icc, $\x02, $\x01\0"
5867
17.6k
    /* 2201 */ "fmovdle %icc, $\x02, $\x01\0"
5868
17.6k
    /* 2222 */ "fmovdge %icc, $\x02, $\x01\0"
5869
17.6k
    /* 2243 */ "fmovdl %icc, $\x02, $\x01\0"
5870
17.6k
    /* 2263 */ "fmovdgu %icc, $\x02, $\x01\0"
5871
17.6k
    /* 2284 */ "fmovdleu %icc, $\x02, $\x01\0"
5872
17.6k
    /* 2306 */ "fmovdcc %icc, $\x02, $\x01\0"
5873
17.6k
    /* 2327 */ "fmovdcs %icc, $\x02, $\x01\0"
5874
17.6k
    /* 2348 */ "fmovdpos %icc, $\x02, $\x01\0"
5875
17.6k
    /* 2370 */ "fmovdneg %icc, $\x02, $\x01\0"
5876
17.6k
    /* 2392 */ "fmovdvc %icc, $\x02, $\x01\0"
5877
17.6k
    /* 2413 */ "fmovdvs %icc, $\x02, $\x01\0"
5878
17.6k
    /* 2434 */ "fmovda %xcc, $\x02, $\x01\0"
5879
17.6k
    /* 2454 */ "fmovdn %xcc, $\x02, $\x01\0"
5880
17.6k
    /* 2474 */ "fmovdne %xcc, $\x02, $\x01\0"
5881
17.6k
    /* 2495 */ "fmovde %xcc, $\x02, $\x01\0"
5882
17.6k
    /* 2515 */ "fmovdg %xcc, $\x02, $\x01\0"
5883
17.6k
    /* 2535 */ "fmovdle %xcc, $\x02, $\x01\0"
5884
17.6k
    /* 2556 */ "fmovdge %xcc, $\x02, $\x01\0"
5885
17.6k
    /* 2577 */ "fmovdl %xcc, $\x02, $\x01\0"
5886
17.6k
    /* 2597 */ "fmovdgu %xcc, $\x02, $\x01\0"
5887
17.6k
    /* 2618 */ "fmovdleu %xcc, $\x02, $\x01\0"
5888
17.6k
    /* 2640 */ "fmovdcc %xcc, $\x02, $\x01\0"
5889
17.6k
    /* 2661 */ "fmovdcs %xcc, $\x02, $\x01\0"
5890
17.6k
    /* 2682 */ "fmovdpos %xcc, $\x02, $\x01\0"
5891
17.6k
    /* 2704 */ "fmovdneg %xcc, $\x02, $\x01\0"
5892
17.6k
    /* 2726 */ "fmovdvc %xcc, $\x02, $\x01\0"
5893
17.6k
    /* 2747 */ "fmovdvs %xcc, $\x02, $\x01\0"
5894
17.6k
    /* 2768 */ "fmovqa %icc, $\x02, $\x01\0"
5895
17.6k
    /* 2788 */ "fmovqn %icc, $\x02, $\x01\0"
5896
17.6k
    /* 2808 */ "fmovqne %icc, $\x02, $\x01\0"
5897
17.6k
    /* 2829 */ "fmovqe %icc, $\x02, $\x01\0"
5898
17.6k
    /* 2849 */ "fmovqg %icc, $\x02, $\x01\0"
5899
17.6k
    /* 2869 */ "fmovqle %icc, $\x02, $\x01\0"
5900
17.6k
    /* 2890 */ "fmovqge %icc, $\x02, $\x01\0"
5901
17.6k
    /* 2911 */ "fmovql %icc, $\x02, $\x01\0"
5902
17.6k
    /* 2931 */ "fmovqgu %icc, $\x02, $\x01\0"
5903
17.6k
    /* 2952 */ "fmovqleu %icc, $\x02, $\x01\0"
5904
17.6k
    /* 2974 */ "fmovqcc %icc, $\x02, $\x01\0"
5905
17.6k
    /* 2995 */ "fmovqcs %icc, $\x02, $\x01\0"
5906
17.6k
    /* 3016 */ "fmovqpos %icc, $\x02, $\x01\0"
5907
17.6k
    /* 3038 */ "fmovqneg %icc, $\x02, $\x01\0"
5908
17.6k
    /* 3060 */ "fmovqvc %icc, $\x02, $\x01\0"
5909
17.6k
    /* 3081 */ "fmovqvs %icc, $\x02, $\x01\0"
5910
17.6k
    /* 3102 */ "fmovqa %xcc, $\x02, $\x01\0"
5911
17.6k
    /* 3122 */ "fmovqn %xcc, $\x02, $\x01\0"
5912
17.6k
    /* 3142 */ "fmovqne %xcc, $\x02, $\x01\0"
5913
17.6k
    /* 3163 */ "fmovqe %xcc, $\x02, $\x01\0"
5914
17.6k
    /* 3183 */ "fmovqg %xcc, $\x02, $\x01\0"
5915
17.6k
    /* 3203 */ "fmovqle %xcc, $\x02, $\x01\0"
5916
17.6k
    /* 3224 */ "fmovqge %xcc, $\x02, $\x01\0"
5917
17.6k
    /* 3245 */ "fmovql %xcc, $\x02, $\x01\0"
5918
17.6k
    /* 3265 */ "fmovqgu %xcc, $\x02, $\x01\0"
5919
17.6k
    /* 3286 */ "fmovqleu %xcc, $\x02, $\x01\0"
5920
17.6k
    /* 3308 */ "fmovqcc %xcc, $\x02, $\x01\0"
5921
17.6k
    /* 3329 */ "fmovqcs %xcc, $\x02, $\x01\0"
5922
17.6k
    /* 3350 */ "fmovqpos %xcc, $\x02, $\x01\0"
5923
17.6k
    /* 3372 */ "fmovqneg %xcc, $\x02, $\x01\0"
5924
17.6k
    /* 3394 */ "fmovqvc %xcc, $\x02, $\x01\0"
5925
17.6k
    /* 3415 */ "fmovqvs %xcc, $\x02, $\x01\0"
5926
17.6k
    /* 3436 */ "fmovrdz $\x02, $\x03, $\x01\0"
5927
17.6k
    /* 3455 */ "fmovrdlez $\x02, $\x03, $\x01\0"
5928
17.6k
    /* 3476 */ "fmovrdlz $\x02, $\x03, $\x01\0"
5929
17.6k
    /* 3496 */ "fmovrdnz $\x02, $\x03, $\x01\0"
5930
17.6k
    /* 3516 */ "fmovrdgz $\x02, $\x03, $\x01\0"
5931
17.6k
    /* 3536 */ "fmovrdgez $\x02, $\x03, $\x01\0"
5932
17.6k
    /* 3557 */ "fmovrqz $\x02, $\x03, $\x01\0"
5933
17.6k
    /* 3576 */ "fmovrqlez $\x02, $\x03, $\x01\0"
5934
17.6k
    /* 3597 */ "fmovrqlz $\x02, $\x03, $\x01\0"
5935
17.6k
    /* 3617 */ "fmovrqnz $\x02, $\x03, $\x01\0"
5936
17.6k
    /* 3637 */ "fmovrqgz $\x02, $\x03, $\x01\0"
5937
17.6k
    /* 3657 */ "fmovrqgez $\x02, $\x03, $\x01\0"
5938
17.6k
    /* 3678 */ "fmovrsz $\x02, $\x03, $\x01\0"
5939
17.6k
    /* 3697 */ "fmovrslez $\x02, $\x03, $\x01\0"
5940
17.6k
    /* 3718 */ "fmovrslz $\x02, $\x03, $\x01\0"
5941
17.6k
    /* 3738 */ "fmovrsnz $\x02, $\x03, $\x01\0"
5942
17.6k
    /* 3758 */ "fmovrsgz $\x02, $\x03, $\x01\0"
5943
17.6k
    /* 3778 */ "fmovrsgez $\x02, $\x03, $\x01\0"
5944
17.6k
    /* 3799 */ "fmovsa %icc, $\x02, $\x01\0"
5945
17.6k
    /* 3819 */ "fmovsn %icc, $\x02, $\x01\0"
5946
17.6k
    /* 3839 */ "fmovsne %icc, $\x02, $\x01\0"
5947
17.6k
    /* 3860 */ "fmovse %icc, $\x02, $\x01\0"
5948
17.6k
    /* 3880 */ "fmovsg %icc, $\x02, $\x01\0"
5949
17.6k
    /* 3900 */ "fmovsle %icc, $\x02, $\x01\0"
5950
17.6k
    /* 3921 */ "fmovsge %icc, $\x02, $\x01\0"
5951
17.6k
    /* 3942 */ "fmovsl %icc, $\x02, $\x01\0"
5952
17.6k
    /* 3962 */ "fmovsgu %icc, $\x02, $\x01\0"
5953
17.6k
    /* 3983 */ "fmovsleu %icc, $\x02, $\x01\0"
5954
17.6k
    /* 4005 */ "fmovscc %icc, $\x02, $\x01\0"
5955
17.6k
    /* 4026 */ "fmovscs %icc, $\x02, $\x01\0"
5956
17.6k
    /* 4047 */ "fmovspos %icc, $\x02, $\x01\0"
5957
17.6k
    /* 4069 */ "fmovsneg %icc, $\x02, $\x01\0"
5958
17.6k
    /* 4091 */ "fmovsvc %icc, $\x02, $\x01\0"
5959
17.6k
    /* 4112 */ "fmovsvs %icc, $\x02, $\x01\0"
5960
17.6k
    /* 4133 */ "fmovsa %xcc, $\x02, $\x01\0"
5961
17.6k
    /* 4153 */ "fmovsn %xcc, $\x02, $\x01\0"
5962
17.6k
    /* 4173 */ "fmovsne %xcc, $\x02, $\x01\0"
5963
17.6k
    /* 4194 */ "fmovse %xcc, $\x02, $\x01\0"
5964
17.6k
    /* 4214 */ "fmovsg %xcc, $\x02, $\x01\0"
5965
17.6k
    /* 4234 */ "fmovsle %xcc, $\x02, $\x01\0"
5966
17.6k
    /* 4255 */ "fmovsge %xcc, $\x02, $\x01\0"
5967
17.6k
    /* 4276 */ "fmovsl %xcc, $\x02, $\x01\0"
5968
17.6k
    /* 4296 */ "fmovsgu %xcc, $\x02, $\x01\0"
5969
17.6k
    /* 4317 */ "fmovsleu %xcc, $\x02, $\x01\0"
5970
17.6k
    /* 4339 */ "fmovscc %xcc, $\x02, $\x01\0"
5971
17.6k
    /* 4360 */ "fmovscs %xcc, $\x02, $\x01\0"
5972
17.6k
    /* 4381 */ "fmovspos %xcc, $\x02, $\x01\0"
5973
17.6k
    /* 4403 */ "fmovsneg %xcc, $\x02, $\x01\0"
5974
17.6k
    /* 4425 */ "fmovsvc %xcc, $\x02, $\x01\0"
5975
17.6k
    /* 4446 */ "fmovsvs %xcc, $\x02, $\x01\0"
5976
17.6k
    /* 4467 */ "mova %icc, $\x02, $\x01\0"
5977
17.6k
    /* 4485 */ "movn %icc, $\x02, $\x01\0"
5978
17.6k
    /* 4503 */ "movne %icc, $\x02, $\x01\0"
5979
17.6k
    /* 4522 */ "move %icc, $\x02, $\x01\0"
5980
17.6k
    /* 4540 */ "movg %icc, $\x02, $\x01\0"
5981
17.6k
    /* 4558 */ "movle %icc, $\x02, $\x01\0"
5982
17.6k
    /* 4577 */ "movge %icc, $\x02, $\x01\0"
5983
17.6k
    /* 4596 */ "movl %icc, $\x02, $\x01\0"
5984
17.6k
    /* 4614 */ "movgu %icc, $\x02, $\x01\0"
5985
17.6k
    /* 4633 */ "movleu %icc, $\x02, $\x01\0"
5986
17.6k
    /* 4653 */ "movcc %icc, $\x02, $\x01\0"
5987
17.6k
    /* 4672 */ "movcs %icc, $\x02, $\x01\0"
5988
17.6k
    /* 4691 */ "movpos %icc, $\x02, $\x01\0"
5989
17.6k
    /* 4711 */ "movneg %icc, $\x02, $\x01\0"
5990
17.6k
    /* 4731 */ "movvc %icc, $\x02, $\x01\0"
5991
17.6k
    /* 4750 */ "movvs %icc, $\x02, $\x01\0"
5992
17.6k
    /* 4769 */ "movrz $\x02, $\x03, $\x01\0"
5993
17.6k
    /* 4786 */ "movrlez $\x02, $\x03, $\x01\0"
5994
17.6k
    /* 4805 */ "movrlz $\x02, $\x03, $\x01\0"
5995
17.6k
    /* 4823 */ "movrnz $\x02, $\x03, $\x01\0"
5996
17.6k
    /* 4841 */ "movrgz $\x02, $\x03, $\x01\0"
5997
17.6k
    /* 4859 */ "movrgez $\x02, $\x03, $\x01\0"
5998
17.6k
    /* 4878 */ "mova %xcc, $\x02, $\x01\0"
5999
17.6k
    /* 4896 */ "movn %xcc, $\x02, $\x01\0"
6000
17.6k
    /* 4914 */ "movne %xcc, $\x02, $\x01\0"
6001
17.6k
    /* 4933 */ "move %xcc, $\x02, $\x01\0"
6002
17.6k
    /* 4951 */ "movg %xcc, $\x02, $\x01\0"
6003
17.6k
    /* 4969 */ "movle %xcc, $\x02, $\x01\0"
6004
17.6k
    /* 4988 */ "movge %xcc, $\x02, $\x01\0"
6005
17.6k
    /* 5007 */ "movl %xcc, $\x02, $\x01\0"
6006
17.6k
    /* 5025 */ "movgu %xcc, $\x02, $\x01\0"
6007
17.6k
    /* 5044 */ "movleu %xcc, $\x02, $\x01\0"
6008
17.6k
    /* 5064 */ "movcc %xcc, $\x02, $\x01\0"
6009
17.6k
    /* 5083 */ "movcs %xcc, $\x02, $\x01\0"
6010
17.6k
    /* 5102 */ "movpos %xcc, $\x02, $\x01\0"
6011
17.6k
    /* 5122 */ "movneg %xcc, $\x02, $\x01\0"
6012
17.6k
    /* 5142 */ "movvc %xcc, $\x02, $\x01\0"
6013
17.6k
    /* 5161 */ "movvs %xcc, $\x02, $\x01\0"
6014
17.6k
    /* 5180 */ "tst $\x02\0"
6015
17.6k
    /* 5187 */ "mov $\x03, $\x01\0"
6016
17.6k
    /* 5198 */ "restore\0"
6017
17.6k
    /* 5206 */ "ret\0"
6018
17.6k
    /* 5210 */ "retl\0"
6019
17.6k
    /* 5215 */ "save\0"
6020
17.6k
    /* 5220 */ "cmp $\x02, $\x03\0"
6021
17.6k
    /* 5231 */ "ta %icc, $\x02\0"
6022
17.6k
    /* 5243 */ "ta %icc, $\x01 + $\x02\0"
6023
17.6k
    /* 5260 */ "tn %icc, $\x02\0"
6024
17.6k
    /* 5272 */ "tn %icc, $\x01 + $\x02\0"
6025
17.6k
    /* 5289 */ "tne %icc, $\x02\0"
6026
17.6k
    /* 5302 */ "tne %icc, $\x01 + $\x02\0"
6027
17.6k
    /* 5320 */ "te %icc, $\x02\0"
6028
17.6k
    /* 5332 */ "te %icc, $\x01 + $\x02\0"
6029
17.6k
    /* 5349 */ "tg %icc, $\x02\0"
6030
17.6k
    /* 5361 */ "tg %icc, $\x01 + $\x02\0"
6031
17.6k
    /* 5378 */ "tle %icc, $\x02\0"
6032
17.6k
    /* 5391 */ "tle %icc, $\x01 + $\x02\0"
6033
17.6k
    /* 5409 */ "tge %icc, $\x02\0"
6034
17.6k
    /* 5422 */ "tge %icc, $\x01 + $\x02\0"
6035
17.6k
    /* 5440 */ "tl %icc, $\x02\0"
6036
17.6k
    /* 5452 */ "tl %icc, $\x01 + $\x02\0"
6037
17.6k
    /* 5469 */ "tgu %icc, $\x02\0"
6038
17.6k
    /* 5482 */ "tgu %icc, $\x01 + $\x02\0"
6039
17.6k
    /* 5500 */ "tleu %icc, $\x02\0"
6040
17.6k
    /* 5514 */ "tleu %icc, $\x01 + $\x02\0"
6041
17.6k
    /* 5533 */ "tcc %icc, $\x02\0"
6042
17.6k
    /* 5546 */ "tcc %icc, $\x01 + $\x02\0"
6043
17.6k
    /* 5564 */ "tcs %icc, $\x02\0"
6044
17.6k
    /* 5577 */ "tcs %icc, $\x01 + $\x02\0"
6045
17.6k
    /* 5595 */ "tpos %icc, $\x02\0"
6046
17.6k
    /* 5609 */ "tpos %icc, $\x01 + $\x02\0"
6047
17.6k
    /* 5628 */ "tneg %icc, $\x02\0"
6048
17.6k
    /* 5642 */ "tneg %icc, $\x01 + $\x02\0"
6049
17.6k
    /* 5661 */ "tvc %icc, $\x02\0"
6050
17.6k
    /* 5674 */ "tvc %icc, $\x01 + $\x02\0"
6051
17.6k
    /* 5692 */ "tvs %icc, $\x02\0"
6052
17.6k
    /* 5705 */ "tvs %icc, $\x01 + $\x02\0"
6053
17.6k
    /* 5723 */ "ta $\x02\0"
6054
17.6k
    /* 5729 */ "ta $\x01 + $\x02\0"
6055
17.6k
    /* 5740 */ "tn $\x02\0"
6056
17.6k
    /* 5746 */ "tn $\x01 + $\x02\0"
6057
17.6k
    /* 5757 */ "tne $\x02\0"
6058
17.6k
    /* 5764 */ "tne $\x01 + $\x02\0"
6059
17.6k
    /* 5776 */ "te $\x02\0"
6060
17.6k
    /* 5782 */ "te $\x01 + $\x02\0"
6061
17.6k
    /* 5793 */ "tg $\x02\0"
6062
17.6k
    /* 5799 */ "tg $\x01 + $\x02\0"
6063
17.6k
    /* 5810 */ "tle $\x02\0"
6064
17.6k
    /* 5817 */ "tle $\x01 + $\x02\0"
6065
17.6k
    /* 5829 */ "tge $\x02\0"
6066
17.6k
    /* 5836 */ "tge $\x01 + $\x02\0"
6067
17.6k
    /* 5848 */ "tl $\x02\0"
6068
17.6k
    /* 5854 */ "tl $\x01 + $\x02\0"
6069
17.6k
    /* 5865 */ "tgu $\x02\0"
6070
17.6k
    /* 5872 */ "tgu $\x01 + $\x02\0"
6071
17.6k
    /* 5884 */ "tleu $\x02\0"
6072
17.6k
    /* 5892 */ "tleu $\x01 + $\x02\0"
6073
17.6k
    /* 5905 */ "tcc $\x02\0"
6074
17.6k
    /* 5912 */ "tcc $\x01 + $\x02\0"
6075
17.6k
    /* 5924 */ "tcs $\x02\0"
6076
17.6k
    /* 5931 */ "tcs $\x01 + $\x02\0"
6077
17.6k
    /* 5943 */ "tpos $\x02\0"
6078
17.6k
    /* 5951 */ "tpos $\x01 + $\x02\0"
6079
17.6k
    /* 5964 */ "tneg $\x02\0"
6080
17.6k
    /* 5972 */ "tneg $\x01 + $\x02\0"
6081
17.6k
    /* 5985 */ "tvc $\x02\0"
6082
17.6k
    /* 5992 */ "tvc $\x01 + $\x02\0"
6083
17.6k
    /* 6004 */ "tvs $\x02\0"
6084
17.6k
    /* 6011 */ "tvs $\x01 + $\x02\0"
6085
17.6k
    /* 6023 */ "ta %xcc, $\x02\0"
6086
17.6k
    /* 6035 */ "ta %xcc, $\x01 + $\x02\0"
6087
17.6k
    /* 6052 */ "tn %xcc, $\x02\0"
6088
17.6k
    /* 6064 */ "tn %xcc, $\x01 + $\x02\0"
6089
17.6k
    /* 6081 */ "tne %xcc, $\x02\0"
6090
17.6k
    /* 6094 */ "tne %xcc, $\x01 + $\x02\0"
6091
17.6k
    /* 6112 */ "te %xcc, $\x02\0"
6092
17.6k
    /* 6124 */ "te %xcc, $\x01 + $\x02\0"
6093
17.6k
    /* 6141 */ "tg %xcc, $\x02\0"
6094
17.6k
    /* 6153 */ "tg %xcc, $\x01 + $\x02\0"
6095
17.6k
    /* 6170 */ "tle %xcc, $\x02\0"
6096
17.6k
    /* 6183 */ "tle %xcc, $\x01 + $\x02\0"
6097
17.6k
    /* 6201 */ "tge %xcc, $\x02\0"
6098
17.6k
    /* 6214 */ "tge %xcc, $\x01 + $\x02\0"
6099
17.6k
    /* 6232 */ "tl %xcc, $\x02\0"
6100
17.6k
    /* 6244 */ "tl %xcc, $\x01 + $\x02\0"
6101
17.6k
    /* 6261 */ "tgu %xcc, $\x02\0"
6102
17.6k
    /* 6274 */ "tgu %xcc, $\x01 + $\x02\0"
6103
17.6k
    /* 6292 */ "tleu %xcc, $\x02\0"
6104
17.6k
    /* 6306 */ "tleu %xcc, $\x01 + $\x02\0"
6105
17.6k
    /* 6325 */ "tcc %xcc, $\x02\0"
6106
17.6k
    /* 6338 */ "tcc %xcc, $\x01 + $\x02\0"
6107
17.6k
    /* 6356 */ "tcs %xcc, $\x02\0"
6108
17.6k
    /* 6369 */ "tcs %xcc, $\x01 + $\x02\0"
6109
17.6k
    /* 6387 */ "tpos %xcc, $\x02\0"
6110
17.6k
    /* 6401 */ "tpos %xcc, $\x01 + $\x02\0"
6111
17.6k
    /* 6420 */ "tneg %xcc, $\x02\0"
6112
17.6k
    /* 6434 */ "tneg %xcc, $\x01 + $\x02\0"
6113
17.6k
    /* 6453 */ "tvc %xcc, $\x02\0"
6114
17.6k
    /* 6466 */ "tvc %xcc, $\x01 + $\x02\0"
6115
17.6k
    /* 6484 */ "tvs %xcc, $\x02\0"
6116
17.6k
    /* 6497 */ "tvs %xcc, $\x01 + $\x02\0"
6117
17.6k
    /* 6515 */ "fcmpd $\x02, $\x03\0"
6118
17.6k
    /* 6528 */ "fcmped $\x02, $\x03\0"
6119
17.6k
    /* 6542 */ "fcmpeq $\x02, $\x03\0"
6120
17.6k
    /* 6556 */ "fcmpes $\x02, $\x03\0"
6121
17.6k
    /* 6570 */ "fcmpq $\x02, $\x03\0"
6122
17.6k
    /* 6583 */ "fcmps $\x02, $\x03\0"
6123
17.6k
    /* 6596 */ "fmovda $\x02, $\x03, $\x01\0"
6124
17.6k
    /* 6614 */ "fmovdn $\x02, $\x03, $\x01\0"
6125
17.6k
    /* 6632 */ "fmovdu $\x02, $\x03, $\x01\0"
6126
17.6k
    /* 6650 */ "fmovdg $\x02, $\x03, $\x01\0"
6127
17.6k
    /* 6668 */ "fmovdug $\x02, $\x03, $\x01\0"
6128
17.6k
    /* 6687 */ "fmovdl $\x02, $\x03, $\x01\0"
6129
17.6k
    /* 6705 */ "fmovdul $\x02, $\x03, $\x01\0"
6130
17.6k
    /* 6724 */ "fmovdlg $\x02, $\x03, $\x01\0"
6131
17.6k
    /* 6743 */ "fmovdne $\x02, $\x03, $\x01\0"
6132
17.6k
    /* 6762 */ "fmovde $\x02, $\x03, $\x01\0"
6133
17.6k
    /* 6780 */ "fmovdue $\x02, $\x03, $\x01\0"
6134
17.6k
    /* 6799 */ "fmovdge $\x02, $\x03, $\x01\0"
6135
17.6k
    /* 6818 */ "fmovduge $\x02, $\x03, $\x01\0"
6136
17.6k
    /* 6838 */ "fmovdle $\x02, $\x03, $\x01\0"
6137
17.6k
    /* 6857 */ "fmovdule $\x02, $\x03, $\x01\0"
6138
17.6k
    /* 6877 */ "fmovdo $\x02, $\x03, $\x01\0"
6139
17.6k
    /* 6895 */ "fmovqa $\x02, $\x03, $\x01\0"
6140
17.6k
    /* 6913 */ "fmovqn $\x02, $\x03, $\x01\0"
6141
17.6k
    /* 6931 */ "fmovqu $\x02, $\x03, $\x01\0"
6142
17.6k
    /* 6949 */ "fmovqg $\x02, $\x03, $\x01\0"
6143
17.6k
    /* 6967 */ "fmovqug $\x02, $\x03, $\x01\0"
6144
17.6k
    /* 6986 */ "fmovql $\x02, $\x03, $\x01\0"
6145
17.6k
    /* 7004 */ "fmovqul $\x02, $\x03, $\x01\0"
6146
17.6k
    /* 7023 */ "fmovqlg $\x02, $\x03, $\x01\0"
6147
17.6k
    /* 7042 */ "fmovqne $\x02, $\x03, $\x01\0"
6148
17.6k
    /* 7061 */ "fmovqe $\x02, $\x03, $\x01\0"
6149
17.6k
    /* 7079 */ "fmovque $\x02, $\x03, $\x01\0"
6150
17.6k
    /* 7098 */ "fmovqge $\x02, $\x03, $\x01\0"
6151
17.6k
    /* 7117 */ "fmovquge $\x02, $\x03, $\x01\0"
6152
17.6k
    /* 7137 */ "fmovqle $\x02, $\x03, $\x01\0"
6153
17.6k
    /* 7156 */ "fmovqule $\x02, $\x03, $\x01\0"
6154
17.6k
    /* 7176 */ "fmovqo $\x02, $\x03, $\x01\0"
6155
17.6k
    /* 7194 */ "fmovsa $\x02, $\x03, $\x01\0"
6156
17.6k
    /* 7212 */ "fmovsn $\x02, $\x03, $\x01\0"
6157
17.6k
    /* 7230 */ "fmovsu $\x02, $\x03, $\x01\0"
6158
17.6k
    /* 7248 */ "fmovsg $\x02, $\x03, $\x01\0"
6159
17.6k
    /* 7266 */ "fmovsug $\x02, $\x03, $\x01\0"
6160
17.6k
    /* 7285 */ "fmovsl $\x02, $\x03, $\x01\0"
6161
17.6k
    /* 7303 */ "fmovsul $\x02, $\x03, $\x01\0"
6162
17.6k
    /* 7322 */ "fmovslg $\x02, $\x03, $\x01\0"
6163
17.6k
    /* 7341 */ "fmovsne $\x02, $\x03, $\x01\0"
6164
17.6k
    /* 7360 */ "fmovse $\x02, $\x03, $\x01\0"
6165
17.6k
    /* 7378 */ "fmovsue $\x02, $\x03, $\x01\0"
6166
17.6k
    /* 7397 */ "fmovsge $\x02, $\x03, $\x01\0"
6167
17.6k
    /* 7416 */ "fmovsuge $\x02, $\x03, $\x01\0"
6168
17.6k
    /* 7436 */ "fmovsle $\x02, $\x03, $\x01\0"
6169
17.6k
    /* 7455 */ "fmovsule $\x02, $\x03, $\x01\0"
6170
17.6k
    /* 7475 */ "fmovso $\x02, $\x03, $\x01\0"
6171
17.6k
    /* 7493 */ "mova $\x02, $\x03, $\x01\0"
6172
17.6k
    /* 7509 */ "movn $\x02, $\x03, $\x01\0"
6173
17.6k
    /* 7525 */ "movu $\x02, $\x03, $\x01\0"
6174
17.6k
    /* 7541 */ "movg $\x02, $\x03, $\x01\0"
6175
17.6k
    /* 7557 */ "movug $\x02, $\x03, $\x01\0"
6176
17.6k
    /* 7574 */ "movl $\x02, $\x03, $\x01\0"
6177
17.6k
    /* 7590 */ "movul $\x02, $\x03, $\x01\0"
6178
17.6k
    /* 7607 */ "movlg $\x02, $\x03, $\x01\0"
6179
17.6k
    /* 7624 */ "movne $\x02, $\x03, $\x01\0"
6180
17.6k
    /* 7641 */ "move $\x02, $\x03, $\x01\0"
6181
17.6k
    /* 7657 */ "movue $\x02, $\x03, $\x01\0"
6182
17.6k
    /* 7674 */ "movge $\x02, $\x03, $\x01\0"
6183
17.6k
    /* 7691 */ "movuge $\x02, $\x03, $\x01\0"
6184
17.6k
    /* 7709 */ "movle $\x02, $\x03, $\x01\0"
6185
17.6k
    /* 7726 */ "movule $\x02, $\x03, $\x01\0"
6186
17.6k
    /* 7744 */ "movo $\x02, $\x03, $\x01\0"
6187
17.6k
  ;
6188
6189
17.6k
#ifndef NDEBUG
6190
  //static struct SortCheck {
6191
  //  SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
6192
  //    assert(std::is_sorted(
6193
  //               OpToPatterns.begin(), OpToPatterns.end(),
6194
  //               [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
6195
  //                 return L.Opcode < R.Opcode;
6196
  //               }) &&
6197
  //           "tablegen failed to sort opcode patterns");
6198
  //  }
6199
  //} sortCheckVar(OpToPatterns);
6200
17.6k
#endif
6201
6202
17.6k
  AliasMatchingData M = {
6203
17.6k
    OpToPatterns,
6204
17.6k
    Patterns,
6205
17.6k
    Conds,
6206
17.6k
    AsmStrings,
6207
17.6k
    NULL,
6208
17.6k
  };
6209
17.6k
  const char *AsmString = matchAliasPatterns(MI, &M);
6210
17.6k
  if (!AsmString) return false;
6211
6212
1.15k
  unsigned I = 0;
6213
5.81k
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
6214
4.65k
         AsmString[I] != '$' && AsmString[I] != '\0')
6215
4.65k
    ++I;
6216
1.15k
  SStream_concat1(OS, '\t');
6217
1.15k
  char *substr = malloc(I+1);
6218
1.15k
  memcpy(substr, AsmString, I);
6219
1.15k
  substr[I] = '\0';
6220
1.15k
  SStream_concat0(OS, substr);
6221
1.15k
  free(substr);
6222
1.15k
  if (AsmString[I] != '\0') {
6223
1.15k
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
6224
1.15k
      SStream_concat1(OS, '\t');
6225
1.15k
      ++I;
6226
1.15k
    }
6227
4.71k
    do {
6228
4.71k
      if (AsmString[I] == '$') {
6229
1.97k
        ++I;
6230
1.97k
        if (AsmString[I] == (char)0xff) {
6231
0
          ++I;
6232
0
          int OpIdx = AsmString[I++] - 1;
6233
0
          int PrintMethodIdx = AsmString[I++] - 1;
6234
0
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
6235
0
        } else
6236
1.97k
          printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
6237
2.73k
      } else {
6238
2.73k
        SStream_concat1(OS, AsmString[I++]);
6239
2.73k
      }
6240
4.71k
    } while (AsmString[I] != '\0');
6241
1.15k
  }
6242
6243
1.15k
  return true;
6244
#else
6245
  return false;
6246
#endif // CAPSTONE_DIET
6247
17.6k
}
6248
6249
static void printCustomAliasOperand(
6250
         MCInst *MI, uint64_t Address, unsigned OpIdx,
6251
         unsigned PrintMethodIdx,
6252
0
         SStream *OS) {
6253
0
#ifndef CAPSTONE_DIET
6254
0
  CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
6255
0
#endif // CAPSTONE_DIET
6256
0
}
6257
6258
#endif // PRINT_ALIAS_INSTR