Coverage Report

Created: 2025-10-12 06:32

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source
1
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
4
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Do not edit. */
10
11
/* Capstone's LLVM TableGen Backends: */
12
/* https://github.com/capstone-engine/llvm-capstone */
13
14
#include <capstone/platform.h>
15
#include "../../cs_priv.h"
16
17
/// getMnemonic - This method is automatically generated by tablegen
18
/// from the instruction set description.
19
29.8k
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
20
29.8k
#ifndef CAPSTONE_DIET
21
29.8k
  static const char AsmStrs[] = {
22
29.8k
  /* 0 */ "fcmpd %fcc0, \0"
23
29.8k
  /* 14 */ "fcmpq %fcc0, \0"
24
29.8k
  /* 28 */ "fcmps %fcc0, \0"
25
29.8k
  /* 42 */ "rd %wim, \0"
26
29.8k
  /* 52 */ "rdpr %fq, \0"
27
29.8k
  /* 63 */ "rd %tbr, \0"
28
29.8k
  /* 73 */ "rd %psr, \0"
29
29.8k
  /* 83 */ "fsrc1 \0"
30
29.8k
  /* 90 */ "fandnot1 \0"
31
29.8k
  /* 100 */ "fnot1 \0"
32
29.8k
  /* 107 */ "fornot1 \0"
33
29.8k
  /* 116 */ "fsra32 \0"
34
29.8k
  /* 124 */ "fpsub32 \0"
35
29.8k
  /* 133 */ "fpadd32 \0"
36
29.8k
  /* 142 */ "edge32 \0"
37
29.8k
  /* 150 */ "fcmple32 \0"
38
29.8k
  /* 160 */ "fcmpne32 \0"
39
29.8k
  /* 170 */ "fpack32 \0"
40
29.8k
  /* 179 */ "cmask32 \0"
41
29.8k
  /* 188 */ "fsll32 \0"
42
29.8k
  /* 196 */ "fsrl32 \0"
43
29.8k
  /* 204 */ "fcmpeq32 \0"
44
29.8k
  /* 214 */ "fslas32 \0"
45
29.8k
  /* 223 */ "fcmpgt32 \0"
46
29.8k
  /* 233 */ "array32 \0"
47
29.8k
  /* 242 */ "fsrc2 \0"
48
29.8k
  /* 249 */ "fandnot2 \0"
49
29.8k
  /* 259 */ "fnot2 \0"
50
29.8k
  /* 266 */ "fornot2 \0"
51
29.8k
  /* 275 */ "fpadd64 \0"
52
29.8k
  /* 284 */ "fsra16 \0"
53
29.8k
  /* 292 */ "fpsub16 \0"
54
29.8k
  /* 301 */ "fpadd16 \0"
55
29.8k
  /* 310 */ "edge16 \0"
56
29.8k
  /* 318 */ "fcmple16 \0"
57
29.8k
  /* 328 */ "fcmpne16 \0"
58
29.8k
  /* 338 */ "fpack16 \0"
59
29.8k
  /* 347 */ "cmask16 \0"
60
29.8k
  /* 356 */ "fsll16 \0"
61
29.8k
  /* 364 */ "fsrl16 \0"
62
29.8k
  /* 372 */ "fchksm16 \0"
63
29.8k
  /* 382 */ "fmean16 \0"
64
29.8k
  /* 391 */ "fcmpeq16 \0"
65
29.8k
  /* 401 */ "fslas16 \0"
66
29.8k
  /* 410 */ "fcmpgt16 \0"
67
29.8k
  /* 420 */ "fmul8x16 \0"
68
29.8k
  /* 430 */ "fmuld8ulx16 \0"
69
29.8k
  /* 443 */ "fmul8ulx16 \0"
70
29.8k
  /* 455 */ "fmuld8sux16 \0"
71
29.8k
  /* 468 */ "fmul8sux16 \0"
72
29.8k
  /* 480 */ "array16 \0"
73
29.8k
  /* 489 */ "edge8 \0"
74
29.8k
  /* 496 */ "cmask8 \0"
75
29.8k
  /* 504 */ "array8 \0"
76
29.8k
  /* 512 */ "!ADJCALLSTACKDOWN \0"
77
29.8k
  /* 531 */ "!ADJCALLSTACKUP \0"
78
29.8k
  /* 548 */ "stba \0"
79
29.8k
  /* 554 */ "stda \0"
80
29.8k
  /* 560 */ "stha \0"
81
29.8k
  /* 566 */ "stqa \0"
82
29.8k
  /* 572 */ "sra \0"
83
29.8k
  /* 577 */ "faligndata \0"
84
29.8k
  /* 589 */ "sta \0"
85
29.8k
  /* 594 */ "stxa \0"
86
29.8k
  /* 600 */ "stb \0"
87
29.8k
  /* 605 */ "sub \0"
88
29.8k
  /* 610 */ "smac \0"
89
29.8k
  /* 616 */ "umac \0"
90
29.8k
  /* 622 */ "tsubcc \0"
91
29.8k
  /* 630 */ "addxccc \0"
92
29.8k
  /* 639 */ "taddcc \0"
93
29.8k
  /* 647 */ "andcc \0"
94
29.8k
  /* 654 */ "smulcc \0"
95
29.8k
  /* 662 */ "umulcc \0"
96
29.8k
  /* 670 */ "andncc \0"
97
29.8k
  /* 678 */ "orncc \0"
98
29.8k
  /* 685 */ "xnorcc \0"
99
29.8k
  /* 693 */ "xorcc \0"
100
29.8k
  /* 700 */ "mulscc \0"
101
29.8k
  /* 708 */ "sdivcc \0"
102
29.8k
  /* 716 */ "udivcc \0"
103
29.8k
  /* 724 */ "subxcc \0"
104
29.8k
  /* 732 */ "addxcc \0"
105
29.8k
  /* 740 */ "popc \0"
106
29.8k
  /* 746 */ "addxc \0"
107
29.8k
  /* 753 */ "fsubd \0"
108
29.8k
  /* 760 */ "fhsubd \0"
109
29.8k
  /* 768 */ "add \0"
110
29.8k
  /* 773 */ "faddd \0"
111
29.8k
  /* 780 */ "fhaddd \0"
112
29.8k
  /* 788 */ "fnhaddd \0"
113
29.8k
  /* 797 */ "fnaddd \0"
114
29.8k
  /* 805 */ "fcmped \0"
115
29.8k
  /* 813 */ "fnegd \0"
116
29.8k
  /* 820 */ "fmuld \0"
117
29.8k
  /* 827 */ "fnmuld \0"
118
29.8k
  /* 835 */ "fsmuld \0"
119
29.8k
  /* 843 */ "fnsmuld \0"
120
29.8k
  /* 852 */ "fand \0"
121
29.8k
  /* 858 */ "fnand \0"
122
29.8k
  /* 865 */ "fexpand \0"
123
29.8k
  /* 874 */ "fitod \0"
124
29.8k
  /* 881 */ "fqtod \0"
125
29.8k
  /* 888 */ "fstod \0"
126
29.8k
  /* 895 */ "fxtod \0"
127
29.8k
  /* 902 */ "movxtod \0"
128
29.8k
  /* 911 */ "fcmpd \0"
129
29.8k
  /* 918 */ "flcmpd \0"
130
29.8k
  /* 926 */ "rd \0"
131
29.8k
  /* 930 */ "fabsd \0"
132
29.8k
  /* 937 */ "fsqrtd \0"
133
29.8k
  /* 945 */ "std \0"
134
29.8k
  /* 950 */ "fdivd \0"
135
29.8k
  /* 957 */ "fmovd \0"
136
29.8k
  /* 964 */ "fpmerge \0"
137
29.8k
  /* 973 */ "bshuffle \0"
138
29.8k
  /* 983 */ "fone \0"
139
29.8k
  /* 989 */ "restore \0"
140
29.8k
  /* 998 */ "save \0"
141
29.8k
  /* 1004 */ "flush \0"
142
29.8k
  /* 1011 */ "sth \0"
143
29.8k
  /* 1016 */ "sethi \0"
144
29.8k
  /* 1023 */ "umulxhi \0"
145
29.8k
  /* 1032 */ "xmulxhi \0"
146
29.8k
  /* 1041 */ "fdtoi \0"
147
29.8k
  /* 1048 */ "fqtoi \0"
148
29.8k
  /* 1055 */ "fstoi \0"
149
29.8k
  /* 1062 */ "bmask \0"
150
29.8k
  /* 1069 */ "edge32l \0"
151
29.8k
  /* 1078 */ "edge16l \0"
152
29.8k
  /* 1087 */ "edge8l \0"
153
29.8k
  /* 1095 */ "fmul8x16al \0"
154
29.8k
  /* 1107 */ "call \0"
155
29.8k
  /* 1113 */ "sll \0"
156
29.8k
  /* 1118 */ "jmpl \0"
157
29.8k
  /* 1124 */ "alignaddrl \0"
158
29.8k
  /* 1136 */ "srl \0"
159
29.8k
  /* 1141 */ "smul \0"
160
29.8k
  /* 1147 */ "umul \0"
161
29.8k
  /* 1153 */ "edge32n \0"
162
29.8k
  /* 1162 */ "edge16n \0"
163
29.8k
  /* 1171 */ "edge8n \0"
164
29.8k
  /* 1179 */ "andn \0"
165
29.8k
  /* 1185 */ "edge32ln \0"
166
29.8k
  /* 1195 */ "edge16ln \0"
167
29.8k
  /* 1205 */ "edge8ln \0"
168
29.8k
  /* 1214 */ "orn \0"
169
29.8k
  /* 1219 */ "pdistn \0"
170
29.8k
  /* 1227 */ "fzero \0"
171
29.8k
  /* 1234 */ "unimp \0"
172
29.8k
  /* 1241 */ "jmp \0"
173
29.8k
  /* 1246 */ "fsubq \0"
174
29.8k
  /* 1253 */ "faddq \0"
175
29.8k
  /* 1260 */ "fcmpeq \0"
176
29.8k
  /* 1268 */ "fnegq \0"
177
29.8k
  /* 1275 */ "fdmulq \0"
178
29.8k
  /* 1283 */ "fmulq \0"
179
29.8k
  /* 1290 */ "fdtoq \0"
180
29.8k
  /* 1297 */ "fitoq \0"
181
29.8k
  /* 1304 */ "fstoq \0"
182
29.8k
  /* 1311 */ "fxtoq \0"
183
29.8k
  /* 1318 */ "fcmpq \0"
184
29.8k
  /* 1325 */ "fabsq \0"
185
29.8k
  /* 1332 */ "fsqrtq \0"
186
29.8k
  /* 1340 */ "stq \0"
187
29.8k
  /* 1345 */ "fdivq \0"
188
29.8k
  /* 1352 */ "fmovq \0"
189
29.8k
  /* 1359 */ "membar \0"
190
29.8k
  /* 1367 */ "alignaddr \0"
191
29.8k
  /* 1378 */ "sir \0"
192
29.8k
  /* 1383 */ "for \0"
193
29.8k
  /* 1388 */ "fnor \0"
194
29.8k
  /* 1394 */ "fxnor \0"
195
29.8k
  /* 1401 */ "fxor \0"
196
29.8k
  /* 1407 */ "rdpr \0"
197
29.8k
  /* 1413 */ "wrpr \0"
198
29.8k
  /* 1419 */ "pwr \0"
199
29.8k
  /* 1424 */ "fsrc1s \0"
200
29.8k
  /* 1432 */ "fandnot1s \0"
201
29.8k
  /* 1443 */ "fnot1s \0"
202
29.8k
  /* 1451 */ "fornot1s \0"
203
29.8k
  /* 1461 */ "fpsub32s \0"
204
29.8k
  /* 1471 */ "fpadd32s \0"
205
29.8k
  /* 1481 */ "fsrc2s \0"
206
29.8k
  /* 1489 */ "fandnot2s \0"
207
29.8k
  /* 1500 */ "fnot2s \0"
208
29.8k
  /* 1508 */ "fornot2s \0"
209
29.8k
  /* 1518 */ "fpsub16s \0"
210
29.8k
  /* 1528 */ "fpadd16s \0"
211
29.8k
  /* 1538 */ "fsubs \0"
212
29.8k
  /* 1545 */ "fhsubs \0"
213
29.8k
  /* 1553 */ "fadds \0"
214
29.8k
  /* 1560 */ "fhadds \0"
215
29.8k
  /* 1568 */ "fnhadds \0"
216
29.8k
  /* 1577 */ "fnadds \0"
217
29.8k
  /* 1585 */ "fands \0"
218
29.8k
  /* 1592 */ "fnands \0"
219
29.8k
  /* 1600 */ "fones \0"
220
29.8k
  /* 1607 */ "fcmpes \0"
221
29.8k
  /* 1615 */ "fnegs \0"
222
29.8k
  /* 1622 */ "fmuls \0"
223
29.8k
  /* 1629 */ "fnmuls \0"
224
29.8k
  /* 1637 */ "fzeros \0"
225
29.8k
  /* 1645 */ "fdtos \0"
226
29.8k
  /* 1652 */ "fitos \0"
227
29.8k
  /* 1659 */ "fqtos \0"
228
29.8k
  /* 1666 */ "movwtos \0"
229
29.8k
  /* 1675 */ "fxtos \0"
230
29.8k
  /* 1682 */ "fcmps \0"
231
29.8k
  /* 1689 */ "flcmps \0"
232
29.8k
  /* 1697 */ "fors \0"
233
29.8k
  /* 1703 */ "fnors \0"
234
29.8k
  /* 1710 */ "fxnors \0"
235
29.8k
  /* 1718 */ "fxors \0"
236
29.8k
  /* 1725 */ "fabss \0"
237
29.8k
  /* 1732 */ "fsqrts \0"
238
29.8k
  /* 1740 */ "fdivs \0"
239
29.8k
  /* 1747 */ "fmovs \0"
240
29.8k
  /* 1754 */ "set \0"
241
29.8k
  /* 1759 */ "lzcnt \0"
242
29.8k
  /* 1766 */ "pdist \0"
243
29.8k
  /* 1773 */ "rett \0"
244
29.8k
  /* 1779 */ "fmul8x16au \0"
245
29.8k
  /* 1791 */ "sdiv \0"
246
29.8k
  /* 1797 */ "udiv \0"
247
29.8k
  /* 1803 */ "tsubcctv \0"
248
29.8k
  /* 1813 */ "taddcctv \0"
249
29.8k
  /* 1823 */ "movstosw \0"
250
29.8k
  /* 1833 */ "movstouw \0"
251
29.8k
  /* 1843 */ "srax \0"
252
29.8k
  /* 1849 */ "subx \0"
253
29.8k
  /* 1855 */ "addx \0"
254
29.8k
  /* 1861 */ "fpackfix \0"
255
29.8k
  /* 1871 */ "sllx \0"
256
29.8k
  /* 1877 */ "srlx \0"
257
29.8k
  /* 1883 */ "xmulx \0"
258
29.8k
  /* 1890 */ "fdtox \0"
259
29.8k
  /* 1897 */ "movdtox \0"
260
29.8k
  /* 1906 */ "fqtox \0"
261
29.8k
  /* 1913 */ "fstox \0"
262
29.8k
  /* 1920 */ "setx \0"
263
29.8k
  /* 1926 */ "stx \0"
264
29.8k
  /* 1931 */ "sdivx \0"
265
29.8k
  /* 1938 */ "udivx \0"
266
29.8k
  /* 1945 */ "; SELECT_CC_DFP_FCC PSEUDO!\0"
267
29.8k
  /* 1973 */ "; SELECT_CC_QFP_FCC PSEUDO!\0"
268
29.8k
  /* 2001 */ "; SELECT_CC_FP_FCC PSEUDO!\0"
269
29.8k
  /* 2028 */ "; SELECT_CC_Int_FCC PSEUDO!\0"
270
29.8k
  /* 2056 */ "; SELECT_CC_DFP_ICC PSEUDO!\0"
271
29.8k
  /* 2084 */ "; SELECT_CC_QFP_ICC PSEUDO!\0"
272
29.8k
  /* 2112 */ "; SELECT_CC_FP_ICC PSEUDO!\0"
273
29.8k
  /* 2139 */ "; SELECT_CC_Int_ICC PSEUDO!\0"
274
29.8k
  /* 2167 */ "; SELECT_CC_DFP_XCC PSEUDO!\0"
275
29.8k
  /* 2195 */ "; SELECT_CC_QFP_XCC PSEUDO!\0"
276
29.8k
  /* 2223 */ "; SELECT_CC_FP_XCC PSEUDO!\0"
277
29.8k
  /* 2250 */ "; SELECT_CC_Int_XCC PSEUDO!\0"
278
29.8k
  /* 2278 */ "jmp %i7+\0"
279
29.8k
  /* 2287 */ "jmp %o7+\0"
280
29.8k
  /* 2296 */ "# XRay Function Patchable RET.\0"
281
29.8k
  /* 2327 */ "# XRay Typed Event Log.\0"
282
29.8k
  /* 2351 */ "# XRay Custom Event Log.\0"
283
29.8k
  /* 2376 */ "# XRay Function Enter.\0"
284
29.8k
  /* 2399 */ "# XRay Tail Call Exit.\0"
285
29.8k
  /* 2422 */ "# XRay Function Exit.\0"
286
29.8k
  /* 2444 */ "flush %g0\0"
287
29.8k
  /* 2454 */ "ta 1\0"
288
29.8k
  /* 2459 */ "ta 3\0"
289
29.8k
  /* 2464 */ "ta 5\0"
290
29.8k
  /* 2469 */ "LIFETIME_END\0"
291
29.8k
  /* 2482 */ "PSEUDO_PROBE\0"
292
29.8k
  /* 2495 */ "BUNDLE\0"
293
29.8k
  /* 2502 */ "DBG_VALUE\0"
294
29.8k
  /* 2512 */ "DBG_INSTR_REF\0"
295
29.8k
  /* 2526 */ "DBG_PHI\0"
296
29.8k
  /* 2534 */ "DBG_LABEL\0"
297
29.8k
  /* 2544 */ "LIFETIME_START\0"
298
29.8k
  /* 2559 */ "DBG_VALUE_LIST\0"
299
29.8k
  /* 2574 */ "std %cq, [\0"
300
29.8k
  /* 2585 */ "std %fq, [\0"
301
29.8k
  /* 2596 */ "st %csr, [\0"
302
29.8k
  /* 2607 */ "st %fsr, [\0"
303
29.8k
  /* 2618 */ "stx %fsr, [\0"
304
29.8k
  /* 2630 */ "ldsba [\0"
305
29.8k
  /* 2638 */ "lduba [\0"
306
29.8k
  /* 2646 */ "ldstuba [\0"
307
29.8k
  /* 2656 */ "ldda [\0"
308
29.8k
  /* 2663 */ "lda [\0"
309
29.8k
  /* 2669 */ "ldsha [\0"
310
29.8k
  /* 2677 */ "lduha [\0"
311
29.8k
  /* 2685 */ "swapa [\0"
312
29.8k
  /* 2693 */ "ldqa [\0"
313
29.8k
  /* 2700 */ "casa [\0"
314
29.8k
  /* 2707 */ "ldswa [\0"
315
29.8k
  /* 2715 */ "ldxa [\0"
316
29.8k
  /* 2722 */ "casxa [\0"
317
29.8k
  /* 2730 */ "ldsb [\0"
318
29.8k
  /* 2737 */ "ldub [\0"
319
29.8k
  /* 2744 */ "ldstub [\0"
320
29.8k
  /* 2753 */ "ldd [\0"
321
29.8k
  /* 2759 */ "ld [\0"
322
29.8k
  /* 2764 */ "prefetch [\0"
323
29.8k
  /* 2775 */ "ldsh [\0"
324
29.8k
  /* 2782 */ "lduh [\0"
325
29.8k
  /* 2789 */ "swap [\0"
326
29.8k
  /* 2796 */ "ldq [\0"
327
29.8k
  /* 2802 */ "ldsw [\0"
328
29.8k
  /* 2809 */ "ldx [\0"
329
29.8k
  /* 2815 */ "cb\0"
330
29.8k
  /* 2818 */ "fb\0"
331
29.8k
  /* 2821 */ "restored\0"
332
29.8k
  /* 2830 */ "saved\0"
333
29.8k
  /* 2836 */ "fmovrd\0"
334
29.8k
  /* 2843 */ "fmovd\0"
335
29.8k
  /* 2849 */ "done\0"
336
29.8k
  /* 2854 */ "# FEntry call\0"
337
29.8k
  /* 2868 */ "siam\0"
338
29.8k
  /* 2873 */ "shutdown\0"
339
29.8k
  /* 2882 */ "nop\0"
340
29.8k
  /* 2886 */ "fmovrq\0"
341
29.8k
  /* 2893 */ "fmovq\0"
342
29.8k
  /* 2899 */ "stbar\0"
343
29.8k
  /* 2905 */ "br\0"
344
29.8k
  /* 2908 */ "movr\0"
345
29.8k
  /* 2913 */ "fmovrs\0"
346
29.8k
  /* 2920 */ "fmovs\0"
347
29.8k
  /* 2926 */ "t\0"
348
29.8k
  /* 2928 */ "mov\0"
349
29.8k
  /* 2932 */ "flushw\0"
350
29.8k
  /* 2939 */ "retry\0"
351
29.8k
};
352
29.8k
#endif // CAPSTONE_DIET
353
354
29.8k
  static const uint32_t OpInfo0[] = {
355
29.8k
    0U, // PHI
356
29.8k
    0U, // INLINEASM
357
29.8k
    0U, // INLINEASM_BR
358
29.8k
    0U, // CFI_INSTRUCTION
359
29.8k
    0U, // EH_LABEL
360
29.8k
    0U, // GC_LABEL
361
29.8k
    0U, // ANNOTATION_LABEL
362
29.8k
    0U, // KILL
363
29.8k
    0U, // EXTRACT_SUBREG
364
29.8k
    0U, // INSERT_SUBREG
365
29.8k
    0U, // IMPLICIT_DEF
366
29.8k
    0U, // SUBREG_TO_REG
367
29.8k
    0U, // COPY_TO_REGCLASS
368
29.8k
    2503U,  // DBG_VALUE
369
29.8k
    2560U,  // DBG_VALUE_LIST
370
29.8k
    2513U,  // DBG_INSTR_REF
371
29.8k
    2527U,  // DBG_PHI
372
29.8k
    2535U,  // DBG_LABEL
373
29.8k
    0U, // REG_SEQUENCE
374
29.8k
    0U, // COPY
375
29.8k
    2496U,  // BUNDLE
376
29.8k
    2545U,  // LIFETIME_START
377
29.8k
    2470U,  // LIFETIME_END
378
29.8k
    2483U,  // PSEUDO_PROBE
379
29.8k
    0U, // ARITH_FENCE
380
29.8k
    0U, // STACKMAP
381
29.8k
    2855U,  // FENTRY_CALL
382
29.8k
    0U, // PATCHPOINT
383
29.8k
    0U, // LOAD_STACK_GUARD
384
29.8k
    0U, // PREALLOCATED_SETUP
385
29.8k
    0U, // PREALLOCATED_ARG
386
29.8k
    0U, // STATEPOINT
387
29.8k
    0U, // LOCAL_ESCAPE
388
29.8k
    0U, // FAULTING_OP
389
29.8k
    0U, // PATCHABLE_OP
390
29.8k
    2377U,  // PATCHABLE_FUNCTION_ENTER
391
29.8k
    2297U,  // PATCHABLE_RET
392
29.8k
    2423U,  // PATCHABLE_FUNCTION_EXIT
393
29.8k
    2400U,  // PATCHABLE_TAIL_CALL
394
29.8k
    2352U,  // PATCHABLE_EVENT_CALL
395
29.8k
    2328U,  // PATCHABLE_TYPED_EVENT_CALL
396
29.8k
    0U, // ICALL_BRANCH_FUNNEL
397
29.8k
    0U, // MEMBARRIER
398
29.8k
    0U, // JUMP_TABLE_DEBUG_INFO
399
29.8k
    0U, // G_ASSERT_SEXT
400
29.8k
    0U, // G_ASSERT_ZEXT
401
29.8k
    0U, // G_ASSERT_ALIGN
402
29.8k
    0U, // G_ADD
403
29.8k
    0U, // G_SUB
404
29.8k
    0U, // G_MUL
405
29.8k
    0U, // G_SDIV
406
29.8k
    0U, // G_UDIV
407
29.8k
    0U, // G_SREM
408
29.8k
    0U, // G_UREM
409
29.8k
    0U, // G_SDIVREM
410
29.8k
    0U, // G_UDIVREM
411
29.8k
    0U, // G_AND
412
29.8k
    0U, // G_OR
413
29.8k
    0U, // G_XOR
414
29.8k
    0U, // G_IMPLICIT_DEF
415
29.8k
    0U, // G_PHI
416
29.8k
    0U, // G_FRAME_INDEX
417
29.8k
    0U, // G_GLOBAL_VALUE
418
29.8k
    0U, // G_CONSTANT_POOL
419
29.8k
    0U, // G_EXTRACT
420
29.8k
    0U, // G_UNMERGE_VALUES
421
29.8k
    0U, // G_INSERT
422
29.8k
    0U, // G_MERGE_VALUES
423
29.8k
    0U, // G_BUILD_VECTOR
424
29.8k
    0U, // G_BUILD_VECTOR_TRUNC
425
29.8k
    0U, // G_CONCAT_VECTORS
426
29.8k
    0U, // G_PTRTOINT
427
29.8k
    0U, // G_INTTOPTR
428
29.8k
    0U, // G_BITCAST
429
29.8k
    0U, // G_FREEZE
430
29.8k
    0U, // G_CONSTANT_FOLD_BARRIER
431
29.8k
    0U, // G_INTRINSIC_FPTRUNC_ROUND
432
29.8k
    0U, // G_INTRINSIC_TRUNC
433
29.8k
    0U, // G_INTRINSIC_ROUND
434
29.8k
    0U, // G_INTRINSIC_LRINT
435
29.8k
    0U, // G_INTRINSIC_ROUNDEVEN
436
29.8k
    0U, // G_READCYCLECOUNTER
437
29.8k
    0U, // G_LOAD
438
29.8k
    0U, // G_SEXTLOAD
439
29.8k
    0U, // G_ZEXTLOAD
440
29.8k
    0U, // G_INDEXED_LOAD
441
29.8k
    0U, // G_INDEXED_SEXTLOAD
442
29.8k
    0U, // G_INDEXED_ZEXTLOAD
443
29.8k
    0U, // G_STORE
444
29.8k
    0U, // G_INDEXED_STORE
445
29.8k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
446
29.8k
    0U, // G_ATOMIC_CMPXCHG
447
29.8k
    0U, // G_ATOMICRMW_XCHG
448
29.8k
    0U, // G_ATOMICRMW_ADD
449
29.8k
    0U, // G_ATOMICRMW_SUB
450
29.8k
    0U, // G_ATOMICRMW_AND
451
29.8k
    0U, // G_ATOMICRMW_NAND
452
29.8k
    0U, // G_ATOMICRMW_OR
453
29.8k
    0U, // G_ATOMICRMW_XOR
454
29.8k
    0U, // G_ATOMICRMW_MAX
455
29.8k
    0U, // G_ATOMICRMW_MIN
456
29.8k
    0U, // G_ATOMICRMW_UMAX
457
29.8k
    0U, // G_ATOMICRMW_UMIN
458
29.8k
    0U, // G_ATOMICRMW_FADD
459
29.8k
    0U, // G_ATOMICRMW_FSUB
460
29.8k
    0U, // G_ATOMICRMW_FMAX
461
29.8k
    0U, // G_ATOMICRMW_FMIN
462
29.8k
    0U, // G_ATOMICRMW_UINC_WRAP
463
29.8k
    0U, // G_ATOMICRMW_UDEC_WRAP
464
29.8k
    0U, // G_FENCE
465
29.8k
    0U, // G_PREFETCH
466
29.8k
    0U, // G_BRCOND
467
29.8k
    0U, // G_BRINDIRECT
468
29.8k
    0U, // G_INVOKE_REGION_START
469
29.8k
    0U, // G_INTRINSIC
470
29.8k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
471
29.8k
    0U, // G_INTRINSIC_CONVERGENT
472
29.8k
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
473
29.8k
    0U, // G_ANYEXT
474
29.8k
    0U, // G_TRUNC
475
29.8k
    0U, // G_CONSTANT
476
29.8k
    0U, // G_FCONSTANT
477
29.8k
    0U, // G_VASTART
478
29.8k
    0U, // G_VAARG
479
29.8k
    0U, // G_SEXT
480
29.8k
    0U, // G_SEXT_INREG
481
29.8k
    0U, // G_ZEXT
482
29.8k
    0U, // G_SHL
483
29.8k
    0U, // G_LSHR
484
29.8k
    0U, // G_ASHR
485
29.8k
    0U, // G_FSHL
486
29.8k
    0U, // G_FSHR
487
29.8k
    0U, // G_ROTR
488
29.8k
    0U, // G_ROTL
489
29.8k
    0U, // G_ICMP
490
29.8k
    0U, // G_FCMP
491
29.8k
    0U, // G_SELECT
492
29.8k
    0U, // G_UADDO
493
29.8k
    0U, // G_UADDE
494
29.8k
    0U, // G_USUBO
495
29.8k
    0U, // G_USUBE
496
29.8k
    0U, // G_SADDO
497
29.8k
    0U, // G_SADDE
498
29.8k
    0U, // G_SSUBO
499
29.8k
    0U, // G_SSUBE
500
29.8k
    0U, // G_UMULO
501
29.8k
    0U, // G_SMULO
502
29.8k
    0U, // G_UMULH
503
29.8k
    0U, // G_SMULH
504
29.8k
    0U, // G_UADDSAT
505
29.8k
    0U, // G_SADDSAT
506
29.8k
    0U, // G_USUBSAT
507
29.8k
    0U, // G_SSUBSAT
508
29.8k
    0U, // G_USHLSAT
509
29.8k
    0U, // G_SSHLSAT
510
29.8k
    0U, // G_SMULFIX
511
29.8k
    0U, // G_UMULFIX
512
29.8k
    0U, // G_SMULFIXSAT
513
29.8k
    0U, // G_UMULFIXSAT
514
29.8k
    0U, // G_SDIVFIX
515
29.8k
    0U, // G_UDIVFIX
516
29.8k
    0U, // G_SDIVFIXSAT
517
29.8k
    0U, // G_UDIVFIXSAT
518
29.8k
    0U, // G_FADD
519
29.8k
    0U, // G_FSUB
520
29.8k
    0U, // G_FMUL
521
29.8k
    0U, // G_FMA
522
29.8k
    0U, // G_FMAD
523
29.8k
    0U, // G_FDIV
524
29.8k
    0U, // G_FREM
525
29.8k
    0U, // G_FPOW
526
29.8k
    0U, // G_FPOWI
527
29.8k
    0U, // G_FEXP
528
29.8k
    0U, // G_FEXP2
529
29.8k
    0U, // G_FEXP10
530
29.8k
    0U, // G_FLOG
531
29.8k
    0U, // G_FLOG2
532
29.8k
    0U, // G_FLOG10
533
29.8k
    0U, // G_FLDEXP
534
29.8k
    0U, // G_FFREXP
535
29.8k
    0U, // G_FNEG
536
29.8k
    0U, // G_FPEXT
537
29.8k
    0U, // G_FPTRUNC
538
29.8k
    0U, // G_FPTOSI
539
29.8k
    0U, // G_FPTOUI
540
29.8k
    0U, // G_SITOFP
541
29.8k
    0U, // G_UITOFP
542
29.8k
    0U, // G_FABS
543
29.8k
    0U, // G_FCOPYSIGN
544
29.8k
    0U, // G_IS_FPCLASS
545
29.8k
    0U, // G_FCANONICALIZE
546
29.8k
    0U, // G_FMINNUM
547
29.8k
    0U, // G_FMAXNUM
548
29.8k
    0U, // G_FMINNUM_IEEE
549
29.8k
    0U, // G_FMAXNUM_IEEE
550
29.8k
    0U, // G_FMINIMUM
551
29.8k
    0U, // G_FMAXIMUM
552
29.8k
    0U, // G_GET_FPENV
553
29.8k
    0U, // G_SET_FPENV
554
29.8k
    0U, // G_RESET_FPENV
555
29.8k
    0U, // G_GET_FPMODE
556
29.8k
    0U, // G_SET_FPMODE
557
29.8k
    0U, // G_RESET_FPMODE
558
29.8k
    0U, // G_PTR_ADD
559
29.8k
    0U, // G_PTRMASK
560
29.8k
    0U, // G_SMIN
561
29.8k
    0U, // G_SMAX
562
29.8k
    0U, // G_UMIN
563
29.8k
    0U, // G_UMAX
564
29.8k
    0U, // G_ABS
565
29.8k
    0U, // G_LROUND
566
29.8k
    0U, // G_LLROUND
567
29.8k
    0U, // G_BR
568
29.8k
    0U, // G_BRJT
569
29.8k
    0U, // G_INSERT_VECTOR_ELT
570
29.8k
    0U, // G_EXTRACT_VECTOR_ELT
571
29.8k
    0U, // G_SHUFFLE_VECTOR
572
29.8k
    0U, // G_CTTZ
573
29.8k
    0U, // G_CTTZ_ZERO_UNDEF
574
29.8k
    0U, // G_CTLZ
575
29.8k
    0U, // G_CTLZ_ZERO_UNDEF
576
29.8k
    0U, // G_CTPOP
577
29.8k
    0U, // G_BSWAP
578
29.8k
    0U, // G_BITREVERSE
579
29.8k
    0U, // G_FCEIL
580
29.8k
    0U, // G_FCOS
581
29.8k
    0U, // G_FSIN
582
29.8k
    0U, // G_FSQRT
583
29.8k
    0U, // G_FFLOOR
584
29.8k
    0U, // G_FRINT
585
29.8k
    0U, // G_FNEARBYINT
586
29.8k
    0U, // G_ADDRSPACE_CAST
587
29.8k
    0U, // G_BLOCK_ADDR
588
29.8k
    0U, // G_JUMP_TABLE
589
29.8k
    0U, // G_DYN_STACKALLOC
590
29.8k
    0U, // G_STACKSAVE
591
29.8k
    0U, // G_STACKRESTORE
592
29.8k
    0U, // G_STRICT_FADD
593
29.8k
    0U, // G_STRICT_FSUB
594
29.8k
    0U, // G_STRICT_FMUL
595
29.8k
    0U, // G_STRICT_FDIV
596
29.8k
    0U, // G_STRICT_FREM
597
29.8k
    0U, // G_STRICT_FMA
598
29.8k
    0U, // G_STRICT_FSQRT
599
29.8k
    0U, // G_STRICT_FLDEXP
600
29.8k
    0U, // G_READ_REGISTER
601
29.8k
    0U, // G_WRITE_REGISTER
602
29.8k
    0U, // G_MEMCPY
603
29.8k
    0U, // G_MEMCPY_INLINE
604
29.8k
    0U, // G_MEMMOVE
605
29.8k
    0U, // G_MEMSET
606
29.8k
    0U, // G_BZERO
607
29.8k
    0U, // G_VECREDUCE_SEQ_FADD
608
29.8k
    0U, // G_VECREDUCE_SEQ_FMUL
609
29.8k
    0U, // G_VECREDUCE_FADD
610
29.8k
    0U, // G_VECREDUCE_FMUL
611
29.8k
    0U, // G_VECREDUCE_FMAX
612
29.8k
    0U, // G_VECREDUCE_FMIN
613
29.8k
    0U, // G_VECREDUCE_FMAXIMUM
614
29.8k
    0U, // G_VECREDUCE_FMINIMUM
615
29.8k
    0U, // G_VECREDUCE_ADD
616
29.8k
    0U, // G_VECREDUCE_MUL
617
29.8k
    0U, // G_VECREDUCE_AND
618
29.8k
    0U, // G_VECREDUCE_OR
619
29.8k
    0U, // G_VECREDUCE_XOR
620
29.8k
    0U, // G_VECREDUCE_SMAX
621
29.8k
    0U, // G_VECREDUCE_SMIN
622
29.8k
    0U, // G_VECREDUCE_UMAX
623
29.8k
    0U, // G_VECREDUCE_UMIN
624
29.8k
    0U, // G_SBFX
625
29.8k
    0U, // G_UBFX
626
29.8k
    4609U,  // ADJCALLSTACKDOWN
627
29.8k
    70164U, // ADJCALLSTACKUP
628
29.8k
    8206U,  // GETPCX
629
29.8k
    1946U,  // SELECT_CC_DFP_FCC
630
29.8k
    2057U,  // SELECT_CC_DFP_ICC
631
29.8k
    2168U,  // SELECT_CC_DFP_XCC
632
29.8k
    2002U,  // SELECT_CC_FP_FCC
633
29.8k
    2113U,  // SELECT_CC_FP_ICC
634
29.8k
    2224U,  // SELECT_CC_FP_XCC
635
29.8k
    2029U,  // SELECT_CC_Int_FCC
636
29.8k
    2140U,  // SELECT_CC_Int_ICC
637
29.8k
    2251U,  // SELECT_CC_Int_XCC
638
29.8k
    1974U,  // SELECT_CC_QFP_FCC
639
29.8k
    2085U,  // SELECT_CC_QFP_ICC
640
29.8k
    2196U,  // SELECT_CC_QFP_XCC
641
29.8k
    2111195U, // SET
642
29.8k
    20985729U,  // SETX
643
29.8k
    20984449U,  // ADDCCri
644
29.8k
    20984449U,  // ADDCCrr
645
29.8k
    20985664U,  // ADDCri
646
29.8k
    20985664U,  // ADDCrr
647
29.8k
    20984541U,  // ADDEri
648
29.8k
    20984541U,  // ADDErr
649
29.8k
    20984555U,  // ADDXC
650
29.8k
    20984439U,  // ADDXCCC
651
29.8k
    20984577U,  // ADDri
652
29.8k
    20984577U,  // ADDrr
653
29.8k
    20985176U,  // ALIGNADDR
654
29.8k
    20984933U,  // ALIGNADDRL
655
29.8k
    20984456U,  // ANDCCri
656
29.8k
    20984456U,  // ANDCCrr
657
29.8k
    20984479U,  // ANDNCCri
658
29.8k
    20984479U,  // ANDNCCrr
659
29.8k
    20984988U,  // ANDNri
660
29.8k
    20984988U,  // ANDNrr
661
29.8k
    20984662U,  // ANDri
662
29.8k
    20984662U,  // ANDrr
663
29.8k
    20984289U,  // ARRAY16
664
29.8k
    20984042U,  // ARRAY32
665
29.8k
    20984313U,  // ARRAY8
666
29.8k
    2247425U, // BCOND
667
29.8k
    2312961U, // BCONDA
668
29.8k
    87258U, // BINDri
669
29.8k
    87258U, // BINDrr
670
29.8k
    20984871U,  // BMASK
671
29.8k
    21121795U,  // BPFCC
672
29.8k
    21187331U,  // BPFCCA
673
29.8k
    281347U,  // BPFCCANT
674
29.8k
    346883U,  // BPFCCNT
675
29.8k
    2509569U, // BPICC
676
29.8k
    477953U,  // BPICCA
677
29.8k
    543489U,  // BPICCANT
678
29.8k
    609025U,  // BPICCNT
679
29.8k
    21121882U,  // BPR
680
29.8k
    21187418U,  // BPRA
681
29.8k
    281434U,  // BPRANT
682
29.8k
    346970U,  // BPRNT
683
29.8k
    2771713U, // BPXCC
684
29.8k
    740097U,  // BPXCCA
685
29.8k
    805633U,  // BPXCCANT
686
29.8k
    871169U,  // BPXCCNT
687
29.8k
    20984782U,  // BSHUFFLE
688
29.8k
    70740U, // CALL
689
29.8k
    87124U, // CALLri
690
29.8k
    87124U, // CALLrr
691
29.8k
    21904013U,  // CASAri
692
29.8k
    7289485U, // CASArr
693
29.8k
    21904035U,  // CASXAri
694
29.8k
    7289507U, // CASXArr
695
29.8k
    2247424U, // CBCOND
696
29.8k
    2312960U, // CBCONDA
697
29.8k
    69980U, // CMASK16
698
29.8k
    69812U, // CMASK32
699
29.8k
    70129U, // CMASK8
700
29.8k
    2850U,  // DONE
701
29.8k
    20984119U,  // EDGE16
702
29.8k
    20984887U,  // EDGE16L
703
29.8k
    20985004U,  // EDGE16LN
704
29.8k
    20984971U,  // EDGE16N
705
29.8k
    20983951U,  // EDGE32
706
29.8k
    20984878U,  // EDGE32L
707
29.8k
    20984994U,  // EDGE32LN
708
29.8k
    20984962U,  // EDGE32N
709
29.8k
    20984298U,  // EDGE8
710
29.8k
    20984896U,  // EDGE8L
711
29.8k
    20985014U,  // EDGE8LN
712
29.8k
    20984980U,  // EDGE8N
713
29.8k
    2110371U, // FABSD
714
29.8k
    2110766U, // FABSQ
715
29.8k
    2111166U, // FABSS
716
29.8k
    20984582U,  // FADDD
717
29.8k
    20985062U,  // FADDQ
718
29.8k
    20985362U,  // FADDS
719
29.8k
    20984386U,  // FALIGNADATA
720
29.8k
    20984661U,  // FAND
721
29.8k
    20983899U,  // FANDNOT1
722
29.8k
    20985241U,  // FANDNOT1S
723
29.8k
    20984058U,  // FANDNOT2
724
29.8k
    20985298U,  // FANDNOT2S
725
29.8k
    20985394U,  // FANDS
726
29.8k
    2247427U, // FBCOND
727
29.8k
    2312963U, // FBCONDA
728
29.8k
    1067779U, // FBCONDA_V9
729
29.8k
    3230467U, // FBCOND_V9
730
29.8k
    20984181U,  // FCHKSM16
731
29.8k
    5008U,  // FCMPD
732
29.8k
    4097U,  // FCMPD_V9
733
29.8k
    20984200U,  // FCMPEQ16
734
29.8k
    20984013U,  // FCMPEQ32
735
29.8k
    20984219U,  // FCMPGT16
736
29.8k
    20984032U,  // FCMPGT32
737
29.8k
    20984127U,  // FCMPLE16
738
29.8k
    20983959U,  // FCMPLE32
739
29.8k
    20984137U,  // FCMPNE16
740
29.8k
    20983969U,  // FCMPNE32
741
29.8k
    5415U,  // FCMPQ
742
29.8k
    4111U,  // FCMPQ_V9
743
29.8k
    5779U,  // FCMPS
744
29.8k
    4125U,  // FCMPS_V9
745
29.8k
    20984759U,  // FDIVD
746
29.8k
    20985154U,  // FDIVQ
747
29.8k
    20985549U,  // FDIVS
748
29.8k
    20985084U,  // FDMULQ
749
29.8k
    2110482U, // FDTOI
750
29.8k
    2110731U, // FDTOQ
751
29.8k
    2111086U, // FDTOS
752
29.8k
    2111331U, // FDTOX
753
29.8k
    2110306U, // FEXPAND
754
29.8k
    20984589U,  // FHADDD
755
29.8k
    20985369U,  // FHADDS
756
29.8k
    20984569U,  // FHSUBD
757
29.8k
    20985354U,  // FHSUBS
758
29.8k
    2110315U, // FITOD
759
29.8k
    2110738U, // FITOQ
760
29.8k
    2111093U, // FITOS
761
29.8k
    150999959U, // FLCMPD
762
29.8k
    151000730U, // FLCMPS
763
29.8k
    2445U,  // FLUSH
764
29.8k
    2933U,  // FLUSHW
765
29.8k
    87021U, // FLUSHri
766
29.8k
    87021U, // FLUSHrr
767
29.8k
    20984191U,  // FMEAN16
768
29.8k
    2110398U, // FMOVD
769
29.8k
    17918748U,  // FMOVD_FCC
770
29.8k
    17197852U,  // FMOVD_ICC
771
29.8k
    17459996U,  // FMOVD_XCC
772
29.8k
    2110793U, // FMOVQ
773
29.8k
    17918798U,  // FMOVQ_FCC
774
29.8k
    17197902U,  // FMOVQ_ICC
775
29.8k
    17460046U,  // FMOVQ_XCC
776
29.8k
    31509U, // FMOVRD
777
29.8k
    31559U, // FMOVRQ
778
29.8k
    31586U, // FMOVRS
779
29.8k
    2111188U, // FMOVS
780
29.8k
    17918825U,  // FMOVS_FCC
781
29.8k
    17197929U,  // FMOVS_ICC
782
29.8k
    17460073U,  // FMOVS_XCC
783
29.8k
    20984277U,  // FMUL8SUX16
784
29.8k
    20984252U,  // FMUL8ULX16
785
29.8k
    20984229U,  // FMUL8X16
786
29.8k
    20984904U,  // FMUL8X16AL
787
29.8k
    20985588U,  // FMUL8X16AU
788
29.8k
    20984629U,  // FMULD
789
29.8k
    20984264U,  // FMULD8SUX16
790
29.8k
    20984239U,  // FMULD8ULX16
791
29.8k
    20985092U,  // FMULQ
792
29.8k
    20985431U,  // FMULS
793
29.8k
    20984606U,  // FNADDD
794
29.8k
    20985386U,  // FNADDS
795
29.8k
    20984667U,  // FNAND
796
29.8k
    20985401U,  // FNANDS
797
29.8k
    2110254U, // FNEGD
798
29.8k
    2110709U, // FNEGQ
799
29.8k
    2111056U, // FNEGS
800
29.8k
    20984597U,  // FNHADDD
801
29.8k
    20985377U,  // FNHADDS
802
29.8k
    20984636U,  // FNMULD
803
29.8k
    20985438U,  // FNMULS
804
29.8k
    20985197U,  // FNOR
805
29.8k
    20985512U,  // FNORS
806
29.8k
    2109541U, // FNOT1
807
29.8k
    2110884U, // FNOT1S
808
29.8k
    2109700U, // FNOT2
809
29.8k
    2110941U, // FNOT2S
810
29.8k
    20984652U,  // FNSMULD
811
29.8k
    70616U, // FONE
812
29.8k
    71233U, // FONES
813
29.8k
    20985192U,  // FOR
814
29.8k
    20983916U,  // FORNOT1
815
29.8k
    20985260U,  // FORNOT1S
816
29.8k
    20984075U,  // FORNOT2
817
29.8k
    20985317U,  // FORNOT2S
818
29.8k
    20985506U,  // FORS
819
29.8k
    2109779U, // FPACK16
820
29.8k
    20983979U,  // FPACK32
821
29.8k
    2111302U, // FPACKFIX
822
29.8k
    20984110U,  // FPADD16
823
29.8k
    20985337U,  // FPADD16S
824
29.8k
    20983942U,  // FPADD32
825
29.8k
    20985280U,  // FPADD32S
826
29.8k
    20984084U,  // FPADD64
827
29.8k
    20984773U,  // FPMERGE
828
29.8k
    20984101U,  // FPSUB16
829
29.8k
    20985327U,  // FPSUB16S
830
29.8k
    20983933U,  // FPSUB32
831
29.8k
    20985270U,  // FPSUB32S
832
29.8k
    2110322U, // FQTOD
833
29.8k
    2110489U, // FQTOI
834
29.8k
    2111100U, // FQTOS
835
29.8k
    2111347U, // FQTOX
836
29.8k
    20984210U,  // FSLAS16
837
29.8k
    20984023U,  // FSLAS32
838
29.8k
    20984165U,  // FSLL16
839
29.8k
    20983997U,  // FSLL32
840
29.8k
    20984644U,  // FSMULD
841
29.8k
    2110378U, // FSQRTD
842
29.8k
    2110773U, // FSQRTQ
843
29.8k
    2111173U, // FSQRTS
844
29.8k
    20984093U,  // FSRA16
845
29.8k
    20983925U,  // FSRA32
846
29.8k
    2109524U, // FSRC1
847
29.8k
    2110865U, // FSRC1S
848
29.8k
    2109683U, // FSRC2
849
29.8k
    2110922U, // FSRC2S
850
29.8k
    20984173U,  // FSRL16
851
29.8k
    20984005U,  // FSRL32
852
29.8k
    2110329U, // FSTOD
853
29.8k
    2110496U, // FSTOI
854
29.8k
    2110745U, // FSTOQ
855
29.8k
    2111354U, // FSTOX
856
29.8k
    20984562U,  // FSUBD
857
29.8k
    20985055U,  // FSUBQ
858
29.8k
    20985347U,  // FSUBS
859
29.8k
    20985203U,  // FXNOR
860
29.8k
    20985519U,  // FXNORS
861
29.8k
    20985210U,  // FXOR
862
29.8k
    20985527U,  // FXORS
863
29.8k
    2110336U, // FXTOD
864
29.8k
    2110752U, // FXTOQ
865
29.8k
    2111116U, // FXTOS
866
29.8k
    70860U, // FZERO
867
29.8k
    71270U, // FZEROS
868
29.8k
    288525050U, // GDOP_LDXrr
869
29.8k
    288525000U, // GDOP_LDrr
870
29.8k
    2131039U, // JMPLri
871
29.8k
    2131039U, // JMPLrr
872
29.8k
    3050088U, // LDAri
873
29.8k
    26184296U,  // LDArr
874
29.8k
    1268424U, // LDCSRri
875
29.8k
    1268424U, // LDCSRrr
876
29.8k
    3312328U, // LDCri
877
29.8k
    3312328U, // LDCrr
878
29.8k
    3050081U, // LDDAri
879
29.8k
    26184289U,  // LDDArr
880
29.8k
    3312322U, // LDDCri
881
29.8k
    3312322U, // LDDCrr
882
29.8k
    3050081U, // LDDFAri
883
29.8k
    26184289U,  // LDDFArr
884
29.8k
    3312322U, // LDDFri
885
29.8k
    3312322U, // LDDFrr
886
29.8k
    3312322U, // LDDri
887
29.8k
    3312322U, // LDDrr
888
29.8k
    3050088U, // LDFAri
889
29.8k
    26184296U,  // LDFArr
890
29.8k
    1333960U, // LDFSRri
891
29.8k
    1333960U, // LDFSRrr
892
29.8k
    3312328U, // LDFri
893
29.8k
    3312328U, // LDFrr
894
29.8k
    3050118U, // LDQFAri
895
29.8k
    26184326U,  // LDQFArr
896
29.8k
    3312365U, // LDQFri
897
29.8k
    3312365U, // LDQFrr
898
29.8k
    3050055U, // LDSBAri
899
29.8k
    26184263U,  // LDSBArr
900
29.8k
    3312299U, // LDSBri
901
29.8k
    3312299U, // LDSBrr
902
29.8k
    3050094U, // LDSHAri
903
29.8k
    26184302U,  // LDSHArr
904
29.8k
    3312344U, // LDSHri
905
29.8k
    3312344U, // LDSHrr
906
29.8k
    3050071U, // LDSTUBAri
907
29.8k
    26184279U,  // LDSTUBArr
908
29.8k
    3312313U, // LDSTUBri
909
29.8k
    3312313U, // LDSTUBrr
910
29.8k
    3050132U, // LDSWAri
911
29.8k
    26184340U,  // LDSWArr
912
29.8k
    3312371U, // LDSWri
913
29.8k
    3312371U, // LDSWrr
914
29.8k
    3050063U, // LDUBAri
915
29.8k
    26184271U,  // LDUBArr
916
29.8k
    3312306U, // LDUBri
917
29.8k
    3312306U, // LDUBrr
918
29.8k
    3050102U, // LDUHAri
919
29.8k
    26184310U,  // LDUHArr
920
29.8k
    3312351U, // LDUHri
921
29.8k
    3312351U, // LDUHrr
922
29.8k
    3050140U, // LDXAri
923
29.8k
    26184348U,  // LDXArr
924
29.8k
    1334010U, // LDXFSRri
925
29.8k
    1334010U, // LDXFSRrr
926
29.8k
    3312378U, // LDXri
927
29.8k
    3312378U, // LDXrr
928
29.8k
    3312328U, // LDri
929
29.8k
    3312328U, // LDrr
930
29.8k
    2111200U, // LZCNT
931
29.8k
    38224U, // MEMBARi
932
29.8k
    2111338U, // MOVDTOX
933
29.8k
    17918833U,  // MOVFCCri
934
29.8k
    17918833U,  // MOVFCCrr
935
29.8k
    17197937U,  // MOVICCri
936
29.8k
    17197937U,  // MOVICCrr
937
29.8k
    31581U, // MOVRri
938
29.8k
    31581U, // MOVRrr
939
29.8k
    2111264U, // MOVSTOSW
940
29.8k
    2111274U, // MOVSTOUW
941
29.8k
    2111107U, // MOVWTOS
942
29.8k
    17460081U,  // MOVXCCri
943
29.8k
    17460081U,  // MOVXCCrr
944
29.8k
    2110343U, // MOVXTOD
945
29.8k
    20984509U,  // MULSCCri
946
29.8k
    20984509U,  // MULSCCrr
947
29.8k
    20985693U,  // MULXri
948
29.8k
    20985693U,  // MULXrr
949
29.8k
    2883U,  // NOP
950
29.8k
    20984496U,  // ORCCri
951
29.8k
    20984496U,  // ORCCrr
952
29.8k
    20984487U,  // ORNCCri
953
29.8k
    20984487U,  // ORNCCrr
954
29.8k
    20985023U,  // ORNri
955
29.8k
    20985023U,  // ORNrr
956
29.8k
    20985193U,  // ORri
957
29.8k
    20985193U,  // ORrr
958
29.8k
    20985575U,  // PDIST
959
29.8k
    20985028U,  // PDISTN
960
29.8k
    2110181U, // POPCrr
961
29.8k
    5397197U, // PREFETCHi
962
29.8k
    5397197U, // PREFETCHr
963
29.8k
    33559948U,  // PWRPSRri
964
29.8k
    33559948U,  // PWRPSRrr
965
29.8k
    2110367U, // RDASR
966
29.8k
    69685U, // RDFQ
967
29.8k
    2110848U, // RDPR
968
29.8k
    69706U, // RDPSR
969
29.8k
    69696U, // RDTBR
970
29.8k
    69675U, // RDWIM
971
29.8k
    2822U,  // RESTORED
972
29.8k
    20984798U,  // RESTOREri
973
29.8k
    20984798U,  // RESTORErr
974
29.8k
    71911U, // RET
975
29.8k
    71920U, // RETL
976
29.8k
    2940U,  // RETRY
977
29.8k
    87790U, // RETTri
978
29.8k
    87790U, // RETTrr
979
29.8k
    2831U,  // SAVED
980
29.8k
    20984807U,  // SAVEri
981
29.8k
    20984807U,  // SAVErr
982
29.8k
    20984517U,  // SDIVCCri
983
29.8k
    20984517U,  // SDIVCCrr
984
29.8k
    20985740U,  // SDIVXri
985
29.8k
    20985740U,  // SDIVXrr
986
29.8k
    20985600U,  // SDIVri
987
29.8k
    20985600U,  // SDIVrr
988
29.8k
    2110457U, // SETHIi
989
29.8k
    2874U,  // SHUTDOWN
990
29.8k
    2869U,  // SIAM
991
29.8k
    71011U, // SIR
992
29.8k
    20985680U,  // SLLXri
993
29.8k
    20985680U,  // SLLXrr
994
29.8k
    20984922U,  // SLLri
995
29.8k
    20984922U,  // SLLrr
996
29.8k
    20984419U,  // SMACri
997
29.8k
    20984419U,  // SMACrr
998
29.8k
    20984463U,  // SMULCCri
999
29.8k
    20984463U,  // SMULCCrr
1000
29.8k
    20984950U,  // SMULri
1001
29.8k
    20984950U,  // SMULrr
1002
29.8k
    20985652U,  // SRAXri
1003
29.8k
    20985652U,  // SRAXrr
1004
29.8k
    20984381U,  // SRAri
1005
29.8k
    20984381U,  // SRArr
1006
29.8k
    20985686U,  // SRLXri
1007
29.8k
    20985686U,  // SRLXrr
1008
29.8k
    20984945U,  // SRLri
1009
29.8k
    20984945U,  // SRLrr
1010
29.8k
    1417806U, // STAri
1011
29.8k
    9413198U, // STArr
1012
29.8k
    2900U,  // STBAR
1013
29.8k
    1417765U, // STBAri
1014
29.8k
    9413157U, // STBArr
1015
29.8k
    1483353U, // STBri
1016
29.8k
    1483353U, // STBrr
1017
29.8k
    1464869U, // STCSRri
1018
29.8k
    1464869U, // STCSRrr
1019
29.8k
    1484522U, // STCri
1020
29.8k
    1484522U, // STCrr
1021
29.8k
    1417771U, // STDAri
1022
29.8k
    9413163U, // STDArr
1023
29.8k
    1464847U, // STDCQri
1024
29.8k
    1464847U, // STDCQrr
1025
29.8k
    1483698U, // STDCri
1026
29.8k
    1483698U, // STDCrr
1027
29.8k
    1417771U, // STDFAri
1028
29.8k
    9413163U, // STDFArr
1029
29.8k
    1464858U, // STDFQri
1030
29.8k
    1464858U, // STDFQrr
1031
29.8k
    1483698U, // STDFri
1032
29.8k
    1483698U, // STDFrr
1033
29.8k
    1483698U, // STDri
1034
29.8k
    1483698U, // STDrr
1035
29.8k
    1417806U, // STFAri
1036
29.8k
    9413198U, // STFArr
1037
29.8k
    1464880U, // STFSRri
1038
29.8k
    1464880U, // STFSRrr
1039
29.8k
    1484522U, // STFri
1040
29.8k
    1484522U, // STFrr
1041
29.8k
    1417777U, // STHAri
1042
29.8k
    9413169U, // STHArr
1043
29.8k
    1483764U, // STHri
1044
29.8k
    1483764U, // STHrr
1045
29.8k
    1417783U, // STQFAri
1046
29.8k
    9413175U, // STQFArr
1047
29.8k
    1484093U, // STQFri
1048
29.8k
    1484093U, // STQFrr
1049
29.8k
    1417811U, // STXAri
1050
29.8k
    9413203U, // STXArr
1051
29.8k
    1464891U, // STXFSRri
1052
29.8k
    1464891U, // STXFSRrr
1053
29.8k
    1484679U, // STXri
1054
29.8k
    1484679U, // STXrr
1055
29.8k
    1484522U, // STri
1056
29.8k
    1484522U, // STrr
1057
29.8k
    20984432U,  // SUBCCri
1058
29.8k
    20984432U,  // SUBCCrr
1059
29.8k
    20985658U,  // SUBCri
1060
29.8k
    20985658U,  // SUBCrr
1061
29.8k
    20984533U,  // SUBEri
1062
29.8k
    20984533U,  // SUBErr
1063
29.8k
    20984414U,  // SUBri
1064
29.8k
    20984414U,  // SUBrr
1065
29.8k
    3050110U, // SWAPAri
1066
29.8k
    26184318U,  // SWAPArr
1067
29.8k
    3312358U, // SWAPri
1068
29.8k
    3312358U, // SWAPrr
1069
29.8k
    2455U,  // TA1
1070
29.8k
    2460U,  // TA3
1071
29.8k
    2465U,  // TA5
1072
29.8k
    20985622U,  // TADDCCTVri
1073
29.8k
    20985622U,  // TADDCCTVrr
1074
29.8k
    20984448U,  // TADDCCri
1075
29.8k
    20984448U,  // TADDCCrr
1076
29.8k
    70740U, // TAIL_CALL
1077
29.8k
    87258U, // TAIL_CALLri
1078
29.8k
    52869999U,  // TICCri
1079
29.8k
    52869999U,  // TICCrr
1080
29.8k
    557855489U, // TLS_ADDrr
1081
29.8k
    5204U,  // TLS_CALL
1082
29.8k
    288525050U, // TLS_LDXrr
1083
29.8k
    288525000U, // TLS_LDrr
1084
29.8k
    52607855U,  // TRAPri
1085
29.8k
    52607855U,  // TRAPrr
1086
29.8k
    20985612U,  // TSUBCCTVri
1087
29.8k
    20985612U,  // TSUBCCTVrr
1088
29.8k
    20984431U,  // TSUBCCri
1089
29.8k
    20984431U,  // TSUBCCrr
1090
29.8k
    53132143U,  // TXCCri
1091
29.8k
    53132143U,  // TXCCrr
1092
29.8k
    20984525U,  // UDIVCCri
1093
29.8k
    20984525U,  // UDIVCCrr
1094
29.8k
    20985747U,  // UDIVXri
1095
29.8k
    20985747U,  // UDIVXrr
1096
29.8k
    20985606U,  // UDIVri
1097
29.8k
    20985606U,  // UDIVrr
1098
29.8k
    20984425U,  // UMACri
1099
29.8k
    20984425U,  // UMACrr
1100
29.8k
    20984471U,  // UMULCCri
1101
29.8k
    20984471U,  // UMULCCrr
1102
29.8k
    20984832U,  // UMULXHI
1103
29.8k
    20984956U,  // UMULri
1104
29.8k
    20984956U,  // UMULrr
1105
29.8k
    70867U, // UNIMP
1106
29.8k
    150999952U, // V9FCMPD
1107
29.8k
    150999846U, // V9FCMPED
1108
29.8k
    151000301U, // V9FCMPEQ
1109
29.8k
    151000648U, // V9FCMPES
1110
29.8k
    151000359U, // V9FCMPQ
1111
29.8k
    151000723U, // V9FCMPS
1112
29.8k
    31516U, // V9FMOVD_FCC
1113
29.8k
    31566U, // V9FMOVQ_FCC
1114
29.8k
    31593U, // V9FMOVS_FCC
1115
29.8k
    31601U, // V9MOVFCCri
1116
29.8k
    31601U, // V9MOVFCCrr
1117
29.8k
    20985229U,  // WRASRri
1118
29.8k
    20985229U,  // WRASRrr
1119
29.8k
    20985222U,  // WRPRri
1120
29.8k
    20985222U,  // WRPRrr
1121
29.8k
    33559949U,  // WRPSRri
1122
29.8k
    33559949U,  // WRPSRrr
1123
29.8k
    67114381U,  // WRTBRri
1124
29.8k
    67114381U,  // WRTBRrr
1125
29.8k
    83891597U,  // WRWIMri
1126
29.8k
    83891597U,  // WRWIMrr
1127
29.8k
    20985692U,  // XMULX
1128
29.8k
    20984841U,  // XMULXHI
1129
29.8k
    20984494U,  // XNORCCri
1130
29.8k
    20984494U,  // XNORCCrr
1131
29.8k
    20985204U,  // XNORri
1132
29.8k
    20985204U,  // XNORrr
1133
29.8k
    20984502U,  // XORCCri
1134
29.8k
    20984502U,  // XORCCrr
1135
29.8k
    20985211U,  // XORri
1136
29.8k
    20985211U,  // XORrr
1137
29.8k
  };
1138
1139
  // Emit the opcode for the instruction.
1140
29.8k
  uint32_t Bits = 0;
1141
29.8k
  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
1142
29.8k
  MnemonicBitsInfo MBI = {
1143
29.8k
#ifndef CAPSTONE_DIET
1144
29.8k
    AsmStrs+(Bits & 4095)-1,
1145
#else
1146
    NULL,
1147
#endif // CAPSTONE_DIET
1148
29.8k
    Bits
1149
29.8k
  };
1150
29.8k
  return MBI;
1151
29.8k
}
1152
1153
/// printInstruction - This method is automatically generated by tablegen
1154
/// from the instruction set description.
1155
29.8k
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
1156
29.8k
  SStream_concat0(O, "");
1157
29.8k
  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
1158
1159
29.8k
  SStream_concat0(O, MnemonicInfo.first);
1160
1161
29.8k
  uint32_t Bits = MnemonicInfo.second;
1162
29.8k
  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
1163
1164
  // Fragment 0 encoded into 4 bits for 12 unique commands.
1165
29.8k
  switch ((Bits >> 12) & 15) {
1166
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1167
26
  case 0:
1168
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1169
26
    return;
1170
0
    break;
1171
7.10k
  case 1:
1172
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CALL, CMASK16, CMASK32, CMASK8, FCMP...
1173
7.10k
    printOperand(MI, 0, O);
1174
7.10k
    break;
1175
0
  case 2:
1176
    // GETPCX
1177
0
    printGetPCX(MI, 0, O);
1178
0
    return;
1179
0
    break;
1180
6.53k
  case 3:
1181
    // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD...
1182
6.53k
    printOperand(MI, 1, O);
1183
6.53k
    break;
1184
4.88k
  case 4:
1185
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1186
4.88k
    printCCOperand(MI, 1, O);
1187
4.88k
    break;
1188
370
  case 5:
1189
    // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD...
1190
370
    printMemOperand(MI, 0, O);
1191
370
    break;
1192
585
  case 6:
1193
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1194
585
    printCCOperand(MI, 3, O);
1195
585
    break;
1196
253
  case 7:
1197
    // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1198
253
    printCCOperand(MI, 4, O);
1199
253
    SStream_concat1(O, ' ');
1200
253
    printOperand(MI, 1, O);
1201
253
    SStream_concat0(O, ", ");
1202
253
    printOperand(MI, 2, O);
1203
253
    SStream_concat0(O, ", ");
1204
253
    printOperand(MI, 0, O);
1205
253
    return;
1206
0
    break;
1207
6.00k
  case 8:
1208
    // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1209
6.00k
    printMemOperand(MI, 1, O);
1210
6.00k
    break;
1211
319
  case 9:
1212
    // MEMBARi
1213
319
    printMembarTag(MI, 0, O);
1214
319
    return;
1215
0
    break;
1216
3.75k
  case 10:
1217
    // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1218
3.75k
    printOperand(MI, 2, O);
1219
3.75k
    SStream_concat0(O, ", [");
1220
3.75k
    printMemOperand(MI, 0, O);
1221
3.75k
    break;
1222
0
  case 11:
1223
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1224
0
    printCCOperand(MI, 2, O);
1225
0
    break;
1226
29.8k
  }
1227
1228
1229
  // Fragment 1 encoded into 5 bits for 23 unique commands.
1230
29.2k
  switch ((Bits >> 16) & 31) {
1231
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1232
7.89k
  case 0:
1233
    // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
1234
7.89k
    SStream_concat0(O, ", ");
1235
7.89k
    break;
1236
5.64k
  case 1:
1237
    // ADJCALLSTACKUP, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMASK32...
1238
5.64k
    return;
1239
0
    break;
1240
1.55k
  case 2:
1241
    // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr
1242
1.55k
    SStream_concat1(O, ' ');
1243
1.55k
    break;
1244
1.45k
  case 3:
1245
    // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA
1246
1.45k
    SStream_concat0(O, ",a ");
1247
1.45k
    break;
1248
84
  case 4:
1249
    // BPFCCANT, BPRANT
1250
84
    SStream_concat0(O, ",a,pn ");
1251
84
    printOperand(MI, 2, O);
1252
84
    SStream_concat0(O, ", ");
1253
84
    printOperand(MI, 0, O);
1254
84
    return;
1255
0
    break;
1256
301
  case 5:
1257
    // BPFCCNT, BPRNT
1258
301
    SStream_concat0(O, ",pn ");
1259
301
    printOperand(MI, 2, O);
1260
301
    SStream_concat0(O, ", ");
1261
301
    printOperand(MI, 0, O);
1262
301
    return;
1263
0
    break;
1264
321
  case 6:
1265
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1266
321
    SStream_concat0(O, " %icc, ");
1267
321
    break;
1268
138
  case 7:
1269
    // BPICCA
1270
138
    SStream_concat0(O, ",a %icc, ");
1271
138
    printOperand(MI, 0, O);
1272
138
    return;
1273
0
    break;
1274
0
  case 8:
1275
    // BPICCANT
1276
0
    SStream_concat0(O, ",a,pn %icc, ");
1277
0
    printOperand(MI, 0, O);
1278
0
    return;
1279
0
    break;
1280
0
  case 9:
1281
    // BPICCNT
1282
0
    SStream_concat0(O, ",pn %icc, ");
1283
0
    printOperand(MI, 0, O);
1284
0
    return;
1285
0
    break;
1286
261
  case 10:
1287
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1288
261
    SStream_concat0(O, " %xcc, ");
1289
261
    break;
1290
336
  case 11:
1291
    // BPXCCA
1292
336
    SStream_concat0(O, ",a %xcc, ");
1293
336
    printOperand(MI, 0, O);
1294
336
    return;
1295
0
    break;
1296
0
  case 12:
1297
    // BPXCCANT
1298
0
    SStream_concat0(O, ",a,pn %xcc, ");
1299
0
    printOperand(MI, 0, O);
1300
0
    return;
1301
0
    break;
1302
0
  case 13:
1303
    // BPXCCNT
1304
0
    SStream_concat0(O, ",pn %xcc, ");
1305
0
    printOperand(MI, 0, O);
1306
0
    return;
1307
0
    break;
1308
2.50k
  case 14:
1309
    // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1310
2.50k
    SStream_concat0(O, "] %asi, ");
1311
2.50k
    break;
1312
3.28k
  case 15:
1313
    // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1314
3.28k
    SStream_concat0(O, "] ");
1315
3.28k
    break;
1316
363
  case 16:
1317
    // FBCONDA_V9
1318
363
    SStream_concat0(O, ",a %fcc0, ");
1319
363
    printOperand(MI, 0, O);
1320
363
    return;
1321
0
    break;
1322
662
  case 17:
1323
    // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1324
662
    SStream_concat0(O, " %fcc0, ");
1325
662
    break;
1326
1.54k
  case 18:
1327
    // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1328
1.54k
    SStream_concat0(O, "], ");
1329
1.54k
    break;
1330
20
  case 19:
1331
    // LDCSRri, LDCSRrr
1332
20
    SStream_concat0(O, "], %csr");
1333
20
    return;
1334
0
    break;
1335
81
  case 20:
1336
    // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1337
81
    SStream_concat0(O, "], %fsr");
1338
81
    return;
1339
0
    break;
1340
1.18k
  case 21:
1341
    // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1342
1.18k
    SStream_concat0(O, "] %asi");
1343
1.18k
    return;
1344
0
    break;
1345
1.59k
  case 22:
1346
    // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1347
1.59k
    SStream_concat1(O, ']');
1348
1.59k
    return;
1349
0
    break;
1350
29.2k
  }
1351
1352
1353
  // Fragment 2 encoded into 3 bits for 5 unique commands.
1354
19.4k
  switch ((Bits >> 21) & 7) {
1355
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1356
2.07k
  case 0:
1357
    // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F...
1358
2.07k
    printOperand(MI, 1, O);
1359
2.07k
    break;
1360
10.1k
  case 1:
1361
    // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS...
1362
10.1k
    printOperand(MI, 0, O);
1363
10.1k
    break;
1364
3.95k
  case 2:
1365
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1366
3.95k
    printOperand(MI, 2, O);
1367
3.95k
    break;
1368
265
  case 3:
1369
    // CASArr, CASXArr
1370
265
    printASITag(MI, 4, O);
1371
265
    SStream_concat0(O, ", ");
1372
265
    printOperand(MI, 2, O);
1373
265
    SStream_concat0(O, ", ");
1374
265
    printOperand(MI, 0, O);
1375
265
    return;
1376
0
    break;
1377
3.02k
  case 4:
1378
    // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1379
3.02k
    printASITag(MI, 3, O);
1380
3.02k
    break;
1381
19.4k
  }
1382
1383
1384
  // Fragment 3 encoded into 3 bits for 6 unique commands.
1385
19.2k
  switch ((Bits >> 24) & 7) {
1386
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1387
11.3k
  case 0:
1388
    // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, F...
1389
11.3k
    return;
1390
0
    break;
1391
7.05k
  case 1:
1392
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1393
7.05k
    SStream_concat0(O, ", ");
1394
7.05k
    break;
1395
322
  case 2:
1396
    // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1397
322
    SStream_concat0(O, ", %psr");
1398
322
    return;
1399
0
    break;
1400
0
  case 3:
1401
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1402
0
    SStream_concat0(O, " + ");
1403
0
    printOperand(MI, 1, O);
1404
0
    return;
1405
0
    break;
1406
328
  case 4:
1407
    // WRTBRri, WRTBRrr
1408
328
    SStream_concat0(O, ", %tbr");
1409
328
    return;
1410
0
    break;
1411
127
  case 5:
1412
    // WRWIMri, WRWIMrr
1413
127
    SStream_concat0(O, ", %wim");
1414
127
    return;
1415
0
    break;
1416
19.2k
  }
1417
1418
1419
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1420
7.05k
  switch ((Bits >> 27) & 3) {
1421
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
1422
6.34k
  case 0:
1423
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1424
6.34k
    printOperand(MI, 0, O);
1425
6.34k
    break;
1426
711
  case 1:
1427
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1428
711
    printOperand(MI, 2, O);
1429
711
    return;
1430
0
    break;
1431
0
  case 2:
1432
    // GDOP_LDXrr, GDOP_LDrr, TLS_LDXrr, TLS_LDrr
1433
0
    printOperand(MI, 3, O);
1434
0
    return;
1435
0
    break;
1436
7.05k
  }
1437
1438
1439
  // Fragment 5 encoded into 1 bits for 2 unique commands.
1440
6.34k
  if ((Bits >> 29) & 1) {
1441
    // TLS_ADDrr
1442
0
    SStream_concat0(O, ", ");
1443
0
    printOperand(MI, 3, O);
1444
0
    return;
1445
6.34k
  } else {
1446
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1447
6.34k
    return;
1448
6.34k
  }
1449
1450
6.34k
}
1451
1452
1453
/// getRegisterName - This method is automatically generated by tblgen
1454
/// from the register set description.  This returns the assembler name
1455
/// for the specified register.
1456
static const char *
1457
107k
getRegisterName(unsigned RegNo, unsigned AltIdx) {
1458
107k
#ifndef CAPSTONE_DIET
1459
107k
  CS_ASSERT_RET_VAL(RegNo && RegNo < 238 && "Invalid register number!", NULL);
1460
1461
107k
  static const char AsmStrsNoRegAltName[] = {
1462
107k
  /* 0 */ "c10\0"
1463
107k
  /* 4 */ "f10\0"
1464
107k
  /* 8 */ "asr10\0"
1465
107k
  /* 14 */ "c20\0"
1466
107k
  /* 18 */ "f20\0"
1467
107k
  /* 22 */ "asr20\0"
1468
107k
  /* 28 */ "c30\0"
1469
107k
  /* 32 */ "f30\0"
1470
107k
  /* 36 */ "asr30\0"
1471
107k
  /* 42 */ "f40\0"
1472
107k
  /* 46 */ "f50\0"
1473
107k
  /* 50 */ "f60\0"
1474
107k
  /* 54 */ "fcc0\0"
1475
107k
  /* 59 */ "f0\0"
1476
107k
  /* 62 */ "g0\0"
1477
107k
  /* 65 */ "i0\0"
1478
107k
  /* 68 */ "l0\0"
1479
107k
  /* 71 */ "o0\0"
1480
107k
  /* 74 */ "c11\0"
1481
107k
  /* 78 */ "f11\0"
1482
107k
  /* 82 */ "asr11\0"
1483
107k
  /* 88 */ "c21\0"
1484
107k
  /* 92 */ "f21\0"
1485
107k
  /* 96 */ "asr21\0"
1486
107k
  /* 102 */ "c31\0"
1487
107k
  /* 106 */ "f31\0"
1488
107k
  /* 110 */ "asr31\0"
1489
107k
  /* 116 */ "fcc1\0"
1490
107k
  /* 121 */ "f1\0"
1491
107k
  /* 124 */ "g1\0"
1492
107k
  /* 127 */ "i1\0"
1493
107k
  /* 130 */ "l1\0"
1494
107k
  /* 133 */ "o1\0"
1495
107k
  /* 136 */ "asr1\0"
1496
107k
  /* 141 */ "c12\0"
1497
107k
  /* 145 */ "f12\0"
1498
107k
  /* 149 */ "asr12\0"
1499
107k
  /* 155 */ "c22\0"
1500
107k
  /* 159 */ "f22\0"
1501
107k
  /* 163 */ "asr22\0"
1502
107k
  /* 169 */ "f32\0"
1503
107k
  /* 173 */ "f42\0"
1504
107k
  /* 177 */ "f52\0"
1505
107k
  /* 181 */ "f62\0"
1506
107k
  /* 185 */ "fcc2\0"
1507
107k
  /* 190 */ "f2\0"
1508
107k
  /* 193 */ "g2\0"
1509
107k
  /* 196 */ "i2\0"
1510
107k
  /* 199 */ "l2\0"
1511
107k
  /* 202 */ "o2\0"
1512
107k
  /* 205 */ "asr2\0"
1513
107k
  /* 210 */ "c13\0"
1514
107k
  /* 214 */ "f13\0"
1515
107k
  /* 218 */ "asr13\0"
1516
107k
  /* 224 */ "c23\0"
1517
107k
  /* 228 */ "f23\0"
1518
107k
  /* 232 */ "asr23\0"
1519
107k
  /* 238 */ "fcc3\0"
1520
107k
  /* 243 */ "f3\0"
1521
107k
  /* 246 */ "g3\0"
1522
107k
  /* 249 */ "i3\0"
1523
107k
  /* 252 */ "l3\0"
1524
107k
  /* 255 */ "o3\0"
1525
107k
  /* 258 */ "asr3\0"
1526
107k
  /* 263 */ "c14\0"
1527
107k
  /* 267 */ "f14\0"
1528
107k
  /* 271 */ "asr14\0"
1529
107k
  /* 277 */ "c24\0"
1530
107k
  /* 281 */ "f24\0"
1531
107k
  /* 285 */ "asr24\0"
1532
107k
  /* 291 */ "f34\0"
1533
107k
  /* 295 */ "f44\0"
1534
107k
  /* 299 */ "f54\0"
1535
107k
  /* 303 */ "c4\0"
1536
107k
  /* 306 */ "f4\0"
1537
107k
  /* 309 */ "g4\0"
1538
107k
  /* 312 */ "i4\0"
1539
107k
  /* 315 */ "l4\0"
1540
107k
  /* 318 */ "o4\0"
1541
107k
  /* 321 */ "asr4\0"
1542
107k
  /* 326 */ "c15\0"
1543
107k
  /* 330 */ "f15\0"
1544
107k
  /* 334 */ "asr15\0"
1545
107k
  /* 340 */ "c25\0"
1546
107k
  /* 344 */ "f25\0"
1547
107k
  /* 348 */ "asr25\0"
1548
107k
  /* 354 */ "c5\0"
1549
107k
  /* 357 */ "f5\0"
1550
107k
  /* 360 */ "g5\0"
1551
107k
  /* 363 */ "i5\0"
1552
107k
  /* 366 */ "l5\0"
1553
107k
  /* 369 */ "o5\0"
1554
107k
  /* 372 */ "asr5\0"
1555
107k
  /* 377 */ "c16\0"
1556
107k
  /* 381 */ "f16\0"
1557
107k
  /* 385 */ "asr16\0"
1558
107k
  /* 391 */ "c26\0"
1559
107k
  /* 395 */ "f26\0"
1560
107k
  /* 399 */ "asr26\0"
1561
107k
  /* 405 */ "f36\0"
1562
107k
  /* 409 */ "f46\0"
1563
107k
  /* 413 */ "f56\0"
1564
107k
  /* 417 */ "c6\0"
1565
107k
  /* 420 */ "f6\0"
1566
107k
  /* 423 */ "g6\0"
1567
107k
  /* 426 */ "i6\0"
1568
107k
  /* 429 */ "l6\0"
1569
107k
  /* 432 */ "o6\0"
1570
107k
  /* 435 */ "asr6\0"
1571
107k
  /* 440 */ "c17\0"
1572
107k
  /* 444 */ "f17\0"
1573
107k
  /* 448 */ "asr17\0"
1574
107k
  /* 454 */ "c27\0"
1575
107k
  /* 458 */ "f27\0"
1576
107k
  /* 462 */ "asr27\0"
1577
107k
  /* 468 */ "c7\0"
1578
107k
  /* 471 */ "f7\0"
1579
107k
  /* 474 */ "g7\0"
1580
107k
  /* 477 */ "i7\0"
1581
107k
  /* 480 */ "l7\0"
1582
107k
  /* 483 */ "o7\0"
1583
107k
  /* 486 */ "asr7\0"
1584
107k
  /* 491 */ "c18\0"
1585
107k
  /* 495 */ "f18\0"
1586
107k
  /* 499 */ "asr18\0"
1587
107k
  /* 505 */ "c28\0"
1588
107k
  /* 509 */ "f28\0"
1589
107k
  /* 513 */ "asr28\0"
1590
107k
  /* 519 */ "f38\0"
1591
107k
  /* 523 */ "f48\0"
1592
107k
  /* 527 */ "f58\0"
1593
107k
  /* 531 */ "c8\0"
1594
107k
  /* 534 */ "f8\0"
1595
107k
  /* 537 */ "asr8\0"
1596
107k
  /* 542 */ "c19\0"
1597
107k
  /* 546 */ "f19\0"
1598
107k
  /* 550 */ "asr19\0"
1599
107k
  /* 556 */ "c29\0"
1600
107k
  /* 560 */ "f29\0"
1601
107k
  /* 564 */ "asr29\0"
1602
107k
  /* 570 */ "c9\0"
1603
107k
  /* 573 */ "f9\0"
1604
107k
  /* 576 */ "asr9\0"
1605
107k
  /* 581 */ "tba\0"
1606
107k
  /* 585 */ "icc\0"
1607
107k
  /* 589 */ "tnpc\0"
1608
107k
  /* 594 */ "tpc\0"
1609
107k
  /* 598 */ "canrestore\0"
1610
107k
  /* 609 */ "pstate\0"
1611
107k
  /* 616 */ "tstate\0"
1612
107k
  /* 623 */ "wstate\0"
1613
107k
  /* 630 */ "cansave\0"
1614
107k
  /* 638 */ "tick\0"
1615
107k
  /* 643 */ "gl\0"
1616
107k
  /* 646 */ "pil\0"
1617
107k
  /* 650 */ "tl\0"
1618
107k
  /* 653 */ "wim\0"
1619
107k
  /* 657 */ "cleanwin\0"
1620
107k
  /* 666 */ "otherwin\0"
1621
107k
  /* 675 */ "fp\0"
1622
107k
  /* 678 */ "sp\0"
1623
107k
  /* 681 */ "cwp\0"
1624
107k
  /* 685 */ "cq\0"
1625
107k
  /* 688 */ "fq\0"
1626
107k
  /* 691 */ "tbr\0"
1627
107k
  /* 695 */ "ver\0"
1628
107k
  /* 699 */ "csr\0"
1629
107k
  /* 703 */ "fsr\0"
1630
107k
  /* 707 */ "psr\0"
1631
107k
  /* 711 */ "tt\0"
1632
107k
  /* 714 */ "y\0"
1633
107k
};
1634
107k
  static const uint16_t RegAsmOffsetNoRegAltName[] = {
1635
107k
    598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, 
1636
107k
    581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, 
1637
107k
    258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, 
1638
107k
    448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, 
1639
107k
    110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, 
1640
107k
    210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, 
1641
107k
    454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, 
1642
107k
    495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, 
1643
107k
    409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, 
1644
107k
    357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, 
1645
107k
    546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, 
1646
107k
    116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, 
1647
107k
    249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, 
1648
107k
    133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, 
1649
107k
    509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, 
1650
107k
    0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, 
1651
107k
    423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, 
1652
107k
  };
1653
1654
107k
  static const char AsmStrsRegNamesStateReg[] = {
1655
107k
  /* 0 */ "pc\0"
1656
107k
  /* 3 */ "asi\0"
1657
107k
  /* 7 */ "tick\0"
1658
107k
  /* 12 */ "ccr\0"
1659
107k
  /* 16 */ "fprs\0"
1660
107k
};
1661
107k
  static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1662
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1663
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, 
1664
107k
    3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1665
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1666
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1667
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1668
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1669
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1670
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1671
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1672
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1673
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1674
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1675
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1676
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1677
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1678
107k
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
1679
107k
  };
1680
1681
107k
  switch(AltIdx) {
1682
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
1683
55.3k
  case Sparc_NoRegAltName:
1684
55.3k
    CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1685
55.3k
           "Invalid alt name index for register!", NULL);
1686
55.3k
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1687
52.3k
  case Sparc_RegNamesStateReg:
1688
52.3k
    if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1689
48.5k
      return getRegisterName(RegNo, Sparc_NoRegAltName);
1690
3.79k
    return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1691
107k
  }
1692
#else
1693
  return NULL;
1694
#endif // CAPSTONE_DIET
1695
107k
}
1696
#ifdef PRINT_ALIAS_INSTR
1697
#undef PRINT_ALIAS_INSTR
1698
1699
33.6k
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
1700
33.6k
#ifndef CAPSTONE_DIET
1701
33.6k
  static const PatternsForOpcode OpToPatterns[] = {
1702
33.6k
    {Sparc_BCOND, 0, 16 },
1703
33.6k
    {Sparc_BCONDA, 16, 16 },
1704
33.6k
    {Sparc_BPFCCANT, 32, 16 },
1705
33.6k
    {Sparc_BPFCCNT, 48, 16 },
1706
33.6k
    {Sparc_BPICCANT, 64, 16 },
1707
33.6k
    {Sparc_BPICCNT, 80, 16 },
1708
33.6k
    {Sparc_BPRANT, 96, 6 },
1709
33.6k
    {Sparc_BPRNT, 102, 6 },
1710
33.6k
    {Sparc_BPXCCANT, 108, 16 },
1711
33.6k
    {Sparc_BPXCCNT, 124, 16 },
1712
33.6k
    {Sparc_CASArr, 140, 2 },
1713
33.6k
    {Sparc_CASXArr, 142, 2 },
1714
33.6k
    {Sparc_FMOVD_ICC, 144, 16 },
1715
33.6k
    {Sparc_FMOVD_XCC, 160, 16 },
1716
33.6k
    {Sparc_FMOVQ_ICC, 176, 16 },
1717
33.6k
    {Sparc_FMOVQ_XCC, 192, 16 },
1718
33.6k
    {Sparc_FMOVRD, 208, 6 },
1719
33.6k
    {Sparc_FMOVRQ, 214, 6 },
1720
33.6k
    {Sparc_FMOVRS, 220, 6 },
1721
33.6k
    {Sparc_FMOVS_ICC, 226, 16 },
1722
33.6k
    {Sparc_FMOVS_XCC, 242, 16 },
1723
33.6k
    {Sparc_MOVICCri, 258, 16 },
1724
33.6k
    {Sparc_MOVICCrr, 274, 16 },
1725
33.6k
    {Sparc_MOVRri, 290, 6 },
1726
33.6k
    {Sparc_MOVRrr, 296, 6 },
1727
33.6k
    {Sparc_MOVXCCri, 302, 16 },
1728
33.6k
    {Sparc_MOVXCCrr, 318, 16 },
1729
33.6k
    {Sparc_ORCCrr, 334, 1 },
1730
33.6k
    {Sparc_ORri, 335, 1 },
1731
33.6k
    {Sparc_ORrr, 336, 1 },
1732
33.6k
    {Sparc_RESTORErr, 337, 1 },
1733
33.6k
    {Sparc_RET, 338, 1 },
1734
33.6k
    {Sparc_RETL, 339, 1 },
1735
33.6k
    {Sparc_SAVErr, 340, 1 },
1736
33.6k
    {Sparc_SUBCCri, 341, 1 },
1737
33.6k
    {Sparc_SUBCCrr, 342, 1 },
1738
33.6k
    {Sparc_TICCri, 343, 32 },
1739
33.6k
    {Sparc_TICCrr, 375, 32 },
1740
33.6k
    {Sparc_TRAPri, 407, 32 },
1741
33.6k
    {Sparc_TRAPrr, 439, 32 },
1742
33.6k
    {Sparc_TXCCri, 471, 32 },
1743
33.6k
    {Sparc_TXCCrr, 503, 32 },
1744
33.6k
    {Sparc_V9FCMPD, 535, 1 },
1745
33.6k
    {Sparc_V9FCMPED, 536, 1 },
1746
33.6k
    {Sparc_V9FCMPEQ, 537, 1 },
1747
33.6k
    {Sparc_V9FCMPES, 538, 1 },
1748
33.6k
    {Sparc_V9FCMPQ, 539, 1 },
1749
33.6k
    {Sparc_V9FCMPS, 540, 1 },
1750
33.6k
    {Sparc_V9FMOVD_FCC, 541, 16 },
1751
33.6k
    {Sparc_V9FMOVQ_FCC, 557, 16 },
1752
33.6k
    {Sparc_V9FMOVS_FCC, 573, 16 },
1753
33.6k
    {Sparc_V9MOVFCCri, 589, 16 },
1754
33.6k
    {Sparc_V9MOVFCCrr, 605, 16 },
1755
33.6k
  {0},  };
1756
1757
33.6k
  static const AliasPattern Patterns[] = {
1758
    // Sparc_BCOND - 0
1759
33.6k
    {0, 0, 2, 2 },
1760
33.6k
    {6, 2, 2, 2 },
1761
33.6k
    {12, 4, 2, 2 },
1762
33.6k
    {19, 6, 2, 2 },
1763
33.6k
    {25, 8, 2, 2 },
1764
33.6k
    {31, 10, 2, 2 },
1765
33.6k
    {38, 12, 2, 2 },
1766
33.6k
    {45, 14, 2, 2 },
1767
33.6k
    {51, 16, 2, 2 },
1768
33.6k
    {58, 18, 2, 2 },
1769
33.6k
    {66, 20, 2, 2 },
1770
33.6k
    {73, 22, 2, 2 },
1771
33.6k
    {80, 24, 2, 2 },
1772
33.6k
    {88, 26, 2, 2 },
1773
33.6k
    {96, 28, 2, 2 },
1774
33.6k
    {103, 30, 2, 2 },
1775
    // Sparc_BCONDA - 16
1776
33.6k
    {110, 32, 2, 2 },
1777
33.6k
    {118, 34, 2, 2 },
1778
33.6k
    {126, 36, 2, 2 },
1779
33.6k
    {135, 38, 2, 2 },
1780
33.6k
    {143, 40, 2, 2 },
1781
33.6k
    {151, 42, 2, 2 },
1782
33.6k
    {160, 44, 2, 2 },
1783
33.6k
    {169, 46, 2, 2 },
1784
33.6k
    {177, 48, 2, 2 },
1785
33.6k
    {186, 50, 2, 2 },
1786
33.6k
    {196, 52, 2, 2 },
1787
33.6k
    {205, 54, 2, 2 },
1788
33.6k
    {214, 56, 2, 2 },
1789
33.6k
    {224, 58, 2, 2 },
1790
33.6k
    {234, 60, 2, 2 },
1791
33.6k
    {243, 62, 2, 2 },
1792
    // Sparc_BPFCCANT - 32
1793
33.6k
    {252, 64, 3, 4 },
1794
33.6k
    {268, 68, 3, 4 },
1795
33.6k
    {284, 72, 3, 4 },
1796
33.6k
    {300, 76, 3, 4 },
1797
33.6k
    {316, 80, 3, 4 },
1798
33.6k
    {333, 84, 3, 4 },
1799
33.6k
    {349, 88, 3, 4 },
1800
33.6k
    {366, 92, 3, 4 },
1801
33.6k
    {383, 96, 3, 4 },
1802
33.6k
    {400, 100, 3, 4 },
1803
33.6k
    {416, 104, 3, 4 },
1804
33.6k
    {433, 108, 3, 4 },
1805
33.6k
    {450, 112, 3, 4 },
1806
33.6k
    {468, 116, 3, 4 },
1807
33.6k
    {485, 120, 3, 4 },
1808
33.6k
    {503, 124, 3, 4 },
1809
    // Sparc_BPFCCNT - 48
1810
33.6k
    {519, 128, 3, 4 },
1811
33.6k
    {533, 132, 3, 4 },
1812
33.6k
    {547, 136, 3, 4 },
1813
33.6k
    {561, 140, 3, 4 },
1814
33.6k
    {575, 144, 3, 4 },
1815
33.6k
    {590, 148, 3, 4 },
1816
33.6k
    {604, 152, 3, 4 },
1817
33.6k
    {619, 156, 3, 4 },
1818
33.6k
    {634, 160, 3, 4 },
1819
33.6k
    {649, 164, 3, 4 },
1820
33.6k
    {663, 168, 3, 4 },
1821
33.6k
    {678, 172, 3, 4 },
1822
33.6k
    {693, 176, 3, 4 },
1823
33.6k
    {709, 180, 3, 4 },
1824
33.6k
    {724, 184, 3, 4 },
1825
33.6k
    {740, 188, 3, 4 },
1826
    // Sparc_BPICCANT - 64
1827
33.6k
    {754, 192, 2, 3 },
1828
33.6k
    {771, 195, 2, 3 },
1829
33.6k
    {788, 198, 2, 3 },
1830
33.6k
    {806, 201, 2, 3 },
1831
33.6k
    {823, 204, 2, 3 },
1832
33.6k
    {840, 207, 2, 3 },
1833
33.6k
    {858, 210, 2, 3 },
1834
33.6k
    {876, 213, 2, 3 },
1835
33.6k
    {893, 216, 2, 3 },
1836
33.6k
    {911, 219, 2, 3 },
1837
33.6k
    {930, 222, 2, 3 },
1838
33.6k
    {948, 225, 2, 3 },
1839
33.6k
    {966, 228, 2, 3 },
1840
33.6k
    {985, 231, 2, 3 },
1841
33.6k
    {1004, 234, 2, 3 },
1842
33.6k
    {1022, 237, 2, 3 },
1843
    // Sparc_BPICCNT - 80
1844
33.6k
    {1040, 240, 2, 3 },
1845
33.6k
    {1055, 243, 2, 3 },
1846
33.6k
    {1070, 246, 2, 3 },
1847
33.6k
    {1086, 249, 2, 3 },
1848
33.6k
    {1101, 252, 2, 3 },
1849
33.6k
    {1116, 255, 2, 3 },
1850
33.6k
    {1132, 258, 2, 3 },
1851
33.6k
    {1148, 261, 2, 3 },
1852
33.6k
    {1163, 264, 2, 3 },
1853
33.6k
    {1179, 267, 2, 3 },
1854
33.6k
    {1196, 270, 2, 3 },
1855
33.6k
    {1212, 273, 2, 3 },
1856
33.6k
    {1228, 276, 2, 3 },
1857
33.6k
    {1245, 279, 2, 3 },
1858
33.6k
    {1262, 282, 2, 3 },
1859
33.6k
    {1278, 285, 2, 3 },
1860
    // Sparc_BPRANT - 96
1861
33.6k
    {1294, 288, 3, 4 },
1862
33.6k
    {1310, 292, 3, 4 },
1863
33.6k
    {1328, 296, 3, 4 },
1864
33.6k
    {1345, 300, 3, 4 },
1865
33.6k
    {1362, 304, 3, 4 },
1866
33.6k
    {1379, 308, 3, 4 },
1867
    // Sparc_BPRNT - 102
1868
33.6k
    {1397, 312, 3, 4 },
1869
33.6k
    {1411, 316, 3, 4 },
1870
33.6k
    {1427, 320, 3, 4 },
1871
33.6k
    {1442, 324, 3, 4 },
1872
33.6k
    {1457, 328, 3, 4 },
1873
33.6k
    {1472, 332, 3, 4 },
1874
    // Sparc_BPXCCANT - 108
1875
33.6k
    {1488, 336, 2, 3 },
1876
33.6k
    {1505, 339, 2, 3 },
1877
33.6k
    {1522, 342, 2, 3 },
1878
33.6k
    {1540, 345, 2, 3 },
1879
33.6k
    {1557, 348, 2, 3 },
1880
33.6k
    {1574, 351, 2, 3 },
1881
33.6k
    {1592, 354, 2, 3 },
1882
33.6k
    {1610, 357, 2, 3 },
1883
33.6k
    {1627, 360, 2, 3 },
1884
33.6k
    {1645, 363, 2, 3 },
1885
33.6k
    {1664, 366, 2, 3 },
1886
33.6k
    {1682, 369, 2, 3 },
1887
33.6k
    {1700, 372, 2, 3 },
1888
33.6k
    {1719, 375, 2, 3 },
1889
33.6k
    {1738, 378, 2, 3 },
1890
33.6k
    {1756, 381, 2, 3 },
1891
    // Sparc_BPXCCNT - 124
1892
33.6k
    {1774, 384, 2, 3 },
1893
33.6k
    {1789, 387, 2, 3 },
1894
33.6k
    {1804, 390, 2, 3 },
1895
33.6k
    {1820, 393, 2, 3 },
1896
33.6k
    {1835, 396, 2, 3 },
1897
33.6k
    {1850, 399, 2, 3 },
1898
33.6k
    {1866, 402, 2, 3 },
1899
33.6k
    {1882, 405, 2, 3 },
1900
33.6k
    {1897, 408, 2, 3 },
1901
33.6k
    {1913, 411, 2, 3 },
1902
33.6k
    {1930, 414, 2, 3 },
1903
33.6k
    {1946, 417, 2, 3 },
1904
33.6k
    {1962, 420, 2, 3 },
1905
33.6k
    {1979, 423, 2, 3 },
1906
33.6k
    {1996, 426, 2, 3 },
1907
33.6k
    {2012, 429, 2, 3 },
1908
    // Sparc_CASArr - 140
1909
33.6k
    {2028, 432, 5, 6 },
1910
33.6k
    {2045, 438, 5, 6 },
1911
    // Sparc_CASXArr - 142
1912
33.6k
    {2063, 444, 5, 6 },
1913
33.6k
    {2081, 450, 5, 6 },
1914
    // Sparc_FMOVD_ICC - 144
1915
33.6k
    {2100, 456, 4, 5 },
1916
33.6k
    {2120, 461, 4, 5 },
1917
33.6k
    {2140, 466, 4, 5 },
1918
33.6k
    {2161, 471, 4, 5 },
1919
33.6k
    {2181, 476, 4, 5 },
1920
33.6k
    {2201, 481, 4, 5 },
1921
33.6k
    {2222, 486, 4, 5 },
1922
33.6k
    {2243, 491, 4, 5 },
1923
33.6k
    {2263, 496, 4, 5 },
1924
33.6k
    {2284, 501, 4, 5 },
1925
33.6k
    {2306, 506, 4, 5 },
1926
33.6k
    {2327, 511, 4, 5 },
1927
33.6k
    {2348, 516, 4, 5 },
1928
33.6k
    {2370, 521, 4, 5 },
1929
33.6k
    {2392, 526, 4, 5 },
1930
33.6k
    {2413, 531, 4, 5 },
1931
    // Sparc_FMOVD_XCC - 160
1932
33.6k
    {2434, 536, 4, 5 },
1933
33.6k
    {2454, 541, 4, 5 },
1934
33.6k
    {2474, 546, 4, 5 },
1935
33.6k
    {2495, 551, 4, 5 },
1936
33.6k
    {2515, 556, 4, 5 },
1937
33.6k
    {2535, 561, 4, 5 },
1938
33.6k
    {2556, 566, 4, 5 },
1939
33.6k
    {2577, 571, 4, 5 },
1940
33.6k
    {2597, 576, 4, 5 },
1941
33.6k
    {2618, 581, 4, 5 },
1942
33.6k
    {2640, 586, 4, 5 },
1943
33.6k
    {2661, 591, 4, 5 },
1944
33.6k
    {2682, 596, 4, 5 },
1945
33.6k
    {2704, 601, 4, 5 },
1946
33.6k
    {2726, 606, 4, 5 },
1947
33.6k
    {2747, 611, 4, 5 },
1948
    // Sparc_FMOVQ_ICC - 176
1949
33.6k
    {2768, 616, 4, 5 },
1950
33.6k
    {2788, 621, 4, 5 },
1951
33.6k
    {2808, 626, 4, 5 },
1952
33.6k
    {2829, 631, 4, 5 },
1953
33.6k
    {2849, 636, 4, 5 },
1954
33.6k
    {2869, 641, 4, 5 },
1955
33.6k
    {2890, 646, 4, 5 },
1956
33.6k
    {2911, 651, 4, 5 },
1957
33.6k
    {2931, 656, 4, 5 },
1958
33.6k
    {2952, 661, 4, 5 },
1959
33.6k
    {2974, 666, 4, 5 },
1960
33.6k
    {2995, 671, 4, 5 },
1961
33.6k
    {3016, 676, 4, 5 },
1962
33.6k
    {3038, 681, 4, 5 },
1963
33.6k
    {3060, 686, 4, 5 },
1964
33.6k
    {3081, 691, 4, 5 },
1965
    // Sparc_FMOVQ_XCC - 192
1966
33.6k
    {3102, 696, 4, 5 },
1967
33.6k
    {3122, 701, 4, 5 },
1968
33.6k
    {3142, 706, 4, 5 },
1969
33.6k
    {3163, 711, 4, 5 },
1970
33.6k
    {3183, 716, 4, 5 },
1971
33.6k
    {3203, 721, 4, 5 },
1972
33.6k
    {3224, 726, 4, 5 },
1973
33.6k
    {3245, 731, 4, 5 },
1974
33.6k
    {3265, 736, 4, 5 },
1975
33.6k
    {3286, 741, 4, 5 },
1976
33.6k
    {3308, 746, 4, 5 },
1977
33.6k
    {3329, 751, 4, 5 },
1978
33.6k
    {3350, 756, 4, 5 },
1979
33.6k
    {3372, 761, 4, 5 },
1980
33.6k
    {3394, 766, 4, 5 },
1981
33.6k
    {3415, 771, 4, 5 },
1982
    // Sparc_FMOVRD - 208
1983
33.6k
    {3436, 776, 5, 6 },
1984
33.6k
    {3455, 782, 5, 6 },
1985
33.6k
    {3476, 788, 5, 6 },
1986
33.6k
    {3496, 794, 5, 6 },
1987
33.6k
    {3516, 800, 5, 6 },
1988
33.6k
    {3536, 806, 5, 6 },
1989
    // Sparc_FMOVRQ - 214
1990
33.6k
    {3557, 812, 5, 6 },
1991
33.6k
    {3576, 818, 5, 6 },
1992
33.6k
    {3597, 824, 5, 6 },
1993
33.6k
    {3617, 830, 5, 6 },
1994
33.6k
    {3637, 836, 5, 6 },
1995
33.6k
    {3657, 842, 5, 6 },
1996
    // Sparc_FMOVRS - 220
1997
33.6k
    {3678, 848, 5, 6 },
1998
33.6k
    {3697, 854, 5, 6 },
1999
33.6k
    {3718, 860, 5, 6 },
2000
33.6k
    {3738, 866, 5, 6 },
2001
33.6k
    {3758, 872, 5, 6 },
2002
33.6k
    {3778, 878, 5, 6 },
2003
    // Sparc_FMOVS_ICC - 226
2004
33.6k
    {3799, 884, 4, 5 },
2005
33.6k
    {3819, 889, 4, 5 },
2006
33.6k
    {3839, 894, 4, 5 },
2007
33.6k
    {3860, 899, 4, 5 },
2008
33.6k
    {3880, 904, 4, 5 },
2009
33.6k
    {3900, 909, 4, 5 },
2010
33.6k
    {3921, 914, 4, 5 },
2011
33.6k
    {3942, 919, 4, 5 },
2012
33.6k
    {3962, 924, 4, 5 },
2013
33.6k
    {3983, 929, 4, 5 },
2014
33.6k
    {4005, 934, 4, 5 },
2015
33.6k
    {4026, 939, 4, 5 },
2016
33.6k
    {4047, 944, 4, 5 },
2017
33.6k
    {4069, 949, 4, 5 },
2018
33.6k
    {4091, 954, 4, 5 },
2019
33.6k
    {4112, 959, 4, 5 },
2020
    // Sparc_FMOVS_XCC - 242
2021
33.6k
    {4133, 964, 4, 5 },
2022
33.6k
    {4153, 969, 4, 5 },
2023
33.6k
    {4173, 974, 4, 5 },
2024
33.6k
    {4194, 979, 4, 5 },
2025
33.6k
    {4214, 984, 4, 5 },
2026
33.6k
    {4234, 989, 4, 5 },
2027
33.6k
    {4255, 994, 4, 5 },
2028
33.6k
    {4276, 999, 4, 5 },
2029
33.6k
    {4296, 1004, 4, 5 },
2030
33.6k
    {4317, 1009, 4, 5 },
2031
33.6k
    {4339, 1014, 4, 5 },
2032
33.6k
    {4360, 1019, 4, 5 },
2033
33.6k
    {4381, 1024, 4, 5 },
2034
33.6k
    {4403, 1029, 4, 5 },
2035
33.6k
    {4425, 1034, 4, 5 },
2036
33.6k
    {4446, 1039, 4, 5 },
2037
    // Sparc_MOVICCri - 258
2038
33.6k
    {4467, 1044, 4, 5 },
2039
33.6k
    {4485, 1049, 4, 5 },
2040
33.6k
    {4503, 1054, 4, 5 },
2041
33.6k
    {4522, 1059, 4, 5 },
2042
33.6k
    {4540, 1064, 4, 5 },
2043
33.6k
    {4558, 1069, 4, 5 },
2044
33.6k
    {4577, 1074, 4, 5 },
2045
33.6k
    {4596, 1079, 4, 5 },
2046
33.6k
    {4614, 1084, 4, 5 },
2047
33.6k
    {4633, 1089, 4, 5 },
2048
33.6k
    {4653, 1094, 4, 5 },
2049
33.6k
    {4672, 1099, 4, 5 },
2050
33.6k
    {4691, 1104, 4, 5 },
2051
33.6k
    {4711, 1109, 4, 5 },
2052
33.6k
    {4731, 1114, 4, 5 },
2053
33.6k
    {4750, 1119, 4, 5 },
2054
    // Sparc_MOVICCrr - 274
2055
33.6k
    {4467, 1124, 4, 5 },
2056
33.6k
    {4485, 1129, 4, 5 },
2057
33.6k
    {4503, 1134, 4, 5 },
2058
33.6k
    {4522, 1139, 4, 5 },
2059
33.6k
    {4540, 1144, 4, 5 },
2060
33.6k
    {4558, 1149, 4, 5 },
2061
33.6k
    {4577, 1154, 4, 5 },
2062
33.6k
    {4596, 1159, 4, 5 },
2063
33.6k
    {4614, 1164, 4, 5 },
2064
33.6k
    {4633, 1169, 4, 5 },
2065
33.6k
    {4653, 1174, 4, 5 },
2066
33.6k
    {4672, 1179, 4, 5 },
2067
33.6k
    {4691, 1184, 4, 5 },
2068
33.6k
    {4711, 1189, 4, 5 },
2069
33.6k
    {4731, 1194, 4, 5 },
2070
33.6k
    {4750, 1199, 4, 5 },
2071
    // Sparc_MOVRri - 290
2072
33.6k
    {4769, 1204, 5, 6 },
2073
33.6k
    {4786, 1210, 5, 6 },
2074
33.6k
    {4805, 1216, 5, 6 },
2075
33.6k
    {4823, 1222, 5, 6 },
2076
33.6k
    {4841, 1228, 5, 6 },
2077
33.6k
    {4859, 1234, 5, 6 },
2078
    // Sparc_MOVRrr - 296
2079
33.6k
    {4769, 1240, 5, 6 },
2080
33.6k
    {4786, 1246, 5, 6 },
2081
33.6k
    {4805, 1252, 5, 6 },
2082
33.6k
    {4823, 1258, 5, 6 },
2083
33.6k
    {4841, 1264, 5, 6 },
2084
33.6k
    {4859, 1270, 5, 6 },
2085
    // Sparc_MOVXCCri - 302
2086
33.6k
    {4878, 1276, 4, 5 },
2087
33.6k
    {4896, 1281, 4, 5 },
2088
33.6k
    {4914, 1286, 4, 5 },
2089
33.6k
    {4933, 1291, 4, 5 },
2090
33.6k
    {4951, 1296, 4, 5 },
2091
33.6k
    {4969, 1301, 4, 5 },
2092
33.6k
    {4988, 1306, 4, 5 },
2093
33.6k
    {5007, 1311, 4, 5 },
2094
33.6k
    {5025, 1316, 4, 5 },
2095
33.6k
    {5044, 1321, 4, 5 },
2096
33.6k
    {5064, 1326, 4, 5 },
2097
33.6k
    {5083, 1331, 4, 5 },
2098
33.6k
    {5102, 1336, 4, 5 },
2099
33.6k
    {5122, 1341, 4, 5 },
2100
33.6k
    {5142, 1346, 4, 5 },
2101
33.6k
    {5161, 1351, 4, 5 },
2102
    // Sparc_MOVXCCrr - 318
2103
33.6k
    {4878, 1356, 4, 5 },
2104
33.6k
    {4896, 1361, 4, 5 },
2105
33.6k
    {4914, 1366, 4, 5 },
2106
33.6k
    {4933, 1371, 4, 5 },
2107
33.6k
    {4951, 1376, 4, 5 },
2108
33.6k
    {4969, 1381, 4, 5 },
2109
33.6k
    {4988, 1386, 4, 5 },
2110
33.6k
    {5007, 1391, 4, 5 },
2111
33.6k
    {5025, 1396, 4, 5 },
2112
33.6k
    {5044, 1401, 4, 5 },
2113
33.6k
    {5064, 1406, 4, 5 },
2114
33.6k
    {5083, 1411, 4, 5 },
2115
33.6k
    {5102, 1416, 4, 5 },
2116
33.6k
    {5122, 1421, 4, 5 },
2117
33.6k
    {5142, 1426, 4, 5 },
2118
33.6k
    {5161, 1431, 4, 5 },
2119
    // Sparc_ORCCrr - 334
2120
33.6k
    {5180, 1436, 3, 3 },
2121
    // Sparc_ORri - 335
2122
33.6k
    {5187, 1439, 3, 2 },
2123
    // Sparc_ORrr - 336
2124
33.6k
    {5187, 1441, 3, 3 },
2125
    // Sparc_RESTORErr - 337
2126
33.6k
    {5198, 1444, 3, 3 },
2127
    // Sparc_RET - 338
2128
33.6k
    {5206, 1447, 1, 1 },
2129
    // Sparc_RETL - 339
2130
33.6k
    {5210, 1448, 1, 1 },
2131
    // Sparc_SAVErr - 340
2132
33.6k
    {5215, 1449, 3, 3 },
2133
    // Sparc_SUBCCri - 341
2134
33.6k
    {5220, 1452, 3, 2 },
2135
    // Sparc_SUBCCrr - 342
2136
33.6k
    {5220, 1454, 3, 3 },
2137
    // Sparc_TICCri - 343
2138
33.6k
    {5231, 1457, 3, 4 },
2139
33.6k
    {5243, 1461, 3, 4 },
2140
33.6k
    {5260, 1465, 3, 4 },
2141
33.6k
    {5272, 1469, 3, 4 },
2142
33.6k
    {5289, 1473, 3, 4 },
2143
33.6k
    {5302, 1477, 3, 4 },
2144
33.6k
    {5320, 1481, 3, 4 },
2145
33.6k
    {5332, 1485, 3, 4 },
2146
33.6k
    {5349, 1489, 3, 4 },
2147
33.6k
    {5361, 1493, 3, 4 },
2148
33.6k
    {5378, 1497, 3, 4 },
2149
33.6k
    {5391, 1501, 3, 4 },
2150
33.6k
    {5409, 1505, 3, 4 },
2151
33.6k
    {5422, 1509, 3, 4 },
2152
33.6k
    {5440, 1513, 3, 4 },
2153
33.6k
    {5452, 1517, 3, 4 },
2154
33.6k
    {5469, 1521, 3, 4 },
2155
33.6k
    {5482, 1525, 3, 4 },
2156
33.6k
    {5500, 1529, 3, 4 },
2157
33.6k
    {5514, 1533, 3, 4 },
2158
33.6k
    {5533, 1537, 3, 4 },
2159
33.6k
    {5546, 1541, 3, 4 },
2160
33.6k
    {5564, 1545, 3, 4 },
2161
33.6k
    {5577, 1549, 3, 4 },
2162
33.6k
    {5595, 1553, 3, 4 },
2163
33.6k
    {5609, 1557, 3, 4 },
2164
33.6k
    {5628, 1561, 3, 4 },
2165
33.6k
    {5642, 1565, 3, 4 },
2166
33.6k
    {5661, 1569, 3, 4 },
2167
33.6k
    {5674, 1573, 3, 4 },
2168
33.6k
    {5692, 1577, 3, 4 },
2169
33.6k
    {5705, 1581, 3, 4 },
2170
    // Sparc_TICCrr - 375
2171
33.6k
    {5231, 1585, 3, 4 },
2172
33.6k
    {5243, 1589, 3, 4 },
2173
33.6k
    {5260, 1593, 3, 4 },
2174
33.6k
    {5272, 1597, 3, 4 },
2175
33.6k
    {5289, 1601, 3, 4 },
2176
33.6k
    {5302, 1605, 3, 4 },
2177
33.6k
    {5320, 1609, 3, 4 },
2178
33.6k
    {5332, 1613, 3, 4 },
2179
33.6k
    {5349, 1617, 3, 4 },
2180
33.6k
    {5361, 1621, 3, 4 },
2181
33.6k
    {5378, 1625, 3, 4 },
2182
33.6k
    {5391, 1629, 3, 4 },
2183
33.6k
    {5409, 1633, 3, 4 },
2184
33.6k
    {5422, 1637, 3, 4 },
2185
33.6k
    {5440, 1641, 3, 4 },
2186
33.6k
    {5452, 1645, 3, 4 },
2187
33.6k
    {5469, 1649, 3, 4 },
2188
33.6k
    {5482, 1653, 3, 4 },
2189
33.6k
    {5500, 1657, 3, 4 },
2190
33.6k
    {5514, 1661, 3, 4 },
2191
33.6k
    {5533, 1665, 3, 4 },
2192
33.6k
    {5546, 1669, 3, 4 },
2193
33.6k
    {5564, 1673, 3, 4 },
2194
33.6k
    {5577, 1677, 3, 4 },
2195
33.6k
    {5595, 1681, 3, 4 },
2196
33.6k
    {5609, 1685, 3, 4 },
2197
33.6k
    {5628, 1689, 3, 4 },
2198
33.6k
    {5642, 1693, 3, 4 },
2199
33.6k
    {5661, 1697, 3, 4 },
2200
33.6k
    {5674, 1701, 3, 4 },
2201
33.6k
    {5692, 1705, 3, 4 },
2202
33.6k
    {5705, 1709, 3, 4 },
2203
    // Sparc_TRAPri - 407
2204
33.6k
    {5723, 1713, 3, 3 },
2205
33.6k
    {5729, 1716, 3, 3 },
2206
33.6k
    {5740, 1719, 3, 3 },
2207
33.6k
    {5746, 1722, 3, 3 },
2208
33.6k
    {5757, 1725, 3, 3 },
2209
33.6k
    {5764, 1728, 3, 3 },
2210
33.6k
    {5776, 1731, 3, 3 },
2211
33.6k
    {5782, 1734, 3, 3 },
2212
33.6k
    {5793, 1737, 3, 3 },
2213
33.6k
    {5799, 1740, 3, 3 },
2214
33.6k
    {5810, 1743, 3, 3 },
2215
33.6k
    {5817, 1746, 3, 3 },
2216
33.6k
    {5829, 1749, 3, 3 },
2217
33.6k
    {5836, 1752, 3, 3 },
2218
33.6k
    {5848, 1755, 3, 3 },
2219
33.6k
    {5854, 1758, 3, 3 },
2220
33.6k
    {5865, 1761, 3, 3 },
2221
33.6k
    {5872, 1764, 3, 3 },
2222
33.6k
    {5884, 1767, 3, 3 },
2223
33.6k
    {5892, 1770, 3, 3 },
2224
33.6k
    {5905, 1773, 3, 3 },
2225
33.6k
    {5912, 1776, 3, 3 },
2226
33.6k
    {5924, 1779, 3, 3 },
2227
33.6k
    {5931, 1782, 3, 3 },
2228
33.6k
    {5943, 1785, 3, 3 },
2229
33.6k
    {5951, 1788, 3, 3 },
2230
33.6k
    {5964, 1791, 3, 3 },
2231
33.6k
    {5972, 1794, 3, 3 },
2232
33.6k
    {5985, 1797, 3, 3 },
2233
33.6k
    {5992, 1800, 3, 3 },
2234
33.6k
    {6004, 1803, 3, 3 },
2235
33.6k
    {6011, 1806, 3, 3 },
2236
    // Sparc_TRAPrr - 439
2237
33.6k
    {5723, 1809, 3, 3 },
2238
33.6k
    {5729, 1812, 3, 3 },
2239
33.6k
    {5740, 1815, 3, 3 },
2240
33.6k
    {5746, 1818, 3, 3 },
2241
33.6k
    {5757, 1821, 3, 3 },
2242
33.6k
    {5764, 1824, 3, 3 },
2243
33.6k
    {5776, 1827, 3, 3 },
2244
33.6k
    {5782, 1830, 3, 3 },
2245
33.6k
    {5793, 1833, 3, 3 },
2246
33.6k
    {5799, 1836, 3, 3 },
2247
33.6k
    {5810, 1839, 3, 3 },
2248
33.6k
    {5817, 1842, 3, 3 },
2249
33.6k
    {5829, 1845, 3, 3 },
2250
33.6k
    {5836, 1848, 3, 3 },
2251
33.6k
    {5848, 1851, 3, 3 },
2252
33.6k
    {5854, 1854, 3, 3 },
2253
33.6k
    {5865, 1857, 3, 3 },
2254
33.6k
    {5872, 1860, 3, 3 },
2255
33.6k
    {5884, 1863, 3, 3 },
2256
33.6k
    {5892, 1866, 3, 3 },
2257
33.6k
    {5905, 1869, 3, 3 },
2258
33.6k
    {5912, 1872, 3, 3 },
2259
33.6k
    {5924, 1875, 3, 3 },
2260
33.6k
    {5931, 1878, 3, 3 },
2261
33.6k
    {5943, 1881, 3, 3 },
2262
33.6k
    {5951, 1884, 3, 3 },
2263
33.6k
    {5964, 1887, 3, 3 },
2264
33.6k
    {5972, 1890, 3, 3 },
2265
33.6k
    {5985, 1893, 3, 3 },
2266
33.6k
    {5992, 1896, 3, 3 },
2267
33.6k
    {6004, 1899, 3, 3 },
2268
33.6k
    {6011, 1902, 3, 3 },
2269
    // Sparc_TXCCri - 471
2270
33.6k
    {6023, 1905, 3, 4 },
2271
33.6k
    {6035, 1909, 3, 4 },
2272
33.6k
    {6052, 1913, 3, 4 },
2273
33.6k
    {6064, 1917, 3, 4 },
2274
33.6k
    {6081, 1921, 3, 4 },
2275
33.6k
    {6094, 1925, 3, 4 },
2276
33.6k
    {6112, 1929, 3, 4 },
2277
33.6k
    {6124, 1933, 3, 4 },
2278
33.6k
    {6141, 1937, 3, 4 },
2279
33.6k
    {6153, 1941, 3, 4 },
2280
33.6k
    {6170, 1945, 3, 4 },
2281
33.6k
    {6183, 1949, 3, 4 },
2282
33.6k
    {6201, 1953, 3, 4 },
2283
33.6k
    {6214, 1957, 3, 4 },
2284
33.6k
    {6232, 1961, 3, 4 },
2285
33.6k
    {6244, 1965, 3, 4 },
2286
33.6k
    {6261, 1969, 3, 4 },
2287
33.6k
    {6274, 1973, 3, 4 },
2288
33.6k
    {6292, 1977, 3, 4 },
2289
33.6k
    {6306, 1981, 3, 4 },
2290
33.6k
    {6325, 1985, 3, 4 },
2291
33.6k
    {6338, 1989, 3, 4 },
2292
33.6k
    {6356, 1993, 3, 4 },
2293
33.6k
    {6369, 1997, 3, 4 },
2294
33.6k
    {6387, 2001, 3, 4 },
2295
33.6k
    {6401, 2005, 3, 4 },
2296
33.6k
    {6420, 2009, 3, 4 },
2297
33.6k
    {6434, 2013, 3, 4 },
2298
33.6k
    {6453, 2017, 3, 4 },
2299
33.6k
    {6466, 2021, 3, 4 },
2300
33.6k
    {6484, 2025, 3, 4 },
2301
33.6k
    {6497, 2029, 3, 4 },
2302
    // Sparc_TXCCrr - 503
2303
33.6k
    {6023, 2033, 3, 4 },
2304
33.6k
    {6035, 2037, 3, 4 },
2305
33.6k
    {6052, 2041, 3, 4 },
2306
33.6k
    {6064, 2045, 3, 4 },
2307
33.6k
    {6081, 2049, 3, 4 },
2308
33.6k
    {6094, 2053, 3, 4 },
2309
33.6k
    {6112, 2057, 3, 4 },
2310
33.6k
    {6124, 2061, 3, 4 },
2311
33.6k
    {6141, 2065, 3, 4 },
2312
33.6k
    {6153, 2069, 3, 4 },
2313
33.6k
    {6170, 2073, 3, 4 },
2314
33.6k
    {6183, 2077, 3, 4 },
2315
33.6k
    {6201, 2081, 3, 4 },
2316
33.6k
    {6214, 2085, 3, 4 },
2317
33.6k
    {6232, 2089, 3, 4 },
2318
33.6k
    {6244, 2093, 3, 4 },
2319
33.6k
    {6261, 2097, 3, 4 },
2320
33.6k
    {6274, 2101, 3, 4 },
2321
33.6k
    {6292, 2105, 3, 4 },
2322
33.6k
    {6306, 2109, 3, 4 },
2323
33.6k
    {6325, 2113, 3, 4 },
2324
33.6k
    {6338, 2117, 3, 4 },
2325
33.6k
    {6356, 2121, 3, 4 },
2326
33.6k
    {6369, 2125, 3, 4 },
2327
33.6k
    {6387, 2129, 3, 4 },
2328
33.6k
    {6401, 2133, 3, 4 },
2329
33.6k
    {6420, 2137, 3, 4 },
2330
33.6k
    {6434, 2141, 3, 4 },
2331
33.6k
    {6453, 2145, 3, 4 },
2332
33.6k
    {6466, 2149, 3, 4 },
2333
33.6k
    {6484, 2153, 3, 4 },
2334
33.6k
    {6497, 2157, 3, 4 },
2335
    // Sparc_V9FCMPD - 535
2336
33.6k
    {6515, 2161, 3, 3 },
2337
    // Sparc_V9FCMPED - 536
2338
33.6k
    {6528, 2164, 3, 3 },
2339
    // Sparc_V9FCMPEQ - 537
2340
33.6k
    {6542, 2167, 3, 3 },
2341
    // Sparc_V9FCMPES - 538
2342
33.6k
    {6556, 2170, 3, 3 },
2343
    // Sparc_V9FCMPQ - 539
2344
33.6k
    {6570, 2173, 3, 3 },
2345
    // Sparc_V9FCMPS - 540
2346
33.6k
    {6583, 2176, 3, 3 },
2347
    // Sparc_V9FMOVD_FCC - 541
2348
33.6k
    {6596, 2179, 5, 6 },
2349
33.6k
    {6614, 2185, 5, 6 },
2350
33.6k
    {6632, 2191, 5, 6 },
2351
33.6k
    {6650, 2197, 5, 6 },
2352
33.6k
    {6668, 2203, 5, 6 },
2353
33.6k
    {6687, 2209, 5, 6 },
2354
33.6k
    {6705, 2215, 5, 6 },
2355
33.6k
    {6724, 2221, 5, 6 },
2356
33.6k
    {6743, 2227, 5, 6 },
2357
33.6k
    {6762, 2233, 5, 6 },
2358
33.6k
    {6780, 2239, 5, 6 },
2359
33.6k
    {6799, 2245, 5, 6 },
2360
33.6k
    {6818, 2251, 5, 6 },
2361
33.6k
    {6838, 2257, 5, 6 },
2362
33.6k
    {6857, 2263, 5, 6 },
2363
33.6k
    {6877, 2269, 5, 6 },
2364
    // Sparc_V9FMOVQ_FCC - 557
2365
33.6k
    {6895, 2275, 5, 6 },
2366
33.6k
    {6913, 2281, 5, 6 },
2367
33.6k
    {6931, 2287, 5, 6 },
2368
33.6k
    {6949, 2293, 5, 6 },
2369
33.6k
    {6967, 2299, 5, 6 },
2370
33.6k
    {6986, 2305, 5, 6 },
2371
33.6k
    {7004, 2311, 5, 6 },
2372
33.6k
    {7023, 2317, 5, 6 },
2373
33.6k
    {7042, 2323, 5, 6 },
2374
33.6k
    {7061, 2329, 5, 6 },
2375
33.6k
    {7079, 2335, 5, 6 },
2376
33.6k
    {7098, 2341, 5, 6 },
2377
33.6k
    {7117, 2347, 5, 6 },
2378
33.6k
    {7137, 2353, 5, 6 },
2379
33.6k
    {7156, 2359, 5, 6 },
2380
33.6k
    {7176, 2365, 5, 6 },
2381
    // Sparc_V9FMOVS_FCC - 573
2382
33.6k
    {7194, 2371, 5, 6 },
2383
33.6k
    {7212, 2377, 5, 6 },
2384
33.6k
    {7230, 2383, 5, 6 },
2385
33.6k
    {7248, 2389, 5, 6 },
2386
33.6k
    {7266, 2395, 5, 6 },
2387
33.6k
    {7285, 2401, 5, 6 },
2388
33.6k
    {7303, 2407, 5, 6 },
2389
33.6k
    {7322, 2413, 5, 6 },
2390
33.6k
    {7341, 2419, 5, 6 },
2391
33.6k
    {7360, 2425, 5, 6 },
2392
33.6k
    {7378, 2431, 5, 6 },
2393
33.6k
    {7397, 2437, 5, 6 },
2394
33.6k
    {7416, 2443, 5, 6 },
2395
33.6k
    {7436, 2449, 5, 6 },
2396
33.6k
    {7455, 2455, 5, 6 },
2397
33.6k
    {7475, 2461, 5, 6 },
2398
    // Sparc_V9MOVFCCri - 589
2399
33.6k
    {7493, 2467, 5, 6 },
2400
33.6k
    {7509, 2473, 5, 6 },
2401
33.6k
    {7525, 2479, 5, 6 },
2402
33.6k
    {7541, 2485, 5, 6 },
2403
33.6k
    {7557, 2491, 5, 6 },
2404
33.6k
    {7574, 2497, 5, 6 },
2405
33.6k
    {7590, 2503, 5, 6 },
2406
33.6k
    {7607, 2509, 5, 6 },
2407
33.6k
    {7624, 2515, 5, 6 },
2408
33.6k
    {7641, 2521, 5, 6 },
2409
33.6k
    {7657, 2527, 5, 6 },
2410
33.6k
    {7674, 2533, 5, 6 },
2411
33.6k
    {7691, 2539, 5, 6 },
2412
33.6k
    {7709, 2545, 5, 6 },
2413
33.6k
    {7726, 2551, 5, 6 },
2414
33.6k
    {7744, 2557, 5, 6 },
2415
    // Sparc_V9MOVFCCrr - 605
2416
33.6k
    {7493, 2563, 5, 6 },
2417
33.6k
    {7509, 2569, 5, 6 },
2418
33.6k
    {7525, 2575, 5, 6 },
2419
33.6k
    {7541, 2581, 5, 6 },
2420
33.6k
    {7557, 2587, 5, 6 },
2421
33.6k
    {7574, 2593, 5, 6 },
2422
33.6k
    {7590, 2599, 5, 6 },
2423
33.6k
    {7607, 2605, 5, 6 },
2424
33.6k
    {7624, 2611, 5, 6 },
2425
33.6k
    {7641, 2617, 5, 6 },
2426
33.6k
    {7657, 2623, 5, 6 },
2427
33.6k
    {7674, 2629, 5, 6 },
2428
33.6k
    {7691, 2635, 5, 6 },
2429
33.6k
    {7709, 2641, 5, 6 },
2430
33.6k
    {7726, 2647, 5, 6 },
2431
33.6k
    {7744, 2653, 5, 6 },
2432
33.6k
  {0},  };
2433
2434
33.6k
  static const AliasPatternCond Conds[] = {
2435
    // (BCOND brtarget:$imm, 8) - 0
2436
33.6k
    {AliasPatternCond_K_Ignore, 0},
2437
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2438
    // (BCOND brtarget:$imm, 0) - 2
2439
33.6k
    {AliasPatternCond_K_Ignore, 0},
2440
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2441
    // (BCOND brtarget:$imm, 9) - 4
2442
33.6k
    {AliasPatternCond_K_Ignore, 0},
2443
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2444
    // (BCOND brtarget:$imm, 1) - 6
2445
33.6k
    {AliasPatternCond_K_Ignore, 0},
2446
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2447
    // (BCOND brtarget:$imm, 10) - 8
2448
33.6k
    {AliasPatternCond_K_Ignore, 0},
2449
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2450
    // (BCOND brtarget:$imm, 2) - 10
2451
33.6k
    {AliasPatternCond_K_Ignore, 0},
2452
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2453
    // (BCOND brtarget:$imm, 11) - 12
2454
33.6k
    {AliasPatternCond_K_Ignore, 0},
2455
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2456
    // (BCOND brtarget:$imm, 3) - 14
2457
33.6k
    {AliasPatternCond_K_Ignore, 0},
2458
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2459
    // (BCOND brtarget:$imm, 12) - 16
2460
33.6k
    {AliasPatternCond_K_Ignore, 0},
2461
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2462
    // (BCOND brtarget:$imm, 4) - 18
2463
33.6k
    {AliasPatternCond_K_Ignore, 0},
2464
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2465
    // (BCOND brtarget:$imm, 13) - 20
2466
33.6k
    {AliasPatternCond_K_Ignore, 0},
2467
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2468
    // (BCOND brtarget:$imm, 5) - 22
2469
33.6k
    {AliasPatternCond_K_Ignore, 0},
2470
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2471
    // (BCOND brtarget:$imm, 14) - 24
2472
33.6k
    {AliasPatternCond_K_Ignore, 0},
2473
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2474
    // (BCOND brtarget:$imm, 6) - 26
2475
33.6k
    {AliasPatternCond_K_Ignore, 0},
2476
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2477
    // (BCOND brtarget:$imm, 15) - 28
2478
33.6k
    {AliasPatternCond_K_Ignore, 0},
2479
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2480
    // (BCOND brtarget:$imm, 7) - 30
2481
33.6k
    {AliasPatternCond_K_Ignore, 0},
2482
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2483
    // (BCONDA brtarget:$imm, 8) - 32
2484
33.6k
    {AliasPatternCond_K_Ignore, 0},
2485
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2486
    // (BCONDA brtarget:$imm, 0) - 34
2487
33.6k
    {AliasPatternCond_K_Ignore, 0},
2488
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2489
    // (BCONDA brtarget:$imm, 9) - 36
2490
33.6k
    {AliasPatternCond_K_Ignore, 0},
2491
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2492
    // (BCONDA brtarget:$imm, 1) - 38
2493
33.6k
    {AliasPatternCond_K_Ignore, 0},
2494
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2495
    // (BCONDA brtarget:$imm, 10) - 40
2496
33.6k
    {AliasPatternCond_K_Ignore, 0},
2497
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2498
    // (BCONDA brtarget:$imm, 2) - 42
2499
33.6k
    {AliasPatternCond_K_Ignore, 0},
2500
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2501
    // (BCONDA brtarget:$imm, 11) - 44
2502
33.6k
    {AliasPatternCond_K_Ignore, 0},
2503
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2504
    // (BCONDA brtarget:$imm, 3) - 46
2505
33.6k
    {AliasPatternCond_K_Ignore, 0},
2506
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2507
    // (BCONDA brtarget:$imm, 12) - 48
2508
33.6k
    {AliasPatternCond_K_Ignore, 0},
2509
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2510
    // (BCONDA brtarget:$imm, 4) - 50
2511
33.6k
    {AliasPatternCond_K_Ignore, 0},
2512
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2513
    // (BCONDA brtarget:$imm, 13) - 52
2514
33.6k
    {AliasPatternCond_K_Ignore, 0},
2515
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2516
    // (BCONDA brtarget:$imm, 5) - 54
2517
33.6k
    {AliasPatternCond_K_Ignore, 0},
2518
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2519
    // (BCONDA brtarget:$imm, 14) - 56
2520
33.6k
    {AliasPatternCond_K_Ignore, 0},
2521
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2522
    // (BCONDA brtarget:$imm, 6) - 58
2523
33.6k
    {AliasPatternCond_K_Ignore, 0},
2524
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2525
    // (BCONDA brtarget:$imm, 15) - 60
2526
33.6k
    {AliasPatternCond_K_Ignore, 0},
2527
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2528
    // (BCONDA brtarget:$imm, 7) - 62
2529
33.6k
    {AliasPatternCond_K_Ignore, 0},
2530
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2531
    // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2532
33.6k
    {AliasPatternCond_K_Ignore, 0},
2533
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2534
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2535
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2536
    // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2537
33.6k
    {AliasPatternCond_K_Ignore, 0},
2538
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2539
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2540
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2541
    // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2542
33.6k
    {AliasPatternCond_K_Ignore, 0},
2543
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2544
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2545
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2546
    // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2547
33.6k
    {AliasPatternCond_K_Ignore, 0},
2548
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2549
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2550
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2551
    // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2552
33.6k
    {AliasPatternCond_K_Ignore, 0},
2553
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2554
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2555
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2556
    // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2557
33.6k
    {AliasPatternCond_K_Ignore, 0},
2558
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2559
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2560
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2561
    // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2562
33.6k
    {AliasPatternCond_K_Ignore, 0},
2563
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2564
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2565
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2566
    // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2567
33.6k
    {AliasPatternCond_K_Ignore, 0},
2568
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2569
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2570
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2571
    // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2572
33.6k
    {AliasPatternCond_K_Ignore, 0},
2573
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2574
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2575
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2576
    // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2577
33.6k
    {AliasPatternCond_K_Ignore, 0},
2578
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2579
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2580
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2581
    // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2582
33.6k
    {AliasPatternCond_K_Ignore, 0},
2583
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2584
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2585
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2586
    // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2587
33.6k
    {AliasPatternCond_K_Ignore, 0},
2588
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2589
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2590
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2591
    // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2592
33.6k
    {AliasPatternCond_K_Ignore, 0},
2593
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2594
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2595
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2596
    // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2597
33.6k
    {AliasPatternCond_K_Ignore, 0},
2598
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2599
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2600
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2601
    // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2602
33.6k
    {AliasPatternCond_K_Ignore, 0},
2603
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2604
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2605
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2606
    // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2607
33.6k
    {AliasPatternCond_K_Ignore, 0},
2608
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2609
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2610
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2611
    // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2612
33.6k
    {AliasPatternCond_K_Ignore, 0},
2613
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2614
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2615
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2616
    // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
2617
33.6k
    {AliasPatternCond_K_Ignore, 0},
2618
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2619
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2620
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2621
    // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
2622
33.6k
    {AliasPatternCond_K_Ignore, 0},
2623
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2624
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2625
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2626
    // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
2627
33.6k
    {AliasPatternCond_K_Ignore, 0},
2628
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2629
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2630
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2631
    // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
2632
33.6k
    {AliasPatternCond_K_Ignore, 0},
2633
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2634
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2635
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2636
    // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
2637
33.6k
    {AliasPatternCond_K_Ignore, 0},
2638
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2639
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2640
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2641
    // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
2642
33.6k
    {AliasPatternCond_K_Ignore, 0},
2643
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2644
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2645
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2646
    // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
2647
33.6k
    {AliasPatternCond_K_Ignore, 0},
2648
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2649
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2650
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2651
    // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
2652
33.6k
    {AliasPatternCond_K_Ignore, 0},
2653
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2654
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2655
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2656
    // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
2657
33.6k
    {AliasPatternCond_K_Ignore, 0},
2658
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2659
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2660
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2661
    // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
2662
33.6k
    {AliasPatternCond_K_Ignore, 0},
2663
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2664
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2665
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2666
    // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
2667
33.6k
    {AliasPatternCond_K_Ignore, 0},
2668
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2669
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2670
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2671
    // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
2672
33.6k
    {AliasPatternCond_K_Ignore, 0},
2673
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2674
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2675
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2676
    // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
2677
33.6k
    {AliasPatternCond_K_Ignore, 0},
2678
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2679
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2680
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2681
    // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
2682
33.6k
    {AliasPatternCond_K_Ignore, 0},
2683
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2684
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2685
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2686
    // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
2687
33.6k
    {AliasPatternCond_K_Ignore, 0},
2688
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2689
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
2690
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2691
    // (BPICCANT brtarget:$imm, 8) - 192
2692
33.6k
    {AliasPatternCond_K_Ignore, 0},
2693
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2694
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2695
    // (BPICCANT brtarget:$imm, 0) - 195
2696
33.6k
    {AliasPatternCond_K_Ignore, 0},
2697
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2698
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2699
    // (BPICCANT brtarget:$imm, 9) - 198
2700
33.6k
    {AliasPatternCond_K_Ignore, 0},
2701
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2702
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2703
    // (BPICCANT brtarget:$imm, 1) - 201
2704
33.6k
    {AliasPatternCond_K_Ignore, 0},
2705
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2706
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2707
    // (BPICCANT brtarget:$imm, 10) - 204
2708
33.6k
    {AliasPatternCond_K_Ignore, 0},
2709
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2710
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2711
    // (BPICCANT brtarget:$imm, 2) - 207
2712
33.6k
    {AliasPatternCond_K_Ignore, 0},
2713
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2714
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2715
    // (BPICCANT brtarget:$imm, 11) - 210
2716
33.6k
    {AliasPatternCond_K_Ignore, 0},
2717
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2718
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2719
    // (BPICCANT brtarget:$imm, 3) - 213
2720
33.6k
    {AliasPatternCond_K_Ignore, 0},
2721
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2722
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2723
    // (BPICCANT brtarget:$imm, 12) - 216
2724
33.6k
    {AliasPatternCond_K_Ignore, 0},
2725
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2726
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2727
    // (BPICCANT brtarget:$imm, 4) - 219
2728
33.6k
    {AliasPatternCond_K_Ignore, 0},
2729
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2730
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2731
    // (BPICCANT brtarget:$imm, 13) - 222
2732
33.6k
    {AliasPatternCond_K_Ignore, 0},
2733
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2734
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2735
    // (BPICCANT brtarget:$imm, 5) - 225
2736
33.6k
    {AliasPatternCond_K_Ignore, 0},
2737
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2738
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2739
    // (BPICCANT brtarget:$imm, 14) - 228
2740
33.6k
    {AliasPatternCond_K_Ignore, 0},
2741
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2742
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2743
    // (BPICCANT brtarget:$imm, 6) - 231
2744
33.6k
    {AliasPatternCond_K_Ignore, 0},
2745
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2746
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2747
    // (BPICCANT brtarget:$imm, 15) - 234
2748
33.6k
    {AliasPatternCond_K_Ignore, 0},
2749
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2750
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2751
    // (BPICCANT brtarget:$imm, 7) - 237
2752
33.6k
    {AliasPatternCond_K_Ignore, 0},
2753
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2754
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2755
    // (BPICCNT brtarget:$imm, 8) - 240
2756
33.6k
    {AliasPatternCond_K_Ignore, 0},
2757
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2758
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2759
    // (BPICCNT brtarget:$imm, 0) - 243
2760
33.6k
    {AliasPatternCond_K_Ignore, 0},
2761
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2762
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2763
    // (BPICCNT brtarget:$imm, 9) - 246
2764
33.6k
    {AliasPatternCond_K_Ignore, 0},
2765
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2766
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2767
    // (BPICCNT brtarget:$imm, 1) - 249
2768
33.6k
    {AliasPatternCond_K_Ignore, 0},
2769
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2770
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2771
    // (BPICCNT brtarget:$imm, 10) - 252
2772
33.6k
    {AliasPatternCond_K_Ignore, 0},
2773
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2774
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2775
    // (BPICCNT brtarget:$imm, 2) - 255
2776
33.6k
    {AliasPatternCond_K_Ignore, 0},
2777
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2778
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2779
    // (BPICCNT brtarget:$imm, 11) - 258
2780
33.6k
    {AliasPatternCond_K_Ignore, 0},
2781
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2782
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2783
    // (BPICCNT brtarget:$imm, 3) - 261
2784
33.6k
    {AliasPatternCond_K_Ignore, 0},
2785
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2786
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2787
    // (BPICCNT brtarget:$imm, 12) - 264
2788
33.6k
    {AliasPatternCond_K_Ignore, 0},
2789
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2790
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2791
    // (BPICCNT brtarget:$imm, 4) - 267
2792
33.6k
    {AliasPatternCond_K_Ignore, 0},
2793
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2794
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2795
    // (BPICCNT brtarget:$imm, 13) - 270
2796
33.6k
    {AliasPatternCond_K_Ignore, 0},
2797
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2798
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2799
    // (BPICCNT brtarget:$imm, 5) - 273
2800
33.6k
    {AliasPatternCond_K_Ignore, 0},
2801
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2802
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2803
    // (BPICCNT brtarget:$imm, 14) - 276
2804
33.6k
    {AliasPatternCond_K_Ignore, 0},
2805
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2806
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2807
    // (BPICCNT brtarget:$imm, 6) - 279
2808
33.6k
    {AliasPatternCond_K_Ignore, 0},
2809
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2810
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2811
    // (BPICCNT brtarget:$imm, 15) - 282
2812
33.6k
    {AliasPatternCond_K_Ignore, 0},
2813
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2814
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2815
    // (BPICCNT brtarget:$imm, 7) - 285
2816
33.6k
    {AliasPatternCond_K_Ignore, 0},
2817
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2818
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2819
    // (BPRANT bprtarget16:$imm, 1, I64Regs:$rs1) - 288
2820
33.6k
    {AliasPatternCond_K_Ignore, 0},
2821
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2822
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2823
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2824
    // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 292
2825
33.6k
    {AliasPatternCond_K_Ignore, 0},
2826
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2827
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2828
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2829
    // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 296
2830
33.6k
    {AliasPatternCond_K_Ignore, 0},
2831
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2832
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2833
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2834
    // (BPRANT bprtarget16:$imm, 5, I64Regs:$rs1) - 300
2835
33.6k
    {AliasPatternCond_K_Ignore, 0},
2836
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2837
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2838
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2839
    // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 304
2840
33.6k
    {AliasPatternCond_K_Ignore, 0},
2841
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2842
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2843
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2844
    // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 308
2845
33.6k
    {AliasPatternCond_K_Ignore, 0},
2846
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2847
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2848
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2849
    // (BPRNT bprtarget16:$imm, 1, I64Regs:$rs1) - 312
2850
33.6k
    {AliasPatternCond_K_Ignore, 0},
2851
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2852
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2853
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2854
    // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 316
2855
33.6k
    {AliasPatternCond_K_Ignore, 0},
2856
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2857
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2858
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2859
    // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 320
2860
33.6k
    {AliasPatternCond_K_Ignore, 0},
2861
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2862
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2863
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2864
    // (BPRNT bprtarget16:$imm, 5, I64Regs:$rs1) - 324
2865
33.6k
    {AliasPatternCond_K_Ignore, 0},
2866
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2867
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2868
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2869
    // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 328
2870
33.6k
    {AliasPatternCond_K_Ignore, 0},
2871
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2872
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2873
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2874
    // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 332
2875
33.6k
    {AliasPatternCond_K_Ignore, 0},
2876
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2877
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
2878
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2879
    // (BPXCCANT brtarget:$imm, 8) - 336
2880
33.6k
    {AliasPatternCond_K_Ignore, 0},
2881
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2882
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2883
    // (BPXCCANT brtarget:$imm, 0) - 339
2884
33.6k
    {AliasPatternCond_K_Ignore, 0},
2885
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2886
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2887
    // (BPXCCANT brtarget:$imm, 9) - 342
2888
33.6k
    {AliasPatternCond_K_Ignore, 0},
2889
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2890
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2891
    // (BPXCCANT brtarget:$imm, 1) - 345
2892
33.6k
    {AliasPatternCond_K_Ignore, 0},
2893
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2894
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2895
    // (BPXCCANT brtarget:$imm, 10) - 348
2896
33.6k
    {AliasPatternCond_K_Ignore, 0},
2897
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2898
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2899
    // (BPXCCANT brtarget:$imm, 2) - 351
2900
33.6k
    {AliasPatternCond_K_Ignore, 0},
2901
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2902
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2903
    // (BPXCCANT brtarget:$imm, 11) - 354
2904
33.6k
    {AliasPatternCond_K_Ignore, 0},
2905
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2906
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2907
    // (BPXCCANT brtarget:$imm, 3) - 357
2908
33.6k
    {AliasPatternCond_K_Ignore, 0},
2909
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2910
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2911
    // (BPXCCANT brtarget:$imm, 12) - 360
2912
33.6k
    {AliasPatternCond_K_Ignore, 0},
2913
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2914
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2915
    // (BPXCCANT brtarget:$imm, 4) - 363
2916
33.6k
    {AliasPatternCond_K_Ignore, 0},
2917
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2918
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2919
    // (BPXCCANT brtarget:$imm, 13) - 366
2920
33.6k
    {AliasPatternCond_K_Ignore, 0},
2921
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2922
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2923
    // (BPXCCANT brtarget:$imm, 5) - 369
2924
33.6k
    {AliasPatternCond_K_Ignore, 0},
2925
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2926
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2927
    // (BPXCCANT brtarget:$imm, 14) - 372
2928
33.6k
    {AliasPatternCond_K_Ignore, 0},
2929
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2930
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2931
    // (BPXCCANT brtarget:$imm, 6) - 375
2932
33.6k
    {AliasPatternCond_K_Ignore, 0},
2933
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2934
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2935
    // (BPXCCANT brtarget:$imm, 15) - 378
2936
33.6k
    {AliasPatternCond_K_Ignore, 0},
2937
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
2938
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2939
    // (BPXCCANT brtarget:$imm, 7) - 381
2940
33.6k
    {AliasPatternCond_K_Ignore, 0},
2941
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
2942
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2943
    // (BPXCCNT brtarget:$imm, 8) - 384
2944
33.6k
    {AliasPatternCond_K_Ignore, 0},
2945
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
2946
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2947
    // (BPXCCNT brtarget:$imm, 0) - 387
2948
33.6k
    {AliasPatternCond_K_Ignore, 0},
2949
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
2950
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2951
    // (BPXCCNT brtarget:$imm, 9) - 390
2952
33.6k
    {AliasPatternCond_K_Ignore, 0},
2953
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
2954
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2955
    // (BPXCCNT brtarget:$imm, 1) - 393
2956
33.6k
    {AliasPatternCond_K_Ignore, 0},
2957
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
2958
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2959
    // (BPXCCNT brtarget:$imm, 10) - 396
2960
33.6k
    {AliasPatternCond_K_Ignore, 0},
2961
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
2962
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2963
    // (BPXCCNT brtarget:$imm, 2) - 399
2964
33.6k
    {AliasPatternCond_K_Ignore, 0},
2965
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
2966
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2967
    // (BPXCCNT brtarget:$imm, 11) - 402
2968
33.6k
    {AliasPatternCond_K_Ignore, 0},
2969
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
2970
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2971
    // (BPXCCNT brtarget:$imm, 3) - 405
2972
33.6k
    {AliasPatternCond_K_Ignore, 0},
2973
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
2974
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2975
    // (BPXCCNT brtarget:$imm, 12) - 408
2976
33.6k
    {AliasPatternCond_K_Ignore, 0},
2977
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
2978
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2979
    // (BPXCCNT brtarget:$imm, 4) - 411
2980
33.6k
    {AliasPatternCond_K_Ignore, 0},
2981
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
2982
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2983
    // (BPXCCNT brtarget:$imm, 13) - 414
2984
33.6k
    {AliasPatternCond_K_Ignore, 0},
2985
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
2986
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2987
    // (BPXCCNT brtarget:$imm, 5) - 417
2988
33.6k
    {AliasPatternCond_K_Ignore, 0},
2989
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
2990
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2991
    // (BPXCCNT brtarget:$imm, 14) - 420
2992
33.6k
    {AliasPatternCond_K_Ignore, 0},
2993
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
2994
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2995
    // (BPXCCNT brtarget:$imm, 6) - 423
2996
33.6k
    {AliasPatternCond_K_Ignore, 0},
2997
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
2998
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
2999
    // (BPXCCNT brtarget:$imm, 15) - 426
3000
33.6k
    {AliasPatternCond_K_Ignore, 0},
3001
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3002
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3003
    // (BPXCCNT brtarget:$imm, 7) - 429
3004
33.6k
    {AliasPatternCond_K_Ignore, 0},
3005
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3006
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3007
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 432
3008
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3009
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3010
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3011
33.6k
    {AliasPatternCond_K_Ignore, 0},
3012
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)128},
3013
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3014
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 438
3015
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3016
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3017
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3018
33.6k
    {AliasPatternCond_K_Ignore, 0},
3019
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)136},
3020
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3021
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 444
3022
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3023
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3024
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3025
33.6k
    {AliasPatternCond_K_Ignore, 0},
3026
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)128},
3027
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3028
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 450
3029
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3030
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3031
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3032
33.6k
    {AliasPatternCond_K_Ignore, 0},
3033
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)136},
3034
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3035
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 456
3036
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3037
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3038
33.6k
    {AliasPatternCond_K_Ignore, 0},
3039
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3040
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3041
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 461
3042
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3043
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3044
33.6k
    {AliasPatternCond_K_Ignore, 0},
3045
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3046
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3047
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 466
3048
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3049
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3050
33.6k
    {AliasPatternCond_K_Ignore, 0},
3051
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3052
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3053
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 471
3054
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3055
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3056
33.6k
    {AliasPatternCond_K_Ignore, 0},
3057
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3058
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3059
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 476
3060
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3061
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3062
33.6k
    {AliasPatternCond_K_Ignore, 0},
3063
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3064
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3065
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 481
3066
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3067
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3068
33.6k
    {AliasPatternCond_K_Ignore, 0},
3069
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3070
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3071
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 486
3072
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3073
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3074
33.6k
    {AliasPatternCond_K_Ignore, 0},
3075
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3076
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3077
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 491
3078
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3079
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3080
33.6k
    {AliasPatternCond_K_Ignore, 0},
3081
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3082
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3083
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 496
3084
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3085
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3086
33.6k
    {AliasPatternCond_K_Ignore, 0},
3087
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3088
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3089
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 501
3090
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3091
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3092
33.6k
    {AliasPatternCond_K_Ignore, 0},
3093
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3094
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3095
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 506
3096
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3097
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3098
33.6k
    {AliasPatternCond_K_Ignore, 0},
3099
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3100
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3101
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 511
3102
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3103
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3104
33.6k
    {AliasPatternCond_K_Ignore, 0},
3105
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3106
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3107
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 516
3108
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3109
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3110
33.6k
    {AliasPatternCond_K_Ignore, 0},
3111
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3112
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3113
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 521
3114
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3115
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3116
33.6k
    {AliasPatternCond_K_Ignore, 0},
3117
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3118
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3119
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 526
3120
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3121
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3122
33.6k
    {AliasPatternCond_K_Ignore, 0},
3123
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3124
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3125
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 531
3126
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3127
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3128
33.6k
    {AliasPatternCond_K_Ignore, 0},
3129
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3130
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3131
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 536
3132
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3133
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3134
33.6k
    {AliasPatternCond_K_Ignore, 0},
3135
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3136
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3137
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 541
3138
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3139
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3140
33.6k
    {AliasPatternCond_K_Ignore, 0},
3141
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3142
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3143
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 546
3144
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3145
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3146
33.6k
    {AliasPatternCond_K_Ignore, 0},
3147
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3148
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3149
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 551
3150
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3151
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3152
33.6k
    {AliasPatternCond_K_Ignore, 0},
3153
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3154
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3155
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 556
3156
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3157
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3158
33.6k
    {AliasPatternCond_K_Ignore, 0},
3159
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3160
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3161
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 561
3162
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3163
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3164
33.6k
    {AliasPatternCond_K_Ignore, 0},
3165
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3166
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3167
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 566
3168
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3169
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3170
33.6k
    {AliasPatternCond_K_Ignore, 0},
3171
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3172
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3173
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 571
3174
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3175
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3176
33.6k
    {AliasPatternCond_K_Ignore, 0},
3177
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3178
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3179
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 576
3180
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3181
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3182
33.6k
    {AliasPatternCond_K_Ignore, 0},
3183
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3184
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3185
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 581
3186
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3187
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3188
33.6k
    {AliasPatternCond_K_Ignore, 0},
3189
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3190
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3191
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 586
3192
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3193
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3194
33.6k
    {AliasPatternCond_K_Ignore, 0},
3195
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3196
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3197
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 591
3198
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3199
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3200
33.6k
    {AliasPatternCond_K_Ignore, 0},
3201
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3202
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3203
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 596
3204
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3205
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3206
33.6k
    {AliasPatternCond_K_Ignore, 0},
3207
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3208
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3209
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 601
3210
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3211
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3212
33.6k
    {AliasPatternCond_K_Ignore, 0},
3213
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3214
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3215
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 606
3216
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3217
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3218
33.6k
    {AliasPatternCond_K_Ignore, 0},
3219
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3220
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3221
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 611
3222
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3223
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3224
33.6k
    {AliasPatternCond_K_Ignore, 0},
3225
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3226
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3227
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 616
3228
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3229
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3230
33.6k
    {AliasPatternCond_K_Ignore, 0},
3231
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3232
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3233
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 621
3234
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3235
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3236
33.6k
    {AliasPatternCond_K_Ignore, 0},
3237
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3238
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3239
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 626
3240
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3241
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3242
33.6k
    {AliasPatternCond_K_Ignore, 0},
3243
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3244
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3245
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 631
3246
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3247
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3248
33.6k
    {AliasPatternCond_K_Ignore, 0},
3249
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3250
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3251
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 636
3252
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3253
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3254
33.6k
    {AliasPatternCond_K_Ignore, 0},
3255
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3256
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3257
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 641
3258
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3259
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3260
33.6k
    {AliasPatternCond_K_Ignore, 0},
3261
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3262
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3263
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 646
3264
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3265
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3266
33.6k
    {AliasPatternCond_K_Ignore, 0},
3267
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3268
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3269
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 651
3270
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3271
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3272
33.6k
    {AliasPatternCond_K_Ignore, 0},
3273
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3274
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3275
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 656
3276
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3277
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3278
33.6k
    {AliasPatternCond_K_Ignore, 0},
3279
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3280
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3281
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 661
3282
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3283
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3284
33.6k
    {AliasPatternCond_K_Ignore, 0},
3285
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3286
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3287
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 666
3288
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3289
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3290
33.6k
    {AliasPatternCond_K_Ignore, 0},
3291
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3292
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3293
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 671
3294
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3295
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3296
33.6k
    {AliasPatternCond_K_Ignore, 0},
3297
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3298
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3299
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 676
3300
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3301
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3302
33.6k
    {AliasPatternCond_K_Ignore, 0},
3303
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3304
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3305
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 681
3306
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3307
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3308
33.6k
    {AliasPatternCond_K_Ignore, 0},
3309
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3310
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3311
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 686
3312
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3313
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3314
33.6k
    {AliasPatternCond_K_Ignore, 0},
3315
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3316
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3317
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 691
3318
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3319
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3320
33.6k
    {AliasPatternCond_K_Ignore, 0},
3321
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3322
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3323
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 696
3324
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3325
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3326
33.6k
    {AliasPatternCond_K_Ignore, 0},
3327
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3328
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3329
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 701
3330
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3331
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3332
33.6k
    {AliasPatternCond_K_Ignore, 0},
3333
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3334
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3335
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 706
3336
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3337
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3338
33.6k
    {AliasPatternCond_K_Ignore, 0},
3339
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3340
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3341
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 711
3342
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3343
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3344
33.6k
    {AliasPatternCond_K_Ignore, 0},
3345
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3346
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3347
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 716
3348
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3349
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3350
33.6k
    {AliasPatternCond_K_Ignore, 0},
3351
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3352
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3353
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 721
3354
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3355
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3356
33.6k
    {AliasPatternCond_K_Ignore, 0},
3357
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3358
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3359
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 726
3360
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3361
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3362
33.6k
    {AliasPatternCond_K_Ignore, 0},
3363
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3364
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3365
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 731
3366
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3367
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3368
33.6k
    {AliasPatternCond_K_Ignore, 0},
3369
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3370
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3371
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 736
3372
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3373
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3374
33.6k
    {AliasPatternCond_K_Ignore, 0},
3375
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3376
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3377
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 741
3378
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3379
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3380
33.6k
    {AliasPatternCond_K_Ignore, 0},
3381
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3382
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3383
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 746
3384
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3385
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3386
33.6k
    {AliasPatternCond_K_Ignore, 0},
3387
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3388
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3389
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 751
3390
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3391
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3392
33.6k
    {AliasPatternCond_K_Ignore, 0},
3393
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3394
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3395
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 756
3396
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3397
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3398
33.6k
    {AliasPatternCond_K_Ignore, 0},
3399
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3400
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3401
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 761
3402
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3403
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3404
33.6k
    {AliasPatternCond_K_Ignore, 0},
3405
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3406
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3407
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 766
3408
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3409
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3410
33.6k
    {AliasPatternCond_K_Ignore, 0},
3411
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3412
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3413
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 771
3414
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3415
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3416
33.6k
    {AliasPatternCond_K_Ignore, 0},
3417
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3418
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3419
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 1) - 776
3420
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3421
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3422
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3423
33.6k
    {AliasPatternCond_K_Ignore, 0},
3424
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3425
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3426
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 782
3427
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3428
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3429
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3430
33.6k
    {AliasPatternCond_K_Ignore, 0},
3431
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3432
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3433
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 788
3434
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3435
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3436
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3437
33.6k
    {AliasPatternCond_K_Ignore, 0},
3438
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3439
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3440
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 5) - 794
3441
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3442
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3443
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3444
33.6k
    {AliasPatternCond_K_Ignore, 0},
3445
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3446
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3447
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 800
3448
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3449
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3450
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3451
33.6k
    {AliasPatternCond_K_Ignore, 0},
3452
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3453
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3454
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 806
3455
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3456
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3457
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
3458
33.6k
    {AliasPatternCond_K_Ignore, 0},
3459
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3460
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3461
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 1) - 812
3462
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3463
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3464
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3465
33.6k
    {AliasPatternCond_K_Ignore, 0},
3466
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3467
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3468
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 818
3469
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3470
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3471
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3472
33.6k
    {AliasPatternCond_K_Ignore, 0},
3473
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3474
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3475
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 824
3476
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3477
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3478
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3479
33.6k
    {AliasPatternCond_K_Ignore, 0},
3480
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3481
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3482
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 5) - 830
3483
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3484
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3485
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3486
33.6k
    {AliasPatternCond_K_Ignore, 0},
3487
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3488
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3489
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 836
3490
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3491
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3492
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3493
33.6k
    {AliasPatternCond_K_Ignore, 0},
3494
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3495
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3496
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 842
3497
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3498
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3499
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
3500
33.6k
    {AliasPatternCond_K_Ignore, 0},
3501
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3502
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3503
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 1) - 848
3504
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3505
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3506
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3507
33.6k
    {AliasPatternCond_K_Ignore, 0},
3508
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3509
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3510
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 854
3511
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3512
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3513
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3514
33.6k
    {AliasPatternCond_K_Ignore, 0},
3515
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3516
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3517
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 860
3518
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3519
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3520
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3521
33.6k
    {AliasPatternCond_K_Ignore, 0},
3522
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3523
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3524
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 5) - 866
3525
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3526
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3527
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3528
33.6k
    {AliasPatternCond_K_Ignore, 0},
3529
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3530
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3531
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 872
3532
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3533
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3534
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3535
33.6k
    {AliasPatternCond_K_Ignore, 0},
3536
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3537
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3538
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 878
3539
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3540
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3541
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3542
33.6k
    {AliasPatternCond_K_Ignore, 0},
3543
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3544
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3545
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 884
3546
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3547
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3548
33.6k
    {AliasPatternCond_K_Ignore, 0},
3549
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3550
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3551
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 889
3552
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3553
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3554
33.6k
    {AliasPatternCond_K_Ignore, 0},
3555
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3556
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3557
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 894
3558
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3559
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3560
33.6k
    {AliasPatternCond_K_Ignore, 0},
3561
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3562
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3563
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 899
3564
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3565
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3566
33.6k
    {AliasPatternCond_K_Ignore, 0},
3567
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3568
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3569
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 904
3570
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3571
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3572
33.6k
    {AliasPatternCond_K_Ignore, 0},
3573
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3574
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3575
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 909
3576
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3577
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3578
33.6k
    {AliasPatternCond_K_Ignore, 0},
3579
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3580
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3581
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 914
3582
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3583
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3584
33.6k
    {AliasPatternCond_K_Ignore, 0},
3585
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3586
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3587
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 919
3588
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3589
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3590
33.6k
    {AliasPatternCond_K_Ignore, 0},
3591
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3592
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3593
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 924
3594
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3595
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3596
33.6k
    {AliasPatternCond_K_Ignore, 0},
3597
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3598
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3599
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 929
3600
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3601
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3602
33.6k
    {AliasPatternCond_K_Ignore, 0},
3603
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3604
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3605
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 934
3606
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3607
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3608
33.6k
    {AliasPatternCond_K_Ignore, 0},
3609
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3610
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3611
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 939
3612
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3613
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3614
33.6k
    {AliasPatternCond_K_Ignore, 0},
3615
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3616
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3617
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 944
3618
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3619
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3620
33.6k
    {AliasPatternCond_K_Ignore, 0},
3621
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3622
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3623
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 949
3624
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3625
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3626
33.6k
    {AliasPatternCond_K_Ignore, 0},
3627
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3628
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3629
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 954
3630
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3631
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3632
33.6k
    {AliasPatternCond_K_Ignore, 0},
3633
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3634
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3635
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 959
3636
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3637
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3638
33.6k
    {AliasPatternCond_K_Ignore, 0},
3639
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3640
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3641
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 964
3642
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3643
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3644
33.6k
    {AliasPatternCond_K_Ignore, 0},
3645
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3646
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3647
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 969
3648
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3649
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3650
33.6k
    {AliasPatternCond_K_Ignore, 0},
3651
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3652
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3653
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 974
3654
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3655
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3656
33.6k
    {AliasPatternCond_K_Ignore, 0},
3657
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3658
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3659
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 979
3660
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3661
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3662
33.6k
    {AliasPatternCond_K_Ignore, 0},
3663
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3664
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3665
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 984
3666
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3667
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3668
33.6k
    {AliasPatternCond_K_Ignore, 0},
3669
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3670
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3671
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 989
3672
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3673
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3674
33.6k
    {AliasPatternCond_K_Ignore, 0},
3675
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3676
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3677
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 994
3678
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3679
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3680
33.6k
    {AliasPatternCond_K_Ignore, 0},
3681
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3682
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3683
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 999
3684
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3685
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3686
33.6k
    {AliasPatternCond_K_Ignore, 0},
3687
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3688
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3689
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 1004
3690
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3691
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3692
33.6k
    {AliasPatternCond_K_Ignore, 0},
3693
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3694
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3695
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 1009
3696
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3697
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3698
33.6k
    {AliasPatternCond_K_Ignore, 0},
3699
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3700
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3701
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 1014
3702
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3703
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3704
33.6k
    {AliasPatternCond_K_Ignore, 0},
3705
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3706
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3707
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 1019
3708
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3709
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3710
33.6k
    {AliasPatternCond_K_Ignore, 0},
3711
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3712
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3713
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 1024
3714
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3715
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3716
33.6k
    {AliasPatternCond_K_Ignore, 0},
3717
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3718
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3719
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 1029
3720
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3721
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3722
33.6k
    {AliasPatternCond_K_Ignore, 0},
3723
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3724
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3725
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 1034
3726
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3727
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3728
33.6k
    {AliasPatternCond_K_Ignore, 0},
3729
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3730
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3731
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 1039
3732
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3733
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
3734
33.6k
    {AliasPatternCond_K_Ignore, 0},
3735
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3736
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3737
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1044
3738
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3739
33.6k
    {AliasPatternCond_K_Ignore, 0},
3740
33.6k
    {AliasPatternCond_K_Ignore, 0},
3741
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3742
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3743
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1049
3744
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3745
33.6k
    {AliasPatternCond_K_Ignore, 0},
3746
33.6k
    {AliasPatternCond_K_Ignore, 0},
3747
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3748
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3749
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1054
3750
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3751
33.6k
    {AliasPatternCond_K_Ignore, 0},
3752
33.6k
    {AliasPatternCond_K_Ignore, 0},
3753
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3754
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3755
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1059
3756
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3757
33.6k
    {AliasPatternCond_K_Ignore, 0},
3758
33.6k
    {AliasPatternCond_K_Ignore, 0},
3759
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3760
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3761
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1064
3762
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3763
33.6k
    {AliasPatternCond_K_Ignore, 0},
3764
33.6k
    {AliasPatternCond_K_Ignore, 0},
3765
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3766
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3767
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1069
3768
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3769
33.6k
    {AliasPatternCond_K_Ignore, 0},
3770
33.6k
    {AliasPatternCond_K_Ignore, 0},
3771
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3772
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3773
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1074
3774
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3775
33.6k
    {AliasPatternCond_K_Ignore, 0},
3776
33.6k
    {AliasPatternCond_K_Ignore, 0},
3777
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3778
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3779
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1079
3780
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3781
33.6k
    {AliasPatternCond_K_Ignore, 0},
3782
33.6k
    {AliasPatternCond_K_Ignore, 0},
3783
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3784
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3785
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1084
3786
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3787
33.6k
    {AliasPatternCond_K_Ignore, 0},
3788
33.6k
    {AliasPatternCond_K_Ignore, 0},
3789
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3790
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3791
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1089
3792
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3793
33.6k
    {AliasPatternCond_K_Ignore, 0},
3794
33.6k
    {AliasPatternCond_K_Ignore, 0},
3795
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3796
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3797
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1094
3798
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3799
33.6k
    {AliasPatternCond_K_Ignore, 0},
3800
33.6k
    {AliasPatternCond_K_Ignore, 0},
3801
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3802
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3803
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1099
3804
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3805
33.6k
    {AliasPatternCond_K_Ignore, 0},
3806
33.6k
    {AliasPatternCond_K_Ignore, 0},
3807
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3808
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3809
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1104
3810
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3811
33.6k
    {AliasPatternCond_K_Ignore, 0},
3812
33.6k
    {AliasPatternCond_K_Ignore, 0},
3813
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3814
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3815
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1109
3816
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3817
33.6k
    {AliasPatternCond_K_Ignore, 0},
3818
33.6k
    {AliasPatternCond_K_Ignore, 0},
3819
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3820
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3821
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1114
3822
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3823
33.6k
    {AliasPatternCond_K_Ignore, 0},
3824
33.6k
    {AliasPatternCond_K_Ignore, 0},
3825
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3826
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3827
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1119
3828
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3829
33.6k
    {AliasPatternCond_K_Ignore, 0},
3830
33.6k
    {AliasPatternCond_K_Ignore, 0},
3831
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3832
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3833
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1124
3834
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3835
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3836
33.6k
    {AliasPatternCond_K_Ignore, 0},
3837
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
3838
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3839
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1129
3840
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3841
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3842
33.6k
    {AliasPatternCond_K_Ignore, 0},
3843
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
3844
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3845
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1134
3846
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3847
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3848
33.6k
    {AliasPatternCond_K_Ignore, 0},
3849
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
3850
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3851
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1139
3852
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3853
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3854
33.6k
    {AliasPatternCond_K_Ignore, 0},
3855
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3856
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3857
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1144
3858
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3859
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3860
33.6k
    {AliasPatternCond_K_Ignore, 0},
3861
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
3862
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3863
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1149
3864
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3865
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3866
33.6k
    {AliasPatternCond_K_Ignore, 0},
3867
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3868
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3869
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1154
3870
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3871
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3872
33.6k
    {AliasPatternCond_K_Ignore, 0},
3873
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
3874
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3875
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1159
3876
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3877
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3878
33.6k
    {AliasPatternCond_K_Ignore, 0},
3879
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3880
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3881
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1164
3882
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3883
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3884
33.6k
    {AliasPatternCond_K_Ignore, 0},
3885
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
3886
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3887
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1169
3888
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3889
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3890
33.6k
    {AliasPatternCond_K_Ignore, 0},
3891
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
3892
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3893
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1174
3894
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3895
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3896
33.6k
    {AliasPatternCond_K_Ignore, 0},
3897
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
3898
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3899
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1179
3900
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3901
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3902
33.6k
    {AliasPatternCond_K_Ignore, 0},
3903
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3904
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3905
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1184
3906
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3907
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3908
33.6k
    {AliasPatternCond_K_Ignore, 0},
3909
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
3910
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3911
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1189
3912
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3913
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3914
33.6k
    {AliasPatternCond_K_Ignore, 0},
3915
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3916
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3917
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1194
3918
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3919
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3920
33.6k
    {AliasPatternCond_K_Ignore, 0},
3921
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
3922
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3923
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1199
3924
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3925
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3926
33.6k
    {AliasPatternCond_K_Ignore, 0},
3927
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3928
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3929
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 1) - 1204
3930
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3931
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3932
33.6k
    {AliasPatternCond_K_Ignore, 0},
3933
33.6k
    {AliasPatternCond_K_Ignore, 0},
3934
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3935
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3936
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1210
3937
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3938
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3939
33.6k
    {AliasPatternCond_K_Ignore, 0},
3940
33.6k
    {AliasPatternCond_K_Ignore, 0},
3941
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3942
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3943
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1216
3944
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3945
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3946
33.6k
    {AliasPatternCond_K_Ignore, 0},
3947
33.6k
    {AliasPatternCond_K_Ignore, 0},
3948
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3949
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3950
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 5) - 1222
3951
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3952
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3953
33.6k
    {AliasPatternCond_K_Ignore, 0},
3954
33.6k
    {AliasPatternCond_K_Ignore, 0},
3955
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3956
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3957
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1228
3958
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3959
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3960
33.6k
    {AliasPatternCond_K_Ignore, 0},
3961
33.6k
    {AliasPatternCond_K_Ignore, 0},
3962
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
3963
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3964
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1234
3965
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3966
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3967
33.6k
    {AliasPatternCond_K_Ignore, 0},
3968
33.6k
    {AliasPatternCond_K_Ignore, 0},
3969
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
3970
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3971
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 1) - 1240
3972
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3973
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3974
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3975
33.6k
    {AliasPatternCond_K_Ignore, 0},
3976
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
3977
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3978
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1246
3979
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3980
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3981
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3982
33.6k
    {AliasPatternCond_K_Ignore, 0},
3983
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
3984
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3985
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1252
3986
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3987
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3988
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3989
33.6k
    {AliasPatternCond_K_Ignore, 0},
3990
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
3991
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3992
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 5) - 1258
3993
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3994
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
3995
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
3996
33.6k
    {AliasPatternCond_K_Ignore, 0},
3997
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
3998
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
3999
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1264
4000
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4001
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
4002
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4003
33.6k
    {AliasPatternCond_K_Ignore, 0},
4004
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4005
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4006
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1270
4007
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4008
33.6k
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
4009
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4010
33.6k
    {AliasPatternCond_K_Ignore, 0},
4011
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4012
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4013
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1276
4014
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4015
33.6k
    {AliasPatternCond_K_Ignore, 0},
4016
33.6k
    {AliasPatternCond_K_Ignore, 0},
4017
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4018
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4019
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1281
4020
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4021
33.6k
    {AliasPatternCond_K_Ignore, 0},
4022
33.6k
    {AliasPatternCond_K_Ignore, 0},
4023
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4024
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4025
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1286
4026
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4027
33.6k
    {AliasPatternCond_K_Ignore, 0},
4028
33.6k
    {AliasPatternCond_K_Ignore, 0},
4029
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4030
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4031
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1291
4032
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4033
33.6k
    {AliasPatternCond_K_Ignore, 0},
4034
33.6k
    {AliasPatternCond_K_Ignore, 0},
4035
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4036
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4037
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1296
4038
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4039
33.6k
    {AliasPatternCond_K_Ignore, 0},
4040
33.6k
    {AliasPatternCond_K_Ignore, 0},
4041
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4042
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4043
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1301
4044
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4045
33.6k
    {AliasPatternCond_K_Ignore, 0},
4046
33.6k
    {AliasPatternCond_K_Ignore, 0},
4047
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4048
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4049
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1306
4050
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4051
33.6k
    {AliasPatternCond_K_Ignore, 0},
4052
33.6k
    {AliasPatternCond_K_Ignore, 0},
4053
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4054
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4055
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1311
4056
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4057
33.6k
    {AliasPatternCond_K_Ignore, 0},
4058
33.6k
    {AliasPatternCond_K_Ignore, 0},
4059
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4060
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4061
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1316
4062
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4063
33.6k
    {AliasPatternCond_K_Ignore, 0},
4064
33.6k
    {AliasPatternCond_K_Ignore, 0},
4065
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4066
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4067
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1321
4068
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4069
33.6k
    {AliasPatternCond_K_Ignore, 0},
4070
33.6k
    {AliasPatternCond_K_Ignore, 0},
4071
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4072
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4073
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1326
4074
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4075
33.6k
    {AliasPatternCond_K_Ignore, 0},
4076
33.6k
    {AliasPatternCond_K_Ignore, 0},
4077
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4078
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4079
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1331
4080
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4081
33.6k
    {AliasPatternCond_K_Ignore, 0},
4082
33.6k
    {AliasPatternCond_K_Ignore, 0},
4083
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4084
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4085
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1336
4086
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4087
33.6k
    {AliasPatternCond_K_Ignore, 0},
4088
33.6k
    {AliasPatternCond_K_Ignore, 0},
4089
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4090
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4091
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1341
4092
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4093
33.6k
    {AliasPatternCond_K_Ignore, 0},
4094
33.6k
    {AliasPatternCond_K_Ignore, 0},
4095
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4096
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4097
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1346
4098
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4099
33.6k
    {AliasPatternCond_K_Ignore, 0},
4100
33.6k
    {AliasPatternCond_K_Ignore, 0},
4101
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4102
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4103
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1351
4104
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4105
33.6k
    {AliasPatternCond_K_Ignore, 0},
4106
33.6k
    {AliasPatternCond_K_Ignore, 0},
4107
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4108
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4109
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1356
4110
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4111
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4112
33.6k
    {AliasPatternCond_K_Ignore, 0},
4113
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4114
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4115
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1361
4116
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4117
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4118
33.6k
    {AliasPatternCond_K_Ignore, 0},
4119
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4120
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4121
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1366
4122
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4123
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4124
33.6k
    {AliasPatternCond_K_Ignore, 0},
4125
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4126
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4127
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1371
4128
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4129
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4130
33.6k
    {AliasPatternCond_K_Ignore, 0},
4131
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4132
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4133
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1376
4134
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4135
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4136
33.6k
    {AliasPatternCond_K_Ignore, 0},
4137
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4138
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4139
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1381
4140
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4141
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4142
33.6k
    {AliasPatternCond_K_Ignore, 0},
4143
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4144
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4145
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1386
4146
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4147
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4148
33.6k
    {AliasPatternCond_K_Ignore, 0},
4149
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4150
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4151
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1391
4152
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4153
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4154
33.6k
    {AliasPatternCond_K_Ignore, 0},
4155
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4156
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4157
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1396
4158
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4159
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4160
33.6k
    {AliasPatternCond_K_Ignore, 0},
4161
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4162
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4163
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1401
4164
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4165
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4166
33.6k
    {AliasPatternCond_K_Ignore, 0},
4167
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4168
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4169
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1406
4170
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4171
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4172
33.6k
    {AliasPatternCond_K_Ignore, 0},
4173
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4174
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4175
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1411
4176
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4177
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4178
33.6k
    {AliasPatternCond_K_Ignore, 0},
4179
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4180
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4181
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1416
4182
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4183
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4184
33.6k
    {AliasPatternCond_K_Ignore, 0},
4185
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4186
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4187
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1421
4188
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4189
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4190
33.6k
    {AliasPatternCond_K_Ignore, 0},
4191
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4192
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4193
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1426
4194
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4195
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4196
33.6k
    {AliasPatternCond_K_Ignore, 0},
4197
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4198
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4199
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1431
4200
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4201
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4202
33.6k
    {AliasPatternCond_K_Ignore, 0},
4203
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4204
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4205
    // (ORCCrr G0, IntRegs:$rs2, G0) - 1436
4206
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4207
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4208
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4209
    // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1439
4210
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4211
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4212
    // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1441
4213
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4214
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4215
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4216
    // (RESTORErr G0, G0, G0) - 1444
4217
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4218
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4219
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4220
    // (RET 8) - 1447
4221
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4222
    // (RETL 8) - 1448
4223
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4224
    // (SAVErr G0, G0, G0) - 1449
4225
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4226
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4227
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4228
    // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1452
4229
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4230
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4231
    // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1454
4232
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4233
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4234
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4235
    // (TICCri G0, i32imm:$imm, 8) - 1457
4236
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4237
33.6k
    {AliasPatternCond_K_Ignore, 0},
4238
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4239
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4240
    // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1461
4241
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4242
33.6k
    {AliasPatternCond_K_Ignore, 0},
4243
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4244
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4245
    // (TICCri G0, i32imm:$imm, 0) - 1465
4246
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4247
33.6k
    {AliasPatternCond_K_Ignore, 0},
4248
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4249
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4250
    // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1469
4251
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4252
33.6k
    {AliasPatternCond_K_Ignore, 0},
4253
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4254
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4255
    // (TICCri G0, i32imm:$imm, 9) - 1473
4256
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4257
33.6k
    {AliasPatternCond_K_Ignore, 0},
4258
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4259
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4260
    // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1477
4261
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4262
33.6k
    {AliasPatternCond_K_Ignore, 0},
4263
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4264
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4265
    // (TICCri G0, i32imm:$imm, 1) - 1481
4266
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4267
33.6k
    {AliasPatternCond_K_Ignore, 0},
4268
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4269
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4270
    // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1485
4271
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4272
33.6k
    {AliasPatternCond_K_Ignore, 0},
4273
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4274
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4275
    // (TICCri G0, i32imm:$imm, 10) - 1489
4276
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4277
33.6k
    {AliasPatternCond_K_Ignore, 0},
4278
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4279
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4280
    // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1493
4281
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4282
33.6k
    {AliasPatternCond_K_Ignore, 0},
4283
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4284
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4285
    // (TICCri G0, i32imm:$imm, 2) - 1497
4286
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4287
33.6k
    {AliasPatternCond_K_Ignore, 0},
4288
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4289
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4290
    // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1501
4291
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4292
33.6k
    {AliasPatternCond_K_Ignore, 0},
4293
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4294
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4295
    // (TICCri G0, i32imm:$imm, 11) - 1505
4296
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4297
33.6k
    {AliasPatternCond_K_Ignore, 0},
4298
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4299
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4300
    // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1509
4301
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4302
33.6k
    {AliasPatternCond_K_Ignore, 0},
4303
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4304
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4305
    // (TICCri G0, i32imm:$imm, 3) - 1513
4306
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4307
33.6k
    {AliasPatternCond_K_Ignore, 0},
4308
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4309
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4310
    // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1517
4311
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4312
33.6k
    {AliasPatternCond_K_Ignore, 0},
4313
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4314
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4315
    // (TICCri G0, i32imm:$imm, 12) - 1521
4316
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4317
33.6k
    {AliasPatternCond_K_Ignore, 0},
4318
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4319
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4320
    // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1525
4321
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4322
33.6k
    {AliasPatternCond_K_Ignore, 0},
4323
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4324
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4325
    // (TICCri G0, i32imm:$imm, 4) - 1529
4326
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4327
33.6k
    {AliasPatternCond_K_Ignore, 0},
4328
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4329
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4330
    // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1533
4331
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4332
33.6k
    {AliasPatternCond_K_Ignore, 0},
4333
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4334
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4335
    // (TICCri G0, i32imm:$imm, 13) - 1537
4336
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4337
33.6k
    {AliasPatternCond_K_Ignore, 0},
4338
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4339
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4340
    // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1541
4341
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4342
33.6k
    {AliasPatternCond_K_Ignore, 0},
4343
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4344
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4345
    // (TICCri G0, i32imm:$imm, 5) - 1545
4346
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4347
33.6k
    {AliasPatternCond_K_Ignore, 0},
4348
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4349
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4350
    // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1549
4351
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4352
33.6k
    {AliasPatternCond_K_Ignore, 0},
4353
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4354
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4355
    // (TICCri G0, i32imm:$imm, 14) - 1553
4356
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4357
33.6k
    {AliasPatternCond_K_Ignore, 0},
4358
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4359
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4360
    // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1557
4361
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4362
33.6k
    {AliasPatternCond_K_Ignore, 0},
4363
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4364
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4365
    // (TICCri G0, i32imm:$imm, 6) - 1561
4366
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4367
33.6k
    {AliasPatternCond_K_Ignore, 0},
4368
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4369
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4370
    // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1565
4371
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4372
33.6k
    {AliasPatternCond_K_Ignore, 0},
4373
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4374
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4375
    // (TICCri G0, i32imm:$imm, 15) - 1569
4376
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4377
33.6k
    {AliasPatternCond_K_Ignore, 0},
4378
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4379
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4380
    // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1573
4381
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4382
33.6k
    {AliasPatternCond_K_Ignore, 0},
4383
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4384
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4385
    // (TICCri G0, i32imm:$imm, 7) - 1577
4386
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4387
33.6k
    {AliasPatternCond_K_Ignore, 0},
4388
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4389
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4390
    // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1581
4391
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4392
33.6k
    {AliasPatternCond_K_Ignore, 0},
4393
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4394
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4395
    // (TICCrr G0, IntRegs:$rs2, 8) - 1585
4396
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4397
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4398
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4399
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4400
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1589
4401
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4402
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4403
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4404
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4405
    // (TICCrr G0, IntRegs:$rs2, 0) - 1593
4406
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4407
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4408
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4409
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4410
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1597
4411
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4412
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4413
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4414
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4415
    // (TICCrr G0, IntRegs:$rs2, 9) - 1601
4416
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4417
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4418
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4419
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4420
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1605
4421
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4422
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4423
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4424
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4425
    // (TICCrr G0, IntRegs:$rs2, 1) - 1609
4426
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4427
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4428
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4429
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4430
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1613
4431
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4432
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4433
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4434
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4435
    // (TICCrr G0, IntRegs:$rs2, 10) - 1617
4436
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4437
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4438
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4439
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4440
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1621
4441
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4442
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4443
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4444
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4445
    // (TICCrr G0, IntRegs:$rs2, 2) - 1625
4446
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4447
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4448
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4449
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4450
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1629
4451
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4452
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4453
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4454
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4455
    // (TICCrr G0, IntRegs:$rs2, 11) - 1633
4456
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4457
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4458
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4459
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4460
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1637
4461
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4462
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4463
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4464
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4465
    // (TICCrr G0, IntRegs:$rs2, 3) - 1641
4466
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4467
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4468
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4469
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4470
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1645
4471
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4472
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4473
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4474
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4475
    // (TICCrr G0, IntRegs:$rs2, 12) - 1649
4476
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4477
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4478
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4479
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4480
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1653
4481
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4482
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4483
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4484
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4485
    // (TICCrr G0, IntRegs:$rs2, 4) - 1657
4486
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4487
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4488
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4489
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4490
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1661
4491
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4492
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4493
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4494
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4495
    // (TICCrr G0, IntRegs:$rs2, 13) - 1665
4496
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4497
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4498
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4499
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4500
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1669
4501
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4502
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4503
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4504
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4505
    // (TICCrr G0, IntRegs:$rs2, 5) - 1673
4506
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4507
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4508
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4509
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4510
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1677
4511
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4512
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4513
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4514
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4515
    // (TICCrr G0, IntRegs:$rs2, 14) - 1681
4516
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4517
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4518
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4519
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4520
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1685
4521
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4522
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4523
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4524
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4525
    // (TICCrr G0, IntRegs:$rs2, 6) - 1689
4526
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4527
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4528
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4529
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4530
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1693
4531
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4532
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4533
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4534
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4535
    // (TICCrr G0, IntRegs:$rs2, 15) - 1697
4536
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4537
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4538
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4539
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4540
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1701
4541
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4542
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4543
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4544
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4545
    // (TICCrr G0, IntRegs:$rs2, 7) - 1705
4546
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4547
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4548
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4549
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4550
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1709
4551
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4552
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4553
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4554
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4555
    // (TRAPri G0, i32imm:$imm, 8) - 1713
4556
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4557
33.6k
    {AliasPatternCond_K_Ignore, 0},
4558
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4559
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1716
4560
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4561
33.6k
    {AliasPatternCond_K_Ignore, 0},
4562
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4563
    // (TRAPri G0, i32imm:$imm, 0) - 1719
4564
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4565
33.6k
    {AliasPatternCond_K_Ignore, 0},
4566
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4567
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1722
4568
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4569
33.6k
    {AliasPatternCond_K_Ignore, 0},
4570
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4571
    // (TRAPri G0, i32imm:$imm, 9) - 1725
4572
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4573
33.6k
    {AliasPatternCond_K_Ignore, 0},
4574
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4575
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1728
4576
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4577
33.6k
    {AliasPatternCond_K_Ignore, 0},
4578
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4579
    // (TRAPri G0, i32imm:$imm, 1) - 1731
4580
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4581
33.6k
    {AliasPatternCond_K_Ignore, 0},
4582
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4583
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1734
4584
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4585
33.6k
    {AliasPatternCond_K_Ignore, 0},
4586
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4587
    // (TRAPri G0, i32imm:$imm, 10) - 1737
4588
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4589
33.6k
    {AliasPatternCond_K_Ignore, 0},
4590
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4591
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1740
4592
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4593
33.6k
    {AliasPatternCond_K_Ignore, 0},
4594
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4595
    // (TRAPri G0, i32imm:$imm, 2) - 1743
4596
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4597
33.6k
    {AliasPatternCond_K_Ignore, 0},
4598
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4599
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1746
4600
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4601
33.6k
    {AliasPatternCond_K_Ignore, 0},
4602
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4603
    // (TRAPri G0, i32imm:$imm, 11) - 1749
4604
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4605
33.6k
    {AliasPatternCond_K_Ignore, 0},
4606
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4607
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1752
4608
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4609
33.6k
    {AliasPatternCond_K_Ignore, 0},
4610
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4611
    // (TRAPri G0, i32imm:$imm, 3) - 1755
4612
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4613
33.6k
    {AliasPatternCond_K_Ignore, 0},
4614
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4615
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1758
4616
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4617
33.6k
    {AliasPatternCond_K_Ignore, 0},
4618
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4619
    // (TRAPri G0, i32imm:$imm, 12) - 1761
4620
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4621
33.6k
    {AliasPatternCond_K_Ignore, 0},
4622
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4623
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1764
4624
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4625
33.6k
    {AliasPatternCond_K_Ignore, 0},
4626
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4627
    // (TRAPri G0, i32imm:$imm, 4) - 1767
4628
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4629
33.6k
    {AliasPatternCond_K_Ignore, 0},
4630
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4631
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1770
4632
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4633
33.6k
    {AliasPatternCond_K_Ignore, 0},
4634
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4635
    // (TRAPri G0, i32imm:$imm, 13) - 1773
4636
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4637
33.6k
    {AliasPatternCond_K_Ignore, 0},
4638
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4639
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1776
4640
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4641
33.6k
    {AliasPatternCond_K_Ignore, 0},
4642
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4643
    // (TRAPri G0, i32imm:$imm, 5) - 1779
4644
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4645
33.6k
    {AliasPatternCond_K_Ignore, 0},
4646
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4647
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1782
4648
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4649
33.6k
    {AliasPatternCond_K_Ignore, 0},
4650
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4651
    // (TRAPri G0, i32imm:$imm, 14) - 1785
4652
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4653
33.6k
    {AliasPatternCond_K_Ignore, 0},
4654
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4655
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1788
4656
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4657
33.6k
    {AliasPatternCond_K_Ignore, 0},
4658
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4659
    // (TRAPri G0, i32imm:$imm, 6) - 1791
4660
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4661
33.6k
    {AliasPatternCond_K_Ignore, 0},
4662
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4663
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1794
4664
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4665
33.6k
    {AliasPatternCond_K_Ignore, 0},
4666
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4667
    // (TRAPri G0, i32imm:$imm, 15) - 1797
4668
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4669
33.6k
    {AliasPatternCond_K_Ignore, 0},
4670
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4671
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1800
4672
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4673
33.6k
    {AliasPatternCond_K_Ignore, 0},
4674
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4675
    // (TRAPri G0, i32imm:$imm, 7) - 1803
4676
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4677
33.6k
    {AliasPatternCond_K_Ignore, 0},
4678
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4679
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1806
4680
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4681
33.6k
    {AliasPatternCond_K_Ignore, 0},
4682
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4683
    // (TRAPrr G0, IntRegs:$rs1, 8) - 1809
4684
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4685
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4686
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4687
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1812
4688
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4689
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4690
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4691
    // (TRAPrr G0, IntRegs:$rs1, 0) - 1815
4692
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4693
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4694
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4695
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1818
4696
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4697
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4698
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4699
    // (TRAPrr G0, IntRegs:$rs1, 9) - 1821
4700
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4701
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4702
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4703
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1824
4704
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4705
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4706
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4707
    // (TRAPrr G0, IntRegs:$rs1, 1) - 1827
4708
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4709
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4710
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4711
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1830
4712
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4713
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4714
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4715
    // (TRAPrr G0, IntRegs:$rs1, 10) - 1833
4716
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4717
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4718
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4719
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1836
4720
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4721
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4722
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4723
    // (TRAPrr G0, IntRegs:$rs1, 2) - 1839
4724
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4725
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4726
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4727
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1842
4728
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4729
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4730
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4731
    // (TRAPrr G0, IntRegs:$rs1, 11) - 1845
4732
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4733
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4734
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4735
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1848
4736
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4737
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4738
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4739
    // (TRAPrr G0, IntRegs:$rs1, 3) - 1851
4740
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4741
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4742
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4743
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1854
4744
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4745
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4746
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4747
    // (TRAPrr G0, IntRegs:$rs1, 12) - 1857
4748
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4749
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4750
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4751
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1860
4752
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4753
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4754
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4755
    // (TRAPrr G0, IntRegs:$rs1, 4) - 1863
4756
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4757
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4758
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4759
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1866
4760
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4761
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4762
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4763
    // (TRAPrr G0, IntRegs:$rs1, 13) - 1869
4764
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4765
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4766
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4767
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1872
4768
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4769
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4770
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4771
    // (TRAPrr G0, IntRegs:$rs1, 5) - 1875
4772
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4773
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4774
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4775
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1878
4776
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4777
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4778
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4779
    // (TRAPrr G0, IntRegs:$rs1, 14) - 1881
4780
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4781
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4782
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4783
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1884
4784
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4785
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4786
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4787
    // (TRAPrr G0, IntRegs:$rs1, 6) - 1887
4788
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4789
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4790
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4791
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1890
4792
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4793
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4794
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4795
    // (TRAPrr G0, IntRegs:$rs1, 15) - 1893
4796
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4797
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4798
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4799
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1896
4800
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4801
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4802
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4803
    // (TRAPrr G0, IntRegs:$rs1, 7) - 1899
4804
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4805
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4806
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4807
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1902
4808
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4809
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4810
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4811
    // (TXCCri G0, i32imm:$imm, 8) - 1905
4812
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4813
33.6k
    {AliasPatternCond_K_Ignore, 0},
4814
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4815
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4816
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1909
4817
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4818
33.6k
    {AliasPatternCond_K_Ignore, 0},
4819
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4820
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4821
    // (TXCCri G0, i32imm:$imm, 0) - 1913
4822
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4823
33.6k
    {AliasPatternCond_K_Ignore, 0},
4824
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4825
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4826
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1917
4827
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4828
33.6k
    {AliasPatternCond_K_Ignore, 0},
4829
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4830
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4831
    // (TXCCri G0, i32imm:$imm, 9) - 1921
4832
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4833
33.6k
    {AliasPatternCond_K_Ignore, 0},
4834
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4835
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4836
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1925
4837
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4838
33.6k
    {AliasPatternCond_K_Ignore, 0},
4839
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4840
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4841
    // (TXCCri G0, i32imm:$imm, 1) - 1929
4842
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4843
33.6k
    {AliasPatternCond_K_Ignore, 0},
4844
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4845
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4846
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1933
4847
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4848
33.6k
    {AliasPatternCond_K_Ignore, 0},
4849
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
4850
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4851
    // (TXCCri G0, i32imm:$imm, 10) - 1937
4852
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4853
33.6k
    {AliasPatternCond_K_Ignore, 0},
4854
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4855
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4856
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1941
4857
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4858
33.6k
    {AliasPatternCond_K_Ignore, 0},
4859
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
4860
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4861
    // (TXCCri G0, i32imm:$imm, 2) - 1945
4862
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4863
33.6k
    {AliasPatternCond_K_Ignore, 0},
4864
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4865
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4866
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1949
4867
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4868
33.6k
    {AliasPatternCond_K_Ignore, 0},
4869
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
4870
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4871
    // (TXCCri G0, i32imm:$imm, 11) - 1953
4872
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4873
33.6k
    {AliasPatternCond_K_Ignore, 0},
4874
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4875
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4876
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1957
4877
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4878
33.6k
    {AliasPatternCond_K_Ignore, 0},
4879
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
4880
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4881
    // (TXCCri G0, i32imm:$imm, 3) - 1961
4882
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4883
33.6k
    {AliasPatternCond_K_Ignore, 0},
4884
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4885
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4886
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1965
4887
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4888
33.6k
    {AliasPatternCond_K_Ignore, 0},
4889
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
4890
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4891
    // (TXCCri G0, i32imm:$imm, 12) - 1969
4892
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4893
33.6k
    {AliasPatternCond_K_Ignore, 0},
4894
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4895
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4896
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1973
4897
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4898
33.6k
    {AliasPatternCond_K_Ignore, 0},
4899
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
4900
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4901
    // (TXCCri G0, i32imm:$imm, 4) - 1977
4902
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4903
33.6k
    {AliasPatternCond_K_Ignore, 0},
4904
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4905
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4906
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1981
4907
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4908
33.6k
    {AliasPatternCond_K_Ignore, 0},
4909
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
4910
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4911
    // (TXCCri G0, i32imm:$imm, 13) - 1985
4912
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4913
33.6k
    {AliasPatternCond_K_Ignore, 0},
4914
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4915
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4916
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1989
4917
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4918
33.6k
    {AliasPatternCond_K_Ignore, 0},
4919
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
4920
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4921
    // (TXCCri G0, i32imm:$imm, 5) - 1993
4922
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4923
33.6k
    {AliasPatternCond_K_Ignore, 0},
4924
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4925
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4926
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1997
4927
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4928
33.6k
    {AliasPatternCond_K_Ignore, 0},
4929
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
4930
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4931
    // (TXCCri G0, i32imm:$imm, 14) - 2001
4932
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4933
33.6k
    {AliasPatternCond_K_Ignore, 0},
4934
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4935
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4936
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2005
4937
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4938
33.6k
    {AliasPatternCond_K_Ignore, 0},
4939
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
4940
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4941
    // (TXCCri G0, i32imm:$imm, 6) - 2009
4942
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4943
33.6k
    {AliasPatternCond_K_Ignore, 0},
4944
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4945
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4946
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2013
4947
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4948
33.6k
    {AliasPatternCond_K_Ignore, 0},
4949
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
4950
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4951
    // (TXCCri G0, i32imm:$imm, 15) - 2017
4952
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4953
33.6k
    {AliasPatternCond_K_Ignore, 0},
4954
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4955
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4956
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2021
4957
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4958
33.6k
    {AliasPatternCond_K_Ignore, 0},
4959
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
4960
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4961
    // (TXCCri G0, i32imm:$imm, 7) - 2025
4962
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4963
33.6k
    {AliasPatternCond_K_Ignore, 0},
4964
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4965
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4966
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2029
4967
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4968
33.6k
    {AliasPatternCond_K_Ignore, 0},
4969
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
4970
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4971
    // (TXCCrr G0, IntRegs:$rs2, 8) - 2033
4972
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4973
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4974
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4975
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4976
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2037
4977
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4978
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4979
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
4980
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4981
    // (TXCCrr G0, IntRegs:$rs2, 0) - 2041
4982
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4983
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4984
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4985
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4986
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2045
4987
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4988
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4989
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
4990
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4991
    // (TXCCrr G0, IntRegs:$rs2, 9) - 2049
4992
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
4993
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4994
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
4995
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
4996
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2053
4997
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4998
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
4999
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5000
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5001
    // (TXCCrr G0, IntRegs:$rs2, 1) - 2057
5002
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5003
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5004
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5005
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5006
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2061
5007
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5008
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5009
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5010
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5011
    // (TXCCrr G0, IntRegs:$rs2, 10) - 2065
5012
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5013
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5014
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5015
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5016
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2069
5017
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5018
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5019
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5020
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5021
    // (TXCCrr G0, IntRegs:$rs2, 2) - 2073
5022
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5023
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5024
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5025
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5026
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2077
5027
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5028
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5029
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5030
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5031
    // (TXCCrr G0, IntRegs:$rs2, 11) - 2081
5032
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5033
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5034
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5035
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5036
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2085
5037
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5038
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5039
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5040
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5041
    // (TXCCrr G0, IntRegs:$rs2, 3) - 2089
5042
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5043
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5044
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5045
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5046
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2093
5047
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5048
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5049
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5050
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5051
    // (TXCCrr G0, IntRegs:$rs2, 12) - 2097
5052
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5053
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5054
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5055
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5056
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2101
5057
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5058
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5059
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5060
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5061
    // (TXCCrr G0, IntRegs:$rs2, 4) - 2105
5062
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5063
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5064
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5065
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5066
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2109
5067
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5068
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5069
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5070
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5071
    // (TXCCrr G0, IntRegs:$rs2, 13) - 2113
5072
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5073
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5074
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5075
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5076
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2117
5077
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5078
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5079
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5080
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5081
    // (TXCCrr G0, IntRegs:$rs2, 5) - 2121
5082
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5083
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5084
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5085
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5086
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2125
5087
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5088
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5089
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5090
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5091
    // (TXCCrr G0, IntRegs:$rs2, 14) - 2129
5092
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5093
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5094
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5095
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5096
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2133
5097
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5098
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5099
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5100
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5101
    // (TXCCrr G0, IntRegs:$rs2, 6) - 2137
5102
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5103
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5104
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5105
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5106
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2141
5107
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5108
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5109
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5110
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5111
    // (TXCCrr G0, IntRegs:$rs2, 15) - 2145
5112
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5113
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5114
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5115
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5116
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2149
5117
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5118
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5119
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5120
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5121
    // (TXCCrr G0, IntRegs:$rs2, 7) - 2153
5122
33.6k
    {AliasPatternCond_K_Reg, Sparc_G0},
5123
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5124
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5125
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5126
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2157
5127
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5128
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5129
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5130
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5131
    // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2161
5132
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5133
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5134
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5135
    // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2164
5136
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5137
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5138
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5139
    // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2167
5140
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5141
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5142
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5143
    // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2170
5144
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5145
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5146
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5147
    // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2173
5148
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5149
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5150
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5151
    // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2176
5152
33.6k
    {AliasPatternCond_K_Reg, Sparc_FCC0},
5153
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5154
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5155
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2179
5156
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5157
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5158
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5159
33.6k
    {AliasPatternCond_K_Ignore, 0},
5160
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5161
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5162
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2185
5163
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5164
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5165
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5166
33.6k
    {AliasPatternCond_K_Ignore, 0},
5167
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5168
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5169
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2191
5170
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5171
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5172
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5173
33.6k
    {AliasPatternCond_K_Ignore, 0},
5174
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5175
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5176
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2197
5177
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5178
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5179
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5180
33.6k
    {AliasPatternCond_K_Ignore, 0},
5181
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5182
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5183
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2203
5184
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5185
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5186
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5187
33.6k
    {AliasPatternCond_K_Ignore, 0},
5188
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5189
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5190
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2209
5191
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5192
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5193
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5194
33.6k
    {AliasPatternCond_K_Ignore, 0},
5195
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5196
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5197
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2215
5198
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5199
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5200
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5201
33.6k
    {AliasPatternCond_K_Ignore, 0},
5202
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5203
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5204
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2221
5205
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5206
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5207
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5208
33.6k
    {AliasPatternCond_K_Ignore, 0},
5209
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5210
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5211
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2227
5212
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5213
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5214
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5215
33.6k
    {AliasPatternCond_K_Ignore, 0},
5216
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5217
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5218
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2233
5219
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5220
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5221
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5222
33.6k
    {AliasPatternCond_K_Ignore, 0},
5223
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5224
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5225
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2239
5226
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5227
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5228
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5229
33.6k
    {AliasPatternCond_K_Ignore, 0},
5230
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5231
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5232
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2245
5233
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5234
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5235
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5236
33.6k
    {AliasPatternCond_K_Ignore, 0},
5237
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5238
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5239
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2251
5240
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5241
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5242
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5243
33.6k
    {AliasPatternCond_K_Ignore, 0},
5244
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5245
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5246
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2257
5247
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5248
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5249
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5250
33.6k
    {AliasPatternCond_K_Ignore, 0},
5251
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5252
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5253
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2263
5254
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5255
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5256
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5257
33.6k
    {AliasPatternCond_K_Ignore, 0},
5258
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5259
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5260
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2269
5261
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5262
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5263
33.6k
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
5264
33.6k
    {AliasPatternCond_K_Ignore, 0},
5265
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5266
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5267
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2275
5268
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5269
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5270
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5271
33.6k
    {AliasPatternCond_K_Ignore, 0},
5272
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5273
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5274
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2281
5275
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5276
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5277
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5278
33.6k
    {AliasPatternCond_K_Ignore, 0},
5279
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5280
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5281
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2287
5282
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5283
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5284
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5285
33.6k
    {AliasPatternCond_K_Ignore, 0},
5286
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5287
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5288
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2293
5289
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5290
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5291
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5292
33.6k
    {AliasPatternCond_K_Ignore, 0},
5293
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5294
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5295
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2299
5296
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5297
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5298
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5299
33.6k
    {AliasPatternCond_K_Ignore, 0},
5300
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5301
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5302
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2305
5303
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5304
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5305
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5306
33.6k
    {AliasPatternCond_K_Ignore, 0},
5307
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5308
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5309
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2311
5310
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5311
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5312
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5313
33.6k
    {AliasPatternCond_K_Ignore, 0},
5314
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5315
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5316
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2317
5317
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5318
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5319
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5320
33.6k
    {AliasPatternCond_K_Ignore, 0},
5321
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5322
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5323
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2323
5324
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5325
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5326
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5327
33.6k
    {AliasPatternCond_K_Ignore, 0},
5328
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5329
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5330
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2329
5331
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5332
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5333
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5334
33.6k
    {AliasPatternCond_K_Ignore, 0},
5335
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5336
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5337
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2335
5338
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5339
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5340
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5341
33.6k
    {AliasPatternCond_K_Ignore, 0},
5342
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5343
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5344
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2341
5345
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5346
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5347
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5348
33.6k
    {AliasPatternCond_K_Ignore, 0},
5349
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5350
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5351
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2347
5352
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5353
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5354
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5355
33.6k
    {AliasPatternCond_K_Ignore, 0},
5356
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5357
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5358
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2353
5359
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5360
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5361
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5362
33.6k
    {AliasPatternCond_K_Ignore, 0},
5363
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5364
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5365
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2359
5366
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5367
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5368
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5369
33.6k
    {AliasPatternCond_K_Ignore, 0},
5370
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5371
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5372
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2365
5373
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5374
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5375
33.6k
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
5376
33.6k
    {AliasPatternCond_K_Ignore, 0},
5377
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5378
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5379
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2371
5380
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5381
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5382
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5383
33.6k
    {AliasPatternCond_K_Ignore, 0},
5384
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5385
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5386
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2377
5387
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5388
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5389
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5390
33.6k
    {AliasPatternCond_K_Ignore, 0},
5391
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5392
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5393
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2383
5394
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5395
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5396
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5397
33.6k
    {AliasPatternCond_K_Ignore, 0},
5398
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5399
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5400
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2389
5401
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5402
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5403
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5404
33.6k
    {AliasPatternCond_K_Ignore, 0},
5405
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5406
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5407
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2395
5408
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5409
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5410
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5411
33.6k
    {AliasPatternCond_K_Ignore, 0},
5412
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5413
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5414
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2401
5415
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5416
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5417
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5418
33.6k
    {AliasPatternCond_K_Ignore, 0},
5419
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5420
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5421
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2407
5422
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5423
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5424
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5425
33.6k
    {AliasPatternCond_K_Ignore, 0},
5426
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5427
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5428
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2413
5429
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5430
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5431
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5432
33.6k
    {AliasPatternCond_K_Ignore, 0},
5433
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5434
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5435
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2419
5436
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5437
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5438
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5439
33.6k
    {AliasPatternCond_K_Ignore, 0},
5440
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5441
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5442
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2425
5443
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5444
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5445
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5446
33.6k
    {AliasPatternCond_K_Ignore, 0},
5447
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5448
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5449
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2431
5450
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5451
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5452
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5453
33.6k
    {AliasPatternCond_K_Ignore, 0},
5454
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5455
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5456
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2437
5457
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5458
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5459
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5460
33.6k
    {AliasPatternCond_K_Ignore, 0},
5461
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5462
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5463
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2443
5464
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5465
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5466
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5467
33.6k
    {AliasPatternCond_K_Ignore, 0},
5468
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5469
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5470
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2449
5471
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5472
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5473
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5474
33.6k
    {AliasPatternCond_K_Ignore, 0},
5475
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5476
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5477
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2455
5478
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5479
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5480
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5481
33.6k
    {AliasPatternCond_K_Ignore, 0},
5482
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5483
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5484
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2461
5485
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5486
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5487
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
5488
33.6k
    {AliasPatternCond_K_Ignore, 0},
5489
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5490
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5491
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2467
5492
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5493
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5494
33.6k
    {AliasPatternCond_K_Ignore, 0},
5495
33.6k
    {AliasPatternCond_K_Ignore, 0},
5496
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5497
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5498
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2473
5499
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5500
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5501
33.6k
    {AliasPatternCond_K_Ignore, 0},
5502
33.6k
    {AliasPatternCond_K_Ignore, 0},
5503
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5504
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5505
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2479
5506
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5507
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5508
33.6k
    {AliasPatternCond_K_Ignore, 0},
5509
33.6k
    {AliasPatternCond_K_Ignore, 0},
5510
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5511
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5512
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2485
5513
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5514
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5515
33.6k
    {AliasPatternCond_K_Ignore, 0},
5516
33.6k
    {AliasPatternCond_K_Ignore, 0},
5517
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5518
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5519
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2491
5520
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5521
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5522
33.6k
    {AliasPatternCond_K_Ignore, 0},
5523
33.6k
    {AliasPatternCond_K_Ignore, 0},
5524
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5525
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5526
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2497
5527
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5528
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5529
33.6k
    {AliasPatternCond_K_Ignore, 0},
5530
33.6k
    {AliasPatternCond_K_Ignore, 0},
5531
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5532
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5533
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2503
5534
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5535
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5536
33.6k
    {AliasPatternCond_K_Ignore, 0},
5537
33.6k
    {AliasPatternCond_K_Ignore, 0},
5538
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5539
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5540
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2509
5541
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5542
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5543
33.6k
    {AliasPatternCond_K_Ignore, 0},
5544
33.6k
    {AliasPatternCond_K_Ignore, 0},
5545
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5546
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5547
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2515
5548
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5549
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5550
33.6k
    {AliasPatternCond_K_Ignore, 0},
5551
33.6k
    {AliasPatternCond_K_Ignore, 0},
5552
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5553
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5554
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2521
5555
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5556
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5557
33.6k
    {AliasPatternCond_K_Ignore, 0},
5558
33.6k
    {AliasPatternCond_K_Ignore, 0},
5559
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5560
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5561
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2527
5562
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5563
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5564
33.6k
    {AliasPatternCond_K_Ignore, 0},
5565
33.6k
    {AliasPatternCond_K_Ignore, 0},
5566
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5567
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5568
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2533
5569
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5570
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5571
33.6k
    {AliasPatternCond_K_Ignore, 0},
5572
33.6k
    {AliasPatternCond_K_Ignore, 0},
5573
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5574
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5575
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2539
5576
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5577
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5578
33.6k
    {AliasPatternCond_K_Ignore, 0},
5579
33.6k
    {AliasPatternCond_K_Ignore, 0},
5580
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5581
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5582
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2545
5583
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5584
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5585
33.6k
    {AliasPatternCond_K_Ignore, 0},
5586
33.6k
    {AliasPatternCond_K_Ignore, 0},
5587
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5588
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5589
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2551
5590
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5591
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5592
33.6k
    {AliasPatternCond_K_Ignore, 0},
5593
33.6k
    {AliasPatternCond_K_Ignore, 0},
5594
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5595
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5596
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2557
5597
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5598
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5599
33.6k
    {AliasPatternCond_K_Ignore, 0},
5600
33.6k
    {AliasPatternCond_K_Ignore, 0},
5601
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5602
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5603
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2563
5604
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5605
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5606
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5607
33.6k
    {AliasPatternCond_K_Ignore, 0},
5608
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)8},
5609
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5610
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2569
5611
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5612
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5613
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5614
33.6k
    {AliasPatternCond_K_Ignore, 0},
5615
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)0},
5616
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5617
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2575
5618
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5619
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5620
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5621
33.6k
    {AliasPatternCond_K_Ignore, 0},
5622
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)7},
5623
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5624
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2581
5625
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5626
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5627
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5628
33.6k
    {AliasPatternCond_K_Ignore, 0},
5629
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)6},
5630
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5631
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2587
5632
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5633
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5634
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5635
33.6k
    {AliasPatternCond_K_Ignore, 0},
5636
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)5},
5637
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5638
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2593
5639
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5640
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5641
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5642
33.6k
    {AliasPatternCond_K_Ignore, 0},
5643
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)4},
5644
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5645
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2599
5646
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5647
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5648
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5649
33.6k
    {AliasPatternCond_K_Ignore, 0},
5650
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)3},
5651
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5652
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2605
5653
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5654
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5655
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5656
33.6k
    {AliasPatternCond_K_Ignore, 0},
5657
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)2},
5658
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5659
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2611
5660
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5661
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5662
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5663
33.6k
    {AliasPatternCond_K_Ignore, 0},
5664
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)1},
5665
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5666
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2617
5667
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5668
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5669
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5670
33.6k
    {AliasPatternCond_K_Ignore, 0},
5671
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)9},
5672
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5673
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2623
5674
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5675
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5676
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5677
33.6k
    {AliasPatternCond_K_Ignore, 0},
5678
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)10},
5679
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5680
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2629
5681
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5682
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5683
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5684
33.6k
    {AliasPatternCond_K_Ignore, 0},
5685
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)11},
5686
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5687
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2635
5688
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5689
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5690
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5691
33.6k
    {AliasPatternCond_K_Ignore, 0},
5692
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)12},
5693
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5694
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2641
5695
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5696
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5697
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5698
33.6k
    {AliasPatternCond_K_Ignore, 0},
5699
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)13},
5700
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5701
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2647
5702
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5703
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5704
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5705
33.6k
    {AliasPatternCond_K_Ignore, 0},
5706
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)14},
5707
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5708
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2653
5709
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5710
33.6k
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
5711
33.6k
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
5712
33.6k
    {AliasPatternCond_K_Ignore, 0},
5713
33.6k
    {AliasPatternCond_K_Imm, (uint32_t)15},
5714
33.6k
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
5715
33.6k
  {0},  };
5716
5717
33.6k
  static const char AsmStrings[] =
5718
33.6k
    /* 0 */ "ba $\x01\0"
5719
33.6k
    /* 6 */ "bn $\x01\0"
5720
33.6k
    /* 12 */ "bne $\x01\0"
5721
33.6k
    /* 19 */ "be $\x01\0"
5722
33.6k
    /* 25 */ "bg $\x01\0"
5723
33.6k
    /* 31 */ "ble $\x01\0"
5724
33.6k
    /* 38 */ "bge $\x01\0"
5725
33.6k
    /* 45 */ "bl $\x01\0"
5726
33.6k
    /* 51 */ "bgu $\x01\0"
5727
33.6k
    /* 58 */ "bleu $\x01\0"
5728
33.6k
    /* 66 */ "bcc $\x01\0"
5729
33.6k
    /* 73 */ "bcs $\x01\0"
5730
33.6k
    /* 80 */ "bpos $\x01\0"
5731
33.6k
    /* 88 */ "bneg $\x01\0"
5732
33.6k
    /* 96 */ "bvc $\x01\0"
5733
33.6k
    /* 103 */ "bvs $\x01\0"
5734
33.6k
    /* 110 */ "ba,a $\x01\0"
5735
33.6k
    /* 118 */ "bn,a $\x01\0"
5736
33.6k
    /* 126 */ "bne,a $\x01\0"
5737
33.6k
    /* 135 */ "be,a $\x01\0"
5738
33.6k
    /* 143 */ "bg,a $\x01\0"
5739
33.6k
    /* 151 */ "ble,a $\x01\0"
5740
33.6k
    /* 160 */ "bge,a $\x01\0"
5741
33.6k
    /* 169 */ "bl,a $\x01\0"
5742
33.6k
    /* 177 */ "bgu,a $\x01\0"
5743
33.6k
    /* 186 */ "bleu,a $\x01\0"
5744
33.6k
    /* 196 */ "bcc,a $\x01\0"
5745
33.6k
    /* 205 */ "bcs,a $\x01\0"
5746
33.6k
    /* 214 */ "bpos,a $\x01\0"
5747
33.6k
    /* 224 */ "bneg,a $\x01\0"
5748
33.6k
    /* 234 */ "bvc,a $\x01\0"
5749
33.6k
    /* 243 */ "bvs,a $\x01\0"
5750
33.6k
    /* 252 */ "fba,a,pn $\x03, $\x01\0"
5751
33.6k
    /* 268 */ "fbn,a,pn $\x03, $\x01\0"
5752
33.6k
    /* 284 */ "fbu,a,pn $\x03, $\x01\0"
5753
33.6k
    /* 300 */ "fbg,a,pn $\x03, $\x01\0"
5754
33.6k
    /* 316 */ "fbug,a,pn $\x03, $\x01\0"
5755
33.6k
    /* 333 */ "fbl,a,pn $\x03, $\x01\0"
5756
33.6k
    /* 349 */ "fbul,a,pn $\x03, $\x01\0"
5757
33.6k
    /* 366 */ "fblg,a,pn $\x03, $\x01\0"
5758
33.6k
    /* 383 */ "fbne,a,pn $\x03, $\x01\0"
5759
33.6k
    /* 400 */ "fbe,a,pn $\x03, $\x01\0"
5760
33.6k
    /* 416 */ "fbue,a,pn $\x03, $\x01\0"
5761
33.6k
    /* 433 */ "fbge,a,pn $\x03, $\x01\0"
5762
33.6k
    /* 450 */ "fbuge,a,pn $\x03, $\x01\0"
5763
33.6k
    /* 468 */ "fble,a,pn $\x03, $\x01\0"
5764
33.6k
    /* 485 */ "fbule,a,pn $\x03, $\x01\0"
5765
33.6k
    /* 503 */ "fbo,a,pn $\x03, $\x01\0"
5766
33.6k
    /* 519 */ "fba,pn $\x03, $\x01\0"
5767
33.6k
    /* 533 */ "fbn,pn $\x03, $\x01\0"
5768
33.6k
    /* 547 */ "fbu,pn $\x03, $\x01\0"
5769
33.6k
    /* 561 */ "fbg,pn $\x03, $\x01\0"
5770
33.6k
    /* 575 */ "fbug,pn $\x03, $\x01\0"
5771
33.6k
    /* 590 */ "fbl,pn $\x03, $\x01\0"
5772
33.6k
    /* 604 */ "fbul,pn $\x03, $\x01\0"
5773
33.6k
    /* 619 */ "fblg,pn $\x03, $\x01\0"
5774
33.6k
    /* 634 */ "fbne,pn $\x03, $\x01\0"
5775
33.6k
    /* 649 */ "fbe,pn $\x03, $\x01\0"
5776
33.6k
    /* 663 */ "fbue,pn $\x03, $\x01\0"
5777
33.6k
    /* 678 */ "fbge,pn $\x03, $\x01\0"
5778
33.6k
    /* 693 */ "fbuge,pn $\x03, $\x01\0"
5779
33.6k
    /* 709 */ "fble,pn $\x03, $\x01\0"
5780
33.6k
    /* 724 */ "fbule,pn $\x03, $\x01\0"
5781
33.6k
    /* 740 */ "fbo,pn $\x03, $\x01\0"
5782
33.6k
    /* 754 */ "ba,a,pn %icc, $\x01\0"
5783
33.6k
    /* 771 */ "bn,a,pn %icc, $\x01\0"
5784
33.6k
    /* 788 */ "bne,a,pn %icc, $\x01\0"
5785
33.6k
    /* 806 */ "be,a,pn %icc, $\x01\0"
5786
33.6k
    /* 823 */ "bg,a,pn %icc, $\x01\0"
5787
33.6k
    /* 840 */ "ble,a,pn %icc, $\x01\0"
5788
33.6k
    /* 858 */ "bge,a,pn %icc, $\x01\0"
5789
33.6k
    /* 876 */ "bl,a,pn %icc, $\x01\0"
5790
33.6k
    /* 893 */ "bgu,a,pn %icc, $\x01\0"
5791
33.6k
    /* 911 */ "bleu,a,pn %icc, $\x01\0"
5792
33.6k
    /* 930 */ "bcc,a,pn %icc, $\x01\0"
5793
33.6k
    /* 948 */ "bcs,a,pn %icc, $\x01\0"
5794
33.6k
    /* 966 */ "bpos,a,pn %icc, $\x01\0"
5795
33.6k
    /* 985 */ "bneg,a,pn %icc, $\x01\0"
5796
33.6k
    /* 1004 */ "bvc,a,pn %icc, $\x01\0"
5797
33.6k
    /* 1022 */ "bvs,a,pn %icc, $\x01\0"
5798
33.6k
    /* 1040 */ "ba,pn %icc, $\x01\0"
5799
33.6k
    /* 1055 */ "bn,pn %icc, $\x01\0"
5800
33.6k
    /* 1070 */ "bne,pn %icc, $\x01\0"
5801
33.6k
    /* 1086 */ "be,pn %icc, $\x01\0"
5802
33.6k
    /* 1101 */ "bg,pn %icc, $\x01\0"
5803
33.6k
    /* 1116 */ "ble,pn %icc, $\x01\0"
5804
33.6k
    /* 1132 */ "bge,pn %icc, $\x01\0"
5805
33.6k
    /* 1148 */ "bl,pn %icc, $\x01\0"
5806
33.6k
    /* 1163 */ "bgu,pn %icc, $\x01\0"
5807
33.6k
    /* 1179 */ "bleu,pn %icc, $\x01\0"
5808
33.6k
    /* 1196 */ "bcc,pn %icc, $\x01\0"
5809
33.6k
    /* 1212 */ "bcs,pn %icc, $\x01\0"
5810
33.6k
    /* 1228 */ "bpos,pn %icc, $\x01\0"
5811
33.6k
    /* 1245 */ "bneg,pn %icc, $\x01\0"
5812
33.6k
    /* 1262 */ "bvc,pn %icc, $\x01\0"
5813
33.6k
    /* 1278 */ "bvs,pn %icc, $\x01\0"
5814
33.6k
    /* 1294 */ "brz,a,pn $\x03, $\x01\0"
5815
33.6k
    /* 1310 */ "brlez,a,pn $\x03, $\x01\0"
5816
33.6k
    /* 1328 */ "brlz,a,pn $\x03, $\x01\0"
5817
33.6k
    /* 1345 */ "brnz,a,pn $\x03, $\x01\0"
5818
33.6k
    /* 1362 */ "brgz,a,pn $\x03, $\x01\0"
5819
33.6k
    /* 1379 */ "brgez,a,pn $\x03, $\x01\0"
5820
33.6k
    /* 1397 */ "brz,pn $\x03, $\x01\0"
5821
33.6k
    /* 1411 */ "brlez,pn $\x03, $\x01\0"
5822
33.6k
    /* 1427 */ "brlz,pn $\x03, $\x01\0"
5823
33.6k
    /* 1442 */ "brnz,pn $\x03, $\x01\0"
5824
33.6k
    /* 1457 */ "brgz,pn $\x03, $\x01\0"
5825
33.6k
    /* 1472 */ "brgez,pn $\x03, $\x01\0"
5826
33.6k
    /* 1488 */ "ba,a,pn %xcc, $\x01\0"
5827
33.6k
    /* 1505 */ "bn,a,pn %xcc, $\x01\0"
5828
33.6k
    /* 1522 */ "bne,a,pn %xcc, $\x01\0"
5829
33.6k
    /* 1540 */ "be,a,pn %xcc, $\x01\0"
5830
33.6k
    /* 1557 */ "bg,a,pn %xcc, $\x01\0"
5831
33.6k
    /* 1574 */ "ble,a,pn %xcc, $\x01\0"
5832
33.6k
    /* 1592 */ "bge,a,pn %xcc, $\x01\0"
5833
33.6k
    /* 1610 */ "bl,a,pn %xcc, $\x01\0"
5834
33.6k
    /* 1627 */ "bgu,a,pn %xcc, $\x01\0"
5835
33.6k
    /* 1645 */ "bleu,a,pn %xcc, $\x01\0"
5836
33.6k
    /* 1664 */ "bcc,a,pn %xcc, $\x01\0"
5837
33.6k
    /* 1682 */ "bcs,a,pn %xcc, $\x01\0"
5838
33.6k
    /* 1700 */ "bpos,a,pn %xcc, $\x01\0"
5839
33.6k
    /* 1719 */ "bneg,a,pn %xcc, $\x01\0"
5840
33.6k
    /* 1738 */ "bvc,a,pn %xcc, $\x01\0"
5841
33.6k
    /* 1756 */ "bvs,a,pn %xcc, $\x01\0"
5842
33.6k
    /* 1774 */ "ba,pn %xcc, $\x01\0"
5843
33.6k
    /* 1789 */ "bn,pn %xcc, $\x01\0"
5844
33.6k
    /* 1804 */ "bne,pn %xcc, $\x01\0"
5845
33.6k
    /* 1820 */ "be,pn %xcc, $\x01\0"
5846
33.6k
    /* 1835 */ "bg,pn %xcc, $\x01\0"
5847
33.6k
    /* 1850 */ "ble,pn %xcc, $\x01\0"
5848
33.6k
    /* 1866 */ "bge,pn %xcc, $\x01\0"
5849
33.6k
    /* 1882 */ "bl,pn %xcc, $\x01\0"
5850
33.6k
    /* 1897 */ "bgu,pn %xcc, $\x01\0"
5851
33.6k
    /* 1913 */ "bleu,pn %xcc, $\x01\0"
5852
33.6k
    /* 1930 */ "bcc,pn %xcc, $\x01\0"
5853
33.6k
    /* 1946 */ "bcs,pn %xcc, $\x01\0"
5854
33.6k
    /* 1962 */ "bpos,pn %xcc, $\x01\0"
5855
33.6k
    /* 1979 */ "bneg,pn %xcc, $\x01\0"
5856
33.6k
    /* 1996 */ "bvc,pn %xcc, $\x01\0"
5857
33.6k
    /* 2012 */ "bvs,pn %xcc, $\x01\0"
5858
33.6k
    /* 2028 */ "cas [$\x02], $\x03, $\x01\0"
5859
33.6k
    /* 2045 */ "casl [$\x02], $\x03, $\x01\0"
5860
33.6k
    /* 2063 */ "casx [$\x02], $\x03, $\x01\0"
5861
33.6k
    /* 2081 */ "casxl [$\x02], $\x03, $\x01\0"
5862
33.6k
    /* 2100 */ "fmovda %icc, $\x02, $\x01\0"
5863
33.6k
    /* 2120 */ "fmovdn %icc, $\x02, $\x01\0"
5864
33.6k
    /* 2140 */ "fmovdne %icc, $\x02, $\x01\0"
5865
33.6k
    /* 2161 */ "fmovde %icc, $\x02, $\x01\0"
5866
33.6k
    /* 2181 */ "fmovdg %icc, $\x02, $\x01\0"
5867
33.6k
    /* 2201 */ "fmovdle %icc, $\x02, $\x01\0"
5868
33.6k
    /* 2222 */ "fmovdge %icc, $\x02, $\x01\0"
5869
33.6k
    /* 2243 */ "fmovdl %icc, $\x02, $\x01\0"
5870
33.6k
    /* 2263 */ "fmovdgu %icc, $\x02, $\x01\0"
5871
33.6k
    /* 2284 */ "fmovdleu %icc, $\x02, $\x01\0"
5872
33.6k
    /* 2306 */ "fmovdcc %icc, $\x02, $\x01\0"
5873
33.6k
    /* 2327 */ "fmovdcs %icc, $\x02, $\x01\0"
5874
33.6k
    /* 2348 */ "fmovdpos %icc, $\x02, $\x01\0"
5875
33.6k
    /* 2370 */ "fmovdneg %icc, $\x02, $\x01\0"
5876
33.6k
    /* 2392 */ "fmovdvc %icc, $\x02, $\x01\0"
5877
33.6k
    /* 2413 */ "fmovdvs %icc, $\x02, $\x01\0"
5878
33.6k
    /* 2434 */ "fmovda %xcc, $\x02, $\x01\0"
5879
33.6k
    /* 2454 */ "fmovdn %xcc, $\x02, $\x01\0"
5880
33.6k
    /* 2474 */ "fmovdne %xcc, $\x02, $\x01\0"
5881
33.6k
    /* 2495 */ "fmovde %xcc, $\x02, $\x01\0"
5882
33.6k
    /* 2515 */ "fmovdg %xcc, $\x02, $\x01\0"
5883
33.6k
    /* 2535 */ "fmovdle %xcc, $\x02, $\x01\0"
5884
33.6k
    /* 2556 */ "fmovdge %xcc, $\x02, $\x01\0"
5885
33.6k
    /* 2577 */ "fmovdl %xcc, $\x02, $\x01\0"
5886
33.6k
    /* 2597 */ "fmovdgu %xcc, $\x02, $\x01\0"
5887
33.6k
    /* 2618 */ "fmovdleu %xcc, $\x02, $\x01\0"
5888
33.6k
    /* 2640 */ "fmovdcc %xcc, $\x02, $\x01\0"
5889
33.6k
    /* 2661 */ "fmovdcs %xcc, $\x02, $\x01\0"
5890
33.6k
    /* 2682 */ "fmovdpos %xcc, $\x02, $\x01\0"
5891
33.6k
    /* 2704 */ "fmovdneg %xcc, $\x02, $\x01\0"
5892
33.6k
    /* 2726 */ "fmovdvc %xcc, $\x02, $\x01\0"
5893
33.6k
    /* 2747 */ "fmovdvs %xcc, $\x02, $\x01\0"
5894
33.6k
    /* 2768 */ "fmovqa %icc, $\x02, $\x01\0"
5895
33.6k
    /* 2788 */ "fmovqn %icc, $\x02, $\x01\0"
5896
33.6k
    /* 2808 */ "fmovqne %icc, $\x02, $\x01\0"
5897
33.6k
    /* 2829 */ "fmovqe %icc, $\x02, $\x01\0"
5898
33.6k
    /* 2849 */ "fmovqg %icc, $\x02, $\x01\0"
5899
33.6k
    /* 2869 */ "fmovqle %icc, $\x02, $\x01\0"
5900
33.6k
    /* 2890 */ "fmovqge %icc, $\x02, $\x01\0"
5901
33.6k
    /* 2911 */ "fmovql %icc, $\x02, $\x01\0"
5902
33.6k
    /* 2931 */ "fmovqgu %icc, $\x02, $\x01\0"
5903
33.6k
    /* 2952 */ "fmovqleu %icc, $\x02, $\x01\0"
5904
33.6k
    /* 2974 */ "fmovqcc %icc, $\x02, $\x01\0"
5905
33.6k
    /* 2995 */ "fmovqcs %icc, $\x02, $\x01\0"
5906
33.6k
    /* 3016 */ "fmovqpos %icc, $\x02, $\x01\0"
5907
33.6k
    /* 3038 */ "fmovqneg %icc, $\x02, $\x01\0"
5908
33.6k
    /* 3060 */ "fmovqvc %icc, $\x02, $\x01\0"
5909
33.6k
    /* 3081 */ "fmovqvs %icc, $\x02, $\x01\0"
5910
33.6k
    /* 3102 */ "fmovqa %xcc, $\x02, $\x01\0"
5911
33.6k
    /* 3122 */ "fmovqn %xcc, $\x02, $\x01\0"
5912
33.6k
    /* 3142 */ "fmovqne %xcc, $\x02, $\x01\0"
5913
33.6k
    /* 3163 */ "fmovqe %xcc, $\x02, $\x01\0"
5914
33.6k
    /* 3183 */ "fmovqg %xcc, $\x02, $\x01\0"
5915
33.6k
    /* 3203 */ "fmovqle %xcc, $\x02, $\x01\0"
5916
33.6k
    /* 3224 */ "fmovqge %xcc, $\x02, $\x01\0"
5917
33.6k
    /* 3245 */ "fmovql %xcc, $\x02, $\x01\0"
5918
33.6k
    /* 3265 */ "fmovqgu %xcc, $\x02, $\x01\0"
5919
33.6k
    /* 3286 */ "fmovqleu %xcc, $\x02, $\x01\0"
5920
33.6k
    /* 3308 */ "fmovqcc %xcc, $\x02, $\x01\0"
5921
33.6k
    /* 3329 */ "fmovqcs %xcc, $\x02, $\x01\0"
5922
33.6k
    /* 3350 */ "fmovqpos %xcc, $\x02, $\x01\0"
5923
33.6k
    /* 3372 */ "fmovqneg %xcc, $\x02, $\x01\0"
5924
33.6k
    /* 3394 */ "fmovqvc %xcc, $\x02, $\x01\0"
5925
33.6k
    /* 3415 */ "fmovqvs %xcc, $\x02, $\x01\0"
5926
33.6k
    /* 3436 */ "fmovrdz $\x02, $\x03, $\x01\0"
5927
33.6k
    /* 3455 */ "fmovrdlez $\x02, $\x03, $\x01\0"
5928
33.6k
    /* 3476 */ "fmovrdlz $\x02, $\x03, $\x01\0"
5929
33.6k
    /* 3496 */ "fmovrdnz $\x02, $\x03, $\x01\0"
5930
33.6k
    /* 3516 */ "fmovrdgz $\x02, $\x03, $\x01\0"
5931
33.6k
    /* 3536 */ "fmovrdgez $\x02, $\x03, $\x01\0"
5932
33.6k
    /* 3557 */ "fmovrqz $\x02, $\x03, $\x01\0"
5933
33.6k
    /* 3576 */ "fmovrqlez $\x02, $\x03, $\x01\0"
5934
33.6k
    /* 3597 */ "fmovrqlz $\x02, $\x03, $\x01\0"
5935
33.6k
    /* 3617 */ "fmovrqnz $\x02, $\x03, $\x01\0"
5936
33.6k
    /* 3637 */ "fmovrqgz $\x02, $\x03, $\x01\0"
5937
33.6k
    /* 3657 */ "fmovrqgez $\x02, $\x03, $\x01\0"
5938
33.6k
    /* 3678 */ "fmovrsz $\x02, $\x03, $\x01\0"
5939
33.6k
    /* 3697 */ "fmovrslez $\x02, $\x03, $\x01\0"
5940
33.6k
    /* 3718 */ "fmovrslz $\x02, $\x03, $\x01\0"
5941
33.6k
    /* 3738 */ "fmovrsnz $\x02, $\x03, $\x01\0"
5942
33.6k
    /* 3758 */ "fmovrsgz $\x02, $\x03, $\x01\0"
5943
33.6k
    /* 3778 */ "fmovrsgez $\x02, $\x03, $\x01\0"
5944
33.6k
    /* 3799 */ "fmovsa %icc, $\x02, $\x01\0"
5945
33.6k
    /* 3819 */ "fmovsn %icc, $\x02, $\x01\0"
5946
33.6k
    /* 3839 */ "fmovsne %icc, $\x02, $\x01\0"
5947
33.6k
    /* 3860 */ "fmovse %icc, $\x02, $\x01\0"
5948
33.6k
    /* 3880 */ "fmovsg %icc, $\x02, $\x01\0"
5949
33.6k
    /* 3900 */ "fmovsle %icc, $\x02, $\x01\0"
5950
33.6k
    /* 3921 */ "fmovsge %icc, $\x02, $\x01\0"
5951
33.6k
    /* 3942 */ "fmovsl %icc, $\x02, $\x01\0"
5952
33.6k
    /* 3962 */ "fmovsgu %icc, $\x02, $\x01\0"
5953
33.6k
    /* 3983 */ "fmovsleu %icc, $\x02, $\x01\0"
5954
33.6k
    /* 4005 */ "fmovscc %icc, $\x02, $\x01\0"
5955
33.6k
    /* 4026 */ "fmovscs %icc, $\x02, $\x01\0"
5956
33.6k
    /* 4047 */ "fmovspos %icc, $\x02, $\x01\0"
5957
33.6k
    /* 4069 */ "fmovsneg %icc, $\x02, $\x01\0"
5958
33.6k
    /* 4091 */ "fmovsvc %icc, $\x02, $\x01\0"
5959
33.6k
    /* 4112 */ "fmovsvs %icc, $\x02, $\x01\0"
5960
33.6k
    /* 4133 */ "fmovsa %xcc, $\x02, $\x01\0"
5961
33.6k
    /* 4153 */ "fmovsn %xcc, $\x02, $\x01\0"
5962
33.6k
    /* 4173 */ "fmovsne %xcc, $\x02, $\x01\0"
5963
33.6k
    /* 4194 */ "fmovse %xcc, $\x02, $\x01\0"
5964
33.6k
    /* 4214 */ "fmovsg %xcc, $\x02, $\x01\0"
5965
33.6k
    /* 4234 */ "fmovsle %xcc, $\x02, $\x01\0"
5966
33.6k
    /* 4255 */ "fmovsge %xcc, $\x02, $\x01\0"
5967
33.6k
    /* 4276 */ "fmovsl %xcc, $\x02, $\x01\0"
5968
33.6k
    /* 4296 */ "fmovsgu %xcc, $\x02, $\x01\0"
5969
33.6k
    /* 4317 */ "fmovsleu %xcc, $\x02, $\x01\0"
5970
33.6k
    /* 4339 */ "fmovscc %xcc, $\x02, $\x01\0"
5971
33.6k
    /* 4360 */ "fmovscs %xcc, $\x02, $\x01\0"
5972
33.6k
    /* 4381 */ "fmovspos %xcc, $\x02, $\x01\0"
5973
33.6k
    /* 4403 */ "fmovsneg %xcc, $\x02, $\x01\0"
5974
33.6k
    /* 4425 */ "fmovsvc %xcc, $\x02, $\x01\0"
5975
33.6k
    /* 4446 */ "fmovsvs %xcc, $\x02, $\x01\0"
5976
33.6k
    /* 4467 */ "mova %icc, $\x02, $\x01\0"
5977
33.6k
    /* 4485 */ "movn %icc, $\x02, $\x01\0"
5978
33.6k
    /* 4503 */ "movne %icc, $\x02, $\x01\0"
5979
33.6k
    /* 4522 */ "move %icc, $\x02, $\x01\0"
5980
33.6k
    /* 4540 */ "movg %icc, $\x02, $\x01\0"
5981
33.6k
    /* 4558 */ "movle %icc, $\x02, $\x01\0"
5982
33.6k
    /* 4577 */ "movge %icc, $\x02, $\x01\0"
5983
33.6k
    /* 4596 */ "movl %icc, $\x02, $\x01\0"
5984
33.6k
    /* 4614 */ "movgu %icc, $\x02, $\x01\0"
5985
33.6k
    /* 4633 */ "movleu %icc, $\x02, $\x01\0"
5986
33.6k
    /* 4653 */ "movcc %icc, $\x02, $\x01\0"
5987
33.6k
    /* 4672 */ "movcs %icc, $\x02, $\x01\0"
5988
33.6k
    /* 4691 */ "movpos %icc, $\x02, $\x01\0"
5989
33.6k
    /* 4711 */ "movneg %icc, $\x02, $\x01\0"
5990
33.6k
    /* 4731 */ "movvc %icc, $\x02, $\x01\0"
5991
33.6k
    /* 4750 */ "movvs %icc, $\x02, $\x01\0"
5992
33.6k
    /* 4769 */ "movrz $\x02, $\x03, $\x01\0"
5993
33.6k
    /* 4786 */ "movrlez $\x02, $\x03, $\x01\0"
5994
33.6k
    /* 4805 */ "movrlz $\x02, $\x03, $\x01\0"
5995
33.6k
    /* 4823 */ "movrnz $\x02, $\x03, $\x01\0"
5996
33.6k
    /* 4841 */ "movrgz $\x02, $\x03, $\x01\0"
5997
33.6k
    /* 4859 */ "movrgez $\x02, $\x03, $\x01\0"
5998
33.6k
    /* 4878 */ "mova %xcc, $\x02, $\x01\0"
5999
33.6k
    /* 4896 */ "movn %xcc, $\x02, $\x01\0"
6000
33.6k
    /* 4914 */ "movne %xcc, $\x02, $\x01\0"
6001
33.6k
    /* 4933 */ "move %xcc, $\x02, $\x01\0"
6002
33.6k
    /* 4951 */ "movg %xcc, $\x02, $\x01\0"
6003
33.6k
    /* 4969 */ "movle %xcc, $\x02, $\x01\0"
6004
33.6k
    /* 4988 */ "movge %xcc, $\x02, $\x01\0"
6005
33.6k
    /* 5007 */ "movl %xcc, $\x02, $\x01\0"
6006
33.6k
    /* 5025 */ "movgu %xcc, $\x02, $\x01\0"
6007
33.6k
    /* 5044 */ "movleu %xcc, $\x02, $\x01\0"
6008
33.6k
    /* 5064 */ "movcc %xcc, $\x02, $\x01\0"
6009
33.6k
    /* 5083 */ "movcs %xcc, $\x02, $\x01\0"
6010
33.6k
    /* 5102 */ "movpos %xcc, $\x02, $\x01\0"
6011
33.6k
    /* 5122 */ "movneg %xcc, $\x02, $\x01\0"
6012
33.6k
    /* 5142 */ "movvc %xcc, $\x02, $\x01\0"
6013
33.6k
    /* 5161 */ "movvs %xcc, $\x02, $\x01\0"
6014
33.6k
    /* 5180 */ "tst $\x02\0"
6015
33.6k
    /* 5187 */ "mov $\x03, $\x01\0"
6016
33.6k
    /* 5198 */ "restore\0"
6017
33.6k
    /* 5206 */ "ret\0"
6018
33.6k
    /* 5210 */ "retl\0"
6019
33.6k
    /* 5215 */ "save\0"
6020
33.6k
    /* 5220 */ "cmp $\x02, $\x03\0"
6021
33.6k
    /* 5231 */ "ta %icc, $\x02\0"
6022
33.6k
    /* 5243 */ "ta %icc, $\x01 + $\x02\0"
6023
33.6k
    /* 5260 */ "tn %icc, $\x02\0"
6024
33.6k
    /* 5272 */ "tn %icc, $\x01 + $\x02\0"
6025
33.6k
    /* 5289 */ "tne %icc, $\x02\0"
6026
33.6k
    /* 5302 */ "tne %icc, $\x01 + $\x02\0"
6027
33.6k
    /* 5320 */ "te %icc, $\x02\0"
6028
33.6k
    /* 5332 */ "te %icc, $\x01 + $\x02\0"
6029
33.6k
    /* 5349 */ "tg %icc, $\x02\0"
6030
33.6k
    /* 5361 */ "tg %icc, $\x01 + $\x02\0"
6031
33.6k
    /* 5378 */ "tle %icc, $\x02\0"
6032
33.6k
    /* 5391 */ "tle %icc, $\x01 + $\x02\0"
6033
33.6k
    /* 5409 */ "tge %icc, $\x02\0"
6034
33.6k
    /* 5422 */ "tge %icc, $\x01 + $\x02\0"
6035
33.6k
    /* 5440 */ "tl %icc, $\x02\0"
6036
33.6k
    /* 5452 */ "tl %icc, $\x01 + $\x02\0"
6037
33.6k
    /* 5469 */ "tgu %icc, $\x02\0"
6038
33.6k
    /* 5482 */ "tgu %icc, $\x01 + $\x02\0"
6039
33.6k
    /* 5500 */ "tleu %icc, $\x02\0"
6040
33.6k
    /* 5514 */ "tleu %icc, $\x01 + $\x02\0"
6041
33.6k
    /* 5533 */ "tcc %icc, $\x02\0"
6042
33.6k
    /* 5546 */ "tcc %icc, $\x01 + $\x02\0"
6043
33.6k
    /* 5564 */ "tcs %icc, $\x02\0"
6044
33.6k
    /* 5577 */ "tcs %icc, $\x01 + $\x02\0"
6045
33.6k
    /* 5595 */ "tpos %icc, $\x02\0"
6046
33.6k
    /* 5609 */ "tpos %icc, $\x01 + $\x02\0"
6047
33.6k
    /* 5628 */ "tneg %icc, $\x02\0"
6048
33.6k
    /* 5642 */ "tneg %icc, $\x01 + $\x02\0"
6049
33.6k
    /* 5661 */ "tvc %icc, $\x02\0"
6050
33.6k
    /* 5674 */ "tvc %icc, $\x01 + $\x02\0"
6051
33.6k
    /* 5692 */ "tvs %icc, $\x02\0"
6052
33.6k
    /* 5705 */ "tvs %icc, $\x01 + $\x02\0"
6053
33.6k
    /* 5723 */ "ta $\x02\0"
6054
33.6k
    /* 5729 */ "ta $\x01 + $\x02\0"
6055
33.6k
    /* 5740 */ "tn $\x02\0"
6056
33.6k
    /* 5746 */ "tn $\x01 + $\x02\0"
6057
33.6k
    /* 5757 */ "tne $\x02\0"
6058
33.6k
    /* 5764 */ "tne $\x01 + $\x02\0"
6059
33.6k
    /* 5776 */ "te $\x02\0"
6060
33.6k
    /* 5782 */ "te $\x01 + $\x02\0"
6061
33.6k
    /* 5793 */ "tg $\x02\0"
6062
33.6k
    /* 5799 */ "tg $\x01 + $\x02\0"
6063
33.6k
    /* 5810 */ "tle $\x02\0"
6064
33.6k
    /* 5817 */ "tle $\x01 + $\x02\0"
6065
33.6k
    /* 5829 */ "tge $\x02\0"
6066
33.6k
    /* 5836 */ "tge $\x01 + $\x02\0"
6067
33.6k
    /* 5848 */ "tl $\x02\0"
6068
33.6k
    /* 5854 */ "tl $\x01 + $\x02\0"
6069
33.6k
    /* 5865 */ "tgu $\x02\0"
6070
33.6k
    /* 5872 */ "tgu $\x01 + $\x02\0"
6071
33.6k
    /* 5884 */ "tleu $\x02\0"
6072
33.6k
    /* 5892 */ "tleu $\x01 + $\x02\0"
6073
33.6k
    /* 5905 */ "tcc $\x02\0"
6074
33.6k
    /* 5912 */ "tcc $\x01 + $\x02\0"
6075
33.6k
    /* 5924 */ "tcs $\x02\0"
6076
33.6k
    /* 5931 */ "tcs $\x01 + $\x02\0"
6077
33.6k
    /* 5943 */ "tpos $\x02\0"
6078
33.6k
    /* 5951 */ "tpos $\x01 + $\x02\0"
6079
33.6k
    /* 5964 */ "tneg $\x02\0"
6080
33.6k
    /* 5972 */ "tneg $\x01 + $\x02\0"
6081
33.6k
    /* 5985 */ "tvc $\x02\0"
6082
33.6k
    /* 5992 */ "tvc $\x01 + $\x02\0"
6083
33.6k
    /* 6004 */ "tvs $\x02\0"
6084
33.6k
    /* 6011 */ "tvs $\x01 + $\x02\0"
6085
33.6k
    /* 6023 */ "ta %xcc, $\x02\0"
6086
33.6k
    /* 6035 */ "ta %xcc, $\x01 + $\x02\0"
6087
33.6k
    /* 6052 */ "tn %xcc, $\x02\0"
6088
33.6k
    /* 6064 */ "tn %xcc, $\x01 + $\x02\0"
6089
33.6k
    /* 6081 */ "tne %xcc, $\x02\0"
6090
33.6k
    /* 6094 */ "tne %xcc, $\x01 + $\x02\0"
6091
33.6k
    /* 6112 */ "te %xcc, $\x02\0"
6092
33.6k
    /* 6124 */ "te %xcc, $\x01 + $\x02\0"
6093
33.6k
    /* 6141 */ "tg %xcc, $\x02\0"
6094
33.6k
    /* 6153 */ "tg %xcc, $\x01 + $\x02\0"
6095
33.6k
    /* 6170 */ "tle %xcc, $\x02\0"
6096
33.6k
    /* 6183 */ "tle %xcc, $\x01 + $\x02\0"
6097
33.6k
    /* 6201 */ "tge %xcc, $\x02\0"
6098
33.6k
    /* 6214 */ "tge %xcc, $\x01 + $\x02\0"
6099
33.6k
    /* 6232 */ "tl %xcc, $\x02\0"
6100
33.6k
    /* 6244 */ "tl %xcc, $\x01 + $\x02\0"
6101
33.6k
    /* 6261 */ "tgu %xcc, $\x02\0"
6102
33.6k
    /* 6274 */ "tgu %xcc, $\x01 + $\x02\0"
6103
33.6k
    /* 6292 */ "tleu %xcc, $\x02\0"
6104
33.6k
    /* 6306 */ "tleu %xcc, $\x01 + $\x02\0"
6105
33.6k
    /* 6325 */ "tcc %xcc, $\x02\0"
6106
33.6k
    /* 6338 */ "tcc %xcc, $\x01 + $\x02\0"
6107
33.6k
    /* 6356 */ "tcs %xcc, $\x02\0"
6108
33.6k
    /* 6369 */ "tcs %xcc, $\x01 + $\x02\0"
6109
33.6k
    /* 6387 */ "tpos %xcc, $\x02\0"
6110
33.6k
    /* 6401 */ "tpos %xcc, $\x01 + $\x02\0"
6111
33.6k
    /* 6420 */ "tneg %xcc, $\x02\0"
6112
33.6k
    /* 6434 */ "tneg %xcc, $\x01 + $\x02\0"
6113
33.6k
    /* 6453 */ "tvc %xcc, $\x02\0"
6114
33.6k
    /* 6466 */ "tvc %xcc, $\x01 + $\x02\0"
6115
33.6k
    /* 6484 */ "tvs %xcc, $\x02\0"
6116
33.6k
    /* 6497 */ "tvs %xcc, $\x01 + $\x02\0"
6117
33.6k
    /* 6515 */ "fcmpd $\x02, $\x03\0"
6118
33.6k
    /* 6528 */ "fcmped $\x02, $\x03\0"
6119
33.6k
    /* 6542 */ "fcmpeq $\x02, $\x03\0"
6120
33.6k
    /* 6556 */ "fcmpes $\x02, $\x03\0"
6121
33.6k
    /* 6570 */ "fcmpq $\x02, $\x03\0"
6122
33.6k
    /* 6583 */ "fcmps $\x02, $\x03\0"
6123
33.6k
    /* 6596 */ "fmovda $\x02, $\x03, $\x01\0"
6124
33.6k
    /* 6614 */ "fmovdn $\x02, $\x03, $\x01\0"
6125
33.6k
    /* 6632 */ "fmovdu $\x02, $\x03, $\x01\0"
6126
33.6k
    /* 6650 */ "fmovdg $\x02, $\x03, $\x01\0"
6127
33.6k
    /* 6668 */ "fmovdug $\x02, $\x03, $\x01\0"
6128
33.6k
    /* 6687 */ "fmovdl $\x02, $\x03, $\x01\0"
6129
33.6k
    /* 6705 */ "fmovdul $\x02, $\x03, $\x01\0"
6130
33.6k
    /* 6724 */ "fmovdlg $\x02, $\x03, $\x01\0"
6131
33.6k
    /* 6743 */ "fmovdne $\x02, $\x03, $\x01\0"
6132
33.6k
    /* 6762 */ "fmovde $\x02, $\x03, $\x01\0"
6133
33.6k
    /* 6780 */ "fmovdue $\x02, $\x03, $\x01\0"
6134
33.6k
    /* 6799 */ "fmovdge $\x02, $\x03, $\x01\0"
6135
33.6k
    /* 6818 */ "fmovduge $\x02, $\x03, $\x01\0"
6136
33.6k
    /* 6838 */ "fmovdle $\x02, $\x03, $\x01\0"
6137
33.6k
    /* 6857 */ "fmovdule $\x02, $\x03, $\x01\0"
6138
33.6k
    /* 6877 */ "fmovdo $\x02, $\x03, $\x01\0"
6139
33.6k
    /* 6895 */ "fmovqa $\x02, $\x03, $\x01\0"
6140
33.6k
    /* 6913 */ "fmovqn $\x02, $\x03, $\x01\0"
6141
33.6k
    /* 6931 */ "fmovqu $\x02, $\x03, $\x01\0"
6142
33.6k
    /* 6949 */ "fmovqg $\x02, $\x03, $\x01\0"
6143
33.6k
    /* 6967 */ "fmovqug $\x02, $\x03, $\x01\0"
6144
33.6k
    /* 6986 */ "fmovql $\x02, $\x03, $\x01\0"
6145
33.6k
    /* 7004 */ "fmovqul $\x02, $\x03, $\x01\0"
6146
33.6k
    /* 7023 */ "fmovqlg $\x02, $\x03, $\x01\0"
6147
33.6k
    /* 7042 */ "fmovqne $\x02, $\x03, $\x01\0"
6148
33.6k
    /* 7061 */ "fmovqe $\x02, $\x03, $\x01\0"
6149
33.6k
    /* 7079 */ "fmovque $\x02, $\x03, $\x01\0"
6150
33.6k
    /* 7098 */ "fmovqge $\x02, $\x03, $\x01\0"
6151
33.6k
    /* 7117 */ "fmovquge $\x02, $\x03, $\x01\0"
6152
33.6k
    /* 7137 */ "fmovqle $\x02, $\x03, $\x01\0"
6153
33.6k
    /* 7156 */ "fmovqule $\x02, $\x03, $\x01\0"
6154
33.6k
    /* 7176 */ "fmovqo $\x02, $\x03, $\x01\0"
6155
33.6k
    /* 7194 */ "fmovsa $\x02, $\x03, $\x01\0"
6156
33.6k
    /* 7212 */ "fmovsn $\x02, $\x03, $\x01\0"
6157
33.6k
    /* 7230 */ "fmovsu $\x02, $\x03, $\x01\0"
6158
33.6k
    /* 7248 */ "fmovsg $\x02, $\x03, $\x01\0"
6159
33.6k
    /* 7266 */ "fmovsug $\x02, $\x03, $\x01\0"
6160
33.6k
    /* 7285 */ "fmovsl $\x02, $\x03, $\x01\0"
6161
33.6k
    /* 7303 */ "fmovsul $\x02, $\x03, $\x01\0"
6162
33.6k
    /* 7322 */ "fmovslg $\x02, $\x03, $\x01\0"
6163
33.6k
    /* 7341 */ "fmovsne $\x02, $\x03, $\x01\0"
6164
33.6k
    /* 7360 */ "fmovse $\x02, $\x03, $\x01\0"
6165
33.6k
    /* 7378 */ "fmovsue $\x02, $\x03, $\x01\0"
6166
33.6k
    /* 7397 */ "fmovsge $\x02, $\x03, $\x01\0"
6167
33.6k
    /* 7416 */ "fmovsuge $\x02, $\x03, $\x01\0"
6168
33.6k
    /* 7436 */ "fmovsle $\x02, $\x03, $\x01\0"
6169
33.6k
    /* 7455 */ "fmovsule $\x02, $\x03, $\x01\0"
6170
33.6k
    /* 7475 */ "fmovso $\x02, $\x03, $\x01\0"
6171
33.6k
    /* 7493 */ "mova $\x02, $\x03, $\x01\0"
6172
33.6k
    /* 7509 */ "movn $\x02, $\x03, $\x01\0"
6173
33.6k
    /* 7525 */ "movu $\x02, $\x03, $\x01\0"
6174
33.6k
    /* 7541 */ "movg $\x02, $\x03, $\x01\0"
6175
33.6k
    /* 7557 */ "movug $\x02, $\x03, $\x01\0"
6176
33.6k
    /* 7574 */ "movl $\x02, $\x03, $\x01\0"
6177
33.6k
    /* 7590 */ "movul $\x02, $\x03, $\x01\0"
6178
33.6k
    /* 7607 */ "movlg $\x02, $\x03, $\x01\0"
6179
33.6k
    /* 7624 */ "movne $\x02, $\x03, $\x01\0"
6180
33.6k
    /* 7641 */ "move $\x02, $\x03, $\x01\0"
6181
33.6k
    /* 7657 */ "movue $\x02, $\x03, $\x01\0"
6182
33.6k
    /* 7674 */ "movge $\x02, $\x03, $\x01\0"
6183
33.6k
    /* 7691 */ "movuge $\x02, $\x03, $\x01\0"
6184
33.6k
    /* 7709 */ "movle $\x02, $\x03, $\x01\0"
6185
33.6k
    /* 7726 */ "movule $\x02, $\x03, $\x01\0"
6186
33.6k
    /* 7744 */ "movo $\x02, $\x03, $\x01\0"
6187
33.6k
  ;
6188
6189
33.6k
#ifndef NDEBUG
6190
  //static struct SortCheck {
6191
  //  SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
6192
  //    assert(std::is_sorted(
6193
  //               OpToPatterns.begin(), OpToPatterns.end(),
6194
  //               [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
6195
  //                 return L.Opcode < R.Opcode;
6196
  //               }) &&
6197
  //           "tablegen failed to sort opcode patterns");
6198
  //  }
6199
  //} sortCheckVar(OpToPatterns);
6200
33.6k
#endif
6201
6202
33.6k
  AliasMatchingData M = {
6203
33.6k
    OpToPatterns,
6204
33.6k
    Patterns,
6205
33.6k
    Conds,
6206
33.6k
    AsmStrings,
6207
33.6k
    NULL,
6208
33.6k
  };
6209
33.6k
  const char *AsmString = matchAliasPatterns(MI, &M);
6210
33.6k
  if (!AsmString) return false;
6211
6212
2.33k
  unsigned I = 0;
6213
12.3k
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
6214
10.0k
         AsmString[I] != '$' && AsmString[I] != '\0')
6215
10.0k
    ++I;
6216
2.33k
  SStream_concat1(OS, '\t');
6217
2.33k
  char *substr = malloc(I+1);
6218
2.33k
  memcpy(substr, AsmString, I);
6219
2.33k
  substr[I] = '\0';
6220
2.33k
  SStream_concat0(OS, substr);
6221
2.33k
  free(substr);
6222
2.33k
  if (AsmString[I] != '\0') {
6223
2.33k
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
6224
2.33k
      SStream_concat1(OS, '\t');
6225
2.33k
      ++I;
6226
2.33k
    }
6227
9.89k
    do {
6228
9.89k
      if (AsmString[I] == '$') {
6229
4.23k
        ++I;
6230
4.23k
        if (AsmString[I] == (char)0xff) {
6231
0
          ++I;
6232
0
          int OpIdx = AsmString[I++] - 1;
6233
0
          int PrintMethodIdx = AsmString[I++] - 1;
6234
0
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
6235
0
        } else
6236
4.23k
          printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
6237
5.65k
      } else {
6238
5.65k
        SStream_concat1(OS, AsmString[I++]);
6239
5.65k
      }
6240
9.89k
    } while (AsmString[I] != '\0');
6241
2.33k
  }
6242
6243
2.33k
  return true;
6244
#else
6245
  return false;
6246
#endif // CAPSTONE_DIET
6247
33.6k
}
6248
6249
static void printCustomAliasOperand(
6250
         MCInst *MI, uint64_t Address, unsigned OpIdx,
6251
         unsigned PrintMethodIdx,
6252
0
         SStream *OS) {
6253
0
#ifndef CAPSTONE_DIET
6254
0
  CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
6255
0
#endif // CAPSTONE_DIET
6256
0
}
6257
6258
#endif // PRINT_ALIAS_INSTR