/src/capstonenext/arch/M68K/M68KInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */

#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>

#include "M68KInstPrinter.h"

#include "M68KDisassembler.h"

#include "../../cs_priv.h"
#include "../../Mapping.h"
#include "../../utils.h"

#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"

#ifndef CAPSTONE_DIET
static const char s_spacing[] = " ";

static const char *const s_reg_names[] = {
  "invalid", "d0",    "d1",    "d2",  "d3",  "d4",   "d5",   "d6",
  "d7",    "a0",    "a1",    "a2",  "a3",  "a4",   "a5",   "a6",
  "a7",    "fp0",   "fp1",   "fp2", "fp3", "fp4",  "fp5",  "fp6",
  "fp7",     "pc",    "sr",    "ccr", "sfc", "dfc",  "usp",  "vbr",
  "cacr",    "caar",  "msp",   "isp", "tc",  "itt0", "itt1", "dtt0",
  "dtt1",    "mmusr", "urp",   "srp",

  "fpcr",    "fpsr",  "fpiar",
};

static const char *const s_instruction_names[] = {
  "invalid",  "abcd", "add",      "adda", "addi",      "addq",
  "addx",     "and",  "andi",     "asl",  "asr",       "bhs",
  "blo",      "bhi",  "bls",      "bcc",  "bcs",       "bne",
  "beq",      "bvc",  "bvs",      "bpl",  "bmi",       "bge",
  "blt",      "bgt",  "ble",      "bra",  "bsr",       "bchg",
  "bclr",     "bset", "btst",     "bfchg",  "bfclr",     "bfexts",
  "bfextu",   "bfffo",  "bfins",    "bfset",  "bftst",     "bkpt",
  "callm",    "cas",  "cas2",     "chk",  "chk2",      "clr",
  "cmp",      "cmpa", "cmpi",     "cmpm", "cmp2",      "cinvl",
  "cinvp",    "cinva",  "cpushl",   "cpushp", "cpusha",    "dbt",
  "dbf",      "dbhi", "dbls",     "dbcc", "dbcs",      "dbne",
  "dbeq",     "dbvc", "dbvs",     "dbpl", "dbmi",      "dbge",
  "dblt",     "dbgt", "dble",     "dbra", "divs",      "divsl",
  "divu",     "divul",  "eor",      "eori", "exg",       "ext",
  "extb",     "fabs", "fsabs",    "fdabs",  "facos",     "fadd",
  "fsadd",    "fdadd",  "fasin",    "fatan",  "fatanh",    "fbf",
  "fbeq",     "fbogt",  "fboge",    "fbolt",  "fbole",     "fbogl",
  "fbor",     "fbun", "fbueq",    "fbugt",  "fbuge",     "fbult",
  "fbule",    "fbne", "fbt",      "fbsf", "fbseq",     "fbgt",
  "fbge",     "fblt", "fble",     "fbgl", "fbgle",     "fbngle",
  "fbngl",    "fbnle",  "fbnlt",    "fbnge",  "fbngt",     "fbsne",
  "fbst",     "fcmp", "fcos",     "fcosh",  "fdbf",      "fdbeq",
  "fdbogt",   "fdboge", "fdbolt",   "fdbole", "fdbogl",    "fdbor",
  "fdbun",    "fdbueq", "fdbugt",   "fdbuge", "fdbult",    "fdbule",
  "fdbne",    "fdbt", "fdbsf",    "fdbseq", "fdbgt",     "fdbge",
  "fdblt",    "fdble",  "fdbgl",    "fdbgle", "fdbngle",   "fdbngl",
  "fdbnle",   "fdbnlt", "fdbnge",   "fdbngt", "fdbsne",    "fdbst",
  "fdiv",     "fsdiv",  "fddiv",    "fetox",  "fetoxm1",   "fgetexp",
  "fgetman",  "fint", "fintrz",   "flog10", "flog2",     "flogn",
  "flognp1",  "fmod", "fmove",    "fsmove", "fdmove",    "fmovecr",
  "fmovem",   "fmul", "fsmul",    "fdmul",  "fneg",      "fsneg",
  "fdneg",    "fnop", "frem",     "frestore", "fsave",     "fscale",
  "fsgldiv",  "fsglmul",  "fsin",     "fsincos",  "fsinh",     "fsqrt",
  "fssqrt",   "fdsqrt", "fsf",      "fseq", "fsogt",     "fsoge",
  "fsolt",    "fsole",  "fsogl",    "fsor", "fsun",      "fsueq",
  "fsugt",    "fsuge",  "fsult",    "fsule",  "fsne",      "fst",
  "fssf",     "fsseq",  "fsgt",     "fsge", "fslt",      "fsle",
  "fsgl",     "fsgle",  "fsngle",   "fsngl",  "fsnle",     "fsnlt",
  "fsnge",    "fsngt",  "fssne",    "fsst", "fsub",      "fssub",
  "fdsub",    "ftan", "ftanh",    "ftentox",  "ftrapf",    "ftrapeq",
  "ftrapogt", "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl",  "ftrapor",
  "ftrapun",  "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult",  "ftrapule",
  "ftrapne",  "ftrapt", "ftrapsf",  "ftrapseq", "ftrapgt",   "ftrapge",
  "ftraplt",  "ftraple",  "ftrapgl",  "ftrapgle", "ftrapngle", "ftrapngl",
  "ftrapnle", "ftrapnlt", "ftrapnge", "ftrapngt", "ftrapsne",  "ftrapst",
  "ftst",     "ftwotox",  "halt",     "illegal",  "jmp",       "jsr",
  "lea",      "link", "lpstop",   "lsl",  "lsr",       "move",
  "movea",    "movec",  "movem",    "movep",  "moveq",     "moves",
  "move16",   "muls", "mulu",     "nbcd", "neg",       "negx",
  "nop",      "not",  "or",     "ori",  "pack",      "pea",
  "pflush",   "pflusha",  "pflushan", "pflushn",  "ploadr",    "ploadw",
  "plpar",    "plpaw",  "pmove",    "pmovefd",  "ptestr",    "ptestw",
  "pulse",    "rems", "remu",     "reset",  "rol",       "ror",
  "roxl",     "roxr", "rtd",      "rte",  "rtm",       "rtr",
  "rts",      "sbcd", "st",     "sf", "shi",       "sls",
  "scc",      "shs",  "scs",      "slo",  "sne",       "seq",
  "svc",      "svs",  "spl",      "smi",  "sge",       "slt",
  "sgt",      "sle",  "stop",     "sub",  "suba",      "subi",
  "subq",     "subx", "swap",     "tas",  "trap",      "trapv",
  "trapt",    "trapf",  "traphi",   "trapls", "trapcc",    "traphs",
  "trapcs",   "traplo", "trapne",   "trapeq", "trapvc",    "trapvs",
  "trappl",   "trapmi", "trapge",   "traplt", "trapgt",    "traple",
  "tst",      "unlk", "unpk",
};
#endif

#ifndef CAPSTONE_DIET
static const char *getRegName(m68k_reg reg)
{
  return s_reg_names[(int)reg];
}

static void printRegbitsRange(char *buffer, size_t buf_len, uint32_t data,
            const char *prefix)
{
  unsigned int first = 0;
  unsigned int run_length = 0;
  int i;

  for (i = 0; i < 8; ++i) {
    if (data & (1 << i)) {
      first = i;
      run_length = 0;

      while (i < 7 && (data & (1 << (i + 1)))) {
        i++;
        run_length++;
      }

      if (buffer[0] != 0)
        strncat(buffer, "/", buf_len - 1);

      snprintf(buffer + strlen(buffer), buf_len, "%s%d",
         prefix, first);
      if (run_length > 0)
        snprintf(buffer + strlen(buffer), buf_len,
           "-%s%d", prefix, first + run_length);
    }
  }
}

static void registerBits(SStream *O, const cs_m68k_op *op)
{
  char buffer[128];
  unsigned int data = op->register_bits;

  buffer[0] = 0;

  if (!data) {
    SStream_concat(O, "%s", "#$0");
    return;
  }

  printRegbitsRange(buffer, sizeof(buffer), data & 0xff, "d");
  printRegbitsRange(buffer, sizeof(buffer), (data >> 8) & 0xff, "a");
  printRegbitsRange(buffer, sizeof(buffer), (data >> 16) & 0xff, "fp");

  SStream_concat(O, "%s", buffer);
}

static void registerPair(SStream *O, const cs_m68k_op *op)
{
  SStream_concat(O, "%s:%s", s_reg_names[op->reg_pair.reg_0],
           s_reg_names[op->reg_pair.reg_1]);
}

static void printAddressingMode(SStream *O, unsigned int pc,
        const cs_m68k *inst, const cs_m68k_op *op)
{
  switch (op->address_mode) {
  case M68K_AM_NONE:
    switch (op->type) {
    case M68K_OP_REG_BITS:
      registerBits(O, op);
      break;
    case M68K_OP_REG_PAIR:
      registerPair(O, op);
      break;
    case M68K_OP_REG:
      SStream_concat(O, "%s", s_reg_names[op->reg]);
      break;
    default:
      break;
    }
    break;

  case M68K_AM_REG_DIRECT_DATA:
    SStream_concat(O, "d%d", (op->reg - M68K_REG_D0));
    break;
  case M68K_AM_REG_DIRECT_ADDR:
    SStream_concat(O, "a%d", (op->reg - M68K_REG_A0));
    break;
  case M68K_AM_REGI_ADDR:
    SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0));
    break;
  case M68K_AM_REGI_ADDR_POST_INC:
    SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0));
    break;
  case M68K_AM_REGI_ADDR_PRE_DEC:
    SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0));
    break;
  case M68K_AM_REGI_ADDR_DISP:
    SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "",
             abs(op->mem.disp),
             (op->mem.base_reg - M68K_REG_A0));
    break;
  case M68K_AM_PCI_DISP:
    SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp);
    break;
  case M68K_AM_ABSOLUTE_DATA_SHORT:
    SStream_concat(O, "$%x.w", op->imm);
    break;
  case M68K_AM_ABSOLUTE_DATA_LONG:
    SStream_concat(O, "$%x.l", op->imm);
    break;
  case M68K_AM_IMMEDIATE:
    if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
#if defined(_KERNEL_MODE)
      // Issue #681: Windows kernel does not support formatting float point
      SStream_concat(O, "#<float_point_unsupported>");
      break;
#else
      if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
        SStream_concat(O, "#%f", op->simm);
      else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE)
        SStream_concat(O, "#%f", op->dimm);
      else
        SStream_concat(O, "#<unsupported>");
      break;
#endif
    }
    SStream_concat(O, "#$%x", op->imm);
    break;
  case M68K_AM_PCI_INDEX_8_BIT_DISP:
    SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp,
             s_spacing, getRegName(op->mem.index_reg),
             op->mem.index_size ? 'l' : 'w');
    break;
  case M68K_AM_AREGI_INDEX_8_BIT_DISP:
    SStream_concat(O, "%s$%x(%s,%s%s.%c)",
             op->mem.disp < 0 ? "-" : "", abs(op->mem.disp),
             getRegName(op->mem.base_reg), s_spacing,
             getRegName(op->mem.index_reg),
             op->mem.index_size ? 'l' : 'w');
    break;
  case M68K_AM_PCI_INDEX_BASE_DISP:
  case M68K_AM_AREGI_INDEX_BASE_DISP:

    if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
      SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
    } else {
      if (op->mem.in_disp > 0)
        SStream_concat(O, "$%x", op->mem.in_disp);
    }

    SStream_concat0(O, "(");

    if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
      SStream_concat(O, "pc,%s.%c",
               getRegName(op->mem.index_reg),
               op->mem.index_size ? 'l' : 'w');
    } else {
      if (op->mem.base_reg != M68K_REG_INVALID)
        SStream_concat(O, "a%d,%s",
                 op->mem.base_reg - M68K_REG_A0,
                 s_spacing);
      SStream_concat(O, "%s.%c",
               getRegName(op->mem.index_reg),
               op->mem.index_size ? 'l' : 'w');
    }

    if (op->mem.scale > 0)
      SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing,
               op->mem.scale);
    else
      SStream_concat0(O, ")");
    break;
    // It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code
    // easier and that is what actually happens when the code is executed anyway.

  case M68K_AM_PC_MEMI_POST_INDEX:
  case M68K_AM_PC_MEMI_PRE_INDEX:
  case M68K_AM_MEMI_PRE_INDEX:
  case M68K_AM_MEMI_POST_INDEX:
    SStream_concat0(O, "([");

    if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX ||
        op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) {
      SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
    } else {
      if (op->mem.in_disp > 0)
        SStream_concat(O, "$%x", op->mem.in_disp);
    }

    if (op->mem.base_reg != M68K_REG_INVALID) {
      if (op->mem.in_disp > 0)
        SStream_concat(O, ",%s%s", s_spacing,
                 getRegName(op->mem.base_reg));
      else
        SStream_concat(O, "%s",
                 getRegName(op->mem.base_reg));
    }

    if (op->address_mode == M68K_AM_MEMI_POST_INDEX ||
        op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
      SStream_concat0(O, "]");

    if (op->mem.index_reg != M68K_REG_INVALID)
      SStream_concat(O, ",%s%s.%c", s_spacing,
               getRegName(op->mem.index_reg),
               op->mem.index_size ? 'l' : 'w');

    if (op->mem.scale > 0)
      SStream_concat(O, "%s*%s%d", s_spacing, s_spacing,
               op->mem.scale);

    if (op->address_mode == M68K_AM_MEMI_PRE_INDEX ||
        op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX)
      SStream_concat0(O, "]");

    if (op->mem.out_disp > 0)
      SStream_concat(O, ",%s$%x", s_spacing,
               op->mem.out_disp);

    SStream_concat0(O, ")");
    break;
  case M68K_AM_BRANCH_DISPLACEMENT:
    SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp);
  default:
    break;
  }

  if (op->mem.bitfield)
    SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width);
}
#endif

#define m68k_sizeof_array(array) (int)(sizeof(array) / sizeof(array[0]))
#define m68k_min(a, b) (a < b) ? a : b

void M68K_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
{
#ifndef CAPSTONE_DIET
  m68k_info *info = (m68k_info *)PrinterInfo;
  cs_m68k *ext = &info->extension;
  cs_detail *detail = NULL;
  int i = 0;

  detail = MI->flat_insn->detail;
  if (detail) {
    int regs_read_count =
      m68k_min(m68k_sizeof_array(detail->regs_read),
         info->regs_read_count);
    int regs_write_count =
      m68k_min(m68k_sizeof_array(detail->regs_write),
         info->regs_write_count);
    int groups_count = m68k_min(m68k_sizeof_array(detail->groups),
              info->groups_count);

    memcpy(&detail->m68k, ext, sizeof(cs_m68k));

    memcpy(&detail->regs_read, &info->regs_read,
           regs_read_count * sizeof(info->regs_read[0]));
    detail->regs_read_count = regs_read_count;

    memcpy(&detail->regs_write, &info->regs_write,
           regs_write_count * sizeof(info->regs_write[0]));
    detail->regs_write_count = regs_write_count;

    memcpy(&detail->groups, &info->groups, groups_count);
    detail->groups_count = groups_count;
  }

  if (MI->Opcode == M68K_INS_INVALID) {
    if (ext->op_count)
      SStream_concat(O, "dc.w $%x", ext->operands[0].imm);
    else
      SStream_concat(O, "dc.w $<unknown>");
    return;
  }

  SStream_concat0(O, (char *)s_instruction_names[MI->Opcode]);

  switch (ext->op_size.type) {
  case M68K_SIZE_TYPE_INVALID:
    break;

  case M68K_SIZE_TYPE_CPU:
    switch (ext->op_size.cpu_size) {
    case M68K_CPU_SIZE_BYTE:
      SStream_concat0(O, ".b");
      break;
    case M68K_CPU_SIZE_WORD:
      SStream_concat0(O, ".w");
      break;
    case M68K_CPU_SIZE_LONG:
      SStream_concat0(O, ".l");
      break;
    case M68K_CPU_SIZE_NONE:
      break;
    }
    break;

  case M68K_SIZE_TYPE_FPU:
    switch (ext->op_size.fpu_size) {
    case M68K_FPU_SIZE_SINGLE:
      SStream_concat0(O, ".s");
      break;
    case M68K_FPU_SIZE_DOUBLE:
      SStream_concat0(O, ".d");
      break;
    case M68K_FPU_SIZE_EXTENDED:
      SStream_concat0(O, ".x");
      break;
    case M68K_FPU_SIZE_NONE:
      break;
    }
    break;
  }

  SStream_concat0(O, " ");

  // this one is a bit spacial so we do special things

  if (MI->Opcode == M68K_INS_CAS2) {
    int reg_value_0, reg_value_1;
    printAddressingMode(O, info->pc, ext, &ext->operands[0]);
    SStream_concat0(O, ",");
    printAddressingMode(O, info->pc, ext, &ext->operands[1]);
    SStream_concat0(O, ",");
    reg_value_0 = ext->operands[2].register_bits >> 4;
    reg_value_1 = ext->operands[2].register_bits & 0xf;
    SStream_concat(O, "(%s):(%s)",
             s_reg_names[M68K_REG_D0 + reg_value_0],
             s_reg_names[M68K_REG_D0 + reg_value_1]);
    return;
  }

  for (i = 0; i < ext->op_count; ++i) {
    printAddressingMode(O, info->pc, ext, &ext->operands[i]);
    if ((i + 1) != ext->op_count)
      SStream_concat(O, ",%s", s_spacing);
  }
#endif
}

const char *M68K_reg_name(csh handle, unsigned int reg)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (reg >= ARR_SIZE(s_reg_names)) {
    return NULL;
  }
  return s_reg_names[(int)reg];
#endif
}

void M68K_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
  insn->id = id; // These id's matches for 68k
}

const char *M68K_insn_name(csh handle, unsigned int id)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  return s_instruction_names[id];
#endif
}

#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
  { M68K_GRP_INVALID, NULL },
  { M68K_GRP_JUMP, "jump" },
  { M68K_GRP_RET, "ret" },
  { M68K_GRP_IRET, "iret" },
  { M68K_GRP_BRANCH_RELATIVE, "branch_relative" },
};
#endif

const char *M68K_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
  return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
  return NULL;
#endif
}

#ifndef CAPSTONE_DIET
void M68K_reg_access(const cs_insn *insn, cs_regs regs_read,
         uint8_t *regs_read_count, cs_regs regs_write,
         uint8_t *regs_write_count)
{
  uint8_t read_count, write_count;

  read_count = insn->detail->regs_read_count;
  write_count = insn->detail->regs_write_count;

  // implicit registers
  memcpy(regs_read, insn->detail->regs_read,
         read_count * sizeof(insn->detail->regs_read[0]));
  memcpy(regs_write, insn->detail->regs_write,
         write_count * sizeof(insn->detail->regs_write[0]));

  *regs_read_count = read_count;
  *regs_write_count = write_count;
}
#endif

Coverage Report

Created: 2025-10-28 07:02

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
3
4		#include <stdio.h> // DEBUG
5		#include <stdlib.h>
6		#include <string.h>
7
8		#include "M68KInstPrinter.h"
9
10		#include "M68KDisassembler.h"
11
12		#include "../../cs_priv.h"
13		#include "../../Mapping.h"
14		#include "../../utils.h"
15
16		#include "../../MCInst.h"
17		#include "../../MCInstrDesc.h"
18		#include "../../MCRegisterInfo.h"
19
20		#ifndef CAPSTONE_DIET
21		static const char s_spacing[] = " ";
22
23		static const char *const s_reg_names[] = {
24		"invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6",
25		"d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6",
26		"a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6",
27		"fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr",
28		"cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
29		"dtt1", "mmusr", "urp", "srp",
30
31		"fpcr", "fpsr", "fpiar",
32		};
33
34		static const char *const s_instruction_names[] = {
35		"invalid", "abcd", "add", "adda", "addi", "addq",
36		"addx", "and", "andi", "asl", "asr", "bhs",
37		"blo", "bhi", "bls", "bcc", "bcs", "bne",
38		"beq", "bvc", "bvs", "bpl", "bmi", "bge",
39		"blt", "bgt", "ble", "bra", "bsr", "bchg",
40		"bclr", "bset", "btst", "bfchg", "bfclr", "bfexts",
41		"bfextu", "bfffo", "bfins", "bfset", "bftst", "bkpt",
42		"callm", "cas", "cas2", "chk", "chk2", "clr",
43		"cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl",
44		"cinvp", "cinva", "cpushl", "cpushp", "cpusha", "dbt",
45		"dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne",
46		"dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge",
47		"dblt", "dbgt", "dble", "dbra", "divs", "divsl",
48		"divu", "divul", "eor", "eori", "exg", "ext",
49		"extb", "fabs", "fsabs", "fdabs", "facos", "fadd",
50		"fsadd", "fdadd", "fasin", "fatan", "fatanh", "fbf",
51		"fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl",
52		"fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult",
53		"fbule", "fbne", "fbt", "fbsf", "fbseq", "fbgt",
54		"fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle",
55		"fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne",
56		"fbst", "fcmp", "fcos", "fcosh", "fdbf", "fdbeq",
57		"fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor",
58		"fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule",
59		"fdbne", "fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge",
60		"fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl",
61		"fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst",
62		"fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp",
63		"fgetman", "fint", "fintrz", "flog10", "flog2", "flogn",
64		"flognp1", "fmod", "fmove", "fsmove", "fdmove", "fmovecr",
65		"fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg",
66		"fdneg", "fnop", "frem", "frestore", "fsave", "fscale",
67		"fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh", "fsqrt",
68		"fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge",
69		"fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
70		"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst",
71		"fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle",
72		"fsgl", "fsgle", "fsngle", "fsngl", "fsnle", "fsnlt",
73		"fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub",
74		"fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq",
75		"ftrapogt", "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor",
76		"ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule",
77		"ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge",
78		"ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl",
79		"ftrapnle", "ftrapnlt", "ftrapnge", "ftrapngt", "ftrapsne", "ftrapst",
80		"ftst", "ftwotox", "halt", "illegal", "jmp", "jsr",
81		"lea", "link", "lpstop", "lsl", "lsr", "move",
82		"movea", "movec", "movem", "movep", "moveq", "moves",
83		"move16", "muls", "mulu", "nbcd", "neg", "negx",
84		"nop", "not", "or", "ori", "pack", "pea",
85		"pflush", "pflusha", "pflushan", "pflushn", "ploadr", "ploadw",
86		"plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw",
87		"pulse", "rems", "remu", "reset", "rol", "ror",
88		"roxl", "roxr", "rtd", "rte", "rtm", "rtr",
89		"rts", "sbcd", "st", "sf", "shi", "sls",
90		"scc", "shs", "scs", "slo", "sne", "seq",
91		"svc", "svs", "spl", "smi", "sge", "slt",
92		"sgt", "sle", "stop", "sub", "suba", "subi",
93		"subq", "subx", "swap", "tas", "trap", "trapv",
94		"trapt", "trapf", "traphi", "trapls", "trapcc", "traphs",
95		"trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs",
96		"trappl", "trapmi", "trapge", "traplt", "trapgt", "traple",
97		"tst", "unlk", "unpk",
98		};
99		#endif
100
101		#ifndef CAPSTONE_DIET
102		static const char *getRegName(m68k_reg reg)
103	50.6k	{
104	50.6k	return s_reg_names[(int)reg];
105	50.6k	}
106
107		static void printRegbitsRange(char *buffer, size_t buf_len, uint32_t data,
108		const char *prefix)
109	26.5k	{
110	26.5k	unsigned int first = 0;
111	26.5k	unsigned int run_length = 0;
112	26.5k	int i;
113
114	216k	for (i = 0; i < 8; ++i) {
115	189k	if (data & (1 << i)) {
116	32.1k	first = i;
117	32.1k	run_length = 0;
118
119	54.5k	while (i < 7 && (data & (1 << (i + 1)))) {
120	22.4k	i++;
121	22.4k	run_length++;
122	22.4k	}
123
124	32.1k	if (buffer[0] != 0)
125	23.2k	strncat(buffer, "/", buf_len - 1);
126
127	32.1k	snprintf(buffer + strlen(buffer), buf_len, "%s%d",
128	32.1k	prefix, first);
129	32.1k	if (run_length > 0)
130	11.3k	snprintf(buffer + strlen(buffer), buf_len,
131	11.3k	"-%s%d", prefix, first + run_length);
132	32.1k	}
133	189k	}
134	26.5k	}
135
136		static void registerBits(SStream O, const cs_m68k_op op)
137	9.72k	{
138	9.72k	char buffer[128];
139	9.72k	unsigned int data = op->register_bits;
140
141	9.72k	buffer[0] = 0;
142
143	9.72k	if (!data) {
144	887	SStream_concat(O, "%s", "#$0");
145	887	return;
146	887	}
147
148	8.84k	printRegbitsRange(buffer, sizeof(buffer), data & 0xff, "d");
149	8.84k	printRegbitsRange(buffer, sizeof(buffer), (data >> 8) & 0xff, "a");
150	8.84k	printRegbitsRange(buffer, sizeof(buffer), (data >> 16) & 0xff, "fp");
151
152	8.84k	SStream_concat(O, "%s", buffer);
153	8.84k	}
154
155		static void registerPair(SStream O, const cs_m68k_op op)
156	5.48k	{
157	5.48k	SStream_concat(O, "%s:%s", s_reg_names[op->reg_pair.reg_0],
158	5.48k	s_reg_names[op->reg_pair.reg_1]);
159	5.48k	}
160
161		static void printAddressingMode(SStream *O, unsigned int pc,
162		const cs_m68k inst, const cs_m68k_op op)
163	690k	{
164	690k	switch (op->address_mode) {
165	81.5k	case M68K_AM_NONE:
166	81.5k	switch (op->type) {
167	9.72k	case M68K_OP_REG_BITS:
168	9.72k	registerBits(O, op);
169	9.72k	break;
170	5.48k	case M68K_OP_REG_PAIR:
171	5.48k	registerPair(O, op);
172	5.48k	break;
173	65.5k	case M68K_OP_REG:
174	65.5k	SStream_concat(O, "%s", s_reg_names[op->reg]);
175	65.5k	break;
176	789	default:
177	789	break;
178	81.5k	}
179	81.5k	break;
180
181	225k	case M68K_AM_REG_DIRECT_DATA:
182	225k	SStream_concat(O, "d%d", (op->reg - M68K_REG_D0));
183	225k	break;
184	34.9k	case M68K_AM_REG_DIRECT_ADDR:
185	34.9k	SStream_concat(O, "a%d", (op->reg - M68K_REG_A0));
186	34.9k	break;
187	39.5k	case M68K_AM_REGI_ADDR:
188	39.5k	SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0));
189	39.5k	break;
190	35.9k	case M68K_AM_REGI_ADDR_POST_INC:
191	35.9k	SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0));
192	35.9k	break;
193	70.3k	case M68K_AM_REGI_ADDR_PRE_DEC:
194	70.3k	SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0));
195	70.3k	break;
196	23.1k	case M68K_AM_REGI_ADDR_DISP:
197	23.1k	SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "",
198	23.1k	abs(op->mem.disp),
199	23.1k	(op->mem.base_reg - M68K_REG_A0));
200	23.1k	break;
201	4.77k	case M68K_AM_PCI_DISP:
202	4.77k	SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp);
203	4.77k	break;
204	3.96k	case M68K_AM_ABSOLUTE_DATA_SHORT:
205	3.96k	SStream_concat(O, "$%x.w", op->imm);
206	3.96k	break;
207	3.81k	case M68K_AM_ABSOLUTE_DATA_LONG:
208	3.81k	SStream_concat(O, "$%x.l", op->imm);
209	3.81k	break;
210	99.6k	case M68K_AM_IMMEDIATE:
211	99.6k	if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
212		#if defined(_KERNEL_MODE)
213		// Issue #681: Windows kernel does not support formatting float point
214		SStream_concat(O, "#<float_point_unsupported>");
215		break;
216		#else
217	817	if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
218	625	SStream_concat(O, "#%f", op->simm);
219	192	else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE)
220	192	SStream_concat(O, "#%f", op->dimm);
221	0	else
222	0	SStream_concat(O, "#<unsupported>");
223	817	break;
224	817	#endif
225	817	}
226	98.8k	SStream_concat(O, "#$%x", op->imm);
227	98.8k	break;
228	2.72k	case M68K_AM_PCI_INDEX_8_BIT_DISP:
229	2.72k	SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp,
230	2.72k	s_spacing, getRegName(op->mem.index_reg),
231	2.72k	op->mem.index_size ? 'l' : 'w');
232	2.72k	break;
233	14.4k	case M68K_AM_AREGI_INDEX_8_BIT_DISP:
234	14.4k	SStream_concat(O, "%s$%x(%s,%s%s.%c)",
235	14.4k	op->mem.disp < 0 ? "-" : "", abs(op->mem.disp),
236	14.4k	getRegName(op->mem.base_reg), s_spacing,
237	14.4k	getRegName(op->mem.index_reg),
238	14.4k	op->mem.index_size ? 'l' : 'w');
239	14.4k	break;
240	1.04k	case M68K_AM_PCI_INDEX_BASE_DISP:
241	6.33k	case M68K_AM_AREGI_INDEX_BASE_DISP:
242
243	6.33k	if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
244	1.04k	SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
245	5.29k	} else {
246	5.29k	if (op->mem.in_disp > 0)
247	1.51k	SStream_concat(O, "$%x", op->mem.in_disp);
248	5.29k	}
249
250	6.33k	SStream_concat0(O, "(");
251
252	6.33k	if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
253	1.04k	SStream_concat(O, "pc,%s.%c",
254	1.04k	getRegName(op->mem.index_reg),
255	1.04k	op->mem.index_size ? 'l' : 'w');
256	5.29k	} else {
257	5.29k	if (op->mem.base_reg != M68K_REG_INVALID)
258	4.31k	SStream_concat(O, "a%d,%s",
259	4.31k	op->mem.base_reg - M68K_REG_A0,
260	4.31k	s_spacing);
261	5.29k	SStream_concat(O, "%s.%c",
262	5.29k	getRegName(op->mem.index_reg),
263	5.29k	op->mem.index_size ? 'l' : 'w');
264	5.29k	}
265
266	6.33k	if (op->mem.scale > 0)
267	3.29k	SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing,
268	3.29k	op->mem.scale);
269	3.03k	else
270	3.03k	SStream_concat0(O, ")");
271	6.33k	break;
272		// It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code
273		// easier and that is what actually happens when the code is executed anyway.
274
275	594	case M68K_AM_PC_MEMI_POST_INDEX:
276	1.48k	case M68K_AM_PC_MEMI_PRE_INDEX:
277	5.57k	case M68K_AM_MEMI_PRE_INDEX:
278	9.60k	case M68K_AM_MEMI_POST_INDEX:
279	9.60k	SStream_concat0(O, "([");
280
281	9.60k	if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX \|\|
282	9.00k	op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) {
283	1.48k	SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
284	8.11k	} else {
285	8.11k	if (op->mem.in_disp > 0)
286	4.05k	SStream_concat(O, "$%x", op->mem.in_disp);
287	8.11k	}
288
289	9.60k	if (op->mem.base_reg != M68K_REG_INVALID) {
290	5.99k	if (op->mem.in_disp > 0)
291	2.71k	SStream_concat(O, ",%s%s", s_spacing,
292	2.71k	getRegName(op->mem.base_reg));
293	3.27k	else
294	3.27k	SStream_concat(O, "%s",
295	3.27k	getRegName(op->mem.base_reg));
296	5.99k	}
297
298	9.60k	if (op->address_mode == M68K_AM_MEMI_POST_INDEX \|\|
299	5.57k	op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
300	4.61k	SStream_concat0(O, "]");
301
302	9.60k	if (op->mem.index_reg != M68K_REG_INVALID)
303	6.78k	SStream_concat(O, ",%s%s.%c", s_spacing,
304	6.78k	getRegName(op->mem.index_reg),
305	6.78k	op->mem.index_size ? 'l' : 'w');
306
307	9.60k	if (op->mem.scale > 0)
308	5.09k	SStream_concat(O, "%s*%s%d", s_spacing, s_spacing,
309	5.09k	op->mem.scale);
310
311	9.60k	if (op->address_mode == M68K_AM_MEMI_PRE_INDEX \|\|
312	5.51k	op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX)
313	4.98k	SStream_concat0(O, "]");
314
315	9.60k	if (op->mem.out_disp > 0)
316	3.95k	SStream_concat(O, ",%s$%x", s_spacing,
317	3.95k	op->mem.out_disp);
318
319	9.60k	SStream_concat0(O, ")");
320	9.60k	break;
321	34.0k	case M68K_AM_BRANCH_DISPLACEMENT:
322	34.0k	SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp);
323	34.0k	default:
324	34.0k	break;
325	690k	}
326
327	690k	if (op->mem.bitfield)
328	3.22k	SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width);
329	690k	}
330		#endif
331
332		#define m68k_sizeof_array(array) (int)(sizeof(array) / sizeof(array[0]))
333	1.33M	#define m68k_min(a, b) (a < b) ? a : b
334
335		void M68K_printInst(MCInst MI, SStream O, void *PrinterInfo)
336	445k	{
337	445k	#ifndef CAPSTONE_DIET
338	445k	m68k_info info = (m68k_info )PrinterInfo;
339	445k	cs_m68k *ext = &info->extension;
340	445k	cs_detail *detail = NULL;
341	445k	int i = 0;
342
343	445k	detail = MI->flat_insn->detail;
344	445k	if (detail) {
345	445k	int regs_read_count =
346	445k	m68k_min(m68k_sizeof_array(detail->regs_read),
347	445k	info->regs_read_count);
348	445k	int regs_write_count =
349	445k	m68k_min(m68k_sizeof_array(detail->regs_write),
350	445k	info->regs_write_count);
351	445k	int groups_count = m68k_min(m68k_sizeof_array(detail->groups),
352	445k	info->groups_count);
353
354	445k	memcpy(&detail->m68k, ext, sizeof(cs_m68k));
355
356	445k	memcpy(&detail->regs_read, &info->regs_read,
357	445k	regs_read_count * sizeof(info->regs_read[0]));
358	445k	detail->regs_read_count = regs_read_count;
359
360	445k	memcpy(&detail->regs_write, &info->regs_write,
361	445k	regs_write_count * sizeof(info->regs_write[0]));
362	445k	detail->regs_write_count = regs_write_count;
363
364	445k	memcpy(&detail->groups, &info->groups, groups_count);
365	445k	detail->groups_count = groups_count;
366	445k	}
367
368	445k	if (MI->Opcode == M68K_INS_INVALID) {
369	61.8k	if (ext->op_count)
370	61.8k	SStream_concat(O, "dc.w $%x", ext->operands[0].imm);
371	0	else
372	0	SStream_concat(O, "dc.w $<unknown>");
373	61.8k	return;
374	61.8k	}
375
376	383k	SStream_concat0(O, (char *)s_instruction_names[MI->Opcode]);
377
378	383k	switch (ext->op_size.type) {
379	0	case M68K_SIZE_TYPE_INVALID:
380	0	break;
381
382	379k	case M68K_SIZE_TYPE_CPU:
383	379k	switch (ext->op_size.cpu_size) {
384	114k	case M68K_CPU_SIZE_BYTE:
385	114k	SStream_concat0(O, ".b");
386	114k	break;
387	106k	case M68K_CPU_SIZE_WORD:
388	106k	SStream_concat0(O, ".w");
389	106k	break;
390	98.7k	case M68K_CPU_SIZE_LONG:
391	98.7k	SStream_concat0(O, ".l");
392	98.7k	break;
393	59.7k	case M68K_CPU_SIZE_NONE:
394	59.7k	break;
395	379k	}
396	379k	break;
397
398	379k	case M68K_SIZE_TYPE_FPU:
399	4.77k	switch (ext->op_size.fpu_size) {
400	1.85k	case M68K_FPU_SIZE_SINGLE:
401	1.85k	SStream_concat0(O, ".s");
402	1.85k	break;
403	1.73k	case M68K_FPU_SIZE_DOUBLE:
404	1.73k	SStream_concat0(O, ".d");
405	1.73k	break;
406	1.18k	case M68K_FPU_SIZE_EXTENDED:
407	1.18k	SStream_concat0(O, ".x");
408	1.18k	break;
409	0	case M68K_FPU_SIZE_NONE:
410	0	break;
411	4.77k	}
412	4.77k	break;
413	383k	}
414
415	383k	SStream_concat0(O, " ");
416
417		// this one is a bit spacial so we do special things
418
419	383k	if (MI->Opcode == M68K_INS_CAS2) {
420	2.46k	int reg_value_0, reg_value_1;
421	2.46k	printAddressingMode(O, info->pc, ext, &ext->operands[0]);
422	2.46k	SStream_concat0(O, ",");
423	2.46k	printAddressingMode(O, info->pc, ext, &ext->operands[1]);
424	2.46k	SStream_concat0(O, ",");
425	2.46k	reg_value_0 = ext->operands[2].register_bits >> 4;
426	2.46k	reg_value_1 = ext->operands[2].register_bits & 0xf;
427	2.46k	SStream_concat(O, "(%s):(%s)",
428	2.46k	s_reg_names[M68K_REG_D0 + reg_value_0],
429	2.46k	s_reg_names[M68K_REG_D0 + reg_value_1]);
430	2.46k	return;
431	2.46k	}
432
433	1.06M	for (i = 0; i < ext->op_count; ++i) {
434	685k	printAddressingMode(O, info->pc, ext, &ext->operands[i]);
435	685k	if ((i + 1) != ext->op_count)
436	308k	SStream_concat(O, ",%s", s_spacing);
437	685k	}
438	381k	#endif
439	381k	}
440
441		const char *M68K_reg_name(csh handle, unsigned int reg)
442	582k	{
443		#ifdef CAPSTONE_DIET
444		return NULL;
445		#else
446	582k	if (reg >= ARR_SIZE(s_reg_names)) {
447	0	return NULL;
448	0	}
449	582k	return s_reg_names[(int)reg];
450	582k	#endif
451	582k	}
452
453		void M68K_get_insn_id(cs_struct h, cs_insn insn, unsigned int id)
454	445k	{
455	445k	insn->id = id; // These id's matches for 68k
456	445k	}
457
458		const char *M68K_insn_name(csh handle, unsigned int id)
459	445k	{
460		#ifdef CAPSTONE_DIET
461		return NULL;
462		#else
463	445k	return s_instruction_names[id];
464	445k	#endif
465	445k	}
466
467		#ifndef CAPSTONE_DIET
468		static const name_map group_name_maps[] = {
469		{ M68K_GRP_INVALID, NULL },
470		{ M68K_GRP_JUMP, "jump" },
471		{ M68K_GRP_RET, "ret" },
472		{ M68K_GRP_IRET, "iret" },
473		{ M68K_GRP_BRANCH_RELATIVE, "branch_relative" },
474		};
475		#endif
476
477		const char *M68K_group_name(csh handle, unsigned int id)
478	77.6k	{
479	77.6k	#ifndef CAPSTONE_DIET
480	77.6k	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
481		#else
482		return NULL;
483		#endif
484	77.6k	}
485
486		#ifndef CAPSTONE_DIET
487		void M68K_reg_access(const cs_insn *insn, cs_regs regs_read,
488		uint8_t *regs_read_count, cs_regs regs_write,
489		uint8_t *regs_write_count)
490	0	{
491	0	uint8_t read_count, write_count;
492
493	0	read_count = insn->detail->regs_read_count;
494	0	write_count = insn->detail->regs_write_count;
495
496		// implicit registers
497	0	memcpy(regs_read, insn->detail->regs_read,
498	0	read_count * sizeof(insn->detail->regs_read[0]));
499	0	memcpy(regs_write, insn->detail->regs_write,
500	0	write_count * sizeof(insn->detail->regs_write[0]));
501
502	0	*regs_read_count = read_count;
503	0	*regs_write_count = write_count;
504	0	}
505		#endif