/src/capstonenext/arch/PowerPC/PPCMCTargetDesc.h

Source


/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */

/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides PowerPC specific target descriptions.
//
//===----------------------------------------------------------------------===//

#ifndef CS_PPC_MCTARGETDESC_H
#define CS_PPC_MCTARGETDESC_H

// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC

#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "../../LEB128.h"
#include "../../MathExtras.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b

/// Returns true iff Val consists of one contiguous run of 1s with any number of
/// 0s on either side.  The 1s are allowed to wrap from LSB to MSB, so
/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.  0x0F0F0000 is not,
/// since all 1s are not contiguous.
static inline bool isRunOfOnes(unsigned Val, unsigned *MB, unsigned *ME)
{
  if (!Val)
    return false;

  if (isShiftedMask_32(Val)) {
    // look for the first non-zero bit
    *MB = countLeadingZeros(Val);
    // look for the first zero bit after the run of ones
    *ME = countLeadingZeros((Val - 1) ^ Val);
    return true;
  } else {
    Val = ~Val; // invert mask
    if (isShiftedMask_32(Val)) {
      // effectively look for the first zero bit
      *ME = countLeadingZeros(Val) - 1;
      // effectively look for the first one bit after the run of zeros
      *MB = countLeadingZeros((Val - 1) ^ Val) + 1;
      return true;
    }
  }
  // no run present
  return false;
}

static inline bool isRunOfOnes64(uint64_t Val, unsigned *MB, unsigned *ME)
{
  if (!Val)
    return false;

  if (isShiftedMask_64(Val)) {
    // look for the first non-zero bit
    *MB = countLeadingZeros(Val);
    // look for the first zero bit after the run of ones
    *ME = countLeadingZeros((Val - 1) ^ Val);
    return true;
  } else {
    Val = ~Val; // invert mask
    if (isShiftedMask_64(Val)) {
      // effectively look for the first zero bit
      *ME = countLeadingZeros(Val) - 1;
      // effectively look for the first one bit after the run of zeros
      *MB = countLeadingZeros((Val - 1) ^ Val) + 1;
      return true;
    }
  }
  // no run present
  return false;
}

// end namespace llvm

// Generated files will use "namespace PPC". To avoid symbol clash,
// undefine PPC here. PPC may be predefined on some hosts.
#undef PPC

// Defines symbolic names for PowerPC registers.  This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"

// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_SCHED_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
#define GET_INSTRINFO_MC_DESC
#include "PPCGenInstrInfo.inc"

#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"

#define PPC_REGS0_7(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
  }

#define PPC_REGS0_31(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
  }

#define PPC_REGS_EVEN0_30(X) \
  { \
    X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, \
      X##18, X##20, X##22, X##24, X##26, X##28, X##30 \
  }

#define PPC_REGS0_63(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
      X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
      X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
      X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
      X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
      X##59, X##60, X##61, X##62, X##63 \
  }

#define PPC_REGS_NO0_31(Z, X) \
  { \
    Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
  }

#define PPC_REGS_LO_HI(LO, HI) \
  { \
    LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
      LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
      LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
      LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
      LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
      HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
      HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
      HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
      HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
      HI##28, HI##29, HI##30, HI##31 \
  }

#define PPC_REGS0_7(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
  }

#define PPC_REGS0_3(X) \
  { \
    X##0, X##1, X##2, X##3 \
  }

#define DEFINE_PPC_REGCLASSES \
  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
  static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC_Fpair); \
  static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
  static const MCPhysReg RRegsNoR0[32] = \
    PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
  static const MCPhysReg XRegsNoX0[32] = \
    PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
  static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
  static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
  static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
  static const MCPhysReg CRBITRegs[32] = { \
    PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
    PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
    PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
    PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
    PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
    PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
    PPC_CR7EQ, PPC_CR7UN \
  }; \
  static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
  static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
  static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
  static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
  static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
  static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
  static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
  static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);

static const MCPhysReg QFRegs[] = {
  PPC_QF0,  PPC_QF1,  PPC_QF2,  PPC_QF3,  PPC_QF4,  PPC_QF5,  PPC_QF6,
  PPC_QF7,  PPC_QF8,  PPC_QF9,  PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
  PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20,
  PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
  PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
};

#endif // CS_PPC_MCTARGETDESC_H

Coverage Report

Created: 2025-10-28 07:02

Line	Count	Source
1
2
3		/* Capstone Disassembly Engine, http://www.capstone-engine.org */
4		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
5		/* Rot127 <unisono@quyllur.org> 2022-2023 */
6		/* Automatically translated source file from LLVM. */
7
8		/* LLVM-commit: <commit> */
9		/* LLVM-tag: <tag> */
10
11		/* Only small edits allowed. */
12		/* For multiple similar edits, please create a Patch for the translator. */
13
14		/* Capstone's C++ file translator: */
15		/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
16
17		//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------- C++ --===//
18		//
19		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
20		// See https://llvm.org/LICENSE.txt for license information.
21		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
22		//
23		//===----------------------------------------------------------------------===//
24		//
25		// This file provides PowerPC specific target descriptions.
26		//
27		//===----------------------------------------------------------------------===//
28
29		#ifndef CS_PPC_MCTARGETDESC_H
30		#define CS_PPC_MCTARGETDESC_H
31
32		// GCC #defines PPC on Linux but we use it as our namespace name
33		#undef PPC
34
35		#include <capstone/platform.h>
36		#include <stdio.h>
37		#include <stdlib.h>
38		#include <string.h>
39
40		#include "../../LEB128.h"
41		#include "../../MathExtras.h"
42		#include "../../MCInst.h"
43		#include "../../MCInstrDesc.h"
44		#include "../../MCRegisterInfo.h"
45		#define CONCAT(a, b) CONCAT_(a, b)
46		#define CONCAT_(a, b) a##_##b
47
48		/// Returns true iff Val consists of one contiguous run of 1s with any number of
49		/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
50		/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
51		/// since all 1s are not contiguous.
52		static inline bool isRunOfOnes(unsigned Val, unsigned MB, unsigned ME)
53	0	{
54	0	if (!Val)
55	0	return false;
56	0
57	0	if (isShiftedMask_32(Val)) {
58	0	// look for the first non-zero bit
59	0	*MB = countLeadingZeros(Val);
60	0	// look for the first zero bit after the run of ones
61	0	*ME = countLeadingZeros((Val - 1) ^ Val);
62	0	return true;
63	0	} else {
64	0	Val = ~Val; // invert mask
65	0	if (isShiftedMask_32(Val)) {
66	0	// effectively look for the first zero bit
67	0	*ME = countLeadingZeros(Val) - 1;
68	0	// effectively look for the first one bit after the run of zeros
69	0	*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
70	0	return true;
71	0	}
72	0	}
73	0	// no run present
74	0	return false;
75	0	} Unexecuted instantiation: PPCMapping.c:isRunOfOnes Unexecuted instantiation: PPCDisassembler.c:isRunOfOnes Unexecuted instantiation: PPCInstPrinter.c:isRunOfOnes
76
77		static inline bool isRunOfOnes64(uint64_t Val, unsigned MB, unsigned ME)
78	0	{
79	0	if (!Val)
80	0	return false;
81	0
82	0	if (isShiftedMask_64(Val)) {
83	0	// look for the first non-zero bit
84	0	*MB = countLeadingZeros(Val);
85	0	// look for the first zero bit after the run of ones
86	0	*ME = countLeadingZeros((Val - 1) ^ Val);
87	0	return true;
88	0	} else {
89	0	Val = ~Val; // invert mask
90	0	if (isShiftedMask_64(Val)) {
91	0	// effectively look for the first zero bit
92	0	*ME = countLeadingZeros(Val) - 1;
93	0	// effectively look for the first one bit after the run of zeros
94	0	*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
95	0	return true;
96	0	}
97	0	}
98	0	// no run present
99	0	return false;
100	0	} Unexecuted instantiation: PPCMapping.c:isRunOfOnes64 Unexecuted instantiation: PPCDisassembler.c:isRunOfOnes64 Unexecuted instantiation: PPCInstPrinter.c:isRunOfOnes64
101
102		// end namespace llvm
103
104		// Generated files will use "namespace PPC". To avoid symbol clash,
105		// undefine PPC here. PPC may be predefined on some hosts.
106		#undef PPC
107
108		// Defines symbolic names for PowerPC registers. This defines a mapping from
109		// register name to register number.
110		//
111		#define GET_REGINFO_ENUM
112		#include "PPCGenRegisterInfo.inc"
113
114		// Defines symbolic names for the PowerPC instructions.
115		//
116		#define GET_INSTRINFO_ENUM
117		#define GET_INSTRINFO_SCHED_ENUM
118		#define GET_INSTRINFO_MC_HELPER_DECLS
119		#define GET_INSTRINFO_MC_DESC
120		#include "PPCGenInstrInfo.inc"
121
122		#define GET_SUBTARGETINFO_ENUM
123		#include "PPCGenSubtargetInfo.inc"
124
125		#define PPC_REGS0_7(X) \
126		{ \
127		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
128		}
129
130		#define PPC_REGS0_31(X) \
131		{ \
132		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
133		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
134		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
135		X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
136		}
137
138		#define PPC_REGS_EVEN0_30(X) \
139		{ \
140		X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, \
141		X##18, X##20, X##22, X##24, X##26, X##28, X##30 \
142		}
143
144		#define PPC_REGS0_63(X) \
145		{ \
146		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
147		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
148		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
149		X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
150		X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
151		X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
152		X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
153		X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
154		X##59, X##60, X##61, X##62, X##63 \
155		}
156
157		#define PPC_REGS_NO0_31(Z, X) \
158		{ \
159		Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
160		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
161		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
162		X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
163		}
164
165		#define PPC_REGS_LO_HI(LO, HI) \
166		{ \
167		LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
168		LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
169		LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
170		LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
171		LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
172		HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
173		HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
174		HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
175		HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
176		HI##28, HI##29, HI##30, HI##31 \
177		}
178
179		#define PPC_REGS0_7(X) \
180		{ \
181		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
182		}
183
184		#define PPC_REGS0_3(X) \
185		{ \
186		X##0, X##1, X##2, X##3 \
187		}
188
189		#define DEFINE_PPC_REGCLASSES \
190		static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
191		static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
192		static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
193		static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC_Fpair); \
194		static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
195		static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
196		static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
197		static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
198		static const MCPhysReg RRegsNoR0[32] = \
199		PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
200		static const MCPhysReg XRegsNoX0[32] = \
201		PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
202		static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
203		static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
204		static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
205		static const MCPhysReg CRBITRegs[32] = { \
206		PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
207		PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
208		PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
209		PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
210		PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
211		PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
212		PPC_CR7EQ, PPC_CR7UN \
213		}; \
214		static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
215		static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
216		static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
217		static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
218		static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
219		static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
220		static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
221		static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);
222
223		static const MCPhysReg QFRegs[] = {
224		PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6,
225		PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
226		PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20,
227		PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
228		PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
229		};
230
231		#endif // CS_PPC_MCTARGETDESC_H